/*
* Copyright (c) 2016-2020 NVIDIA CORPORATION.  All rights reserved.
*
* NVIDIA CORPORATION and its licensors retain all intellectual property
* and proprietary rights in and to this software, related documentation
* and any modifications thereto.  Any use, reproduction, disclosure or
* distribution of this software and related documentation without an express
* license agreement from NVIDIA CORPORATION is strictly prohibited.
*/

#ifndef PROCESSOR__IRQS_HW_H
#define PROCESSOR__IRQS_HW_H
#define FSP__PROCESSOR__IRQS_HW_H                       1

/* Late FSP headers */
#include <misc/macros.h>                // for START_RFD_BLOCK, END_RFD_BLOCK, INLINE_RFD
START_RFD_BLOCK(MISRA, DEVIATE, Rule_2_5, "Approval: Bug 3175244, DR: SWE-FSP-013-SWSADR.docx",
                MISRA, DEVIATE, Directive_4_9, "Approval: Bug 200531995, DR: SWE-FSP-012-SWSADR.docx")

#define MAX_VIC_CONTROLLER       2

#define NV_AON_INTERRUPT_VIC0_BASE	0
#define NV_AON_INTERRUPT_VIC1_BASE	32

// VIC0 interrupts
#define NV_AON_INTERRUPT_WDTFIQ     MK_U32_CONST(0)
#define NV_AON_INTERRUPT_WDTIRQ     MK_U32_CONST(1)
#define NV_AON_INTERRUPT_TIMER0     MK_U32_CONST(2)
#define NV_AON_INTERRUPT_TIMER1     MK_U32_CONST(3)
#define NV_AON_INTERRUPT_TIMER2     MK_U32_CONST(4)
#define NV_AON_INTERRUPT_TIMER3     MK_U32_CONST(5)
#define NV_AON_INTERRUPT_MBOX       MK_U32_CONST(6)
#define NV_AON_INTERRUPT_GTE        MK_U32_CONST(7)
#define NV_AON_INTERRUPT_PMU        MK_U32_CONST(8)
#define NV_AON_INTERRUPT_DMA0       MK_U32_CONST(9)
#define NV_AON_INTERRUPT_DMA1       MK_U32_CONST(10)
#define NV_AON_INTERRUPT_DMA2       MK_U32_CONST(11)
#define NV_AON_INTERRUPT_DMA3       MK_U32_CONST(12)
#define NV_AON_INTERRUPT_DMA4       MK_U32_CONST(13)
#define NV_AON_INTERRUPT_DMA5       MK_U32_CONST(14)
#define NV_AON_INTERRUPT_DMA6       MK_U32_CONST(15)
#define NV_AON_INTERRUPT_DMA7       MK_U32_CONST(16)
#define NV_AON_INTERRUPT_I2C1       MK_U32_CONST(17)
#define NV_AON_INTERRUPT_I2C2       MK_U32_CONST(18)
#define NV_AON_INTERRUPT_I2C3       MK_U32_CONST(19)
#define NV_AON_INTERRUPT_SPI        MK_U32_CONST(20)
#define NV_AON_INTERRUPT_DMIC       MK_U32_CONST(21)
#define NV_AON_INTERRUPT_UART_1     MK_U32_CONST(22)
#define NV_AON_INTERRUPT_UART_2     MK_U32_CONST(23)
#define NV_AON_INTERRUPT_CAN1_0     MK_U32_CONST(24)
#define NV_AON_INTERRUPT_CAN1_1     MK_U32_CONST(25)
#define NV_AON_INTERRUPT_CAN2_0     MK_U32_CONST(26)
#define NV_AON_INTERRUPT_CAN2_1     MK_U32_CONST(27)
#define NV_AON_INTERRUPT_LIC0       MK_U32_CONST(28)
#define NV_AON_INTERRUPT_LIC1       MK_U32_CONST(29)
#define NV_AON_INTERRUPT_LIC2       MK_U32_CONST(30)
#define NV_AON_INTERRUPT_LIC3       MK_U32_CONST(31)

// VIC1 interrupts
#define NV_AON_INTERRUPT_NOC_ERR    MK_U32_CONST(0)
#define NV_AON_INTERRUPT_GPIO       MK_U32_CONST(1)
#define NV_AON_INTERRUPT_WAKE0      MK_U32_CONST(2)
#define NV_AON_INTERRUPT_PMC        MK_U32_CONST(3)
#define NV_AON_INTERRUPT_V1RSVD4    MK_U32_CONST(4)
#define NV_AON_INTERRUPT_PM         MK_U32_CONST(5)
#define NV_AON_INTERRUPT_FPUINT     MK_U32_CONST(6)
#define NV_AON_INTERRUPT_AOVC       MK_U32_CONST(7)
#define NV_AON_INTERRUPT_ACTMON     MK_U32_CONST(8)
#define NV_AON_INTERRUPT_AOWDT      MK_U32_CONST(9)
#define NV_AON_INTERRUPT_TOP0_HSP_DB MK_U32_CONST(10)
#define NV_AON_INTERRUPT_CTIIRQ     MK_U32_CONST(11)
#define NV_AON_INTERRUPT_NOC_SEC    MK_U32_CONST(12)
#define NV_AON_INTERRUPT_CAR        MK_U32_CONST(13)
#define NV_AON_INTERRUPT_UART6      MK_U32_CONST(14)
#define NV_AON_INTERRUPT_UART8      MK_U32_CONST(15)
#define NV_AON_INTERRUPT_GPIO_3     MK_U32_CONST(16)
#define NV_AON_INTERRUPT_V1RSVD17   MK_U32_CONST(17)
#define NV_AON_INTERRUPT_V1RSVD18   MK_U32_CONST(18)
#define NV_AON_INTERRUPT_V1RSVD19   MK_U32_CONST(19)
#define NV_AON_INTERRUPT_V1RSVD20   MK_U32_CONST(20)
#define NV_AON_INTERRUPT_V1RSVD21   MK_U32_CONST(21)
#define NV_AON_INTERRUPT_V1RSVD22   MK_U32_CONST(22)
#define NV_AON_INTERRUPT_V1RSVD23   MK_U32_CONST(23)
#define NV_AON_INTERRUPT_V1RSVD24   MK_U32_CONST(24)
#define NV_AON_INTERRUPT_V1RSVD25   MK_U32_CONST(25)
#define NV_AON_INTERRUPT_V1RSVD26   MK_U32_CONST(26)
#define NV_AON_INTERRUPT_V1RSVD27   MK_U32_CONST(27)
#define NV_AON_INTERRUPT_V1RSVD28   MK_U32_CONST(28)
#define NV_AON_INTERRUPT_V1RSVD29   MK_U32_CONST(29)
#define NV_AON_INTERRUPT_V1RSVD30   MK_U32_CONST(30)
#define NV_AON_INTERRUPT_V1RSVD31   MK_U32_CONST(31)
END_RFD_BLOCK(MISRA, DEVIATE, Rule_2_5, "Approval: Bug 3175244, DR: SWE-FSP-013-SWSADR.docx",
              MISRA, DEVIATE, Directive_4_9, "Approval: Bug 200531995, DR: SWE-FSP-012-SWSADR.docx")

#endif /* PROCESSOR__IRQS_HW_H */
