/*
 * Copyright (c) 2021-2022 NVIDIA CORPORATION. All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 *  * Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
 *  * Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in the
 *    documentation and/or other materials provided with the distribution.
 *  * Neither the name of NVIDIA CORPORATION nor the names of its
 *    contributors may be used to endorse or promote products derived
 *    from this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
 * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
 * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
 * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 */

//
// DO NOT EDIT - generated by simspec!
//

#ifndef ARPMC_IMPL_PUBLIC_H_INC
#define ARPMC_IMPL_PUBLIC_H_INC
#define NV_MOBILE_ARPMC_IMPL_PUBLIC_H_UNIT_OF_OFFSET 1B

#define NV_MOBILE_ARPMC_IMPL_PUBLIC_H_SCRREG_NOMENCLATURE INFERRED

//PMC Control Register
//There could be adverse effect if SW program the fields marked as DEFUNCT.

// Register PMC_IMPL_CNTRL_0
#define PMC_IMPL_CNTRL_0                        MK_ADDR_CONST(0x0)
#define PMC_IMPL_CNTRL_0_SECURE                         0x0
#define PMC_IMPL_CNTRL_0_DUAL                   0x0
#define PMC_IMPL_CNTRL_0_SCR                    CNTRL_SCR_0
#define PMC_IMPL_CNTRL_0_SCRREG                         PMC_IMPL_SCR_CNTRL_SCR_0
#define PMC_IMPL_CNTRL_0_WORD_COUNT                     0x1
#define PMC_IMPL_CNTRL_0_RESET_VAL                      MK_MASK_CONST(0x400a00)
#define PMC_IMPL_CNTRL_0_RESET_MASK                     MK_MASK_CONST(0x447f9f)
#define PMC_IMPL_CNTRL_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define PMC_IMPL_CNTRL_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define PMC_IMPL_CNTRL_0_READ_MASK                      MK_MASK_CONST(0x447f9f)
#define PMC_IMPL_CNTRL_0_WRITE_MASK                     MK_MASK_CONST(0x447f9f)
//DEFUNCT - This bit is reserved for KBC
#define PMC_IMPL_CNTRL_0_RESERVED_1_SHIFT                       MK_SHIFT_CONST(0)
#define PMC_IMPL_CNTRL_0_RESERVED_1_FIELD                       MK_FIELD_CONST(0x1, PMC_IMPL_CNTRL_0_RESERVED_1_SHIFT)
#define PMC_IMPL_CNTRL_0_RESERVED_1_RANGE                       0:0
#define PMC_IMPL_CNTRL_0_RESERVED_1_MSB                 MK_SHIFT_CONST(0)
#define PMC_IMPL_CNTRL_0_RESERVED_1_LSB                 MK_SHIFT_CONST(0)
#define PMC_IMPL_CNTRL_0_RESERVED_1_WOFFSET                     0x0
#define PMC_IMPL_CNTRL_0_RESERVED_1_DEFAULT                     MK_MASK_CONST(0x0)
#define PMC_IMPL_CNTRL_0_RESERVED_1_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define PMC_IMPL_CNTRL_0_RESERVED_1_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define PMC_IMPL_CNTRL_0_RESERVED_1_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define PMC_IMPL_CNTRL_0_RESERVED_1_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define PMC_IMPL_CNTRL_0_RESERVED_1_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

//Disable  32KHz clock to RTC
#define PMC_IMPL_CNTRL_0_RTC_CLK_DIS_SHIFT                      MK_SHIFT_CONST(1)
#define PMC_IMPL_CNTRL_0_RTC_CLK_DIS_FIELD                      MK_FIELD_CONST(0x1, PMC_IMPL_CNTRL_0_RTC_CLK_DIS_SHIFT)
#define PMC_IMPL_CNTRL_0_RTC_CLK_DIS_RANGE                      1:1
#define PMC_IMPL_CNTRL_0_RTC_CLK_DIS_MSB                        MK_SHIFT_CONST(1)
#define PMC_IMPL_CNTRL_0_RTC_CLK_DIS_LSB                        MK_SHIFT_CONST(1)
#define PMC_IMPL_CNTRL_0_RTC_CLK_DIS_WOFFSET                    0x0
#define PMC_IMPL_CNTRL_0_RTC_CLK_DIS_DEFAULT                    MK_MASK_CONST(0x0)
#define PMC_IMPL_CNTRL_0_RTC_CLK_DIS_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define PMC_IMPL_CNTRL_0_RTC_CLK_DIS_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define PMC_IMPL_CNTRL_0_RTC_CLK_DIS_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define PMC_IMPL_CNTRL_0_RTC_CLK_DIS_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define PMC_IMPL_CNTRL_0_RTC_CLK_DIS_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define PMC_IMPL_CNTRL_0_RTC_CLK_DIS_DISABLE                    MK_ENUM_CONST(0)
#define PMC_IMPL_CNTRL_0_RTC_CLK_DIS_ENABLE                     MK_ENUM_CONST(1)

//DEFUNCT - Software reset to RTC -defunct for t30
#define PMC_IMPL_CNTRL_0_RTC_RST_SHIFT                  MK_SHIFT_CONST(2)
#define PMC_IMPL_CNTRL_0_RTC_RST_FIELD                  MK_FIELD_CONST(0x1, PMC_IMPL_CNTRL_0_RTC_RST_SHIFT)
#define PMC_IMPL_CNTRL_0_RTC_RST_RANGE                  2:2
#define PMC_IMPL_CNTRL_0_RTC_RST_MSB                    MK_SHIFT_CONST(2)
#define PMC_IMPL_CNTRL_0_RTC_RST_LSB                    MK_SHIFT_CONST(2)
#define PMC_IMPL_CNTRL_0_RTC_RST_WOFFSET                        0x0
#define PMC_IMPL_CNTRL_0_RTC_RST_DEFAULT                        MK_MASK_CONST(0x0)
#define PMC_IMPL_CNTRL_0_RTC_RST_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define PMC_IMPL_CNTRL_0_RTC_RST_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define PMC_IMPL_CNTRL_0_RTC_RST_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define PMC_IMPL_CNTRL_0_RTC_RST_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define PMC_IMPL_CNTRL_0_RTC_RST_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define PMC_IMPL_CNTRL_0_RTC_RST_DISABLE                        MK_ENUM_CONST(0)
#define PMC_IMPL_CNTRL_0_RTC_RST_ENABLE                 MK_ENUM_CONST(1)

//DEFUNCT - This bit is reserved for KBC
#define PMC_IMPL_CNTRL_0_RESERVED_2_SHIFT                       MK_SHIFT_CONST(3)
#define PMC_IMPL_CNTRL_0_RESERVED_2_FIELD                       MK_FIELD_CONST(0x1, PMC_IMPL_CNTRL_0_RESERVED_2_SHIFT)
#define PMC_IMPL_CNTRL_0_RESERVED_2_RANGE                       3:3
#define PMC_IMPL_CNTRL_0_RESERVED_2_MSB                 MK_SHIFT_CONST(3)
#define PMC_IMPL_CNTRL_0_RESERVED_2_LSB                 MK_SHIFT_CONST(3)
#define PMC_IMPL_CNTRL_0_RESERVED_2_WOFFSET                     0x0
#define PMC_IMPL_CNTRL_0_RESERVED_2_DEFAULT                     MK_MASK_CONST(0x0)
#define PMC_IMPL_CNTRL_0_RESERVED_2_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define PMC_IMPL_CNTRL_0_RESERVED_2_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define PMC_IMPL_CNTRL_0_RESERVED_2_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define PMC_IMPL_CNTRL_0_RESERVED_2_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define PMC_IMPL_CNTRL_0_RESERVED_2_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

//SW Main Reset triggers L1C cold reset. Self Clearing Bit
#define PMC_IMPL_CNTRL_0_MAIN_RST_SHIFT                 MK_SHIFT_CONST(4)
#define PMC_IMPL_CNTRL_0_MAIN_RST_FIELD                 MK_FIELD_CONST(0x1, PMC_IMPL_CNTRL_0_MAIN_RST_SHIFT)
#define PMC_IMPL_CNTRL_0_MAIN_RST_RANGE                 4:4
#define PMC_IMPL_CNTRL_0_MAIN_RST_MSB                   MK_SHIFT_CONST(4)
#define PMC_IMPL_CNTRL_0_MAIN_RST_LSB                   MK_SHIFT_CONST(4)
#define PMC_IMPL_CNTRL_0_MAIN_RST_WOFFSET                       0x0
#define PMC_IMPL_CNTRL_0_MAIN_RST_DEFAULT                       MK_MASK_CONST(0x0)
#define PMC_IMPL_CNTRL_0_MAIN_RST_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define PMC_IMPL_CNTRL_0_MAIN_RST_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define PMC_IMPL_CNTRL_0_MAIN_RST_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define PMC_IMPL_CNTRL_0_MAIN_RST_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define PMC_IMPL_CNTRL_0_MAIN_RST_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define PMC_IMPL_CNTRL_0_MAIN_RST_DISABLE                       MK_ENUM_CONST(0)
#define PMC_IMPL_CNTRL_0_MAIN_RST_ENABLE                        MK_ENUM_CONST(1)

// Enables blinking counter and blink output
#define PMC_IMPL_CNTRL_0_BLINK_EN_SHIFT                 MK_SHIFT_CONST(7)
#define PMC_IMPL_CNTRL_0_BLINK_EN_FIELD                 MK_FIELD_CONST(0x1, PMC_IMPL_CNTRL_0_BLINK_EN_SHIFT)
#define PMC_IMPL_CNTRL_0_BLINK_EN_RANGE                 7:7
#define PMC_IMPL_CNTRL_0_BLINK_EN_MSB                   MK_SHIFT_CONST(7)
#define PMC_IMPL_CNTRL_0_BLINK_EN_LSB                   MK_SHIFT_CONST(7)
#define PMC_IMPL_CNTRL_0_BLINK_EN_WOFFSET                       0x0
#define PMC_IMPL_CNTRL_0_BLINK_EN_DEFAULT                       MK_MASK_CONST(0x0)
#define PMC_IMPL_CNTRL_0_BLINK_EN_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define PMC_IMPL_CNTRL_0_BLINK_EN_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define PMC_IMPL_CNTRL_0_BLINK_EN_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define PMC_IMPL_CNTRL_0_BLINK_EN_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define PMC_IMPL_CNTRL_0_BLINK_EN_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define PMC_IMPL_CNTRL_0_BLINK_EN_DISABLE                       MK_ENUM_CONST(0)
#define PMC_IMPL_CNTRL_0_BLINK_EN_ENABLE                        MK_ENUM_CONST(1)

//Inverts power request polarity - SW SHOULD NEVER PROGRAM "INVERT" for this.
//Only NORMAL polarity is valid usecase (Bug 200067516/Comment 11)
#define PMC_IMPL_CNTRL_0_PWRREQ_POLARITY_SHIFT                  MK_SHIFT_CONST(8)
#define PMC_IMPL_CNTRL_0_PWRREQ_POLARITY_FIELD                  MK_FIELD_CONST(0x1, PMC_IMPL_CNTRL_0_PWRREQ_POLARITY_SHIFT)
#define PMC_IMPL_CNTRL_0_PWRREQ_POLARITY_RANGE                  8:8
#define PMC_IMPL_CNTRL_0_PWRREQ_POLARITY_MSB                    MK_SHIFT_CONST(8)
#define PMC_IMPL_CNTRL_0_PWRREQ_POLARITY_LSB                    MK_SHIFT_CONST(8)
#define PMC_IMPL_CNTRL_0_PWRREQ_POLARITY_WOFFSET                        0x0
#define PMC_IMPL_CNTRL_0_PWRREQ_POLARITY_DEFAULT                        MK_MASK_CONST(0x0)
#define PMC_IMPL_CNTRL_0_PWRREQ_POLARITY_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define PMC_IMPL_CNTRL_0_PWRREQ_POLARITY_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define PMC_IMPL_CNTRL_0_PWRREQ_POLARITY_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define PMC_IMPL_CNTRL_0_PWRREQ_POLARITY_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define PMC_IMPL_CNTRL_0_PWRREQ_POLARITY_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define PMC_IMPL_CNTRL_0_PWRREQ_POLARITY_NORMAL                 MK_ENUM_CONST(0)
#define PMC_IMPL_CNTRL_0_PWRREQ_POLARITY_INVERT                 MK_ENUM_CONST(1)

//Power request output enable. resets to enable the pad
#define PMC_IMPL_CNTRL_0_PWRREQ_OE_SHIFT                        MK_SHIFT_CONST(9)
#define PMC_IMPL_CNTRL_0_PWRREQ_OE_FIELD                        MK_FIELD_CONST(0x1, PMC_IMPL_CNTRL_0_PWRREQ_OE_SHIFT)
#define PMC_IMPL_CNTRL_0_PWRREQ_OE_RANGE                        9:9
#define PMC_IMPL_CNTRL_0_PWRREQ_OE_MSB                  MK_SHIFT_CONST(9)
#define PMC_IMPL_CNTRL_0_PWRREQ_OE_LSB                  MK_SHIFT_CONST(9)
#define PMC_IMPL_CNTRL_0_PWRREQ_OE_WOFFSET                      0x0
#define PMC_IMPL_CNTRL_0_PWRREQ_OE_DEFAULT                      MK_MASK_CONST(0x1)
#define PMC_IMPL_CNTRL_0_PWRREQ_OE_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define PMC_IMPL_CNTRL_0_PWRREQ_OE_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define PMC_IMPL_CNTRL_0_PWRREQ_OE_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define PMC_IMPL_CNTRL_0_PWRREQ_OE_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define PMC_IMPL_CNTRL_0_PWRREQ_OE_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define PMC_IMPL_CNTRL_0_PWRREQ_OE_DISABLE                      MK_ENUM_CONST(0)
#define PMC_IMPL_CNTRL_0_PWRREQ_OE_ENABLE                       MK_ENUM_CONST(1)

//DEFUNCT - Not used in RTL anymore. SYS_CLK_REQ output pad is not supported.
#define PMC_IMPL_CNTRL_0_SYSCLK_POLARITY_SHIFT                  MK_SHIFT_CONST(10)
#define PMC_IMPL_CNTRL_0_SYSCLK_POLARITY_FIELD                  MK_FIELD_CONST(0x1, PMC_IMPL_CNTRL_0_SYSCLK_POLARITY_SHIFT)
#define PMC_IMPL_CNTRL_0_SYSCLK_POLARITY_RANGE                  10:10
#define PMC_IMPL_CNTRL_0_SYSCLK_POLARITY_MSB                    MK_SHIFT_CONST(10)
#define PMC_IMPL_CNTRL_0_SYSCLK_POLARITY_LSB                    MK_SHIFT_CONST(10)
#define PMC_IMPL_CNTRL_0_SYSCLK_POLARITY_WOFFSET                        0x0
#define PMC_IMPL_CNTRL_0_SYSCLK_POLARITY_DEFAULT                        MK_MASK_CONST(0x0)
#define PMC_IMPL_CNTRL_0_SYSCLK_POLARITY_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define PMC_IMPL_CNTRL_0_SYSCLK_POLARITY_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define PMC_IMPL_CNTRL_0_SYSCLK_POLARITY_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define PMC_IMPL_CNTRL_0_SYSCLK_POLARITY_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define PMC_IMPL_CNTRL_0_SYSCLK_POLARITY_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define PMC_IMPL_CNTRL_0_SYSCLK_POLARITY_NORMAL                 MK_ENUM_CONST(0)
#define PMC_IMPL_CNTRL_0_SYSCLK_POLARITY_INVERT                 MK_ENUM_CONST(1)

//DEFUNCT - Enables output of system enable clock - works only if SYS_CLK field in DPD_PADS_ORIDE is set to 1.
//resets to tristate
#define PMC_IMPL_CNTRL_0_SYSCLK_OE_SHIFT                        MK_SHIFT_CONST(11)
#define PMC_IMPL_CNTRL_0_SYSCLK_OE_FIELD                        MK_FIELD_CONST(0x1, PMC_IMPL_CNTRL_0_SYSCLK_OE_SHIFT)
#define PMC_IMPL_CNTRL_0_SYSCLK_OE_RANGE                        11:11
#define PMC_IMPL_CNTRL_0_SYSCLK_OE_MSB                  MK_SHIFT_CONST(11)
#define PMC_IMPL_CNTRL_0_SYSCLK_OE_LSB                  MK_SHIFT_CONST(11)
#define PMC_IMPL_CNTRL_0_SYSCLK_OE_WOFFSET                      0x0
#define PMC_IMPL_CNTRL_0_SYSCLK_OE_DEFAULT                      MK_MASK_CONST(0x1)
#define PMC_IMPL_CNTRL_0_SYSCLK_OE_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define PMC_IMPL_CNTRL_0_SYSCLK_OE_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define PMC_IMPL_CNTRL_0_SYSCLK_OE_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define PMC_IMPL_CNTRL_0_SYSCLK_OE_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define PMC_IMPL_CNTRL_0_SYSCLK_OE_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define PMC_IMPL_CNTRL_0_SYSCLK_OE_DISABLE                      MK_ENUM_CONST(0)
#define PMC_IMPL_CNTRL_0_SYSCLK_OE_ENABLE                       MK_ENUM_CONST(1)

//DEFUNCT - Disable  power gating - global override, will override function of PWRGATE_TOGGLE register.
#define PMC_IMPL_CNTRL_0_PWRGATE_DIS_SHIFT                      MK_SHIFT_CONST(12)
#define PMC_IMPL_CNTRL_0_PWRGATE_DIS_FIELD                      MK_FIELD_CONST(0x1, PMC_IMPL_CNTRL_0_PWRGATE_DIS_SHIFT)
#define PMC_IMPL_CNTRL_0_PWRGATE_DIS_RANGE                      12:12
#define PMC_IMPL_CNTRL_0_PWRGATE_DIS_MSB                        MK_SHIFT_CONST(12)
#define PMC_IMPL_CNTRL_0_PWRGATE_DIS_LSB                        MK_SHIFT_CONST(12)
#define PMC_IMPL_CNTRL_0_PWRGATE_DIS_WOFFSET                    0x0
#define PMC_IMPL_CNTRL_0_PWRGATE_DIS_DEFAULT                    MK_MASK_CONST(0x0)
#define PMC_IMPL_CNTRL_0_PWRGATE_DIS_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define PMC_IMPL_CNTRL_0_PWRGATE_DIS_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define PMC_IMPL_CNTRL_0_PWRGATE_DIS_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define PMC_IMPL_CNTRL_0_PWRGATE_DIS_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define PMC_IMPL_CNTRL_0_PWRGATE_DIS_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define PMC_IMPL_CNTRL_0_PWRGATE_DIS_DISABLE                    MK_ENUM_CONST(0)
#define PMC_IMPL_CNTRL_0_PWRGATE_DIS_ENABLE                     MK_ENUM_CONST(1)

//AO intitlized  purely sftw diagnostic and interpretation
#define PMC_IMPL_CNTRL_0_AOINIT_SHIFT                   MK_SHIFT_CONST(13)
#define PMC_IMPL_CNTRL_0_AOINIT_FIELD                   MK_FIELD_CONST(0x1, PMC_IMPL_CNTRL_0_AOINIT_SHIFT)
#define PMC_IMPL_CNTRL_0_AOINIT_RANGE                   13:13
#define PMC_IMPL_CNTRL_0_AOINIT_MSB                     MK_SHIFT_CONST(13)
#define PMC_IMPL_CNTRL_0_AOINIT_LSB                     MK_SHIFT_CONST(13)
#define PMC_IMPL_CNTRL_0_AOINIT_WOFFSET                 0x0
#define PMC_IMPL_CNTRL_0_AOINIT_DEFAULT                 MK_MASK_CONST(0x0)
#define PMC_IMPL_CNTRL_0_AOINIT_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define PMC_IMPL_CNTRL_0_AOINIT_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define PMC_IMPL_CNTRL_0_AOINIT_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define PMC_IMPL_CNTRL_0_AOINIT_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define PMC_IMPL_CNTRL_0_AOINIT_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define PMC_IMPL_CNTRL_0_AOINIT_NOTDONE                 MK_ENUM_CONST(0)
#define PMC_IMPL_CNTRL_0_AOINIT_DONE                    MK_ENUM_CONST(1)

//DEFUNCT - SW Should Never program this field!!! (when set causes side effect of entering sc7 -
//INSTEAD just use DPD_ENABLE register)
#define PMC_IMPL_CNTRL_0_SIDE_EFFECT_LP0_SHIFT                  MK_SHIFT_CONST(14)
#define PMC_IMPL_CNTRL_0_SIDE_EFFECT_LP0_FIELD                  MK_FIELD_CONST(0x1, PMC_IMPL_CNTRL_0_SIDE_EFFECT_LP0_SHIFT)
#define PMC_IMPL_CNTRL_0_SIDE_EFFECT_LP0_RANGE                  14:14
#define PMC_IMPL_CNTRL_0_SIDE_EFFECT_LP0_MSB                    MK_SHIFT_CONST(14)
#define PMC_IMPL_CNTRL_0_SIDE_EFFECT_LP0_LSB                    MK_SHIFT_CONST(14)
#define PMC_IMPL_CNTRL_0_SIDE_EFFECT_LP0_WOFFSET                        0x0
#define PMC_IMPL_CNTRL_0_SIDE_EFFECT_LP0_DEFAULT                        MK_MASK_CONST(0x0)
#define PMC_IMPL_CNTRL_0_SIDE_EFFECT_LP0_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define PMC_IMPL_CNTRL_0_SIDE_EFFECT_LP0_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define PMC_IMPL_CNTRL_0_SIDE_EFFECT_LP0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define PMC_IMPL_CNTRL_0_SIDE_EFFECT_LP0_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define PMC_IMPL_CNTRL_0_SIDE_EFFECT_LP0_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define PMC_IMPL_CNTRL_0_SIDE_EFFECT_LP0_DISABLE                        MK_ENUM_CONST(0)
#define PMC_IMPL_CNTRL_0_SIDE_EFFECT_LP0_ENABLE                 MK_ENUM_CONST(1)

//DEFUNCT - Fuse override
#define PMC_IMPL_CNTRL_0_FUSE_OVERRIDE_SHIFT                    MK_SHIFT_CONST(18)
#define PMC_IMPL_CNTRL_0_FUSE_OVERRIDE_FIELD                    MK_FIELD_CONST(0x1, PMC_IMPL_CNTRL_0_FUSE_OVERRIDE_SHIFT)
#define PMC_IMPL_CNTRL_0_FUSE_OVERRIDE_RANGE                    18:18
#define PMC_IMPL_CNTRL_0_FUSE_OVERRIDE_MSB                      MK_SHIFT_CONST(18)
#define PMC_IMPL_CNTRL_0_FUSE_OVERRIDE_LSB                      MK_SHIFT_CONST(18)
#define PMC_IMPL_CNTRL_0_FUSE_OVERRIDE_WOFFSET                  0x0
#define PMC_IMPL_CNTRL_0_FUSE_OVERRIDE_DEFAULT                  MK_MASK_CONST(0x0)
#define PMC_IMPL_CNTRL_0_FUSE_OVERRIDE_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define PMC_IMPL_CNTRL_0_FUSE_OVERRIDE_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define PMC_IMPL_CNTRL_0_FUSE_OVERRIDE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define PMC_IMPL_CNTRL_0_FUSE_OVERRIDE_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define PMC_IMPL_CNTRL_0_FUSE_OVERRIDE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define PMC_IMPL_CNTRL_0_FUSE_OVERRIDE_DISABLE                  MK_ENUM_CONST(0)
#define PMC_IMPL_CNTRL_0_FUSE_OVERRIDE_ENABLE                   MK_ENUM_CONST(1)

//DEFUNCT - enable shutdown pad
#define PMC_IMPL_CNTRL_0_SHUTDOWN_OE_SHIFT                      MK_SHIFT_CONST(22)
#define PMC_IMPL_CNTRL_0_SHUTDOWN_OE_FIELD                      MK_FIELD_CONST(0x1, PMC_IMPL_CNTRL_0_SHUTDOWN_OE_SHIFT)
#define PMC_IMPL_CNTRL_0_SHUTDOWN_OE_RANGE                      22:22
#define PMC_IMPL_CNTRL_0_SHUTDOWN_OE_MSB                        MK_SHIFT_CONST(22)
#define PMC_IMPL_CNTRL_0_SHUTDOWN_OE_LSB                        MK_SHIFT_CONST(22)
#define PMC_IMPL_CNTRL_0_SHUTDOWN_OE_WOFFSET                    0x0
#define PMC_IMPL_CNTRL_0_SHUTDOWN_OE_DEFAULT                    MK_MASK_CONST(0x1)
#define PMC_IMPL_CNTRL_0_SHUTDOWN_OE_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define PMC_IMPL_CNTRL_0_SHUTDOWN_OE_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define PMC_IMPL_CNTRL_0_SHUTDOWN_OE_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define PMC_IMPL_CNTRL_0_SHUTDOWN_OE_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define PMC_IMPL_CNTRL_0_SHUTDOWN_OE_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define PMC_IMPL_CNTRL_0_SHUTDOWN_OE_DISABLE                    MK_ENUM_CONST(0)
#define PMC_IMPL_CNTRL_0_SHUTDOWN_OE_ENABLE                     MK_ENUM_CONST(1)

//PMC SLCG Control Register

// Register PMC_IMPL_SLCG_CTRL_0
#define PMC_IMPL_SLCG_CTRL_0                    MK_ADDR_CONST(0x4)
#define PMC_IMPL_SLCG_CTRL_0_SECURE                     0x0
#define PMC_IMPL_SLCG_CTRL_0_DUAL                       0x0
#define PMC_IMPL_SLCG_CTRL_0_SCR                        CNTRL_SCR_0
#define PMC_IMPL_SLCG_CTRL_0_SCRREG                     PMC_IMPL_SCR_CNTRL_SCR_0
#define PMC_IMPL_SLCG_CTRL_0_WORD_COUNT                         0x1
#define PMC_IMPL_SLCG_CTRL_0_RESET_VAL                  MK_MASK_CONST(0x70000)
#define PMC_IMPL_SLCG_CTRL_0_RESET_MASK                         MK_MASK_CONST(0xff0703)
#define PMC_IMPL_SLCG_CTRL_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define PMC_IMPL_SLCG_CTRL_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define PMC_IMPL_SLCG_CTRL_0_READ_MASK                  MK_MASK_CONST(0xff0703)
#define PMC_IMPL_SLCG_CTRL_0_WRITE_MASK                         MK_MASK_CONST(0xff0703)
//Enable/Disable SLCG for PMC_PCLK. global override for three PMC_PCLK feature parts.
#define PMC_IMPL_SLCG_CTRL_0_PCLK_SLCG_EN_SHIFT                 MK_SHIFT_CONST(0)
#define PMC_IMPL_SLCG_CTRL_0_PCLK_SLCG_EN_FIELD                 MK_FIELD_CONST(0x1, PMC_IMPL_SLCG_CTRL_0_PCLK_SLCG_EN_SHIFT)
#define PMC_IMPL_SLCG_CTRL_0_PCLK_SLCG_EN_RANGE                 0:0
#define PMC_IMPL_SLCG_CTRL_0_PCLK_SLCG_EN_MSB                   MK_SHIFT_CONST(0)
#define PMC_IMPL_SLCG_CTRL_0_PCLK_SLCG_EN_LSB                   MK_SHIFT_CONST(0)
#define PMC_IMPL_SLCG_CTRL_0_PCLK_SLCG_EN_WOFFSET                       0x0
#define PMC_IMPL_SLCG_CTRL_0_PCLK_SLCG_EN_DEFAULT                       MK_MASK_CONST(0x0)
#define PMC_IMPL_SLCG_CTRL_0_PCLK_SLCG_EN_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define PMC_IMPL_SLCG_CTRL_0_PCLK_SLCG_EN_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define PMC_IMPL_SLCG_CTRL_0_PCLK_SLCG_EN_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define PMC_IMPL_SLCG_CTRL_0_PCLK_SLCG_EN_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define PMC_IMPL_SLCG_CTRL_0_PCLK_SLCG_EN_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define PMC_IMPL_SLCG_CTRL_0_PCLK_SLCG_EN_INIT_ENUM                     DISABLE
#define PMC_IMPL_SLCG_CTRL_0_PCLK_SLCG_EN_DISABLE                       MK_ENUM_CONST(0)
#define PMC_IMPL_SLCG_CTRL_0_PCLK_SLCG_EN_ENABLE                        MK_ENUM_CONST(1)

//Enable/Disable SLCG for PMC_CLK (32K)
#define PMC_IMPL_SLCG_CTRL_0_CLK32_SLCG_EN_SHIFT                        MK_SHIFT_CONST(1)
#define PMC_IMPL_SLCG_CTRL_0_CLK32_SLCG_EN_FIELD                        MK_FIELD_CONST(0x1, PMC_IMPL_SLCG_CTRL_0_CLK32_SLCG_EN_SHIFT)
#define PMC_IMPL_SLCG_CTRL_0_CLK32_SLCG_EN_RANGE                        1:1
#define PMC_IMPL_SLCG_CTRL_0_CLK32_SLCG_EN_MSB                  MK_SHIFT_CONST(1)
#define PMC_IMPL_SLCG_CTRL_0_CLK32_SLCG_EN_LSB                  MK_SHIFT_CONST(1)
#define PMC_IMPL_SLCG_CTRL_0_CLK32_SLCG_EN_WOFFSET                      0x0
#define PMC_IMPL_SLCG_CTRL_0_CLK32_SLCG_EN_DEFAULT                      MK_MASK_CONST(0x0)
#define PMC_IMPL_SLCG_CTRL_0_CLK32_SLCG_EN_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define PMC_IMPL_SLCG_CTRL_0_CLK32_SLCG_EN_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define PMC_IMPL_SLCG_CTRL_0_CLK32_SLCG_EN_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define PMC_IMPL_SLCG_CTRL_0_CLK32_SLCG_EN_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define PMC_IMPL_SLCG_CTRL_0_CLK32_SLCG_EN_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define PMC_IMPL_SLCG_CTRL_0_CLK32_SLCG_EN_INIT_ENUM                    DISABLE
#define PMC_IMPL_SLCG_CTRL_0_CLK32_SLCG_EN_DISABLE                      MK_ENUM_CONST(0)
#define PMC_IMPL_SLCG_CTRL_0_CLK32_SLCG_EN_ENABLE                       MK_ENUM_CONST(1)

//Enable/Disable SLCG for PMC_PCLK register access feature
#define PMC_IMPL_SLCG_CTRL_0_PCLK_REG_SLCG_EN_SHIFT                     MK_SHIFT_CONST(8)
#define PMC_IMPL_SLCG_CTRL_0_PCLK_REG_SLCG_EN_FIELD                     MK_FIELD_CONST(0x1, PMC_IMPL_SLCG_CTRL_0_PCLK_REG_SLCG_EN_SHIFT)
#define PMC_IMPL_SLCG_CTRL_0_PCLK_REG_SLCG_EN_RANGE                     8:8
#define PMC_IMPL_SLCG_CTRL_0_PCLK_REG_SLCG_EN_MSB                       MK_SHIFT_CONST(8)
#define PMC_IMPL_SLCG_CTRL_0_PCLK_REG_SLCG_EN_LSB                       MK_SHIFT_CONST(8)
#define PMC_IMPL_SLCG_CTRL_0_PCLK_REG_SLCG_EN_WOFFSET                   0x0
#define PMC_IMPL_SLCG_CTRL_0_PCLK_REG_SLCG_EN_DEFAULT                   MK_MASK_CONST(0x0)
#define PMC_IMPL_SLCG_CTRL_0_PCLK_REG_SLCG_EN_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define PMC_IMPL_SLCG_CTRL_0_PCLK_REG_SLCG_EN_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define PMC_IMPL_SLCG_CTRL_0_PCLK_REG_SLCG_EN_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define PMC_IMPL_SLCG_CTRL_0_PCLK_REG_SLCG_EN_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define PMC_IMPL_SLCG_CTRL_0_PCLK_REG_SLCG_EN_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define PMC_IMPL_SLCG_CTRL_0_PCLK_REG_SLCG_EN_INIT_ENUM                 DISABLE
#define PMC_IMPL_SLCG_CTRL_0_PCLK_REG_SLCG_EN_DISABLE                   MK_ENUM_CONST(0)
#define PMC_IMPL_SLCG_CTRL_0_PCLK_REG_SLCG_EN_ENABLE                    MK_ENUM_CONST(1)

//Enable/Disable SLCG for PMC_PCLK PG feature
#define PMC_IMPL_SLCG_CTRL_0_PCLK_PG_SLCG_EN_SHIFT                      MK_SHIFT_CONST(9)
#define PMC_IMPL_SLCG_CTRL_0_PCLK_PG_SLCG_EN_FIELD                      MK_FIELD_CONST(0x1, PMC_IMPL_SLCG_CTRL_0_PCLK_PG_SLCG_EN_SHIFT)
#define PMC_IMPL_SLCG_CTRL_0_PCLK_PG_SLCG_EN_RANGE                      9:9
#define PMC_IMPL_SLCG_CTRL_0_PCLK_PG_SLCG_EN_MSB                        MK_SHIFT_CONST(9)
#define PMC_IMPL_SLCG_CTRL_0_PCLK_PG_SLCG_EN_LSB                        MK_SHIFT_CONST(9)
#define PMC_IMPL_SLCG_CTRL_0_PCLK_PG_SLCG_EN_WOFFSET                    0x0
#define PMC_IMPL_SLCG_CTRL_0_PCLK_PG_SLCG_EN_DEFAULT                    MK_MASK_CONST(0x0)
#define PMC_IMPL_SLCG_CTRL_0_PCLK_PG_SLCG_EN_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define PMC_IMPL_SLCG_CTRL_0_PCLK_PG_SLCG_EN_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define PMC_IMPL_SLCG_CTRL_0_PCLK_PG_SLCG_EN_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define PMC_IMPL_SLCG_CTRL_0_PCLK_PG_SLCG_EN_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define PMC_IMPL_SLCG_CTRL_0_PCLK_PG_SLCG_EN_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define PMC_IMPL_SLCG_CTRL_0_PCLK_PG_SLCG_EN_INIT_ENUM                  DISABLE
#define PMC_IMPL_SLCG_CTRL_0_PCLK_PG_SLCG_EN_DISABLE                    MK_ENUM_CONST(0)
#define PMC_IMPL_SLCG_CTRL_0_PCLK_PG_SLCG_EN_ENABLE                     MK_ENUM_CONST(1)

//Enable/Disable SLCG for PMC_PCLK IO DPD feature
#define PMC_IMPL_SLCG_CTRL_0_PCLK_DPD_SLCG_EN_SHIFT                     MK_SHIFT_CONST(10)
#define PMC_IMPL_SLCG_CTRL_0_PCLK_DPD_SLCG_EN_FIELD                     MK_FIELD_CONST(0x1, PMC_IMPL_SLCG_CTRL_0_PCLK_DPD_SLCG_EN_SHIFT)
#define PMC_IMPL_SLCG_CTRL_0_PCLK_DPD_SLCG_EN_RANGE                     10:10
#define PMC_IMPL_SLCG_CTRL_0_PCLK_DPD_SLCG_EN_MSB                       MK_SHIFT_CONST(10)
#define PMC_IMPL_SLCG_CTRL_0_PCLK_DPD_SLCG_EN_LSB                       MK_SHIFT_CONST(10)
#define PMC_IMPL_SLCG_CTRL_0_PCLK_DPD_SLCG_EN_WOFFSET                   0x0
#define PMC_IMPL_SLCG_CTRL_0_PCLK_DPD_SLCG_EN_DEFAULT                   MK_MASK_CONST(0x0)
#define PMC_IMPL_SLCG_CTRL_0_PCLK_DPD_SLCG_EN_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define PMC_IMPL_SLCG_CTRL_0_PCLK_DPD_SLCG_EN_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define PMC_IMPL_SLCG_CTRL_0_PCLK_DPD_SLCG_EN_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define PMC_IMPL_SLCG_CTRL_0_PCLK_DPD_SLCG_EN_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define PMC_IMPL_SLCG_CTRL_0_PCLK_DPD_SLCG_EN_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define PMC_IMPL_SLCG_CTRL_0_PCLK_DPD_SLCG_EN_INIT_ENUM                 DISABLE
#define PMC_IMPL_SLCG_CTRL_0_PCLK_DPD_SLCG_EN_DISABLE                   MK_ENUM_CONST(0)
#define PMC_IMPL_SLCG_CTRL_0_PCLK_DPD_SLCG_EN_ENABLE                    MK_ENUM_CONST(1)

//Keep PCLK_REG clock running for this period after psel is deasserted
#define PMC_IMPL_SLCG_CTRL_0_PCLK_REG_SLCG_TIMER_SHIFT                  MK_SHIFT_CONST(16)
#define PMC_IMPL_SLCG_CTRL_0_PCLK_REG_SLCG_TIMER_FIELD                  MK_FIELD_CONST(0xff, PMC_IMPL_SLCG_CTRL_0_PCLK_REG_SLCG_TIMER_SHIFT)
#define PMC_IMPL_SLCG_CTRL_0_PCLK_REG_SLCG_TIMER_RANGE                  23:16
#define PMC_IMPL_SLCG_CTRL_0_PCLK_REG_SLCG_TIMER_MSB                    MK_SHIFT_CONST(23)
#define PMC_IMPL_SLCG_CTRL_0_PCLK_REG_SLCG_TIMER_LSB                    MK_SHIFT_CONST(16)
#define PMC_IMPL_SLCG_CTRL_0_PCLK_REG_SLCG_TIMER_WOFFSET                        0x0
#define PMC_IMPL_SLCG_CTRL_0_PCLK_REG_SLCG_TIMER_DEFAULT                        MK_MASK_CONST(0x7)
#define PMC_IMPL_SLCG_CTRL_0_PCLK_REG_SLCG_TIMER_DEFAULT_MASK                   MK_MASK_CONST(0xff)
#define PMC_IMPL_SLCG_CTRL_0_PCLK_REG_SLCG_TIMER_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define PMC_IMPL_SLCG_CTRL_0_PCLK_REG_SLCG_TIMER_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define PMC_IMPL_SLCG_CTRL_0_PCLK_REG_SLCG_TIMER_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define PMC_IMPL_SLCG_CTRL_0_PCLK_REG_SLCG_TIMER_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)


// Reserved address 0x8

// Reserved address 0xc

// Reserved address 0x10

// Reserved address 0x14

// Reserved address 0x18

// Reserved address 0x1c

// Reserved address 0x20

// Reserved address 0x24

// Reserved address 0x28

// Reserved address 0x2c

// Register PMC_IMPL_BLINK_TIMER_0
#define PMC_IMPL_BLINK_TIMER_0                  MK_ADDR_CONST(0x30)
#define PMC_IMPL_BLINK_TIMER_0_SECURE                   0x0
#define PMC_IMPL_BLINK_TIMER_0_DUAL                     0x0
#define PMC_IMPL_BLINK_TIMER_0_SCR                      BLINK_TIMER_SCR_0
#define PMC_IMPL_BLINK_TIMER_0_SCRREG                   PMC_IMPL_SCR_BLINK_TIMER_SCR_0
#define PMC_IMPL_BLINK_TIMER_0_WORD_COUNT                       0x1
#define PMC_IMPL_BLINK_TIMER_0_RESET_VAL                        MK_MASK_CONST(0xffff7fff)
#define PMC_IMPL_BLINK_TIMER_0_RESET_MASK                       MK_MASK_CONST(0xffffffff)
#define PMC_IMPL_BLINK_TIMER_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define PMC_IMPL_BLINK_TIMER_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define PMC_IMPL_BLINK_TIMER_0_READ_MASK                        MK_MASK_CONST(0xffffffff)
#define PMC_IMPL_BLINK_TIMER_0_WRITE_MASK                       MK_MASK_CONST(0xffffffff)
// time on
#define PMC_IMPL_BLINK_TIMER_0_DATA_ON_SHIFT                    MK_SHIFT_CONST(0)
#define PMC_IMPL_BLINK_TIMER_0_DATA_ON_FIELD                    MK_FIELD_CONST(0x7fff, PMC_IMPL_BLINK_TIMER_0_DATA_ON_SHIFT)
#define PMC_IMPL_BLINK_TIMER_0_DATA_ON_RANGE                    14:0
#define PMC_IMPL_BLINK_TIMER_0_DATA_ON_MSB                      MK_SHIFT_CONST(14)
#define PMC_IMPL_BLINK_TIMER_0_DATA_ON_LSB                      MK_SHIFT_CONST(0)
#define PMC_IMPL_BLINK_TIMER_0_DATA_ON_WOFFSET                  0x0
#define PMC_IMPL_BLINK_TIMER_0_DATA_ON_DEFAULT                  MK_MASK_CONST(0x7fff)
#define PMC_IMPL_BLINK_TIMER_0_DATA_ON_DEFAULT_MASK                     MK_MASK_CONST(0x7fff)
#define PMC_IMPL_BLINK_TIMER_0_DATA_ON_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define PMC_IMPL_BLINK_TIMER_0_DATA_ON_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define PMC_IMPL_BLINK_TIMER_0_DATA_ON_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define PMC_IMPL_BLINK_TIMER_0_DATA_ON_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

// Force the LED to blink at 32Khz
// 0 - Force disabled, regular blink based on DATA_ON and DATA_OFF
// 1 - Force enabled , Blink at 32Khz (16us on and 16us off)
#define PMC_IMPL_BLINK_TIMER_0_FORCE_BLINK_SHIFT                        MK_SHIFT_CONST(15)
#define PMC_IMPL_BLINK_TIMER_0_FORCE_BLINK_FIELD                        MK_FIELD_CONST(0x1, PMC_IMPL_BLINK_TIMER_0_FORCE_BLINK_SHIFT)
#define PMC_IMPL_BLINK_TIMER_0_FORCE_BLINK_RANGE                        15:15
#define PMC_IMPL_BLINK_TIMER_0_FORCE_BLINK_MSB                  MK_SHIFT_CONST(15)
#define PMC_IMPL_BLINK_TIMER_0_FORCE_BLINK_LSB                  MK_SHIFT_CONST(15)
#define PMC_IMPL_BLINK_TIMER_0_FORCE_BLINK_WOFFSET                      0x0
#define PMC_IMPL_BLINK_TIMER_0_FORCE_BLINK_DEFAULT                      MK_MASK_CONST(0x0)
#define PMC_IMPL_BLINK_TIMER_0_FORCE_BLINK_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define PMC_IMPL_BLINK_TIMER_0_FORCE_BLINK_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define PMC_IMPL_BLINK_TIMER_0_FORCE_BLINK_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define PMC_IMPL_BLINK_TIMER_0_FORCE_BLINK_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define PMC_IMPL_BLINK_TIMER_0_FORCE_BLINK_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

// time off
#define PMC_IMPL_BLINK_TIMER_0_DATA_OFF_SHIFT                   MK_SHIFT_CONST(16)
#define PMC_IMPL_BLINK_TIMER_0_DATA_OFF_FIELD                   MK_FIELD_CONST(0xffff, PMC_IMPL_BLINK_TIMER_0_DATA_OFF_SHIFT)
#define PMC_IMPL_BLINK_TIMER_0_DATA_OFF_RANGE                   31:16
#define PMC_IMPL_BLINK_TIMER_0_DATA_OFF_MSB                     MK_SHIFT_CONST(31)
#define PMC_IMPL_BLINK_TIMER_0_DATA_OFF_LSB                     MK_SHIFT_CONST(16)
#define PMC_IMPL_BLINK_TIMER_0_DATA_OFF_WOFFSET                 0x0
#define PMC_IMPL_BLINK_TIMER_0_DATA_OFF_DEFAULT                 MK_MASK_CONST(0xffff)
#define PMC_IMPL_BLINK_TIMER_0_DATA_OFF_DEFAULT_MASK                    MK_MASK_CONST(0xffff)
#define PMC_IMPL_BLINK_TIMER_0_DATA_OFF_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define PMC_IMPL_BLINK_TIMER_0_DATA_OFF_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define PMC_IMPL_BLINK_TIMER_0_DATA_OFF_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define PMC_IMPL_BLINK_TIMER_0_DATA_OFF_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Reserved address 0x34
// This register is used to program the "E_18V" pin of the ddr pads.
//reg     DDR_PWR incr4 scr_DDR_PWR_SCR  noprodck // DEFUNCT : This register is not used in RTL. A write will have no impact. Instead, use E_18V_PWR register

// Reserved address 0x38
// DDR_PWR
// This register is used to program the E_18V pin of the pads listed for each of the fields

// Register PMC_IMPL_E_18V_PWR_0
#define PMC_IMPL_E_18V_PWR_0                    MK_ADDR_CONST(0x3c)
#define PMC_IMPL_E_18V_PWR_0_SECURE                     0x0
#define PMC_IMPL_E_18V_PWR_0_DUAL                       0x0
#define PMC_IMPL_E_18V_PWR_0_SCR                        E_18V_PWR_SCR_0
#define PMC_IMPL_E_18V_PWR_0_SCRREG                     PMC_IMPL_SCR_E_18V_PWR_SCR_0
#define PMC_IMPL_E_18V_PWR_0_WORD_COUNT                         0x1
#define PMC_IMPL_E_18V_PWR_0_RESET_VAL                  MK_MASK_CONST(0x70)
#define PMC_IMPL_E_18V_PWR_0_RESET_MASK                         MK_MASK_CONST(0x72)
#define PMC_IMPL_E_18V_PWR_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define PMC_IMPL_E_18V_PWR_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define PMC_IMPL_E_18V_PWR_0_READ_MASK                  MK_MASK_CONST(0x72)
#define PMC_IMPL_E_18V_PWR_0_WRITE_MASK                         MK_MASK_CONST(0x72)
#define PMC_IMPL_E_18V_PWR_0_UFS_SHIFT                  MK_SHIFT_CONST(1)
#define PMC_IMPL_E_18V_PWR_0_UFS_FIELD                  MK_FIELD_CONST(0x1, PMC_IMPL_E_18V_PWR_0_UFS_SHIFT)
#define PMC_IMPL_E_18V_PWR_0_UFS_RANGE                  1:1
#define PMC_IMPL_E_18V_PWR_0_UFS_MSB                    MK_SHIFT_CONST(1)
#define PMC_IMPL_E_18V_PWR_0_UFS_LSB                    MK_SHIFT_CONST(1)
#define PMC_IMPL_E_18V_PWR_0_UFS_WOFFSET                        0x0
#define PMC_IMPL_E_18V_PWR_0_UFS_DEFAULT                        MK_MASK_CONST(0x0)
#define PMC_IMPL_E_18V_PWR_0_UFS_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define PMC_IMPL_E_18V_PWR_0_UFS_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define PMC_IMPL_E_18V_PWR_0_UFS_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define PMC_IMPL_E_18V_PWR_0_UFS_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define PMC_IMPL_E_18V_PWR_0_UFS_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define PMC_IMPL_E_18V_PWR_0_UFS_INIT_ENUM                      DISABLE
#define PMC_IMPL_E_18V_PWR_0_UFS_DISABLE                        MK_ENUM_CONST(0)
#define PMC_IMPL_E_18V_PWR_0_UFS_ENABLE                 MK_ENUM_CONST(1)

#define PMC_IMPL_E_18V_PWR_0_DBG_SHIFT                  MK_SHIFT_CONST(4)
#define PMC_IMPL_E_18V_PWR_0_DBG_FIELD                  MK_FIELD_CONST(0x1, PMC_IMPL_E_18V_PWR_0_DBG_SHIFT)
#define PMC_IMPL_E_18V_PWR_0_DBG_RANGE                  4:4
#define PMC_IMPL_E_18V_PWR_0_DBG_MSB                    MK_SHIFT_CONST(4)
#define PMC_IMPL_E_18V_PWR_0_DBG_LSB                    MK_SHIFT_CONST(4)
#define PMC_IMPL_E_18V_PWR_0_DBG_WOFFSET                        0x0
#define PMC_IMPL_E_18V_PWR_0_DBG_DEFAULT                        MK_MASK_CONST(0x1)
#define PMC_IMPL_E_18V_PWR_0_DBG_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define PMC_IMPL_E_18V_PWR_0_DBG_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define PMC_IMPL_E_18V_PWR_0_DBG_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define PMC_IMPL_E_18V_PWR_0_DBG_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define PMC_IMPL_E_18V_PWR_0_DBG_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define PMC_IMPL_E_18V_PWR_0_DBG_INIT_ENUM                      ENABLE
#define PMC_IMPL_E_18V_PWR_0_DBG_DISABLE                        MK_ENUM_CONST(0)
#define PMC_IMPL_E_18V_PWR_0_DBG_ENABLE                 MK_ENUM_CONST(1)

#define PMC_IMPL_E_18V_PWR_0_SPI_SHIFT                  MK_SHIFT_CONST(5)
#define PMC_IMPL_E_18V_PWR_0_SPI_FIELD                  MK_FIELD_CONST(0x1, PMC_IMPL_E_18V_PWR_0_SPI_SHIFT)
#define PMC_IMPL_E_18V_PWR_0_SPI_RANGE                  5:5
#define PMC_IMPL_E_18V_PWR_0_SPI_MSB                    MK_SHIFT_CONST(5)
#define PMC_IMPL_E_18V_PWR_0_SPI_LSB                    MK_SHIFT_CONST(5)
#define PMC_IMPL_E_18V_PWR_0_SPI_WOFFSET                        0x0
#define PMC_IMPL_E_18V_PWR_0_SPI_DEFAULT                        MK_MASK_CONST(0x1)
#define PMC_IMPL_E_18V_PWR_0_SPI_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define PMC_IMPL_E_18V_PWR_0_SPI_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define PMC_IMPL_E_18V_PWR_0_SPI_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define PMC_IMPL_E_18V_PWR_0_SPI_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define PMC_IMPL_E_18V_PWR_0_SPI_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define PMC_IMPL_E_18V_PWR_0_SPI_INIT_ENUM                      ENABLE
#define PMC_IMPL_E_18V_PWR_0_SPI_DISABLE                        MK_ENUM_CONST(0)
#define PMC_IMPL_E_18V_PWR_0_SPI_ENABLE                 MK_ENUM_CONST(1)

#define PMC_IMPL_E_18V_PWR_0_EQOS_SHIFT                 MK_SHIFT_CONST(6)
#define PMC_IMPL_E_18V_PWR_0_EQOS_FIELD                 MK_FIELD_CONST(0x1, PMC_IMPL_E_18V_PWR_0_EQOS_SHIFT)
#define PMC_IMPL_E_18V_PWR_0_EQOS_RANGE                 6:6
#define PMC_IMPL_E_18V_PWR_0_EQOS_MSB                   MK_SHIFT_CONST(6)
#define PMC_IMPL_E_18V_PWR_0_EQOS_LSB                   MK_SHIFT_CONST(6)
#define PMC_IMPL_E_18V_PWR_0_EQOS_WOFFSET                       0x0
#define PMC_IMPL_E_18V_PWR_0_EQOS_DEFAULT                       MK_MASK_CONST(0x1)
#define PMC_IMPL_E_18V_PWR_0_EQOS_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define PMC_IMPL_E_18V_PWR_0_EQOS_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define PMC_IMPL_E_18V_PWR_0_EQOS_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define PMC_IMPL_E_18V_PWR_0_EQOS_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define PMC_IMPL_E_18V_PWR_0_EQOS_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define PMC_IMPL_E_18V_PWR_0_EQOS_INIT_ENUM                     ENABLE
#define PMC_IMPL_E_18V_PWR_0_EQOS_DISABLE                       MK_ENUM_CONST(0)
#define PMC_IMPL_E_18V_PWR_0_EQOS_ENABLE                        MK_ENUM_CONST(1)

// This register is used to program the E_33V pin of the pads listed for each of the fields

// Register PMC_IMPL_E_33V_PWR_0
#define PMC_IMPL_E_33V_PWR_0                    MK_ADDR_CONST(0x40)
#define PMC_IMPL_E_33V_PWR_0_SECURE                     0x0
#define PMC_IMPL_E_33V_PWR_0_DUAL                       0x0
#define PMC_IMPL_E_33V_PWR_0_SCR                        E_33V_PWR_SCR_0
#define PMC_IMPL_E_33V_PWR_0_SCRREG                     PMC_IMPL_SCR_E_33V_PWR_SCR_0
#define PMC_IMPL_E_33V_PWR_0_WORD_COUNT                         0x1
#define PMC_IMPL_E_33V_PWR_0_RESET_VAL                  MK_MASK_CONST(0x53)
#define PMC_IMPL_E_33V_PWR_0_RESET_MASK                         MK_MASK_CONST(0x53)
#define PMC_IMPL_E_33V_PWR_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define PMC_IMPL_E_33V_PWR_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define PMC_IMPL_E_33V_PWR_0_READ_MASK                  MK_MASK_CONST(0x53)
#define PMC_IMPL_E_33V_PWR_0_WRITE_MASK                         MK_MASK_CONST(0x53)
#define PMC_IMPL_E_33V_PWR_0_AO_HV_SHIFT                        MK_SHIFT_CONST(0)
#define PMC_IMPL_E_33V_PWR_0_AO_HV_FIELD                        MK_FIELD_CONST(0x1, PMC_IMPL_E_33V_PWR_0_AO_HV_SHIFT)
#define PMC_IMPL_E_33V_PWR_0_AO_HV_RANGE                        0:0
#define PMC_IMPL_E_33V_PWR_0_AO_HV_MSB                  MK_SHIFT_CONST(0)
#define PMC_IMPL_E_33V_PWR_0_AO_HV_LSB                  MK_SHIFT_CONST(0)
#define PMC_IMPL_E_33V_PWR_0_AO_HV_WOFFSET                      0x0
#define PMC_IMPL_E_33V_PWR_0_AO_HV_DEFAULT                      MK_MASK_CONST(0x1)
#define PMC_IMPL_E_33V_PWR_0_AO_HV_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define PMC_IMPL_E_33V_PWR_0_AO_HV_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define PMC_IMPL_E_33V_PWR_0_AO_HV_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define PMC_IMPL_E_33V_PWR_0_AO_HV_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define PMC_IMPL_E_33V_PWR_0_AO_HV_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define PMC_IMPL_E_33V_PWR_0_AO_HV_INIT_ENUM                    ENABLE
#define PMC_IMPL_E_33V_PWR_0_AO_HV_DISABLE                      MK_ENUM_CONST(0)
#define PMC_IMPL_E_33V_PWR_0_AO_HV_ENABLE                       MK_ENUM_CONST(1)

#define PMC_IMPL_E_33V_PWR_0_AUDIO_HV_SHIFT                     MK_SHIFT_CONST(1)
#define PMC_IMPL_E_33V_PWR_0_AUDIO_HV_FIELD                     MK_FIELD_CONST(0x1, PMC_IMPL_E_33V_PWR_0_AUDIO_HV_SHIFT)
#define PMC_IMPL_E_33V_PWR_0_AUDIO_HV_RANGE                     1:1
#define PMC_IMPL_E_33V_PWR_0_AUDIO_HV_MSB                       MK_SHIFT_CONST(1)
#define PMC_IMPL_E_33V_PWR_0_AUDIO_HV_LSB                       MK_SHIFT_CONST(1)
#define PMC_IMPL_E_33V_PWR_0_AUDIO_HV_WOFFSET                   0x0
#define PMC_IMPL_E_33V_PWR_0_AUDIO_HV_DEFAULT                   MK_MASK_CONST(0x1)
#define PMC_IMPL_E_33V_PWR_0_AUDIO_HV_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define PMC_IMPL_E_33V_PWR_0_AUDIO_HV_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define PMC_IMPL_E_33V_PWR_0_AUDIO_HV_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define PMC_IMPL_E_33V_PWR_0_AUDIO_HV_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define PMC_IMPL_E_33V_PWR_0_AUDIO_HV_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define PMC_IMPL_E_33V_PWR_0_AUDIO_HV_INIT_ENUM                 ENABLE
#define PMC_IMPL_E_33V_PWR_0_AUDIO_HV_DISABLE                   MK_ENUM_CONST(0)
#define PMC_IMPL_E_33V_PWR_0_AUDIO_HV_ENABLE                    MK_ENUM_CONST(1)

#define PMC_IMPL_E_33V_PWR_0_SDMMC1_HV_SHIFT                    MK_SHIFT_CONST(4)
#define PMC_IMPL_E_33V_PWR_0_SDMMC1_HV_FIELD                    MK_FIELD_CONST(0x1, PMC_IMPL_E_33V_PWR_0_SDMMC1_HV_SHIFT)
#define PMC_IMPL_E_33V_PWR_0_SDMMC1_HV_RANGE                    4:4
#define PMC_IMPL_E_33V_PWR_0_SDMMC1_HV_MSB                      MK_SHIFT_CONST(4)
#define PMC_IMPL_E_33V_PWR_0_SDMMC1_HV_LSB                      MK_SHIFT_CONST(4)
#define PMC_IMPL_E_33V_PWR_0_SDMMC1_HV_WOFFSET                  0x0
#define PMC_IMPL_E_33V_PWR_0_SDMMC1_HV_DEFAULT                  MK_MASK_CONST(0x1)
#define PMC_IMPL_E_33V_PWR_0_SDMMC1_HV_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define PMC_IMPL_E_33V_PWR_0_SDMMC1_HV_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define PMC_IMPL_E_33V_PWR_0_SDMMC1_HV_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define PMC_IMPL_E_33V_PWR_0_SDMMC1_HV_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define PMC_IMPL_E_33V_PWR_0_SDMMC1_HV_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define PMC_IMPL_E_33V_PWR_0_SDMMC1_HV_INIT_ENUM                        ENABLE
#define PMC_IMPL_E_33V_PWR_0_SDMMC1_HV_DISABLE                  MK_ENUM_CONST(0)
#define PMC_IMPL_E_33V_PWR_0_SDMMC1_HV_ENABLE                   MK_ENUM_CONST(1)
#define PMC_IMPL_E_33V_PWR_0_SDMMC1_HV__PROD_C_3_3V                     MK_ENUM_CONST(1)
#define PMC_IMPL_E_33V_PWR_0_SDMMC1_HV__PROD_C_1_8V                     MK_ENUM_CONST(0)

#define PMC_IMPL_E_33V_PWR_0_SDMMC3_HV_SHIFT                    MK_SHIFT_CONST(6)
#define PMC_IMPL_E_33V_PWR_0_SDMMC3_HV_FIELD                    MK_FIELD_CONST(0x1, PMC_IMPL_E_33V_PWR_0_SDMMC3_HV_SHIFT)
#define PMC_IMPL_E_33V_PWR_0_SDMMC3_HV_RANGE                    6:6
#define PMC_IMPL_E_33V_PWR_0_SDMMC3_HV_MSB                      MK_SHIFT_CONST(6)
#define PMC_IMPL_E_33V_PWR_0_SDMMC3_HV_LSB                      MK_SHIFT_CONST(6)
#define PMC_IMPL_E_33V_PWR_0_SDMMC3_HV_WOFFSET                  0x0
#define PMC_IMPL_E_33V_PWR_0_SDMMC3_HV_DEFAULT                  MK_MASK_CONST(0x1)
#define PMC_IMPL_E_33V_PWR_0_SDMMC3_HV_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define PMC_IMPL_E_33V_PWR_0_SDMMC3_HV_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define PMC_IMPL_E_33V_PWR_0_SDMMC3_HV_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define PMC_IMPL_E_33V_PWR_0_SDMMC3_HV_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define PMC_IMPL_E_33V_PWR_0_SDMMC3_HV_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define PMC_IMPL_E_33V_PWR_0_SDMMC3_HV_INIT_ENUM                        ENABLE
#define PMC_IMPL_E_33V_PWR_0_SDMMC3_HV_DISABLE                  MK_ENUM_CONST(0)
#define PMC_IMPL_E_33V_PWR_0_SDMMC3_HV_ENABLE                   MK_ENUM_CONST(1)
#define PMC_IMPL_E_33V_PWR_0_SDMMC3_HV__PROD_C_3_3V                     MK_ENUM_CONST(1)
#define PMC_IMPL_E_33V_PWR_0_SDMMC3_HV__PROD_C_1_8V                     MK_ENUM_CONST(0)


// Reserved address 0x44
//DISP_SECURE_CTL - T194 - Moved to arpmc_misc bug #200181701

// Reserved address 0x48
//CRYPTO_OP       - T194 - Moved to arpmc_misc bug #200181701
//T194 - Removed PMC to CAR interface - Bug #200140661

// Reserved address 0x4c
// PLLP_WB0_OVERRIDE

// Reserved address 0x50
// PLLM_WB0_OVERRIDE_FREQ

// Reserved address 0x54
// PLLM_WB0_OVERRIDE2

// Reserved address 0x58
// PLLMSB_WB0_OVERRIDE_FREQ

// Reserved address 0x5c
// PLLMSB_WB0_OVERRIDE2
// This register can be programmed to keep oscilator ON during lp0 mode. It cuts the latency time on lp0 wake if oscilator pad does not
// have to be restarted
// When oscilator pad is on, during lp0 mode, dspare, duty, strenght , bypass are controlled by fields bellow
// Oscilator can be in one in forth modes during lp0 - in dpd, not dpd but not enabled, running, running only  when external request is active.

// Register PMC_IMPL_OSC_EDPD_OVER_0
#define PMC_IMPL_OSC_EDPD_OVER_0                        MK_ADDR_CONST(0x60)
#define PMC_IMPL_OSC_EDPD_OVER_0_SECURE                         0x0
#define PMC_IMPL_OSC_EDPD_OVER_0_DUAL                   0x0
#define PMC_IMPL_OSC_EDPD_OVER_0_SCR                    CNTRL_SCR_0
#define PMC_IMPL_OSC_EDPD_OVER_0_SCRREG                         PMC_IMPL_SCR_CNTRL_SCR_0
#define PMC_IMPL_OSC_EDPD_OVER_0_WORD_COUNT                     0x1
#define PMC_IMPL_OSC_EDPD_OVER_0_RESET_VAL                      MK_MASK_CONST(0x2)
#define PMC_IMPL_OSC_EDPD_OVER_0_RESET_MASK                     MK_MASK_CONST(0xffffff)
#define PMC_IMPL_OSC_EDPD_OVER_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define PMC_IMPL_OSC_EDPD_OVER_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define PMC_IMPL_OSC_EDPD_OVER_0_READ_MASK                      MK_MASK_CONST(0xffffff)
#define PMC_IMPL_OSC_EDPD_OVER_0_WRITE_MASK                     MK_MASK_CONST(0xffffff)
// Crystal oscillator clk_ok signal
#define PMC_IMPL_OSC_EDPD_OVER_0_CLK_OK_SHIFT                   MK_SHIFT_CONST(23)
#define PMC_IMPL_OSC_EDPD_OVER_0_CLK_OK_FIELD                   MK_FIELD_CONST(0x1, PMC_IMPL_OSC_EDPD_OVER_0_CLK_OK_SHIFT)
#define PMC_IMPL_OSC_EDPD_OVER_0_CLK_OK_RANGE                   23:23
#define PMC_IMPL_OSC_EDPD_OVER_0_CLK_OK_MSB                     MK_SHIFT_CONST(23)
#define PMC_IMPL_OSC_EDPD_OVER_0_CLK_OK_LSB                     MK_SHIFT_CONST(23)
#define PMC_IMPL_OSC_EDPD_OVER_0_CLK_OK_WOFFSET                 0x0
#define PMC_IMPL_OSC_EDPD_OVER_0_CLK_OK_DEFAULT                 MK_MASK_CONST(0x0)
#define PMC_IMPL_OSC_EDPD_OVER_0_CLK_OK_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define PMC_IMPL_OSC_EDPD_OVER_0_CLK_OK_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define PMC_IMPL_OSC_EDPD_OVER_0_CLK_OK_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define PMC_IMPL_OSC_EDPD_OVER_0_CLK_OK_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define PMC_IMPL_OSC_EDPD_OVER_0_CLK_OK_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define PMC_IMPL_OSC_EDPD_OVER_0_CLK_OK_DISABLE                 MK_ENUM_CONST(0)
#define PMC_IMPL_OSC_EDPD_OVER_0_CLK_OK_ENABLE                  MK_ENUM_CONST(1)

// select whether CAR's OSC_CTRL or PMC's OSC_CTRL_OVER affects the oscillator cell. This bit should always be "1" in LP0.
#define PMC_IMPL_OSC_EDPD_OVER_0_OSC_CTRL_SELECT_SHIFT                  MK_SHIFT_CONST(22)
#define PMC_IMPL_OSC_EDPD_OVER_0_OSC_CTRL_SELECT_FIELD                  MK_FIELD_CONST(0x1, PMC_IMPL_OSC_EDPD_OVER_0_OSC_CTRL_SELECT_SHIFT)
#define PMC_IMPL_OSC_EDPD_OVER_0_OSC_CTRL_SELECT_RANGE                  22:22
#define PMC_IMPL_OSC_EDPD_OVER_0_OSC_CTRL_SELECT_MSB                    MK_SHIFT_CONST(22)
#define PMC_IMPL_OSC_EDPD_OVER_0_OSC_CTRL_SELECT_LSB                    MK_SHIFT_CONST(22)
#define PMC_IMPL_OSC_EDPD_OVER_0_OSC_CTRL_SELECT_WOFFSET                        0x0
#define PMC_IMPL_OSC_EDPD_OVER_0_OSC_CTRL_SELECT_DEFAULT                        MK_MASK_CONST(0x0)
#define PMC_IMPL_OSC_EDPD_OVER_0_OSC_CTRL_SELECT_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define PMC_IMPL_OSC_EDPD_OVER_0_OSC_CTRL_SELECT_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define PMC_IMPL_OSC_EDPD_OVER_0_OSC_CTRL_SELECT_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define PMC_IMPL_OSC_EDPD_OVER_0_OSC_CTRL_SELECT_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define PMC_IMPL_OSC_EDPD_OVER_0_OSC_CTRL_SELECT_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define PMC_IMPL_OSC_EDPD_OVER_0_OSC_CTRL_SELECT_CAR                    MK_ENUM_CONST(0)
#define PMC_IMPL_OSC_EDPD_OVER_0_OSC_CTRL_SELECT_PMC                    MK_ENUM_CONST(1)

// control the behavior of the oscillator during LP0 (assuming OSC_CTRL_SELECT is set to PMC
// during LP0, put oscilator in dpd mode
// during LP0, bypass dpd, but do not enable oscilator
// during LP0, force the oscillator to run
// during LP0, run the oscillator when requested by an external clock request pin
// (EXT_REQ is DEFUNCT - THIS MODE IS NOT APPLICABLE/SUPPORTED in HW)
#define PMC_IMPL_OSC_EDPD_OVER_0_XO_LP0_MODE_SHIFT                      MK_SHIFT_CONST(20)
#define PMC_IMPL_OSC_EDPD_OVER_0_XO_LP0_MODE_FIELD                      MK_FIELD_CONST(0x3, PMC_IMPL_OSC_EDPD_OVER_0_XO_LP0_MODE_SHIFT)
#define PMC_IMPL_OSC_EDPD_OVER_0_XO_LP0_MODE_RANGE                      21:20
#define PMC_IMPL_OSC_EDPD_OVER_0_XO_LP0_MODE_MSB                        MK_SHIFT_CONST(21)
#define PMC_IMPL_OSC_EDPD_OVER_0_XO_LP0_MODE_LSB                        MK_SHIFT_CONST(20)
#define PMC_IMPL_OSC_EDPD_OVER_0_XO_LP0_MODE_WOFFSET                    0x0
#define PMC_IMPL_OSC_EDPD_OVER_0_XO_LP0_MODE_DEFAULT                    MK_MASK_CONST(0x0)
#define PMC_IMPL_OSC_EDPD_OVER_0_XO_LP0_MODE_DEFAULT_MASK                       MK_MASK_CONST(0x3)
#define PMC_IMPL_OSC_EDPD_OVER_0_XO_LP0_MODE_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define PMC_IMPL_OSC_EDPD_OVER_0_XO_LP0_MODE_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define PMC_IMPL_OSC_EDPD_OVER_0_XO_LP0_MODE_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define PMC_IMPL_OSC_EDPD_OVER_0_XO_LP0_MODE_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define PMC_IMPL_OSC_EDPD_OVER_0_XO_LP0_MODE_DPD                        MK_ENUM_CONST(0)
#define PMC_IMPL_OSC_EDPD_OVER_0_XO_LP0_MODE_OFF                        MK_ENUM_CONST(1)
#define PMC_IMPL_OSC_EDPD_OVER_0_XO_LP0_MODE_ON                 MK_ENUM_CONST(2)
#define PMC_IMPL_OSC_EDPD_OVER_0_XO_LP0_MODE_EXT_REQ                    MK_ENUM_CONST(3)

// Crystal oscillator spare register control.
#define PMC_IMPL_OSC_EDPD_OVER_0_OSCFI_SPARE_SHIFT                      MK_SHIFT_CONST(12)
#define PMC_IMPL_OSC_EDPD_OVER_0_OSCFI_SPARE_FIELD                      MK_FIELD_CONST(0xff, PMC_IMPL_OSC_EDPD_OVER_0_OSCFI_SPARE_SHIFT)
#define PMC_IMPL_OSC_EDPD_OVER_0_OSCFI_SPARE_RANGE                      19:12
#define PMC_IMPL_OSC_EDPD_OVER_0_OSCFI_SPARE_MSB                        MK_SHIFT_CONST(19)
#define PMC_IMPL_OSC_EDPD_OVER_0_OSCFI_SPARE_LSB                        MK_SHIFT_CONST(12)
#define PMC_IMPL_OSC_EDPD_OVER_0_OSCFI_SPARE_WOFFSET                    0x0
#define PMC_IMPL_OSC_EDPD_OVER_0_OSCFI_SPARE_DEFAULT                    MK_MASK_CONST(0x0)
#define PMC_IMPL_OSC_EDPD_OVER_0_OSCFI_SPARE_DEFAULT_MASK                       MK_MASK_CONST(0xff)
#define PMC_IMPL_OSC_EDPD_OVER_0_OSCFI_SPARE_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define PMC_IMPL_OSC_EDPD_OVER_0_OSCFI_SPARE_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define PMC_IMPL_OSC_EDPD_OVER_0_OSCFI_SPARE_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define PMC_IMPL_OSC_EDPD_OVER_0_OSCFI_SPARE_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

// Crystal oscillator duty cycle control.
#define PMC_IMPL_OSC_EDPD_OVER_0_XODS_SHIFT                     MK_SHIFT_CONST(7)
#define PMC_IMPL_OSC_EDPD_OVER_0_XODS_FIELD                     MK_FIELD_CONST(0x1f, PMC_IMPL_OSC_EDPD_OVER_0_XODS_SHIFT)
#define PMC_IMPL_OSC_EDPD_OVER_0_XODS_RANGE                     11:7
#define PMC_IMPL_OSC_EDPD_OVER_0_XODS_MSB                       MK_SHIFT_CONST(11)
#define PMC_IMPL_OSC_EDPD_OVER_0_XODS_LSB                       MK_SHIFT_CONST(7)
#define PMC_IMPL_OSC_EDPD_OVER_0_XODS_WOFFSET                   0x0
#define PMC_IMPL_OSC_EDPD_OVER_0_XODS_DEFAULT                   MK_MASK_CONST(0x0)
#define PMC_IMPL_OSC_EDPD_OVER_0_XODS_DEFAULT_MASK                      MK_MASK_CONST(0x1f)
#define PMC_IMPL_OSC_EDPD_OVER_0_XODS_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define PMC_IMPL_OSC_EDPD_OVER_0_XODS_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define PMC_IMPL_OSC_EDPD_OVER_0_XODS_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define PMC_IMPL_OSC_EDPD_OVER_0_XODS_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

// Crystal oscillator drive strength control. (Bug 1593591/28 - change of default to match CAR settings)
#define PMC_IMPL_OSC_EDPD_OVER_0_XOFS_SHIFT                     MK_SHIFT_CONST(1)
#define PMC_IMPL_OSC_EDPD_OVER_0_XOFS_FIELD                     MK_FIELD_CONST(0x3f, PMC_IMPL_OSC_EDPD_OVER_0_XOFS_SHIFT)
#define PMC_IMPL_OSC_EDPD_OVER_0_XOFS_RANGE                     6:1
#define PMC_IMPL_OSC_EDPD_OVER_0_XOFS_MSB                       MK_SHIFT_CONST(6)
#define PMC_IMPL_OSC_EDPD_OVER_0_XOFS_LSB                       MK_SHIFT_CONST(1)
#define PMC_IMPL_OSC_EDPD_OVER_0_XOFS_WOFFSET                   0x0
#define PMC_IMPL_OSC_EDPD_OVER_0_XOFS_DEFAULT                   MK_MASK_CONST(0x1)
#define PMC_IMPL_OSC_EDPD_OVER_0_XOFS_DEFAULT_MASK                      MK_MASK_CONST(0x3f)
#define PMC_IMPL_OSC_EDPD_OVER_0_XOFS_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define PMC_IMPL_OSC_EDPD_OVER_0_XOFS_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define PMC_IMPL_OSC_EDPD_OVER_0_XOFS_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define PMC_IMPL_OSC_EDPD_OVER_0_XOFS_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

// DEFUNCT : Crystal oscillator bypass enable (1 = enable bypass).
#define PMC_IMPL_OSC_EDPD_OVER_0_XOBP_SHIFT                     MK_SHIFT_CONST(0)
#define PMC_IMPL_OSC_EDPD_OVER_0_XOBP_FIELD                     MK_FIELD_CONST(0x1, PMC_IMPL_OSC_EDPD_OVER_0_XOBP_SHIFT)
#define PMC_IMPL_OSC_EDPD_OVER_0_XOBP_RANGE                     0:0
#define PMC_IMPL_OSC_EDPD_OVER_0_XOBP_MSB                       MK_SHIFT_CONST(0)
#define PMC_IMPL_OSC_EDPD_OVER_0_XOBP_LSB                       MK_SHIFT_CONST(0)
#define PMC_IMPL_OSC_EDPD_OVER_0_XOBP_WOFFSET                   0x0
#define PMC_IMPL_OSC_EDPD_OVER_0_XOBP_DEFAULT                   MK_MASK_CONST(0x0)
#define PMC_IMPL_OSC_EDPD_OVER_0_XOBP_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define PMC_IMPL_OSC_EDPD_OVER_0_XOBP_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define PMC_IMPL_OSC_EDPD_OVER_0_XOBP_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define PMC_IMPL_OSC_EDPD_OVER_0_XOBP_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define PMC_IMPL_OSC_EDPD_OVER_0_XOBP_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

//DEFUNCT - CLK_OUT_CNTRL - DEFUNCT

// Register PMC_IMPL_CLK_OUT_CNTRL_0
#define PMC_IMPL_CLK_OUT_CNTRL_0                        MK_ADDR_CONST(0x64)
#define PMC_IMPL_CLK_OUT_CNTRL_0_SECURE                         0x0
#define PMC_IMPL_CLK_OUT_CNTRL_0_DUAL                   0x0
#define PMC_IMPL_CLK_OUT_CNTRL_0_SCR                    CNTRL_SCR_0
#define PMC_IMPL_CLK_OUT_CNTRL_0_SCRREG                         PMC_IMPL_SCR_CNTRL_SCR_0
#define PMC_IMPL_CLK_OUT_CNTRL_0_WORD_COUNT                     0x1
#define PMC_IMPL_CLK_OUT_CNTRL_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define PMC_IMPL_CLK_OUT_CNTRL_0_RESET_MASK                     MK_MASK_CONST(0xffffff)
#define PMC_IMPL_CLK_OUT_CNTRL_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define PMC_IMPL_CLK_OUT_CNTRL_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define PMC_IMPL_CLK_OUT_CNTRL_0_READ_MASK                      MK_MASK_CONST(0xffffff)
#define PMC_IMPL_CLK_OUT_CNTRL_0_WRITE_MASK                     MK_MASK_CONST(0xffffff)
//Need to set this bit along with FORCE_EN when entering LP0
#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK1_ACCEPT_REQ_SHIFT                  MK_SHIFT_CONST(0)
#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK1_ACCEPT_REQ_FIELD                  MK_FIELD_CONST(0x1, PMC_IMPL_CLK_OUT_CNTRL_0_CLK1_ACCEPT_REQ_SHIFT)
#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK1_ACCEPT_REQ_RANGE                  0:0
#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK1_ACCEPT_REQ_MSB                    MK_SHIFT_CONST(0)
#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK1_ACCEPT_REQ_LSB                    MK_SHIFT_CONST(0)
#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK1_ACCEPT_REQ_WOFFSET                        0x0
#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK1_ACCEPT_REQ_DEFAULT                        MK_MASK_CONST(0x0)
#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK1_ACCEPT_REQ_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK1_ACCEPT_REQ_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK1_ACCEPT_REQ_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK1_ACCEPT_REQ_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK1_ACCEPT_REQ_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

//
#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK1_INVERT_REQ_SHIFT                  MK_SHIFT_CONST(1)
#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK1_INVERT_REQ_FIELD                  MK_FIELD_CONST(0x1, PMC_IMPL_CLK_OUT_CNTRL_0_CLK1_INVERT_REQ_SHIFT)
#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK1_INVERT_REQ_RANGE                  1:1
#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK1_INVERT_REQ_MSB                    MK_SHIFT_CONST(1)
#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK1_INVERT_REQ_LSB                    MK_SHIFT_CONST(1)
#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK1_INVERT_REQ_WOFFSET                        0x0
#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK1_INVERT_REQ_DEFAULT                        MK_MASK_CONST(0x0)
#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK1_INVERT_REQ_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK1_INVERT_REQ_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK1_INVERT_REQ_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK1_INVERT_REQ_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK1_INVERT_REQ_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

// force the clock to run regardless of ACCEPT_REQ or INVERT_REQ
#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK1_FORCE_EN_SHIFT                    MK_SHIFT_CONST(2)
#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK1_FORCE_EN_FIELD                    MK_FIELD_CONST(0x1, PMC_IMPL_CLK_OUT_CNTRL_0_CLK1_FORCE_EN_SHIFT)
#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK1_FORCE_EN_RANGE                    2:2
#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK1_FORCE_EN_MSB                      MK_SHIFT_CONST(2)
#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK1_FORCE_EN_LSB                      MK_SHIFT_CONST(2)
#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK1_FORCE_EN_WOFFSET                  0x0
#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK1_FORCE_EN_DEFAULT                  MK_MASK_CONST(0x0)
#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK1_FORCE_EN_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK1_FORCE_EN_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK1_FORCE_EN_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK1_FORCE_EN_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK1_FORCE_EN_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

//reserved
#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK1_RESERVED_SHIFT                    MK_SHIFT_CONST(3)
#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK1_RESERVED_FIELD                    MK_FIELD_CONST(0x1, PMC_IMPL_CLK_OUT_CNTRL_0_CLK1_RESERVED_SHIFT)
#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK1_RESERVED_RANGE                    3:3
#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK1_RESERVED_MSB                      MK_SHIFT_CONST(3)
#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK1_RESERVED_LSB                      MK_SHIFT_CONST(3)
#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK1_RESERVED_WOFFSET                  0x0
#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK1_RESERVED_DEFAULT                  MK_MASK_CONST(0x0)
#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK1_RESERVED_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK1_RESERVED_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK1_RESERVED_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK1_RESERVED_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK1_RESERVED_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

// state of the output line before clock request is active
#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK1_IDLE_STATE_SHIFT                  MK_SHIFT_CONST(4)
#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK1_IDLE_STATE_FIELD                  MK_FIELD_CONST(0x3, PMC_IMPL_CLK_OUT_CNTRL_0_CLK1_IDLE_STATE_SHIFT)
#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK1_IDLE_STATE_RANGE                  5:4
#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK1_IDLE_STATE_MSB                    MK_SHIFT_CONST(5)
#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK1_IDLE_STATE_LSB                    MK_SHIFT_CONST(4)
#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK1_IDLE_STATE_WOFFSET                        0x0
#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK1_IDLE_STATE_DEFAULT                        MK_MASK_CONST(0x0)
#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK1_IDLE_STATE_DEFAULT_MASK                   MK_MASK_CONST(0x3)
#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK1_IDLE_STATE_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK1_IDLE_STATE_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK1_IDLE_STATE_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK1_IDLE_STATE_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK1_IDLE_STATE_LOW                    MK_ENUM_CONST(0)
#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK1_IDLE_STATE_HIGH                   MK_ENUM_CONST(1)
#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK1_IDLE_STATE_TRIS                   MK_ENUM_CONST(2)

#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK1_SRC_SEL_SHIFT                     MK_SHIFT_CONST(6)
#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK1_SRC_SEL_FIELD                     MK_FIELD_CONST(0x3, PMC_IMPL_CLK_OUT_CNTRL_0_CLK1_SRC_SEL_SHIFT)
#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK1_SRC_SEL_RANGE                     7:6
#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK1_SRC_SEL_MSB                       MK_SHIFT_CONST(7)
#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK1_SRC_SEL_LSB                       MK_SHIFT_CONST(6)
#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK1_SRC_SEL_WOFFSET                   0x0
#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK1_SRC_SEL_DEFAULT                   MK_MASK_CONST(0x0)
#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK1_SRC_SEL_DEFAULT_MASK                      MK_MASK_CONST(0x3)
#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK1_SRC_SEL_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK1_SRC_SEL_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK1_SRC_SEL_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK1_SRC_SEL_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK1_SRC_SEL_OSC_DIV1                  MK_ENUM_CONST(0)
#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK1_SRC_SEL_OSC_DIV2                  MK_ENUM_CONST(1)
#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK1_SRC_SEL_OSC_DIV3                  MK_ENUM_CONST(2)
#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK1_SRC_SEL_CAR                       MK_ENUM_CONST(3)

//Need to set this bit along with FORCE_EN when entering LP0
#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK2_ACCEPT_REQ_SHIFT                  MK_SHIFT_CONST(8)
#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK2_ACCEPT_REQ_FIELD                  MK_FIELD_CONST(0x1, PMC_IMPL_CLK_OUT_CNTRL_0_CLK2_ACCEPT_REQ_SHIFT)
#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK2_ACCEPT_REQ_RANGE                  8:8
#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK2_ACCEPT_REQ_MSB                    MK_SHIFT_CONST(8)
#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK2_ACCEPT_REQ_LSB                    MK_SHIFT_CONST(8)
#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK2_ACCEPT_REQ_WOFFSET                        0x0
#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK2_ACCEPT_REQ_DEFAULT                        MK_MASK_CONST(0x0)
#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK2_ACCEPT_REQ_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK2_ACCEPT_REQ_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK2_ACCEPT_REQ_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK2_ACCEPT_REQ_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK2_ACCEPT_REQ_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

//
#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK2_INVERT_REQ_SHIFT                  MK_SHIFT_CONST(9)
#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK2_INVERT_REQ_FIELD                  MK_FIELD_CONST(0x1, PMC_IMPL_CLK_OUT_CNTRL_0_CLK2_INVERT_REQ_SHIFT)
#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK2_INVERT_REQ_RANGE                  9:9
#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK2_INVERT_REQ_MSB                    MK_SHIFT_CONST(9)
#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK2_INVERT_REQ_LSB                    MK_SHIFT_CONST(9)
#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK2_INVERT_REQ_WOFFSET                        0x0
#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK2_INVERT_REQ_DEFAULT                        MK_MASK_CONST(0x0)
#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK2_INVERT_REQ_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK2_INVERT_REQ_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK2_INVERT_REQ_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK2_INVERT_REQ_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK2_INVERT_REQ_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

// force the clock to run regardless of ACCEPT_REQ or INVERT_REQ
#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK2_FORCE_EN_SHIFT                    MK_SHIFT_CONST(10)
#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK2_FORCE_EN_FIELD                    MK_FIELD_CONST(0x1, PMC_IMPL_CLK_OUT_CNTRL_0_CLK2_FORCE_EN_SHIFT)
#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK2_FORCE_EN_RANGE                    10:10
#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK2_FORCE_EN_MSB                      MK_SHIFT_CONST(10)
#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK2_FORCE_EN_LSB                      MK_SHIFT_CONST(10)
#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK2_FORCE_EN_WOFFSET                  0x0
#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK2_FORCE_EN_DEFAULT                  MK_MASK_CONST(0x0)
#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK2_FORCE_EN_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK2_FORCE_EN_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK2_FORCE_EN_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK2_FORCE_EN_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK2_FORCE_EN_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

//reserved
#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK2_RESERVED_SHIFT                    MK_SHIFT_CONST(11)
#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK2_RESERVED_FIELD                    MK_FIELD_CONST(0x1, PMC_IMPL_CLK_OUT_CNTRL_0_CLK2_RESERVED_SHIFT)
#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK2_RESERVED_RANGE                    11:11
#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK2_RESERVED_MSB                      MK_SHIFT_CONST(11)
#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK2_RESERVED_LSB                      MK_SHIFT_CONST(11)
#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK2_RESERVED_WOFFSET                  0x0
#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK2_RESERVED_DEFAULT                  MK_MASK_CONST(0x0)
#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK2_RESERVED_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK2_RESERVED_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK2_RESERVED_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK2_RESERVED_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK2_RESERVED_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

//
#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK2_IDLE_STATE_SHIFT                  MK_SHIFT_CONST(12)
#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK2_IDLE_STATE_FIELD                  MK_FIELD_CONST(0x3, PMC_IMPL_CLK_OUT_CNTRL_0_CLK2_IDLE_STATE_SHIFT)
#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK2_IDLE_STATE_RANGE                  13:12
#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK2_IDLE_STATE_MSB                    MK_SHIFT_CONST(13)
#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK2_IDLE_STATE_LSB                    MK_SHIFT_CONST(12)
#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK2_IDLE_STATE_WOFFSET                        0x0
#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK2_IDLE_STATE_DEFAULT                        MK_MASK_CONST(0x0)
#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK2_IDLE_STATE_DEFAULT_MASK                   MK_MASK_CONST(0x3)
#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK2_IDLE_STATE_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK2_IDLE_STATE_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK2_IDLE_STATE_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK2_IDLE_STATE_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK2_IDLE_STATE_LOW                    MK_ENUM_CONST(0)
#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK2_IDLE_STATE_HIGH                   MK_ENUM_CONST(1)
#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK2_IDLE_STATE_TRIS                   MK_ENUM_CONST(2)

#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK2_SRC_SEL_SHIFT                     MK_SHIFT_CONST(14)
#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK2_SRC_SEL_FIELD                     MK_FIELD_CONST(0x3, PMC_IMPL_CLK_OUT_CNTRL_0_CLK2_SRC_SEL_SHIFT)
#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK2_SRC_SEL_RANGE                     15:14
#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK2_SRC_SEL_MSB                       MK_SHIFT_CONST(15)
#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK2_SRC_SEL_LSB                       MK_SHIFT_CONST(14)
#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK2_SRC_SEL_WOFFSET                   0x0
#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK2_SRC_SEL_DEFAULT                   MK_MASK_CONST(0x0)
#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK2_SRC_SEL_DEFAULT_MASK                      MK_MASK_CONST(0x3)
#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK2_SRC_SEL_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK2_SRC_SEL_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK2_SRC_SEL_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK2_SRC_SEL_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK2_SRC_SEL_OSC_DIV1                  MK_ENUM_CONST(0)
#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK2_SRC_SEL_OSC_DIV2                  MK_ENUM_CONST(1)
#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK2_SRC_SEL_OSC_DIV3                  MK_ENUM_CONST(2)
#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK2_SRC_SEL_CAR                       MK_ENUM_CONST(3)

// Need to set this bit along with FORCE_EN when entering LP0
#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK3_ACCEPT_REQ_SHIFT                  MK_SHIFT_CONST(16)
#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK3_ACCEPT_REQ_FIELD                  MK_FIELD_CONST(0x1, PMC_IMPL_CLK_OUT_CNTRL_0_CLK3_ACCEPT_REQ_SHIFT)
#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK3_ACCEPT_REQ_RANGE                  16:16
#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK3_ACCEPT_REQ_MSB                    MK_SHIFT_CONST(16)
#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK3_ACCEPT_REQ_LSB                    MK_SHIFT_CONST(16)
#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK3_ACCEPT_REQ_WOFFSET                        0x0
#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK3_ACCEPT_REQ_DEFAULT                        MK_MASK_CONST(0x0)
#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK3_ACCEPT_REQ_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK3_ACCEPT_REQ_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK3_ACCEPT_REQ_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK3_ACCEPT_REQ_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK3_ACCEPT_REQ_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

//
#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK3_INVERT_REQ_SHIFT                  MK_SHIFT_CONST(17)
#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK3_INVERT_REQ_FIELD                  MK_FIELD_CONST(0x1, PMC_IMPL_CLK_OUT_CNTRL_0_CLK3_INVERT_REQ_SHIFT)
#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK3_INVERT_REQ_RANGE                  17:17
#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK3_INVERT_REQ_MSB                    MK_SHIFT_CONST(17)
#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK3_INVERT_REQ_LSB                    MK_SHIFT_CONST(17)
#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK3_INVERT_REQ_WOFFSET                        0x0
#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK3_INVERT_REQ_DEFAULT                        MK_MASK_CONST(0x0)
#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK3_INVERT_REQ_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK3_INVERT_REQ_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK3_INVERT_REQ_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK3_INVERT_REQ_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK3_INVERT_REQ_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

// force the clock to run regardless of ACCEPT_REQ or INVERT_REQ
#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK3_FORCE_EN_SHIFT                    MK_SHIFT_CONST(18)
#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK3_FORCE_EN_FIELD                    MK_FIELD_CONST(0x1, PMC_IMPL_CLK_OUT_CNTRL_0_CLK3_FORCE_EN_SHIFT)
#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK3_FORCE_EN_RANGE                    18:18
#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK3_FORCE_EN_MSB                      MK_SHIFT_CONST(18)
#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK3_FORCE_EN_LSB                      MK_SHIFT_CONST(18)
#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK3_FORCE_EN_WOFFSET                  0x0
#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK3_FORCE_EN_DEFAULT                  MK_MASK_CONST(0x0)
#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK3_FORCE_EN_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK3_FORCE_EN_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK3_FORCE_EN_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK3_FORCE_EN_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK3_FORCE_EN_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

//reserved
#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK3_RESERVED_SHIFT                    MK_SHIFT_CONST(19)
#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK3_RESERVED_FIELD                    MK_FIELD_CONST(0x1, PMC_IMPL_CLK_OUT_CNTRL_0_CLK3_RESERVED_SHIFT)
#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK3_RESERVED_RANGE                    19:19
#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK3_RESERVED_MSB                      MK_SHIFT_CONST(19)
#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK3_RESERVED_LSB                      MK_SHIFT_CONST(19)
#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK3_RESERVED_WOFFSET                  0x0
#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK3_RESERVED_DEFAULT                  MK_MASK_CONST(0x0)
#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK3_RESERVED_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK3_RESERVED_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK3_RESERVED_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK3_RESERVED_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK3_RESERVED_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

//
#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK3_IDLE_STATE_SHIFT                  MK_SHIFT_CONST(20)
#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK3_IDLE_STATE_FIELD                  MK_FIELD_CONST(0x3, PMC_IMPL_CLK_OUT_CNTRL_0_CLK3_IDLE_STATE_SHIFT)
#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK3_IDLE_STATE_RANGE                  21:20
#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK3_IDLE_STATE_MSB                    MK_SHIFT_CONST(21)
#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK3_IDLE_STATE_LSB                    MK_SHIFT_CONST(20)
#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK3_IDLE_STATE_WOFFSET                        0x0
#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK3_IDLE_STATE_DEFAULT                        MK_MASK_CONST(0x0)
#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK3_IDLE_STATE_DEFAULT_MASK                   MK_MASK_CONST(0x3)
#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK3_IDLE_STATE_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK3_IDLE_STATE_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK3_IDLE_STATE_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK3_IDLE_STATE_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK3_IDLE_STATE_LOW                    MK_ENUM_CONST(0)
#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK3_IDLE_STATE_HIGH                   MK_ENUM_CONST(1)
#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK3_IDLE_STATE_TRIS                   MK_ENUM_CONST(2)

#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK3_SRC_SEL_SHIFT                     MK_SHIFT_CONST(22)
#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK3_SRC_SEL_FIELD                     MK_FIELD_CONST(0x3, PMC_IMPL_CLK_OUT_CNTRL_0_CLK3_SRC_SEL_SHIFT)
#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK3_SRC_SEL_RANGE                     23:22
#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK3_SRC_SEL_MSB                       MK_SHIFT_CONST(23)
#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK3_SRC_SEL_LSB                       MK_SHIFT_CONST(22)
#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK3_SRC_SEL_WOFFSET                   0x0
#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK3_SRC_SEL_DEFAULT                   MK_MASK_CONST(0x0)
#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK3_SRC_SEL_DEFAULT_MASK                      MK_MASK_CONST(0x3)
#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK3_SRC_SEL_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK3_SRC_SEL_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK3_SRC_SEL_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK3_SRC_SEL_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK3_SRC_SEL_OSC_DIV1                  MK_ENUM_CONST(0)
#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK3_SRC_SEL_OSC_DIV2                  MK_ENUM_CONST(1)
#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK3_SRC_SEL_OSC_DIV3                  MK_ENUM_CONST(2)
#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK3_SRC_SEL_CAR                       MK_ENUM_CONST(3)


// Reserved address 0x68
//SATA_PWRGT       - Moved to arpmc_misc bug #200181701
//For sensor shutdown and control
//sensor control register defines chip behaviour when sensor request is triggered
//it can power gate down all cpus if enabled
//it can trigger reset - (will cause cpu power request to go down and power gating down all cpus)
//IMPORTANT, to preserve ram content, any reads/writes to scratch registers  will  be blocked after sensor triggered reset.
//sw must reset BLOCK_SCRATCH_WRITE to enable writes to scratch registers
//Reset level:l0coldrst_pmc_pclk_srstn

// Register PMC_IMPL_SENSOR_CTRL_0
#define PMC_IMPL_SENSOR_CTRL_0                  MK_ADDR_CONST(0x6c)
#define PMC_IMPL_SENSOR_CTRL_0_SECURE                   0x0
#define PMC_IMPL_SENSOR_CTRL_0_DUAL                     0x0
#define PMC_IMPL_SENSOR_CTRL_0_SCR                      CNTRL_SCR_0
#define PMC_IMPL_SENSOR_CTRL_0_SCRREG                   PMC_IMPL_SCR_CNTRL_SCR_0
#define PMC_IMPL_SENSOR_CTRL_0_WORD_COUNT                       0x1
#define PMC_IMPL_SENSOR_CTRL_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define PMC_IMPL_SENSOR_CTRL_0_RESET_MASK                       MK_MASK_CONST(0xf)
#define PMC_IMPL_SENSOR_CTRL_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define PMC_IMPL_SENSOR_CTRL_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define PMC_IMPL_SENSOR_CTRL_0_READ_MASK                        MK_MASK_CONST(0xf)
#define PMC_IMPL_SENSOR_CTRL_0_WRITE_MASK                       MK_MASK_CONST(0xf)
//DEFUNCT - power gate cpus on temp sensor going up
#define PMC_IMPL_SENSOR_CTRL_0_ENABLE_PG_SHIFT                  MK_SHIFT_CONST(0)
#define PMC_IMPL_SENSOR_CTRL_0_ENABLE_PG_FIELD                  MK_FIELD_CONST(0x1, PMC_IMPL_SENSOR_CTRL_0_ENABLE_PG_SHIFT)
#define PMC_IMPL_SENSOR_CTRL_0_ENABLE_PG_RANGE                  0:0
#define PMC_IMPL_SENSOR_CTRL_0_ENABLE_PG_MSB                    MK_SHIFT_CONST(0)
#define PMC_IMPL_SENSOR_CTRL_0_ENABLE_PG_LSB                    MK_SHIFT_CONST(0)
#define PMC_IMPL_SENSOR_CTRL_0_ENABLE_PG_WOFFSET                        0x0
#define PMC_IMPL_SENSOR_CTRL_0_ENABLE_PG_DEFAULT                        MK_MASK_CONST(0x0)
#define PMC_IMPL_SENSOR_CTRL_0_ENABLE_PG_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define PMC_IMPL_SENSOR_CTRL_0_ENABLE_PG_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define PMC_IMPL_SENSOR_CTRL_0_ENABLE_PG_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define PMC_IMPL_SENSOR_CTRL_0_ENABLE_PG_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define PMC_IMPL_SENSOR_CTRL_0_ENABLE_PG_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define PMC_IMPL_SENSOR_CTRL_0_ENABLE_PG_OFF                    MK_ENUM_CONST(0)
#define PMC_IMPL_SENSOR_CTRL_0_ENABLE_PG_ON                     MK_ENUM_CONST(1)

// enables reset on sensor going up.
#define PMC_IMPL_SENSOR_CTRL_0_ENABLE_RST_SHIFT                 MK_SHIFT_CONST(1)
#define PMC_IMPL_SENSOR_CTRL_0_ENABLE_RST_FIELD                 MK_FIELD_CONST(0x1, PMC_IMPL_SENSOR_CTRL_0_ENABLE_RST_SHIFT)
#define PMC_IMPL_SENSOR_CTRL_0_ENABLE_RST_RANGE                 1:1
#define PMC_IMPL_SENSOR_CTRL_0_ENABLE_RST_MSB                   MK_SHIFT_CONST(1)
#define PMC_IMPL_SENSOR_CTRL_0_ENABLE_RST_LSB                   MK_SHIFT_CONST(1)
#define PMC_IMPL_SENSOR_CTRL_0_ENABLE_RST_WOFFSET                       0x0
#define PMC_IMPL_SENSOR_CTRL_0_ENABLE_RST_DEFAULT                       MK_MASK_CONST(0x0)
#define PMC_IMPL_SENSOR_CTRL_0_ENABLE_RST_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define PMC_IMPL_SENSOR_CTRL_0_ENABLE_RST_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define PMC_IMPL_SENSOR_CTRL_0_ENABLE_RST_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define PMC_IMPL_SENSOR_CTRL_0_ENABLE_RST_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define PMC_IMPL_SENSOR_CTRL_0_ENABLE_RST_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define PMC_IMPL_SENSOR_CTRL_0_ENABLE_RST_OFF                   MK_ENUM_CONST(0)
#define PMC_IMPL_SENSOR_CTRL_0_ENABLE_RST_ON                    MK_ENUM_CONST(1)

//reset by user, set by pmc when entering sensor reset - DEFUNCT - will always read back 0
#define PMC_IMPL_SENSOR_CTRL_0_BLOCK_SCRATCH_WRITE_SHIFT                        MK_SHIFT_CONST(2)
#define PMC_IMPL_SENSOR_CTRL_0_BLOCK_SCRATCH_WRITE_FIELD                        MK_FIELD_CONST(0x1, PMC_IMPL_SENSOR_CTRL_0_BLOCK_SCRATCH_WRITE_SHIFT)
#define PMC_IMPL_SENSOR_CTRL_0_BLOCK_SCRATCH_WRITE_RANGE                        2:2
#define PMC_IMPL_SENSOR_CTRL_0_BLOCK_SCRATCH_WRITE_MSB                  MK_SHIFT_CONST(2)
#define PMC_IMPL_SENSOR_CTRL_0_BLOCK_SCRATCH_WRITE_LSB                  MK_SHIFT_CONST(2)
#define PMC_IMPL_SENSOR_CTRL_0_BLOCK_SCRATCH_WRITE_WOFFSET                      0x0
#define PMC_IMPL_SENSOR_CTRL_0_BLOCK_SCRATCH_WRITE_DEFAULT                      MK_MASK_CONST(0x0)
#define PMC_IMPL_SENSOR_CTRL_0_BLOCK_SCRATCH_WRITE_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define PMC_IMPL_SENSOR_CTRL_0_BLOCK_SCRATCH_WRITE_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define PMC_IMPL_SENSOR_CTRL_0_BLOCK_SCRATCH_WRITE_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define PMC_IMPL_SENSOR_CTRL_0_BLOCK_SCRATCH_WRITE_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define PMC_IMPL_SENSOR_CTRL_0_BLOCK_SCRATCH_WRITE_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define PMC_IMPL_SENSOR_CTRL_0_BLOCK_SCRATCH_WRITE_OFF_ON                       MK_ENUM_CONST(0)

// enables reset on FSI therm reset req
#define PMC_IMPL_SENSOR_CTRL_0_ENABLE_FSI_RST_SHIFT                     MK_SHIFT_CONST(3)
#define PMC_IMPL_SENSOR_CTRL_0_ENABLE_FSI_RST_FIELD                     MK_FIELD_CONST(0x1, PMC_IMPL_SENSOR_CTRL_0_ENABLE_FSI_RST_SHIFT)
#define PMC_IMPL_SENSOR_CTRL_0_ENABLE_FSI_RST_RANGE                     3:3
#define PMC_IMPL_SENSOR_CTRL_0_ENABLE_FSI_RST_MSB                       MK_SHIFT_CONST(3)
#define PMC_IMPL_SENSOR_CTRL_0_ENABLE_FSI_RST_LSB                       MK_SHIFT_CONST(3)
#define PMC_IMPL_SENSOR_CTRL_0_ENABLE_FSI_RST_WOFFSET                   0x0
#define PMC_IMPL_SENSOR_CTRL_0_ENABLE_FSI_RST_DEFAULT                   MK_MASK_CONST(0x0)
#define PMC_IMPL_SENSOR_CTRL_0_ENABLE_FSI_RST_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define PMC_IMPL_SENSOR_CTRL_0_ENABLE_FSI_RST_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define PMC_IMPL_SENSOR_CTRL_0_ENABLE_FSI_RST_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define PMC_IMPL_SENSOR_CTRL_0_ENABLE_FSI_RST_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define PMC_IMPL_SENSOR_CTRL_0_ENABLE_FSI_RST_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define PMC_IMPL_SENSOR_CTRL_0_ENABLE_FSI_RST_OFF                       MK_ENUM_CONST(0)
#define PMC_IMPL_SENSOR_CTRL_0_ENABLE_FSI_RST_ON                        MK_ENUM_CONST(1)

// RESET STATUS REGISTER (RST_STATUS)
// L0 source asserts ALL resets (L0, L1 and L2 resets - warm AND cold)
// L1 source asserts all L1 and L2 resets (L1 and L2 resets - warm AND cold)
// L2 source asserts all L2 resets - warm AND cold
// Warm source asserts all warm resets (L1 AND L2 warm)
// Reset level:l0coldrst_pmc_pclk_srstn

// Register PMC_IMPL_RST_STATUS_0
#define PMC_IMPL_RST_STATUS_0                   MK_ADDR_CONST(0x70)
#define PMC_IMPL_RST_STATUS_0_SECURE                    0x0
#define PMC_IMPL_RST_STATUS_0_DUAL                      0x0
#define PMC_IMPL_RST_STATUS_0_SCR                       CNTRL_SCR_0
#define PMC_IMPL_RST_STATUS_0_SCRREG                    PMC_IMPL_SCR_CNTRL_SCR_0
#define PMC_IMPL_RST_STATUS_0_WORD_COUNT                        0x1
#define PMC_IMPL_RST_STATUS_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define PMC_IMPL_RST_STATUS_0_RESET_MASK                        MK_MASK_CONST(0xff)
#define PMC_IMPL_RST_STATUS_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define PMC_IMPL_RST_STATUS_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define PMC_IMPL_RST_STATUS_0_READ_MASK                         MK_MASK_CONST(0xff)
#define PMC_IMPL_RST_STATUS_0_WRITE_MASK                        MK_MASK_CONST(0x0)
//Reset Level
#define PMC_IMPL_RST_STATUS_0_RST_LEVEL_SHIFT                   MK_SHIFT_CONST(0)
#define PMC_IMPL_RST_STATUS_0_RST_LEVEL_FIELD                   MK_FIELD_CONST(0x3, PMC_IMPL_RST_STATUS_0_RST_LEVEL_SHIFT)
#define PMC_IMPL_RST_STATUS_0_RST_LEVEL_RANGE                   1:0
#define PMC_IMPL_RST_STATUS_0_RST_LEVEL_MSB                     MK_SHIFT_CONST(1)
#define PMC_IMPL_RST_STATUS_0_RST_LEVEL_LSB                     MK_SHIFT_CONST(0)
#define PMC_IMPL_RST_STATUS_0_RST_LEVEL_WOFFSET                 0x0
#define PMC_IMPL_RST_STATUS_0_RST_LEVEL_DEFAULT                 MK_MASK_CONST(0x0)
#define PMC_IMPL_RST_STATUS_0_RST_LEVEL_DEFAULT_MASK                    MK_MASK_CONST(0x3)
#define PMC_IMPL_RST_STATUS_0_RST_LEVEL_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define PMC_IMPL_RST_STATUS_0_RST_LEVEL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define PMC_IMPL_RST_STATUS_0_RST_LEVEL_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define PMC_IMPL_RST_STATUS_0_RST_LEVEL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define PMC_IMPL_RST_STATUS_0_RST_LEVEL_INIT_ENUM                       L0
#define PMC_IMPL_RST_STATUS_0_RST_LEVEL_L0                      MK_ENUM_CONST(0)
#define PMC_IMPL_RST_STATUS_0_RST_LEVEL_L1                      MK_ENUM_CONST(1)
#define PMC_IMPL_RST_STATUS_0_RST_LEVEL_L2                      MK_ENUM_CONST(2)
#define PMC_IMPL_RST_STATUS_0_RST_LEVEL_WARM                    MK_ENUM_CONST(3)

//Reset Source - NOTE: BCCPLEX is TOP_WDT0, LCCPLEX is TOP_WDT1 and APEWDT is TOP_WDT2.
#define PMC_IMPL_RST_STATUS_0_RST_SOURCE_SHIFT                  MK_SHIFT_CONST(2)
#define PMC_IMPL_RST_STATUS_0_RST_SOURCE_FIELD                  MK_FIELD_CONST(0x3f, PMC_IMPL_RST_STATUS_0_RST_SOURCE_SHIFT)
#define PMC_IMPL_RST_STATUS_0_RST_SOURCE_RANGE                  7:2
#define PMC_IMPL_RST_STATUS_0_RST_SOURCE_MSB                    MK_SHIFT_CONST(7)
#define PMC_IMPL_RST_STATUS_0_RST_SOURCE_LSB                    MK_SHIFT_CONST(2)
#define PMC_IMPL_RST_STATUS_0_RST_SOURCE_WOFFSET                        0x0
#define PMC_IMPL_RST_STATUS_0_RST_SOURCE_DEFAULT                        MK_MASK_CONST(0x0)
#define PMC_IMPL_RST_STATUS_0_RST_SOURCE_DEFAULT_MASK                   MK_MASK_CONST(0x3f)
#define PMC_IMPL_RST_STATUS_0_RST_SOURCE_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define PMC_IMPL_RST_STATUS_0_RST_SOURCE_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define PMC_IMPL_RST_STATUS_0_RST_SOURCE_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define PMC_IMPL_RST_STATUS_0_RST_SOURCE_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define PMC_IMPL_RST_STATUS_0_RST_SOURCE_INIT_ENUM                      SYS_RESET_N
#define PMC_IMPL_RST_STATUS_0_RST_SOURCE_SYS_RESET_N                    MK_ENUM_CONST(0)
#define PMC_IMPL_RST_STATUS_0_RST_SOURCE_AOWDT                  MK_ENUM_CONST(1)
#define PMC_IMPL_RST_STATUS_0_RST_SOURCE_BCCPLEXWDT                     MK_ENUM_CONST(2)
#define PMC_IMPL_RST_STATUS_0_RST_SOURCE_BPMPWDT                        MK_ENUM_CONST(3)
#define PMC_IMPL_RST_STATUS_0_RST_SOURCE_SCEWDT                 MK_ENUM_CONST(4)
#define PMC_IMPL_RST_STATUS_0_RST_SOURCE_SPEWDT                 MK_ENUM_CONST(5)
#define PMC_IMPL_RST_STATUS_0_RST_SOURCE_APEWDT                 MK_ENUM_CONST(6)
#define PMC_IMPL_RST_STATUS_0_RST_SOURCE_LCCPLEXWDT                     MK_ENUM_CONST(7)
#define PMC_IMPL_RST_STATUS_0_RST_SOURCE_SENSOR                 MK_ENUM_CONST(8)
#define PMC_IMPL_RST_STATUS_0_RST_SOURCE_AOTAG                  MK_ENUM_CONST(9)
#define PMC_IMPL_RST_STATUS_0_RST_SOURCE_VFSENSOR                       MK_ENUM_CONST(10)
#define PMC_IMPL_RST_STATUS_0_RST_SOURCE_MAINSWRST                      MK_ENUM_CONST(11)
#define PMC_IMPL_RST_STATUS_0_RST_SOURCE_SC7                    MK_ENUM_CONST(12)
#define PMC_IMPL_RST_STATUS_0_RST_SOURCE_HSM                    MK_ENUM_CONST(13)
#define PMC_IMPL_RST_STATUS_0_RST_SOURCE_CSITE                  MK_ENUM_CONST(14)
#define PMC_IMPL_RST_STATUS_0_RST_SOURCE_RCEWDT                 MK_ENUM_CONST(15)
#define PMC_IMPL_RST_STATUS_0_RST_SOURCE_PVA0WDT                        MK_ENUM_CONST(16)
#define PMC_IMPL_RST_STATUS_0_RST_SOURCE_PVA1WDT                        MK_ENUM_CONST(17)
#define PMC_IMPL_RST_STATUS_0_RST_SOURCE_L1A_ASYNC                      MK_ENUM_CONST(18)
#define PMC_IMPL_RST_STATUS_0_RST_SOURCE_BPMPBOOT                       MK_ENUM_CONST(19)
#define PMC_IMPL_RST_STATUS_0_RST_SOURCE_FUSECRC                        MK_ENUM_CONST(20)
#define PMC_IMPL_RST_STATUS_0_RST_SOURCE_DCEWDT                 MK_ENUM_CONST(21)
#define PMC_IMPL_RST_STATUS_0_RST_SOURCE_PSCWDT                 MK_ENUM_CONST(22)
#define PMC_IMPL_RST_STATUS_0_RST_SOURCE_PSC_SW                 MK_ENUM_CONST(23)
#define PMC_IMPL_RST_STATUS_0_RST_SOURCE_CSITE_SW                       MK_ENUM_CONST(24)
#define PMC_IMPL_RST_STATUS_0_RST_SOURCE_POD                    MK_ENUM_CONST(25)
#define PMC_IMPL_RST_STATUS_0_RST_SOURCE_SCPM                   MK_ENUM_CONST(26)
#define PMC_IMPL_RST_STATUS_0_RST_SOURCE_VREFRO_POWERBAD                        MK_ENUM_CONST(27)
#define PMC_IMPL_RST_STATUS_0_RST_SOURCE_VMON                   MK_ENUM_CONST(28)
#define PMC_IMPL_RST_STATUS_0_RST_SOURCE_FMON                   MK_ENUM_CONST(29)
#define PMC_IMPL_RST_STATUS_0_RST_SOURCE_FSI_R5WDT                      MK_ENUM_CONST(30)
#define PMC_IMPL_RST_STATUS_0_RST_SOURCE_FSI_THERM                      MK_ENUM_CONST(31)
#define PMC_IMPL_RST_STATUS_0_RST_SOURCE_FSI_R52C0WDT                   MK_ENUM_CONST(32)
#define PMC_IMPL_RST_STATUS_0_RST_SOURCE_FSI_R52C1WDT                   MK_ENUM_CONST(33)
#define PMC_IMPL_RST_STATUS_0_RST_SOURCE_FSI_R52C2WDT                   MK_ENUM_CONST(34)
#define PMC_IMPL_RST_STATUS_0_RST_SOURCE_FSI_R52C3WDT                   MK_ENUM_CONST(35)
#define PMC_IMPL_RST_STATUS_0_RST_SOURCE_FSI_FMON                       MK_ENUM_CONST(36)
#define PMC_IMPL_RST_STATUS_0_RST_SOURCE_FSI_VMON                       MK_ENUM_CONST(37)


// Register PMC_IMPL_IO_DPD_REQ_0
#define PMC_IMPL_IO_DPD_REQ_0                   MK_ADDR_CONST(0x74)
#define PMC_IMPL_IO_DPD_REQ_0_SECURE                    0x0
#define PMC_IMPL_IO_DPD_REQ_0_DUAL                      0x0
#define PMC_IMPL_IO_DPD_REQ_0_SCR                       0
#define PMC_IMPL_IO_DPD_REQ_0_SCRREG                    0
#define PMC_IMPL_IO_DPD_REQ_0_WORD_COUNT                        0x1
#define PMC_IMPL_IO_DPD_REQ_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD_REQ_0_RESET_MASK                        MK_MASK_CONST(0xc0000000)
#define PMC_IMPL_IO_DPD_REQ_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD_REQ_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD_REQ_0_READ_MASK                         MK_MASK_CONST(0xc0000000)
#define PMC_IMPL_IO_DPD_REQ_0_WRITE_MASK                        MK_MASK_CONST(0x0)
// DEFUNC : Retaining this for viva
#define PMC_IMPL_IO_DPD_REQ_0_CODE_SHIFT                        MK_SHIFT_CONST(30)
#define PMC_IMPL_IO_DPD_REQ_0_CODE_FIELD                        MK_FIELD_CONST(0x3, PMC_IMPL_IO_DPD_REQ_0_CODE_SHIFT)
#define PMC_IMPL_IO_DPD_REQ_0_CODE_RANGE                        31:30
#define PMC_IMPL_IO_DPD_REQ_0_CODE_MSB                  MK_SHIFT_CONST(31)
#define PMC_IMPL_IO_DPD_REQ_0_CODE_LSB                  MK_SHIFT_CONST(30)
#define PMC_IMPL_IO_DPD_REQ_0_CODE_WOFFSET                      0x0
#define PMC_IMPL_IO_DPD_REQ_0_CODE_DEFAULT                      MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD_REQ_0_CODE_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define PMC_IMPL_IO_DPD_REQ_0_CODE_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD_REQ_0_CODE_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD_REQ_0_CODE_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD_REQ_0_CODE_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DPD_REQ_0_CODE_IDLE                 MK_ENUM_CONST(0)
#define PMC_IMPL_IO_DPD_REQ_0_CODE_DPD_OFF                      MK_ENUM_CONST(1)
#define PMC_IMPL_IO_DPD_REQ_0_CODE_DPD_ON                       MK_ENUM_CONST(2)


// Reserved address 0x78
//IO_DPD_STATUS

// Reserved address 0x7c
//IO_DPD2_REQ

// Reserved address 0x80
//IO_DPD2_STATUS

// Reserved address 0x84
//IO_DPD3_REQ

// Reserved address 0x88
//IO_DPD3_STATUS

// Reserved address 0x8c
//IO_DPD4_REQ

// Reserved address 0x90
//IO_DPD4_STATUS

// Reserved address 0x94
//IO_DPD5_REQ

// Reserved address 0x98
//IO_DPD5_STATUS

// Reserved address 0x9c
//IO_DPD6_REQ

// Reserved address 0xa0
//IO_DPD6_STATUS

// Reserved address 0xa4
//IO_DPD7_REQ

// Reserved address 0xa8
//IO_DPD7_STATUS

// Reserved address 0xac
//IO_DPD8_REQ

// Reserved address 0xb0
//IO_DPD8_STATUS

// Reserved address 0xb4
//IO_DPD7_OFF_MASK

// Reserved address 0xb8
//IO_DPD8_OFF_MASK
//Reset level:l0coldrst_pmc_pclk_srstn
//this is timer added to guarantee proper timing spacing in hw between sel_dpd and e_dpd signals issued to pads.
//minimum of 200ns is required, timer in apb clock. Refer to the description under IO_DPD_REQ register for more details on the usage of this timer.

// Register PMC_IMPL_SEL_DPD_TIM_0
#define PMC_IMPL_SEL_DPD_TIM_0                  MK_ADDR_CONST(0xbc)
#define PMC_IMPL_SEL_DPD_TIM_0_SECURE                   0x0
#define PMC_IMPL_SEL_DPD_TIM_0_DUAL                     0x0
#define PMC_IMPL_SEL_DPD_TIM_0_SCR                      SEL_DPD_TIM_SCR_0
#define PMC_IMPL_SEL_DPD_TIM_0_SCRREG                   PMC_IMPL_SCR_SEL_DPD_TIM_SCR_0
#define PMC_IMPL_SEL_DPD_TIM_0_WORD_COUNT                       0x1
#define PMC_IMPL_SEL_DPD_TIM_0_RESET_VAL                        MK_MASK_CONST(0x7f)
#define PMC_IMPL_SEL_DPD_TIM_0_RESET_MASK                       MK_MASK_CONST(0x7f)
#define PMC_IMPL_SEL_DPD_TIM_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define PMC_IMPL_SEL_DPD_TIM_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define PMC_IMPL_SEL_DPD_TIM_0_READ_MASK                        MK_MASK_CONST(0x7f)
#define PMC_IMPL_SEL_DPD_TIM_0_WRITE_MASK                       MK_MASK_CONST(0x7f)
// timer which separates e_dpd deassertion time from sel_dpd deassertion time. in apb_clk
#define PMC_IMPL_SEL_DPD_TIM_0_SEL_DPD_TIM_SHIFT                        MK_SHIFT_CONST(0)
#define PMC_IMPL_SEL_DPD_TIM_0_SEL_DPD_TIM_FIELD                        MK_FIELD_CONST(0x7f, PMC_IMPL_SEL_DPD_TIM_0_SEL_DPD_TIM_SHIFT)
#define PMC_IMPL_SEL_DPD_TIM_0_SEL_DPD_TIM_RANGE                        6:0
#define PMC_IMPL_SEL_DPD_TIM_0_SEL_DPD_TIM_MSB                  MK_SHIFT_CONST(6)
#define PMC_IMPL_SEL_DPD_TIM_0_SEL_DPD_TIM_LSB                  MK_SHIFT_CONST(0)
#define PMC_IMPL_SEL_DPD_TIM_0_SEL_DPD_TIM_WOFFSET                      0x0
#define PMC_IMPL_SEL_DPD_TIM_0_SEL_DPD_TIM_DEFAULT                      MK_MASK_CONST(0x7f)
#define PMC_IMPL_SEL_DPD_TIM_0_SEL_DPD_TIM_DEFAULT_MASK                 MK_MASK_CONST(0x7f)
#define PMC_IMPL_SEL_DPD_TIM_0_SEL_DPD_TIM_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define PMC_IMPL_SEL_DPD_TIM_0_SEL_DPD_TIM_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define PMC_IMPL_SEL_DPD_TIM_0_SEL_DPD_TIM_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define PMC_IMPL_SEL_DPD_TIM_0_SEL_DPD_TIM_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

//Removed following register as part of bug 200117927 cleanup

// Reserved address 0xc0
//VDD_SEL

// Reserved address 0xc4
//VDDSEL_MEM1

// Reserved address 0xc8
//DDR_CFG

// Reserved address 0xcc
//DDR_CFG_MEM1

// Reserved address 0xd0
//DSI_SEL_DPD removed.
//DEFUNCT - TSC_MULT - DEFUNCT

// Register PMC_IMPL_TSC_MULT_0
#define PMC_IMPL_TSC_MULT_0                     MK_ADDR_CONST(0xd4)
#define PMC_IMPL_TSC_MULT_0_SECURE                      0x0
#define PMC_IMPL_TSC_MULT_0_DUAL                        0x0
#define PMC_IMPL_TSC_MULT_0_SCR                         0
#define PMC_IMPL_TSC_MULT_0_SCRREG                      0
#define PMC_IMPL_TSC_MULT_0_WORD_COUNT                  0x1
#define PMC_IMPL_TSC_MULT_0_RESET_VAL                   MK_MASK_CONST(0x16e0)
#define PMC_IMPL_TSC_MULT_0_RESET_MASK                  MK_MASK_CONST(0xeffff)
#define PMC_IMPL_TSC_MULT_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define PMC_IMPL_TSC_MULT_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define PMC_IMPL_TSC_MULT_0_READ_MASK                   MK_MASK_CONST(0xfffff)
#define PMC_IMPL_TSC_MULT_0_WRITE_MASK                  MK_MASK_CONST(0xeffff)
//TSC multiply value (default based on 12Mhz osc).
//Value is (osc-freq * 16 / 32.768khz) when osc is disabled and tsc runs at 32khz clock.
//For example for 12Mhz osc, VALUE = 5856.
#define PMC_IMPL_TSC_MULT_0_MULT_VAL_SHIFT                      MK_SHIFT_CONST(0)
#define PMC_IMPL_TSC_MULT_0_MULT_VAL_FIELD                      MK_FIELD_CONST(0xffff, PMC_IMPL_TSC_MULT_0_MULT_VAL_SHIFT)
#define PMC_IMPL_TSC_MULT_0_MULT_VAL_RANGE                      15:0
#define PMC_IMPL_TSC_MULT_0_MULT_VAL_MSB                        MK_SHIFT_CONST(15)
#define PMC_IMPL_TSC_MULT_0_MULT_VAL_LSB                        MK_SHIFT_CONST(0)
#define PMC_IMPL_TSC_MULT_0_MULT_VAL_WOFFSET                    0x0
#define PMC_IMPL_TSC_MULT_0_MULT_VAL_DEFAULT                    MK_MASK_CONST(0x16e0)
#define PMC_IMPL_TSC_MULT_0_MULT_VAL_DEFAULT_MASK                       MK_MASK_CONST(0xffff)
#define PMC_IMPL_TSC_MULT_0_MULT_VAL_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define PMC_IMPL_TSC_MULT_0_MULT_VAL_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define PMC_IMPL_TSC_MULT_0_MULT_VAL_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define PMC_IMPL_TSC_MULT_0_MULT_VAL_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

//Clock frequency being used for counter.
//0 = Fast (i.e. osc frequency)
//1 = Slow (i.e. 32khz)
//Note, when PMC_DPD_ENABLE[TSC_MULT_EN] bit is set to '1' then PMC waits for first rising-edge on slow clock
//before switching counter to slow clock. This status is also set at the first rising-edge of slow clock
//(to indicate the change of clock for counter).
#define PMC_IMPL_TSC_MULT_0_FREQ_STS_SHIFT                      MK_SHIFT_CONST(16)
#define PMC_IMPL_TSC_MULT_0_FREQ_STS_FIELD                      MK_FIELD_CONST(0x1, PMC_IMPL_TSC_MULT_0_FREQ_STS_SHIFT)
#define PMC_IMPL_TSC_MULT_0_FREQ_STS_RANGE                      16:16
#define PMC_IMPL_TSC_MULT_0_FREQ_STS_MSB                        MK_SHIFT_CONST(16)
#define PMC_IMPL_TSC_MULT_0_FREQ_STS_LSB                        MK_SHIFT_CONST(16)
#define PMC_IMPL_TSC_MULT_0_FREQ_STS_WOFFSET                    0x0
#define PMC_IMPL_TSC_MULT_0_FREQ_STS_DEFAULT                    MK_MASK_CONST(0x0)
#define PMC_IMPL_TSC_MULT_0_FREQ_STS_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define PMC_IMPL_TSC_MULT_0_FREQ_STS_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define PMC_IMPL_TSC_MULT_0_FREQ_STS_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define PMC_IMPL_TSC_MULT_0_FREQ_STS_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define PMC_IMPL_TSC_MULT_0_FREQ_STS_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

//This bit selects one of the 6 binary time stamp counter bits. Bug 895886
#define PMC_IMPL_TSC_MULT_0_TICK_SEL_SHIFT                      MK_SHIFT_CONST(17)
#define PMC_IMPL_TSC_MULT_0_TICK_SEL_FIELD                      MK_FIELD_CONST(0x7, PMC_IMPL_TSC_MULT_0_TICK_SEL_SHIFT)
#define PMC_IMPL_TSC_MULT_0_TICK_SEL_RANGE                      19:17
#define PMC_IMPL_TSC_MULT_0_TICK_SEL_MSB                        MK_SHIFT_CONST(19)
#define PMC_IMPL_TSC_MULT_0_TICK_SEL_LSB                        MK_SHIFT_CONST(17)
#define PMC_IMPL_TSC_MULT_0_TICK_SEL_WOFFSET                    0x0
#define PMC_IMPL_TSC_MULT_0_TICK_SEL_DEFAULT                    MK_MASK_CONST(0x0)
#define PMC_IMPL_TSC_MULT_0_TICK_SEL_DEFAULT_MASK                       MK_MASK_CONST(0x7)
#define PMC_IMPL_TSC_MULT_0_TICK_SEL_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define PMC_IMPL_TSC_MULT_0_TICK_SEL_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define PMC_IMPL_TSC_MULT_0_TICK_SEL_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define PMC_IMPL_TSC_MULT_0_TICK_SEL_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define PMC_IMPL_TSC_MULT_0_TICK_SEL_BIT0                       MK_ENUM_CONST(0)
#define PMC_IMPL_TSC_MULT_0_TICK_SEL_BIT1                       MK_ENUM_CONST(1)
#define PMC_IMPL_TSC_MULT_0_TICK_SEL_BIT2                       MK_ENUM_CONST(2)
#define PMC_IMPL_TSC_MULT_0_TICK_SEL_BIT3                       MK_ENUM_CONST(3)
#define PMC_IMPL_TSC_MULT_0_TICK_SEL_BIT4                       MK_ENUM_CONST(4)
#define PMC_IMPL_TSC_MULT_0_TICK_SEL_BIT5                       MK_ENUM_CONST(5)


// Reserved address 0xd8

// Reserved address 0xdc
//STICKY_BITS       - Moved to arpmc_misc bug #200181701
//Removed following register as part of bug 200117927 cleanup

// Reserved address 0xe0
//WEAK_BIAS

// Reserved address 0xe4
//WEAK_BIAS_MEM1

// Reserved address 0xe8

// Reserved address 0xec
//GPU_SRAM_STATUS

// Reserved address 0xf0
//SRAM_RAIL_CLAMP

// Reserved address 0xf4
//UFSHC_PWR_CNTRL
//DEFUNCT - CNTRL2 - DEFUNCT

// Register PMC_IMPL_CNTRL2_0
#define PMC_IMPL_CNTRL2_0                       MK_ADDR_CONST(0xf8)
#define PMC_IMPL_CNTRL2_0_SECURE                        0x0
#define PMC_IMPL_CNTRL2_0_DUAL                  0x0
#define PMC_IMPL_CNTRL2_0_SCR                   CNTRL_SCR_0
#define PMC_IMPL_CNTRL2_0_SCRREG                        PMC_IMPL_SCR_CNTRL_SCR_0
#define PMC_IMPL_CNTRL2_0_WORD_COUNT                    0x1
#define PMC_IMPL_CNTRL2_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define PMC_IMPL_CNTRL2_0_RESET_MASK                    MK_MASK_CONST(0x1c00)
#define PMC_IMPL_CNTRL2_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define PMC_IMPL_CNTRL2_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define PMC_IMPL_CNTRL2_0_READ_MASK                     MK_MASK_CONST(0x1dfe)
#define PMC_IMPL_CNTRL2_0_WRITE_MASK                    MK_MASK_CONST(0x1dfe)
//DEFUNT: Enable for PMC to asset CKE low
#define PMC_IMPL_CNTRL2_0_HOLD_CKE_LOW_EN_SHIFT                 MK_SHIFT_CONST(12)
#define PMC_IMPL_CNTRL2_0_HOLD_CKE_LOW_EN_FIELD                 MK_FIELD_CONST(0x1, PMC_IMPL_CNTRL2_0_HOLD_CKE_LOW_EN_SHIFT)
#define PMC_IMPL_CNTRL2_0_HOLD_CKE_LOW_EN_RANGE                 12:12
#define PMC_IMPL_CNTRL2_0_HOLD_CKE_LOW_EN_MSB                   MK_SHIFT_CONST(12)
#define PMC_IMPL_CNTRL2_0_HOLD_CKE_LOW_EN_LSB                   MK_SHIFT_CONST(12)
#define PMC_IMPL_CNTRL2_0_HOLD_CKE_LOW_EN_WOFFSET                       0x0
#define PMC_IMPL_CNTRL2_0_HOLD_CKE_LOW_EN_DEFAULT                       MK_MASK_CONST(0x0)
#define PMC_IMPL_CNTRL2_0_HOLD_CKE_LOW_EN_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define PMC_IMPL_CNTRL2_0_HOLD_CKE_LOW_EN_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define PMC_IMPL_CNTRL2_0_HOLD_CKE_LOW_EN_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define PMC_IMPL_CNTRL2_0_HOLD_CKE_LOW_EN_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define PMC_IMPL_CNTRL2_0_HOLD_CKE_LOW_EN_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define PMC_IMPL_CNTRL2_0_HOLD_CKE_LOW_EN_DISABLE                       MK_ENUM_CONST(0)
#define PMC_IMPL_CNTRL2_0_HOLD_CKE_LOW_EN_ENABLE                        MK_ENUM_CONST(1)

//SYS_CLK_REQ data value.
//This is used when SYSCLK_ORRIDE is set to '1'
#define PMC_IMPL_CNTRL2_0_SYSCLK_DATA_SHIFT                     MK_SHIFT_CONST(11)
#define PMC_IMPL_CNTRL2_0_SYSCLK_DATA_FIELD                     MK_FIELD_CONST(0x1, PMC_IMPL_CNTRL2_0_SYSCLK_DATA_SHIFT)
#define PMC_IMPL_CNTRL2_0_SYSCLK_DATA_RANGE                     11:11
#define PMC_IMPL_CNTRL2_0_SYSCLK_DATA_MSB                       MK_SHIFT_CONST(11)
#define PMC_IMPL_CNTRL2_0_SYSCLK_DATA_LSB                       MK_SHIFT_CONST(11)
#define PMC_IMPL_CNTRL2_0_SYSCLK_DATA_WOFFSET                   0x0
#define PMC_IMPL_CNTRL2_0_SYSCLK_DATA_DEFAULT                   MK_MASK_CONST(0x0)
#define PMC_IMPL_CNTRL2_0_SYSCLK_DATA_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define PMC_IMPL_CNTRL2_0_SYSCLK_DATA_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define PMC_IMPL_CNTRL2_0_SYSCLK_DATA_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define PMC_IMPL_CNTRL2_0_SYSCLK_DATA_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define PMC_IMPL_CNTRL2_0_SYSCLK_DATA_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

//SYS_CLK_REQ data orride mux-control
//0: data is driven by HW
//1: data is driven by SYSCLK_DATA
#define PMC_IMPL_CNTRL2_0_SYSCLK_ORRIDE_SHIFT                   MK_SHIFT_CONST(10)
#define PMC_IMPL_CNTRL2_0_SYSCLK_ORRIDE_FIELD                   MK_FIELD_CONST(0x1, PMC_IMPL_CNTRL2_0_SYSCLK_ORRIDE_SHIFT)
#define PMC_IMPL_CNTRL2_0_SYSCLK_ORRIDE_RANGE                   10:10
#define PMC_IMPL_CNTRL2_0_SYSCLK_ORRIDE_MSB                     MK_SHIFT_CONST(10)
#define PMC_IMPL_CNTRL2_0_SYSCLK_ORRIDE_LSB                     MK_SHIFT_CONST(10)
#define PMC_IMPL_CNTRL2_0_SYSCLK_ORRIDE_WOFFSET                 0x0
#define PMC_IMPL_CNTRL2_0_SYSCLK_ORRIDE_DEFAULT                 MK_MASK_CONST(0x0)
#define PMC_IMPL_CNTRL2_0_SYSCLK_ORRIDE_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define PMC_IMPL_CNTRL2_0_SYSCLK_ORRIDE_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define PMC_IMPL_CNTRL2_0_SYSCLK_ORRIDE_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define PMC_IMPL_CNTRL2_0_SYSCLK_ORRIDE_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define PMC_IMPL_CNTRL2_0_SYSCLK_ORRIDE_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define PMC_IMPL_CNTRL2_0_SYSCLK_ORRIDE_DISABLE                 MK_ENUM_CONST(0)
#define PMC_IMPL_CNTRL2_0_SYSCLK_ORRIDE_ENABLE                  MK_ENUM_CONST(1)

//RESERVED for LP0BB
#define PMC_IMPL_CNTRL2_0_RESERVED_SHIFT                        MK_SHIFT_CONST(1)
#define PMC_IMPL_CNTRL2_0_RESERVED_FIELD                        MK_FIELD_CONST(0xff, PMC_IMPL_CNTRL2_0_RESERVED_SHIFT)
#define PMC_IMPL_CNTRL2_0_RESERVED_RANGE                        8:1
#define PMC_IMPL_CNTRL2_0_RESERVED_MSB                  MK_SHIFT_CONST(8)
#define PMC_IMPL_CNTRL2_0_RESERVED_LSB                  MK_SHIFT_CONST(1)
#define PMC_IMPL_CNTRL2_0_RESERVED_WOFFSET                      0x0
#define PMC_IMPL_CNTRL2_0_RESERVED_DEFAULT                      MK_MASK_CONST(0x0)
#define PMC_IMPL_CNTRL2_0_RESERVED_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define PMC_IMPL_CNTRL2_0_RESERVED_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define PMC_IMPL_CNTRL2_0_RESERVED_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define PMC_IMPL_CNTRL2_0_RESERVED_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define PMC_IMPL_CNTRL2_0_RESERVED_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Reserved address 0xfc

// Reserved address 0x100
//FUSE_CONTROL       - Moved to arpmc_misc bug #200181701

// Reserved address 0x104

// Reserved address 0x108
//DEBUG_AUTHENTICATION       - Moved to arpmc_misc bug #200181701
// This register is used for Ramdump feature. Refer to bug 1394916 for details
// These bits should be reset only on por reset, s/w reset, thermtrip reset. These should survive watchdog reset and LP0 reset

// Register PMC_IMPL_RAMDUMP_CTL_STATUS_0
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0                   MK_ADDR_CONST(0x10c)
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_SECURE                    0x0
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_DUAL                      0x0
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_SCR                       RAMDUMP_COM_SCR_0
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_SCRREG                    PMC_IMPL_SCR_RAMDUMP_COM_SCR_0
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_WORD_COUNT                        0x1
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_RESET_MASK                        MK_MASK_CONST(0xffffe403)
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_READ_MASK                         MK_MASK_CONST(0xffffe4ff)
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_WRITE_MASK                        MK_MASK_CONST(0x1fffe403)
//Current State of RAMDUMP FSM
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_RAMDUMP_CSTATE_SHIFT                      MK_SHIFT_CONST(29)
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_RAMDUMP_CSTATE_FIELD                      MK_FIELD_CONST(0x7, PMC_IMPL_RAMDUMP_CTL_STATUS_0_RAMDUMP_CSTATE_SHIFT)
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_RAMDUMP_CSTATE_RANGE                      31:29
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_RAMDUMP_CSTATE_MSB                        MK_SHIFT_CONST(31)
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_RAMDUMP_CSTATE_LSB                        MK_SHIFT_CONST(29)
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_RAMDUMP_CSTATE_WOFFSET                    0x0
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_RAMDUMP_CSTATE_DEFAULT                    MK_MASK_CONST(0x0)
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_RAMDUMP_CSTATE_DEFAULT_MASK                       MK_MASK_CONST(0x7)
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_RAMDUMP_CSTATE_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_RAMDUMP_CSTATE_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_RAMDUMP_CSTATE_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_RAMDUMP_CSTATE_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_RAMDUMP_CSTATE_INIT_ENUM                  IDLE
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_RAMDUMP_CSTATE_IDLE                       MK_ENUM_CONST(0)
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_RAMDUMP_CSTATE_CACHEFLUSH                 MK_ENUM_CONST(1)
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_RAMDUMP_CSTATE_WAIT                       MK_ENUM_CONST(2)
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_RAMDUMP_CSTATE_DRAM_SELF_REFRESH                  MK_ENUM_CONST(3)
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_RAMDUMP_CSTATE_DEBUG_RESET_ACK                    MK_ENUM_CONST(4)
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_RAMDUMP_CSTATE_WAIT_FOR_SW_ACK                    MK_ENUM_CONST(5)

//(SW Read/Writable)- indicates if the CCPLEX FIQ handler should halt the CPUs for external debugger to poke.
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_HALT_IN_FIQ_SHIFT                 MK_SHIFT_CONST(28)
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_HALT_IN_FIQ_FIELD                 MK_FIELD_CONST(0x1, PMC_IMPL_RAMDUMP_CTL_STATUS_0_HALT_IN_FIQ_SHIFT)
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_HALT_IN_FIQ_RANGE                 28:28
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_HALT_IN_FIQ_MSB                   MK_SHIFT_CONST(28)
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_HALT_IN_FIQ_LSB                   MK_SHIFT_CONST(28)
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_HALT_IN_FIQ_WOFFSET                       0x0
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_HALT_IN_FIQ_DEFAULT                       MK_MASK_CONST(0x0)
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_HALT_IN_FIQ_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_HALT_IN_FIQ_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_HALT_IN_FIQ_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_HALT_IN_FIQ_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_HALT_IN_FIQ_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

//not used by HW
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_FSI_CLUSTER1_WDT3_FIQ_EXITED_GRACEFULLY_SHIFT                     MK_SHIFT_CONST(27)
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_FSI_CLUSTER1_WDT3_FIQ_EXITED_GRACEFULLY_FIELD                     MK_FIELD_CONST(0x1, PMC_IMPL_RAMDUMP_CTL_STATUS_0_FSI_CLUSTER1_WDT3_FIQ_EXITED_GRACEFULLY_SHIFT)
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_FSI_CLUSTER1_WDT3_FIQ_EXITED_GRACEFULLY_RANGE                     27:27
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_FSI_CLUSTER1_WDT3_FIQ_EXITED_GRACEFULLY_MSB                       MK_SHIFT_CONST(27)
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_FSI_CLUSTER1_WDT3_FIQ_EXITED_GRACEFULLY_LSB                       MK_SHIFT_CONST(27)
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_FSI_CLUSTER1_WDT3_FIQ_EXITED_GRACEFULLY_WOFFSET                   0x0
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_FSI_CLUSTER1_WDT3_FIQ_EXITED_GRACEFULLY_DEFAULT                   MK_MASK_CONST(0x0)
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_FSI_CLUSTER1_WDT3_FIQ_EXITED_GRACEFULLY_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_FSI_CLUSTER1_WDT3_FIQ_EXITED_GRACEFULLY_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_FSI_CLUSTER1_WDT3_FIQ_EXITED_GRACEFULLY_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_FSI_CLUSTER1_WDT3_FIQ_EXITED_GRACEFULLY_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_FSI_CLUSTER1_WDT3_FIQ_EXITED_GRACEFULLY_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

//not used by HW
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_FSI_CLUSTER1_WDT2_FIQ_EXITED_GRACEFULLY_SHIFT                     MK_SHIFT_CONST(26)
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_FSI_CLUSTER1_WDT2_FIQ_EXITED_GRACEFULLY_FIELD                     MK_FIELD_CONST(0x1, PMC_IMPL_RAMDUMP_CTL_STATUS_0_FSI_CLUSTER1_WDT2_FIQ_EXITED_GRACEFULLY_SHIFT)
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_FSI_CLUSTER1_WDT2_FIQ_EXITED_GRACEFULLY_RANGE                     26:26
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_FSI_CLUSTER1_WDT2_FIQ_EXITED_GRACEFULLY_MSB                       MK_SHIFT_CONST(26)
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_FSI_CLUSTER1_WDT2_FIQ_EXITED_GRACEFULLY_LSB                       MK_SHIFT_CONST(26)
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_FSI_CLUSTER1_WDT2_FIQ_EXITED_GRACEFULLY_WOFFSET                   0x0
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_FSI_CLUSTER1_WDT2_FIQ_EXITED_GRACEFULLY_DEFAULT                   MK_MASK_CONST(0x0)
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_FSI_CLUSTER1_WDT2_FIQ_EXITED_GRACEFULLY_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_FSI_CLUSTER1_WDT2_FIQ_EXITED_GRACEFULLY_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_FSI_CLUSTER1_WDT2_FIQ_EXITED_GRACEFULLY_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_FSI_CLUSTER1_WDT2_FIQ_EXITED_GRACEFULLY_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_FSI_CLUSTER1_WDT2_FIQ_EXITED_GRACEFULLY_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

//not used by HW
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_DCE_FIQ_EXITED_GRACEFULLY_SHIFT                   MK_SHIFT_CONST(25)
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_DCE_FIQ_EXITED_GRACEFULLY_FIELD                   MK_FIELD_CONST(0x1, PMC_IMPL_RAMDUMP_CTL_STATUS_0_DCE_FIQ_EXITED_GRACEFULLY_SHIFT)
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_DCE_FIQ_EXITED_GRACEFULLY_RANGE                   25:25
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_DCE_FIQ_EXITED_GRACEFULLY_MSB                     MK_SHIFT_CONST(25)
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_DCE_FIQ_EXITED_GRACEFULLY_LSB                     MK_SHIFT_CONST(25)
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_DCE_FIQ_EXITED_GRACEFULLY_WOFFSET                 0x0
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_DCE_FIQ_EXITED_GRACEFULLY_DEFAULT                 MK_MASK_CONST(0x0)
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_DCE_FIQ_EXITED_GRACEFULLY_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_DCE_FIQ_EXITED_GRACEFULLY_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_DCE_FIQ_EXITED_GRACEFULLY_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_DCE_FIQ_EXITED_GRACEFULLY_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_DCE_FIQ_EXITED_GRACEFULLY_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

//not used by HW
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_RCE_FIQ_EXITED_GRACEFULLY_SHIFT                   MK_SHIFT_CONST(24)
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_RCE_FIQ_EXITED_GRACEFULLY_FIELD                   MK_FIELD_CONST(0x1, PMC_IMPL_RAMDUMP_CTL_STATUS_0_RCE_FIQ_EXITED_GRACEFULLY_SHIFT)
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_RCE_FIQ_EXITED_GRACEFULLY_RANGE                   24:24
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_RCE_FIQ_EXITED_GRACEFULLY_MSB                     MK_SHIFT_CONST(24)
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_RCE_FIQ_EXITED_GRACEFULLY_LSB                     MK_SHIFT_CONST(24)
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_RCE_FIQ_EXITED_GRACEFULLY_WOFFSET                 0x0
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_RCE_FIQ_EXITED_GRACEFULLY_DEFAULT                 MK_MASK_CONST(0x0)
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_RCE_FIQ_EXITED_GRACEFULLY_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_RCE_FIQ_EXITED_GRACEFULLY_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_RCE_FIQ_EXITED_GRACEFULLY_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_RCE_FIQ_EXITED_GRACEFULLY_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_RCE_FIQ_EXITED_GRACEFULLY_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

//SW needs to set this bit before intiating DRAM dump to host PC. This allows RAMDUMP FSM go back to IDLE
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_RAMDUMP_2ND_BOOT_COMPLETE_SHIFT                   MK_SHIFT_CONST(23)
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_RAMDUMP_2ND_BOOT_COMPLETE_FIELD                   MK_FIELD_CONST(0x1, PMC_IMPL_RAMDUMP_CTL_STATUS_0_RAMDUMP_2ND_BOOT_COMPLETE_SHIFT)
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_RAMDUMP_2ND_BOOT_COMPLETE_RANGE                   23:23
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_RAMDUMP_2ND_BOOT_COMPLETE_MSB                     MK_SHIFT_CONST(23)
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_RAMDUMP_2ND_BOOT_COMPLETE_LSB                     MK_SHIFT_CONST(23)
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_RAMDUMP_2ND_BOOT_COMPLETE_WOFFSET                 0x0
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_RAMDUMP_2ND_BOOT_COMPLETE_DEFAULT                 MK_MASK_CONST(0x0)
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_RAMDUMP_2ND_BOOT_COMPLETE_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_RAMDUMP_2ND_BOOT_COMPLETE_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_RAMDUMP_2ND_BOOT_COMPLETE_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_RAMDUMP_2ND_BOOT_COMPLETE_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_RAMDUMP_2ND_BOOT_COMPLETE_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

//not used by HW
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_CCPLEX_REMOTE_EXITED_GRACEFULLY_SHIFT                     MK_SHIFT_CONST(22)
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_CCPLEX_REMOTE_EXITED_GRACEFULLY_FIELD                     MK_FIELD_CONST(0x1, PMC_IMPL_RAMDUMP_CTL_STATUS_0_CCPLEX_REMOTE_EXITED_GRACEFULLY_SHIFT)
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_CCPLEX_REMOTE_EXITED_GRACEFULLY_RANGE                     22:22
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_CCPLEX_REMOTE_EXITED_GRACEFULLY_MSB                       MK_SHIFT_CONST(22)
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_CCPLEX_REMOTE_EXITED_GRACEFULLY_LSB                       MK_SHIFT_CONST(22)
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_CCPLEX_REMOTE_EXITED_GRACEFULLY_WOFFSET                   0x0
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_CCPLEX_REMOTE_EXITED_GRACEFULLY_DEFAULT                   MK_MASK_CONST(0x0)
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_CCPLEX_REMOTE_EXITED_GRACEFULLY_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_CCPLEX_REMOTE_EXITED_GRACEFULLY_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_CCPLEX_REMOTE_EXITED_GRACEFULLY_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_CCPLEX_REMOTE_EXITED_GRACEFULLY_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_CCPLEX_REMOTE_EXITED_GRACEFULLY_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

//not used by HW
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_FSI_CLUSTER1_WDT1_FIQ_EXITED_GRACEFULLY_SHIFT                     MK_SHIFT_CONST(21)
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_FSI_CLUSTER1_WDT1_FIQ_EXITED_GRACEFULLY_FIELD                     MK_FIELD_CONST(0x1, PMC_IMPL_RAMDUMP_CTL_STATUS_0_FSI_CLUSTER1_WDT1_FIQ_EXITED_GRACEFULLY_SHIFT)
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_FSI_CLUSTER1_WDT1_FIQ_EXITED_GRACEFULLY_RANGE                     21:21
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_FSI_CLUSTER1_WDT1_FIQ_EXITED_GRACEFULLY_MSB                       MK_SHIFT_CONST(21)
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_FSI_CLUSTER1_WDT1_FIQ_EXITED_GRACEFULLY_LSB                       MK_SHIFT_CONST(21)
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_FSI_CLUSTER1_WDT1_FIQ_EXITED_GRACEFULLY_WOFFSET                   0x0
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_FSI_CLUSTER1_WDT1_FIQ_EXITED_GRACEFULLY_DEFAULT                   MK_MASK_CONST(0x0)
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_FSI_CLUSTER1_WDT1_FIQ_EXITED_GRACEFULLY_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_FSI_CLUSTER1_WDT1_FIQ_EXITED_GRACEFULLY_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_FSI_CLUSTER1_WDT1_FIQ_EXITED_GRACEFULLY_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_FSI_CLUSTER1_WDT1_FIQ_EXITED_GRACEFULLY_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_FSI_CLUSTER1_WDT1_FIQ_EXITED_GRACEFULLY_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

//not used by HW
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_FSI_CLUSTER1_WDT0_FIQ_EXITED_GRACEFULLY_SHIFT                     MK_SHIFT_CONST(20)
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_FSI_CLUSTER1_WDT0_FIQ_EXITED_GRACEFULLY_FIELD                     MK_FIELD_CONST(0x1, PMC_IMPL_RAMDUMP_CTL_STATUS_0_FSI_CLUSTER1_WDT0_FIQ_EXITED_GRACEFULLY_SHIFT)
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_FSI_CLUSTER1_WDT0_FIQ_EXITED_GRACEFULLY_RANGE                     20:20
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_FSI_CLUSTER1_WDT0_FIQ_EXITED_GRACEFULLY_MSB                       MK_SHIFT_CONST(20)
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_FSI_CLUSTER1_WDT0_FIQ_EXITED_GRACEFULLY_LSB                       MK_SHIFT_CONST(20)
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_FSI_CLUSTER1_WDT0_FIQ_EXITED_GRACEFULLY_WOFFSET                   0x0
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_FSI_CLUSTER1_WDT0_FIQ_EXITED_GRACEFULLY_DEFAULT                   MK_MASK_CONST(0x0)
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_FSI_CLUSTER1_WDT0_FIQ_EXITED_GRACEFULLY_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_FSI_CLUSTER1_WDT0_FIQ_EXITED_GRACEFULLY_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_FSI_CLUSTER1_WDT0_FIQ_EXITED_GRACEFULLY_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_FSI_CLUSTER1_WDT0_FIQ_EXITED_GRACEFULLY_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_FSI_CLUSTER1_WDT0_FIQ_EXITED_GRACEFULLY_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

//not used by HW
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_FSI_CLUSTER0_WDT_FIQ_EXITED_GRACEFULLY_SHIFT                      MK_SHIFT_CONST(19)
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_FSI_CLUSTER0_WDT_FIQ_EXITED_GRACEFULLY_FIELD                      MK_FIELD_CONST(0x1, PMC_IMPL_RAMDUMP_CTL_STATUS_0_FSI_CLUSTER0_WDT_FIQ_EXITED_GRACEFULLY_SHIFT)
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_FSI_CLUSTER0_WDT_FIQ_EXITED_GRACEFULLY_RANGE                      19:19
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_FSI_CLUSTER0_WDT_FIQ_EXITED_GRACEFULLY_MSB                        MK_SHIFT_CONST(19)
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_FSI_CLUSTER0_WDT_FIQ_EXITED_GRACEFULLY_LSB                        MK_SHIFT_CONST(19)
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_FSI_CLUSTER0_WDT_FIQ_EXITED_GRACEFULLY_WOFFSET                    0x0
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_FSI_CLUSTER0_WDT_FIQ_EXITED_GRACEFULLY_DEFAULT                    MK_MASK_CONST(0x0)
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_FSI_CLUSTER0_WDT_FIQ_EXITED_GRACEFULLY_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_FSI_CLUSTER0_WDT_FIQ_EXITED_GRACEFULLY_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_FSI_CLUSTER0_WDT_FIQ_EXITED_GRACEFULLY_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_FSI_CLUSTER0_WDT_FIQ_EXITED_GRACEFULLY_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_FSI_CLUSTER0_WDT_FIQ_EXITED_GRACEFULLY_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

//not used by HW
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_SCE_FIQ_EXITED_GRACEFULLY_SHIFT                   MK_SHIFT_CONST(18)
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_SCE_FIQ_EXITED_GRACEFULLY_FIELD                   MK_FIELD_CONST(0x1, PMC_IMPL_RAMDUMP_CTL_STATUS_0_SCE_FIQ_EXITED_GRACEFULLY_SHIFT)
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_SCE_FIQ_EXITED_GRACEFULLY_RANGE                   18:18
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_SCE_FIQ_EXITED_GRACEFULLY_MSB                     MK_SHIFT_CONST(18)
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_SCE_FIQ_EXITED_GRACEFULLY_LSB                     MK_SHIFT_CONST(18)
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_SCE_FIQ_EXITED_GRACEFULLY_WOFFSET                 0x0
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_SCE_FIQ_EXITED_GRACEFULLY_DEFAULT                 MK_MASK_CONST(0x0)
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_SCE_FIQ_EXITED_GRACEFULLY_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_SCE_FIQ_EXITED_GRACEFULLY_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_SCE_FIQ_EXITED_GRACEFULLY_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_SCE_FIQ_EXITED_GRACEFULLY_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_SCE_FIQ_EXITED_GRACEFULLY_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

//not used by HW
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_APE_FIQ_EXITED_GRACEFULLY_SHIFT                   MK_SHIFT_CONST(17)
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_APE_FIQ_EXITED_GRACEFULLY_FIELD                   MK_FIELD_CONST(0x1, PMC_IMPL_RAMDUMP_CTL_STATUS_0_APE_FIQ_EXITED_GRACEFULLY_SHIFT)
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_APE_FIQ_EXITED_GRACEFULLY_RANGE                   17:17
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_APE_FIQ_EXITED_GRACEFULLY_MSB                     MK_SHIFT_CONST(17)
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_APE_FIQ_EXITED_GRACEFULLY_LSB                     MK_SHIFT_CONST(17)
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_APE_FIQ_EXITED_GRACEFULLY_WOFFSET                 0x0
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_APE_FIQ_EXITED_GRACEFULLY_DEFAULT                 MK_MASK_CONST(0x0)
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_APE_FIQ_EXITED_GRACEFULLY_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_APE_FIQ_EXITED_GRACEFULLY_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_APE_FIQ_EXITED_GRACEFULLY_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_APE_FIQ_EXITED_GRACEFULLY_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_APE_FIQ_EXITED_GRACEFULLY_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

//not used by HW
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_SPE_FIQ_EXITED_GRACEFULLY_SHIFT                   MK_SHIFT_CONST(16)
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_SPE_FIQ_EXITED_GRACEFULLY_FIELD                   MK_FIELD_CONST(0x1, PMC_IMPL_RAMDUMP_CTL_STATUS_0_SPE_FIQ_EXITED_GRACEFULLY_SHIFT)
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_SPE_FIQ_EXITED_GRACEFULLY_RANGE                   16:16
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_SPE_FIQ_EXITED_GRACEFULLY_MSB                     MK_SHIFT_CONST(16)
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_SPE_FIQ_EXITED_GRACEFULLY_LSB                     MK_SHIFT_CONST(16)
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_SPE_FIQ_EXITED_GRACEFULLY_WOFFSET                 0x0
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_SPE_FIQ_EXITED_GRACEFULLY_DEFAULT                 MK_MASK_CONST(0x0)
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_SPE_FIQ_EXITED_GRACEFULLY_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_SPE_FIQ_EXITED_GRACEFULLY_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_SPE_FIQ_EXITED_GRACEFULLY_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_SPE_FIQ_EXITED_GRACEFULLY_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_SPE_FIQ_EXITED_GRACEFULLY_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

//not used by HW
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_BPMP_FIQ_EXITED_GRACEFULLY_SHIFT                  MK_SHIFT_CONST(15)
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_BPMP_FIQ_EXITED_GRACEFULLY_FIELD                  MK_FIELD_CONST(0x1, PMC_IMPL_RAMDUMP_CTL_STATUS_0_BPMP_FIQ_EXITED_GRACEFULLY_SHIFT)
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_BPMP_FIQ_EXITED_GRACEFULLY_RANGE                  15:15
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_BPMP_FIQ_EXITED_GRACEFULLY_MSB                    MK_SHIFT_CONST(15)
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_BPMP_FIQ_EXITED_GRACEFULLY_LSB                    MK_SHIFT_CONST(15)
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_BPMP_FIQ_EXITED_GRACEFULLY_WOFFSET                        0x0
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_BPMP_FIQ_EXITED_GRACEFULLY_DEFAULT                        MK_MASK_CONST(0x0)
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_BPMP_FIQ_EXITED_GRACEFULLY_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_BPMP_FIQ_EXITED_GRACEFULLY_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_BPMP_FIQ_EXITED_GRACEFULLY_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_BPMP_FIQ_EXITED_GRACEFULLY_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_BPMP_FIQ_EXITED_GRACEFULLY_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

//not used by HW
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_CCPLEX_CLUSTER1_FIQ_EXITED_GRACEFULLY_SHIFT                       MK_SHIFT_CONST(14)
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_CCPLEX_CLUSTER1_FIQ_EXITED_GRACEFULLY_FIELD                       MK_FIELD_CONST(0x1, PMC_IMPL_RAMDUMP_CTL_STATUS_0_CCPLEX_CLUSTER1_FIQ_EXITED_GRACEFULLY_SHIFT)
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_CCPLEX_CLUSTER1_FIQ_EXITED_GRACEFULLY_RANGE                       14:14
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_CCPLEX_CLUSTER1_FIQ_EXITED_GRACEFULLY_MSB                 MK_SHIFT_CONST(14)
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_CCPLEX_CLUSTER1_FIQ_EXITED_GRACEFULLY_LSB                 MK_SHIFT_CONST(14)
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_CCPLEX_CLUSTER1_FIQ_EXITED_GRACEFULLY_WOFFSET                     0x0
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_CCPLEX_CLUSTER1_FIQ_EXITED_GRACEFULLY_DEFAULT                     MK_MASK_CONST(0x0)
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_CCPLEX_CLUSTER1_FIQ_EXITED_GRACEFULLY_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_CCPLEX_CLUSTER1_FIQ_EXITED_GRACEFULLY_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_CCPLEX_CLUSTER1_FIQ_EXITED_GRACEFULLY_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_CCPLEX_CLUSTER1_FIQ_EXITED_GRACEFULLY_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_CCPLEX_CLUSTER1_FIQ_EXITED_GRACEFULLY_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

//not used by HW
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_CCPLEX_CLUSTER0_FIQ_EXITED_GRACEFULLY_SHIFT                       MK_SHIFT_CONST(13)
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_CCPLEX_CLUSTER0_FIQ_EXITED_GRACEFULLY_FIELD                       MK_FIELD_CONST(0x1, PMC_IMPL_RAMDUMP_CTL_STATUS_0_CCPLEX_CLUSTER0_FIQ_EXITED_GRACEFULLY_SHIFT)
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_CCPLEX_CLUSTER0_FIQ_EXITED_GRACEFULLY_RANGE                       13:13
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_CCPLEX_CLUSTER0_FIQ_EXITED_GRACEFULLY_MSB                 MK_SHIFT_CONST(13)
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_CCPLEX_CLUSTER0_FIQ_EXITED_GRACEFULLY_LSB                 MK_SHIFT_CONST(13)
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_CCPLEX_CLUSTER0_FIQ_EXITED_GRACEFULLY_WOFFSET                     0x0
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_CCPLEX_CLUSTER0_FIQ_EXITED_GRACEFULLY_DEFAULT                     MK_MASK_CONST(0x0)
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_CCPLEX_CLUSTER0_FIQ_EXITED_GRACEFULLY_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_CCPLEX_CLUSTER0_FIQ_EXITED_GRACEFULLY_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_CCPLEX_CLUSTER0_FIQ_EXITED_GRACEFULLY_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_CCPLEX_CLUSTER0_FIQ_EXITED_GRACEFULLY_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_CCPLEX_CLUSTER0_FIQ_EXITED_GRACEFULLY_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

//CYA bit
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_RAMDUMP_STATUS_6_SHIFT                    MK_SHIFT_CONST(10)
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_RAMDUMP_STATUS_6_FIELD                    MK_FIELD_CONST(0x1, PMC_IMPL_RAMDUMP_CTL_STATUS_0_RAMDUMP_STATUS_6_SHIFT)
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_RAMDUMP_STATUS_6_RANGE                    10:10
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_RAMDUMP_STATUS_6_MSB                      MK_SHIFT_CONST(10)
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_RAMDUMP_STATUS_6_LSB                      MK_SHIFT_CONST(10)
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_RAMDUMP_STATUS_6_WOFFSET                  0x0
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_RAMDUMP_STATUS_6_DEFAULT                  MK_MASK_CONST(0x0)
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_RAMDUMP_STATUS_6_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_RAMDUMP_STATUS_6_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_RAMDUMP_STATUS_6_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_RAMDUMP_STATUS_6_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_RAMDUMP_STATUS_6_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

//DRAM could not be put in self refresh. Contents of DRAM on WDT boot may not be reliable.
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_DRAM_SELF_REFRESH_REQUEST_TIMEOUT_SHIFT                   MK_SHIFT_CONST(7)
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_DRAM_SELF_REFRESH_REQUEST_TIMEOUT_FIELD                   MK_FIELD_CONST(0x1, PMC_IMPL_RAMDUMP_CTL_STATUS_0_DRAM_SELF_REFRESH_REQUEST_TIMEOUT_SHIFT)
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_DRAM_SELF_REFRESH_REQUEST_TIMEOUT_RANGE                   7:7
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_DRAM_SELF_REFRESH_REQUEST_TIMEOUT_MSB                     MK_SHIFT_CONST(7)
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_DRAM_SELF_REFRESH_REQUEST_TIMEOUT_LSB                     MK_SHIFT_CONST(7)
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_DRAM_SELF_REFRESH_REQUEST_TIMEOUT_WOFFSET                 0x0
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_DRAM_SELF_REFRESH_REQUEST_TIMEOUT_DEFAULT                 MK_MASK_CONST(0x0)
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_DRAM_SELF_REFRESH_REQUEST_TIMEOUT_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_DRAM_SELF_REFRESH_REQUEST_TIMEOUT_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_DRAM_SELF_REFRESH_REQUEST_TIMEOUT_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_DRAM_SELF_REFRESH_REQUEST_TIMEOUT_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_DRAM_SELF_REFRESH_REQUEST_TIMEOUT_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

//MC was able to successfully put DRAM into Self Refresh.  Contents of DRAM on WDT boot are reliable
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_DRAM_IN_SELF_REFRESH_SHIFT                        MK_SHIFT_CONST(6)
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_DRAM_IN_SELF_REFRESH_FIELD                        MK_FIELD_CONST(0x1, PMC_IMPL_RAMDUMP_CTL_STATUS_0_DRAM_IN_SELF_REFRESH_SHIFT)
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_DRAM_IN_SELF_REFRESH_RANGE                        6:6
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_DRAM_IN_SELF_REFRESH_MSB                  MK_SHIFT_CONST(6)
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_DRAM_IN_SELF_REFRESH_LSB                  MK_SHIFT_CONST(6)
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_DRAM_IN_SELF_REFRESH_WOFFSET                      0x0
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_DRAM_IN_SELF_REFRESH_DEFAULT                      MK_MASK_CONST(0x0)
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_DRAM_IN_SELF_REFRESH_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_DRAM_IN_SELF_REFRESH_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_DRAM_IN_SELF_REFRESH_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_DRAM_IN_SELF_REFRESH_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_DRAM_IN_SELF_REFRESH_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

//CCPLEX cache flush failed. DRAM does not have CCPLEX caches flushed.
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_CCPLEX_CACHEFLUSH_REQUEST_TIMEOUT_SHIFT                   MK_SHIFT_CONST(5)
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_CCPLEX_CACHEFLUSH_REQUEST_TIMEOUT_FIELD                   MK_FIELD_CONST(0x1, PMC_IMPL_RAMDUMP_CTL_STATUS_0_CCPLEX_CACHEFLUSH_REQUEST_TIMEOUT_SHIFT)
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_CCPLEX_CACHEFLUSH_REQUEST_TIMEOUT_RANGE                   5:5
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_CCPLEX_CACHEFLUSH_REQUEST_TIMEOUT_MSB                     MK_SHIFT_CONST(5)
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_CCPLEX_CACHEFLUSH_REQUEST_TIMEOUT_LSB                     MK_SHIFT_CONST(5)
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_CCPLEX_CACHEFLUSH_REQUEST_TIMEOUT_WOFFSET                 0x0
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_CCPLEX_CACHEFLUSH_REQUEST_TIMEOUT_DEFAULT                 MK_MASK_CONST(0x0)
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_CCPLEX_CACHEFLUSH_REQUEST_TIMEOUT_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_CCPLEX_CACHEFLUSH_REQUEST_TIMEOUT_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_CCPLEX_CACHEFLUSH_REQUEST_TIMEOUT_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_CCPLEX_CACHEFLUSH_REQUEST_TIMEOUT_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_CCPLEX_CACHEFLUSH_REQUEST_TIMEOUT_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

//CCPLEX cache flush successful. DRAM has latest data
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_CCPLEX_CACHEFLUSH_DONE_SHIFT                      MK_SHIFT_CONST(4)
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_CCPLEX_CACHEFLUSH_DONE_FIELD                      MK_FIELD_CONST(0x1, PMC_IMPL_RAMDUMP_CTL_STATUS_0_CCPLEX_CACHEFLUSH_DONE_SHIFT)
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_CCPLEX_CACHEFLUSH_DONE_RANGE                      4:4
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_CCPLEX_CACHEFLUSH_DONE_MSB                        MK_SHIFT_CONST(4)
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_CCPLEX_CACHEFLUSH_DONE_LSB                        MK_SHIFT_CONST(4)
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_CCPLEX_CACHEFLUSH_DONE_WOFFSET                    0x0
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_CCPLEX_CACHEFLUSH_DONE_DEFAULT                    MK_MASK_CONST(0x0)
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_CCPLEX_CACHEFLUSH_DONE_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_CCPLEX_CACHEFLUSH_DONE_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_CCPLEX_CACHEFLUSH_DONE_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_CCPLEX_CACHEFLUSH_DONE_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_CCPLEX_CACHEFLUSH_DONE_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_WDT_DFD_RST_ACK_SHIFT                     MK_SHIFT_CONST(3)
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_WDT_DFD_RST_ACK_FIELD                     MK_FIELD_CONST(0x1, PMC_IMPL_RAMDUMP_CTL_STATUS_0_WDT_DFD_RST_ACK_SHIFT)
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_WDT_DFD_RST_ACK_RANGE                     3:3
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_WDT_DFD_RST_ACK_MSB                       MK_SHIFT_CONST(3)
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_WDT_DFD_RST_ACK_LSB                       MK_SHIFT_CONST(3)
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_WDT_DFD_RST_ACK_WOFFSET                   0x0
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_WDT_DFD_RST_ACK_DEFAULT                   MK_MASK_CONST(0x0)
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_WDT_DFD_RST_ACK_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_WDT_DFD_RST_ACK_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_WDT_DFD_RST_ACK_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_WDT_DFD_RST_ACK_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_WDT_DFD_RST_ACK_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_WDT_DFD_RST_REQ_SHIFT                     MK_SHIFT_CONST(2)
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_WDT_DFD_RST_REQ_FIELD                     MK_FIELD_CONST(0x1, PMC_IMPL_RAMDUMP_CTL_STATUS_0_WDT_DFD_RST_REQ_SHIFT)
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_WDT_DFD_RST_REQ_RANGE                     2:2
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_WDT_DFD_RST_REQ_MSB                       MK_SHIFT_CONST(2)
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_WDT_DFD_RST_REQ_LSB                       MK_SHIFT_CONST(2)
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_WDT_DFD_RST_REQ_WOFFSET                   0x0
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_WDT_DFD_RST_REQ_DEFAULT                   MK_MASK_CONST(0x0)
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_WDT_DFD_RST_REQ_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_WDT_DFD_RST_REQ_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_WDT_DFD_RST_REQ_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_WDT_DFD_RST_REQ_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_WDT_DFD_RST_REQ_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

//Not connected in Parker. Reserved for Future use
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_CCPLEX_CACHE_RSTDISABLE_SHIFT                     MK_SHIFT_CONST(1)
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_CCPLEX_CACHE_RSTDISABLE_FIELD                     MK_FIELD_CONST(0x1, PMC_IMPL_RAMDUMP_CTL_STATUS_0_CCPLEX_CACHE_RSTDISABLE_SHIFT)
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_CCPLEX_CACHE_RSTDISABLE_RANGE                     1:1
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_CCPLEX_CACHE_RSTDISABLE_MSB                       MK_SHIFT_CONST(1)
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_CCPLEX_CACHE_RSTDISABLE_LSB                       MK_SHIFT_CONST(1)
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_CCPLEX_CACHE_RSTDISABLE_WOFFSET                   0x0
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_CCPLEX_CACHE_RSTDISABLE_DEFAULT                   MK_MASK_CONST(0x0)
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_CCPLEX_CACHE_RSTDISABLE_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_CCPLEX_CACHE_RSTDISABLE_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_CCPLEX_CACHE_RSTDISABLE_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_CCPLEX_CACHE_RSTDISABLE_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_CCPLEX_CACHE_RSTDISABLE_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

//Defunc. Please check RAMDUMP_CTL_STATUS2 or 2594099
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_RAMDUMP_EN_SHIFT                  MK_SHIFT_CONST(0)
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_RAMDUMP_EN_FIELD                  MK_FIELD_CONST(0x1, PMC_IMPL_RAMDUMP_CTL_STATUS_0_RAMDUMP_EN_SHIFT)
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_RAMDUMP_EN_RANGE                  0:0
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_RAMDUMP_EN_MSB                    MK_SHIFT_CONST(0)
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_RAMDUMP_EN_LSB                    MK_SHIFT_CONST(0)
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_RAMDUMP_EN_WOFFSET                        0x0
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_RAMDUMP_EN_DEFAULT                        MK_MASK_CONST(0x0)
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_RAMDUMP_EN_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_RAMDUMP_EN_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_RAMDUMP_EN_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_RAMDUMP_EN_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_RAMDUMP_EN_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)


// Reserved address 0x110
// For the RST_REQ_CONFIG and RST_REQ_CNTVAL registers - the configuration variables for each reset level are reset using
// a reset one level lower
// Example:
// L1a configurations knobs are reset using L0  cold register
// L1b configurations knobs are reset using L1a cold register
// L1c configurations knobs are reset using L1b cold register
// L2  configurations knobs are reset using L1c cold register
// Bug 1600231 - WDT_OUT_RST_EN fields that enable WDT_RESET_OUT - should NOT be written by SW. It is supposed to be set only in bootcode.

// Register PMC_IMPL_RST_REQ_CONFIG_0
#define PMC_IMPL_RST_REQ_CONFIG_0                       MK_ADDR_CONST(0x114)
#define PMC_IMPL_RST_REQ_CONFIG_0_SECURE                        0x0
#define PMC_IMPL_RST_REQ_CONFIG_0_DUAL                  0x0
#define PMC_IMPL_RST_REQ_CONFIG_0_SCR                   CNTRL_SCR_0
#define PMC_IMPL_RST_REQ_CONFIG_0_SCRREG                        PMC_IMPL_SCR_CNTRL_SCR_0
#define PMC_IMPL_RST_REQ_CONFIG_0_WORD_COUNT                    0x1
#define PMC_IMPL_RST_REQ_CONFIG_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define PMC_IMPL_RST_REQ_CONFIG_0_RESET_MASK                    MK_MASK_CONST(0xb)
#define PMC_IMPL_RST_REQ_CONFIG_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define PMC_IMPL_RST_REQ_CONFIG_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define PMC_IMPL_RST_REQ_CONFIG_0_READ_MASK                     MK_MASK_CONST(0xb)
#define PMC_IMPL_RST_REQ_CONFIG_0_WRITE_MASK                    MK_MASK_CONST(0xb)
//Enables Sideband WDT_RESET_OUT for WDT usecases.
//Should only be used with PMIC that support RESET_IN
#define PMC_IMPL_RST_REQ_CONFIG_0_L1BWDTRST_WDT_OUT_RST_EN_SHIFT                        MK_SHIFT_CONST(0)
#define PMC_IMPL_RST_REQ_CONFIG_0_L1BWDTRST_WDT_OUT_RST_EN_FIELD                        MK_FIELD_CONST(0x1, PMC_IMPL_RST_REQ_CONFIG_0_L1BWDTRST_WDT_OUT_RST_EN_SHIFT)
#define PMC_IMPL_RST_REQ_CONFIG_0_L1BWDTRST_WDT_OUT_RST_EN_RANGE                        0:0
#define PMC_IMPL_RST_REQ_CONFIG_0_L1BWDTRST_WDT_OUT_RST_EN_MSB                  MK_SHIFT_CONST(0)
#define PMC_IMPL_RST_REQ_CONFIG_0_L1BWDTRST_WDT_OUT_RST_EN_LSB                  MK_SHIFT_CONST(0)
#define PMC_IMPL_RST_REQ_CONFIG_0_L1BWDTRST_WDT_OUT_RST_EN_WOFFSET                      0x0
#define PMC_IMPL_RST_REQ_CONFIG_0_L1BWDTRST_WDT_OUT_RST_EN_DEFAULT                      MK_MASK_CONST(0x0)
#define PMC_IMPL_RST_REQ_CONFIG_0_L1BWDTRST_WDT_OUT_RST_EN_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define PMC_IMPL_RST_REQ_CONFIG_0_L1BWDTRST_WDT_OUT_RST_EN_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define PMC_IMPL_RST_REQ_CONFIG_0_L1BWDTRST_WDT_OUT_RST_EN_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define PMC_IMPL_RST_REQ_CONFIG_0_L1BWDTRST_WDT_OUT_RST_EN_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define PMC_IMPL_RST_REQ_CONFIG_0_L1BWDTRST_WDT_OUT_RST_EN_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define PMC_IMPL_RST_REQ_CONFIG_0_L1BWDTRST_WDT_OUT_RST_EN_INIT_ENUM                    DISABLE
#define PMC_IMPL_RST_REQ_CONFIG_0_L1BWDTRST_WDT_OUT_RST_EN_DISABLE                      MK_ENUM_CONST(0)
#define PMC_IMPL_RST_REQ_CONFIG_0_L1BWDTRST_WDT_OUT_RST_EN_ENABLE                       MK_ENUM_CONST(1)

//Enables Sideband WDT_RESET_OUT for AOWDT usecases.
//Should only be used with PMIC that support RESET_IN
#define PMC_IMPL_RST_REQ_CONFIG_0_L1BAOWDTRST_WDT_OUT_RST_EN_SHIFT                      MK_SHIFT_CONST(1)
#define PMC_IMPL_RST_REQ_CONFIG_0_L1BAOWDTRST_WDT_OUT_RST_EN_FIELD                      MK_FIELD_CONST(0x1, PMC_IMPL_RST_REQ_CONFIG_0_L1BAOWDTRST_WDT_OUT_RST_EN_SHIFT)
#define PMC_IMPL_RST_REQ_CONFIG_0_L1BAOWDTRST_WDT_OUT_RST_EN_RANGE                      1:1
#define PMC_IMPL_RST_REQ_CONFIG_0_L1BAOWDTRST_WDT_OUT_RST_EN_MSB                        MK_SHIFT_CONST(1)
#define PMC_IMPL_RST_REQ_CONFIG_0_L1BAOWDTRST_WDT_OUT_RST_EN_LSB                        MK_SHIFT_CONST(1)
#define PMC_IMPL_RST_REQ_CONFIG_0_L1BAOWDTRST_WDT_OUT_RST_EN_WOFFSET                    0x0
#define PMC_IMPL_RST_REQ_CONFIG_0_L1BAOWDTRST_WDT_OUT_RST_EN_DEFAULT                    MK_MASK_CONST(0x0)
#define PMC_IMPL_RST_REQ_CONFIG_0_L1BAOWDTRST_WDT_OUT_RST_EN_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define PMC_IMPL_RST_REQ_CONFIG_0_L1BAOWDTRST_WDT_OUT_RST_EN_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define PMC_IMPL_RST_REQ_CONFIG_0_L1BAOWDTRST_WDT_OUT_RST_EN_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define PMC_IMPL_RST_REQ_CONFIG_0_L1BAOWDTRST_WDT_OUT_RST_EN_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define PMC_IMPL_RST_REQ_CONFIG_0_L1BAOWDTRST_WDT_OUT_RST_EN_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define PMC_IMPL_RST_REQ_CONFIG_0_L1BAOWDTRST_WDT_OUT_RST_EN_INIT_ENUM                  DISABLE
#define PMC_IMPL_RST_REQ_CONFIG_0_L1BAOWDTRST_WDT_OUT_RST_EN_DISABLE                    MK_ENUM_CONST(0)
#define PMC_IMPL_RST_REQ_CONFIG_0_L1BAOWDTRST_WDT_OUT_RST_EN_ENABLE                     MK_ENUM_CONST(1)

//Enables Sideband WDT_RESET_OUT for SW  resetcases.
//Should only be used with PMIC that support RESET_IN
#define PMC_IMPL_RST_REQ_CONFIG_0_L1CRST_WDT_OUT_RST_EN_SHIFT                   MK_SHIFT_CONST(3)
#define PMC_IMPL_RST_REQ_CONFIG_0_L1CRST_WDT_OUT_RST_EN_FIELD                   MK_FIELD_CONST(0x1, PMC_IMPL_RST_REQ_CONFIG_0_L1CRST_WDT_OUT_RST_EN_SHIFT)
#define PMC_IMPL_RST_REQ_CONFIG_0_L1CRST_WDT_OUT_RST_EN_RANGE                   3:3
#define PMC_IMPL_RST_REQ_CONFIG_0_L1CRST_WDT_OUT_RST_EN_MSB                     MK_SHIFT_CONST(3)
#define PMC_IMPL_RST_REQ_CONFIG_0_L1CRST_WDT_OUT_RST_EN_LSB                     MK_SHIFT_CONST(3)
#define PMC_IMPL_RST_REQ_CONFIG_0_L1CRST_WDT_OUT_RST_EN_WOFFSET                 0x0
#define PMC_IMPL_RST_REQ_CONFIG_0_L1CRST_WDT_OUT_RST_EN_DEFAULT                 MK_MASK_CONST(0x0)
#define PMC_IMPL_RST_REQ_CONFIG_0_L1CRST_WDT_OUT_RST_EN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define PMC_IMPL_RST_REQ_CONFIG_0_L1CRST_WDT_OUT_RST_EN_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define PMC_IMPL_RST_REQ_CONFIG_0_L1CRST_WDT_OUT_RST_EN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define PMC_IMPL_RST_REQ_CONFIG_0_L1CRST_WDT_OUT_RST_EN_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define PMC_IMPL_RST_REQ_CONFIG_0_L1CRST_WDT_OUT_RST_EN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define PMC_IMPL_RST_REQ_CONFIG_0_L1CRST_WDT_OUT_RST_EN_INIT_ENUM                       DISABLE
#define PMC_IMPL_RST_REQ_CONFIG_0_L1CRST_WDT_OUT_RST_EN_DISABLE                 MK_ENUM_CONST(0)
#define PMC_IMPL_RST_REQ_CONFIG_0_L1CRST_WDT_OUT_RST_EN_ENABLE                  MK_ENUM_CONST(1)

//Reset level:one reset level lower than the reset it generates

// Register PMC_IMPL_RST_REQ_CNTVAL_0
#define PMC_IMPL_RST_REQ_CNTVAL_0                       MK_ADDR_CONST(0x118)
#define PMC_IMPL_RST_REQ_CNTVAL_0_SECURE                        0x0
#define PMC_IMPL_RST_REQ_CNTVAL_0_DUAL                  0x0
#define PMC_IMPL_RST_REQ_CNTVAL_0_SCR                   CNTRL_SCR_0
#define PMC_IMPL_RST_REQ_CNTVAL_0_SCRREG                        PMC_IMPL_SCR_CNTRL_SCR_0
#define PMC_IMPL_RST_REQ_CNTVAL_0_WORD_COUNT                    0x1
#define PMC_IMPL_RST_REQ_CNTVAL_0_RESET_VAL                     MK_MASK_CONST(0x4000000)
#define PMC_IMPL_RST_REQ_CNTVAL_0_RESET_MASK                    MK_MASK_CONST(0xffffffff)
#define PMC_IMPL_RST_REQ_CNTVAL_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define PMC_IMPL_RST_REQ_CNTVAL_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define PMC_IMPL_RST_REQ_CNTVAL_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
#define PMC_IMPL_RST_REQ_CNTVAL_0_WRITE_MASK                    MK_MASK_CONST(0xffffffff)
//Number of pmc_clk (32K) cycles before L1a reset deassertion
#define PMC_IMPL_RST_REQ_CNTVAL_0_L1ARST_SHIFT                  MK_SHIFT_CONST(0)
#define PMC_IMPL_RST_REQ_CNTVAL_0_L1ARST_FIELD                  MK_FIELD_CONST(0xff, PMC_IMPL_RST_REQ_CNTVAL_0_L1ARST_SHIFT)
#define PMC_IMPL_RST_REQ_CNTVAL_0_L1ARST_RANGE                  7:0
#define PMC_IMPL_RST_REQ_CNTVAL_0_L1ARST_MSB                    MK_SHIFT_CONST(7)
#define PMC_IMPL_RST_REQ_CNTVAL_0_L1ARST_LSB                    MK_SHIFT_CONST(0)
#define PMC_IMPL_RST_REQ_CNTVAL_0_L1ARST_WOFFSET                        0x0
#define PMC_IMPL_RST_REQ_CNTVAL_0_L1ARST_DEFAULT                        MK_MASK_CONST(0x0)
#define PMC_IMPL_RST_REQ_CNTVAL_0_L1ARST_DEFAULT_MASK                   MK_MASK_CONST(0xff)
#define PMC_IMPL_RST_REQ_CNTVAL_0_L1ARST_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define PMC_IMPL_RST_REQ_CNTVAL_0_L1ARST_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define PMC_IMPL_RST_REQ_CNTVAL_0_L1ARST_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define PMC_IMPL_RST_REQ_CNTVAL_0_L1ARST_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

//IST/BOOT SW should make sure that the value is more than 4 before enterting into IST. Number of pmc_clk (32K) cycles before L1b reset deassertion
#define PMC_IMPL_RST_REQ_CNTVAL_0_L1BRST_SHIFT                  MK_SHIFT_CONST(8)
#define PMC_IMPL_RST_REQ_CNTVAL_0_L1BRST_FIELD                  MK_FIELD_CONST(0xff, PMC_IMPL_RST_REQ_CNTVAL_0_L1BRST_SHIFT)
#define PMC_IMPL_RST_REQ_CNTVAL_0_L1BRST_RANGE                  15:8
#define PMC_IMPL_RST_REQ_CNTVAL_0_L1BRST_MSB                    MK_SHIFT_CONST(15)
#define PMC_IMPL_RST_REQ_CNTVAL_0_L1BRST_LSB                    MK_SHIFT_CONST(8)
#define PMC_IMPL_RST_REQ_CNTVAL_0_L1BRST_WOFFSET                        0x0
#define PMC_IMPL_RST_REQ_CNTVAL_0_L1BRST_DEFAULT                        MK_MASK_CONST(0x0)
#define PMC_IMPL_RST_REQ_CNTVAL_0_L1BRST_DEFAULT_MASK                   MK_MASK_CONST(0xff)
#define PMC_IMPL_RST_REQ_CNTVAL_0_L1BRST_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define PMC_IMPL_RST_REQ_CNTVAL_0_L1BRST_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define PMC_IMPL_RST_REQ_CNTVAL_0_L1BRST_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define PMC_IMPL_RST_REQ_CNTVAL_0_L1BRST_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

//IST/BOOT SW should make sure that the value is more than 4 before enterting into IST. Number of pmc_clk (32K) cycles before L1c reset deassertion
#define PMC_IMPL_RST_REQ_CNTVAL_0_L1CRST_SHIFT                  MK_SHIFT_CONST(16)
#define PMC_IMPL_RST_REQ_CNTVAL_0_L1CRST_FIELD                  MK_FIELD_CONST(0xff, PMC_IMPL_RST_REQ_CNTVAL_0_L1CRST_SHIFT)
#define PMC_IMPL_RST_REQ_CNTVAL_0_L1CRST_RANGE                  23:16
#define PMC_IMPL_RST_REQ_CNTVAL_0_L1CRST_MSB                    MK_SHIFT_CONST(23)
#define PMC_IMPL_RST_REQ_CNTVAL_0_L1CRST_LSB                    MK_SHIFT_CONST(16)
#define PMC_IMPL_RST_REQ_CNTVAL_0_L1CRST_WOFFSET                        0x0
#define PMC_IMPL_RST_REQ_CNTVAL_0_L1CRST_DEFAULT                        MK_MASK_CONST(0x0)
#define PMC_IMPL_RST_REQ_CNTVAL_0_L1CRST_DEFAULT_MASK                   MK_MASK_CONST(0xff)
#define PMC_IMPL_RST_REQ_CNTVAL_0_L1CRST_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define PMC_IMPL_RST_REQ_CNTVAL_0_L1CRST_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define PMC_IMPL_RST_REQ_CNTVAL_0_L1CRST_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define PMC_IMPL_RST_REQ_CNTVAL_0_L1CRST_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

//IST/BOOT SW should make sure that the value is more than 4 before enterting into IST. Number of pmc_clk (32K) cycles before L2  reset deassertion
#define PMC_IMPL_RST_REQ_CNTVAL_0_L2RST_SHIFT                   MK_SHIFT_CONST(24)
#define PMC_IMPL_RST_REQ_CNTVAL_0_L2RST_FIELD                   MK_FIELD_CONST(0xff, PMC_IMPL_RST_REQ_CNTVAL_0_L2RST_SHIFT)
#define PMC_IMPL_RST_REQ_CNTVAL_0_L2RST_RANGE                   31:24
#define PMC_IMPL_RST_REQ_CNTVAL_0_L2RST_MSB                     MK_SHIFT_CONST(31)
#define PMC_IMPL_RST_REQ_CNTVAL_0_L2RST_LSB                     MK_SHIFT_CONST(24)
#define PMC_IMPL_RST_REQ_CNTVAL_0_L2RST_WOFFSET                 0x0
#define PMC_IMPL_RST_REQ_CNTVAL_0_L2RST_DEFAULT                 MK_MASK_CONST(0x4)
#define PMC_IMPL_RST_REQ_CNTVAL_0_L2RST_DEFAULT_MASK                    MK_MASK_CONST(0xff)
#define PMC_IMPL_RST_REQ_CNTVAL_0_L2RST_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define PMC_IMPL_RST_REQ_CNTVAL_0_L2RST_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define PMC_IMPL_RST_REQ_CNTVAL_0_L2RST_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define PMC_IMPL_RST_REQ_CNTVAL_0_L2RST_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

//Removed following register as part of bug 200117927 cleanup

// Reserved address 0x11c
//DDR_CNTRL

// Reserved address 0x120
//DDR_CNTRL_MEM1
// --------------------------------------------------------------------------
//
// Copyright (c) 2004, NVIDIA Corp.
// All Rights Reserved.
//
// This is UNPUBLISHED PROPRIETARY SOURCE CODE of NVIDIA Corp.;
// the contents of this file may not be disclosed to third parties, copied or
// duplicated in any form, in whole or in part, without the prior written
// permission of NVIDIA Corp.
//
// RESTRICTED RIGHTS LEGEND:
// Use, duplication or disclosure by the Government is subject to restrictions
// as set forth in subdivision (c)(1)(ii) of the Rights in Technical Data
// and Computer Software clause at DFARS 252.227-7013, and/or in similar or
// successor clauses in the FAR, DOD or NASA FAR Supplement. Unpublished -
// rights reserved under the Copyright Laws of the United States.
//
// --------------------------------------------------------------------------
//
// This space is reserved for BBC registers. BBC registers are always at offset 32'h500

// Reserved address 0x124

// Reserved address 0x128

// Reserved address 0x12c

// Reserved address 0x130

// Reserved address 0x134

// Reserved address 0x138

// Reserved address 0x13c

// Reserved address 0x140

// Reserved address 0x144

// Reserved address 0x148

// Reserved address 0x14c

// Reserved address 0x150

// Reserved address 0x154

// Reserved address 0x158

// Reserved address 0x15c

// Reserved address 0x160

// Reserved address 0x164

// Reserved address 0x168

// Reserved address 0x16c

// Reserved address 0x170

// Reserved address 0x174

// Reserved address 0x178

// Reserved address 0x17c

// Reserved address 0x180

// Reserved address 0x184

// Reserved address 0x188

// Reserved address 0x18c

// Reserved address 0x190

// Reserved address 0x194

// Reserved address 0x198

// Reserved address 0x19c

// Reserved address 0x1a0

// Reserved address 0x1a4

// Reserved address 0x1a8

// Reserved address 0x1ac

// Reserved address 0x1b0

// Reserved address 0x1b4

// Reserved address 0x1b8

// Reserved address 0x1bc

// Reserved address 0x1c0

// Reserved address 0x1c4

// Reserved address 0x1c8

// Reserved address 0x1cc

// Reserved address 0x1d0

// Reserved address 0x1d4

// Reserved address 0x1d8

// Reserved address 0x1dc

// Reserved address 0x1e0
// VFMON_CONFIG

// Reserved address 0x1e4
// VFMON_OSC_TIMING

// Reserved address 0x1e8
// VFMON_CLK32_THRESHOLD

// Reserved address 0x1ec

// Reserved address 0x1f0

// Reserved address 0x1f4

// Reserved address 0x1f8

// Reserved address 0x1fc

// Reserved address 0x200

// Reserved address 0x204

// Register PMC_IMPL_PART_AUD_POWER_GATE_CONTROL_0
#define PMC_IMPL_PART_AUD_POWER_GATE_CONTROL_0                  MK_ADDR_CONST(0x208)
#define PMC_IMPL_PART_AUD_POWER_GATE_CONTROL_0_SECURE                   0x0
#define PMC_IMPL_PART_AUD_POWER_GATE_CONTROL_0_DUAL                     0x0
#define PMC_IMPL_PART_AUD_POWER_GATE_CONTROL_0_SCR                      PG_AUD_SCR_0
#define PMC_IMPL_PART_AUD_POWER_GATE_CONTROL_0_SCRREG                   PMC_IMPL_SCR_PG_AUD_SCR_0
#define PMC_IMPL_PART_AUD_POWER_GATE_CONTROL_0_WORD_COUNT                       0x1
#define PMC_IMPL_PART_AUD_POWER_GATE_CONTROL_0_RESET_VAL                        MK_MASK_CONST(0x80000005)
#define PMC_IMPL_PART_AUD_POWER_GATE_CONTROL_0_RESET_MASK                       MK_MASK_CONST(0x80000107)
#define PMC_IMPL_PART_AUD_POWER_GATE_CONTROL_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AUD_POWER_GATE_CONTROL_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AUD_POWER_GATE_CONTROL_0_READ_MASK                        MK_MASK_CONST(0x80000107)
#define PMC_IMPL_PART_AUD_POWER_GATE_CONTROL_0_WRITE_MASK                       MK_MASK_CONST(0x80000105)
#define PMC_IMPL_PART_AUD_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SHIFT                        MK_SHIFT_CONST(31)
#define PMC_IMPL_PART_AUD_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_FIELD                        MK_FIELD_CONST(0x1, PMC_IMPL_PART_AUD_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SHIFT)
#define PMC_IMPL_PART_AUD_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_RANGE                        31:31
#define PMC_IMPL_PART_AUD_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_MSB                  MK_SHIFT_CONST(31)
#define PMC_IMPL_PART_AUD_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_LSB                  MK_SHIFT_CONST(31)
#define PMC_IMPL_PART_AUD_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_WOFFSET                      0x0
#define PMC_IMPL_PART_AUD_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_DEFAULT                      MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AUD_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AUD_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AUD_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AUD_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AUD_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AUD_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_INIT_ENUM                    ENABLE
#define PMC_IMPL_PART_AUD_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_DISABLE                      MK_ENUM_CONST(0)
#define PMC_IMPL_PART_AUD_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_ENABLE                       MK_ENUM_CONST(1)

#define PMC_IMPL_PART_AUD_POWER_GATE_CONTROL_0_START_SHIFT                      MK_SHIFT_CONST(8)
#define PMC_IMPL_PART_AUD_POWER_GATE_CONTROL_0_START_FIELD                      MK_FIELD_CONST(0x1, PMC_IMPL_PART_AUD_POWER_GATE_CONTROL_0_START_SHIFT)
#define PMC_IMPL_PART_AUD_POWER_GATE_CONTROL_0_START_RANGE                      8:8
#define PMC_IMPL_PART_AUD_POWER_GATE_CONTROL_0_START_MSB                        MK_SHIFT_CONST(8)
#define PMC_IMPL_PART_AUD_POWER_GATE_CONTROL_0_START_LSB                        MK_SHIFT_CONST(8)
#define PMC_IMPL_PART_AUD_POWER_GATE_CONTROL_0_START_WOFFSET                    0x0
#define PMC_IMPL_PART_AUD_POWER_GATE_CONTROL_0_START_DEFAULT                    MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AUD_POWER_GATE_CONTROL_0_START_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AUD_POWER_GATE_CONTROL_0_START_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AUD_POWER_GATE_CONTROL_0_START_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AUD_POWER_GATE_CONTROL_0_START_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AUD_POWER_GATE_CONTROL_0_START_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AUD_POWER_GATE_CONTROL_0_START_INIT_ENUM                  DONE
#define PMC_IMPL_PART_AUD_POWER_GATE_CONTROL_0_START_DONE                       MK_ENUM_CONST(0)
#define PMC_IMPL_PART_AUD_POWER_GATE_CONTROL_0_START_PENDING                    MK_ENUM_CONST(1)

#define PMC_IMPL_PART_AUD_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SHIFT                      MK_SHIFT_CONST(2)
#define PMC_IMPL_PART_AUD_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_FIELD                      MK_FIELD_CONST(0x1, PMC_IMPL_PART_AUD_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SHIFT)
#define PMC_IMPL_PART_AUD_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_RANGE                      2:2
#define PMC_IMPL_PART_AUD_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_MSB                        MK_SHIFT_CONST(2)
#define PMC_IMPL_PART_AUD_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_LSB                        MK_SHIFT_CONST(2)
#define PMC_IMPL_PART_AUD_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_WOFFSET                    0x0
#define PMC_IMPL_PART_AUD_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_DEFAULT                    MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AUD_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AUD_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AUD_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AUD_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AUD_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AUD_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_INIT_ENUM                  ON
#define PMC_IMPL_PART_AUD_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_OFF                        MK_ENUM_CONST(0)
#define PMC_IMPL_PART_AUD_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_ON                 MK_ENUM_CONST(1)

#define PMC_IMPL_PART_AUD_POWER_GATE_CONTROL_0_SRAM_RET_EN_SHIFT                        MK_SHIFT_CONST(1)
#define PMC_IMPL_PART_AUD_POWER_GATE_CONTROL_0_SRAM_RET_EN_FIELD                        MK_FIELD_CONST(0x1, PMC_IMPL_PART_AUD_POWER_GATE_CONTROL_0_SRAM_RET_EN_SHIFT)
#define PMC_IMPL_PART_AUD_POWER_GATE_CONTROL_0_SRAM_RET_EN_RANGE                        1:1
#define PMC_IMPL_PART_AUD_POWER_GATE_CONTROL_0_SRAM_RET_EN_MSB                  MK_SHIFT_CONST(1)
#define PMC_IMPL_PART_AUD_POWER_GATE_CONTROL_0_SRAM_RET_EN_LSB                  MK_SHIFT_CONST(1)
#define PMC_IMPL_PART_AUD_POWER_GATE_CONTROL_0_SRAM_RET_EN_WOFFSET                      0x0
#define PMC_IMPL_PART_AUD_POWER_GATE_CONTROL_0_SRAM_RET_EN_DEFAULT                      MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AUD_POWER_GATE_CONTROL_0_SRAM_RET_EN_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AUD_POWER_GATE_CONTROL_0_SRAM_RET_EN_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AUD_POWER_GATE_CONTROL_0_SRAM_RET_EN_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AUD_POWER_GATE_CONTROL_0_SRAM_RET_EN_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AUD_POWER_GATE_CONTROL_0_SRAM_RET_EN_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AUD_POWER_GATE_CONTROL_0_SRAM_RET_EN_INIT_ENUM                    OFF
#define PMC_IMPL_PART_AUD_POWER_GATE_CONTROL_0_SRAM_RET_EN_OFF                  MK_ENUM_CONST(0)
#define PMC_IMPL_PART_AUD_POWER_GATE_CONTROL_0_SRAM_RET_EN_ON                   MK_ENUM_CONST(1)

#define PMC_IMPL_PART_AUD_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SHIFT                        MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_AUD_POWER_GATE_CONTROL_0_LOGIC_SLEEP_FIELD                        MK_FIELD_CONST(0x1, PMC_IMPL_PART_AUD_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SHIFT)
#define PMC_IMPL_PART_AUD_POWER_GATE_CONTROL_0_LOGIC_SLEEP_RANGE                        0:0
#define PMC_IMPL_PART_AUD_POWER_GATE_CONTROL_0_LOGIC_SLEEP_MSB                  MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_AUD_POWER_GATE_CONTROL_0_LOGIC_SLEEP_LSB                  MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_AUD_POWER_GATE_CONTROL_0_LOGIC_SLEEP_WOFFSET                      0x0
#define PMC_IMPL_PART_AUD_POWER_GATE_CONTROL_0_LOGIC_SLEEP_DEFAULT                      MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AUD_POWER_GATE_CONTROL_0_LOGIC_SLEEP_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AUD_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AUD_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AUD_POWER_GATE_CONTROL_0_LOGIC_SLEEP_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AUD_POWER_GATE_CONTROL_0_LOGIC_SLEEP_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AUD_POWER_GATE_CONTROL_0_LOGIC_SLEEP_INIT_ENUM                    ON
#define PMC_IMPL_PART_AUD_POWER_GATE_CONTROL_0_LOGIC_SLEEP_OFF                  MK_ENUM_CONST(0)
#define PMC_IMPL_PART_AUD_POWER_GATE_CONTROL_0_LOGIC_SLEEP_ON                   MK_ENUM_CONST(1)


// Register PMC_IMPL_PART_AUD_POWER_GATE_STATUS_0
#define PMC_IMPL_PART_AUD_POWER_GATE_STATUS_0                   MK_ADDR_CONST(0x20c)
#define PMC_IMPL_PART_AUD_POWER_GATE_STATUS_0_SECURE                    0x0
#define PMC_IMPL_PART_AUD_POWER_GATE_STATUS_0_DUAL                      0x0
#define PMC_IMPL_PART_AUD_POWER_GATE_STATUS_0_SCR                       PG_AUD_SCR_0
#define PMC_IMPL_PART_AUD_POWER_GATE_STATUS_0_SCRREG                    PMC_IMPL_SCR_PG_AUD_SCR_0
#define PMC_IMPL_PART_AUD_POWER_GATE_STATUS_0_WORD_COUNT                        0x1
#define PMC_IMPL_PART_AUD_POWER_GATE_STATUS_0_RESET_VAL                         MK_MASK_CONST(0x5)
#define PMC_IMPL_PART_AUD_POWER_GATE_STATUS_0_RESET_MASK                        MK_MASK_CONST(0x7)
#define PMC_IMPL_PART_AUD_POWER_GATE_STATUS_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AUD_POWER_GATE_STATUS_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AUD_POWER_GATE_STATUS_0_READ_MASK                         MK_MASK_CONST(0x7)
#define PMC_IMPL_PART_AUD_POWER_GATE_STATUS_0_WRITE_MASK                        MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AUD_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SHIFT                      MK_SHIFT_CONST(2)
#define PMC_IMPL_PART_AUD_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_FIELD                      MK_FIELD_CONST(0x1, PMC_IMPL_PART_AUD_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SHIFT)
#define PMC_IMPL_PART_AUD_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_RANGE                      2:2
#define PMC_IMPL_PART_AUD_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_MSB                        MK_SHIFT_CONST(2)
#define PMC_IMPL_PART_AUD_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_LSB                        MK_SHIFT_CONST(2)
#define PMC_IMPL_PART_AUD_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_WOFFSET                    0x0
#define PMC_IMPL_PART_AUD_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_DEFAULT                    MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AUD_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AUD_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AUD_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AUD_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AUD_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AUD_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_INIT_ENUM                  ON
#define PMC_IMPL_PART_AUD_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_OFF                        MK_ENUM_CONST(0)
#define PMC_IMPL_PART_AUD_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_ON                 MK_ENUM_CONST(1)

#define PMC_IMPL_PART_AUD_POWER_GATE_STATUS_0_SRAM_RET_STS_SHIFT                        MK_SHIFT_CONST(1)
#define PMC_IMPL_PART_AUD_POWER_GATE_STATUS_0_SRAM_RET_STS_FIELD                        MK_FIELD_CONST(0x1, PMC_IMPL_PART_AUD_POWER_GATE_STATUS_0_SRAM_RET_STS_SHIFT)
#define PMC_IMPL_PART_AUD_POWER_GATE_STATUS_0_SRAM_RET_STS_RANGE                        1:1
#define PMC_IMPL_PART_AUD_POWER_GATE_STATUS_0_SRAM_RET_STS_MSB                  MK_SHIFT_CONST(1)
#define PMC_IMPL_PART_AUD_POWER_GATE_STATUS_0_SRAM_RET_STS_LSB                  MK_SHIFT_CONST(1)
#define PMC_IMPL_PART_AUD_POWER_GATE_STATUS_0_SRAM_RET_STS_WOFFSET                      0x0
#define PMC_IMPL_PART_AUD_POWER_GATE_STATUS_0_SRAM_RET_STS_DEFAULT                      MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AUD_POWER_GATE_STATUS_0_SRAM_RET_STS_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AUD_POWER_GATE_STATUS_0_SRAM_RET_STS_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AUD_POWER_GATE_STATUS_0_SRAM_RET_STS_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AUD_POWER_GATE_STATUS_0_SRAM_RET_STS_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AUD_POWER_GATE_STATUS_0_SRAM_RET_STS_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AUD_POWER_GATE_STATUS_0_SRAM_RET_STS_INIT_ENUM                    OFF
#define PMC_IMPL_PART_AUD_POWER_GATE_STATUS_0_SRAM_RET_STS_OFF                  MK_ENUM_CONST(0)
#define PMC_IMPL_PART_AUD_POWER_GATE_STATUS_0_SRAM_RET_STS_ON                   MK_ENUM_CONST(1)

#define PMC_IMPL_PART_AUD_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SHIFT                     MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_AUD_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_FIELD                     MK_FIELD_CONST(0x1, PMC_IMPL_PART_AUD_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SHIFT)
#define PMC_IMPL_PART_AUD_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_RANGE                     0:0
#define PMC_IMPL_PART_AUD_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_MSB                       MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_AUD_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_LSB                       MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_AUD_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_WOFFSET                   0x0
#define PMC_IMPL_PART_AUD_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_DEFAULT                   MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AUD_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AUD_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AUD_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AUD_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AUD_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AUD_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_INIT_ENUM                 ON
#define PMC_IMPL_PART_AUD_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_OFF                       MK_ENUM_CONST(0)
#define PMC_IMPL_PART_AUD_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_ON                        MK_ENUM_CONST(1)


// Register PMC_IMPL_PART_AUD_CLAMP_CONTROL_0
#define PMC_IMPL_PART_AUD_CLAMP_CONTROL_0                       MK_ADDR_CONST(0x210)
#define PMC_IMPL_PART_AUD_CLAMP_CONTROL_0_SECURE                        0x0
#define PMC_IMPL_PART_AUD_CLAMP_CONTROL_0_DUAL                  0x0
#define PMC_IMPL_PART_AUD_CLAMP_CONTROL_0_SCR                   PG_AUD_SCR_0
#define PMC_IMPL_PART_AUD_CLAMP_CONTROL_0_SCRREG                        PMC_IMPL_SCR_PG_AUD_SCR_0
#define PMC_IMPL_PART_AUD_CLAMP_CONTROL_0_WORD_COUNT                    0x1
#define PMC_IMPL_PART_AUD_CLAMP_CONTROL_0_RESET_VAL                     MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AUD_CLAMP_CONTROL_0_RESET_MASK                    MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AUD_CLAMP_CONTROL_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AUD_CLAMP_CONTROL_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AUD_CLAMP_CONTROL_0_READ_MASK                     MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AUD_CLAMP_CONTROL_0_WRITE_MASK                    MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AUD_CLAMP_CONTROL_0_CLAMP_SHIFT                   MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_AUD_CLAMP_CONTROL_0_CLAMP_FIELD                   MK_FIELD_CONST(0x1, PMC_IMPL_PART_AUD_CLAMP_CONTROL_0_CLAMP_SHIFT)
#define PMC_IMPL_PART_AUD_CLAMP_CONTROL_0_CLAMP_RANGE                   0:0
#define PMC_IMPL_PART_AUD_CLAMP_CONTROL_0_CLAMP_MSB                     MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_AUD_CLAMP_CONTROL_0_CLAMP_LSB                     MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_AUD_CLAMP_CONTROL_0_CLAMP_WOFFSET                 0x0
#define PMC_IMPL_PART_AUD_CLAMP_CONTROL_0_CLAMP_DEFAULT                 MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AUD_CLAMP_CONTROL_0_CLAMP_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AUD_CLAMP_CONTROL_0_CLAMP_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AUD_CLAMP_CONTROL_0_CLAMP_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AUD_CLAMP_CONTROL_0_CLAMP_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AUD_CLAMP_CONTROL_0_CLAMP_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AUD_CLAMP_CONTROL_0_CLAMP_INIT_ENUM                       ON
#define PMC_IMPL_PART_AUD_CLAMP_CONTROL_0_CLAMP_OFF                     MK_ENUM_CONST(0)
#define PMC_IMPL_PART_AUD_CLAMP_CONTROL_0_CLAMP_ON                      MK_ENUM_CONST(1)


// Reserved address 0x214

// Reserved address 0x218

// Reserved address 0x21c

// Register PMC_IMPL_PART_DISP_POWER_GATE_CONTROL_0
#define PMC_IMPL_PART_DISP_POWER_GATE_CONTROL_0                 MK_ADDR_CONST(0x220)
#define PMC_IMPL_PART_DISP_POWER_GATE_CONTROL_0_SECURE                  0x0
#define PMC_IMPL_PART_DISP_POWER_GATE_CONTROL_0_DUAL                    0x0
#define PMC_IMPL_PART_DISP_POWER_GATE_CONTROL_0_SCR                     PG_DISP_SCR_0
#define PMC_IMPL_PART_DISP_POWER_GATE_CONTROL_0_SCRREG                  PMC_IMPL_SCR_PG_DISP_SCR_0
#define PMC_IMPL_PART_DISP_POWER_GATE_CONTROL_0_WORD_COUNT                      0x1
#define PMC_IMPL_PART_DISP_POWER_GATE_CONTROL_0_RESET_VAL                       MK_MASK_CONST(0x80000005)
#define PMC_IMPL_PART_DISP_POWER_GATE_CONTROL_0_RESET_MASK                      MK_MASK_CONST(0x80000107)
#define PMC_IMPL_PART_DISP_POWER_GATE_CONTROL_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_DISP_POWER_GATE_CONTROL_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_DISP_POWER_GATE_CONTROL_0_READ_MASK                       MK_MASK_CONST(0x80000107)
#define PMC_IMPL_PART_DISP_POWER_GATE_CONTROL_0_WRITE_MASK                      MK_MASK_CONST(0x80000105)
#define PMC_IMPL_PART_DISP_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SHIFT                       MK_SHIFT_CONST(31)
#define PMC_IMPL_PART_DISP_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_FIELD                       MK_FIELD_CONST(0x1, PMC_IMPL_PART_DISP_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SHIFT)
#define PMC_IMPL_PART_DISP_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_RANGE                       31:31
#define PMC_IMPL_PART_DISP_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_MSB                 MK_SHIFT_CONST(31)
#define PMC_IMPL_PART_DISP_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_LSB                 MK_SHIFT_CONST(31)
#define PMC_IMPL_PART_DISP_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_WOFFSET                     0x0
#define PMC_IMPL_PART_DISP_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_DEFAULT                     MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_DISP_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_DISP_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_DISP_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_DISP_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_DISP_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_DISP_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_INIT_ENUM                   ENABLE
#define PMC_IMPL_PART_DISP_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_DISABLE                     MK_ENUM_CONST(0)
#define PMC_IMPL_PART_DISP_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_ENABLE                      MK_ENUM_CONST(1)

#define PMC_IMPL_PART_DISP_POWER_GATE_CONTROL_0_START_SHIFT                     MK_SHIFT_CONST(8)
#define PMC_IMPL_PART_DISP_POWER_GATE_CONTROL_0_START_FIELD                     MK_FIELD_CONST(0x1, PMC_IMPL_PART_DISP_POWER_GATE_CONTROL_0_START_SHIFT)
#define PMC_IMPL_PART_DISP_POWER_GATE_CONTROL_0_START_RANGE                     8:8
#define PMC_IMPL_PART_DISP_POWER_GATE_CONTROL_0_START_MSB                       MK_SHIFT_CONST(8)
#define PMC_IMPL_PART_DISP_POWER_GATE_CONTROL_0_START_LSB                       MK_SHIFT_CONST(8)
#define PMC_IMPL_PART_DISP_POWER_GATE_CONTROL_0_START_WOFFSET                   0x0
#define PMC_IMPL_PART_DISP_POWER_GATE_CONTROL_0_START_DEFAULT                   MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_DISP_POWER_GATE_CONTROL_0_START_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_DISP_POWER_GATE_CONTROL_0_START_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_DISP_POWER_GATE_CONTROL_0_START_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_DISP_POWER_GATE_CONTROL_0_START_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_DISP_POWER_GATE_CONTROL_0_START_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_DISP_POWER_GATE_CONTROL_0_START_INIT_ENUM                 DONE
#define PMC_IMPL_PART_DISP_POWER_GATE_CONTROL_0_START_DONE                      MK_ENUM_CONST(0)
#define PMC_IMPL_PART_DISP_POWER_GATE_CONTROL_0_START_PENDING                   MK_ENUM_CONST(1)

#define PMC_IMPL_PART_DISP_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SHIFT                     MK_SHIFT_CONST(2)
#define PMC_IMPL_PART_DISP_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_FIELD                     MK_FIELD_CONST(0x1, PMC_IMPL_PART_DISP_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SHIFT)
#define PMC_IMPL_PART_DISP_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_RANGE                     2:2
#define PMC_IMPL_PART_DISP_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_MSB                       MK_SHIFT_CONST(2)
#define PMC_IMPL_PART_DISP_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_LSB                       MK_SHIFT_CONST(2)
#define PMC_IMPL_PART_DISP_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_WOFFSET                   0x0
#define PMC_IMPL_PART_DISP_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_DEFAULT                   MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_DISP_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_DISP_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_DISP_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_DISP_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_DISP_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_DISP_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_INIT_ENUM                 ON
#define PMC_IMPL_PART_DISP_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_OFF                       MK_ENUM_CONST(0)
#define PMC_IMPL_PART_DISP_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_ON                        MK_ENUM_CONST(1)

#define PMC_IMPL_PART_DISP_POWER_GATE_CONTROL_0_SRAM_RET_EN_SHIFT                       MK_SHIFT_CONST(1)
#define PMC_IMPL_PART_DISP_POWER_GATE_CONTROL_0_SRAM_RET_EN_FIELD                       MK_FIELD_CONST(0x1, PMC_IMPL_PART_DISP_POWER_GATE_CONTROL_0_SRAM_RET_EN_SHIFT)
#define PMC_IMPL_PART_DISP_POWER_GATE_CONTROL_0_SRAM_RET_EN_RANGE                       1:1
#define PMC_IMPL_PART_DISP_POWER_GATE_CONTROL_0_SRAM_RET_EN_MSB                 MK_SHIFT_CONST(1)
#define PMC_IMPL_PART_DISP_POWER_GATE_CONTROL_0_SRAM_RET_EN_LSB                 MK_SHIFT_CONST(1)
#define PMC_IMPL_PART_DISP_POWER_GATE_CONTROL_0_SRAM_RET_EN_WOFFSET                     0x0
#define PMC_IMPL_PART_DISP_POWER_GATE_CONTROL_0_SRAM_RET_EN_DEFAULT                     MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_DISP_POWER_GATE_CONTROL_0_SRAM_RET_EN_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_DISP_POWER_GATE_CONTROL_0_SRAM_RET_EN_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_DISP_POWER_GATE_CONTROL_0_SRAM_RET_EN_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_DISP_POWER_GATE_CONTROL_0_SRAM_RET_EN_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_DISP_POWER_GATE_CONTROL_0_SRAM_RET_EN_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_DISP_POWER_GATE_CONTROL_0_SRAM_RET_EN_INIT_ENUM                   OFF
#define PMC_IMPL_PART_DISP_POWER_GATE_CONTROL_0_SRAM_RET_EN_OFF                 MK_ENUM_CONST(0)
#define PMC_IMPL_PART_DISP_POWER_GATE_CONTROL_0_SRAM_RET_EN_ON                  MK_ENUM_CONST(1)

#define PMC_IMPL_PART_DISP_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SHIFT                       MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_DISP_POWER_GATE_CONTROL_0_LOGIC_SLEEP_FIELD                       MK_FIELD_CONST(0x1, PMC_IMPL_PART_DISP_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SHIFT)
#define PMC_IMPL_PART_DISP_POWER_GATE_CONTROL_0_LOGIC_SLEEP_RANGE                       0:0
#define PMC_IMPL_PART_DISP_POWER_GATE_CONTROL_0_LOGIC_SLEEP_MSB                 MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_DISP_POWER_GATE_CONTROL_0_LOGIC_SLEEP_LSB                 MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_DISP_POWER_GATE_CONTROL_0_LOGIC_SLEEP_WOFFSET                     0x0
#define PMC_IMPL_PART_DISP_POWER_GATE_CONTROL_0_LOGIC_SLEEP_DEFAULT                     MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_DISP_POWER_GATE_CONTROL_0_LOGIC_SLEEP_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_DISP_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_DISP_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_DISP_POWER_GATE_CONTROL_0_LOGIC_SLEEP_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_DISP_POWER_GATE_CONTROL_0_LOGIC_SLEEP_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_DISP_POWER_GATE_CONTROL_0_LOGIC_SLEEP_INIT_ENUM                   ON
#define PMC_IMPL_PART_DISP_POWER_GATE_CONTROL_0_LOGIC_SLEEP_OFF                 MK_ENUM_CONST(0)
#define PMC_IMPL_PART_DISP_POWER_GATE_CONTROL_0_LOGIC_SLEEP_ON                  MK_ENUM_CONST(1)


// Register PMC_IMPL_PART_DISP_POWER_GATE_STATUS_0
#define PMC_IMPL_PART_DISP_POWER_GATE_STATUS_0                  MK_ADDR_CONST(0x224)
#define PMC_IMPL_PART_DISP_POWER_GATE_STATUS_0_SECURE                   0x0
#define PMC_IMPL_PART_DISP_POWER_GATE_STATUS_0_DUAL                     0x0
#define PMC_IMPL_PART_DISP_POWER_GATE_STATUS_0_SCR                      PG_DISP_SCR_0
#define PMC_IMPL_PART_DISP_POWER_GATE_STATUS_0_SCRREG                   PMC_IMPL_SCR_PG_DISP_SCR_0
#define PMC_IMPL_PART_DISP_POWER_GATE_STATUS_0_WORD_COUNT                       0x1
#define PMC_IMPL_PART_DISP_POWER_GATE_STATUS_0_RESET_VAL                        MK_MASK_CONST(0x5)
#define PMC_IMPL_PART_DISP_POWER_GATE_STATUS_0_RESET_MASK                       MK_MASK_CONST(0x7)
#define PMC_IMPL_PART_DISP_POWER_GATE_STATUS_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_DISP_POWER_GATE_STATUS_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_DISP_POWER_GATE_STATUS_0_READ_MASK                        MK_MASK_CONST(0x7)
#define PMC_IMPL_PART_DISP_POWER_GATE_STATUS_0_WRITE_MASK                       MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_DISP_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SHIFT                     MK_SHIFT_CONST(2)
#define PMC_IMPL_PART_DISP_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_FIELD                     MK_FIELD_CONST(0x1, PMC_IMPL_PART_DISP_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SHIFT)
#define PMC_IMPL_PART_DISP_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_RANGE                     2:2
#define PMC_IMPL_PART_DISP_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_MSB                       MK_SHIFT_CONST(2)
#define PMC_IMPL_PART_DISP_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_LSB                       MK_SHIFT_CONST(2)
#define PMC_IMPL_PART_DISP_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_WOFFSET                   0x0
#define PMC_IMPL_PART_DISP_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_DEFAULT                   MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_DISP_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_DISP_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_DISP_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_DISP_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_DISP_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_DISP_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_INIT_ENUM                 ON
#define PMC_IMPL_PART_DISP_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_OFF                       MK_ENUM_CONST(0)
#define PMC_IMPL_PART_DISP_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_ON                        MK_ENUM_CONST(1)

#define PMC_IMPL_PART_DISP_POWER_GATE_STATUS_0_SRAM_RET_STS_SHIFT                       MK_SHIFT_CONST(1)
#define PMC_IMPL_PART_DISP_POWER_GATE_STATUS_0_SRAM_RET_STS_FIELD                       MK_FIELD_CONST(0x1, PMC_IMPL_PART_DISP_POWER_GATE_STATUS_0_SRAM_RET_STS_SHIFT)
#define PMC_IMPL_PART_DISP_POWER_GATE_STATUS_0_SRAM_RET_STS_RANGE                       1:1
#define PMC_IMPL_PART_DISP_POWER_GATE_STATUS_0_SRAM_RET_STS_MSB                 MK_SHIFT_CONST(1)
#define PMC_IMPL_PART_DISP_POWER_GATE_STATUS_0_SRAM_RET_STS_LSB                 MK_SHIFT_CONST(1)
#define PMC_IMPL_PART_DISP_POWER_GATE_STATUS_0_SRAM_RET_STS_WOFFSET                     0x0
#define PMC_IMPL_PART_DISP_POWER_GATE_STATUS_0_SRAM_RET_STS_DEFAULT                     MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_DISP_POWER_GATE_STATUS_0_SRAM_RET_STS_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_DISP_POWER_GATE_STATUS_0_SRAM_RET_STS_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_DISP_POWER_GATE_STATUS_0_SRAM_RET_STS_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_DISP_POWER_GATE_STATUS_0_SRAM_RET_STS_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_DISP_POWER_GATE_STATUS_0_SRAM_RET_STS_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_DISP_POWER_GATE_STATUS_0_SRAM_RET_STS_INIT_ENUM                   OFF
#define PMC_IMPL_PART_DISP_POWER_GATE_STATUS_0_SRAM_RET_STS_OFF                 MK_ENUM_CONST(0)
#define PMC_IMPL_PART_DISP_POWER_GATE_STATUS_0_SRAM_RET_STS_ON                  MK_ENUM_CONST(1)

#define PMC_IMPL_PART_DISP_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SHIFT                    MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_DISP_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_FIELD                    MK_FIELD_CONST(0x1, PMC_IMPL_PART_DISP_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SHIFT)
#define PMC_IMPL_PART_DISP_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_RANGE                    0:0
#define PMC_IMPL_PART_DISP_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_MSB                      MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_DISP_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_LSB                      MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_DISP_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_WOFFSET                  0x0
#define PMC_IMPL_PART_DISP_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_DEFAULT                  MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_DISP_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_DISP_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_DISP_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_DISP_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_DISP_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_DISP_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_INIT_ENUM                        ON
#define PMC_IMPL_PART_DISP_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_OFF                      MK_ENUM_CONST(0)
#define PMC_IMPL_PART_DISP_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_ON                       MK_ENUM_CONST(1)


// Register PMC_IMPL_PART_DISP_CLAMP_CONTROL_0
#define PMC_IMPL_PART_DISP_CLAMP_CONTROL_0                      MK_ADDR_CONST(0x228)
#define PMC_IMPL_PART_DISP_CLAMP_CONTROL_0_SECURE                       0x0
#define PMC_IMPL_PART_DISP_CLAMP_CONTROL_0_DUAL                         0x0
#define PMC_IMPL_PART_DISP_CLAMP_CONTROL_0_SCR                  PG_DISP_SCR_0
#define PMC_IMPL_PART_DISP_CLAMP_CONTROL_0_SCRREG                       PMC_IMPL_SCR_PG_DISP_SCR_0
#define PMC_IMPL_PART_DISP_CLAMP_CONTROL_0_WORD_COUNT                   0x1
#define PMC_IMPL_PART_DISP_CLAMP_CONTROL_0_RESET_VAL                    MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_DISP_CLAMP_CONTROL_0_RESET_MASK                   MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_DISP_CLAMP_CONTROL_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_DISP_CLAMP_CONTROL_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_DISP_CLAMP_CONTROL_0_READ_MASK                    MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_DISP_CLAMP_CONTROL_0_WRITE_MASK                   MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_DISP_CLAMP_CONTROL_0_CLAMP_SHIFT                  MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_DISP_CLAMP_CONTROL_0_CLAMP_FIELD                  MK_FIELD_CONST(0x1, PMC_IMPL_PART_DISP_CLAMP_CONTROL_0_CLAMP_SHIFT)
#define PMC_IMPL_PART_DISP_CLAMP_CONTROL_0_CLAMP_RANGE                  0:0
#define PMC_IMPL_PART_DISP_CLAMP_CONTROL_0_CLAMP_MSB                    MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_DISP_CLAMP_CONTROL_0_CLAMP_LSB                    MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_DISP_CLAMP_CONTROL_0_CLAMP_WOFFSET                        0x0
#define PMC_IMPL_PART_DISP_CLAMP_CONTROL_0_CLAMP_DEFAULT                        MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_DISP_CLAMP_CONTROL_0_CLAMP_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_DISP_CLAMP_CONTROL_0_CLAMP_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_DISP_CLAMP_CONTROL_0_CLAMP_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_DISP_CLAMP_CONTROL_0_CLAMP_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_DISP_CLAMP_CONTROL_0_CLAMP_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_DISP_CLAMP_CONTROL_0_CLAMP_INIT_ENUM                      ON
#define PMC_IMPL_PART_DISP_CLAMP_CONTROL_0_CLAMP_OFF                    MK_ENUM_CONST(0)
#define PMC_IMPL_PART_DISP_CLAMP_CONTROL_0_CLAMP_ON                     MK_ENUM_CONST(1)


// Reserved address 0x22c

// Reserved address 0x230

// Reserved address 0x234

// Reserved address 0x238

// Reserved address 0x23c

// Reserved address 0x240

// Reserved address 0x244

// Reserved address 0x248

// Reserved address 0x24c

// Reserved address 0x250

// Reserved address 0x254

// Reserved address 0x258

// Reserved address 0x25c

// Reserved address 0x260

// Reserved address 0x264

// Reserved address 0x268

// Reserved address 0x26c

// Reserved address 0x270

// Reserved address 0x274

// Reserved address 0x278

// Reserved address 0x27c

// Reserved address 0x280

// Reserved address 0x284

// Reserved address 0x288

// Reserved address 0x28c

// Reserved address 0x290

// Reserved address 0x294

// Register PMC_IMPL_PART_VIC_POWER_GATE_CONTROL_0
#define PMC_IMPL_PART_VIC_POWER_GATE_CONTROL_0                  MK_ADDR_CONST(0x298)
#define PMC_IMPL_PART_VIC_POWER_GATE_CONTROL_0_SECURE                   0x0
#define PMC_IMPL_PART_VIC_POWER_GATE_CONTROL_0_DUAL                     0x0
#define PMC_IMPL_PART_VIC_POWER_GATE_CONTROL_0_SCR                      PG_VIC_SCR_0
#define PMC_IMPL_PART_VIC_POWER_GATE_CONTROL_0_SCRREG                   PMC_IMPL_SCR_PG_VIC_SCR_0
#define PMC_IMPL_PART_VIC_POWER_GATE_CONTROL_0_WORD_COUNT                       0x1
#define PMC_IMPL_PART_VIC_POWER_GATE_CONTROL_0_RESET_VAL                        MK_MASK_CONST(0x80000005)
#define PMC_IMPL_PART_VIC_POWER_GATE_CONTROL_0_RESET_MASK                       MK_MASK_CONST(0x80000107)
#define PMC_IMPL_PART_VIC_POWER_GATE_CONTROL_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_VIC_POWER_GATE_CONTROL_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_VIC_POWER_GATE_CONTROL_0_READ_MASK                        MK_MASK_CONST(0x80000107)
#define PMC_IMPL_PART_VIC_POWER_GATE_CONTROL_0_WRITE_MASK                       MK_MASK_CONST(0x80000105)
#define PMC_IMPL_PART_VIC_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SHIFT                        MK_SHIFT_CONST(31)
#define PMC_IMPL_PART_VIC_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_FIELD                        MK_FIELD_CONST(0x1, PMC_IMPL_PART_VIC_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SHIFT)
#define PMC_IMPL_PART_VIC_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_RANGE                        31:31
#define PMC_IMPL_PART_VIC_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_MSB                  MK_SHIFT_CONST(31)
#define PMC_IMPL_PART_VIC_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_LSB                  MK_SHIFT_CONST(31)
#define PMC_IMPL_PART_VIC_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_WOFFSET                      0x0
#define PMC_IMPL_PART_VIC_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_DEFAULT                      MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_VIC_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_VIC_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_VIC_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_VIC_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_VIC_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_VIC_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_INIT_ENUM                    ENABLE
#define PMC_IMPL_PART_VIC_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_DISABLE                      MK_ENUM_CONST(0)
#define PMC_IMPL_PART_VIC_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_ENABLE                       MK_ENUM_CONST(1)

#define PMC_IMPL_PART_VIC_POWER_GATE_CONTROL_0_START_SHIFT                      MK_SHIFT_CONST(8)
#define PMC_IMPL_PART_VIC_POWER_GATE_CONTROL_0_START_FIELD                      MK_FIELD_CONST(0x1, PMC_IMPL_PART_VIC_POWER_GATE_CONTROL_0_START_SHIFT)
#define PMC_IMPL_PART_VIC_POWER_GATE_CONTROL_0_START_RANGE                      8:8
#define PMC_IMPL_PART_VIC_POWER_GATE_CONTROL_0_START_MSB                        MK_SHIFT_CONST(8)
#define PMC_IMPL_PART_VIC_POWER_GATE_CONTROL_0_START_LSB                        MK_SHIFT_CONST(8)
#define PMC_IMPL_PART_VIC_POWER_GATE_CONTROL_0_START_WOFFSET                    0x0
#define PMC_IMPL_PART_VIC_POWER_GATE_CONTROL_0_START_DEFAULT                    MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_VIC_POWER_GATE_CONTROL_0_START_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_VIC_POWER_GATE_CONTROL_0_START_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_VIC_POWER_GATE_CONTROL_0_START_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_VIC_POWER_GATE_CONTROL_0_START_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_VIC_POWER_GATE_CONTROL_0_START_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_VIC_POWER_GATE_CONTROL_0_START_INIT_ENUM                  DONE
#define PMC_IMPL_PART_VIC_POWER_GATE_CONTROL_0_START_DONE                       MK_ENUM_CONST(0)
#define PMC_IMPL_PART_VIC_POWER_GATE_CONTROL_0_START_PENDING                    MK_ENUM_CONST(1)

#define PMC_IMPL_PART_VIC_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SHIFT                      MK_SHIFT_CONST(2)
#define PMC_IMPL_PART_VIC_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_FIELD                      MK_FIELD_CONST(0x1, PMC_IMPL_PART_VIC_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SHIFT)
#define PMC_IMPL_PART_VIC_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_RANGE                      2:2
#define PMC_IMPL_PART_VIC_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_MSB                        MK_SHIFT_CONST(2)
#define PMC_IMPL_PART_VIC_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_LSB                        MK_SHIFT_CONST(2)
#define PMC_IMPL_PART_VIC_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_WOFFSET                    0x0
#define PMC_IMPL_PART_VIC_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_DEFAULT                    MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_VIC_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_VIC_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_VIC_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_VIC_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_VIC_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_VIC_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_INIT_ENUM                  ON
#define PMC_IMPL_PART_VIC_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_OFF                        MK_ENUM_CONST(0)
#define PMC_IMPL_PART_VIC_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_ON                 MK_ENUM_CONST(1)

#define PMC_IMPL_PART_VIC_POWER_GATE_CONTROL_0_SRAM_RET_EN_SHIFT                        MK_SHIFT_CONST(1)
#define PMC_IMPL_PART_VIC_POWER_GATE_CONTROL_0_SRAM_RET_EN_FIELD                        MK_FIELD_CONST(0x1, PMC_IMPL_PART_VIC_POWER_GATE_CONTROL_0_SRAM_RET_EN_SHIFT)
#define PMC_IMPL_PART_VIC_POWER_GATE_CONTROL_0_SRAM_RET_EN_RANGE                        1:1
#define PMC_IMPL_PART_VIC_POWER_GATE_CONTROL_0_SRAM_RET_EN_MSB                  MK_SHIFT_CONST(1)
#define PMC_IMPL_PART_VIC_POWER_GATE_CONTROL_0_SRAM_RET_EN_LSB                  MK_SHIFT_CONST(1)
#define PMC_IMPL_PART_VIC_POWER_GATE_CONTROL_0_SRAM_RET_EN_WOFFSET                      0x0
#define PMC_IMPL_PART_VIC_POWER_GATE_CONTROL_0_SRAM_RET_EN_DEFAULT                      MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_VIC_POWER_GATE_CONTROL_0_SRAM_RET_EN_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_VIC_POWER_GATE_CONTROL_0_SRAM_RET_EN_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_VIC_POWER_GATE_CONTROL_0_SRAM_RET_EN_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_VIC_POWER_GATE_CONTROL_0_SRAM_RET_EN_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_VIC_POWER_GATE_CONTROL_0_SRAM_RET_EN_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_VIC_POWER_GATE_CONTROL_0_SRAM_RET_EN_INIT_ENUM                    OFF
#define PMC_IMPL_PART_VIC_POWER_GATE_CONTROL_0_SRAM_RET_EN_OFF                  MK_ENUM_CONST(0)
#define PMC_IMPL_PART_VIC_POWER_GATE_CONTROL_0_SRAM_RET_EN_ON                   MK_ENUM_CONST(1)

#define PMC_IMPL_PART_VIC_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SHIFT                        MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_VIC_POWER_GATE_CONTROL_0_LOGIC_SLEEP_FIELD                        MK_FIELD_CONST(0x1, PMC_IMPL_PART_VIC_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SHIFT)
#define PMC_IMPL_PART_VIC_POWER_GATE_CONTROL_0_LOGIC_SLEEP_RANGE                        0:0
#define PMC_IMPL_PART_VIC_POWER_GATE_CONTROL_0_LOGIC_SLEEP_MSB                  MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_VIC_POWER_GATE_CONTROL_0_LOGIC_SLEEP_LSB                  MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_VIC_POWER_GATE_CONTROL_0_LOGIC_SLEEP_WOFFSET                      0x0
#define PMC_IMPL_PART_VIC_POWER_GATE_CONTROL_0_LOGIC_SLEEP_DEFAULT                      MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_VIC_POWER_GATE_CONTROL_0_LOGIC_SLEEP_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_VIC_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_VIC_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_VIC_POWER_GATE_CONTROL_0_LOGIC_SLEEP_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_VIC_POWER_GATE_CONTROL_0_LOGIC_SLEEP_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_VIC_POWER_GATE_CONTROL_0_LOGIC_SLEEP_INIT_ENUM                    ON
#define PMC_IMPL_PART_VIC_POWER_GATE_CONTROL_0_LOGIC_SLEEP_OFF                  MK_ENUM_CONST(0)
#define PMC_IMPL_PART_VIC_POWER_GATE_CONTROL_0_LOGIC_SLEEP_ON                   MK_ENUM_CONST(1)


// Register PMC_IMPL_PART_VIC_POWER_GATE_STATUS_0
#define PMC_IMPL_PART_VIC_POWER_GATE_STATUS_0                   MK_ADDR_CONST(0x29c)
#define PMC_IMPL_PART_VIC_POWER_GATE_STATUS_0_SECURE                    0x0
#define PMC_IMPL_PART_VIC_POWER_GATE_STATUS_0_DUAL                      0x0
#define PMC_IMPL_PART_VIC_POWER_GATE_STATUS_0_SCR                       PG_VIC_SCR_0
#define PMC_IMPL_PART_VIC_POWER_GATE_STATUS_0_SCRREG                    PMC_IMPL_SCR_PG_VIC_SCR_0
#define PMC_IMPL_PART_VIC_POWER_GATE_STATUS_0_WORD_COUNT                        0x1
#define PMC_IMPL_PART_VIC_POWER_GATE_STATUS_0_RESET_VAL                         MK_MASK_CONST(0x5)
#define PMC_IMPL_PART_VIC_POWER_GATE_STATUS_0_RESET_MASK                        MK_MASK_CONST(0x7)
#define PMC_IMPL_PART_VIC_POWER_GATE_STATUS_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_VIC_POWER_GATE_STATUS_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_VIC_POWER_GATE_STATUS_0_READ_MASK                         MK_MASK_CONST(0x7)
#define PMC_IMPL_PART_VIC_POWER_GATE_STATUS_0_WRITE_MASK                        MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_VIC_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SHIFT                      MK_SHIFT_CONST(2)
#define PMC_IMPL_PART_VIC_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_FIELD                      MK_FIELD_CONST(0x1, PMC_IMPL_PART_VIC_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SHIFT)
#define PMC_IMPL_PART_VIC_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_RANGE                      2:2
#define PMC_IMPL_PART_VIC_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_MSB                        MK_SHIFT_CONST(2)
#define PMC_IMPL_PART_VIC_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_LSB                        MK_SHIFT_CONST(2)
#define PMC_IMPL_PART_VIC_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_WOFFSET                    0x0
#define PMC_IMPL_PART_VIC_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_DEFAULT                    MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_VIC_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_VIC_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_VIC_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_VIC_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_VIC_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_VIC_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_INIT_ENUM                  ON
#define PMC_IMPL_PART_VIC_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_OFF                        MK_ENUM_CONST(0)
#define PMC_IMPL_PART_VIC_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_ON                 MK_ENUM_CONST(1)

#define PMC_IMPL_PART_VIC_POWER_GATE_STATUS_0_SRAM_RET_STS_SHIFT                        MK_SHIFT_CONST(1)
#define PMC_IMPL_PART_VIC_POWER_GATE_STATUS_0_SRAM_RET_STS_FIELD                        MK_FIELD_CONST(0x1, PMC_IMPL_PART_VIC_POWER_GATE_STATUS_0_SRAM_RET_STS_SHIFT)
#define PMC_IMPL_PART_VIC_POWER_GATE_STATUS_0_SRAM_RET_STS_RANGE                        1:1
#define PMC_IMPL_PART_VIC_POWER_GATE_STATUS_0_SRAM_RET_STS_MSB                  MK_SHIFT_CONST(1)
#define PMC_IMPL_PART_VIC_POWER_GATE_STATUS_0_SRAM_RET_STS_LSB                  MK_SHIFT_CONST(1)
#define PMC_IMPL_PART_VIC_POWER_GATE_STATUS_0_SRAM_RET_STS_WOFFSET                      0x0
#define PMC_IMPL_PART_VIC_POWER_GATE_STATUS_0_SRAM_RET_STS_DEFAULT                      MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_VIC_POWER_GATE_STATUS_0_SRAM_RET_STS_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_VIC_POWER_GATE_STATUS_0_SRAM_RET_STS_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_VIC_POWER_GATE_STATUS_0_SRAM_RET_STS_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_VIC_POWER_GATE_STATUS_0_SRAM_RET_STS_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_VIC_POWER_GATE_STATUS_0_SRAM_RET_STS_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_VIC_POWER_GATE_STATUS_0_SRAM_RET_STS_INIT_ENUM                    OFF
#define PMC_IMPL_PART_VIC_POWER_GATE_STATUS_0_SRAM_RET_STS_OFF                  MK_ENUM_CONST(0)
#define PMC_IMPL_PART_VIC_POWER_GATE_STATUS_0_SRAM_RET_STS_ON                   MK_ENUM_CONST(1)

#define PMC_IMPL_PART_VIC_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SHIFT                     MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_VIC_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_FIELD                     MK_FIELD_CONST(0x1, PMC_IMPL_PART_VIC_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SHIFT)
#define PMC_IMPL_PART_VIC_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_RANGE                     0:0
#define PMC_IMPL_PART_VIC_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_MSB                       MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_VIC_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_LSB                       MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_VIC_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_WOFFSET                   0x0
#define PMC_IMPL_PART_VIC_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_DEFAULT                   MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_VIC_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_VIC_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_VIC_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_VIC_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_VIC_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_VIC_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_INIT_ENUM                 ON
#define PMC_IMPL_PART_VIC_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_OFF                       MK_ENUM_CONST(0)
#define PMC_IMPL_PART_VIC_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_ON                        MK_ENUM_CONST(1)


// Register PMC_IMPL_PART_VIC_CLAMP_CONTROL_0
#define PMC_IMPL_PART_VIC_CLAMP_CONTROL_0                       MK_ADDR_CONST(0x2a0)
#define PMC_IMPL_PART_VIC_CLAMP_CONTROL_0_SECURE                        0x0
#define PMC_IMPL_PART_VIC_CLAMP_CONTROL_0_DUAL                  0x0
#define PMC_IMPL_PART_VIC_CLAMP_CONTROL_0_SCR                   PG_VIC_SCR_0
#define PMC_IMPL_PART_VIC_CLAMP_CONTROL_0_SCRREG                        PMC_IMPL_SCR_PG_VIC_SCR_0
#define PMC_IMPL_PART_VIC_CLAMP_CONTROL_0_WORD_COUNT                    0x1
#define PMC_IMPL_PART_VIC_CLAMP_CONTROL_0_RESET_VAL                     MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_VIC_CLAMP_CONTROL_0_RESET_MASK                    MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_VIC_CLAMP_CONTROL_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_VIC_CLAMP_CONTROL_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_VIC_CLAMP_CONTROL_0_READ_MASK                     MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_VIC_CLAMP_CONTROL_0_WRITE_MASK                    MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_VIC_CLAMP_CONTROL_0_CLAMP_SHIFT                   MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_VIC_CLAMP_CONTROL_0_CLAMP_FIELD                   MK_FIELD_CONST(0x1, PMC_IMPL_PART_VIC_CLAMP_CONTROL_0_CLAMP_SHIFT)
#define PMC_IMPL_PART_VIC_CLAMP_CONTROL_0_CLAMP_RANGE                   0:0
#define PMC_IMPL_PART_VIC_CLAMP_CONTROL_0_CLAMP_MSB                     MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_VIC_CLAMP_CONTROL_0_CLAMP_LSB                     MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_VIC_CLAMP_CONTROL_0_CLAMP_WOFFSET                 0x0
#define PMC_IMPL_PART_VIC_CLAMP_CONTROL_0_CLAMP_DEFAULT                 MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_VIC_CLAMP_CONTROL_0_CLAMP_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_VIC_CLAMP_CONTROL_0_CLAMP_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_VIC_CLAMP_CONTROL_0_CLAMP_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_VIC_CLAMP_CONTROL_0_CLAMP_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_VIC_CLAMP_CONTROL_0_CLAMP_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_VIC_CLAMP_CONTROL_0_CLAMP_INIT_ENUM                       ON
#define PMC_IMPL_PART_VIC_CLAMP_CONTROL_0_CLAMP_OFF                     MK_ENUM_CONST(0)
#define PMC_IMPL_PART_VIC_CLAMP_CONTROL_0_CLAMP_ON                      MK_ENUM_CONST(1)


// Register PMC_IMPL_PART_XUSBA_POWER_GATE_CONTROL_0
#define PMC_IMPL_PART_XUSBA_POWER_GATE_CONTROL_0                        MK_ADDR_CONST(0x2a4)
#define PMC_IMPL_PART_XUSBA_POWER_GATE_CONTROL_0_SECURE                         0x0
#define PMC_IMPL_PART_XUSBA_POWER_GATE_CONTROL_0_DUAL                   0x0
#define PMC_IMPL_PART_XUSBA_POWER_GATE_CONTROL_0_SCR                    PG_XUSBA_SCR_0
#define PMC_IMPL_PART_XUSBA_POWER_GATE_CONTROL_0_SCRREG                         PMC_IMPL_SCR_PG_XUSBA_SCR_0
#define PMC_IMPL_PART_XUSBA_POWER_GATE_CONTROL_0_WORD_COUNT                     0x1
#define PMC_IMPL_PART_XUSBA_POWER_GATE_CONTROL_0_RESET_VAL                      MK_MASK_CONST(0x80000000)
#define PMC_IMPL_PART_XUSBA_POWER_GATE_CONTROL_0_RESET_MASK                     MK_MASK_CONST(0x80000107)
#define PMC_IMPL_PART_XUSBA_POWER_GATE_CONTROL_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_XUSBA_POWER_GATE_CONTROL_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_XUSBA_POWER_GATE_CONTROL_0_READ_MASK                      MK_MASK_CONST(0x80000107)
#define PMC_IMPL_PART_XUSBA_POWER_GATE_CONTROL_0_WRITE_MASK                     MK_MASK_CONST(0x80000105)
#define PMC_IMPL_PART_XUSBA_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SHIFT                      MK_SHIFT_CONST(31)
#define PMC_IMPL_PART_XUSBA_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_FIELD                      MK_FIELD_CONST(0x1, PMC_IMPL_PART_XUSBA_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SHIFT)
#define PMC_IMPL_PART_XUSBA_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_RANGE                      31:31
#define PMC_IMPL_PART_XUSBA_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_MSB                        MK_SHIFT_CONST(31)
#define PMC_IMPL_PART_XUSBA_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_LSB                        MK_SHIFT_CONST(31)
#define PMC_IMPL_PART_XUSBA_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_WOFFSET                    0x0
#define PMC_IMPL_PART_XUSBA_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_DEFAULT                    MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_XUSBA_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_XUSBA_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_XUSBA_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_XUSBA_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_XUSBA_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_XUSBA_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_INIT_ENUM                  ENABLE
#define PMC_IMPL_PART_XUSBA_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_DISABLE                    MK_ENUM_CONST(0)
#define PMC_IMPL_PART_XUSBA_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_ENABLE                     MK_ENUM_CONST(1)

#define PMC_IMPL_PART_XUSBA_POWER_GATE_CONTROL_0_START_SHIFT                    MK_SHIFT_CONST(8)
#define PMC_IMPL_PART_XUSBA_POWER_GATE_CONTROL_0_START_FIELD                    MK_FIELD_CONST(0x1, PMC_IMPL_PART_XUSBA_POWER_GATE_CONTROL_0_START_SHIFT)
#define PMC_IMPL_PART_XUSBA_POWER_GATE_CONTROL_0_START_RANGE                    8:8
#define PMC_IMPL_PART_XUSBA_POWER_GATE_CONTROL_0_START_MSB                      MK_SHIFT_CONST(8)
#define PMC_IMPL_PART_XUSBA_POWER_GATE_CONTROL_0_START_LSB                      MK_SHIFT_CONST(8)
#define PMC_IMPL_PART_XUSBA_POWER_GATE_CONTROL_0_START_WOFFSET                  0x0
#define PMC_IMPL_PART_XUSBA_POWER_GATE_CONTROL_0_START_DEFAULT                  MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_XUSBA_POWER_GATE_CONTROL_0_START_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_XUSBA_POWER_GATE_CONTROL_0_START_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_XUSBA_POWER_GATE_CONTROL_0_START_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_XUSBA_POWER_GATE_CONTROL_0_START_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_XUSBA_POWER_GATE_CONTROL_0_START_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_XUSBA_POWER_GATE_CONTROL_0_START_INIT_ENUM                        DONE
#define PMC_IMPL_PART_XUSBA_POWER_GATE_CONTROL_0_START_DONE                     MK_ENUM_CONST(0)
#define PMC_IMPL_PART_XUSBA_POWER_GATE_CONTROL_0_START_PENDING                  MK_ENUM_CONST(1)

#define PMC_IMPL_PART_XUSBA_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SHIFT                    MK_SHIFT_CONST(2)
#define PMC_IMPL_PART_XUSBA_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_FIELD                    MK_FIELD_CONST(0x1, PMC_IMPL_PART_XUSBA_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SHIFT)
#define PMC_IMPL_PART_XUSBA_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_RANGE                    2:2
#define PMC_IMPL_PART_XUSBA_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_MSB                      MK_SHIFT_CONST(2)
#define PMC_IMPL_PART_XUSBA_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_LSB                      MK_SHIFT_CONST(2)
#define PMC_IMPL_PART_XUSBA_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_WOFFSET                  0x0
#define PMC_IMPL_PART_XUSBA_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_DEFAULT                  MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_XUSBA_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_XUSBA_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_XUSBA_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_XUSBA_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_XUSBA_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_XUSBA_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_INIT_ENUM                        OFF
#define PMC_IMPL_PART_XUSBA_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_OFF                      MK_ENUM_CONST(0)
#define PMC_IMPL_PART_XUSBA_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_ON                       MK_ENUM_CONST(1)

#define PMC_IMPL_PART_XUSBA_POWER_GATE_CONTROL_0_SRAM_RET_EN_SHIFT                      MK_SHIFT_CONST(1)
#define PMC_IMPL_PART_XUSBA_POWER_GATE_CONTROL_0_SRAM_RET_EN_FIELD                      MK_FIELD_CONST(0x1, PMC_IMPL_PART_XUSBA_POWER_GATE_CONTROL_0_SRAM_RET_EN_SHIFT)
#define PMC_IMPL_PART_XUSBA_POWER_GATE_CONTROL_0_SRAM_RET_EN_RANGE                      1:1
#define PMC_IMPL_PART_XUSBA_POWER_GATE_CONTROL_0_SRAM_RET_EN_MSB                        MK_SHIFT_CONST(1)
#define PMC_IMPL_PART_XUSBA_POWER_GATE_CONTROL_0_SRAM_RET_EN_LSB                        MK_SHIFT_CONST(1)
#define PMC_IMPL_PART_XUSBA_POWER_GATE_CONTROL_0_SRAM_RET_EN_WOFFSET                    0x0
#define PMC_IMPL_PART_XUSBA_POWER_GATE_CONTROL_0_SRAM_RET_EN_DEFAULT                    MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_XUSBA_POWER_GATE_CONTROL_0_SRAM_RET_EN_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_XUSBA_POWER_GATE_CONTROL_0_SRAM_RET_EN_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_XUSBA_POWER_GATE_CONTROL_0_SRAM_RET_EN_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_XUSBA_POWER_GATE_CONTROL_0_SRAM_RET_EN_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_XUSBA_POWER_GATE_CONTROL_0_SRAM_RET_EN_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_XUSBA_POWER_GATE_CONTROL_0_SRAM_RET_EN_INIT_ENUM                  OFF
#define PMC_IMPL_PART_XUSBA_POWER_GATE_CONTROL_0_SRAM_RET_EN_OFF                        MK_ENUM_CONST(0)
#define PMC_IMPL_PART_XUSBA_POWER_GATE_CONTROL_0_SRAM_RET_EN_ON                 MK_ENUM_CONST(1)

#define PMC_IMPL_PART_XUSBA_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SHIFT                      MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_XUSBA_POWER_GATE_CONTROL_0_LOGIC_SLEEP_FIELD                      MK_FIELD_CONST(0x1, PMC_IMPL_PART_XUSBA_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SHIFT)
#define PMC_IMPL_PART_XUSBA_POWER_GATE_CONTROL_0_LOGIC_SLEEP_RANGE                      0:0
#define PMC_IMPL_PART_XUSBA_POWER_GATE_CONTROL_0_LOGIC_SLEEP_MSB                        MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_XUSBA_POWER_GATE_CONTROL_0_LOGIC_SLEEP_LSB                        MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_XUSBA_POWER_GATE_CONTROL_0_LOGIC_SLEEP_WOFFSET                    0x0
#define PMC_IMPL_PART_XUSBA_POWER_GATE_CONTROL_0_LOGIC_SLEEP_DEFAULT                    MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_XUSBA_POWER_GATE_CONTROL_0_LOGIC_SLEEP_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_XUSBA_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_XUSBA_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_XUSBA_POWER_GATE_CONTROL_0_LOGIC_SLEEP_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_XUSBA_POWER_GATE_CONTROL_0_LOGIC_SLEEP_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_XUSBA_POWER_GATE_CONTROL_0_LOGIC_SLEEP_INIT_ENUM                  OFF
#define PMC_IMPL_PART_XUSBA_POWER_GATE_CONTROL_0_LOGIC_SLEEP_OFF                        MK_ENUM_CONST(0)
#define PMC_IMPL_PART_XUSBA_POWER_GATE_CONTROL_0_LOGIC_SLEEP_ON                 MK_ENUM_CONST(1)


// Register PMC_IMPL_PART_XUSBA_POWER_GATE_STATUS_0
#define PMC_IMPL_PART_XUSBA_POWER_GATE_STATUS_0                 MK_ADDR_CONST(0x2a8)
#define PMC_IMPL_PART_XUSBA_POWER_GATE_STATUS_0_SECURE                  0x0
#define PMC_IMPL_PART_XUSBA_POWER_GATE_STATUS_0_DUAL                    0x0
#define PMC_IMPL_PART_XUSBA_POWER_GATE_STATUS_0_SCR                     PG_XUSBA_SCR_0
#define PMC_IMPL_PART_XUSBA_POWER_GATE_STATUS_0_SCRREG                  PMC_IMPL_SCR_PG_XUSBA_SCR_0
#define PMC_IMPL_PART_XUSBA_POWER_GATE_STATUS_0_WORD_COUNT                      0x1
#define PMC_IMPL_PART_XUSBA_POWER_GATE_STATUS_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_XUSBA_POWER_GATE_STATUS_0_RESET_MASK                      MK_MASK_CONST(0x7)
#define PMC_IMPL_PART_XUSBA_POWER_GATE_STATUS_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_XUSBA_POWER_GATE_STATUS_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_XUSBA_POWER_GATE_STATUS_0_READ_MASK                       MK_MASK_CONST(0x7)
#define PMC_IMPL_PART_XUSBA_POWER_GATE_STATUS_0_WRITE_MASK                      MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_XUSBA_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SHIFT                    MK_SHIFT_CONST(2)
#define PMC_IMPL_PART_XUSBA_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_FIELD                    MK_FIELD_CONST(0x1, PMC_IMPL_PART_XUSBA_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SHIFT)
#define PMC_IMPL_PART_XUSBA_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_RANGE                    2:2
#define PMC_IMPL_PART_XUSBA_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_MSB                      MK_SHIFT_CONST(2)
#define PMC_IMPL_PART_XUSBA_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_LSB                      MK_SHIFT_CONST(2)
#define PMC_IMPL_PART_XUSBA_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_WOFFSET                  0x0
#define PMC_IMPL_PART_XUSBA_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_DEFAULT                  MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_XUSBA_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_XUSBA_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_XUSBA_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_XUSBA_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_XUSBA_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_XUSBA_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_INIT_ENUM                        OFF
#define PMC_IMPL_PART_XUSBA_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_OFF                      MK_ENUM_CONST(0)
#define PMC_IMPL_PART_XUSBA_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_ON                       MK_ENUM_CONST(1)

#define PMC_IMPL_PART_XUSBA_POWER_GATE_STATUS_0_SRAM_RET_STS_SHIFT                      MK_SHIFT_CONST(1)
#define PMC_IMPL_PART_XUSBA_POWER_GATE_STATUS_0_SRAM_RET_STS_FIELD                      MK_FIELD_CONST(0x1, PMC_IMPL_PART_XUSBA_POWER_GATE_STATUS_0_SRAM_RET_STS_SHIFT)
#define PMC_IMPL_PART_XUSBA_POWER_GATE_STATUS_0_SRAM_RET_STS_RANGE                      1:1
#define PMC_IMPL_PART_XUSBA_POWER_GATE_STATUS_0_SRAM_RET_STS_MSB                        MK_SHIFT_CONST(1)
#define PMC_IMPL_PART_XUSBA_POWER_GATE_STATUS_0_SRAM_RET_STS_LSB                        MK_SHIFT_CONST(1)
#define PMC_IMPL_PART_XUSBA_POWER_GATE_STATUS_0_SRAM_RET_STS_WOFFSET                    0x0
#define PMC_IMPL_PART_XUSBA_POWER_GATE_STATUS_0_SRAM_RET_STS_DEFAULT                    MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_XUSBA_POWER_GATE_STATUS_0_SRAM_RET_STS_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_XUSBA_POWER_GATE_STATUS_0_SRAM_RET_STS_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_XUSBA_POWER_GATE_STATUS_0_SRAM_RET_STS_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_XUSBA_POWER_GATE_STATUS_0_SRAM_RET_STS_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_XUSBA_POWER_GATE_STATUS_0_SRAM_RET_STS_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_XUSBA_POWER_GATE_STATUS_0_SRAM_RET_STS_INIT_ENUM                  OFF
#define PMC_IMPL_PART_XUSBA_POWER_GATE_STATUS_0_SRAM_RET_STS_OFF                        MK_ENUM_CONST(0)
#define PMC_IMPL_PART_XUSBA_POWER_GATE_STATUS_0_SRAM_RET_STS_ON                 MK_ENUM_CONST(1)

#define PMC_IMPL_PART_XUSBA_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SHIFT                   MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_XUSBA_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_FIELD                   MK_FIELD_CONST(0x1, PMC_IMPL_PART_XUSBA_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SHIFT)
#define PMC_IMPL_PART_XUSBA_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_RANGE                   0:0
#define PMC_IMPL_PART_XUSBA_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_MSB                     MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_XUSBA_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_LSB                     MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_XUSBA_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_WOFFSET                 0x0
#define PMC_IMPL_PART_XUSBA_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_DEFAULT                 MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_XUSBA_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_XUSBA_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_XUSBA_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_XUSBA_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_XUSBA_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_XUSBA_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_INIT_ENUM                       OFF
#define PMC_IMPL_PART_XUSBA_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_OFF                     MK_ENUM_CONST(0)
#define PMC_IMPL_PART_XUSBA_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_ON                      MK_ENUM_CONST(1)


// Register PMC_IMPL_PART_XUSBA_CLAMP_CONTROL_0
#define PMC_IMPL_PART_XUSBA_CLAMP_CONTROL_0                     MK_ADDR_CONST(0x2ac)
#define PMC_IMPL_PART_XUSBA_CLAMP_CONTROL_0_SECURE                      0x0
#define PMC_IMPL_PART_XUSBA_CLAMP_CONTROL_0_DUAL                        0x0
#define PMC_IMPL_PART_XUSBA_CLAMP_CONTROL_0_SCR                         PG_XUSBA_SCR_0
#define PMC_IMPL_PART_XUSBA_CLAMP_CONTROL_0_SCRREG                      PMC_IMPL_SCR_PG_XUSBA_SCR_0
#define PMC_IMPL_PART_XUSBA_CLAMP_CONTROL_0_WORD_COUNT                  0x1
#define PMC_IMPL_PART_XUSBA_CLAMP_CONTROL_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_XUSBA_CLAMP_CONTROL_0_RESET_MASK                  MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_XUSBA_CLAMP_CONTROL_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_XUSBA_CLAMP_CONTROL_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_XUSBA_CLAMP_CONTROL_0_READ_MASK                   MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_XUSBA_CLAMP_CONTROL_0_WRITE_MASK                  MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_XUSBA_CLAMP_CONTROL_0_CLAMP_SHIFT                 MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_XUSBA_CLAMP_CONTROL_0_CLAMP_FIELD                 MK_FIELD_CONST(0x1, PMC_IMPL_PART_XUSBA_CLAMP_CONTROL_0_CLAMP_SHIFT)
#define PMC_IMPL_PART_XUSBA_CLAMP_CONTROL_0_CLAMP_RANGE                 0:0
#define PMC_IMPL_PART_XUSBA_CLAMP_CONTROL_0_CLAMP_MSB                   MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_XUSBA_CLAMP_CONTROL_0_CLAMP_LSB                   MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_XUSBA_CLAMP_CONTROL_0_CLAMP_WOFFSET                       0x0
#define PMC_IMPL_PART_XUSBA_CLAMP_CONTROL_0_CLAMP_DEFAULT                       MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_XUSBA_CLAMP_CONTROL_0_CLAMP_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_XUSBA_CLAMP_CONTROL_0_CLAMP_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_XUSBA_CLAMP_CONTROL_0_CLAMP_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_XUSBA_CLAMP_CONTROL_0_CLAMP_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_XUSBA_CLAMP_CONTROL_0_CLAMP_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_XUSBA_CLAMP_CONTROL_0_CLAMP_INIT_ENUM                     OFF
#define PMC_IMPL_PART_XUSBA_CLAMP_CONTROL_0_CLAMP_OFF                   MK_ENUM_CONST(0)
#define PMC_IMPL_PART_XUSBA_CLAMP_CONTROL_0_CLAMP_ON                    MK_ENUM_CONST(1)


// Register PMC_IMPL_PART_XUSBB_POWER_GATE_CONTROL_0
#define PMC_IMPL_PART_XUSBB_POWER_GATE_CONTROL_0                        MK_ADDR_CONST(0x2b0)
#define PMC_IMPL_PART_XUSBB_POWER_GATE_CONTROL_0_SECURE                         0x0
#define PMC_IMPL_PART_XUSBB_POWER_GATE_CONTROL_0_DUAL                   0x0
#define PMC_IMPL_PART_XUSBB_POWER_GATE_CONTROL_0_SCR                    PG_XUSBB_SCR_0
#define PMC_IMPL_PART_XUSBB_POWER_GATE_CONTROL_0_SCRREG                         PMC_IMPL_SCR_PG_XUSBB_SCR_0
#define PMC_IMPL_PART_XUSBB_POWER_GATE_CONTROL_0_WORD_COUNT                     0x1
#define PMC_IMPL_PART_XUSBB_POWER_GATE_CONTROL_0_RESET_VAL                      MK_MASK_CONST(0x80000000)
#define PMC_IMPL_PART_XUSBB_POWER_GATE_CONTROL_0_RESET_MASK                     MK_MASK_CONST(0x80000107)
#define PMC_IMPL_PART_XUSBB_POWER_GATE_CONTROL_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_XUSBB_POWER_GATE_CONTROL_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_XUSBB_POWER_GATE_CONTROL_0_READ_MASK                      MK_MASK_CONST(0x80000107)
#define PMC_IMPL_PART_XUSBB_POWER_GATE_CONTROL_0_WRITE_MASK                     MK_MASK_CONST(0x80000105)
#define PMC_IMPL_PART_XUSBB_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SHIFT                      MK_SHIFT_CONST(31)
#define PMC_IMPL_PART_XUSBB_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_FIELD                      MK_FIELD_CONST(0x1, PMC_IMPL_PART_XUSBB_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SHIFT)
#define PMC_IMPL_PART_XUSBB_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_RANGE                      31:31
#define PMC_IMPL_PART_XUSBB_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_MSB                        MK_SHIFT_CONST(31)
#define PMC_IMPL_PART_XUSBB_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_LSB                        MK_SHIFT_CONST(31)
#define PMC_IMPL_PART_XUSBB_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_WOFFSET                    0x0
#define PMC_IMPL_PART_XUSBB_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_DEFAULT                    MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_XUSBB_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_XUSBB_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_XUSBB_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_XUSBB_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_XUSBB_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_XUSBB_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_INIT_ENUM                  ENABLE
#define PMC_IMPL_PART_XUSBB_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_DISABLE                    MK_ENUM_CONST(0)
#define PMC_IMPL_PART_XUSBB_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_ENABLE                     MK_ENUM_CONST(1)

#define PMC_IMPL_PART_XUSBB_POWER_GATE_CONTROL_0_START_SHIFT                    MK_SHIFT_CONST(8)
#define PMC_IMPL_PART_XUSBB_POWER_GATE_CONTROL_0_START_FIELD                    MK_FIELD_CONST(0x1, PMC_IMPL_PART_XUSBB_POWER_GATE_CONTROL_0_START_SHIFT)
#define PMC_IMPL_PART_XUSBB_POWER_GATE_CONTROL_0_START_RANGE                    8:8
#define PMC_IMPL_PART_XUSBB_POWER_GATE_CONTROL_0_START_MSB                      MK_SHIFT_CONST(8)
#define PMC_IMPL_PART_XUSBB_POWER_GATE_CONTROL_0_START_LSB                      MK_SHIFT_CONST(8)
#define PMC_IMPL_PART_XUSBB_POWER_GATE_CONTROL_0_START_WOFFSET                  0x0
#define PMC_IMPL_PART_XUSBB_POWER_GATE_CONTROL_0_START_DEFAULT                  MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_XUSBB_POWER_GATE_CONTROL_0_START_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_XUSBB_POWER_GATE_CONTROL_0_START_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_XUSBB_POWER_GATE_CONTROL_0_START_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_XUSBB_POWER_GATE_CONTROL_0_START_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_XUSBB_POWER_GATE_CONTROL_0_START_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_XUSBB_POWER_GATE_CONTROL_0_START_INIT_ENUM                        DONE
#define PMC_IMPL_PART_XUSBB_POWER_GATE_CONTROL_0_START_DONE                     MK_ENUM_CONST(0)
#define PMC_IMPL_PART_XUSBB_POWER_GATE_CONTROL_0_START_PENDING                  MK_ENUM_CONST(1)

#define PMC_IMPL_PART_XUSBB_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SHIFT                    MK_SHIFT_CONST(2)
#define PMC_IMPL_PART_XUSBB_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_FIELD                    MK_FIELD_CONST(0x1, PMC_IMPL_PART_XUSBB_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SHIFT)
#define PMC_IMPL_PART_XUSBB_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_RANGE                    2:2
#define PMC_IMPL_PART_XUSBB_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_MSB                      MK_SHIFT_CONST(2)
#define PMC_IMPL_PART_XUSBB_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_LSB                      MK_SHIFT_CONST(2)
#define PMC_IMPL_PART_XUSBB_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_WOFFSET                  0x0
#define PMC_IMPL_PART_XUSBB_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_DEFAULT                  MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_XUSBB_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_XUSBB_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_XUSBB_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_XUSBB_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_XUSBB_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_XUSBB_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_INIT_ENUM                        OFF
#define PMC_IMPL_PART_XUSBB_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_OFF                      MK_ENUM_CONST(0)
#define PMC_IMPL_PART_XUSBB_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_ON                       MK_ENUM_CONST(1)

#define PMC_IMPL_PART_XUSBB_POWER_GATE_CONTROL_0_SRAM_RET_EN_SHIFT                      MK_SHIFT_CONST(1)
#define PMC_IMPL_PART_XUSBB_POWER_GATE_CONTROL_0_SRAM_RET_EN_FIELD                      MK_FIELD_CONST(0x1, PMC_IMPL_PART_XUSBB_POWER_GATE_CONTROL_0_SRAM_RET_EN_SHIFT)
#define PMC_IMPL_PART_XUSBB_POWER_GATE_CONTROL_0_SRAM_RET_EN_RANGE                      1:1
#define PMC_IMPL_PART_XUSBB_POWER_GATE_CONTROL_0_SRAM_RET_EN_MSB                        MK_SHIFT_CONST(1)
#define PMC_IMPL_PART_XUSBB_POWER_GATE_CONTROL_0_SRAM_RET_EN_LSB                        MK_SHIFT_CONST(1)
#define PMC_IMPL_PART_XUSBB_POWER_GATE_CONTROL_0_SRAM_RET_EN_WOFFSET                    0x0
#define PMC_IMPL_PART_XUSBB_POWER_GATE_CONTROL_0_SRAM_RET_EN_DEFAULT                    MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_XUSBB_POWER_GATE_CONTROL_0_SRAM_RET_EN_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_XUSBB_POWER_GATE_CONTROL_0_SRAM_RET_EN_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_XUSBB_POWER_GATE_CONTROL_0_SRAM_RET_EN_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_XUSBB_POWER_GATE_CONTROL_0_SRAM_RET_EN_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_XUSBB_POWER_GATE_CONTROL_0_SRAM_RET_EN_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_XUSBB_POWER_GATE_CONTROL_0_SRAM_RET_EN_INIT_ENUM                  OFF
#define PMC_IMPL_PART_XUSBB_POWER_GATE_CONTROL_0_SRAM_RET_EN_OFF                        MK_ENUM_CONST(0)
#define PMC_IMPL_PART_XUSBB_POWER_GATE_CONTROL_0_SRAM_RET_EN_ON                 MK_ENUM_CONST(1)

#define PMC_IMPL_PART_XUSBB_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SHIFT                      MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_XUSBB_POWER_GATE_CONTROL_0_LOGIC_SLEEP_FIELD                      MK_FIELD_CONST(0x1, PMC_IMPL_PART_XUSBB_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SHIFT)
#define PMC_IMPL_PART_XUSBB_POWER_GATE_CONTROL_0_LOGIC_SLEEP_RANGE                      0:0
#define PMC_IMPL_PART_XUSBB_POWER_GATE_CONTROL_0_LOGIC_SLEEP_MSB                        MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_XUSBB_POWER_GATE_CONTROL_0_LOGIC_SLEEP_LSB                        MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_XUSBB_POWER_GATE_CONTROL_0_LOGIC_SLEEP_WOFFSET                    0x0
#define PMC_IMPL_PART_XUSBB_POWER_GATE_CONTROL_0_LOGIC_SLEEP_DEFAULT                    MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_XUSBB_POWER_GATE_CONTROL_0_LOGIC_SLEEP_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_XUSBB_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_XUSBB_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_XUSBB_POWER_GATE_CONTROL_0_LOGIC_SLEEP_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_XUSBB_POWER_GATE_CONTROL_0_LOGIC_SLEEP_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_XUSBB_POWER_GATE_CONTROL_0_LOGIC_SLEEP_INIT_ENUM                  OFF
#define PMC_IMPL_PART_XUSBB_POWER_GATE_CONTROL_0_LOGIC_SLEEP_OFF                        MK_ENUM_CONST(0)
#define PMC_IMPL_PART_XUSBB_POWER_GATE_CONTROL_0_LOGIC_SLEEP_ON                 MK_ENUM_CONST(1)


// Register PMC_IMPL_PART_XUSBB_POWER_GATE_STATUS_0
#define PMC_IMPL_PART_XUSBB_POWER_GATE_STATUS_0                 MK_ADDR_CONST(0x2b4)
#define PMC_IMPL_PART_XUSBB_POWER_GATE_STATUS_0_SECURE                  0x0
#define PMC_IMPL_PART_XUSBB_POWER_GATE_STATUS_0_DUAL                    0x0
#define PMC_IMPL_PART_XUSBB_POWER_GATE_STATUS_0_SCR                     PG_XUSBB_SCR_0
#define PMC_IMPL_PART_XUSBB_POWER_GATE_STATUS_0_SCRREG                  PMC_IMPL_SCR_PG_XUSBB_SCR_0
#define PMC_IMPL_PART_XUSBB_POWER_GATE_STATUS_0_WORD_COUNT                      0x1
#define PMC_IMPL_PART_XUSBB_POWER_GATE_STATUS_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_XUSBB_POWER_GATE_STATUS_0_RESET_MASK                      MK_MASK_CONST(0x7)
#define PMC_IMPL_PART_XUSBB_POWER_GATE_STATUS_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_XUSBB_POWER_GATE_STATUS_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_XUSBB_POWER_GATE_STATUS_0_READ_MASK                       MK_MASK_CONST(0x7)
#define PMC_IMPL_PART_XUSBB_POWER_GATE_STATUS_0_WRITE_MASK                      MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_XUSBB_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SHIFT                    MK_SHIFT_CONST(2)
#define PMC_IMPL_PART_XUSBB_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_FIELD                    MK_FIELD_CONST(0x1, PMC_IMPL_PART_XUSBB_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SHIFT)
#define PMC_IMPL_PART_XUSBB_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_RANGE                    2:2
#define PMC_IMPL_PART_XUSBB_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_MSB                      MK_SHIFT_CONST(2)
#define PMC_IMPL_PART_XUSBB_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_LSB                      MK_SHIFT_CONST(2)
#define PMC_IMPL_PART_XUSBB_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_WOFFSET                  0x0
#define PMC_IMPL_PART_XUSBB_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_DEFAULT                  MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_XUSBB_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_XUSBB_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_XUSBB_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_XUSBB_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_XUSBB_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_XUSBB_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_INIT_ENUM                        OFF
#define PMC_IMPL_PART_XUSBB_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_OFF                      MK_ENUM_CONST(0)
#define PMC_IMPL_PART_XUSBB_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_ON                       MK_ENUM_CONST(1)

#define PMC_IMPL_PART_XUSBB_POWER_GATE_STATUS_0_SRAM_RET_STS_SHIFT                      MK_SHIFT_CONST(1)
#define PMC_IMPL_PART_XUSBB_POWER_GATE_STATUS_0_SRAM_RET_STS_FIELD                      MK_FIELD_CONST(0x1, PMC_IMPL_PART_XUSBB_POWER_GATE_STATUS_0_SRAM_RET_STS_SHIFT)
#define PMC_IMPL_PART_XUSBB_POWER_GATE_STATUS_0_SRAM_RET_STS_RANGE                      1:1
#define PMC_IMPL_PART_XUSBB_POWER_GATE_STATUS_0_SRAM_RET_STS_MSB                        MK_SHIFT_CONST(1)
#define PMC_IMPL_PART_XUSBB_POWER_GATE_STATUS_0_SRAM_RET_STS_LSB                        MK_SHIFT_CONST(1)
#define PMC_IMPL_PART_XUSBB_POWER_GATE_STATUS_0_SRAM_RET_STS_WOFFSET                    0x0
#define PMC_IMPL_PART_XUSBB_POWER_GATE_STATUS_0_SRAM_RET_STS_DEFAULT                    MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_XUSBB_POWER_GATE_STATUS_0_SRAM_RET_STS_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_XUSBB_POWER_GATE_STATUS_0_SRAM_RET_STS_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_XUSBB_POWER_GATE_STATUS_0_SRAM_RET_STS_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_XUSBB_POWER_GATE_STATUS_0_SRAM_RET_STS_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_XUSBB_POWER_GATE_STATUS_0_SRAM_RET_STS_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_XUSBB_POWER_GATE_STATUS_0_SRAM_RET_STS_INIT_ENUM                  OFF
#define PMC_IMPL_PART_XUSBB_POWER_GATE_STATUS_0_SRAM_RET_STS_OFF                        MK_ENUM_CONST(0)
#define PMC_IMPL_PART_XUSBB_POWER_GATE_STATUS_0_SRAM_RET_STS_ON                 MK_ENUM_CONST(1)

#define PMC_IMPL_PART_XUSBB_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SHIFT                   MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_XUSBB_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_FIELD                   MK_FIELD_CONST(0x1, PMC_IMPL_PART_XUSBB_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SHIFT)
#define PMC_IMPL_PART_XUSBB_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_RANGE                   0:0
#define PMC_IMPL_PART_XUSBB_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_MSB                     MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_XUSBB_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_LSB                     MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_XUSBB_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_WOFFSET                 0x0
#define PMC_IMPL_PART_XUSBB_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_DEFAULT                 MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_XUSBB_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_XUSBB_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_XUSBB_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_XUSBB_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_XUSBB_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_XUSBB_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_INIT_ENUM                       OFF
#define PMC_IMPL_PART_XUSBB_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_OFF                     MK_ENUM_CONST(0)
#define PMC_IMPL_PART_XUSBB_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_ON                      MK_ENUM_CONST(1)


// Register PMC_IMPL_PART_XUSBB_CLAMP_CONTROL_0
#define PMC_IMPL_PART_XUSBB_CLAMP_CONTROL_0                     MK_ADDR_CONST(0x2b8)
#define PMC_IMPL_PART_XUSBB_CLAMP_CONTROL_0_SECURE                      0x0
#define PMC_IMPL_PART_XUSBB_CLAMP_CONTROL_0_DUAL                        0x0
#define PMC_IMPL_PART_XUSBB_CLAMP_CONTROL_0_SCR                         PG_XUSBB_SCR_0
#define PMC_IMPL_PART_XUSBB_CLAMP_CONTROL_0_SCRREG                      PMC_IMPL_SCR_PG_XUSBB_SCR_0
#define PMC_IMPL_PART_XUSBB_CLAMP_CONTROL_0_WORD_COUNT                  0x1
#define PMC_IMPL_PART_XUSBB_CLAMP_CONTROL_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_XUSBB_CLAMP_CONTROL_0_RESET_MASK                  MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_XUSBB_CLAMP_CONTROL_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_XUSBB_CLAMP_CONTROL_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_XUSBB_CLAMP_CONTROL_0_READ_MASK                   MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_XUSBB_CLAMP_CONTROL_0_WRITE_MASK                  MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_XUSBB_CLAMP_CONTROL_0_CLAMP_SHIFT                 MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_XUSBB_CLAMP_CONTROL_0_CLAMP_FIELD                 MK_FIELD_CONST(0x1, PMC_IMPL_PART_XUSBB_CLAMP_CONTROL_0_CLAMP_SHIFT)
#define PMC_IMPL_PART_XUSBB_CLAMP_CONTROL_0_CLAMP_RANGE                 0:0
#define PMC_IMPL_PART_XUSBB_CLAMP_CONTROL_0_CLAMP_MSB                   MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_XUSBB_CLAMP_CONTROL_0_CLAMP_LSB                   MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_XUSBB_CLAMP_CONTROL_0_CLAMP_WOFFSET                       0x0
#define PMC_IMPL_PART_XUSBB_CLAMP_CONTROL_0_CLAMP_DEFAULT                       MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_XUSBB_CLAMP_CONTROL_0_CLAMP_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_XUSBB_CLAMP_CONTROL_0_CLAMP_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_XUSBB_CLAMP_CONTROL_0_CLAMP_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_XUSBB_CLAMP_CONTROL_0_CLAMP_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_XUSBB_CLAMP_CONTROL_0_CLAMP_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_XUSBB_CLAMP_CONTROL_0_CLAMP_INIT_ENUM                     OFF
#define PMC_IMPL_PART_XUSBB_CLAMP_CONTROL_0_CLAMP_OFF                   MK_ENUM_CONST(0)
#define PMC_IMPL_PART_XUSBB_CLAMP_CONTROL_0_CLAMP_ON                    MK_ENUM_CONST(1)


// Register PMC_IMPL_PART_XUSBC_POWER_GATE_CONTROL_0
#define PMC_IMPL_PART_XUSBC_POWER_GATE_CONTROL_0                        MK_ADDR_CONST(0x2bc)
#define PMC_IMPL_PART_XUSBC_POWER_GATE_CONTROL_0_SECURE                         0x0
#define PMC_IMPL_PART_XUSBC_POWER_GATE_CONTROL_0_DUAL                   0x0
#define PMC_IMPL_PART_XUSBC_POWER_GATE_CONTROL_0_SCR                    PG_XUSBC_SCR_0
#define PMC_IMPL_PART_XUSBC_POWER_GATE_CONTROL_0_SCRREG                         PMC_IMPL_SCR_PG_XUSBC_SCR_0
#define PMC_IMPL_PART_XUSBC_POWER_GATE_CONTROL_0_WORD_COUNT                     0x1
#define PMC_IMPL_PART_XUSBC_POWER_GATE_CONTROL_0_RESET_VAL                      MK_MASK_CONST(0x80000000)
#define PMC_IMPL_PART_XUSBC_POWER_GATE_CONTROL_0_RESET_MASK                     MK_MASK_CONST(0x80000107)
#define PMC_IMPL_PART_XUSBC_POWER_GATE_CONTROL_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_XUSBC_POWER_GATE_CONTROL_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_XUSBC_POWER_GATE_CONTROL_0_READ_MASK                      MK_MASK_CONST(0x80000107)
#define PMC_IMPL_PART_XUSBC_POWER_GATE_CONTROL_0_WRITE_MASK                     MK_MASK_CONST(0x80000105)
#define PMC_IMPL_PART_XUSBC_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SHIFT                      MK_SHIFT_CONST(31)
#define PMC_IMPL_PART_XUSBC_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_FIELD                      MK_FIELD_CONST(0x1, PMC_IMPL_PART_XUSBC_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SHIFT)
#define PMC_IMPL_PART_XUSBC_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_RANGE                      31:31
#define PMC_IMPL_PART_XUSBC_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_MSB                        MK_SHIFT_CONST(31)
#define PMC_IMPL_PART_XUSBC_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_LSB                        MK_SHIFT_CONST(31)
#define PMC_IMPL_PART_XUSBC_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_WOFFSET                    0x0
#define PMC_IMPL_PART_XUSBC_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_DEFAULT                    MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_XUSBC_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_XUSBC_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_XUSBC_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_XUSBC_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_XUSBC_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_XUSBC_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_INIT_ENUM                  ENABLE
#define PMC_IMPL_PART_XUSBC_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_DISABLE                    MK_ENUM_CONST(0)
#define PMC_IMPL_PART_XUSBC_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_ENABLE                     MK_ENUM_CONST(1)

#define PMC_IMPL_PART_XUSBC_POWER_GATE_CONTROL_0_START_SHIFT                    MK_SHIFT_CONST(8)
#define PMC_IMPL_PART_XUSBC_POWER_GATE_CONTROL_0_START_FIELD                    MK_FIELD_CONST(0x1, PMC_IMPL_PART_XUSBC_POWER_GATE_CONTROL_0_START_SHIFT)
#define PMC_IMPL_PART_XUSBC_POWER_GATE_CONTROL_0_START_RANGE                    8:8
#define PMC_IMPL_PART_XUSBC_POWER_GATE_CONTROL_0_START_MSB                      MK_SHIFT_CONST(8)
#define PMC_IMPL_PART_XUSBC_POWER_GATE_CONTROL_0_START_LSB                      MK_SHIFT_CONST(8)
#define PMC_IMPL_PART_XUSBC_POWER_GATE_CONTROL_0_START_WOFFSET                  0x0
#define PMC_IMPL_PART_XUSBC_POWER_GATE_CONTROL_0_START_DEFAULT                  MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_XUSBC_POWER_GATE_CONTROL_0_START_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_XUSBC_POWER_GATE_CONTROL_0_START_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_XUSBC_POWER_GATE_CONTROL_0_START_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_XUSBC_POWER_GATE_CONTROL_0_START_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_XUSBC_POWER_GATE_CONTROL_0_START_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_XUSBC_POWER_GATE_CONTROL_0_START_INIT_ENUM                        DONE
#define PMC_IMPL_PART_XUSBC_POWER_GATE_CONTROL_0_START_DONE                     MK_ENUM_CONST(0)
#define PMC_IMPL_PART_XUSBC_POWER_GATE_CONTROL_0_START_PENDING                  MK_ENUM_CONST(1)

#define PMC_IMPL_PART_XUSBC_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SHIFT                    MK_SHIFT_CONST(2)
#define PMC_IMPL_PART_XUSBC_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_FIELD                    MK_FIELD_CONST(0x1, PMC_IMPL_PART_XUSBC_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SHIFT)
#define PMC_IMPL_PART_XUSBC_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_RANGE                    2:2
#define PMC_IMPL_PART_XUSBC_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_MSB                      MK_SHIFT_CONST(2)
#define PMC_IMPL_PART_XUSBC_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_LSB                      MK_SHIFT_CONST(2)
#define PMC_IMPL_PART_XUSBC_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_WOFFSET                  0x0
#define PMC_IMPL_PART_XUSBC_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_DEFAULT                  MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_XUSBC_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_XUSBC_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_XUSBC_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_XUSBC_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_XUSBC_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_XUSBC_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_INIT_ENUM                        OFF
#define PMC_IMPL_PART_XUSBC_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_OFF                      MK_ENUM_CONST(0)
#define PMC_IMPL_PART_XUSBC_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_ON                       MK_ENUM_CONST(1)

#define PMC_IMPL_PART_XUSBC_POWER_GATE_CONTROL_0_SRAM_RET_EN_SHIFT                      MK_SHIFT_CONST(1)
#define PMC_IMPL_PART_XUSBC_POWER_GATE_CONTROL_0_SRAM_RET_EN_FIELD                      MK_FIELD_CONST(0x1, PMC_IMPL_PART_XUSBC_POWER_GATE_CONTROL_0_SRAM_RET_EN_SHIFT)
#define PMC_IMPL_PART_XUSBC_POWER_GATE_CONTROL_0_SRAM_RET_EN_RANGE                      1:1
#define PMC_IMPL_PART_XUSBC_POWER_GATE_CONTROL_0_SRAM_RET_EN_MSB                        MK_SHIFT_CONST(1)
#define PMC_IMPL_PART_XUSBC_POWER_GATE_CONTROL_0_SRAM_RET_EN_LSB                        MK_SHIFT_CONST(1)
#define PMC_IMPL_PART_XUSBC_POWER_GATE_CONTROL_0_SRAM_RET_EN_WOFFSET                    0x0
#define PMC_IMPL_PART_XUSBC_POWER_GATE_CONTROL_0_SRAM_RET_EN_DEFAULT                    MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_XUSBC_POWER_GATE_CONTROL_0_SRAM_RET_EN_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_XUSBC_POWER_GATE_CONTROL_0_SRAM_RET_EN_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_XUSBC_POWER_GATE_CONTROL_0_SRAM_RET_EN_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_XUSBC_POWER_GATE_CONTROL_0_SRAM_RET_EN_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_XUSBC_POWER_GATE_CONTROL_0_SRAM_RET_EN_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_XUSBC_POWER_GATE_CONTROL_0_SRAM_RET_EN_INIT_ENUM                  OFF
#define PMC_IMPL_PART_XUSBC_POWER_GATE_CONTROL_0_SRAM_RET_EN_OFF                        MK_ENUM_CONST(0)
#define PMC_IMPL_PART_XUSBC_POWER_GATE_CONTROL_0_SRAM_RET_EN_ON                 MK_ENUM_CONST(1)

#define PMC_IMPL_PART_XUSBC_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SHIFT                      MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_XUSBC_POWER_GATE_CONTROL_0_LOGIC_SLEEP_FIELD                      MK_FIELD_CONST(0x1, PMC_IMPL_PART_XUSBC_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SHIFT)
#define PMC_IMPL_PART_XUSBC_POWER_GATE_CONTROL_0_LOGIC_SLEEP_RANGE                      0:0
#define PMC_IMPL_PART_XUSBC_POWER_GATE_CONTROL_0_LOGIC_SLEEP_MSB                        MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_XUSBC_POWER_GATE_CONTROL_0_LOGIC_SLEEP_LSB                        MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_XUSBC_POWER_GATE_CONTROL_0_LOGIC_SLEEP_WOFFSET                    0x0
#define PMC_IMPL_PART_XUSBC_POWER_GATE_CONTROL_0_LOGIC_SLEEP_DEFAULT                    MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_XUSBC_POWER_GATE_CONTROL_0_LOGIC_SLEEP_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_XUSBC_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_XUSBC_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_XUSBC_POWER_GATE_CONTROL_0_LOGIC_SLEEP_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_XUSBC_POWER_GATE_CONTROL_0_LOGIC_SLEEP_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_XUSBC_POWER_GATE_CONTROL_0_LOGIC_SLEEP_INIT_ENUM                  OFF
#define PMC_IMPL_PART_XUSBC_POWER_GATE_CONTROL_0_LOGIC_SLEEP_OFF                        MK_ENUM_CONST(0)
#define PMC_IMPL_PART_XUSBC_POWER_GATE_CONTROL_0_LOGIC_SLEEP_ON                 MK_ENUM_CONST(1)


// Register PMC_IMPL_PART_XUSBC_POWER_GATE_STATUS_0
#define PMC_IMPL_PART_XUSBC_POWER_GATE_STATUS_0                 MK_ADDR_CONST(0x2c0)
#define PMC_IMPL_PART_XUSBC_POWER_GATE_STATUS_0_SECURE                  0x0
#define PMC_IMPL_PART_XUSBC_POWER_GATE_STATUS_0_DUAL                    0x0
#define PMC_IMPL_PART_XUSBC_POWER_GATE_STATUS_0_SCR                     PG_XUSBC_SCR_0
#define PMC_IMPL_PART_XUSBC_POWER_GATE_STATUS_0_SCRREG                  PMC_IMPL_SCR_PG_XUSBC_SCR_0
#define PMC_IMPL_PART_XUSBC_POWER_GATE_STATUS_0_WORD_COUNT                      0x1
#define PMC_IMPL_PART_XUSBC_POWER_GATE_STATUS_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_XUSBC_POWER_GATE_STATUS_0_RESET_MASK                      MK_MASK_CONST(0x7)
#define PMC_IMPL_PART_XUSBC_POWER_GATE_STATUS_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_XUSBC_POWER_GATE_STATUS_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_XUSBC_POWER_GATE_STATUS_0_READ_MASK                       MK_MASK_CONST(0x7)
#define PMC_IMPL_PART_XUSBC_POWER_GATE_STATUS_0_WRITE_MASK                      MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_XUSBC_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SHIFT                    MK_SHIFT_CONST(2)
#define PMC_IMPL_PART_XUSBC_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_FIELD                    MK_FIELD_CONST(0x1, PMC_IMPL_PART_XUSBC_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SHIFT)
#define PMC_IMPL_PART_XUSBC_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_RANGE                    2:2
#define PMC_IMPL_PART_XUSBC_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_MSB                      MK_SHIFT_CONST(2)
#define PMC_IMPL_PART_XUSBC_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_LSB                      MK_SHIFT_CONST(2)
#define PMC_IMPL_PART_XUSBC_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_WOFFSET                  0x0
#define PMC_IMPL_PART_XUSBC_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_DEFAULT                  MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_XUSBC_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_XUSBC_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_XUSBC_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_XUSBC_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_XUSBC_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_XUSBC_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_INIT_ENUM                        OFF
#define PMC_IMPL_PART_XUSBC_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_OFF                      MK_ENUM_CONST(0)
#define PMC_IMPL_PART_XUSBC_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_ON                       MK_ENUM_CONST(1)

#define PMC_IMPL_PART_XUSBC_POWER_GATE_STATUS_0_SRAM_RET_STS_SHIFT                      MK_SHIFT_CONST(1)
#define PMC_IMPL_PART_XUSBC_POWER_GATE_STATUS_0_SRAM_RET_STS_FIELD                      MK_FIELD_CONST(0x1, PMC_IMPL_PART_XUSBC_POWER_GATE_STATUS_0_SRAM_RET_STS_SHIFT)
#define PMC_IMPL_PART_XUSBC_POWER_GATE_STATUS_0_SRAM_RET_STS_RANGE                      1:1
#define PMC_IMPL_PART_XUSBC_POWER_GATE_STATUS_0_SRAM_RET_STS_MSB                        MK_SHIFT_CONST(1)
#define PMC_IMPL_PART_XUSBC_POWER_GATE_STATUS_0_SRAM_RET_STS_LSB                        MK_SHIFT_CONST(1)
#define PMC_IMPL_PART_XUSBC_POWER_GATE_STATUS_0_SRAM_RET_STS_WOFFSET                    0x0
#define PMC_IMPL_PART_XUSBC_POWER_GATE_STATUS_0_SRAM_RET_STS_DEFAULT                    MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_XUSBC_POWER_GATE_STATUS_0_SRAM_RET_STS_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_XUSBC_POWER_GATE_STATUS_0_SRAM_RET_STS_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_XUSBC_POWER_GATE_STATUS_0_SRAM_RET_STS_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_XUSBC_POWER_GATE_STATUS_0_SRAM_RET_STS_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_XUSBC_POWER_GATE_STATUS_0_SRAM_RET_STS_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_XUSBC_POWER_GATE_STATUS_0_SRAM_RET_STS_INIT_ENUM                  OFF
#define PMC_IMPL_PART_XUSBC_POWER_GATE_STATUS_0_SRAM_RET_STS_OFF                        MK_ENUM_CONST(0)
#define PMC_IMPL_PART_XUSBC_POWER_GATE_STATUS_0_SRAM_RET_STS_ON                 MK_ENUM_CONST(1)

#define PMC_IMPL_PART_XUSBC_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SHIFT                   MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_XUSBC_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_FIELD                   MK_FIELD_CONST(0x1, PMC_IMPL_PART_XUSBC_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SHIFT)
#define PMC_IMPL_PART_XUSBC_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_RANGE                   0:0
#define PMC_IMPL_PART_XUSBC_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_MSB                     MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_XUSBC_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_LSB                     MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_XUSBC_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_WOFFSET                 0x0
#define PMC_IMPL_PART_XUSBC_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_DEFAULT                 MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_XUSBC_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_XUSBC_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_XUSBC_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_XUSBC_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_XUSBC_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_XUSBC_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_INIT_ENUM                       OFF
#define PMC_IMPL_PART_XUSBC_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_OFF                     MK_ENUM_CONST(0)
#define PMC_IMPL_PART_XUSBC_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_ON                      MK_ENUM_CONST(1)


// Register PMC_IMPL_PART_XUSBC_CLAMP_CONTROL_0
#define PMC_IMPL_PART_XUSBC_CLAMP_CONTROL_0                     MK_ADDR_CONST(0x2c4)
#define PMC_IMPL_PART_XUSBC_CLAMP_CONTROL_0_SECURE                      0x0
#define PMC_IMPL_PART_XUSBC_CLAMP_CONTROL_0_DUAL                        0x0
#define PMC_IMPL_PART_XUSBC_CLAMP_CONTROL_0_SCR                         PG_XUSBC_SCR_0
#define PMC_IMPL_PART_XUSBC_CLAMP_CONTROL_0_SCRREG                      PMC_IMPL_SCR_PG_XUSBC_SCR_0
#define PMC_IMPL_PART_XUSBC_CLAMP_CONTROL_0_WORD_COUNT                  0x1
#define PMC_IMPL_PART_XUSBC_CLAMP_CONTROL_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_XUSBC_CLAMP_CONTROL_0_RESET_MASK                  MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_XUSBC_CLAMP_CONTROL_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_XUSBC_CLAMP_CONTROL_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_XUSBC_CLAMP_CONTROL_0_READ_MASK                   MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_XUSBC_CLAMP_CONTROL_0_WRITE_MASK                  MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_XUSBC_CLAMP_CONTROL_0_CLAMP_SHIFT                 MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_XUSBC_CLAMP_CONTROL_0_CLAMP_FIELD                 MK_FIELD_CONST(0x1, PMC_IMPL_PART_XUSBC_CLAMP_CONTROL_0_CLAMP_SHIFT)
#define PMC_IMPL_PART_XUSBC_CLAMP_CONTROL_0_CLAMP_RANGE                 0:0
#define PMC_IMPL_PART_XUSBC_CLAMP_CONTROL_0_CLAMP_MSB                   MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_XUSBC_CLAMP_CONTROL_0_CLAMP_LSB                   MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_XUSBC_CLAMP_CONTROL_0_CLAMP_WOFFSET                       0x0
#define PMC_IMPL_PART_XUSBC_CLAMP_CONTROL_0_CLAMP_DEFAULT                       MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_XUSBC_CLAMP_CONTROL_0_CLAMP_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_XUSBC_CLAMP_CONTROL_0_CLAMP_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_XUSBC_CLAMP_CONTROL_0_CLAMP_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_XUSBC_CLAMP_CONTROL_0_CLAMP_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_XUSBC_CLAMP_CONTROL_0_CLAMP_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_XUSBC_CLAMP_CONTROL_0_CLAMP_INIT_ENUM                     OFF
#define PMC_IMPL_PART_XUSBC_CLAMP_CONTROL_0_CLAMP_OFF                   MK_ENUM_CONST(0)
#define PMC_IMPL_PART_XUSBC_CLAMP_CONTROL_0_CLAMP_ON                    MK_ENUM_CONST(1)


// Reserved address 0x2c8

// Reserved address 0x2cc

// Reserved address 0x2d0

// Reserved address 0x2d4

// Reserved address 0x2d8

// Reserved address 0x2dc

// Reserved address 0x2e0

// Reserved address 0x2e4

// Reserved address 0x2e8

// Reserved address 0x2ec

// Reserved address 0x2f0

// Reserved address 0x2f4

// Reserved address 0x2f8

// Reserved address 0x2fc

// Reserved address 0x300

// Reserved address 0x304

// Reserved address 0x308

// Reserved address 0x30c

// Reserved address 0x310

// Reserved address 0x314

// Reserved address 0x318

// Reserved address 0x31c

// Reserved address 0x320

// Reserved address 0x324

// Reserved address 0x328

// Reserved address 0x32c

// Reserved address 0x330

// Reserved address 0x334

// Reserved address 0x338

// Reserved address 0x33c

// Reserved address 0x340

// Reserved address 0x344

// Reserved address 0x348

// Reserved address 0x34c

// Reserved address 0x350

// Reserved address 0x354

// Reserved address 0x358

// Reserved address 0x35c

// Reserved address 0x360

// Reserved address 0x364

// Reserved address 0x368

// Reserved address 0x36c

// Reserved address 0x370

// Reserved address 0x374

// Reserved address 0x378

// Reserved address 0x37c

// Reserved address 0x380

// Reserved address 0x384

// Register PMC_IMPL_PART_AOPG_TCM0_POWER_GATE_CONTROL_0
#define PMC_IMPL_PART_AOPG_TCM0_POWER_GATE_CONTROL_0                    MK_ADDR_CONST(0x388)
#define PMC_IMPL_PART_AOPG_TCM0_POWER_GATE_CONTROL_0_SECURE                     0x0
#define PMC_IMPL_PART_AOPG_TCM0_POWER_GATE_CONTROL_0_DUAL                       0x0
#define PMC_IMPL_PART_AOPG_TCM0_POWER_GATE_CONTROL_0_SCR                        PG_AOPG_TCM0_SCR_0
#define PMC_IMPL_PART_AOPG_TCM0_POWER_GATE_CONTROL_0_SCRREG                     PMC_IMPL_SCR_PG_AOPG_TCM0_SCR_0
#define PMC_IMPL_PART_AOPG_TCM0_POWER_GATE_CONTROL_0_WORD_COUNT                         0x1
#define PMC_IMPL_PART_AOPG_TCM0_POWER_GATE_CONTROL_0_RESET_VAL                  MK_MASK_CONST(0x80000000)
#define PMC_IMPL_PART_AOPG_TCM0_POWER_GATE_CONTROL_0_RESET_MASK                         MK_MASK_CONST(0x80000107)
#define PMC_IMPL_PART_AOPG_TCM0_POWER_GATE_CONTROL_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM0_POWER_GATE_CONTROL_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM0_POWER_GATE_CONTROL_0_READ_MASK                  MK_MASK_CONST(0x80000107)
#define PMC_IMPL_PART_AOPG_TCM0_POWER_GATE_CONTROL_0_WRITE_MASK                         MK_MASK_CONST(0x80000106)
#define PMC_IMPL_PART_AOPG_TCM0_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SHIFT                  MK_SHIFT_CONST(31)
#define PMC_IMPL_PART_AOPG_TCM0_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_FIELD                  MK_FIELD_CONST(0x1, PMC_IMPL_PART_AOPG_TCM0_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SHIFT)
#define PMC_IMPL_PART_AOPG_TCM0_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_RANGE                  31:31
#define PMC_IMPL_PART_AOPG_TCM0_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_MSB                    MK_SHIFT_CONST(31)
#define PMC_IMPL_PART_AOPG_TCM0_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_LSB                    MK_SHIFT_CONST(31)
#define PMC_IMPL_PART_AOPG_TCM0_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_WOFFSET                        0x0
#define PMC_IMPL_PART_AOPG_TCM0_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_DEFAULT                        MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AOPG_TCM0_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AOPG_TCM0_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM0_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM0_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM0_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AOPG_TCM0_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_INIT_ENUM                      ENABLE
#define PMC_IMPL_PART_AOPG_TCM0_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_DISABLE                        MK_ENUM_CONST(0)
#define PMC_IMPL_PART_AOPG_TCM0_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_ENABLE                 MK_ENUM_CONST(1)

#define PMC_IMPL_PART_AOPG_TCM0_POWER_GATE_CONTROL_0_START_SHIFT                        MK_SHIFT_CONST(8)
#define PMC_IMPL_PART_AOPG_TCM0_POWER_GATE_CONTROL_0_START_FIELD                        MK_FIELD_CONST(0x1, PMC_IMPL_PART_AOPG_TCM0_POWER_GATE_CONTROL_0_START_SHIFT)
#define PMC_IMPL_PART_AOPG_TCM0_POWER_GATE_CONTROL_0_START_RANGE                        8:8
#define PMC_IMPL_PART_AOPG_TCM0_POWER_GATE_CONTROL_0_START_MSB                  MK_SHIFT_CONST(8)
#define PMC_IMPL_PART_AOPG_TCM0_POWER_GATE_CONTROL_0_START_LSB                  MK_SHIFT_CONST(8)
#define PMC_IMPL_PART_AOPG_TCM0_POWER_GATE_CONTROL_0_START_WOFFSET                      0x0
#define PMC_IMPL_PART_AOPG_TCM0_POWER_GATE_CONTROL_0_START_DEFAULT                      MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM0_POWER_GATE_CONTROL_0_START_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AOPG_TCM0_POWER_GATE_CONTROL_0_START_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM0_POWER_GATE_CONTROL_0_START_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM0_POWER_GATE_CONTROL_0_START_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM0_POWER_GATE_CONTROL_0_START_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AOPG_TCM0_POWER_GATE_CONTROL_0_START_INIT_ENUM                    DONE
#define PMC_IMPL_PART_AOPG_TCM0_POWER_GATE_CONTROL_0_START_DONE                 MK_ENUM_CONST(0)
#define PMC_IMPL_PART_AOPG_TCM0_POWER_GATE_CONTROL_0_START_PENDING                      MK_ENUM_CONST(1)

#define PMC_IMPL_PART_AOPG_TCM0_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SHIFT                        MK_SHIFT_CONST(2)
#define PMC_IMPL_PART_AOPG_TCM0_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_FIELD                        MK_FIELD_CONST(0x1, PMC_IMPL_PART_AOPG_TCM0_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SHIFT)
#define PMC_IMPL_PART_AOPG_TCM0_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_RANGE                        2:2
#define PMC_IMPL_PART_AOPG_TCM0_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_MSB                  MK_SHIFT_CONST(2)
#define PMC_IMPL_PART_AOPG_TCM0_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_LSB                  MK_SHIFT_CONST(2)
#define PMC_IMPL_PART_AOPG_TCM0_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_WOFFSET                      0x0
#define PMC_IMPL_PART_AOPG_TCM0_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_DEFAULT                      MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM0_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AOPG_TCM0_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM0_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM0_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM0_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AOPG_TCM0_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_INIT_ENUM                    OFF
#define PMC_IMPL_PART_AOPG_TCM0_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_OFF                  MK_ENUM_CONST(0)
#define PMC_IMPL_PART_AOPG_TCM0_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_ON                   MK_ENUM_CONST(1)

#define PMC_IMPL_PART_AOPG_TCM0_POWER_GATE_CONTROL_0_SRAM_RET_EN_SHIFT                  MK_SHIFT_CONST(1)
#define PMC_IMPL_PART_AOPG_TCM0_POWER_GATE_CONTROL_0_SRAM_RET_EN_FIELD                  MK_FIELD_CONST(0x1, PMC_IMPL_PART_AOPG_TCM0_POWER_GATE_CONTROL_0_SRAM_RET_EN_SHIFT)
#define PMC_IMPL_PART_AOPG_TCM0_POWER_GATE_CONTROL_0_SRAM_RET_EN_RANGE                  1:1
#define PMC_IMPL_PART_AOPG_TCM0_POWER_GATE_CONTROL_0_SRAM_RET_EN_MSB                    MK_SHIFT_CONST(1)
#define PMC_IMPL_PART_AOPG_TCM0_POWER_GATE_CONTROL_0_SRAM_RET_EN_LSB                    MK_SHIFT_CONST(1)
#define PMC_IMPL_PART_AOPG_TCM0_POWER_GATE_CONTROL_0_SRAM_RET_EN_WOFFSET                        0x0
#define PMC_IMPL_PART_AOPG_TCM0_POWER_GATE_CONTROL_0_SRAM_RET_EN_DEFAULT                        MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM0_POWER_GATE_CONTROL_0_SRAM_RET_EN_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AOPG_TCM0_POWER_GATE_CONTROL_0_SRAM_RET_EN_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM0_POWER_GATE_CONTROL_0_SRAM_RET_EN_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM0_POWER_GATE_CONTROL_0_SRAM_RET_EN_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM0_POWER_GATE_CONTROL_0_SRAM_RET_EN_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AOPG_TCM0_POWER_GATE_CONTROL_0_SRAM_RET_EN_INIT_ENUM                      OFF
#define PMC_IMPL_PART_AOPG_TCM0_POWER_GATE_CONTROL_0_SRAM_RET_EN_OFF                    MK_ENUM_CONST(0)
#define PMC_IMPL_PART_AOPG_TCM0_POWER_GATE_CONTROL_0_SRAM_RET_EN_ON                     MK_ENUM_CONST(1)

#define PMC_IMPL_PART_AOPG_TCM0_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SHIFT                  MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_AOPG_TCM0_POWER_GATE_CONTROL_0_LOGIC_SLEEP_FIELD                  MK_FIELD_CONST(0x1, PMC_IMPL_PART_AOPG_TCM0_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SHIFT)
#define PMC_IMPL_PART_AOPG_TCM0_POWER_GATE_CONTROL_0_LOGIC_SLEEP_RANGE                  0:0
#define PMC_IMPL_PART_AOPG_TCM0_POWER_GATE_CONTROL_0_LOGIC_SLEEP_MSB                    MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_AOPG_TCM0_POWER_GATE_CONTROL_0_LOGIC_SLEEP_LSB                    MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_AOPG_TCM0_POWER_GATE_CONTROL_0_LOGIC_SLEEP_WOFFSET                        0x0
#define PMC_IMPL_PART_AOPG_TCM0_POWER_GATE_CONTROL_0_LOGIC_SLEEP_DEFAULT                        MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM0_POWER_GATE_CONTROL_0_LOGIC_SLEEP_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AOPG_TCM0_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM0_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM0_POWER_GATE_CONTROL_0_LOGIC_SLEEP_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM0_POWER_GATE_CONTROL_0_LOGIC_SLEEP_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AOPG_TCM0_POWER_GATE_CONTROL_0_LOGIC_SLEEP_INIT_ENUM                      OFF
#define PMC_IMPL_PART_AOPG_TCM0_POWER_GATE_CONTROL_0_LOGIC_SLEEP_OFF                    MK_ENUM_CONST(0)
#define PMC_IMPL_PART_AOPG_TCM0_POWER_GATE_CONTROL_0_LOGIC_SLEEP_ON                     MK_ENUM_CONST(1)


// Register PMC_IMPL_PART_AOPG_TCM0_POWER_GATE_STATUS_0
#define PMC_IMPL_PART_AOPG_TCM0_POWER_GATE_STATUS_0                     MK_ADDR_CONST(0x38c)
#define PMC_IMPL_PART_AOPG_TCM0_POWER_GATE_STATUS_0_SECURE                      0x0
#define PMC_IMPL_PART_AOPG_TCM0_POWER_GATE_STATUS_0_DUAL                        0x0
#define PMC_IMPL_PART_AOPG_TCM0_POWER_GATE_STATUS_0_SCR                         PG_AOPG_TCM0_SCR_0
#define PMC_IMPL_PART_AOPG_TCM0_POWER_GATE_STATUS_0_SCRREG                      PMC_IMPL_SCR_PG_AOPG_TCM0_SCR_0
#define PMC_IMPL_PART_AOPG_TCM0_POWER_GATE_STATUS_0_WORD_COUNT                  0x1
#define PMC_IMPL_PART_AOPG_TCM0_POWER_GATE_STATUS_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM0_POWER_GATE_STATUS_0_RESET_MASK                  MK_MASK_CONST(0x7)
#define PMC_IMPL_PART_AOPG_TCM0_POWER_GATE_STATUS_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM0_POWER_GATE_STATUS_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM0_POWER_GATE_STATUS_0_READ_MASK                   MK_MASK_CONST(0x7)
#define PMC_IMPL_PART_AOPG_TCM0_POWER_GATE_STATUS_0_WRITE_MASK                  MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM0_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SHIFT                        MK_SHIFT_CONST(2)
#define PMC_IMPL_PART_AOPG_TCM0_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_FIELD                        MK_FIELD_CONST(0x1, PMC_IMPL_PART_AOPG_TCM0_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SHIFT)
#define PMC_IMPL_PART_AOPG_TCM0_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_RANGE                        2:2
#define PMC_IMPL_PART_AOPG_TCM0_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_MSB                  MK_SHIFT_CONST(2)
#define PMC_IMPL_PART_AOPG_TCM0_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_LSB                  MK_SHIFT_CONST(2)
#define PMC_IMPL_PART_AOPG_TCM0_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_WOFFSET                      0x0
#define PMC_IMPL_PART_AOPG_TCM0_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_DEFAULT                      MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM0_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AOPG_TCM0_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM0_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM0_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM0_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AOPG_TCM0_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_INIT_ENUM                    OFF
#define PMC_IMPL_PART_AOPG_TCM0_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_OFF                  MK_ENUM_CONST(0)
#define PMC_IMPL_PART_AOPG_TCM0_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_ON                   MK_ENUM_CONST(1)

#define PMC_IMPL_PART_AOPG_TCM0_POWER_GATE_STATUS_0_SRAM_RET_STS_SHIFT                  MK_SHIFT_CONST(1)
#define PMC_IMPL_PART_AOPG_TCM0_POWER_GATE_STATUS_0_SRAM_RET_STS_FIELD                  MK_FIELD_CONST(0x1, PMC_IMPL_PART_AOPG_TCM0_POWER_GATE_STATUS_0_SRAM_RET_STS_SHIFT)
#define PMC_IMPL_PART_AOPG_TCM0_POWER_GATE_STATUS_0_SRAM_RET_STS_RANGE                  1:1
#define PMC_IMPL_PART_AOPG_TCM0_POWER_GATE_STATUS_0_SRAM_RET_STS_MSB                    MK_SHIFT_CONST(1)
#define PMC_IMPL_PART_AOPG_TCM0_POWER_GATE_STATUS_0_SRAM_RET_STS_LSB                    MK_SHIFT_CONST(1)
#define PMC_IMPL_PART_AOPG_TCM0_POWER_GATE_STATUS_0_SRAM_RET_STS_WOFFSET                        0x0
#define PMC_IMPL_PART_AOPG_TCM0_POWER_GATE_STATUS_0_SRAM_RET_STS_DEFAULT                        MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM0_POWER_GATE_STATUS_0_SRAM_RET_STS_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AOPG_TCM0_POWER_GATE_STATUS_0_SRAM_RET_STS_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM0_POWER_GATE_STATUS_0_SRAM_RET_STS_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM0_POWER_GATE_STATUS_0_SRAM_RET_STS_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM0_POWER_GATE_STATUS_0_SRAM_RET_STS_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AOPG_TCM0_POWER_GATE_STATUS_0_SRAM_RET_STS_INIT_ENUM                      OFF
#define PMC_IMPL_PART_AOPG_TCM0_POWER_GATE_STATUS_0_SRAM_RET_STS_OFF                    MK_ENUM_CONST(0)
#define PMC_IMPL_PART_AOPG_TCM0_POWER_GATE_STATUS_0_SRAM_RET_STS_ON                     MK_ENUM_CONST(1)

#define PMC_IMPL_PART_AOPG_TCM0_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SHIFT                       MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_AOPG_TCM0_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_FIELD                       MK_FIELD_CONST(0x1, PMC_IMPL_PART_AOPG_TCM0_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SHIFT)
#define PMC_IMPL_PART_AOPG_TCM0_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_RANGE                       0:0
#define PMC_IMPL_PART_AOPG_TCM0_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_MSB                 MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_AOPG_TCM0_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_LSB                 MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_AOPG_TCM0_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_WOFFSET                     0x0
#define PMC_IMPL_PART_AOPG_TCM0_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_DEFAULT                     MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM0_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AOPG_TCM0_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM0_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM0_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM0_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AOPG_TCM0_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_INIT_ENUM                   OFF
#define PMC_IMPL_PART_AOPG_TCM0_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_OFF                 MK_ENUM_CONST(0)
#define PMC_IMPL_PART_AOPG_TCM0_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_ON                  MK_ENUM_CONST(1)


// Register PMC_IMPL_PART_AOPG_TCM0_CLAMP_CONTROL_0
#define PMC_IMPL_PART_AOPG_TCM0_CLAMP_CONTROL_0                 MK_ADDR_CONST(0x390)
#define PMC_IMPL_PART_AOPG_TCM0_CLAMP_CONTROL_0_SECURE                  0x0
#define PMC_IMPL_PART_AOPG_TCM0_CLAMP_CONTROL_0_DUAL                    0x0
#define PMC_IMPL_PART_AOPG_TCM0_CLAMP_CONTROL_0_SCR                     PG_AOPG_TCM0_SCR_0
#define PMC_IMPL_PART_AOPG_TCM0_CLAMP_CONTROL_0_SCRREG                  PMC_IMPL_SCR_PG_AOPG_TCM0_SCR_0
#define PMC_IMPL_PART_AOPG_TCM0_CLAMP_CONTROL_0_WORD_COUNT                      0x1
#define PMC_IMPL_PART_AOPG_TCM0_CLAMP_CONTROL_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM0_CLAMP_CONTROL_0_RESET_MASK                      MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AOPG_TCM0_CLAMP_CONTROL_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM0_CLAMP_CONTROL_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM0_CLAMP_CONTROL_0_READ_MASK                       MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AOPG_TCM0_CLAMP_CONTROL_0_WRITE_MASK                      MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM0_CLAMP_CONTROL_0_CLAMP_SHIFT                     MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_AOPG_TCM0_CLAMP_CONTROL_0_CLAMP_FIELD                     MK_FIELD_CONST(0x1, PMC_IMPL_PART_AOPG_TCM0_CLAMP_CONTROL_0_CLAMP_SHIFT)
#define PMC_IMPL_PART_AOPG_TCM0_CLAMP_CONTROL_0_CLAMP_RANGE                     0:0
#define PMC_IMPL_PART_AOPG_TCM0_CLAMP_CONTROL_0_CLAMP_MSB                       MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_AOPG_TCM0_CLAMP_CONTROL_0_CLAMP_LSB                       MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_AOPG_TCM0_CLAMP_CONTROL_0_CLAMP_WOFFSET                   0x0
#define PMC_IMPL_PART_AOPG_TCM0_CLAMP_CONTROL_0_CLAMP_DEFAULT                   MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM0_CLAMP_CONTROL_0_CLAMP_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AOPG_TCM0_CLAMP_CONTROL_0_CLAMP_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM0_CLAMP_CONTROL_0_CLAMP_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM0_CLAMP_CONTROL_0_CLAMP_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM0_CLAMP_CONTROL_0_CLAMP_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AOPG_TCM0_CLAMP_CONTROL_0_CLAMP_INIT_ENUM                 OFF
#define PMC_IMPL_PART_AOPG_TCM0_CLAMP_CONTROL_0_CLAMP_OFF                       MK_ENUM_CONST(0)
#define PMC_IMPL_PART_AOPG_TCM0_CLAMP_CONTROL_0_CLAMP_ON                        MK_ENUM_CONST(1)


// Register PMC_IMPL_PART_AOPG_TCM1_POWER_GATE_CONTROL_0
#define PMC_IMPL_PART_AOPG_TCM1_POWER_GATE_CONTROL_0                    MK_ADDR_CONST(0x394)
#define PMC_IMPL_PART_AOPG_TCM1_POWER_GATE_CONTROL_0_SECURE                     0x0
#define PMC_IMPL_PART_AOPG_TCM1_POWER_GATE_CONTROL_0_DUAL                       0x0
#define PMC_IMPL_PART_AOPG_TCM1_POWER_GATE_CONTROL_0_SCR                        PG_AOPG_TCM1_SCR_0
#define PMC_IMPL_PART_AOPG_TCM1_POWER_GATE_CONTROL_0_SCRREG                     PMC_IMPL_SCR_PG_AOPG_TCM1_SCR_0
#define PMC_IMPL_PART_AOPG_TCM1_POWER_GATE_CONTROL_0_WORD_COUNT                         0x1
#define PMC_IMPL_PART_AOPG_TCM1_POWER_GATE_CONTROL_0_RESET_VAL                  MK_MASK_CONST(0x80000000)
#define PMC_IMPL_PART_AOPG_TCM1_POWER_GATE_CONTROL_0_RESET_MASK                         MK_MASK_CONST(0x80000107)
#define PMC_IMPL_PART_AOPG_TCM1_POWER_GATE_CONTROL_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM1_POWER_GATE_CONTROL_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM1_POWER_GATE_CONTROL_0_READ_MASK                  MK_MASK_CONST(0x80000107)
#define PMC_IMPL_PART_AOPG_TCM1_POWER_GATE_CONTROL_0_WRITE_MASK                         MK_MASK_CONST(0x80000106)
#define PMC_IMPL_PART_AOPG_TCM1_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SHIFT                  MK_SHIFT_CONST(31)
#define PMC_IMPL_PART_AOPG_TCM1_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_FIELD                  MK_FIELD_CONST(0x1, PMC_IMPL_PART_AOPG_TCM1_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SHIFT)
#define PMC_IMPL_PART_AOPG_TCM1_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_RANGE                  31:31
#define PMC_IMPL_PART_AOPG_TCM1_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_MSB                    MK_SHIFT_CONST(31)
#define PMC_IMPL_PART_AOPG_TCM1_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_LSB                    MK_SHIFT_CONST(31)
#define PMC_IMPL_PART_AOPG_TCM1_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_WOFFSET                        0x0
#define PMC_IMPL_PART_AOPG_TCM1_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_DEFAULT                        MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AOPG_TCM1_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AOPG_TCM1_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM1_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM1_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM1_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AOPG_TCM1_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_INIT_ENUM                      ENABLE
#define PMC_IMPL_PART_AOPG_TCM1_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_DISABLE                        MK_ENUM_CONST(0)
#define PMC_IMPL_PART_AOPG_TCM1_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_ENABLE                 MK_ENUM_CONST(1)

#define PMC_IMPL_PART_AOPG_TCM1_POWER_GATE_CONTROL_0_START_SHIFT                        MK_SHIFT_CONST(8)
#define PMC_IMPL_PART_AOPG_TCM1_POWER_GATE_CONTROL_0_START_FIELD                        MK_FIELD_CONST(0x1, PMC_IMPL_PART_AOPG_TCM1_POWER_GATE_CONTROL_0_START_SHIFT)
#define PMC_IMPL_PART_AOPG_TCM1_POWER_GATE_CONTROL_0_START_RANGE                        8:8
#define PMC_IMPL_PART_AOPG_TCM1_POWER_GATE_CONTROL_0_START_MSB                  MK_SHIFT_CONST(8)
#define PMC_IMPL_PART_AOPG_TCM1_POWER_GATE_CONTROL_0_START_LSB                  MK_SHIFT_CONST(8)
#define PMC_IMPL_PART_AOPG_TCM1_POWER_GATE_CONTROL_0_START_WOFFSET                      0x0
#define PMC_IMPL_PART_AOPG_TCM1_POWER_GATE_CONTROL_0_START_DEFAULT                      MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM1_POWER_GATE_CONTROL_0_START_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AOPG_TCM1_POWER_GATE_CONTROL_0_START_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM1_POWER_GATE_CONTROL_0_START_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM1_POWER_GATE_CONTROL_0_START_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM1_POWER_GATE_CONTROL_0_START_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AOPG_TCM1_POWER_GATE_CONTROL_0_START_INIT_ENUM                    DONE
#define PMC_IMPL_PART_AOPG_TCM1_POWER_GATE_CONTROL_0_START_DONE                 MK_ENUM_CONST(0)
#define PMC_IMPL_PART_AOPG_TCM1_POWER_GATE_CONTROL_0_START_PENDING                      MK_ENUM_CONST(1)

#define PMC_IMPL_PART_AOPG_TCM1_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SHIFT                        MK_SHIFT_CONST(2)
#define PMC_IMPL_PART_AOPG_TCM1_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_FIELD                        MK_FIELD_CONST(0x1, PMC_IMPL_PART_AOPG_TCM1_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SHIFT)
#define PMC_IMPL_PART_AOPG_TCM1_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_RANGE                        2:2
#define PMC_IMPL_PART_AOPG_TCM1_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_MSB                  MK_SHIFT_CONST(2)
#define PMC_IMPL_PART_AOPG_TCM1_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_LSB                  MK_SHIFT_CONST(2)
#define PMC_IMPL_PART_AOPG_TCM1_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_WOFFSET                      0x0
#define PMC_IMPL_PART_AOPG_TCM1_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_DEFAULT                      MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM1_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AOPG_TCM1_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM1_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM1_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM1_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AOPG_TCM1_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_INIT_ENUM                    OFF
#define PMC_IMPL_PART_AOPG_TCM1_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_OFF                  MK_ENUM_CONST(0)
#define PMC_IMPL_PART_AOPG_TCM1_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_ON                   MK_ENUM_CONST(1)

#define PMC_IMPL_PART_AOPG_TCM1_POWER_GATE_CONTROL_0_SRAM_RET_EN_SHIFT                  MK_SHIFT_CONST(1)
#define PMC_IMPL_PART_AOPG_TCM1_POWER_GATE_CONTROL_0_SRAM_RET_EN_FIELD                  MK_FIELD_CONST(0x1, PMC_IMPL_PART_AOPG_TCM1_POWER_GATE_CONTROL_0_SRAM_RET_EN_SHIFT)
#define PMC_IMPL_PART_AOPG_TCM1_POWER_GATE_CONTROL_0_SRAM_RET_EN_RANGE                  1:1
#define PMC_IMPL_PART_AOPG_TCM1_POWER_GATE_CONTROL_0_SRAM_RET_EN_MSB                    MK_SHIFT_CONST(1)
#define PMC_IMPL_PART_AOPG_TCM1_POWER_GATE_CONTROL_0_SRAM_RET_EN_LSB                    MK_SHIFT_CONST(1)
#define PMC_IMPL_PART_AOPG_TCM1_POWER_GATE_CONTROL_0_SRAM_RET_EN_WOFFSET                        0x0
#define PMC_IMPL_PART_AOPG_TCM1_POWER_GATE_CONTROL_0_SRAM_RET_EN_DEFAULT                        MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM1_POWER_GATE_CONTROL_0_SRAM_RET_EN_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AOPG_TCM1_POWER_GATE_CONTROL_0_SRAM_RET_EN_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM1_POWER_GATE_CONTROL_0_SRAM_RET_EN_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM1_POWER_GATE_CONTROL_0_SRAM_RET_EN_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM1_POWER_GATE_CONTROL_0_SRAM_RET_EN_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AOPG_TCM1_POWER_GATE_CONTROL_0_SRAM_RET_EN_INIT_ENUM                      OFF
#define PMC_IMPL_PART_AOPG_TCM1_POWER_GATE_CONTROL_0_SRAM_RET_EN_OFF                    MK_ENUM_CONST(0)
#define PMC_IMPL_PART_AOPG_TCM1_POWER_GATE_CONTROL_0_SRAM_RET_EN_ON                     MK_ENUM_CONST(1)

#define PMC_IMPL_PART_AOPG_TCM1_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SHIFT                  MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_AOPG_TCM1_POWER_GATE_CONTROL_0_LOGIC_SLEEP_FIELD                  MK_FIELD_CONST(0x1, PMC_IMPL_PART_AOPG_TCM1_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SHIFT)
#define PMC_IMPL_PART_AOPG_TCM1_POWER_GATE_CONTROL_0_LOGIC_SLEEP_RANGE                  0:0
#define PMC_IMPL_PART_AOPG_TCM1_POWER_GATE_CONTROL_0_LOGIC_SLEEP_MSB                    MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_AOPG_TCM1_POWER_GATE_CONTROL_0_LOGIC_SLEEP_LSB                    MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_AOPG_TCM1_POWER_GATE_CONTROL_0_LOGIC_SLEEP_WOFFSET                        0x0
#define PMC_IMPL_PART_AOPG_TCM1_POWER_GATE_CONTROL_0_LOGIC_SLEEP_DEFAULT                        MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM1_POWER_GATE_CONTROL_0_LOGIC_SLEEP_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AOPG_TCM1_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM1_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM1_POWER_GATE_CONTROL_0_LOGIC_SLEEP_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM1_POWER_GATE_CONTROL_0_LOGIC_SLEEP_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AOPG_TCM1_POWER_GATE_CONTROL_0_LOGIC_SLEEP_INIT_ENUM                      OFF
#define PMC_IMPL_PART_AOPG_TCM1_POWER_GATE_CONTROL_0_LOGIC_SLEEP_OFF                    MK_ENUM_CONST(0)
#define PMC_IMPL_PART_AOPG_TCM1_POWER_GATE_CONTROL_0_LOGIC_SLEEP_ON                     MK_ENUM_CONST(1)


// Register PMC_IMPL_PART_AOPG_TCM1_POWER_GATE_STATUS_0
#define PMC_IMPL_PART_AOPG_TCM1_POWER_GATE_STATUS_0                     MK_ADDR_CONST(0x398)
#define PMC_IMPL_PART_AOPG_TCM1_POWER_GATE_STATUS_0_SECURE                      0x0
#define PMC_IMPL_PART_AOPG_TCM1_POWER_GATE_STATUS_0_DUAL                        0x0
#define PMC_IMPL_PART_AOPG_TCM1_POWER_GATE_STATUS_0_SCR                         PG_AOPG_TCM1_SCR_0
#define PMC_IMPL_PART_AOPG_TCM1_POWER_GATE_STATUS_0_SCRREG                      PMC_IMPL_SCR_PG_AOPG_TCM1_SCR_0
#define PMC_IMPL_PART_AOPG_TCM1_POWER_GATE_STATUS_0_WORD_COUNT                  0x1
#define PMC_IMPL_PART_AOPG_TCM1_POWER_GATE_STATUS_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM1_POWER_GATE_STATUS_0_RESET_MASK                  MK_MASK_CONST(0x7)
#define PMC_IMPL_PART_AOPG_TCM1_POWER_GATE_STATUS_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM1_POWER_GATE_STATUS_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM1_POWER_GATE_STATUS_0_READ_MASK                   MK_MASK_CONST(0x7)
#define PMC_IMPL_PART_AOPG_TCM1_POWER_GATE_STATUS_0_WRITE_MASK                  MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM1_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SHIFT                        MK_SHIFT_CONST(2)
#define PMC_IMPL_PART_AOPG_TCM1_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_FIELD                        MK_FIELD_CONST(0x1, PMC_IMPL_PART_AOPG_TCM1_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SHIFT)
#define PMC_IMPL_PART_AOPG_TCM1_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_RANGE                        2:2
#define PMC_IMPL_PART_AOPG_TCM1_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_MSB                  MK_SHIFT_CONST(2)
#define PMC_IMPL_PART_AOPG_TCM1_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_LSB                  MK_SHIFT_CONST(2)
#define PMC_IMPL_PART_AOPG_TCM1_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_WOFFSET                      0x0
#define PMC_IMPL_PART_AOPG_TCM1_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_DEFAULT                      MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM1_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AOPG_TCM1_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM1_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM1_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM1_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AOPG_TCM1_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_INIT_ENUM                    OFF
#define PMC_IMPL_PART_AOPG_TCM1_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_OFF                  MK_ENUM_CONST(0)
#define PMC_IMPL_PART_AOPG_TCM1_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_ON                   MK_ENUM_CONST(1)

#define PMC_IMPL_PART_AOPG_TCM1_POWER_GATE_STATUS_0_SRAM_RET_STS_SHIFT                  MK_SHIFT_CONST(1)
#define PMC_IMPL_PART_AOPG_TCM1_POWER_GATE_STATUS_0_SRAM_RET_STS_FIELD                  MK_FIELD_CONST(0x1, PMC_IMPL_PART_AOPG_TCM1_POWER_GATE_STATUS_0_SRAM_RET_STS_SHIFT)
#define PMC_IMPL_PART_AOPG_TCM1_POWER_GATE_STATUS_0_SRAM_RET_STS_RANGE                  1:1
#define PMC_IMPL_PART_AOPG_TCM1_POWER_GATE_STATUS_0_SRAM_RET_STS_MSB                    MK_SHIFT_CONST(1)
#define PMC_IMPL_PART_AOPG_TCM1_POWER_GATE_STATUS_0_SRAM_RET_STS_LSB                    MK_SHIFT_CONST(1)
#define PMC_IMPL_PART_AOPG_TCM1_POWER_GATE_STATUS_0_SRAM_RET_STS_WOFFSET                        0x0
#define PMC_IMPL_PART_AOPG_TCM1_POWER_GATE_STATUS_0_SRAM_RET_STS_DEFAULT                        MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM1_POWER_GATE_STATUS_0_SRAM_RET_STS_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AOPG_TCM1_POWER_GATE_STATUS_0_SRAM_RET_STS_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM1_POWER_GATE_STATUS_0_SRAM_RET_STS_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM1_POWER_GATE_STATUS_0_SRAM_RET_STS_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM1_POWER_GATE_STATUS_0_SRAM_RET_STS_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AOPG_TCM1_POWER_GATE_STATUS_0_SRAM_RET_STS_INIT_ENUM                      OFF
#define PMC_IMPL_PART_AOPG_TCM1_POWER_GATE_STATUS_0_SRAM_RET_STS_OFF                    MK_ENUM_CONST(0)
#define PMC_IMPL_PART_AOPG_TCM1_POWER_GATE_STATUS_0_SRAM_RET_STS_ON                     MK_ENUM_CONST(1)

#define PMC_IMPL_PART_AOPG_TCM1_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SHIFT                       MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_AOPG_TCM1_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_FIELD                       MK_FIELD_CONST(0x1, PMC_IMPL_PART_AOPG_TCM1_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SHIFT)
#define PMC_IMPL_PART_AOPG_TCM1_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_RANGE                       0:0
#define PMC_IMPL_PART_AOPG_TCM1_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_MSB                 MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_AOPG_TCM1_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_LSB                 MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_AOPG_TCM1_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_WOFFSET                     0x0
#define PMC_IMPL_PART_AOPG_TCM1_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_DEFAULT                     MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM1_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AOPG_TCM1_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM1_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM1_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM1_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AOPG_TCM1_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_INIT_ENUM                   OFF
#define PMC_IMPL_PART_AOPG_TCM1_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_OFF                 MK_ENUM_CONST(0)
#define PMC_IMPL_PART_AOPG_TCM1_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_ON                  MK_ENUM_CONST(1)


// Register PMC_IMPL_PART_AOPG_TCM1_CLAMP_CONTROL_0
#define PMC_IMPL_PART_AOPG_TCM1_CLAMP_CONTROL_0                 MK_ADDR_CONST(0x39c)
#define PMC_IMPL_PART_AOPG_TCM1_CLAMP_CONTROL_0_SECURE                  0x0
#define PMC_IMPL_PART_AOPG_TCM1_CLAMP_CONTROL_0_DUAL                    0x0
#define PMC_IMPL_PART_AOPG_TCM1_CLAMP_CONTROL_0_SCR                     PG_AOPG_TCM1_SCR_0
#define PMC_IMPL_PART_AOPG_TCM1_CLAMP_CONTROL_0_SCRREG                  PMC_IMPL_SCR_PG_AOPG_TCM1_SCR_0
#define PMC_IMPL_PART_AOPG_TCM1_CLAMP_CONTROL_0_WORD_COUNT                      0x1
#define PMC_IMPL_PART_AOPG_TCM1_CLAMP_CONTROL_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM1_CLAMP_CONTROL_0_RESET_MASK                      MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AOPG_TCM1_CLAMP_CONTROL_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM1_CLAMP_CONTROL_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM1_CLAMP_CONTROL_0_READ_MASK                       MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AOPG_TCM1_CLAMP_CONTROL_0_WRITE_MASK                      MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM1_CLAMP_CONTROL_0_CLAMP_SHIFT                     MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_AOPG_TCM1_CLAMP_CONTROL_0_CLAMP_FIELD                     MK_FIELD_CONST(0x1, PMC_IMPL_PART_AOPG_TCM1_CLAMP_CONTROL_0_CLAMP_SHIFT)
#define PMC_IMPL_PART_AOPG_TCM1_CLAMP_CONTROL_0_CLAMP_RANGE                     0:0
#define PMC_IMPL_PART_AOPG_TCM1_CLAMP_CONTROL_0_CLAMP_MSB                       MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_AOPG_TCM1_CLAMP_CONTROL_0_CLAMP_LSB                       MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_AOPG_TCM1_CLAMP_CONTROL_0_CLAMP_WOFFSET                   0x0
#define PMC_IMPL_PART_AOPG_TCM1_CLAMP_CONTROL_0_CLAMP_DEFAULT                   MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM1_CLAMP_CONTROL_0_CLAMP_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AOPG_TCM1_CLAMP_CONTROL_0_CLAMP_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM1_CLAMP_CONTROL_0_CLAMP_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM1_CLAMP_CONTROL_0_CLAMP_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM1_CLAMP_CONTROL_0_CLAMP_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AOPG_TCM1_CLAMP_CONTROL_0_CLAMP_INIT_ENUM                 OFF
#define PMC_IMPL_PART_AOPG_TCM1_CLAMP_CONTROL_0_CLAMP_OFF                       MK_ENUM_CONST(0)
#define PMC_IMPL_PART_AOPG_TCM1_CLAMP_CONTROL_0_CLAMP_ON                        MK_ENUM_CONST(1)


// Register PMC_IMPL_PART_AOPG_TCM2_POWER_GATE_CONTROL_0
#define PMC_IMPL_PART_AOPG_TCM2_POWER_GATE_CONTROL_0                    MK_ADDR_CONST(0x3a0)
#define PMC_IMPL_PART_AOPG_TCM2_POWER_GATE_CONTROL_0_SECURE                     0x0
#define PMC_IMPL_PART_AOPG_TCM2_POWER_GATE_CONTROL_0_DUAL                       0x0
#define PMC_IMPL_PART_AOPG_TCM2_POWER_GATE_CONTROL_0_SCR                        PG_AOPG_TCM2_SCR_0
#define PMC_IMPL_PART_AOPG_TCM2_POWER_GATE_CONTROL_0_SCRREG                     PMC_IMPL_SCR_PG_AOPG_TCM2_SCR_0
#define PMC_IMPL_PART_AOPG_TCM2_POWER_GATE_CONTROL_0_WORD_COUNT                         0x1
#define PMC_IMPL_PART_AOPG_TCM2_POWER_GATE_CONTROL_0_RESET_VAL                  MK_MASK_CONST(0x80000000)
#define PMC_IMPL_PART_AOPG_TCM2_POWER_GATE_CONTROL_0_RESET_MASK                         MK_MASK_CONST(0x80000107)
#define PMC_IMPL_PART_AOPG_TCM2_POWER_GATE_CONTROL_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM2_POWER_GATE_CONTROL_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM2_POWER_GATE_CONTROL_0_READ_MASK                  MK_MASK_CONST(0x80000107)
#define PMC_IMPL_PART_AOPG_TCM2_POWER_GATE_CONTROL_0_WRITE_MASK                         MK_MASK_CONST(0x80000106)
#define PMC_IMPL_PART_AOPG_TCM2_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SHIFT                  MK_SHIFT_CONST(31)
#define PMC_IMPL_PART_AOPG_TCM2_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_FIELD                  MK_FIELD_CONST(0x1, PMC_IMPL_PART_AOPG_TCM2_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SHIFT)
#define PMC_IMPL_PART_AOPG_TCM2_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_RANGE                  31:31
#define PMC_IMPL_PART_AOPG_TCM2_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_MSB                    MK_SHIFT_CONST(31)
#define PMC_IMPL_PART_AOPG_TCM2_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_LSB                    MK_SHIFT_CONST(31)
#define PMC_IMPL_PART_AOPG_TCM2_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_WOFFSET                        0x0
#define PMC_IMPL_PART_AOPG_TCM2_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_DEFAULT                        MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AOPG_TCM2_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AOPG_TCM2_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM2_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM2_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM2_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AOPG_TCM2_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_INIT_ENUM                      ENABLE
#define PMC_IMPL_PART_AOPG_TCM2_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_DISABLE                        MK_ENUM_CONST(0)
#define PMC_IMPL_PART_AOPG_TCM2_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_ENABLE                 MK_ENUM_CONST(1)

#define PMC_IMPL_PART_AOPG_TCM2_POWER_GATE_CONTROL_0_START_SHIFT                        MK_SHIFT_CONST(8)
#define PMC_IMPL_PART_AOPG_TCM2_POWER_GATE_CONTROL_0_START_FIELD                        MK_FIELD_CONST(0x1, PMC_IMPL_PART_AOPG_TCM2_POWER_GATE_CONTROL_0_START_SHIFT)
#define PMC_IMPL_PART_AOPG_TCM2_POWER_GATE_CONTROL_0_START_RANGE                        8:8
#define PMC_IMPL_PART_AOPG_TCM2_POWER_GATE_CONTROL_0_START_MSB                  MK_SHIFT_CONST(8)
#define PMC_IMPL_PART_AOPG_TCM2_POWER_GATE_CONTROL_0_START_LSB                  MK_SHIFT_CONST(8)
#define PMC_IMPL_PART_AOPG_TCM2_POWER_GATE_CONTROL_0_START_WOFFSET                      0x0
#define PMC_IMPL_PART_AOPG_TCM2_POWER_GATE_CONTROL_0_START_DEFAULT                      MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM2_POWER_GATE_CONTROL_0_START_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AOPG_TCM2_POWER_GATE_CONTROL_0_START_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM2_POWER_GATE_CONTROL_0_START_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM2_POWER_GATE_CONTROL_0_START_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM2_POWER_GATE_CONTROL_0_START_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AOPG_TCM2_POWER_GATE_CONTROL_0_START_INIT_ENUM                    DONE
#define PMC_IMPL_PART_AOPG_TCM2_POWER_GATE_CONTROL_0_START_DONE                 MK_ENUM_CONST(0)
#define PMC_IMPL_PART_AOPG_TCM2_POWER_GATE_CONTROL_0_START_PENDING                      MK_ENUM_CONST(1)

#define PMC_IMPL_PART_AOPG_TCM2_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SHIFT                        MK_SHIFT_CONST(2)
#define PMC_IMPL_PART_AOPG_TCM2_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_FIELD                        MK_FIELD_CONST(0x1, PMC_IMPL_PART_AOPG_TCM2_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SHIFT)
#define PMC_IMPL_PART_AOPG_TCM2_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_RANGE                        2:2
#define PMC_IMPL_PART_AOPG_TCM2_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_MSB                  MK_SHIFT_CONST(2)
#define PMC_IMPL_PART_AOPG_TCM2_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_LSB                  MK_SHIFT_CONST(2)
#define PMC_IMPL_PART_AOPG_TCM2_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_WOFFSET                      0x0
#define PMC_IMPL_PART_AOPG_TCM2_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_DEFAULT                      MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM2_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AOPG_TCM2_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM2_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM2_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM2_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AOPG_TCM2_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_INIT_ENUM                    OFF
#define PMC_IMPL_PART_AOPG_TCM2_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_OFF                  MK_ENUM_CONST(0)
#define PMC_IMPL_PART_AOPG_TCM2_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_ON                   MK_ENUM_CONST(1)

#define PMC_IMPL_PART_AOPG_TCM2_POWER_GATE_CONTROL_0_SRAM_RET_EN_SHIFT                  MK_SHIFT_CONST(1)
#define PMC_IMPL_PART_AOPG_TCM2_POWER_GATE_CONTROL_0_SRAM_RET_EN_FIELD                  MK_FIELD_CONST(0x1, PMC_IMPL_PART_AOPG_TCM2_POWER_GATE_CONTROL_0_SRAM_RET_EN_SHIFT)
#define PMC_IMPL_PART_AOPG_TCM2_POWER_GATE_CONTROL_0_SRAM_RET_EN_RANGE                  1:1
#define PMC_IMPL_PART_AOPG_TCM2_POWER_GATE_CONTROL_0_SRAM_RET_EN_MSB                    MK_SHIFT_CONST(1)
#define PMC_IMPL_PART_AOPG_TCM2_POWER_GATE_CONTROL_0_SRAM_RET_EN_LSB                    MK_SHIFT_CONST(1)
#define PMC_IMPL_PART_AOPG_TCM2_POWER_GATE_CONTROL_0_SRAM_RET_EN_WOFFSET                        0x0
#define PMC_IMPL_PART_AOPG_TCM2_POWER_GATE_CONTROL_0_SRAM_RET_EN_DEFAULT                        MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM2_POWER_GATE_CONTROL_0_SRAM_RET_EN_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AOPG_TCM2_POWER_GATE_CONTROL_0_SRAM_RET_EN_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM2_POWER_GATE_CONTROL_0_SRAM_RET_EN_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM2_POWER_GATE_CONTROL_0_SRAM_RET_EN_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM2_POWER_GATE_CONTROL_0_SRAM_RET_EN_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AOPG_TCM2_POWER_GATE_CONTROL_0_SRAM_RET_EN_INIT_ENUM                      OFF
#define PMC_IMPL_PART_AOPG_TCM2_POWER_GATE_CONTROL_0_SRAM_RET_EN_OFF                    MK_ENUM_CONST(0)
#define PMC_IMPL_PART_AOPG_TCM2_POWER_GATE_CONTROL_0_SRAM_RET_EN_ON                     MK_ENUM_CONST(1)

#define PMC_IMPL_PART_AOPG_TCM2_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SHIFT                  MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_AOPG_TCM2_POWER_GATE_CONTROL_0_LOGIC_SLEEP_FIELD                  MK_FIELD_CONST(0x1, PMC_IMPL_PART_AOPG_TCM2_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SHIFT)
#define PMC_IMPL_PART_AOPG_TCM2_POWER_GATE_CONTROL_0_LOGIC_SLEEP_RANGE                  0:0
#define PMC_IMPL_PART_AOPG_TCM2_POWER_GATE_CONTROL_0_LOGIC_SLEEP_MSB                    MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_AOPG_TCM2_POWER_GATE_CONTROL_0_LOGIC_SLEEP_LSB                    MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_AOPG_TCM2_POWER_GATE_CONTROL_0_LOGIC_SLEEP_WOFFSET                        0x0
#define PMC_IMPL_PART_AOPG_TCM2_POWER_GATE_CONTROL_0_LOGIC_SLEEP_DEFAULT                        MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM2_POWER_GATE_CONTROL_0_LOGIC_SLEEP_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AOPG_TCM2_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM2_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM2_POWER_GATE_CONTROL_0_LOGIC_SLEEP_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM2_POWER_GATE_CONTROL_0_LOGIC_SLEEP_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AOPG_TCM2_POWER_GATE_CONTROL_0_LOGIC_SLEEP_INIT_ENUM                      OFF
#define PMC_IMPL_PART_AOPG_TCM2_POWER_GATE_CONTROL_0_LOGIC_SLEEP_OFF                    MK_ENUM_CONST(0)
#define PMC_IMPL_PART_AOPG_TCM2_POWER_GATE_CONTROL_0_LOGIC_SLEEP_ON                     MK_ENUM_CONST(1)


// Register PMC_IMPL_PART_AOPG_TCM2_POWER_GATE_STATUS_0
#define PMC_IMPL_PART_AOPG_TCM2_POWER_GATE_STATUS_0                     MK_ADDR_CONST(0x3a4)
#define PMC_IMPL_PART_AOPG_TCM2_POWER_GATE_STATUS_0_SECURE                      0x0
#define PMC_IMPL_PART_AOPG_TCM2_POWER_GATE_STATUS_0_DUAL                        0x0
#define PMC_IMPL_PART_AOPG_TCM2_POWER_GATE_STATUS_0_SCR                         PG_AOPG_TCM2_SCR_0
#define PMC_IMPL_PART_AOPG_TCM2_POWER_GATE_STATUS_0_SCRREG                      PMC_IMPL_SCR_PG_AOPG_TCM2_SCR_0
#define PMC_IMPL_PART_AOPG_TCM2_POWER_GATE_STATUS_0_WORD_COUNT                  0x1
#define PMC_IMPL_PART_AOPG_TCM2_POWER_GATE_STATUS_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM2_POWER_GATE_STATUS_0_RESET_MASK                  MK_MASK_CONST(0x7)
#define PMC_IMPL_PART_AOPG_TCM2_POWER_GATE_STATUS_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM2_POWER_GATE_STATUS_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM2_POWER_GATE_STATUS_0_READ_MASK                   MK_MASK_CONST(0x7)
#define PMC_IMPL_PART_AOPG_TCM2_POWER_GATE_STATUS_0_WRITE_MASK                  MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM2_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SHIFT                        MK_SHIFT_CONST(2)
#define PMC_IMPL_PART_AOPG_TCM2_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_FIELD                        MK_FIELD_CONST(0x1, PMC_IMPL_PART_AOPG_TCM2_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SHIFT)
#define PMC_IMPL_PART_AOPG_TCM2_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_RANGE                        2:2
#define PMC_IMPL_PART_AOPG_TCM2_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_MSB                  MK_SHIFT_CONST(2)
#define PMC_IMPL_PART_AOPG_TCM2_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_LSB                  MK_SHIFT_CONST(2)
#define PMC_IMPL_PART_AOPG_TCM2_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_WOFFSET                      0x0
#define PMC_IMPL_PART_AOPG_TCM2_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_DEFAULT                      MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM2_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AOPG_TCM2_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM2_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM2_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM2_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AOPG_TCM2_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_INIT_ENUM                    OFF
#define PMC_IMPL_PART_AOPG_TCM2_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_OFF                  MK_ENUM_CONST(0)
#define PMC_IMPL_PART_AOPG_TCM2_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_ON                   MK_ENUM_CONST(1)

#define PMC_IMPL_PART_AOPG_TCM2_POWER_GATE_STATUS_0_SRAM_RET_STS_SHIFT                  MK_SHIFT_CONST(1)
#define PMC_IMPL_PART_AOPG_TCM2_POWER_GATE_STATUS_0_SRAM_RET_STS_FIELD                  MK_FIELD_CONST(0x1, PMC_IMPL_PART_AOPG_TCM2_POWER_GATE_STATUS_0_SRAM_RET_STS_SHIFT)
#define PMC_IMPL_PART_AOPG_TCM2_POWER_GATE_STATUS_0_SRAM_RET_STS_RANGE                  1:1
#define PMC_IMPL_PART_AOPG_TCM2_POWER_GATE_STATUS_0_SRAM_RET_STS_MSB                    MK_SHIFT_CONST(1)
#define PMC_IMPL_PART_AOPG_TCM2_POWER_GATE_STATUS_0_SRAM_RET_STS_LSB                    MK_SHIFT_CONST(1)
#define PMC_IMPL_PART_AOPG_TCM2_POWER_GATE_STATUS_0_SRAM_RET_STS_WOFFSET                        0x0
#define PMC_IMPL_PART_AOPG_TCM2_POWER_GATE_STATUS_0_SRAM_RET_STS_DEFAULT                        MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM2_POWER_GATE_STATUS_0_SRAM_RET_STS_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AOPG_TCM2_POWER_GATE_STATUS_0_SRAM_RET_STS_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM2_POWER_GATE_STATUS_0_SRAM_RET_STS_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM2_POWER_GATE_STATUS_0_SRAM_RET_STS_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM2_POWER_GATE_STATUS_0_SRAM_RET_STS_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AOPG_TCM2_POWER_GATE_STATUS_0_SRAM_RET_STS_INIT_ENUM                      OFF
#define PMC_IMPL_PART_AOPG_TCM2_POWER_GATE_STATUS_0_SRAM_RET_STS_OFF                    MK_ENUM_CONST(0)
#define PMC_IMPL_PART_AOPG_TCM2_POWER_GATE_STATUS_0_SRAM_RET_STS_ON                     MK_ENUM_CONST(1)

#define PMC_IMPL_PART_AOPG_TCM2_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SHIFT                       MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_AOPG_TCM2_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_FIELD                       MK_FIELD_CONST(0x1, PMC_IMPL_PART_AOPG_TCM2_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SHIFT)
#define PMC_IMPL_PART_AOPG_TCM2_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_RANGE                       0:0
#define PMC_IMPL_PART_AOPG_TCM2_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_MSB                 MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_AOPG_TCM2_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_LSB                 MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_AOPG_TCM2_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_WOFFSET                     0x0
#define PMC_IMPL_PART_AOPG_TCM2_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_DEFAULT                     MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM2_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AOPG_TCM2_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM2_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM2_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM2_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AOPG_TCM2_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_INIT_ENUM                   OFF
#define PMC_IMPL_PART_AOPG_TCM2_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_OFF                 MK_ENUM_CONST(0)
#define PMC_IMPL_PART_AOPG_TCM2_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_ON                  MK_ENUM_CONST(1)


// Register PMC_IMPL_PART_AOPG_TCM2_CLAMP_CONTROL_0
#define PMC_IMPL_PART_AOPG_TCM2_CLAMP_CONTROL_0                 MK_ADDR_CONST(0x3a8)
#define PMC_IMPL_PART_AOPG_TCM2_CLAMP_CONTROL_0_SECURE                  0x0
#define PMC_IMPL_PART_AOPG_TCM2_CLAMP_CONTROL_0_DUAL                    0x0
#define PMC_IMPL_PART_AOPG_TCM2_CLAMP_CONTROL_0_SCR                     PG_AOPG_TCM2_SCR_0
#define PMC_IMPL_PART_AOPG_TCM2_CLAMP_CONTROL_0_SCRREG                  PMC_IMPL_SCR_PG_AOPG_TCM2_SCR_0
#define PMC_IMPL_PART_AOPG_TCM2_CLAMP_CONTROL_0_WORD_COUNT                      0x1
#define PMC_IMPL_PART_AOPG_TCM2_CLAMP_CONTROL_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM2_CLAMP_CONTROL_0_RESET_MASK                      MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AOPG_TCM2_CLAMP_CONTROL_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM2_CLAMP_CONTROL_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM2_CLAMP_CONTROL_0_READ_MASK                       MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AOPG_TCM2_CLAMP_CONTROL_0_WRITE_MASK                      MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM2_CLAMP_CONTROL_0_CLAMP_SHIFT                     MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_AOPG_TCM2_CLAMP_CONTROL_0_CLAMP_FIELD                     MK_FIELD_CONST(0x1, PMC_IMPL_PART_AOPG_TCM2_CLAMP_CONTROL_0_CLAMP_SHIFT)
#define PMC_IMPL_PART_AOPG_TCM2_CLAMP_CONTROL_0_CLAMP_RANGE                     0:0
#define PMC_IMPL_PART_AOPG_TCM2_CLAMP_CONTROL_0_CLAMP_MSB                       MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_AOPG_TCM2_CLAMP_CONTROL_0_CLAMP_LSB                       MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_AOPG_TCM2_CLAMP_CONTROL_0_CLAMP_WOFFSET                   0x0
#define PMC_IMPL_PART_AOPG_TCM2_CLAMP_CONTROL_0_CLAMP_DEFAULT                   MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM2_CLAMP_CONTROL_0_CLAMP_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AOPG_TCM2_CLAMP_CONTROL_0_CLAMP_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM2_CLAMP_CONTROL_0_CLAMP_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM2_CLAMP_CONTROL_0_CLAMP_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM2_CLAMP_CONTROL_0_CLAMP_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AOPG_TCM2_CLAMP_CONTROL_0_CLAMP_INIT_ENUM                 OFF
#define PMC_IMPL_PART_AOPG_TCM2_CLAMP_CONTROL_0_CLAMP_OFF                       MK_ENUM_CONST(0)
#define PMC_IMPL_PART_AOPG_TCM2_CLAMP_CONTROL_0_CLAMP_ON                        MK_ENUM_CONST(1)


// Register PMC_IMPL_PART_AOPG_TCM3_POWER_GATE_CONTROL_0
#define PMC_IMPL_PART_AOPG_TCM3_POWER_GATE_CONTROL_0                    MK_ADDR_CONST(0x3ac)
#define PMC_IMPL_PART_AOPG_TCM3_POWER_GATE_CONTROL_0_SECURE                     0x0
#define PMC_IMPL_PART_AOPG_TCM3_POWER_GATE_CONTROL_0_DUAL                       0x0
#define PMC_IMPL_PART_AOPG_TCM3_POWER_GATE_CONTROL_0_SCR                        PG_AOPG_TCM3_SCR_0
#define PMC_IMPL_PART_AOPG_TCM3_POWER_GATE_CONTROL_0_SCRREG                     PMC_IMPL_SCR_PG_AOPG_TCM3_SCR_0
#define PMC_IMPL_PART_AOPG_TCM3_POWER_GATE_CONTROL_0_WORD_COUNT                         0x1
#define PMC_IMPL_PART_AOPG_TCM3_POWER_GATE_CONTROL_0_RESET_VAL                  MK_MASK_CONST(0x80000000)
#define PMC_IMPL_PART_AOPG_TCM3_POWER_GATE_CONTROL_0_RESET_MASK                         MK_MASK_CONST(0x80000107)
#define PMC_IMPL_PART_AOPG_TCM3_POWER_GATE_CONTROL_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM3_POWER_GATE_CONTROL_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM3_POWER_GATE_CONTROL_0_READ_MASK                  MK_MASK_CONST(0x80000107)
#define PMC_IMPL_PART_AOPG_TCM3_POWER_GATE_CONTROL_0_WRITE_MASK                         MK_MASK_CONST(0x80000106)
#define PMC_IMPL_PART_AOPG_TCM3_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SHIFT                  MK_SHIFT_CONST(31)
#define PMC_IMPL_PART_AOPG_TCM3_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_FIELD                  MK_FIELD_CONST(0x1, PMC_IMPL_PART_AOPG_TCM3_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SHIFT)
#define PMC_IMPL_PART_AOPG_TCM3_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_RANGE                  31:31
#define PMC_IMPL_PART_AOPG_TCM3_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_MSB                    MK_SHIFT_CONST(31)
#define PMC_IMPL_PART_AOPG_TCM3_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_LSB                    MK_SHIFT_CONST(31)
#define PMC_IMPL_PART_AOPG_TCM3_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_WOFFSET                        0x0
#define PMC_IMPL_PART_AOPG_TCM3_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_DEFAULT                        MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AOPG_TCM3_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AOPG_TCM3_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM3_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM3_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM3_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AOPG_TCM3_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_INIT_ENUM                      ENABLE
#define PMC_IMPL_PART_AOPG_TCM3_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_DISABLE                        MK_ENUM_CONST(0)
#define PMC_IMPL_PART_AOPG_TCM3_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_ENABLE                 MK_ENUM_CONST(1)

#define PMC_IMPL_PART_AOPG_TCM3_POWER_GATE_CONTROL_0_START_SHIFT                        MK_SHIFT_CONST(8)
#define PMC_IMPL_PART_AOPG_TCM3_POWER_GATE_CONTROL_0_START_FIELD                        MK_FIELD_CONST(0x1, PMC_IMPL_PART_AOPG_TCM3_POWER_GATE_CONTROL_0_START_SHIFT)
#define PMC_IMPL_PART_AOPG_TCM3_POWER_GATE_CONTROL_0_START_RANGE                        8:8
#define PMC_IMPL_PART_AOPG_TCM3_POWER_GATE_CONTROL_0_START_MSB                  MK_SHIFT_CONST(8)
#define PMC_IMPL_PART_AOPG_TCM3_POWER_GATE_CONTROL_0_START_LSB                  MK_SHIFT_CONST(8)
#define PMC_IMPL_PART_AOPG_TCM3_POWER_GATE_CONTROL_0_START_WOFFSET                      0x0
#define PMC_IMPL_PART_AOPG_TCM3_POWER_GATE_CONTROL_0_START_DEFAULT                      MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM3_POWER_GATE_CONTROL_0_START_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AOPG_TCM3_POWER_GATE_CONTROL_0_START_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM3_POWER_GATE_CONTROL_0_START_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM3_POWER_GATE_CONTROL_0_START_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM3_POWER_GATE_CONTROL_0_START_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AOPG_TCM3_POWER_GATE_CONTROL_0_START_INIT_ENUM                    DONE
#define PMC_IMPL_PART_AOPG_TCM3_POWER_GATE_CONTROL_0_START_DONE                 MK_ENUM_CONST(0)
#define PMC_IMPL_PART_AOPG_TCM3_POWER_GATE_CONTROL_0_START_PENDING                      MK_ENUM_CONST(1)

#define PMC_IMPL_PART_AOPG_TCM3_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SHIFT                        MK_SHIFT_CONST(2)
#define PMC_IMPL_PART_AOPG_TCM3_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_FIELD                        MK_FIELD_CONST(0x1, PMC_IMPL_PART_AOPG_TCM3_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SHIFT)
#define PMC_IMPL_PART_AOPG_TCM3_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_RANGE                        2:2
#define PMC_IMPL_PART_AOPG_TCM3_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_MSB                  MK_SHIFT_CONST(2)
#define PMC_IMPL_PART_AOPG_TCM3_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_LSB                  MK_SHIFT_CONST(2)
#define PMC_IMPL_PART_AOPG_TCM3_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_WOFFSET                      0x0
#define PMC_IMPL_PART_AOPG_TCM3_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_DEFAULT                      MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM3_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AOPG_TCM3_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM3_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM3_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM3_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AOPG_TCM3_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_INIT_ENUM                    OFF
#define PMC_IMPL_PART_AOPG_TCM3_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_OFF                  MK_ENUM_CONST(0)
#define PMC_IMPL_PART_AOPG_TCM3_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_ON                   MK_ENUM_CONST(1)

#define PMC_IMPL_PART_AOPG_TCM3_POWER_GATE_CONTROL_0_SRAM_RET_EN_SHIFT                  MK_SHIFT_CONST(1)
#define PMC_IMPL_PART_AOPG_TCM3_POWER_GATE_CONTROL_0_SRAM_RET_EN_FIELD                  MK_FIELD_CONST(0x1, PMC_IMPL_PART_AOPG_TCM3_POWER_GATE_CONTROL_0_SRAM_RET_EN_SHIFT)
#define PMC_IMPL_PART_AOPG_TCM3_POWER_GATE_CONTROL_0_SRAM_RET_EN_RANGE                  1:1
#define PMC_IMPL_PART_AOPG_TCM3_POWER_GATE_CONTROL_0_SRAM_RET_EN_MSB                    MK_SHIFT_CONST(1)
#define PMC_IMPL_PART_AOPG_TCM3_POWER_GATE_CONTROL_0_SRAM_RET_EN_LSB                    MK_SHIFT_CONST(1)
#define PMC_IMPL_PART_AOPG_TCM3_POWER_GATE_CONTROL_0_SRAM_RET_EN_WOFFSET                        0x0
#define PMC_IMPL_PART_AOPG_TCM3_POWER_GATE_CONTROL_0_SRAM_RET_EN_DEFAULT                        MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM3_POWER_GATE_CONTROL_0_SRAM_RET_EN_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AOPG_TCM3_POWER_GATE_CONTROL_0_SRAM_RET_EN_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM3_POWER_GATE_CONTROL_0_SRAM_RET_EN_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM3_POWER_GATE_CONTROL_0_SRAM_RET_EN_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM3_POWER_GATE_CONTROL_0_SRAM_RET_EN_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AOPG_TCM3_POWER_GATE_CONTROL_0_SRAM_RET_EN_INIT_ENUM                      OFF
#define PMC_IMPL_PART_AOPG_TCM3_POWER_GATE_CONTROL_0_SRAM_RET_EN_OFF                    MK_ENUM_CONST(0)
#define PMC_IMPL_PART_AOPG_TCM3_POWER_GATE_CONTROL_0_SRAM_RET_EN_ON                     MK_ENUM_CONST(1)

#define PMC_IMPL_PART_AOPG_TCM3_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SHIFT                  MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_AOPG_TCM3_POWER_GATE_CONTROL_0_LOGIC_SLEEP_FIELD                  MK_FIELD_CONST(0x1, PMC_IMPL_PART_AOPG_TCM3_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SHIFT)
#define PMC_IMPL_PART_AOPG_TCM3_POWER_GATE_CONTROL_0_LOGIC_SLEEP_RANGE                  0:0
#define PMC_IMPL_PART_AOPG_TCM3_POWER_GATE_CONTROL_0_LOGIC_SLEEP_MSB                    MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_AOPG_TCM3_POWER_GATE_CONTROL_0_LOGIC_SLEEP_LSB                    MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_AOPG_TCM3_POWER_GATE_CONTROL_0_LOGIC_SLEEP_WOFFSET                        0x0
#define PMC_IMPL_PART_AOPG_TCM3_POWER_GATE_CONTROL_0_LOGIC_SLEEP_DEFAULT                        MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM3_POWER_GATE_CONTROL_0_LOGIC_SLEEP_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AOPG_TCM3_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM3_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM3_POWER_GATE_CONTROL_0_LOGIC_SLEEP_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM3_POWER_GATE_CONTROL_0_LOGIC_SLEEP_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AOPG_TCM3_POWER_GATE_CONTROL_0_LOGIC_SLEEP_INIT_ENUM                      OFF
#define PMC_IMPL_PART_AOPG_TCM3_POWER_GATE_CONTROL_0_LOGIC_SLEEP_OFF                    MK_ENUM_CONST(0)
#define PMC_IMPL_PART_AOPG_TCM3_POWER_GATE_CONTROL_0_LOGIC_SLEEP_ON                     MK_ENUM_CONST(1)


// Register PMC_IMPL_PART_AOPG_TCM3_POWER_GATE_STATUS_0
#define PMC_IMPL_PART_AOPG_TCM3_POWER_GATE_STATUS_0                     MK_ADDR_CONST(0x3b0)
#define PMC_IMPL_PART_AOPG_TCM3_POWER_GATE_STATUS_0_SECURE                      0x0
#define PMC_IMPL_PART_AOPG_TCM3_POWER_GATE_STATUS_0_DUAL                        0x0
#define PMC_IMPL_PART_AOPG_TCM3_POWER_GATE_STATUS_0_SCR                         PG_AOPG_TCM3_SCR_0
#define PMC_IMPL_PART_AOPG_TCM3_POWER_GATE_STATUS_0_SCRREG                      PMC_IMPL_SCR_PG_AOPG_TCM3_SCR_0
#define PMC_IMPL_PART_AOPG_TCM3_POWER_GATE_STATUS_0_WORD_COUNT                  0x1
#define PMC_IMPL_PART_AOPG_TCM3_POWER_GATE_STATUS_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM3_POWER_GATE_STATUS_0_RESET_MASK                  MK_MASK_CONST(0x7)
#define PMC_IMPL_PART_AOPG_TCM3_POWER_GATE_STATUS_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM3_POWER_GATE_STATUS_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM3_POWER_GATE_STATUS_0_READ_MASK                   MK_MASK_CONST(0x7)
#define PMC_IMPL_PART_AOPG_TCM3_POWER_GATE_STATUS_0_WRITE_MASK                  MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM3_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SHIFT                        MK_SHIFT_CONST(2)
#define PMC_IMPL_PART_AOPG_TCM3_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_FIELD                        MK_FIELD_CONST(0x1, PMC_IMPL_PART_AOPG_TCM3_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SHIFT)
#define PMC_IMPL_PART_AOPG_TCM3_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_RANGE                        2:2
#define PMC_IMPL_PART_AOPG_TCM3_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_MSB                  MK_SHIFT_CONST(2)
#define PMC_IMPL_PART_AOPG_TCM3_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_LSB                  MK_SHIFT_CONST(2)
#define PMC_IMPL_PART_AOPG_TCM3_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_WOFFSET                      0x0
#define PMC_IMPL_PART_AOPG_TCM3_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_DEFAULT                      MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM3_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AOPG_TCM3_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM3_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM3_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM3_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AOPG_TCM3_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_INIT_ENUM                    OFF
#define PMC_IMPL_PART_AOPG_TCM3_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_OFF                  MK_ENUM_CONST(0)
#define PMC_IMPL_PART_AOPG_TCM3_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_ON                   MK_ENUM_CONST(1)

#define PMC_IMPL_PART_AOPG_TCM3_POWER_GATE_STATUS_0_SRAM_RET_STS_SHIFT                  MK_SHIFT_CONST(1)
#define PMC_IMPL_PART_AOPG_TCM3_POWER_GATE_STATUS_0_SRAM_RET_STS_FIELD                  MK_FIELD_CONST(0x1, PMC_IMPL_PART_AOPG_TCM3_POWER_GATE_STATUS_0_SRAM_RET_STS_SHIFT)
#define PMC_IMPL_PART_AOPG_TCM3_POWER_GATE_STATUS_0_SRAM_RET_STS_RANGE                  1:1
#define PMC_IMPL_PART_AOPG_TCM3_POWER_GATE_STATUS_0_SRAM_RET_STS_MSB                    MK_SHIFT_CONST(1)
#define PMC_IMPL_PART_AOPG_TCM3_POWER_GATE_STATUS_0_SRAM_RET_STS_LSB                    MK_SHIFT_CONST(1)
#define PMC_IMPL_PART_AOPG_TCM3_POWER_GATE_STATUS_0_SRAM_RET_STS_WOFFSET                        0x0
#define PMC_IMPL_PART_AOPG_TCM3_POWER_GATE_STATUS_0_SRAM_RET_STS_DEFAULT                        MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM3_POWER_GATE_STATUS_0_SRAM_RET_STS_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AOPG_TCM3_POWER_GATE_STATUS_0_SRAM_RET_STS_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM3_POWER_GATE_STATUS_0_SRAM_RET_STS_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM3_POWER_GATE_STATUS_0_SRAM_RET_STS_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM3_POWER_GATE_STATUS_0_SRAM_RET_STS_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AOPG_TCM3_POWER_GATE_STATUS_0_SRAM_RET_STS_INIT_ENUM                      OFF
#define PMC_IMPL_PART_AOPG_TCM3_POWER_GATE_STATUS_0_SRAM_RET_STS_OFF                    MK_ENUM_CONST(0)
#define PMC_IMPL_PART_AOPG_TCM3_POWER_GATE_STATUS_0_SRAM_RET_STS_ON                     MK_ENUM_CONST(1)

#define PMC_IMPL_PART_AOPG_TCM3_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SHIFT                       MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_AOPG_TCM3_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_FIELD                       MK_FIELD_CONST(0x1, PMC_IMPL_PART_AOPG_TCM3_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SHIFT)
#define PMC_IMPL_PART_AOPG_TCM3_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_RANGE                       0:0
#define PMC_IMPL_PART_AOPG_TCM3_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_MSB                 MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_AOPG_TCM3_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_LSB                 MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_AOPG_TCM3_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_WOFFSET                     0x0
#define PMC_IMPL_PART_AOPG_TCM3_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_DEFAULT                     MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM3_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AOPG_TCM3_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM3_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM3_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM3_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AOPG_TCM3_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_INIT_ENUM                   OFF
#define PMC_IMPL_PART_AOPG_TCM3_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_OFF                 MK_ENUM_CONST(0)
#define PMC_IMPL_PART_AOPG_TCM3_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_ON                  MK_ENUM_CONST(1)


// Register PMC_IMPL_PART_AOPG_TCM3_CLAMP_CONTROL_0
#define PMC_IMPL_PART_AOPG_TCM3_CLAMP_CONTROL_0                 MK_ADDR_CONST(0x3b4)
#define PMC_IMPL_PART_AOPG_TCM3_CLAMP_CONTROL_0_SECURE                  0x0
#define PMC_IMPL_PART_AOPG_TCM3_CLAMP_CONTROL_0_DUAL                    0x0
#define PMC_IMPL_PART_AOPG_TCM3_CLAMP_CONTROL_0_SCR                     PG_AOPG_TCM3_SCR_0
#define PMC_IMPL_PART_AOPG_TCM3_CLAMP_CONTROL_0_SCRREG                  PMC_IMPL_SCR_PG_AOPG_TCM3_SCR_0
#define PMC_IMPL_PART_AOPG_TCM3_CLAMP_CONTROL_0_WORD_COUNT                      0x1
#define PMC_IMPL_PART_AOPG_TCM3_CLAMP_CONTROL_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM3_CLAMP_CONTROL_0_RESET_MASK                      MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AOPG_TCM3_CLAMP_CONTROL_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM3_CLAMP_CONTROL_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM3_CLAMP_CONTROL_0_READ_MASK                       MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AOPG_TCM3_CLAMP_CONTROL_0_WRITE_MASK                      MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM3_CLAMP_CONTROL_0_CLAMP_SHIFT                     MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_AOPG_TCM3_CLAMP_CONTROL_0_CLAMP_FIELD                     MK_FIELD_CONST(0x1, PMC_IMPL_PART_AOPG_TCM3_CLAMP_CONTROL_0_CLAMP_SHIFT)
#define PMC_IMPL_PART_AOPG_TCM3_CLAMP_CONTROL_0_CLAMP_RANGE                     0:0
#define PMC_IMPL_PART_AOPG_TCM3_CLAMP_CONTROL_0_CLAMP_MSB                       MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_AOPG_TCM3_CLAMP_CONTROL_0_CLAMP_LSB                       MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_AOPG_TCM3_CLAMP_CONTROL_0_CLAMP_WOFFSET                   0x0
#define PMC_IMPL_PART_AOPG_TCM3_CLAMP_CONTROL_0_CLAMP_DEFAULT                   MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM3_CLAMP_CONTROL_0_CLAMP_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AOPG_TCM3_CLAMP_CONTROL_0_CLAMP_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM3_CLAMP_CONTROL_0_CLAMP_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM3_CLAMP_CONTROL_0_CLAMP_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM3_CLAMP_CONTROL_0_CLAMP_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AOPG_TCM3_CLAMP_CONTROL_0_CLAMP_INIT_ENUM                 OFF
#define PMC_IMPL_PART_AOPG_TCM3_CLAMP_CONTROL_0_CLAMP_OFF                       MK_ENUM_CONST(0)
#define PMC_IMPL_PART_AOPG_TCM3_CLAMP_CONTROL_0_CLAMP_ON                        MK_ENUM_CONST(1)


// Register PMC_IMPL_PART_AOPG_TCM4_POWER_GATE_CONTROL_0
#define PMC_IMPL_PART_AOPG_TCM4_POWER_GATE_CONTROL_0                    MK_ADDR_CONST(0x3b8)
#define PMC_IMPL_PART_AOPG_TCM4_POWER_GATE_CONTROL_0_SECURE                     0x0
#define PMC_IMPL_PART_AOPG_TCM4_POWER_GATE_CONTROL_0_DUAL                       0x0
#define PMC_IMPL_PART_AOPG_TCM4_POWER_GATE_CONTROL_0_SCR                        PG_AOPG_TCM4_SCR_0
#define PMC_IMPL_PART_AOPG_TCM4_POWER_GATE_CONTROL_0_SCRREG                     PMC_IMPL_SCR_PG_AOPG_TCM4_SCR_0
#define PMC_IMPL_PART_AOPG_TCM4_POWER_GATE_CONTROL_0_WORD_COUNT                         0x1
#define PMC_IMPL_PART_AOPG_TCM4_POWER_GATE_CONTROL_0_RESET_VAL                  MK_MASK_CONST(0x80000000)
#define PMC_IMPL_PART_AOPG_TCM4_POWER_GATE_CONTROL_0_RESET_MASK                         MK_MASK_CONST(0x80000107)
#define PMC_IMPL_PART_AOPG_TCM4_POWER_GATE_CONTROL_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM4_POWER_GATE_CONTROL_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM4_POWER_GATE_CONTROL_0_READ_MASK                  MK_MASK_CONST(0x80000107)
#define PMC_IMPL_PART_AOPG_TCM4_POWER_GATE_CONTROL_0_WRITE_MASK                         MK_MASK_CONST(0x80000106)
#define PMC_IMPL_PART_AOPG_TCM4_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SHIFT                  MK_SHIFT_CONST(31)
#define PMC_IMPL_PART_AOPG_TCM4_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_FIELD                  MK_FIELD_CONST(0x1, PMC_IMPL_PART_AOPG_TCM4_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SHIFT)
#define PMC_IMPL_PART_AOPG_TCM4_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_RANGE                  31:31
#define PMC_IMPL_PART_AOPG_TCM4_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_MSB                    MK_SHIFT_CONST(31)
#define PMC_IMPL_PART_AOPG_TCM4_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_LSB                    MK_SHIFT_CONST(31)
#define PMC_IMPL_PART_AOPG_TCM4_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_WOFFSET                        0x0
#define PMC_IMPL_PART_AOPG_TCM4_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_DEFAULT                        MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AOPG_TCM4_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AOPG_TCM4_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM4_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM4_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM4_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AOPG_TCM4_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_INIT_ENUM                      ENABLE
#define PMC_IMPL_PART_AOPG_TCM4_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_DISABLE                        MK_ENUM_CONST(0)
#define PMC_IMPL_PART_AOPG_TCM4_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_ENABLE                 MK_ENUM_CONST(1)

#define PMC_IMPL_PART_AOPG_TCM4_POWER_GATE_CONTROL_0_START_SHIFT                        MK_SHIFT_CONST(8)
#define PMC_IMPL_PART_AOPG_TCM4_POWER_GATE_CONTROL_0_START_FIELD                        MK_FIELD_CONST(0x1, PMC_IMPL_PART_AOPG_TCM4_POWER_GATE_CONTROL_0_START_SHIFT)
#define PMC_IMPL_PART_AOPG_TCM4_POWER_GATE_CONTROL_0_START_RANGE                        8:8
#define PMC_IMPL_PART_AOPG_TCM4_POWER_GATE_CONTROL_0_START_MSB                  MK_SHIFT_CONST(8)
#define PMC_IMPL_PART_AOPG_TCM4_POWER_GATE_CONTROL_0_START_LSB                  MK_SHIFT_CONST(8)
#define PMC_IMPL_PART_AOPG_TCM4_POWER_GATE_CONTROL_0_START_WOFFSET                      0x0
#define PMC_IMPL_PART_AOPG_TCM4_POWER_GATE_CONTROL_0_START_DEFAULT                      MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM4_POWER_GATE_CONTROL_0_START_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AOPG_TCM4_POWER_GATE_CONTROL_0_START_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM4_POWER_GATE_CONTROL_0_START_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM4_POWER_GATE_CONTROL_0_START_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM4_POWER_GATE_CONTROL_0_START_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AOPG_TCM4_POWER_GATE_CONTROL_0_START_INIT_ENUM                    DONE
#define PMC_IMPL_PART_AOPG_TCM4_POWER_GATE_CONTROL_0_START_DONE                 MK_ENUM_CONST(0)
#define PMC_IMPL_PART_AOPG_TCM4_POWER_GATE_CONTROL_0_START_PENDING                      MK_ENUM_CONST(1)

#define PMC_IMPL_PART_AOPG_TCM4_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SHIFT                        MK_SHIFT_CONST(2)
#define PMC_IMPL_PART_AOPG_TCM4_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_FIELD                        MK_FIELD_CONST(0x1, PMC_IMPL_PART_AOPG_TCM4_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SHIFT)
#define PMC_IMPL_PART_AOPG_TCM4_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_RANGE                        2:2
#define PMC_IMPL_PART_AOPG_TCM4_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_MSB                  MK_SHIFT_CONST(2)
#define PMC_IMPL_PART_AOPG_TCM4_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_LSB                  MK_SHIFT_CONST(2)
#define PMC_IMPL_PART_AOPG_TCM4_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_WOFFSET                      0x0
#define PMC_IMPL_PART_AOPG_TCM4_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_DEFAULT                      MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM4_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AOPG_TCM4_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM4_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM4_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM4_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AOPG_TCM4_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_INIT_ENUM                    OFF
#define PMC_IMPL_PART_AOPG_TCM4_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_OFF                  MK_ENUM_CONST(0)
#define PMC_IMPL_PART_AOPG_TCM4_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_ON                   MK_ENUM_CONST(1)

#define PMC_IMPL_PART_AOPG_TCM4_POWER_GATE_CONTROL_0_SRAM_RET_EN_SHIFT                  MK_SHIFT_CONST(1)
#define PMC_IMPL_PART_AOPG_TCM4_POWER_GATE_CONTROL_0_SRAM_RET_EN_FIELD                  MK_FIELD_CONST(0x1, PMC_IMPL_PART_AOPG_TCM4_POWER_GATE_CONTROL_0_SRAM_RET_EN_SHIFT)
#define PMC_IMPL_PART_AOPG_TCM4_POWER_GATE_CONTROL_0_SRAM_RET_EN_RANGE                  1:1
#define PMC_IMPL_PART_AOPG_TCM4_POWER_GATE_CONTROL_0_SRAM_RET_EN_MSB                    MK_SHIFT_CONST(1)
#define PMC_IMPL_PART_AOPG_TCM4_POWER_GATE_CONTROL_0_SRAM_RET_EN_LSB                    MK_SHIFT_CONST(1)
#define PMC_IMPL_PART_AOPG_TCM4_POWER_GATE_CONTROL_0_SRAM_RET_EN_WOFFSET                        0x0
#define PMC_IMPL_PART_AOPG_TCM4_POWER_GATE_CONTROL_0_SRAM_RET_EN_DEFAULT                        MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM4_POWER_GATE_CONTROL_0_SRAM_RET_EN_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AOPG_TCM4_POWER_GATE_CONTROL_0_SRAM_RET_EN_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM4_POWER_GATE_CONTROL_0_SRAM_RET_EN_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM4_POWER_GATE_CONTROL_0_SRAM_RET_EN_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM4_POWER_GATE_CONTROL_0_SRAM_RET_EN_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AOPG_TCM4_POWER_GATE_CONTROL_0_SRAM_RET_EN_INIT_ENUM                      OFF
#define PMC_IMPL_PART_AOPG_TCM4_POWER_GATE_CONTROL_0_SRAM_RET_EN_OFF                    MK_ENUM_CONST(0)
#define PMC_IMPL_PART_AOPG_TCM4_POWER_GATE_CONTROL_0_SRAM_RET_EN_ON                     MK_ENUM_CONST(1)

#define PMC_IMPL_PART_AOPG_TCM4_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SHIFT                  MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_AOPG_TCM4_POWER_GATE_CONTROL_0_LOGIC_SLEEP_FIELD                  MK_FIELD_CONST(0x1, PMC_IMPL_PART_AOPG_TCM4_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SHIFT)
#define PMC_IMPL_PART_AOPG_TCM4_POWER_GATE_CONTROL_0_LOGIC_SLEEP_RANGE                  0:0
#define PMC_IMPL_PART_AOPG_TCM4_POWER_GATE_CONTROL_0_LOGIC_SLEEP_MSB                    MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_AOPG_TCM4_POWER_GATE_CONTROL_0_LOGIC_SLEEP_LSB                    MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_AOPG_TCM4_POWER_GATE_CONTROL_0_LOGIC_SLEEP_WOFFSET                        0x0
#define PMC_IMPL_PART_AOPG_TCM4_POWER_GATE_CONTROL_0_LOGIC_SLEEP_DEFAULT                        MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM4_POWER_GATE_CONTROL_0_LOGIC_SLEEP_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AOPG_TCM4_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM4_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM4_POWER_GATE_CONTROL_0_LOGIC_SLEEP_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM4_POWER_GATE_CONTROL_0_LOGIC_SLEEP_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AOPG_TCM4_POWER_GATE_CONTROL_0_LOGIC_SLEEP_INIT_ENUM                      OFF
#define PMC_IMPL_PART_AOPG_TCM4_POWER_GATE_CONTROL_0_LOGIC_SLEEP_OFF                    MK_ENUM_CONST(0)
#define PMC_IMPL_PART_AOPG_TCM4_POWER_GATE_CONTROL_0_LOGIC_SLEEP_ON                     MK_ENUM_CONST(1)


// Register PMC_IMPL_PART_AOPG_TCM4_POWER_GATE_STATUS_0
#define PMC_IMPL_PART_AOPG_TCM4_POWER_GATE_STATUS_0                     MK_ADDR_CONST(0x3bc)
#define PMC_IMPL_PART_AOPG_TCM4_POWER_GATE_STATUS_0_SECURE                      0x0
#define PMC_IMPL_PART_AOPG_TCM4_POWER_GATE_STATUS_0_DUAL                        0x0
#define PMC_IMPL_PART_AOPG_TCM4_POWER_GATE_STATUS_0_SCR                         PG_AOPG_TCM4_SCR_0
#define PMC_IMPL_PART_AOPG_TCM4_POWER_GATE_STATUS_0_SCRREG                      PMC_IMPL_SCR_PG_AOPG_TCM4_SCR_0
#define PMC_IMPL_PART_AOPG_TCM4_POWER_GATE_STATUS_0_WORD_COUNT                  0x1
#define PMC_IMPL_PART_AOPG_TCM4_POWER_GATE_STATUS_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM4_POWER_GATE_STATUS_0_RESET_MASK                  MK_MASK_CONST(0x7)
#define PMC_IMPL_PART_AOPG_TCM4_POWER_GATE_STATUS_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM4_POWER_GATE_STATUS_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM4_POWER_GATE_STATUS_0_READ_MASK                   MK_MASK_CONST(0x7)
#define PMC_IMPL_PART_AOPG_TCM4_POWER_GATE_STATUS_0_WRITE_MASK                  MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM4_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SHIFT                        MK_SHIFT_CONST(2)
#define PMC_IMPL_PART_AOPG_TCM4_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_FIELD                        MK_FIELD_CONST(0x1, PMC_IMPL_PART_AOPG_TCM4_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SHIFT)
#define PMC_IMPL_PART_AOPG_TCM4_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_RANGE                        2:2
#define PMC_IMPL_PART_AOPG_TCM4_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_MSB                  MK_SHIFT_CONST(2)
#define PMC_IMPL_PART_AOPG_TCM4_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_LSB                  MK_SHIFT_CONST(2)
#define PMC_IMPL_PART_AOPG_TCM4_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_WOFFSET                      0x0
#define PMC_IMPL_PART_AOPG_TCM4_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_DEFAULT                      MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM4_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AOPG_TCM4_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM4_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM4_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM4_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AOPG_TCM4_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_INIT_ENUM                    OFF
#define PMC_IMPL_PART_AOPG_TCM4_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_OFF                  MK_ENUM_CONST(0)
#define PMC_IMPL_PART_AOPG_TCM4_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_ON                   MK_ENUM_CONST(1)

#define PMC_IMPL_PART_AOPG_TCM4_POWER_GATE_STATUS_0_SRAM_RET_STS_SHIFT                  MK_SHIFT_CONST(1)
#define PMC_IMPL_PART_AOPG_TCM4_POWER_GATE_STATUS_0_SRAM_RET_STS_FIELD                  MK_FIELD_CONST(0x1, PMC_IMPL_PART_AOPG_TCM4_POWER_GATE_STATUS_0_SRAM_RET_STS_SHIFT)
#define PMC_IMPL_PART_AOPG_TCM4_POWER_GATE_STATUS_0_SRAM_RET_STS_RANGE                  1:1
#define PMC_IMPL_PART_AOPG_TCM4_POWER_GATE_STATUS_0_SRAM_RET_STS_MSB                    MK_SHIFT_CONST(1)
#define PMC_IMPL_PART_AOPG_TCM4_POWER_GATE_STATUS_0_SRAM_RET_STS_LSB                    MK_SHIFT_CONST(1)
#define PMC_IMPL_PART_AOPG_TCM4_POWER_GATE_STATUS_0_SRAM_RET_STS_WOFFSET                        0x0
#define PMC_IMPL_PART_AOPG_TCM4_POWER_GATE_STATUS_0_SRAM_RET_STS_DEFAULT                        MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM4_POWER_GATE_STATUS_0_SRAM_RET_STS_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AOPG_TCM4_POWER_GATE_STATUS_0_SRAM_RET_STS_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM4_POWER_GATE_STATUS_0_SRAM_RET_STS_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM4_POWER_GATE_STATUS_0_SRAM_RET_STS_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM4_POWER_GATE_STATUS_0_SRAM_RET_STS_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AOPG_TCM4_POWER_GATE_STATUS_0_SRAM_RET_STS_INIT_ENUM                      OFF
#define PMC_IMPL_PART_AOPG_TCM4_POWER_GATE_STATUS_0_SRAM_RET_STS_OFF                    MK_ENUM_CONST(0)
#define PMC_IMPL_PART_AOPG_TCM4_POWER_GATE_STATUS_0_SRAM_RET_STS_ON                     MK_ENUM_CONST(1)

#define PMC_IMPL_PART_AOPG_TCM4_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SHIFT                       MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_AOPG_TCM4_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_FIELD                       MK_FIELD_CONST(0x1, PMC_IMPL_PART_AOPG_TCM4_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SHIFT)
#define PMC_IMPL_PART_AOPG_TCM4_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_RANGE                       0:0
#define PMC_IMPL_PART_AOPG_TCM4_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_MSB                 MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_AOPG_TCM4_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_LSB                 MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_AOPG_TCM4_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_WOFFSET                     0x0
#define PMC_IMPL_PART_AOPG_TCM4_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_DEFAULT                     MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM4_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AOPG_TCM4_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM4_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM4_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM4_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AOPG_TCM4_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_INIT_ENUM                   OFF
#define PMC_IMPL_PART_AOPG_TCM4_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_OFF                 MK_ENUM_CONST(0)
#define PMC_IMPL_PART_AOPG_TCM4_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_ON                  MK_ENUM_CONST(1)


// Register PMC_IMPL_PART_AOPG_TCM4_CLAMP_CONTROL_0
#define PMC_IMPL_PART_AOPG_TCM4_CLAMP_CONTROL_0                 MK_ADDR_CONST(0x3c0)
#define PMC_IMPL_PART_AOPG_TCM4_CLAMP_CONTROL_0_SECURE                  0x0
#define PMC_IMPL_PART_AOPG_TCM4_CLAMP_CONTROL_0_DUAL                    0x0
#define PMC_IMPL_PART_AOPG_TCM4_CLAMP_CONTROL_0_SCR                     PG_AOPG_TCM4_SCR_0
#define PMC_IMPL_PART_AOPG_TCM4_CLAMP_CONTROL_0_SCRREG                  PMC_IMPL_SCR_PG_AOPG_TCM4_SCR_0
#define PMC_IMPL_PART_AOPG_TCM4_CLAMP_CONTROL_0_WORD_COUNT                      0x1
#define PMC_IMPL_PART_AOPG_TCM4_CLAMP_CONTROL_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM4_CLAMP_CONTROL_0_RESET_MASK                      MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AOPG_TCM4_CLAMP_CONTROL_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM4_CLAMP_CONTROL_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM4_CLAMP_CONTROL_0_READ_MASK                       MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AOPG_TCM4_CLAMP_CONTROL_0_WRITE_MASK                      MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM4_CLAMP_CONTROL_0_CLAMP_SHIFT                     MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_AOPG_TCM4_CLAMP_CONTROL_0_CLAMP_FIELD                     MK_FIELD_CONST(0x1, PMC_IMPL_PART_AOPG_TCM4_CLAMP_CONTROL_0_CLAMP_SHIFT)
#define PMC_IMPL_PART_AOPG_TCM4_CLAMP_CONTROL_0_CLAMP_RANGE                     0:0
#define PMC_IMPL_PART_AOPG_TCM4_CLAMP_CONTROL_0_CLAMP_MSB                       MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_AOPG_TCM4_CLAMP_CONTROL_0_CLAMP_LSB                       MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_AOPG_TCM4_CLAMP_CONTROL_0_CLAMP_WOFFSET                   0x0
#define PMC_IMPL_PART_AOPG_TCM4_CLAMP_CONTROL_0_CLAMP_DEFAULT                   MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM4_CLAMP_CONTROL_0_CLAMP_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AOPG_TCM4_CLAMP_CONTROL_0_CLAMP_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM4_CLAMP_CONTROL_0_CLAMP_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM4_CLAMP_CONTROL_0_CLAMP_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM4_CLAMP_CONTROL_0_CLAMP_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AOPG_TCM4_CLAMP_CONTROL_0_CLAMP_INIT_ENUM                 OFF
#define PMC_IMPL_PART_AOPG_TCM4_CLAMP_CONTROL_0_CLAMP_OFF                       MK_ENUM_CONST(0)
#define PMC_IMPL_PART_AOPG_TCM4_CLAMP_CONTROL_0_CLAMP_ON                        MK_ENUM_CONST(1)


// Register PMC_IMPL_PART_AOPG_TCM5_POWER_GATE_CONTROL_0
#define PMC_IMPL_PART_AOPG_TCM5_POWER_GATE_CONTROL_0                    MK_ADDR_CONST(0x3c4)
#define PMC_IMPL_PART_AOPG_TCM5_POWER_GATE_CONTROL_0_SECURE                     0x0
#define PMC_IMPL_PART_AOPG_TCM5_POWER_GATE_CONTROL_0_DUAL                       0x0
#define PMC_IMPL_PART_AOPG_TCM5_POWER_GATE_CONTROL_0_SCR                        PG_AOPG_TCM5_SCR_0
#define PMC_IMPL_PART_AOPG_TCM5_POWER_GATE_CONTROL_0_SCRREG                     PMC_IMPL_SCR_PG_AOPG_TCM5_SCR_0
#define PMC_IMPL_PART_AOPG_TCM5_POWER_GATE_CONTROL_0_WORD_COUNT                         0x1
#define PMC_IMPL_PART_AOPG_TCM5_POWER_GATE_CONTROL_0_RESET_VAL                  MK_MASK_CONST(0x80000000)
#define PMC_IMPL_PART_AOPG_TCM5_POWER_GATE_CONTROL_0_RESET_MASK                         MK_MASK_CONST(0x80000107)
#define PMC_IMPL_PART_AOPG_TCM5_POWER_GATE_CONTROL_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM5_POWER_GATE_CONTROL_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM5_POWER_GATE_CONTROL_0_READ_MASK                  MK_MASK_CONST(0x80000107)
#define PMC_IMPL_PART_AOPG_TCM5_POWER_GATE_CONTROL_0_WRITE_MASK                         MK_MASK_CONST(0x80000106)
#define PMC_IMPL_PART_AOPG_TCM5_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SHIFT                  MK_SHIFT_CONST(31)
#define PMC_IMPL_PART_AOPG_TCM5_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_FIELD                  MK_FIELD_CONST(0x1, PMC_IMPL_PART_AOPG_TCM5_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SHIFT)
#define PMC_IMPL_PART_AOPG_TCM5_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_RANGE                  31:31
#define PMC_IMPL_PART_AOPG_TCM5_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_MSB                    MK_SHIFT_CONST(31)
#define PMC_IMPL_PART_AOPG_TCM5_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_LSB                    MK_SHIFT_CONST(31)
#define PMC_IMPL_PART_AOPG_TCM5_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_WOFFSET                        0x0
#define PMC_IMPL_PART_AOPG_TCM5_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_DEFAULT                        MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AOPG_TCM5_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AOPG_TCM5_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM5_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM5_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM5_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AOPG_TCM5_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_INIT_ENUM                      ENABLE
#define PMC_IMPL_PART_AOPG_TCM5_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_DISABLE                        MK_ENUM_CONST(0)
#define PMC_IMPL_PART_AOPG_TCM5_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_ENABLE                 MK_ENUM_CONST(1)

#define PMC_IMPL_PART_AOPG_TCM5_POWER_GATE_CONTROL_0_START_SHIFT                        MK_SHIFT_CONST(8)
#define PMC_IMPL_PART_AOPG_TCM5_POWER_GATE_CONTROL_0_START_FIELD                        MK_FIELD_CONST(0x1, PMC_IMPL_PART_AOPG_TCM5_POWER_GATE_CONTROL_0_START_SHIFT)
#define PMC_IMPL_PART_AOPG_TCM5_POWER_GATE_CONTROL_0_START_RANGE                        8:8
#define PMC_IMPL_PART_AOPG_TCM5_POWER_GATE_CONTROL_0_START_MSB                  MK_SHIFT_CONST(8)
#define PMC_IMPL_PART_AOPG_TCM5_POWER_GATE_CONTROL_0_START_LSB                  MK_SHIFT_CONST(8)
#define PMC_IMPL_PART_AOPG_TCM5_POWER_GATE_CONTROL_0_START_WOFFSET                      0x0
#define PMC_IMPL_PART_AOPG_TCM5_POWER_GATE_CONTROL_0_START_DEFAULT                      MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM5_POWER_GATE_CONTROL_0_START_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AOPG_TCM5_POWER_GATE_CONTROL_0_START_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM5_POWER_GATE_CONTROL_0_START_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM5_POWER_GATE_CONTROL_0_START_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM5_POWER_GATE_CONTROL_0_START_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AOPG_TCM5_POWER_GATE_CONTROL_0_START_INIT_ENUM                    DONE
#define PMC_IMPL_PART_AOPG_TCM5_POWER_GATE_CONTROL_0_START_DONE                 MK_ENUM_CONST(0)
#define PMC_IMPL_PART_AOPG_TCM5_POWER_GATE_CONTROL_0_START_PENDING                      MK_ENUM_CONST(1)

#define PMC_IMPL_PART_AOPG_TCM5_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SHIFT                        MK_SHIFT_CONST(2)
#define PMC_IMPL_PART_AOPG_TCM5_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_FIELD                        MK_FIELD_CONST(0x1, PMC_IMPL_PART_AOPG_TCM5_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SHIFT)
#define PMC_IMPL_PART_AOPG_TCM5_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_RANGE                        2:2
#define PMC_IMPL_PART_AOPG_TCM5_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_MSB                  MK_SHIFT_CONST(2)
#define PMC_IMPL_PART_AOPG_TCM5_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_LSB                  MK_SHIFT_CONST(2)
#define PMC_IMPL_PART_AOPG_TCM5_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_WOFFSET                      0x0
#define PMC_IMPL_PART_AOPG_TCM5_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_DEFAULT                      MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM5_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AOPG_TCM5_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM5_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM5_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM5_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AOPG_TCM5_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_INIT_ENUM                    OFF
#define PMC_IMPL_PART_AOPG_TCM5_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_OFF                  MK_ENUM_CONST(0)
#define PMC_IMPL_PART_AOPG_TCM5_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_ON                   MK_ENUM_CONST(1)

#define PMC_IMPL_PART_AOPG_TCM5_POWER_GATE_CONTROL_0_SRAM_RET_EN_SHIFT                  MK_SHIFT_CONST(1)
#define PMC_IMPL_PART_AOPG_TCM5_POWER_GATE_CONTROL_0_SRAM_RET_EN_FIELD                  MK_FIELD_CONST(0x1, PMC_IMPL_PART_AOPG_TCM5_POWER_GATE_CONTROL_0_SRAM_RET_EN_SHIFT)
#define PMC_IMPL_PART_AOPG_TCM5_POWER_GATE_CONTROL_0_SRAM_RET_EN_RANGE                  1:1
#define PMC_IMPL_PART_AOPG_TCM5_POWER_GATE_CONTROL_0_SRAM_RET_EN_MSB                    MK_SHIFT_CONST(1)
#define PMC_IMPL_PART_AOPG_TCM5_POWER_GATE_CONTROL_0_SRAM_RET_EN_LSB                    MK_SHIFT_CONST(1)
#define PMC_IMPL_PART_AOPG_TCM5_POWER_GATE_CONTROL_0_SRAM_RET_EN_WOFFSET                        0x0
#define PMC_IMPL_PART_AOPG_TCM5_POWER_GATE_CONTROL_0_SRAM_RET_EN_DEFAULT                        MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM5_POWER_GATE_CONTROL_0_SRAM_RET_EN_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AOPG_TCM5_POWER_GATE_CONTROL_0_SRAM_RET_EN_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM5_POWER_GATE_CONTROL_0_SRAM_RET_EN_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM5_POWER_GATE_CONTROL_0_SRAM_RET_EN_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM5_POWER_GATE_CONTROL_0_SRAM_RET_EN_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AOPG_TCM5_POWER_GATE_CONTROL_0_SRAM_RET_EN_INIT_ENUM                      OFF
#define PMC_IMPL_PART_AOPG_TCM5_POWER_GATE_CONTROL_0_SRAM_RET_EN_OFF                    MK_ENUM_CONST(0)
#define PMC_IMPL_PART_AOPG_TCM5_POWER_GATE_CONTROL_0_SRAM_RET_EN_ON                     MK_ENUM_CONST(1)

#define PMC_IMPL_PART_AOPG_TCM5_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SHIFT                  MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_AOPG_TCM5_POWER_GATE_CONTROL_0_LOGIC_SLEEP_FIELD                  MK_FIELD_CONST(0x1, PMC_IMPL_PART_AOPG_TCM5_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SHIFT)
#define PMC_IMPL_PART_AOPG_TCM5_POWER_GATE_CONTROL_0_LOGIC_SLEEP_RANGE                  0:0
#define PMC_IMPL_PART_AOPG_TCM5_POWER_GATE_CONTROL_0_LOGIC_SLEEP_MSB                    MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_AOPG_TCM5_POWER_GATE_CONTROL_0_LOGIC_SLEEP_LSB                    MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_AOPG_TCM5_POWER_GATE_CONTROL_0_LOGIC_SLEEP_WOFFSET                        0x0
#define PMC_IMPL_PART_AOPG_TCM5_POWER_GATE_CONTROL_0_LOGIC_SLEEP_DEFAULT                        MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM5_POWER_GATE_CONTROL_0_LOGIC_SLEEP_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AOPG_TCM5_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM5_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM5_POWER_GATE_CONTROL_0_LOGIC_SLEEP_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM5_POWER_GATE_CONTROL_0_LOGIC_SLEEP_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AOPG_TCM5_POWER_GATE_CONTROL_0_LOGIC_SLEEP_INIT_ENUM                      OFF
#define PMC_IMPL_PART_AOPG_TCM5_POWER_GATE_CONTROL_0_LOGIC_SLEEP_OFF                    MK_ENUM_CONST(0)
#define PMC_IMPL_PART_AOPG_TCM5_POWER_GATE_CONTROL_0_LOGIC_SLEEP_ON                     MK_ENUM_CONST(1)


// Register PMC_IMPL_PART_AOPG_TCM5_POWER_GATE_STATUS_0
#define PMC_IMPL_PART_AOPG_TCM5_POWER_GATE_STATUS_0                     MK_ADDR_CONST(0x3c8)
#define PMC_IMPL_PART_AOPG_TCM5_POWER_GATE_STATUS_0_SECURE                      0x0
#define PMC_IMPL_PART_AOPG_TCM5_POWER_GATE_STATUS_0_DUAL                        0x0
#define PMC_IMPL_PART_AOPG_TCM5_POWER_GATE_STATUS_0_SCR                         PG_AOPG_TCM5_SCR_0
#define PMC_IMPL_PART_AOPG_TCM5_POWER_GATE_STATUS_0_SCRREG                      PMC_IMPL_SCR_PG_AOPG_TCM5_SCR_0
#define PMC_IMPL_PART_AOPG_TCM5_POWER_GATE_STATUS_0_WORD_COUNT                  0x1
#define PMC_IMPL_PART_AOPG_TCM5_POWER_GATE_STATUS_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM5_POWER_GATE_STATUS_0_RESET_MASK                  MK_MASK_CONST(0x7)
#define PMC_IMPL_PART_AOPG_TCM5_POWER_GATE_STATUS_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM5_POWER_GATE_STATUS_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM5_POWER_GATE_STATUS_0_READ_MASK                   MK_MASK_CONST(0x7)
#define PMC_IMPL_PART_AOPG_TCM5_POWER_GATE_STATUS_0_WRITE_MASK                  MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM5_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SHIFT                        MK_SHIFT_CONST(2)
#define PMC_IMPL_PART_AOPG_TCM5_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_FIELD                        MK_FIELD_CONST(0x1, PMC_IMPL_PART_AOPG_TCM5_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SHIFT)
#define PMC_IMPL_PART_AOPG_TCM5_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_RANGE                        2:2
#define PMC_IMPL_PART_AOPG_TCM5_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_MSB                  MK_SHIFT_CONST(2)
#define PMC_IMPL_PART_AOPG_TCM5_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_LSB                  MK_SHIFT_CONST(2)
#define PMC_IMPL_PART_AOPG_TCM5_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_WOFFSET                      0x0
#define PMC_IMPL_PART_AOPG_TCM5_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_DEFAULT                      MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM5_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AOPG_TCM5_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM5_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM5_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM5_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AOPG_TCM5_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_INIT_ENUM                    OFF
#define PMC_IMPL_PART_AOPG_TCM5_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_OFF                  MK_ENUM_CONST(0)
#define PMC_IMPL_PART_AOPG_TCM5_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_ON                   MK_ENUM_CONST(1)

#define PMC_IMPL_PART_AOPG_TCM5_POWER_GATE_STATUS_0_SRAM_RET_STS_SHIFT                  MK_SHIFT_CONST(1)
#define PMC_IMPL_PART_AOPG_TCM5_POWER_GATE_STATUS_0_SRAM_RET_STS_FIELD                  MK_FIELD_CONST(0x1, PMC_IMPL_PART_AOPG_TCM5_POWER_GATE_STATUS_0_SRAM_RET_STS_SHIFT)
#define PMC_IMPL_PART_AOPG_TCM5_POWER_GATE_STATUS_0_SRAM_RET_STS_RANGE                  1:1
#define PMC_IMPL_PART_AOPG_TCM5_POWER_GATE_STATUS_0_SRAM_RET_STS_MSB                    MK_SHIFT_CONST(1)
#define PMC_IMPL_PART_AOPG_TCM5_POWER_GATE_STATUS_0_SRAM_RET_STS_LSB                    MK_SHIFT_CONST(1)
#define PMC_IMPL_PART_AOPG_TCM5_POWER_GATE_STATUS_0_SRAM_RET_STS_WOFFSET                        0x0
#define PMC_IMPL_PART_AOPG_TCM5_POWER_GATE_STATUS_0_SRAM_RET_STS_DEFAULT                        MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM5_POWER_GATE_STATUS_0_SRAM_RET_STS_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AOPG_TCM5_POWER_GATE_STATUS_0_SRAM_RET_STS_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM5_POWER_GATE_STATUS_0_SRAM_RET_STS_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM5_POWER_GATE_STATUS_0_SRAM_RET_STS_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM5_POWER_GATE_STATUS_0_SRAM_RET_STS_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AOPG_TCM5_POWER_GATE_STATUS_0_SRAM_RET_STS_INIT_ENUM                      OFF
#define PMC_IMPL_PART_AOPG_TCM5_POWER_GATE_STATUS_0_SRAM_RET_STS_OFF                    MK_ENUM_CONST(0)
#define PMC_IMPL_PART_AOPG_TCM5_POWER_GATE_STATUS_0_SRAM_RET_STS_ON                     MK_ENUM_CONST(1)

#define PMC_IMPL_PART_AOPG_TCM5_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SHIFT                       MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_AOPG_TCM5_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_FIELD                       MK_FIELD_CONST(0x1, PMC_IMPL_PART_AOPG_TCM5_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SHIFT)
#define PMC_IMPL_PART_AOPG_TCM5_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_RANGE                       0:0
#define PMC_IMPL_PART_AOPG_TCM5_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_MSB                 MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_AOPG_TCM5_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_LSB                 MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_AOPG_TCM5_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_WOFFSET                     0x0
#define PMC_IMPL_PART_AOPG_TCM5_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_DEFAULT                     MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM5_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AOPG_TCM5_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM5_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM5_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM5_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AOPG_TCM5_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_INIT_ENUM                   OFF
#define PMC_IMPL_PART_AOPG_TCM5_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_OFF                 MK_ENUM_CONST(0)
#define PMC_IMPL_PART_AOPG_TCM5_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_ON                  MK_ENUM_CONST(1)


// Register PMC_IMPL_PART_AOPG_TCM5_CLAMP_CONTROL_0
#define PMC_IMPL_PART_AOPG_TCM5_CLAMP_CONTROL_0                 MK_ADDR_CONST(0x3cc)
#define PMC_IMPL_PART_AOPG_TCM5_CLAMP_CONTROL_0_SECURE                  0x0
#define PMC_IMPL_PART_AOPG_TCM5_CLAMP_CONTROL_0_DUAL                    0x0
#define PMC_IMPL_PART_AOPG_TCM5_CLAMP_CONTROL_0_SCR                     PG_AOPG_TCM5_SCR_0
#define PMC_IMPL_PART_AOPG_TCM5_CLAMP_CONTROL_0_SCRREG                  PMC_IMPL_SCR_PG_AOPG_TCM5_SCR_0
#define PMC_IMPL_PART_AOPG_TCM5_CLAMP_CONTROL_0_WORD_COUNT                      0x1
#define PMC_IMPL_PART_AOPG_TCM5_CLAMP_CONTROL_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM5_CLAMP_CONTROL_0_RESET_MASK                      MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AOPG_TCM5_CLAMP_CONTROL_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM5_CLAMP_CONTROL_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM5_CLAMP_CONTROL_0_READ_MASK                       MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AOPG_TCM5_CLAMP_CONTROL_0_WRITE_MASK                      MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM5_CLAMP_CONTROL_0_CLAMP_SHIFT                     MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_AOPG_TCM5_CLAMP_CONTROL_0_CLAMP_FIELD                     MK_FIELD_CONST(0x1, PMC_IMPL_PART_AOPG_TCM5_CLAMP_CONTROL_0_CLAMP_SHIFT)
#define PMC_IMPL_PART_AOPG_TCM5_CLAMP_CONTROL_0_CLAMP_RANGE                     0:0
#define PMC_IMPL_PART_AOPG_TCM5_CLAMP_CONTROL_0_CLAMP_MSB                       MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_AOPG_TCM5_CLAMP_CONTROL_0_CLAMP_LSB                       MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_AOPG_TCM5_CLAMP_CONTROL_0_CLAMP_WOFFSET                   0x0
#define PMC_IMPL_PART_AOPG_TCM5_CLAMP_CONTROL_0_CLAMP_DEFAULT                   MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM5_CLAMP_CONTROL_0_CLAMP_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AOPG_TCM5_CLAMP_CONTROL_0_CLAMP_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM5_CLAMP_CONTROL_0_CLAMP_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM5_CLAMP_CONTROL_0_CLAMP_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM5_CLAMP_CONTROL_0_CLAMP_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AOPG_TCM5_CLAMP_CONTROL_0_CLAMP_INIT_ENUM                 OFF
#define PMC_IMPL_PART_AOPG_TCM5_CLAMP_CONTROL_0_CLAMP_OFF                       MK_ENUM_CONST(0)
#define PMC_IMPL_PART_AOPG_TCM5_CLAMP_CONTROL_0_CLAMP_ON                        MK_ENUM_CONST(1)


// Register PMC_IMPL_PART_AOPG_TCM6_POWER_GATE_CONTROL_0
#define PMC_IMPL_PART_AOPG_TCM6_POWER_GATE_CONTROL_0                    MK_ADDR_CONST(0x3d0)
#define PMC_IMPL_PART_AOPG_TCM6_POWER_GATE_CONTROL_0_SECURE                     0x0
#define PMC_IMPL_PART_AOPG_TCM6_POWER_GATE_CONTROL_0_DUAL                       0x0
#define PMC_IMPL_PART_AOPG_TCM6_POWER_GATE_CONTROL_0_SCR                        PG_AOPG_TCM6_SCR_0
#define PMC_IMPL_PART_AOPG_TCM6_POWER_GATE_CONTROL_0_SCRREG                     PMC_IMPL_SCR_PG_AOPG_TCM6_SCR_0
#define PMC_IMPL_PART_AOPG_TCM6_POWER_GATE_CONTROL_0_WORD_COUNT                         0x1
#define PMC_IMPL_PART_AOPG_TCM6_POWER_GATE_CONTROL_0_RESET_VAL                  MK_MASK_CONST(0x80000000)
#define PMC_IMPL_PART_AOPG_TCM6_POWER_GATE_CONTROL_0_RESET_MASK                         MK_MASK_CONST(0x80000107)
#define PMC_IMPL_PART_AOPG_TCM6_POWER_GATE_CONTROL_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM6_POWER_GATE_CONTROL_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM6_POWER_GATE_CONTROL_0_READ_MASK                  MK_MASK_CONST(0x80000107)
#define PMC_IMPL_PART_AOPG_TCM6_POWER_GATE_CONTROL_0_WRITE_MASK                         MK_MASK_CONST(0x80000106)
#define PMC_IMPL_PART_AOPG_TCM6_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SHIFT                  MK_SHIFT_CONST(31)
#define PMC_IMPL_PART_AOPG_TCM6_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_FIELD                  MK_FIELD_CONST(0x1, PMC_IMPL_PART_AOPG_TCM6_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SHIFT)
#define PMC_IMPL_PART_AOPG_TCM6_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_RANGE                  31:31
#define PMC_IMPL_PART_AOPG_TCM6_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_MSB                    MK_SHIFT_CONST(31)
#define PMC_IMPL_PART_AOPG_TCM6_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_LSB                    MK_SHIFT_CONST(31)
#define PMC_IMPL_PART_AOPG_TCM6_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_WOFFSET                        0x0
#define PMC_IMPL_PART_AOPG_TCM6_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_DEFAULT                        MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AOPG_TCM6_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AOPG_TCM6_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM6_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM6_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM6_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AOPG_TCM6_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_INIT_ENUM                      ENABLE
#define PMC_IMPL_PART_AOPG_TCM6_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_DISABLE                        MK_ENUM_CONST(0)
#define PMC_IMPL_PART_AOPG_TCM6_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_ENABLE                 MK_ENUM_CONST(1)

#define PMC_IMPL_PART_AOPG_TCM6_POWER_GATE_CONTROL_0_START_SHIFT                        MK_SHIFT_CONST(8)
#define PMC_IMPL_PART_AOPG_TCM6_POWER_GATE_CONTROL_0_START_FIELD                        MK_FIELD_CONST(0x1, PMC_IMPL_PART_AOPG_TCM6_POWER_GATE_CONTROL_0_START_SHIFT)
#define PMC_IMPL_PART_AOPG_TCM6_POWER_GATE_CONTROL_0_START_RANGE                        8:8
#define PMC_IMPL_PART_AOPG_TCM6_POWER_GATE_CONTROL_0_START_MSB                  MK_SHIFT_CONST(8)
#define PMC_IMPL_PART_AOPG_TCM6_POWER_GATE_CONTROL_0_START_LSB                  MK_SHIFT_CONST(8)
#define PMC_IMPL_PART_AOPG_TCM6_POWER_GATE_CONTROL_0_START_WOFFSET                      0x0
#define PMC_IMPL_PART_AOPG_TCM6_POWER_GATE_CONTROL_0_START_DEFAULT                      MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM6_POWER_GATE_CONTROL_0_START_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AOPG_TCM6_POWER_GATE_CONTROL_0_START_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM6_POWER_GATE_CONTROL_0_START_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM6_POWER_GATE_CONTROL_0_START_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM6_POWER_GATE_CONTROL_0_START_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AOPG_TCM6_POWER_GATE_CONTROL_0_START_INIT_ENUM                    DONE
#define PMC_IMPL_PART_AOPG_TCM6_POWER_GATE_CONTROL_0_START_DONE                 MK_ENUM_CONST(0)
#define PMC_IMPL_PART_AOPG_TCM6_POWER_GATE_CONTROL_0_START_PENDING                      MK_ENUM_CONST(1)

#define PMC_IMPL_PART_AOPG_TCM6_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SHIFT                        MK_SHIFT_CONST(2)
#define PMC_IMPL_PART_AOPG_TCM6_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_FIELD                        MK_FIELD_CONST(0x1, PMC_IMPL_PART_AOPG_TCM6_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SHIFT)
#define PMC_IMPL_PART_AOPG_TCM6_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_RANGE                        2:2
#define PMC_IMPL_PART_AOPG_TCM6_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_MSB                  MK_SHIFT_CONST(2)
#define PMC_IMPL_PART_AOPG_TCM6_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_LSB                  MK_SHIFT_CONST(2)
#define PMC_IMPL_PART_AOPG_TCM6_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_WOFFSET                      0x0
#define PMC_IMPL_PART_AOPG_TCM6_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_DEFAULT                      MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM6_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AOPG_TCM6_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM6_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM6_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM6_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AOPG_TCM6_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_INIT_ENUM                    OFF
#define PMC_IMPL_PART_AOPG_TCM6_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_OFF                  MK_ENUM_CONST(0)
#define PMC_IMPL_PART_AOPG_TCM6_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_ON                   MK_ENUM_CONST(1)

#define PMC_IMPL_PART_AOPG_TCM6_POWER_GATE_CONTROL_0_SRAM_RET_EN_SHIFT                  MK_SHIFT_CONST(1)
#define PMC_IMPL_PART_AOPG_TCM6_POWER_GATE_CONTROL_0_SRAM_RET_EN_FIELD                  MK_FIELD_CONST(0x1, PMC_IMPL_PART_AOPG_TCM6_POWER_GATE_CONTROL_0_SRAM_RET_EN_SHIFT)
#define PMC_IMPL_PART_AOPG_TCM6_POWER_GATE_CONTROL_0_SRAM_RET_EN_RANGE                  1:1
#define PMC_IMPL_PART_AOPG_TCM6_POWER_GATE_CONTROL_0_SRAM_RET_EN_MSB                    MK_SHIFT_CONST(1)
#define PMC_IMPL_PART_AOPG_TCM6_POWER_GATE_CONTROL_0_SRAM_RET_EN_LSB                    MK_SHIFT_CONST(1)
#define PMC_IMPL_PART_AOPG_TCM6_POWER_GATE_CONTROL_0_SRAM_RET_EN_WOFFSET                        0x0
#define PMC_IMPL_PART_AOPG_TCM6_POWER_GATE_CONTROL_0_SRAM_RET_EN_DEFAULT                        MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM6_POWER_GATE_CONTROL_0_SRAM_RET_EN_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AOPG_TCM6_POWER_GATE_CONTROL_0_SRAM_RET_EN_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM6_POWER_GATE_CONTROL_0_SRAM_RET_EN_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM6_POWER_GATE_CONTROL_0_SRAM_RET_EN_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM6_POWER_GATE_CONTROL_0_SRAM_RET_EN_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AOPG_TCM6_POWER_GATE_CONTROL_0_SRAM_RET_EN_INIT_ENUM                      OFF
#define PMC_IMPL_PART_AOPG_TCM6_POWER_GATE_CONTROL_0_SRAM_RET_EN_OFF                    MK_ENUM_CONST(0)
#define PMC_IMPL_PART_AOPG_TCM6_POWER_GATE_CONTROL_0_SRAM_RET_EN_ON                     MK_ENUM_CONST(1)

#define PMC_IMPL_PART_AOPG_TCM6_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SHIFT                  MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_AOPG_TCM6_POWER_GATE_CONTROL_0_LOGIC_SLEEP_FIELD                  MK_FIELD_CONST(0x1, PMC_IMPL_PART_AOPG_TCM6_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SHIFT)
#define PMC_IMPL_PART_AOPG_TCM6_POWER_GATE_CONTROL_0_LOGIC_SLEEP_RANGE                  0:0
#define PMC_IMPL_PART_AOPG_TCM6_POWER_GATE_CONTROL_0_LOGIC_SLEEP_MSB                    MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_AOPG_TCM6_POWER_GATE_CONTROL_0_LOGIC_SLEEP_LSB                    MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_AOPG_TCM6_POWER_GATE_CONTROL_0_LOGIC_SLEEP_WOFFSET                        0x0
#define PMC_IMPL_PART_AOPG_TCM6_POWER_GATE_CONTROL_0_LOGIC_SLEEP_DEFAULT                        MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM6_POWER_GATE_CONTROL_0_LOGIC_SLEEP_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AOPG_TCM6_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM6_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM6_POWER_GATE_CONTROL_0_LOGIC_SLEEP_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM6_POWER_GATE_CONTROL_0_LOGIC_SLEEP_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AOPG_TCM6_POWER_GATE_CONTROL_0_LOGIC_SLEEP_INIT_ENUM                      OFF
#define PMC_IMPL_PART_AOPG_TCM6_POWER_GATE_CONTROL_0_LOGIC_SLEEP_OFF                    MK_ENUM_CONST(0)
#define PMC_IMPL_PART_AOPG_TCM6_POWER_GATE_CONTROL_0_LOGIC_SLEEP_ON                     MK_ENUM_CONST(1)


// Register PMC_IMPL_PART_AOPG_TCM6_POWER_GATE_STATUS_0
#define PMC_IMPL_PART_AOPG_TCM6_POWER_GATE_STATUS_0                     MK_ADDR_CONST(0x3d4)
#define PMC_IMPL_PART_AOPG_TCM6_POWER_GATE_STATUS_0_SECURE                      0x0
#define PMC_IMPL_PART_AOPG_TCM6_POWER_GATE_STATUS_0_DUAL                        0x0
#define PMC_IMPL_PART_AOPG_TCM6_POWER_GATE_STATUS_0_SCR                         PG_AOPG_TCM6_SCR_0
#define PMC_IMPL_PART_AOPG_TCM6_POWER_GATE_STATUS_0_SCRREG                      PMC_IMPL_SCR_PG_AOPG_TCM6_SCR_0
#define PMC_IMPL_PART_AOPG_TCM6_POWER_GATE_STATUS_0_WORD_COUNT                  0x1
#define PMC_IMPL_PART_AOPG_TCM6_POWER_GATE_STATUS_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM6_POWER_GATE_STATUS_0_RESET_MASK                  MK_MASK_CONST(0x7)
#define PMC_IMPL_PART_AOPG_TCM6_POWER_GATE_STATUS_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM6_POWER_GATE_STATUS_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM6_POWER_GATE_STATUS_0_READ_MASK                   MK_MASK_CONST(0x7)
#define PMC_IMPL_PART_AOPG_TCM6_POWER_GATE_STATUS_0_WRITE_MASK                  MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM6_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SHIFT                        MK_SHIFT_CONST(2)
#define PMC_IMPL_PART_AOPG_TCM6_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_FIELD                        MK_FIELD_CONST(0x1, PMC_IMPL_PART_AOPG_TCM6_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SHIFT)
#define PMC_IMPL_PART_AOPG_TCM6_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_RANGE                        2:2
#define PMC_IMPL_PART_AOPG_TCM6_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_MSB                  MK_SHIFT_CONST(2)
#define PMC_IMPL_PART_AOPG_TCM6_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_LSB                  MK_SHIFT_CONST(2)
#define PMC_IMPL_PART_AOPG_TCM6_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_WOFFSET                      0x0
#define PMC_IMPL_PART_AOPG_TCM6_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_DEFAULT                      MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM6_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AOPG_TCM6_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM6_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM6_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM6_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AOPG_TCM6_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_INIT_ENUM                    OFF
#define PMC_IMPL_PART_AOPG_TCM6_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_OFF                  MK_ENUM_CONST(0)
#define PMC_IMPL_PART_AOPG_TCM6_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_ON                   MK_ENUM_CONST(1)

#define PMC_IMPL_PART_AOPG_TCM6_POWER_GATE_STATUS_0_SRAM_RET_STS_SHIFT                  MK_SHIFT_CONST(1)
#define PMC_IMPL_PART_AOPG_TCM6_POWER_GATE_STATUS_0_SRAM_RET_STS_FIELD                  MK_FIELD_CONST(0x1, PMC_IMPL_PART_AOPG_TCM6_POWER_GATE_STATUS_0_SRAM_RET_STS_SHIFT)
#define PMC_IMPL_PART_AOPG_TCM6_POWER_GATE_STATUS_0_SRAM_RET_STS_RANGE                  1:1
#define PMC_IMPL_PART_AOPG_TCM6_POWER_GATE_STATUS_0_SRAM_RET_STS_MSB                    MK_SHIFT_CONST(1)
#define PMC_IMPL_PART_AOPG_TCM6_POWER_GATE_STATUS_0_SRAM_RET_STS_LSB                    MK_SHIFT_CONST(1)
#define PMC_IMPL_PART_AOPG_TCM6_POWER_GATE_STATUS_0_SRAM_RET_STS_WOFFSET                        0x0
#define PMC_IMPL_PART_AOPG_TCM6_POWER_GATE_STATUS_0_SRAM_RET_STS_DEFAULT                        MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM6_POWER_GATE_STATUS_0_SRAM_RET_STS_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AOPG_TCM6_POWER_GATE_STATUS_0_SRAM_RET_STS_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM6_POWER_GATE_STATUS_0_SRAM_RET_STS_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM6_POWER_GATE_STATUS_0_SRAM_RET_STS_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM6_POWER_GATE_STATUS_0_SRAM_RET_STS_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AOPG_TCM6_POWER_GATE_STATUS_0_SRAM_RET_STS_INIT_ENUM                      OFF
#define PMC_IMPL_PART_AOPG_TCM6_POWER_GATE_STATUS_0_SRAM_RET_STS_OFF                    MK_ENUM_CONST(0)
#define PMC_IMPL_PART_AOPG_TCM6_POWER_GATE_STATUS_0_SRAM_RET_STS_ON                     MK_ENUM_CONST(1)

#define PMC_IMPL_PART_AOPG_TCM6_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SHIFT                       MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_AOPG_TCM6_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_FIELD                       MK_FIELD_CONST(0x1, PMC_IMPL_PART_AOPG_TCM6_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SHIFT)
#define PMC_IMPL_PART_AOPG_TCM6_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_RANGE                       0:0
#define PMC_IMPL_PART_AOPG_TCM6_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_MSB                 MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_AOPG_TCM6_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_LSB                 MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_AOPG_TCM6_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_WOFFSET                     0x0
#define PMC_IMPL_PART_AOPG_TCM6_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_DEFAULT                     MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM6_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AOPG_TCM6_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM6_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM6_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM6_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AOPG_TCM6_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_INIT_ENUM                   OFF
#define PMC_IMPL_PART_AOPG_TCM6_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_OFF                 MK_ENUM_CONST(0)
#define PMC_IMPL_PART_AOPG_TCM6_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_ON                  MK_ENUM_CONST(1)


// Register PMC_IMPL_PART_AOPG_TCM6_CLAMP_CONTROL_0
#define PMC_IMPL_PART_AOPG_TCM6_CLAMP_CONTROL_0                 MK_ADDR_CONST(0x3d8)
#define PMC_IMPL_PART_AOPG_TCM6_CLAMP_CONTROL_0_SECURE                  0x0
#define PMC_IMPL_PART_AOPG_TCM6_CLAMP_CONTROL_0_DUAL                    0x0
#define PMC_IMPL_PART_AOPG_TCM6_CLAMP_CONTROL_0_SCR                     PG_AOPG_TCM6_SCR_0
#define PMC_IMPL_PART_AOPG_TCM6_CLAMP_CONTROL_0_SCRREG                  PMC_IMPL_SCR_PG_AOPG_TCM6_SCR_0
#define PMC_IMPL_PART_AOPG_TCM6_CLAMP_CONTROL_0_WORD_COUNT                      0x1
#define PMC_IMPL_PART_AOPG_TCM6_CLAMP_CONTROL_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM6_CLAMP_CONTROL_0_RESET_MASK                      MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AOPG_TCM6_CLAMP_CONTROL_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM6_CLAMP_CONTROL_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM6_CLAMP_CONTROL_0_READ_MASK                       MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AOPG_TCM6_CLAMP_CONTROL_0_WRITE_MASK                      MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM6_CLAMP_CONTROL_0_CLAMP_SHIFT                     MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_AOPG_TCM6_CLAMP_CONTROL_0_CLAMP_FIELD                     MK_FIELD_CONST(0x1, PMC_IMPL_PART_AOPG_TCM6_CLAMP_CONTROL_0_CLAMP_SHIFT)
#define PMC_IMPL_PART_AOPG_TCM6_CLAMP_CONTROL_0_CLAMP_RANGE                     0:0
#define PMC_IMPL_PART_AOPG_TCM6_CLAMP_CONTROL_0_CLAMP_MSB                       MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_AOPG_TCM6_CLAMP_CONTROL_0_CLAMP_LSB                       MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_AOPG_TCM6_CLAMP_CONTROL_0_CLAMP_WOFFSET                   0x0
#define PMC_IMPL_PART_AOPG_TCM6_CLAMP_CONTROL_0_CLAMP_DEFAULT                   MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM6_CLAMP_CONTROL_0_CLAMP_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AOPG_TCM6_CLAMP_CONTROL_0_CLAMP_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM6_CLAMP_CONTROL_0_CLAMP_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM6_CLAMP_CONTROL_0_CLAMP_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM6_CLAMP_CONTROL_0_CLAMP_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AOPG_TCM6_CLAMP_CONTROL_0_CLAMP_INIT_ENUM                 OFF
#define PMC_IMPL_PART_AOPG_TCM6_CLAMP_CONTROL_0_CLAMP_OFF                       MK_ENUM_CONST(0)
#define PMC_IMPL_PART_AOPG_TCM6_CLAMP_CONTROL_0_CLAMP_ON                        MK_ENUM_CONST(1)


// Register PMC_IMPL_PART_AOPG_TCM7_POWER_GATE_CONTROL_0
#define PMC_IMPL_PART_AOPG_TCM7_POWER_GATE_CONTROL_0                    MK_ADDR_CONST(0x3dc)
#define PMC_IMPL_PART_AOPG_TCM7_POWER_GATE_CONTROL_0_SECURE                     0x0
#define PMC_IMPL_PART_AOPG_TCM7_POWER_GATE_CONTROL_0_DUAL                       0x0
#define PMC_IMPL_PART_AOPG_TCM7_POWER_GATE_CONTROL_0_SCR                        PG_AOPG_TCM7_SCR_0
#define PMC_IMPL_PART_AOPG_TCM7_POWER_GATE_CONTROL_0_SCRREG                     PMC_IMPL_SCR_PG_AOPG_TCM7_SCR_0
#define PMC_IMPL_PART_AOPG_TCM7_POWER_GATE_CONTROL_0_WORD_COUNT                         0x1
#define PMC_IMPL_PART_AOPG_TCM7_POWER_GATE_CONTROL_0_RESET_VAL                  MK_MASK_CONST(0x80000000)
#define PMC_IMPL_PART_AOPG_TCM7_POWER_GATE_CONTROL_0_RESET_MASK                         MK_MASK_CONST(0x80000107)
#define PMC_IMPL_PART_AOPG_TCM7_POWER_GATE_CONTROL_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM7_POWER_GATE_CONTROL_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM7_POWER_GATE_CONTROL_0_READ_MASK                  MK_MASK_CONST(0x80000107)
#define PMC_IMPL_PART_AOPG_TCM7_POWER_GATE_CONTROL_0_WRITE_MASK                         MK_MASK_CONST(0x80000106)
#define PMC_IMPL_PART_AOPG_TCM7_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SHIFT                  MK_SHIFT_CONST(31)
#define PMC_IMPL_PART_AOPG_TCM7_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_FIELD                  MK_FIELD_CONST(0x1, PMC_IMPL_PART_AOPG_TCM7_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SHIFT)
#define PMC_IMPL_PART_AOPG_TCM7_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_RANGE                  31:31
#define PMC_IMPL_PART_AOPG_TCM7_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_MSB                    MK_SHIFT_CONST(31)
#define PMC_IMPL_PART_AOPG_TCM7_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_LSB                    MK_SHIFT_CONST(31)
#define PMC_IMPL_PART_AOPG_TCM7_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_WOFFSET                        0x0
#define PMC_IMPL_PART_AOPG_TCM7_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_DEFAULT                        MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AOPG_TCM7_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AOPG_TCM7_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM7_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM7_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM7_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AOPG_TCM7_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_INIT_ENUM                      ENABLE
#define PMC_IMPL_PART_AOPG_TCM7_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_DISABLE                        MK_ENUM_CONST(0)
#define PMC_IMPL_PART_AOPG_TCM7_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_ENABLE                 MK_ENUM_CONST(1)

#define PMC_IMPL_PART_AOPG_TCM7_POWER_GATE_CONTROL_0_START_SHIFT                        MK_SHIFT_CONST(8)
#define PMC_IMPL_PART_AOPG_TCM7_POWER_GATE_CONTROL_0_START_FIELD                        MK_FIELD_CONST(0x1, PMC_IMPL_PART_AOPG_TCM7_POWER_GATE_CONTROL_0_START_SHIFT)
#define PMC_IMPL_PART_AOPG_TCM7_POWER_GATE_CONTROL_0_START_RANGE                        8:8
#define PMC_IMPL_PART_AOPG_TCM7_POWER_GATE_CONTROL_0_START_MSB                  MK_SHIFT_CONST(8)
#define PMC_IMPL_PART_AOPG_TCM7_POWER_GATE_CONTROL_0_START_LSB                  MK_SHIFT_CONST(8)
#define PMC_IMPL_PART_AOPG_TCM7_POWER_GATE_CONTROL_0_START_WOFFSET                      0x0
#define PMC_IMPL_PART_AOPG_TCM7_POWER_GATE_CONTROL_0_START_DEFAULT                      MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM7_POWER_GATE_CONTROL_0_START_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AOPG_TCM7_POWER_GATE_CONTROL_0_START_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM7_POWER_GATE_CONTROL_0_START_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM7_POWER_GATE_CONTROL_0_START_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM7_POWER_GATE_CONTROL_0_START_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AOPG_TCM7_POWER_GATE_CONTROL_0_START_INIT_ENUM                    DONE
#define PMC_IMPL_PART_AOPG_TCM7_POWER_GATE_CONTROL_0_START_DONE                 MK_ENUM_CONST(0)
#define PMC_IMPL_PART_AOPG_TCM7_POWER_GATE_CONTROL_0_START_PENDING                      MK_ENUM_CONST(1)

#define PMC_IMPL_PART_AOPG_TCM7_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SHIFT                        MK_SHIFT_CONST(2)
#define PMC_IMPL_PART_AOPG_TCM7_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_FIELD                        MK_FIELD_CONST(0x1, PMC_IMPL_PART_AOPG_TCM7_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SHIFT)
#define PMC_IMPL_PART_AOPG_TCM7_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_RANGE                        2:2
#define PMC_IMPL_PART_AOPG_TCM7_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_MSB                  MK_SHIFT_CONST(2)
#define PMC_IMPL_PART_AOPG_TCM7_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_LSB                  MK_SHIFT_CONST(2)
#define PMC_IMPL_PART_AOPG_TCM7_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_WOFFSET                      0x0
#define PMC_IMPL_PART_AOPG_TCM7_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_DEFAULT                      MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM7_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AOPG_TCM7_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM7_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM7_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM7_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AOPG_TCM7_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_INIT_ENUM                    OFF
#define PMC_IMPL_PART_AOPG_TCM7_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_OFF                  MK_ENUM_CONST(0)
#define PMC_IMPL_PART_AOPG_TCM7_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_ON                   MK_ENUM_CONST(1)

#define PMC_IMPL_PART_AOPG_TCM7_POWER_GATE_CONTROL_0_SRAM_RET_EN_SHIFT                  MK_SHIFT_CONST(1)
#define PMC_IMPL_PART_AOPG_TCM7_POWER_GATE_CONTROL_0_SRAM_RET_EN_FIELD                  MK_FIELD_CONST(0x1, PMC_IMPL_PART_AOPG_TCM7_POWER_GATE_CONTROL_0_SRAM_RET_EN_SHIFT)
#define PMC_IMPL_PART_AOPG_TCM7_POWER_GATE_CONTROL_0_SRAM_RET_EN_RANGE                  1:1
#define PMC_IMPL_PART_AOPG_TCM7_POWER_GATE_CONTROL_0_SRAM_RET_EN_MSB                    MK_SHIFT_CONST(1)
#define PMC_IMPL_PART_AOPG_TCM7_POWER_GATE_CONTROL_0_SRAM_RET_EN_LSB                    MK_SHIFT_CONST(1)
#define PMC_IMPL_PART_AOPG_TCM7_POWER_GATE_CONTROL_0_SRAM_RET_EN_WOFFSET                        0x0
#define PMC_IMPL_PART_AOPG_TCM7_POWER_GATE_CONTROL_0_SRAM_RET_EN_DEFAULT                        MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM7_POWER_GATE_CONTROL_0_SRAM_RET_EN_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AOPG_TCM7_POWER_GATE_CONTROL_0_SRAM_RET_EN_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM7_POWER_GATE_CONTROL_0_SRAM_RET_EN_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM7_POWER_GATE_CONTROL_0_SRAM_RET_EN_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM7_POWER_GATE_CONTROL_0_SRAM_RET_EN_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AOPG_TCM7_POWER_GATE_CONTROL_0_SRAM_RET_EN_INIT_ENUM                      OFF
#define PMC_IMPL_PART_AOPG_TCM7_POWER_GATE_CONTROL_0_SRAM_RET_EN_OFF                    MK_ENUM_CONST(0)
#define PMC_IMPL_PART_AOPG_TCM7_POWER_GATE_CONTROL_0_SRAM_RET_EN_ON                     MK_ENUM_CONST(1)

#define PMC_IMPL_PART_AOPG_TCM7_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SHIFT                  MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_AOPG_TCM7_POWER_GATE_CONTROL_0_LOGIC_SLEEP_FIELD                  MK_FIELD_CONST(0x1, PMC_IMPL_PART_AOPG_TCM7_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SHIFT)
#define PMC_IMPL_PART_AOPG_TCM7_POWER_GATE_CONTROL_0_LOGIC_SLEEP_RANGE                  0:0
#define PMC_IMPL_PART_AOPG_TCM7_POWER_GATE_CONTROL_0_LOGIC_SLEEP_MSB                    MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_AOPG_TCM7_POWER_GATE_CONTROL_0_LOGIC_SLEEP_LSB                    MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_AOPG_TCM7_POWER_GATE_CONTROL_0_LOGIC_SLEEP_WOFFSET                        0x0
#define PMC_IMPL_PART_AOPG_TCM7_POWER_GATE_CONTROL_0_LOGIC_SLEEP_DEFAULT                        MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM7_POWER_GATE_CONTROL_0_LOGIC_SLEEP_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AOPG_TCM7_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM7_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM7_POWER_GATE_CONTROL_0_LOGIC_SLEEP_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM7_POWER_GATE_CONTROL_0_LOGIC_SLEEP_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AOPG_TCM7_POWER_GATE_CONTROL_0_LOGIC_SLEEP_INIT_ENUM                      OFF
#define PMC_IMPL_PART_AOPG_TCM7_POWER_GATE_CONTROL_0_LOGIC_SLEEP_OFF                    MK_ENUM_CONST(0)
#define PMC_IMPL_PART_AOPG_TCM7_POWER_GATE_CONTROL_0_LOGIC_SLEEP_ON                     MK_ENUM_CONST(1)


// Register PMC_IMPL_PART_AOPG_TCM7_POWER_GATE_STATUS_0
#define PMC_IMPL_PART_AOPG_TCM7_POWER_GATE_STATUS_0                     MK_ADDR_CONST(0x3e0)
#define PMC_IMPL_PART_AOPG_TCM7_POWER_GATE_STATUS_0_SECURE                      0x0
#define PMC_IMPL_PART_AOPG_TCM7_POWER_GATE_STATUS_0_DUAL                        0x0
#define PMC_IMPL_PART_AOPG_TCM7_POWER_GATE_STATUS_0_SCR                         PG_AOPG_TCM7_SCR_0
#define PMC_IMPL_PART_AOPG_TCM7_POWER_GATE_STATUS_0_SCRREG                      PMC_IMPL_SCR_PG_AOPG_TCM7_SCR_0
#define PMC_IMPL_PART_AOPG_TCM7_POWER_GATE_STATUS_0_WORD_COUNT                  0x1
#define PMC_IMPL_PART_AOPG_TCM7_POWER_GATE_STATUS_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM7_POWER_GATE_STATUS_0_RESET_MASK                  MK_MASK_CONST(0x7)
#define PMC_IMPL_PART_AOPG_TCM7_POWER_GATE_STATUS_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM7_POWER_GATE_STATUS_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM7_POWER_GATE_STATUS_0_READ_MASK                   MK_MASK_CONST(0x7)
#define PMC_IMPL_PART_AOPG_TCM7_POWER_GATE_STATUS_0_WRITE_MASK                  MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM7_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SHIFT                        MK_SHIFT_CONST(2)
#define PMC_IMPL_PART_AOPG_TCM7_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_FIELD                        MK_FIELD_CONST(0x1, PMC_IMPL_PART_AOPG_TCM7_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SHIFT)
#define PMC_IMPL_PART_AOPG_TCM7_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_RANGE                        2:2
#define PMC_IMPL_PART_AOPG_TCM7_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_MSB                  MK_SHIFT_CONST(2)
#define PMC_IMPL_PART_AOPG_TCM7_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_LSB                  MK_SHIFT_CONST(2)
#define PMC_IMPL_PART_AOPG_TCM7_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_WOFFSET                      0x0
#define PMC_IMPL_PART_AOPG_TCM7_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_DEFAULT                      MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM7_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AOPG_TCM7_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM7_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM7_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM7_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AOPG_TCM7_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_INIT_ENUM                    OFF
#define PMC_IMPL_PART_AOPG_TCM7_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_OFF                  MK_ENUM_CONST(0)
#define PMC_IMPL_PART_AOPG_TCM7_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_ON                   MK_ENUM_CONST(1)

#define PMC_IMPL_PART_AOPG_TCM7_POWER_GATE_STATUS_0_SRAM_RET_STS_SHIFT                  MK_SHIFT_CONST(1)
#define PMC_IMPL_PART_AOPG_TCM7_POWER_GATE_STATUS_0_SRAM_RET_STS_FIELD                  MK_FIELD_CONST(0x1, PMC_IMPL_PART_AOPG_TCM7_POWER_GATE_STATUS_0_SRAM_RET_STS_SHIFT)
#define PMC_IMPL_PART_AOPG_TCM7_POWER_GATE_STATUS_0_SRAM_RET_STS_RANGE                  1:1
#define PMC_IMPL_PART_AOPG_TCM7_POWER_GATE_STATUS_0_SRAM_RET_STS_MSB                    MK_SHIFT_CONST(1)
#define PMC_IMPL_PART_AOPG_TCM7_POWER_GATE_STATUS_0_SRAM_RET_STS_LSB                    MK_SHIFT_CONST(1)
#define PMC_IMPL_PART_AOPG_TCM7_POWER_GATE_STATUS_0_SRAM_RET_STS_WOFFSET                        0x0
#define PMC_IMPL_PART_AOPG_TCM7_POWER_GATE_STATUS_0_SRAM_RET_STS_DEFAULT                        MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM7_POWER_GATE_STATUS_0_SRAM_RET_STS_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AOPG_TCM7_POWER_GATE_STATUS_0_SRAM_RET_STS_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM7_POWER_GATE_STATUS_0_SRAM_RET_STS_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM7_POWER_GATE_STATUS_0_SRAM_RET_STS_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM7_POWER_GATE_STATUS_0_SRAM_RET_STS_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AOPG_TCM7_POWER_GATE_STATUS_0_SRAM_RET_STS_INIT_ENUM                      OFF
#define PMC_IMPL_PART_AOPG_TCM7_POWER_GATE_STATUS_0_SRAM_RET_STS_OFF                    MK_ENUM_CONST(0)
#define PMC_IMPL_PART_AOPG_TCM7_POWER_GATE_STATUS_0_SRAM_RET_STS_ON                     MK_ENUM_CONST(1)

#define PMC_IMPL_PART_AOPG_TCM7_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SHIFT                       MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_AOPG_TCM7_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_FIELD                       MK_FIELD_CONST(0x1, PMC_IMPL_PART_AOPG_TCM7_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SHIFT)
#define PMC_IMPL_PART_AOPG_TCM7_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_RANGE                       0:0
#define PMC_IMPL_PART_AOPG_TCM7_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_MSB                 MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_AOPG_TCM7_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_LSB                 MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_AOPG_TCM7_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_WOFFSET                     0x0
#define PMC_IMPL_PART_AOPG_TCM7_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_DEFAULT                     MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM7_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AOPG_TCM7_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM7_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM7_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM7_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AOPG_TCM7_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_INIT_ENUM                   OFF
#define PMC_IMPL_PART_AOPG_TCM7_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_OFF                 MK_ENUM_CONST(0)
#define PMC_IMPL_PART_AOPG_TCM7_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_ON                  MK_ENUM_CONST(1)


// Register PMC_IMPL_PART_AOPG_TCM7_CLAMP_CONTROL_0
#define PMC_IMPL_PART_AOPG_TCM7_CLAMP_CONTROL_0                 MK_ADDR_CONST(0x3e4)
#define PMC_IMPL_PART_AOPG_TCM7_CLAMP_CONTROL_0_SECURE                  0x0
#define PMC_IMPL_PART_AOPG_TCM7_CLAMP_CONTROL_0_DUAL                    0x0
#define PMC_IMPL_PART_AOPG_TCM7_CLAMP_CONTROL_0_SCR                     PG_AOPG_TCM7_SCR_0
#define PMC_IMPL_PART_AOPG_TCM7_CLAMP_CONTROL_0_SCRREG                  PMC_IMPL_SCR_PG_AOPG_TCM7_SCR_0
#define PMC_IMPL_PART_AOPG_TCM7_CLAMP_CONTROL_0_WORD_COUNT                      0x1
#define PMC_IMPL_PART_AOPG_TCM7_CLAMP_CONTROL_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM7_CLAMP_CONTROL_0_RESET_MASK                      MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AOPG_TCM7_CLAMP_CONTROL_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM7_CLAMP_CONTROL_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM7_CLAMP_CONTROL_0_READ_MASK                       MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AOPG_TCM7_CLAMP_CONTROL_0_WRITE_MASK                      MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM7_CLAMP_CONTROL_0_CLAMP_SHIFT                     MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_AOPG_TCM7_CLAMP_CONTROL_0_CLAMP_FIELD                     MK_FIELD_CONST(0x1, PMC_IMPL_PART_AOPG_TCM7_CLAMP_CONTROL_0_CLAMP_SHIFT)
#define PMC_IMPL_PART_AOPG_TCM7_CLAMP_CONTROL_0_CLAMP_RANGE                     0:0
#define PMC_IMPL_PART_AOPG_TCM7_CLAMP_CONTROL_0_CLAMP_MSB                       MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_AOPG_TCM7_CLAMP_CONTROL_0_CLAMP_LSB                       MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_AOPG_TCM7_CLAMP_CONTROL_0_CLAMP_WOFFSET                   0x0
#define PMC_IMPL_PART_AOPG_TCM7_CLAMP_CONTROL_0_CLAMP_DEFAULT                   MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM7_CLAMP_CONTROL_0_CLAMP_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AOPG_TCM7_CLAMP_CONTROL_0_CLAMP_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM7_CLAMP_CONTROL_0_CLAMP_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM7_CLAMP_CONTROL_0_CLAMP_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM7_CLAMP_CONTROL_0_CLAMP_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AOPG_TCM7_CLAMP_CONTROL_0_CLAMP_INIT_ENUM                 OFF
#define PMC_IMPL_PART_AOPG_TCM7_CLAMP_CONTROL_0_CLAMP_OFF                       MK_ENUM_CONST(0)
#define PMC_IMPL_PART_AOPG_TCM7_CLAMP_CONTROL_0_CLAMP_ON                        MK_ENUM_CONST(1)


// Register PMC_IMPL_PART_AOPG_CACHE_POWER_GATE_CONTROL_0
#define PMC_IMPL_PART_AOPG_CACHE_POWER_GATE_CONTROL_0                   MK_ADDR_CONST(0x3e8)
#define PMC_IMPL_PART_AOPG_CACHE_POWER_GATE_CONTROL_0_SECURE                    0x0
#define PMC_IMPL_PART_AOPG_CACHE_POWER_GATE_CONTROL_0_DUAL                      0x0
#define PMC_IMPL_PART_AOPG_CACHE_POWER_GATE_CONTROL_0_SCR                       PG_AOPG_CACHE_SCR_0
#define PMC_IMPL_PART_AOPG_CACHE_POWER_GATE_CONTROL_0_SCRREG                    PMC_IMPL_SCR_PG_AOPG_CACHE_SCR_0
#define PMC_IMPL_PART_AOPG_CACHE_POWER_GATE_CONTROL_0_WORD_COUNT                        0x1
#define PMC_IMPL_PART_AOPG_CACHE_POWER_GATE_CONTROL_0_RESET_VAL                         MK_MASK_CONST(0x80000000)
#define PMC_IMPL_PART_AOPG_CACHE_POWER_GATE_CONTROL_0_RESET_MASK                        MK_MASK_CONST(0x80000107)
#define PMC_IMPL_PART_AOPG_CACHE_POWER_GATE_CONTROL_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_CACHE_POWER_GATE_CONTROL_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_CACHE_POWER_GATE_CONTROL_0_READ_MASK                         MK_MASK_CONST(0x80000107)
#define PMC_IMPL_PART_AOPG_CACHE_POWER_GATE_CONTROL_0_WRITE_MASK                        MK_MASK_CONST(0x80000106)
#define PMC_IMPL_PART_AOPG_CACHE_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SHIFT                 MK_SHIFT_CONST(31)
#define PMC_IMPL_PART_AOPG_CACHE_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_FIELD                 MK_FIELD_CONST(0x1, PMC_IMPL_PART_AOPG_CACHE_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SHIFT)
#define PMC_IMPL_PART_AOPG_CACHE_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_RANGE                 31:31
#define PMC_IMPL_PART_AOPG_CACHE_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_MSB                   MK_SHIFT_CONST(31)
#define PMC_IMPL_PART_AOPG_CACHE_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_LSB                   MK_SHIFT_CONST(31)
#define PMC_IMPL_PART_AOPG_CACHE_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_WOFFSET                       0x0
#define PMC_IMPL_PART_AOPG_CACHE_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_DEFAULT                       MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AOPG_CACHE_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AOPG_CACHE_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_CACHE_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_CACHE_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_CACHE_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AOPG_CACHE_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_INIT_ENUM                     ENABLE
#define PMC_IMPL_PART_AOPG_CACHE_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_DISABLE                       MK_ENUM_CONST(0)
#define PMC_IMPL_PART_AOPG_CACHE_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_ENABLE                        MK_ENUM_CONST(1)

#define PMC_IMPL_PART_AOPG_CACHE_POWER_GATE_CONTROL_0_START_SHIFT                       MK_SHIFT_CONST(8)
#define PMC_IMPL_PART_AOPG_CACHE_POWER_GATE_CONTROL_0_START_FIELD                       MK_FIELD_CONST(0x1, PMC_IMPL_PART_AOPG_CACHE_POWER_GATE_CONTROL_0_START_SHIFT)
#define PMC_IMPL_PART_AOPG_CACHE_POWER_GATE_CONTROL_0_START_RANGE                       8:8
#define PMC_IMPL_PART_AOPG_CACHE_POWER_GATE_CONTROL_0_START_MSB                 MK_SHIFT_CONST(8)
#define PMC_IMPL_PART_AOPG_CACHE_POWER_GATE_CONTROL_0_START_LSB                 MK_SHIFT_CONST(8)
#define PMC_IMPL_PART_AOPG_CACHE_POWER_GATE_CONTROL_0_START_WOFFSET                     0x0
#define PMC_IMPL_PART_AOPG_CACHE_POWER_GATE_CONTROL_0_START_DEFAULT                     MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_CACHE_POWER_GATE_CONTROL_0_START_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AOPG_CACHE_POWER_GATE_CONTROL_0_START_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_CACHE_POWER_GATE_CONTROL_0_START_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_CACHE_POWER_GATE_CONTROL_0_START_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_CACHE_POWER_GATE_CONTROL_0_START_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AOPG_CACHE_POWER_GATE_CONTROL_0_START_INIT_ENUM                   DONE
#define PMC_IMPL_PART_AOPG_CACHE_POWER_GATE_CONTROL_0_START_DONE                        MK_ENUM_CONST(0)
#define PMC_IMPL_PART_AOPG_CACHE_POWER_GATE_CONTROL_0_START_PENDING                     MK_ENUM_CONST(1)

#define PMC_IMPL_PART_AOPG_CACHE_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SHIFT                       MK_SHIFT_CONST(2)
#define PMC_IMPL_PART_AOPG_CACHE_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_FIELD                       MK_FIELD_CONST(0x1, PMC_IMPL_PART_AOPG_CACHE_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SHIFT)
#define PMC_IMPL_PART_AOPG_CACHE_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_RANGE                       2:2
#define PMC_IMPL_PART_AOPG_CACHE_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_MSB                 MK_SHIFT_CONST(2)
#define PMC_IMPL_PART_AOPG_CACHE_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_LSB                 MK_SHIFT_CONST(2)
#define PMC_IMPL_PART_AOPG_CACHE_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_WOFFSET                     0x0
#define PMC_IMPL_PART_AOPG_CACHE_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_DEFAULT                     MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_CACHE_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AOPG_CACHE_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_CACHE_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_CACHE_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_CACHE_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AOPG_CACHE_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_INIT_ENUM                   OFF
#define PMC_IMPL_PART_AOPG_CACHE_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_OFF                 MK_ENUM_CONST(0)
#define PMC_IMPL_PART_AOPG_CACHE_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_ON                  MK_ENUM_CONST(1)

#define PMC_IMPL_PART_AOPG_CACHE_POWER_GATE_CONTROL_0_SRAM_RET_EN_SHIFT                 MK_SHIFT_CONST(1)
#define PMC_IMPL_PART_AOPG_CACHE_POWER_GATE_CONTROL_0_SRAM_RET_EN_FIELD                 MK_FIELD_CONST(0x1, PMC_IMPL_PART_AOPG_CACHE_POWER_GATE_CONTROL_0_SRAM_RET_EN_SHIFT)
#define PMC_IMPL_PART_AOPG_CACHE_POWER_GATE_CONTROL_0_SRAM_RET_EN_RANGE                 1:1
#define PMC_IMPL_PART_AOPG_CACHE_POWER_GATE_CONTROL_0_SRAM_RET_EN_MSB                   MK_SHIFT_CONST(1)
#define PMC_IMPL_PART_AOPG_CACHE_POWER_GATE_CONTROL_0_SRAM_RET_EN_LSB                   MK_SHIFT_CONST(1)
#define PMC_IMPL_PART_AOPG_CACHE_POWER_GATE_CONTROL_0_SRAM_RET_EN_WOFFSET                       0x0
#define PMC_IMPL_PART_AOPG_CACHE_POWER_GATE_CONTROL_0_SRAM_RET_EN_DEFAULT                       MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_CACHE_POWER_GATE_CONTROL_0_SRAM_RET_EN_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AOPG_CACHE_POWER_GATE_CONTROL_0_SRAM_RET_EN_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_CACHE_POWER_GATE_CONTROL_0_SRAM_RET_EN_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_CACHE_POWER_GATE_CONTROL_0_SRAM_RET_EN_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_CACHE_POWER_GATE_CONTROL_0_SRAM_RET_EN_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AOPG_CACHE_POWER_GATE_CONTROL_0_SRAM_RET_EN_INIT_ENUM                     OFF
#define PMC_IMPL_PART_AOPG_CACHE_POWER_GATE_CONTROL_0_SRAM_RET_EN_OFF                   MK_ENUM_CONST(0)
#define PMC_IMPL_PART_AOPG_CACHE_POWER_GATE_CONTROL_0_SRAM_RET_EN_ON                    MK_ENUM_CONST(1)

#define PMC_IMPL_PART_AOPG_CACHE_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SHIFT                 MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_AOPG_CACHE_POWER_GATE_CONTROL_0_LOGIC_SLEEP_FIELD                 MK_FIELD_CONST(0x1, PMC_IMPL_PART_AOPG_CACHE_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SHIFT)
#define PMC_IMPL_PART_AOPG_CACHE_POWER_GATE_CONTROL_0_LOGIC_SLEEP_RANGE                 0:0
#define PMC_IMPL_PART_AOPG_CACHE_POWER_GATE_CONTROL_0_LOGIC_SLEEP_MSB                   MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_AOPG_CACHE_POWER_GATE_CONTROL_0_LOGIC_SLEEP_LSB                   MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_AOPG_CACHE_POWER_GATE_CONTROL_0_LOGIC_SLEEP_WOFFSET                       0x0
#define PMC_IMPL_PART_AOPG_CACHE_POWER_GATE_CONTROL_0_LOGIC_SLEEP_DEFAULT                       MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_CACHE_POWER_GATE_CONTROL_0_LOGIC_SLEEP_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AOPG_CACHE_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_CACHE_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_CACHE_POWER_GATE_CONTROL_0_LOGIC_SLEEP_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_CACHE_POWER_GATE_CONTROL_0_LOGIC_SLEEP_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AOPG_CACHE_POWER_GATE_CONTROL_0_LOGIC_SLEEP_INIT_ENUM                     OFF
#define PMC_IMPL_PART_AOPG_CACHE_POWER_GATE_CONTROL_0_LOGIC_SLEEP_OFF                   MK_ENUM_CONST(0)
#define PMC_IMPL_PART_AOPG_CACHE_POWER_GATE_CONTROL_0_LOGIC_SLEEP_ON                    MK_ENUM_CONST(1)


// Register PMC_IMPL_PART_AOPG_CACHE_POWER_GATE_STATUS_0
#define PMC_IMPL_PART_AOPG_CACHE_POWER_GATE_STATUS_0                    MK_ADDR_CONST(0x3ec)
#define PMC_IMPL_PART_AOPG_CACHE_POWER_GATE_STATUS_0_SECURE                     0x0
#define PMC_IMPL_PART_AOPG_CACHE_POWER_GATE_STATUS_0_DUAL                       0x0
#define PMC_IMPL_PART_AOPG_CACHE_POWER_GATE_STATUS_0_SCR                        PG_AOPG_CACHE_SCR_0
#define PMC_IMPL_PART_AOPG_CACHE_POWER_GATE_STATUS_0_SCRREG                     PMC_IMPL_SCR_PG_AOPG_CACHE_SCR_0
#define PMC_IMPL_PART_AOPG_CACHE_POWER_GATE_STATUS_0_WORD_COUNT                         0x1
#define PMC_IMPL_PART_AOPG_CACHE_POWER_GATE_STATUS_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_CACHE_POWER_GATE_STATUS_0_RESET_MASK                         MK_MASK_CONST(0x7)
#define PMC_IMPL_PART_AOPG_CACHE_POWER_GATE_STATUS_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_CACHE_POWER_GATE_STATUS_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_CACHE_POWER_GATE_STATUS_0_READ_MASK                  MK_MASK_CONST(0x7)
#define PMC_IMPL_PART_AOPG_CACHE_POWER_GATE_STATUS_0_WRITE_MASK                         MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_CACHE_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SHIFT                       MK_SHIFT_CONST(2)
#define PMC_IMPL_PART_AOPG_CACHE_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_FIELD                       MK_FIELD_CONST(0x1, PMC_IMPL_PART_AOPG_CACHE_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SHIFT)
#define PMC_IMPL_PART_AOPG_CACHE_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_RANGE                       2:2
#define PMC_IMPL_PART_AOPG_CACHE_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_MSB                 MK_SHIFT_CONST(2)
#define PMC_IMPL_PART_AOPG_CACHE_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_LSB                 MK_SHIFT_CONST(2)
#define PMC_IMPL_PART_AOPG_CACHE_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_WOFFSET                     0x0
#define PMC_IMPL_PART_AOPG_CACHE_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_DEFAULT                     MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_CACHE_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AOPG_CACHE_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_CACHE_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_CACHE_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_CACHE_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AOPG_CACHE_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_INIT_ENUM                   OFF
#define PMC_IMPL_PART_AOPG_CACHE_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_OFF                 MK_ENUM_CONST(0)
#define PMC_IMPL_PART_AOPG_CACHE_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_ON                  MK_ENUM_CONST(1)

#define PMC_IMPL_PART_AOPG_CACHE_POWER_GATE_STATUS_0_SRAM_RET_STS_SHIFT                 MK_SHIFT_CONST(1)
#define PMC_IMPL_PART_AOPG_CACHE_POWER_GATE_STATUS_0_SRAM_RET_STS_FIELD                 MK_FIELD_CONST(0x1, PMC_IMPL_PART_AOPG_CACHE_POWER_GATE_STATUS_0_SRAM_RET_STS_SHIFT)
#define PMC_IMPL_PART_AOPG_CACHE_POWER_GATE_STATUS_0_SRAM_RET_STS_RANGE                 1:1
#define PMC_IMPL_PART_AOPG_CACHE_POWER_GATE_STATUS_0_SRAM_RET_STS_MSB                   MK_SHIFT_CONST(1)
#define PMC_IMPL_PART_AOPG_CACHE_POWER_GATE_STATUS_0_SRAM_RET_STS_LSB                   MK_SHIFT_CONST(1)
#define PMC_IMPL_PART_AOPG_CACHE_POWER_GATE_STATUS_0_SRAM_RET_STS_WOFFSET                       0x0
#define PMC_IMPL_PART_AOPG_CACHE_POWER_GATE_STATUS_0_SRAM_RET_STS_DEFAULT                       MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_CACHE_POWER_GATE_STATUS_0_SRAM_RET_STS_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AOPG_CACHE_POWER_GATE_STATUS_0_SRAM_RET_STS_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_CACHE_POWER_GATE_STATUS_0_SRAM_RET_STS_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_CACHE_POWER_GATE_STATUS_0_SRAM_RET_STS_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_CACHE_POWER_GATE_STATUS_0_SRAM_RET_STS_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AOPG_CACHE_POWER_GATE_STATUS_0_SRAM_RET_STS_INIT_ENUM                     OFF
#define PMC_IMPL_PART_AOPG_CACHE_POWER_GATE_STATUS_0_SRAM_RET_STS_OFF                   MK_ENUM_CONST(0)
#define PMC_IMPL_PART_AOPG_CACHE_POWER_GATE_STATUS_0_SRAM_RET_STS_ON                    MK_ENUM_CONST(1)

#define PMC_IMPL_PART_AOPG_CACHE_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SHIFT                      MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_AOPG_CACHE_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_FIELD                      MK_FIELD_CONST(0x1, PMC_IMPL_PART_AOPG_CACHE_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SHIFT)
#define PMC_IMPL_PART_AOPG_CACHE_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_RANGE                      0:0
#define PMC_IMPL_PART_AOPG_CACHE_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_MSB                        MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_AOPG_CACHE_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_LSB                        MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_AOPG_CACHE_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_WOFFSET                    0x0
#define PMC_IMPL_PART_AOPG_CACHE_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_DEFAULT                    MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_CACHE_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AOPG_CACHE_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_CACHE_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_CACHE_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_CACHE_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AOPG_CACHE_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_INIT_ENUM                  OFF
#define PMC_IMPL_PART_AOPG_CACHE_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_OFF                        MK_ENUM_CONST(0)
#define PMC_IMPL_PART_AOPG_CACHE_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_ON                 MK_ENUM_CONST(1)


// Register PMC_IMPL_PART_AOPG_CACHE_CLAMP_CONTROL_0
#define PMC_IMPL_PART_AOPG_CACHE_CLAMP_CONTROL_0                        MK_ADDR_CONST(0x3f0)
#define PMC_IMPL_PART_AOPG_CACHE_CLAMP_CONTROL_0_SECURE                         0x0
#define PMC_IMPL_PART_AOPG_CACHE_CLAMP_CONTROL_0_DUAL                   0x0
#define PMC_IMPL_PART_AOPG_CACHE_CLAMP_CONTROL_0_SCR                    PG_AOPG_CACHE_SCR_0
#define PMC_IMPL_PART_AOPG_CACHE_CLAMP_CONTROL_0_SCRREG                         PMC_IMPL_SCR_PG_AOPG_CACHE_SCR_0
#define PMC_IMPL_PART_AOPG_CACHE_CLAMP_CONTROL_0_WORD_COUNT                     0x1
#define PMC_IMPL_PART_AOPG_CACHE_CLAMP_CONTROL_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_CACHE_CLAMP_CONTROL_0_RESET_MASK                     MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AOPG_CACHE_CLAMP_CONTROL_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_CACHE_CLAMP_CONTROL_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_CACHE_CLAMP_CONTROL_0_READ_MASK                      MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AOPG_CACHE_CLAMP_CONTROL_0_WRITE_MASK                     MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_CACHE_CLAMP_CONTROL_0_CLAMP_SHIFT                    MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_AOPG_CACHE_CLAMP_CONTROL_0_CLAMP_FIELD                    MK_FIELD_CONST(0x1, PMC_IMPL_PART_AOPG_CACHE_CLAMP_CONTROL_0_CLAMP_SHIFT)
#define PMC_IMPL_PART_AOPG_CACHE_CLAMP_CONTROL_0_CLAMP_RANGE                    0:0
#define PMC_IMPL_PART_AOPG_CACHE_CLAMP_CONTROL_0_CLAMP_MSB                      MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_AOPG_CACHE_CLAMP_CONTROL_0_CLAMP_LSB                      MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_AOPG_CACHE_CLAMP_CONTROL_0_CLAMP_WOFFSET                  0x0
#define PMC_IMPL_PART_AOPG_CACHE_CLAMP_CONTROL_0_CLAMP_DEFAULT                  MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_CACHE_CLAMP_CONTROL_0_CLAMP_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AOPG_CACHE_CLAMP_CONTROL_0_CLAMP_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_CACHE_CLAMP_CONTROL_0_CLAMP_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_CACHE_CLAMP_CONTROL_0_CLAMP_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_CACHE_CLAMP_CONTROL_0_CLAMP_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AOPG_CACHE_CLAMP_CONTROL_0_CLAMP_INIT_ENUM                        OFF
#define PMC_IMPL_PART_AOPG_CACHE_CLAMP_CONTROL_0_CLAMP_OFF                      MK_ENUM_CONST(0)
#define PMC_IMPL_PART_AOPG_CACHE_CLAMP_CONTROL_0_CLAMP_ON                       MK_ENUM_CONST(1)


// Register PMC_IMPL_PART_AOPG_CAN0_POWER_GATE_CONTROL_0
#define PMC_IMPL_PART_AOPG_CAN0_POWER_GATE_CONTROL_0                    MK_ADDR_CONST(0x3f4)
#define PMC_IMPL_PART_AOPG_CAN0_POWER_GATE_CONTROL_0_SECURE                     0x0
#define PMC_IMPL_PART_AOPG_CAN0_POWER_GATE_CONTROL_0_DUAL                       0x0
#define PMC_IMPL_PART_AOPG_CAN0_POWER_GATE_CONTROL_0_SCR                        PG_AOPG_CAN0_SCR_0
#define PMC_IMPL_PART_AOPG_CAN0_POWER_GATE_CONTROL_0_SCRREG                     PMC_IMPL_SCR_PG_AOPG_CAN0_SCR_0
#define PMC_IMPL_PART_AOPG_CAN0_POWER_GATE_CONTROL_0_WORD_COUNT                         0x1
#define PMC_IMPL_PART_AOPG_CAN0_POWER_GATE_CONTROL_0_RESET_VAL                  MK_MASK_CONST(0x80000000)
#define PMC_IMPL_PART_AOPG_CAN0_POWER_GATE_CONTROL_0_RESET_MASK                         MK_MASK_CONST(0x80000107)
#define PMC_IMPL_PART_AOPG_CAN0_POWER_GATE_CONTROL_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_CAN0_POWER_GATE_CONTROL_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_CAN0_POWER_GATE_CONTROL_0_READ_MASK                  MK_MASK_CONST(0x80000107)
#define PMC_IMPL_PART_AOPG_CAN0_POWER_GATE_CONTROL_0_WRITE_MASK                         MK_MASK_CONST(0x80000106)
#define PMC_IMPL_PART_AOPG_CAN0_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SHIFT                  MK_SHIFT_CONST(31)
#define PMC_IMPL_PART_AOPG_CAN0_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_FIELD                  MK_FIELD_CONST(0x1, PMC_IMPL_PART_AOPG_CAN0_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SHIFT)
#define PMC_IMPL_PART_AOPG_CAN0_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_RANGE                  31:31
#define PMC_IMPL_PART_AOPG_CAN0_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_MSB                    MK_SHIFT_CONST(31)
#define PMC_IMPL_PART_AOPG_CAN0_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_LSB                    MK_SHIFT_CONST(31)
#define PMC_IMPL_PART_AOPG_CAN0_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_WOFFSET                        0x0
#define PMC_IMPL_PART_AOPG_CAN0_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_DEFAULT                        MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AOPG_CAN0_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AOPG_CAN0_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_CAN0_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_CAN0_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_CAN0_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AOPG_CAN0_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_INIT_ENUM                      ENABLE
#define PMC_IMPL_PART_AOPG_CAN0_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_DISABLE                        MK_ENUM_CONST(0)
#define PMC_IMPL_PART_AOPG_CAN0_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_ENABLE                 MK_ENUM_CONST(1)

#define PMC_IMPL_PART_AOPG_CAN0_POWER_GATE_CONTROL_0_START_SHIFT                        MK_SHIFT_CONST(8)
#define PMC_IMPL_PART_AOPG_CAN0_POWER_GATE_CONTROL_0_START_FIELD                        MK_FIELD_CONST(0x1, PMC_IMPL_PART_AOPG_CAN0_POWER_GATE_CONTROL_0_START_SHIFT)
#define PMC_IMPL_PART_AOPG_CAN0_POWER_GATE_CONTROL_0_START_RANGE                        8:8
#define PMC_IMPL_PART_AOPG_CAN0_POWER_GATE_CONTROL_0_START_MSB                  MK_SHIFT_CONST(8)
#define PMC_IMPL_PART_AOPG_CAN0_POWER_GATE_CONTROL_0_START_LSB                  MK_SHIFT_CONST(8)
#define PMC_IMPL_PART_AOPG_CAN0_POWER_GATE_CONTROL_0_START_WOFFSET                      0x0
#define PMC_IMPL_PART_AOPG_CAN0_POWER_GATE_CONTROL_0_START_DEFAULT                      MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_CAN0_POWER_GATE_CONTROL_0_START_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AOPG_CAN0_POWER_GATE_CONTROL_0_START_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_CAN0_POWER_GATE_CONTROL_0_START_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_CAN0_POWER_GATE_CONTROL_0_START_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_CAN0_POWER_GATE_CONTROL_0_START_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AOPG_CAN0_POWER_GATE_CONTROL_0_START_INIT_ENUM                    DONE
#define PMC_IMPL_PART_AOPG_CAN0_POWER_GATE_CONTROL_0_START_DONE                 MK_ENUM_CONST(0)
#define PMC_IMPL_PART_AOPG_CAN0_POWER_GATE_CONTROL_0_START_PENDING                      MK_ENUM_CONST(1)

#define PMC_IMPL_PART_AOPG_CAN0_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SHIFT                        MK_SHIFT_CONST(2)
#define PMC_IMPL_PART_AOPG_CAN0_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_FIELD                        MK_FIELD_CONST(0x1, PMC_IMPL_PART_AOPG_CAN0_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SHIFT)
#define PMC_IMPL_PART_AOPG_CAN0_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_RANGE                        2:2
#define PMC_IMPL_PART_AOPG_CAN0_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_MSB                  MK_SHIFT_CONST(2)
#define PMC_IMPL_PART_AOPG_CAN0_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_LSB                  MK_SHIFT_CONST(2)
#define PMC_IMPL_PART_AOPG_CAN0_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_WOFFSET                      0x0
#define PMC_IMPL_PART_AOPG_CAN0_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_DEFAULT                      MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_CAN0_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AOPG_CAN0_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_CAN0_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_CAN0_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_CAN0_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AOPG_CAN0_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_INIT_ENUM                    OFF
#define PMC_IMPL_PART_AOPG_CAN0_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_OFF                  MK_ENUM_CONST(0)
#define PMC_IMPL_PART_AOPG_CAN0_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_ON                   MK_ENUM_CONST(1)

#define PMC_IMPL_PART_AOPG_CAN0_POWER_GATE_CONTROL_0_SRAM_RET_EN_SHIFT                  MK_SHIFT_CONST(1)
#define PMC_IMPL_PART_AOPG_CAN0_POWER_GATE_CONTROL_0_SRAM_RET_EN_FIELD                  MK_FIELD_CONST(0x1, PMC_IMPL_PART_AOPG_CAN0_POWER_GATE_CONTROL_0_SRAM_RET_EN_SHIFT)
#define PMC_IMPL_PART_AOPG_CAN0_POWER_GATE_CONTROL_0_SRAM_RET_EN_RANGE                  1:1
#define PMC_IMPL_PART_AOPG_CAN0_POWER_GATE_CONTROL_0_SRAM_RET_EN_MSB                    MK_SHIFT_CONST(1)
#define PMC_IMPL_PART_AOPG_CAN0_POWER_GATE_CONTROL_0_SRAM_RET_EN_LSB                    MK_SHIFT_CONST(1)
#define PMC_IMPL_PART_AOPG_CAN0_POWER_GATE_CONTROL_0_SRAM_RET_EN_WOFFSET                        0x0
#define PMC_IMPL_PART_AOPG_CAN0_POWER_GATE_CONTROL_0_SRAM_RET_EN_DEFAULT                        MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_CAN0_POWER_GATE_CONTROL_0_SRAM_RET_EN_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AOPG_CAN0_POWER_GATE_CONTROL_0_SRAM_RET_EN_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_CAN0_POWER_GATE_CONTROL_0_SRAM_RET_EN_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_CAN0_POWER_GATE_CONTROL_0_SRAM_RET_EN_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_CAN0_POWER_GATE_CONTROL_0_SRAM_RET_EN_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AOPG_CAN0_POWER_GATE_CONTROL_0_SRAM_RET_EN_INIT_ENUM                      OFF
#define PMC_IMPL_PART_AOPG_CAN0_POWER_GATE_CONTROL_0_SRAM_RET_EN_OFF                    MK_ENUM_CONST(0)
#define PMC_IMPL_PART_AOPG_CAN0_POWER_GATE_CONTROL_0_SRAM_RET_EN_ON                     MK_ENUM_CONST(1)

#define PMC_IMPL_PART_AOPG_CAN0_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SHIFT                  MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_AOPG_CAN0_POWER_GATE_CONTROL_0_LOGIC_SLEEP_FIELD                  MK_FIELD_CONST(0x1, PMC_IMPL_PART_AOPG_CAN0_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SHIFT)
#define PMC_IMPL_PART_AOPG_CAN0_POWER_GATE_CONTROL_0_LOGIC_SLEEP_RANGE                  0:0
#define PMC_IMPL_PART_AOPG_CAN0_POWER_GATE_CONTROL_0_LOGIC_SLEEP_MSB                    MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_AOPG_CAN0_POWER_GATE_CONTROL_0_LOGIC_SLEEP_LSB                    MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_AOPG_CAN0_POWER_GATE_CONTROL_0_LOGIC_SLEEP_WOFFSET                        0x0
#define PMC_IMPL_PART_AOPG_CAN0_POWER_GATE_CONTROL_0_LOGIC_SLEEP_DEFAULT                        MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_CAN0_POWER_GATE_CONTROL_0_LOGIC_SLEEP_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AOPG_CAN0_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_CAN0_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_CAN0_POWER_GATE_CONTROL_0_LOGIC_SLEEP_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_CAN0_POWER_GATE_CONTROL_0_LOGIC_SLEEP_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AOPG_CAN0_POWER_GATE_CONTROL_0_LOGIC_SLEEP_INIT_ENUM                      OFF
#define PMC_IMPL_PART_AOPG_CAN0_POWER_GATE_CONTROL_0_LOGIC_SLEEP_OFF                    MK_ENUM_CONST(0)
#define PMC_IMPL_PART_AOPG_CAN0_POWER_GATE_CONTROL_0_LOGIC_SLEEP_ON                     MK_ENUM_CONST(1)


// Register PMC_IMPL_PART_AOPG_CAN0_POWER_GATE_STATUS_0
#define PMC_IMPL_PART_AOPG_CAN0_POWER_GATE_STATUS_0                     MK_ADDR_CONST(0x3f8)
#define PMC_IMPL_PART_AOPG_CAN0_POWER_GATE_STATUS_0_SECURE                      0x0
#define PMC_IMPL_PART_AOPG_CAN0_POWER_GATE_STATUS_0_DUAL                        0x0
#define PMC_IMPL_PART_AOPG_CAN0_POWER_GATE_STATUS_0_SCR                         PG_AOPG_CAN0_SCR_0
#define PMC_IMPL_PART_AOPG_CAN0_POWER_GATE_STATUS_0_SCRREG                      PMC_IMPL_SCR_PG_AOPG_CAN0_SCR_0
#define PMC_IMPL_PART_AOPG_CAN0_POWER_GATE_STATUS_0_WORD_COUNT                  0x1
#define PMC_IMPL_PART_AOPG_CAN0_POWER_GATE_STATUS_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_CAN0_POWER_GATE_STATUS_0_RESET_MASK                  MK_MASK_CONST(0x7)
#define PMC_IMPL_PART_AOPG_CAN0_POWER_GATE_STATUS_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_CAN0_POWER_GATE_STATUS_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_CAN0_POWER_GATE_STATUS_0_READ_MASK                   MK_MASK_CONST(0x7)
#define PMC_IMPL_PART_AOPG_CAN0_POWER_GATE_STATUS_0_WRITE_MASK                  MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_CAN0_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SHIFT                        MK_SHIFT_CONST(2)
#define PMC_IMPL_PART_AOPG_CAN0_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_FIELD                        MK_FIELD_CONST(0x1, PMC_IMPL_PART_AOPG_CAN0_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SHIFT)
#define PMC_IMPL_PART_AOPG_CAN0_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_RANGE                        2:2
#define PMC_IMPL_PART_AOPG_CAN0_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_MSB                  MK_SHIFT_CONST(2)
#define PMC_IMPL_PART_AOPG_CAN0_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_LSB                  MK_SHIFT_CONST(2)
#define PMC_IMPL_PART_AOPG_CAN0_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_WOFFSET                      0x0
#define PMC_IMPL_PART_AOPG_CAN0_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_DEFAULT                      MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_CAN0_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AOPG_CAN0_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_CAN0_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_CAN0_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_CAN0_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AOPG_CAN0_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_INIT_ENUM                    OFF
#define PMC_IMPL_PART_AOPG_CAN0_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_OFF                  MK_ENUM_CONST(0)
#define PMC_IMPL_PART_AOPG_CAN0_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_ON                   MK_ENUM_CONST(1)

#define PMC_IMPL_PART_AOPG_CAN0_POWER_GATE_STATUS_0_SRAM_RET_STS_SHIFT                  MK_SHIFT_CONST(1)
#define PMC_IMPL_PART_AOPG_CAN0_POWER_GATE_STATUS_0_SRAM_RET_STS_FIELD                  MK_FIELD_CONST(0x1, PMC_IMPL_PART_AOPG_CAN0_POWER_GATE_STATUS_0_SRAM_RET_STS_SHIFT)
#define PMC_IMPL_PART_AOPG_CAN0_POWER_GATE_STATUS_0_SRAM_RET_STS_RANGE                  1:1
#define PMC_IMPL_PART_AOPG_CAN0_POWER_GATE_STATUS_0_SRAM_RET_STS_MSB                    MK_SHIFT_CONST(1)
#define PMC_IMPL_PART_AOPG_CAN0_POWER_GATE_STATUS_0_SRAM_RET_STS_LSB                    MK_SHIFT_CONST(1)
#define PMC_IMPL_PART_AOPG_CAN0_POWER_GATE_STATUS_0_SRAM_RET_STS_WOFFSET                        0x0
#define PMC_IMPL_PART_AOPG_CAN0_POWER_GATE_STATUS_0_SRAM_RET_STS_DEFAULT                        MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_CAN0_POWER_GATE_STATUS_0_SRAM_RET_STS_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AOPG_CAN0_POWER_GATE_STATUS_0_SRAM_RET_STS_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_CAN0_POWER_GATE_STATUS_0_SRAM_RET_STS_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_CAN0_POWER_GATE_STATUS_0_SRAM_RET_STS_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_CAN0_POWER_GATE_STATUS_0_SRAM_RET_STS_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AOPG_CAN0_POWER_GATE_STATUS_0_SRAM_RET_STS_INIT_ENUM                      OFF
#define PMC_IMPL_PART_AOPG_CAN0_POWER_GATE_STATUS_0_SRAM_RET_STS_OFF                    MK_ENUM_CONST(0)
#define PMC_IMPL_PART_AOPG_CAN0_POWER_GATE_STATUS_0_SRAM_RET_STS_ON                     MK_ENUM_CONST(1)

#define PMC_IMPL_PART_AOPG_CAN0_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SHIFT                       MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_AOPG_CAN0_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_FIELD                       MK_FIELD_CONST(0x1, PMC_IMPL_PART_AOPG_CAN0_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SHIFT)
#define PMC_IMPL_PART_AOPG_CAN0_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_RANGE                       0:0
#define PMC_IMPL_PART_AOPG_CAN0_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_MSB                 MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_AOPG_CAN0_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_LSB                 MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_AOPG_CAN0_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_WOFFSET                     0x0
#define PMC_IMPL_PART_AOPG_CAN0_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_DEFAULT                     MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_CAN0_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AOPG_CAN0_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_CAN0_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_CAN0_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_CAN0_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AOPG_CAN0_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_INIT_ENUM                   OFF
#define PMC_IMPL_PART_AOPG_CAN0_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_OFF                 MK_ENUM_CONST(0)
#define PMC_IMPL_PART_AOPG_CAN0_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_ON                  MK_ENUM_CONST(1)


// Register PMC_IMPL_PART_AOPG_CAN0_CLAMP_CONTROL_0
#define PMC_IMPL_PART_AOPG_CAN0_CLAMP_CONTROL_0                 MK_ADDR_CONST(0x3fc)
#define PMC_IMPL_PART_AOPG_CAN0_CLAMP_CONTROL_0_SECURE                  0x0
#define PMC_IMPL_PART_AOPG_CAN0_CLAMP_CONTROL_0_DUAL                    0x0
#define PMC_IMPL_PART_AOPG_CAN0_CLAMP_CONTROL_0_SCR                     PG_AOPG_CAN0_SCR_0
#define PMC_IMPL_PART_AOPG_CAN0_CLAMP_CONTROL_0_SCRREG                  PMC_IMPL_SCR_PG_AOPG_CAN0_SCR_0
#define PMC_IMPL_PART_AOPG_CAN0_CLAMP_CONTROL_0_WORD_COUNT                      0x1
#define PMC_IMPL_PART_AOPG_CAN0_CLAMP_CONTROL_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_CAN0_CLAMP_CONTROL_0_RESET_MASK                      MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AOPG_CAN0_CLAMP_CONTROL_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_CAN0_CLAMP_CONTROL_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_CAN0_CLAMP_CONTROL_0_READ_MASK                       MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AOPG_CAN0_CLAMP_CONTROL_0_WRITE_MASK                      MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_CAN0_CLAMP_CONTROL_0_CLAMP_SHIFT                     MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_AOPG_CAN0_CLAMP_CONTROL_0_CLAMP_FIELD                     MK_FIELD_CONST(0x1, PMC_IMPL_PART_AOPG_CAN0_CLAMP_CONTROL_0_CLAMP_SHIFT)
#define PMC_IMPL_PART_AOPG_CAN0_CLAMP_CONTROL_0_CLAMP_RANGE                     0:0
#define PMC_IMPL_PART_AOPG_CAN0_CLAMP_CONTROL_0_CLAMP_MSB                       MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_AOPG_CAN0_CLAMP_CONTROL_0_CLAMP_LSB                       MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_AOPG_CAN0_CLAMP_CONTROL_0_CLAMP_WOFFSET                   0x0
#define PMC_IMPL_PART_AOPG_CAN0_CLAMP_CONTROL_0_CLAMP_DEFAULT                   MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_CAN0_CLAMP_CONTROL_0_CLAMP_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AOPG_CAN0_CLAMP_CONTROL_0_CLAMP_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_CAN0_CLAMP_CONTROL_0_CLAMP_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_CAN0_CLAMP_CONTROL_0_CLAMP_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_CAN0_CLAMP_CONTROL_0_CLAMP_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AOPG_CAN0_CLAMP_CONTROL_0_CLAMP_INIT_ENUM                 OFF
#define PMC_IMPL_PART_AOPG_CAN0_CLAMP_CONTROL_0_CLAMP_OFF                       MK_ENUM_CONST(0)
#define PMC_IMPL_PART_AOPG_CAN0_CLAMP_CONTROL_0_CLAMP_ON                        MK_ENUM_CONST(1)


// Register PMC_IMPL_PART_AOPG_CAN1_POWER_GATE_CONTROL_0
#define PMC_IMPL_PART_AOPG_CAN1_POWER_GATE_CONTROL_0                    MK_ADDR_CONST(0x400)
#define PMC_IMPL_PART_AOPG_CAN1_POWER_GATE_CONTROL_0_SECURE                     0x0
#define PMC_IMPL_PART_AOPG_CAN1_POWER_GATE_CONTROL_0_DUAL                       0x0
#define PMC_IMPL_PART_AOPG_CAN1_POWER_GATE_CONTROL_0_SCR                        PG_AOPG_CAN1_SCR_0
#define PMC_IMPL_PART_AOPG_CAN1_POWER_GATE_CONTROL_0_SCRREG                     PMC_IMPL_SCR_PG_AOPG_CAN1_SCR_0
#define PMC_IMPL_PART_AOPG_CAN1_POWER_GATE_CONTROL_0_WORD_COUNT                         0x1
#define PMC_IMPL_PART_AOPG_CAN1_POWER_GATE_CONTROL_0_RESET_VAL                  MK_MASK_CONST(0x80000000)
#define PMC_IMPL_PART_AOPG_CAN1_POWER_GATE_CONTROL_0_RESET_MASK                         MK_MASK_CONST(0x80000107)
#define PMC_IMPL_PART_AOPG_CAN1_POWER_GATE_CONTROL_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_CAN1_POWER_GATE_CONTROL_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_CAN1_POWER_GATE_CONTROL_0_READ_MASK                  MK_MASK_CONST(0x80000107)
#define PMC_IMPL_PART_AOPG_CAN1_POWER_GATE_CONTROL_0_WRITE_MASK                         MK_MASK_CONST(0x80000106)
#define PMC_IMPL_PART_AOPG_CAN1_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SHIFT                  MK_SHIFT_CONST(31)
#define PMC_IMPL_PART_AOPG_CAN1_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_FIELD                  MK_FIELD_CONST(0x1, PMC_IMPL_PART_AOPG_CAN1_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SHIFT)
#define PMC_IMPL_PART_AOPG_CAN1_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_RANGE                  31:31
#define PMC_IMPL_PART_AOPG_CAN1_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_MSB                    MK_SHIFT_CONST(31)
#define PMC_IMPL_PART_AOPG_CAN1_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_LSB                    MK_SHIFT_CONST(31)
#define PMC_IMPL_PART_AOPG_CAN1_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_WOFFSET                        0x0
#define PMC_IMPL_PART_AOPG_CAN1_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_DEFAULT                        MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AOPG_CAN1_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AOPG_CAN1_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_CAN1_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_CAN1_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_CAN1_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AOPG_CAN1_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_INIT_ENUM                      ENABLE
#define PMC_IMPL_PART_AOPG_CAN1_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_DISABLE                        MK_ENUM_CONST(0)
#define PMC_IMPL_PART_AOPG_CAN1_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_ENABLE                 MK_ENUM_CONST(1)

#define PMC_IMPL_PART_AOPG_CAN1_POWER_GATE_CONTROL_0_START_SHIFT                        MK_SHIFT_CONST(8)
#define PMC_IMPL_PART_AOPG_CAN1_POWER_GATE_CONTROL_0_START_FIELD                        MK_FIELD_CONST(0x1, PMC_IMPL_PART_AOPG_CAN1_POWER_GATE_CONTROL_0_START_SHIFT)
#define PMC_IMPL_PART_AOPG_CAN1_POWER_GATE_CONTROL_0_START_RANGE                        8:8
#define PMC_IMPL_PART_AOPG_CAN1_POWER_GATE_CONTROL_0_START_MSB                  MK_SHIFT_CONST(8)
#define PMC_IMPL_PART_AOPG_CAN1_POWER_GATE_CONTROL_0_START_LSB                  MK_SHIFT_CONST(8)
#define PMC_IMPL_PART_AOPG_CAN1_POWER_GATE_CONTROL_0_START_WOFFSET                      0x0
#define PMC_IMPL_PART_AOPG_CAN1_POWER_GATE_CONTROL_0_START_DEFAULT                      MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_CAN1_POWER_GATE_CONTROL_0_START_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AOPG_CAN1_POWER_GATE_CONTROL_0_START_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_CAN1_POWER_GATE_CONTROL_0_START_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_CAN1_POWER_GATE_CONTROL_0_START_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_CAN1_POWER_GATE_CONTROL_0_START_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AOPG_CAN1_POWER_GATE_CONTROL_0_START_INIT_ENUM                    DONE
#define PMC_IMPL_PART_AOPG_CAN1_POWER_GATE_CONTROL_0_START_DONE                 MK_ENUM_CONST(0)
#define PMC_IMPL_PART_AOPG_CAN1_POWER_GATE_CONTROL_0_START_PENDING                      MK_ENUM_CONST(1)

#define PMC_IMPL_PART_AOPG_CAN1_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SHIFT                        MK_SHIFT_CONST(2)
#define PMC_IMPL_PART_AOPG_CAN1_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_FIELD                        MK_FIELD_CONST(0x1, PMC_IMPL_PART_AOPG_CAN1_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SHIFT)
#define PMC_IMPL_PART_AOPG_CAN1_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_RANGE                        2:2
#define PMC_IMPL_PART_AOPG_CAN1_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_MSB                  MK_SHIFT_CONST(2)
#define PMC_IMPL_PART_AOPG_CAN1_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_LSB                  MK_SHIFT_CONST(2)
#define PMC_IMPL_PART_AOPG_CAN1_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_WOFFSET                      0x0
#define PMC_IMPL_PART_AOPG_CAN1_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_DEFAULT                      MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_CAN1_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AOPG_CAN1_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_CAN1_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_CAN1_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_CAN1_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AOPG_CAN1_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_INIT_ENUM                    OFF
#define PMC_IMPL_PART_AOPG_CAN1_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_OFF                  MK_ENUM_CONST(0)
#define PMC_IMPL_PART_AOPG_CAN1_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_ON                   MK_ENUM_CONST(1)

#define PMC_IMPL_PART_AOPG_CAN1_POWER_GATE_CONTROL_0_SRAM_RET_EN_SHIFT                  MK_SHIFT_CONST(1)
#define PMC_IMPL_PART_AOPG_CAN1_POWER_GATE_CONTROL_0_SRAM_RET_EN_FIELD                  MK_FIELD_CONST(0x1, PMC_IMPL_PART_AOPG_CAN1_POWER_GATE_CONTROL_0_SRAM_RET_EN_SHIFT)
#define PMC_IMPL_PART_AOPG_CAN1_POWER_GATE_CONTROL_0_SRAM_RET_EN_RANGE                  1:1
#define PMC_IMPL_PART_AOPG_CAN1_POWER_GATE_CONTROL_0_SRAM_RET_EN_MSB                    MK_SHIFT_CONST(1)
#define PMC_IMPL_PART_AOPG_CAN1_POWER_GATE_CONTROL_0_SRAM_RET_EN_LSB                    MK_SHIFT_CONST(1)
#define PMC_IMPL_PART_AOPG_CAN1_POWER_GATE_CONTROL_0_SRAM_RET_EN_WOFFSET                        0x0
#define PMC_IMPL_PART_AOPG_CAN1_POWER_GATE_CONTROL_0_SRAM_RET_EN_DEFAULT                        MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_CAN1_POWER_GATE_CONTROL_0_SRAM_RET_EN_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AOPG_CAN1_POWER_GATE_CONTROL_0_SRAM_RET_EN_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_CAN1_POWER_GATE_CONTROL_0_SRAM_RET_EN_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_CAN1_POWER_GATE_CONTROL_0_SRAM_RET_EN_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_CAN1_POWER_GATE_CONTROL_0_SRAM_RET_EN_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AOPG_CAN1_POWER_GATE_CONTROL_0_SRAM_RET_EN_INIT_ENUM                      OFF
#define PMC_IMPL_PART_AOPG_CAN1_POWER_GATE_CONTROL_0_SRAM_RET_EN_OFF                    MK_ENUM_CONST(0)
#define PMC_IMPL_PART_AOPG_CAN1_POWER_GATE_CONTROL_0_SRAM_RET_EN_ON                     MK_ENUM_CONST(1)

#define PMC_IMPL_PART_AOPG_CAN1_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SHIFT                  MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_AOPG_CAN1_POWER_GATE_CONTROL_0_LOGIC_SLEEP_FIELD                  MK_FIELD_CONST(0x1, PMC_IMPL_PART_AOPG_CAN1_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SHIFT)
#define PMC_IMPL_PART_AOPG_CAN1_POWER_GATE_CONTROL_0_LOGIC_SLEEP_RANGE                  0:0
#define PMC_IMPL_PART_AOPG_CAN1_POWER_GATE_CONTROL_0_LOGIC_SLEEP_MSB                    MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_AOPG_CAN1_POWER_GATE_CONTROL_0_LOGIC_SLEEP_LSB                    MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_AOPG_CAN1_POWER_GATE_CONTROL_0_LOGIC_SLEEP_WOFFSET                        0x0
#define PMC_IMPL_PART_AOPG_CAN1_POWER_GATE_CONTROL_0_LOGIC_SLEEP_DEFAULT                        MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_CAN1_POWER_GATE_CONTROL_0_LOGIC_SLEEP_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AOPG_CAN1_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_CAN1_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_CAN1_POWER_GATE_CONTROL_0_LOGIC_SLEEP_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_CAN1_POWER_GATE_CONTROL_0_LOGIC_SLEEP_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AOPG_CAN1_POWER_GATE_CONTROL_0_LOGIC_SLEEP_INIT_ENUM                      OFF
#define PMC_IMPL_PART_AOPG_CAN1_POWER_GATE_CONTROL_0_LOGIC_SLEEP_OFF                    MK_ENUM_CONST(0)
#define PMC_IMPL_PART_AOPG_CAN1_POWER_GATE_CONTROL_0_LOGIC_SLEEP_ON                     MK_ENUM_CONST(1)


// Register PMC_IMPL_PART_AOPG_CAN1_POWER_GATE_STATUS_0
#define PMC_IMPL_PART_AOPG_CAN1_POWER_GATE_STATUS_0                     MK_ADDR_CONST(0x404)
#define PMC_IMPL_PART_AOPG_CAN1_POWER_GATE_STATUS_0_SECURE                      0x0
#define PMC_IMPL_PART_AOPG_CAN1_POWER_GATE_STATUS_0_DUAL                        0x0
#define PMC_IMPL_PART_AOPG_CAN1_POWER_GATE_STATUS_0_SCR                         PG_AOPG_CAN1_SCR_0
#define PMC_IMPL_PART_AOPG_CAN1_POWER_GATE_STATUS_0_SCRREG                      PMC_IMPL_SCR_PG_AOPG_CAN1_SCR_0
#define PMC_IMPL_PART_AOPG_CAN1_POWER_GATE_STATUS_0_WORD_COUNT                  0x1
#define PMC_IMPL_PART_AOPG_CAN1_POWER_GATE_STATUS_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_CAN1_POWER_GATE_STATUS_0_RESET_MASK                  MK_MASK_CONST(0x7)
#define PMC_IMPL_PART_AOPG_CAN1_POWER_GATE_STATUS_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_CAN1_POWER_GATE_STATUS_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_CAN1_POWER_GATE_STATUS_0_READ_MASK                   MK_MASK_CONST(0x7)
#define PMC_IMPL_PART_AOPG_CAN1_POWER_GATE_STATUS_0_WRITE_MASK                  MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_CAN1_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SHIFT                        MK_SHIFT_CONST(2)
#define PMC_IMPL_PART_AOPG_CAN1_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_FIELD                        MK_FIELD_CONST(0x1, PMC_IMPL_PART_AOPG_CAN1_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SHIFT)
#define PMC_IMPL_PART_AOPG_CAN1_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_RANGE                        2:2
#define PMC_IMPL_PART_AOPG_CAN1_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_MSB                  MK_SHIFT_CONST(2)
#define PMC_IMPL_PART_AOPG_CAN1_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_LSB                  MK_SHIFT_CONST(2)
#define PMC_IMPL_PART_AOPG_CAN1_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_WOFFSET                      0x0
#define PMC_IMPL_PART_AOPG_CAN1_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_DEFAULT                      MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_CAN1_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AOPG_CAN1_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_CAN1_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_CAN1_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_CAN1_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AOPG_CAN1_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_INIT_ENUM                    OFF
#define PMC_IMPL_PART_AOPG_CAN1_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_OFF                  MK_ENUM_CONST(0)
#define PMC_IMPL_PART_AOPG_CAN1_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_ON                   MK_ENUM_CONST(1)

#define PMC_IMPL_PART_AOPG_CAN1_POWER_GATE_STATUS_0_SRAM_RET_STS_SHIFT                  MK_SHIFT_CONST(1)
#define PMC_IMPL_PART_AOPG_CAN1_POWER_GATE_STATUS_0_SRAM_RET_STS_FIELD                  MK_FIELD_CONST(0x1, PMC_IMPL_PART_AOPG_CAN1_POWER_GATE_STATUS_0_SRAM_RET_STS_SHIFT)
#define PMC_IMPL_PART_AOPG_CAN1_POWER_GATE_STATUS_0_SRAM_RET_STS_RANGE                  1:1
#define PMC_IMPL_PART_AOPG_CAN1_POWER_GATE_STATUS_0_SRAM_RET_STS_MSB                    MK_SHIFT_CONST(1)
#define PMC_IMPL_PART_AOPG_CAN1_POWER_GATE_STATUS_0_SRAM_RET_STS_LSB                    MK_SHIFT_CONST(1)
#define PMC_IMPL_PART_AOPG_CAN1_POWER_GATE_STATUS_0_SRAM_RET_STS_WOFFSET                        0x0
#define PMC_IMPL_PART_AOPG_CAN1_POWER_GATE_STATUS_0_SRAM_RET_STS_DEFAULT                        MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_CAN1_POWER_GATE_STATUS_0_SRAM_RET_STS_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AOPG_CAN1_POWER_GATE_STATUS_0_SRAM_RET_STS_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_CAN1_POWER_GATE_STATUS_0_SRAM_RET_STS_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_CAN1_POWER_GATE_STATUS_0_SRAM_RET_STS_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_CAN1_POWER_GATE_STATUS_0_SRAM_RET_STS_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AOPG_CAN1_POWER_GATE_STATUS_0_SRAM_RET_STS_INIT_ENUM                      OFF
#define PMC_IMPL_PART_AOPG_CAN1_POWER_GATE_STATUS_0_SRAM_RET_STS_OFF                    MK_ENUM_CONST(0)
#define PMC_IMPL_PART_AOPG_CAN1_POWER_GATE_STATUS_0_SRAM_RET_STS_ON                     MK_ENUM_CONST(1)

#define PMC_IMPL_PART_AOPG_CAN1_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SHIFT                       MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_AOPG_CAN1_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_FIELD                       MK_FIELD_CONST(0x1, PMC_IMPL_PART_AOPG_CAN1_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SHIFT)
#define PMC_IMPL_PART_AOPG_CAN1_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_RANGE                       0:0
#define PMC_IMPL_PART_AOPG_CAN1_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_MSB                 MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_AOPG_CAN1_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_LSB                 MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_AOPG_CAN1_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_WOFFSET                     0x0
#define PMC_IMPL_PART_AOPG_CAN1_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_DEFAULT                     MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_CAN1_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AOPG_CAN1_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_CAN1_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_CAN1_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_CAN1_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AOPG_CAN1_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_INIT_ENUM                   OFF
#define PMC_IMPL_PART_AOPG_CAN1_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_OFF                 MK_ENUM_CONST(0)
#define PMC_IMPL_PART_AOPG_CAN1_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_ON                  MK_ENUM_CONST(1)


// Register PMC_IMPL_PART_AOPG_CAN1_CLAMP_CONTROL_0
#define PMC_IMPL_PART_AOPG_CAN1_CLAMP_CONTROL_0                 MK_ADDR_CONST(0x408)
#define PMC_IMPL_PART_AOPG_CAN1_CLAMP_CONTROL_0_SECURE                  0x0
#define PMC_IMPL_PART_AOPG_CAN1_CLAMP_CONTROL_0_DUAL                    0x0
#define PMC_IMPL_PART_AOPG_CAN1_CLAMP_CONTROL_0_SCR                     PG_AOPG_CAN1_SCR_0
#define PMC_IMPL_PART_AOPG_CAN1_CLAMP_CONTROL_0_SCRREG                  PMC_IMPL_SCR_PG_AOPG_CAN1_SCR_0
#define PMC_IMPL_PART_AOPG_CAN1_CLAMP_CONTROL_0_WORD_COUNT                      0x1
#define PMC_IMPL_PART_AOPG_CAN1_CLAMP_CONTROL_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_CAN1_CLAMP_CONTROL_0_RESET_MASK                      MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AOPG_CAN1_CLAMP_CONTROL_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_CAN1_CLAMP_CONTROL_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_CAN1_CLAMP_CONTROL_0_READ_MASK                       MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AOPG_CAN1_CLAMP_CONTROL_0_WRITE_MASK                      MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_CAN1_CLAMP_CONTROL_0_CLAMP_SHIFT                     MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_AOPG_CAN1_CLAMP_CONTROL_0_CLAMP_FIELD                     MK_FIELD_CONST(0x1, PMC_IMPL_PART_AOPG_CAN1_CLAMP_CONTROL_0_CLAMP_SHIFT)
#define PMC_IMPL_PART_AOPG_CAN1_CLAMP_CONTROL_0_CLAMP_RANGE                     0:0
#define PMC_IMPL_PART_AOPG_CAN1_CLAMP_CONTROL_0_CLAMP_MSB                       MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_AOPG_CAN1_CLAMP_CONTROL_0_CLAMP_LSB                       MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_AOPG_CAN1_CLAMP_CONTROL_0_CLAMP_WOFFSET                   0x0
#define PMC_IMPL_PART_AOPG_CAN1_CLAMP_CONTROL_0_CLAMP_DEFAULT                   MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_CAN1_CLAMP_CONTROL_0_CLAMP_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AOPG_CAN1_CLAMP_CONTROL_0_CLAMP_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_CAN1_CLAMP_CONTROL_0_CLAMP_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_CAN1_CLAMP_CONTROL_0_CLAMP_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_CAN1_CLAMP_CONTROL_0_CLAMP_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AOPG_CAN1_CLAMP_CONTROL_0_CLAMP_INIT_ENUM                 OFF
#define PMC_IMPL_PART_AOPG_CAN1_CLAMP_CONTROL_0_CLAMP_OFF                       MK_ENUM_CONST(0)
#define PMC_IMPL_PART_AOPG_CAN1_CLAMP_CONTROL_0_CLAMP_ON                        MK_ENUM_CONST(1)


// Reserved address 0x40c

// Reserved address 0x410

// Reserved address 0x414

// Reserved address 0x418

// Reserved address 0x41c

// Reserved address 0x420

// Register PMC_IMPL_PART_PCIEX8A_POWER_GATE_CONTROL_0
#define PMC_IMPL_PART_PCIEX8A_POWER_GATE_CONTROL_0                      MK_ADDR_CONST(0x424)
#define PMC_IMPL_PART_PCIEX8A_POWER_GATE_CONTROL_0_SECURE                       0x0
#define PMC_IMPL_PART_PCIEX8A_POWER_GATE_CONTROL_0_DUAL                         0x0
#define PMC_IMPL_PART_PCIEX8A_POWER_GATE_CONTROL_0_SCR                  PG_PCIEX8A_SCR_0
#define PMC_IMPL_PART_PCIEX8A_POWER_GATE_CONTROL_0_SCRREG                       PMC_IMPL_SCR_PG_PCIEX8A_SCR_0
#define PMC_IMPL_PART_PCIEX8A_POWER_GATE_CONTROL_0_WORD_COUNT                   0x1
#define PMC_IMPL_PART_PCIEX8A_POWER_GATE_CONTROL_0_RESET_VAL                    MK_MASK_CONST(0x80000005)
#define PMC_IMPL_PART_PCIEX8A_POWER_GATE_CONTROL_0_RESET_MASK                   MK_MASK_CONST(0x80000107)
#define PMC_IMPL_PART_PCIEX8A_POWER_GATE_CONTROL_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX8A_POWER_GATE_CONTROL_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX8A_POWER_GATE_CONTROL_0_READ_MASK                    MK_MASK_CONST(0x80000107)
#define PMC_IMPL_PART_PCIEX8A_POWER_GATE_CONTROL_0_WRITE_MASK                   MK_MASK_CONST(0x80000105)
#define PMC_IMPL_PART_PCIEX8A_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SHIFT                    MK_SHIFT_CONST(31)
#define PMC_IMPL_PART_PCIEX8A_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_FIELD                    MK_FIELD_CONST(0x1, PMC_IMPL_PART_PCIEX8A_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SHIFT)
#define PMC_IMPL_PART_PCIEX8A_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_RANGE                    31:31
#define PMC_IMPL_PART_PCIEX8A_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_MSB                      MK_SHIFT_CONST(31)
#define PMC_IMPL_PART_PCIEX8A_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_LSB                      MK_SHIFT_CONST(31)
#define PMC_IMPL_PART_PCIEX8A_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_WOFFSET                  0x0
#define PMC_IMPL_PART_PCIEX8A_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_DEFAULT                  MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PCIEX8A_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PCIEX8A_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX8A_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX8A_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX8A_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PCIEX8A_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_INIT_ENUM                        ENABLE
#define PMC_IMPL_PART_PCIEX8A_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_DISABLE                  MK_ENUM_CONST(0)
#define PMC_IMPL_PART_PCIEX8A_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_ENABLE                   MK_ENUM_CONST(1)

#define PMC_IMPL_PART_PCIEX8A_POWER_GATE_CONTROL_0_START_SHIFT                  MK_SHIFT_CONST(8)
#define PMC_IMPL_PART_PCIEX8A_POWER_GATE_CONTROL_0_START_FIELD                  MK_FIELD_CONST(0x1, PMC_IMPL_PART_PCIEX8A_POWER_GATE_CONTROL_0_START_SHIFT)
#define PMC_IMPL_PART_PCIEX8A_POWER_GATE_CONTROL_0_START_RANGE                  8:8
#define PMC_IMPL_PART_PCIEX8A_POWER_GATE_CONTROL_0_START_MSB                    MK_SHIFT_CONST(8)
#define PMC_IMPL_PART_PCIEX8A_POWER_GATE_CONTROL_0_START_LSB                    MK_SHIFT_CONST(8)
#define PMC_IMPL_PART_PCIEX8A_POWER_GATE_CONTROL_0_START_WOFFSET                        0x0
#define PMC_IMPL_PART_PCIEX8A_POWER_GATE_CONTROL_0_START_DEFAULT                        MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX8A_POWER_GATE_CONTROL_0_START_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PCIEX8A_POWER_GATE_CONTROL_0_START_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX8A_POWER_GATE_CONTROL_0_START_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX8A_POWER_GATE_CONTROL_0_START_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX8A_POWER_GATE_CONTROL_0_START_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PCIEX8A_POWER_GATE_CONTROL_0_START_INIT_ENUM                      DONE
#define PMC_IMPL_PART_PCIEX8A_POWER_GATE_CONTROL_0_START_DONE                   MK_ENUM_CONST(0)
#define PMC_IMPL_PART_PCIEX8A_POWER_GATE_CONTROL_0_START_PENDING                        MK_ENUM_CONST(1)

#define PMC_IMPL_PART_PCIEX8A_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SHIFT                  MK_SHIFT_CONST(2)
#define PMC_IMPL_PART_PCIEX8A_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_FIELD                  MK_FIELD_CONST(0x1, PMC_IMPL_PART_PCIEX8A_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SHIFT)
#define PMC_IMPL_PART_PCIEX8A_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_RANGE                  2:2
#define PMC_IMPL_PART_PCIEX8A_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_MSB                    MK_SHIFT_CONST(2)
#define PMC_IMPL_PART_PCIEX8A_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_LSB                    MK_SHIFT_CONST(2)
#define PMC_IMPL_PART_PCIEX8A_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_WOFFSET                        0x0
#define PMC_IMPL_PART_PCIEX8A_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_DEFAULT                        MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PCIEX8A_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PCIEX8A_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX8A_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX8A_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX8A_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PCIEX8A_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_INIT_ENUM                      ON
#define PMC_IMPL_PART_PCIEX8A_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_OFF                    MK_ENUM_CONST(0)
#define PMC_IMPL_PART_PCIEX8A_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_ON                     MK_ENUM_CONST(1)

#define PMC_IMPL_PART_PCIEX8A_POWER_GATE_CONTROL_0_SRAM_RET_EN_SHIFT                    MK_SHIFT_CONST(1)
#define PMC_IMPL_PART_PCIEX8A_POWER_GATE_CONTROL_0_SRAM_RET_EN_FIELD                    MK_FIELD_CONST(0x1, PMC_IMPL_PART_PCIEX8A_POWER_GATE_CONTROL_0_SRAM_RET_EN_SHIFT)
#define PMC_IMPL_PART_PCIEX8A_POWER_GATE_CONTROL_0_SRAM_RET_EN_RANGE                    1:1
#define PMC_IMPL_PART_PCIEX8A_POWER_GATE_CONTROL_0_SRAM_RET_EN_MSB                      MK_SHIFT_CONST(1)
#define PMC_IMPL_PART_PCIEX8A_POWER_GATE_CONTROL_0_SRAM_RET_EN_LSB                      MK_SHIFT_CONST(1)
#define PMC_IMPL_PART_PCIEX8A_POWER_GATE_CONTROL_0_SRAM_RET_EN_WOFFSET                  0x0
#define PMC_IMPL_PART_PCIEX8A_POWER_GATE_CONTROL_0_SRAM_RET_EN_DEFAULT                  MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX8A_POWER_GATE_CONTROL_0_SRAM_RET_EN_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PCIEX8A_POWER_GATE_CONTROL_0_SRAM_RET_EN_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX8A_POWER_GATE_CONTROL_0_SRAM_RET_EN_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX8A_POWER_GATE_CONTROL_0_SRAM_RET_EN_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX8A_POWER_GATE_CONTROL_0_SRAM_RET_EN_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PCIEX8A_POWER_GATE_CONTROL_0_SRAM_RET_EN_INIT_ENUM                        OFF
#define PMC_IMPL_PART_PCIEX8A_POWER_GATE_CONTROL_0_SRAM_RET_EN_OFF                      MK_ENUM_CONST(0)
#define PMC_IMPL_PART_PCIEX8A_POWER_GATE_CONTROL_0_SRAM_RET_EN_ON                       MK_ENUM_CONST(1)

#define PMC_IMPL_PART_PCIEX8A_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SHIFT                    MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_PCIEX8A_POWER_GATE_CONTROL_0_LOGIC_SLEEP_FIELD                    MK_FIELD_CONST(0x1, PMC_IMPL_PART_PCIEX8A_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SHIFT)
#define PMC_IMPL_PART_PCIEX8A_POWER_GATE_CONTROL_0_LOGIC_SLEEP_RANGE                    0:0
#define PMC_IMPL_PART_PCIEX8A_POWER_GATE_CONTROL_0_LOGIC_SLEEP_MSB                      MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_PCIEX8A_POWER_GATE_CONTROL_0_LOGIC_SLEEP_LSB                      MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_PCIEX8A_POWER_GATE_CONTROL_0_LOGIC_SLEEP_WOFFSET                  0x0
#define PMC_IMPL_PART_PCIEX8A_POWER_GATE_CONTROL_0_LOGIC_SLEEP_DEFAULT                  MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PCIEX8A_POWER_GATE_CONTROL_0_LOGIC_SLEEP_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PCIEX8A_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX8A_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX8A_POWER_GATE_CONTROL_0_LOGIC_SLEEP_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX8A_POWER_GATE_CONTROL_0_LOGIC_SLEEP_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PCIEX8A_POWER_GATE_CONTROL_0_LOGIC_SLEEP_INIT_ENUM                        ON
#define PMC_IMPL_PART_PCIEX8A_POWER_GATE_CONTROL_0_LOGIC_SLEEP_OFF                      MK_ENUM_CONST(0)
#define PMC_IMPL_PART_PCIEX8A_POWER_GATE_CONTROL_0_LOGIC_SLEEP_ON                       MK_ENUM_CONST(1)


// Register PMC_IMPL_PART_PCIEX8A_POWER_GATE_STATUS_0
#define PMC_IMPL_PART_PCIEX8A_POWER_GATE_STATUS_0                       MK_ADDR_CONST(0x428)
#define PMC_IMPL_PART_PCIEX8A_POWER_GATE_STATUS_0_SECURE                        0x0
#define PMC_IMPL_PART_PCIEX8A_POWER_GATE_STATUS_0_DUAL                  0x0
#define PMC_IMPL_PART_PCIEX8A_POWER_GATE_STATUS_0_SCR                   PG_PCIEX8A_SCR_0
#define PMC_IMPL_PART_PCIEX8A_POWER_GATE_STATUS_0_SCRREG                        PMC_IMPL_SCR_PG_PCIEX8A_SCR_0
#define PMC_IMPL_PART_PCIEX8A_POWER_GATE_STATUS_0_WORD_COUNT                    0x1
#define PMC_IMPL_PART_PCIEX8A_POWER_GATE_STATUS_0_RESET_VAL                     MK_MASK_CONST(0x5)
#define PMC_IMPL_PART_PCIEX8A_POWER_GATE_STATUS_0_RESET_MASK                    MK_MASK_CONST(0x7)
#define PMC_IMPL_PART_PCIEX8A_POWER_GATE_STATUS_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX8A_POWER_GATE_STATUS_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX8A_POWER_GATE_STATUS_0_READ_MASK                     MK_MASK_CONST(0x7)
#define PMC_IMPL_PART_PCIEX8A_POWER_GATE_STATUS_0_WRITE_MASK                    MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX8A_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SHIFT                  MK_SHIFT_CONST(2)
#define PMC_IMPL_PART_PCIEX8A_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_FIELD                  MK_FIELD_CONST(0x1, PMC_IMPL_PART_PCIEX8A_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SHIFT)
#define PMC_IMPL_PART_PCIEX8A_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_RANGE                  2:2
#define PMC_IMPL_PART_PCIEX8A_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_MSB                    MK_SHIFT_CONST(2)
#define PMC_IMPL_PART_PCIEX8A_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_LSB                    MK_SHIFT_CONST(2)
#define PMC_IMPL_PART_PCIEX8A_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_WOFFSET                        0x0
#define PMC_IMPL_PART_PCIEX8A_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_DEFAULT                        MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PCIEX8A_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PCIEX8A_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX8A_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX8A_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX8A_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PCIEX8A_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_INIT_ENUM                      ON
#define PMC_IMPL_PART_PCIEX8A_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_OFF                    MK_ENUM_CONST(0)
#define PMC_IMPL_PART_PCIEX8A_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_ON                     MK_ENUM_CONST(1)

#define PMC_IMPL_PART_PCIEX8A_POWER_GATE_STATUS_0_SRAM_RET_STS_SHIFT                    MK_SHIFT_CONST(1)
#define PMC_IMPL_PART_PCIEX8A_POWER_GATE_STATUS_0_SRAM_RET_STS_FIELD                    MK_FIELD_CONST(0x1, PMC_IMPL_PART_PCIEX8A_POWER_GATE_STATUS_0_SRAM_RET_STS_SHIFT)
#define PMC_IMPL_PART_PCIEX8A_POWER_GATE_STATUS_0_SRAM_RET_STS_RANGE                    1:1
#define PMC_IMPL_PART_PCIEX8A_POWER_GATE_STATUS_0_SRAM_RET_STS_MSB                      MK_SHIFT_CONST(1)
#define PMC_IMPL_PART_PCIEX8A_POWER_GATE_STATUS_0_SRAM_RET_STS_LSB                      MK_SHIFT_CONST(1)
#define PMC_IMPL_PART_PCIEX8A_POWER_GATE_STATUS_0_SRAM_RET_STS_WOFFSET                  0x0
#define PMC_IMPL_PART_PCIEX8A_POWER_GATE_STATUS_0_SRAM_RET_STS_DEFAULT                  MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX8A_POWER_GATE_STATUS_0_SRAM_RET_STS_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PCIEX8A_POWER_GATE_STATUS_0_SRAM_RET_STS_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX8A_POWER_GATE_STATUS_0_SRAM_RET_STS_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX8A_POWER_GATE_STATUS_0_SRAM_RET_STS_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX8A_POWER_GATE_STATUS_0_SRAM_RET_STS_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PCIEX8A_POWER_GATE_STATUS_0_SRAM_RET_STS_INIT_ENUM                        OFF
#define PMC_IMPL_PART_PCIEX8A_POWER_GATE_STATUS_0_SRAM_RET_STS_OFF                      MK_ENUM_CONST(0)
#define PMC_IMPL_PART_PCIEX8A_POWER_GATE_STATUS_0_SRAM_RET_STS_ON                       MK_ENUM_CONST(1)

#define PMC_IMPL_PART_PCIEX8A_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SHIFT                 MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_PCIEX8A_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_FIELD                 MK_FIELD_CONST(0x1, PMC_IMPL_PART_PCIEX8A_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SHIFT)
#define PMC_IMPL_PART_PCIEX8A_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_RANGE                 0:0
#define PMC_IMPL_PART_PCIEX8A_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_MSB                   MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_PCIEX8A_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_LSB                   MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_PCIEX8A_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_WOFFSET                       0x0
#define PMC_IMPL_PART_PCIEX8A_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_DEFAULT                       MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PCIEX8A_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PCIEX8A_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX8A_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX8A_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX8A_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PCIEX8A_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_INIT_ENUM                     ON
#define PMC_IMPL_PART_PCIEX8A_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_OFF                   MK_ENUM_CONST(0)
#define PMC_IMPL_PART_PCIEX8A_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_ON                    MK_ENUM_CONST(1)


// Register PMC_IMPL_PART_PCIEX8A_CLAMP_CONTROL_0
#define PMC_IMPL_PART_PCIEX8A_CLAMP_CONTROL_0                   MK_ADDR_CONST(0x42c)
#define PMC_IMPL_PART_PCIEX8A_CLAMP_CONTROL_0_SECURE                    0x0
#define PMC_IMPL_PART_PCIEX8A_CLAMP_CONTROL_0_DUAL                      0x0
#define PMC_IMPL_PART_PCIEX8A_CLAMP_CONTROL_0_SCR                       PG_PCIEX8A_SCR_0
#define PMC_IMPL_PART_PCIEX8A_CLAMP_CONTROL_0_SCRREG                    PMC_IMPL_SCR_PG_PCIEX8A_SCR_0
#define PMC_IMPL_PART_PCIEX8A_CLAMP_CONTROL_0_WORD_COUNT                        0x1
#define PMC_IMPL_PART_PCIEX8A_CLAMP_CONTROL_0_RESET_VAL                         MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PCIEX8A_CLAMP_CONTROL_0_RESET_MASK                        MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PCIEX8A_CLAMP_CONTROL_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX8A_CLAMP_CONTROL_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX8A_CLAMP_CONTROL_0_READ_MASK                         MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PCIEX8A_CLAMP_CONTROL_0_WRITE_MASK                        MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PCIEX8A_CLAMP_CONTROL_0_CLAMP_SHIFT                       MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_PCIEX8A_CLAMP_CONTROL_0_CLAMP_FIELD                       MK_FIELD_CONST(0x1, PMC_IMPL_PART_PCIEX8A_CLAMP_CONTROL_0_CLAMP_SHIFT)
#define PMC_IMPL_PART_PCIEX8A_CLAMP_CONTROL_0_CLAMP_RANGE                       0:0
#define PMC_IMPL_PART_PCIEX8A_CLAMP_CONTROL_0_CLAMP_MSB                 MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_PCIEX8A_CLAMP_CONTROL_0_CLAMP_LSB                 MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_PCIEX8A_CLAMP_CONTROL_0_CLAMP_WOFFSET                     0x0
#define PMC_IMPL_PART_PCIEX8A_CLAMP_CONTROL_0_CLAMP_DEFAULT                     MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PCIEX8A_CLAMP_CONTROL_0_CLAMP_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PCIEX8A_CLAMP_CONTROL_0_CLAMP_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX8A_CLAMP_CONTROL_0_CLAMP_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX8A_CLAMP_CONTROL_0_CLAMP_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX8A_CLAMP_CONTROL_0_CLAMP_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PCIEX8A_CLAMP_CONTROL_0_CLAMP_INIT_ENUM                   ON
#define PMC_IMPL_PART_PCIEX8A_CLAMP_CONTROL_0_CLAMP_OFF                 MK_ENUM_CONST(0)
#define PMC_IMPL_PART_PCIEX8A_CLAMP_CONTROL_0_CLAMP_ON                  MK_ENUM_CONST(1)


// Register PMC_IMPL_PART_PCIEX4A_POWER_GATE_CONTROL_0
#define PMC_IMPL_PART_PCIEX4A_POWER_GATE_CONTROL_0                      MK_ADDR_CONST(0x430)
#define PMC_IMPL_PART_PCIEX4A_POWER_GATE_CONTROL_0_SECURE                       0x0
#define PMC_IMPL_PART_PCIEX4A_POWER_GATE_CONTROL_0_DUAL                         0x0
#define PMC_IMPL_PART_PCIEX4A_POWER_GATE_CONTROL_0_SCR                  PG_PCIEX4A_SCR_0
#define PMC_IMPL_PART_PCIEX4A_POWER_GATE_CONTROL_0_SCRREG                       PMC_IMPL_SCR_PG_PCIEX4A_SCR_0
#define PMC_IMPL_PART_PCIEX4A_POWER_GATE_CONTROL_0_WORD_COUNT                   0x1
#define PMC_IMPL_PART_PCIEX4A_POWER_GATE_CONTROL_0_RESET_VAL                    MK_MASK_CONST(0x80000005)
#define PMC_IMPL_PART_PCIEX4A_POWER_GATE_CONTROL_0_RESET_MASK                   MK_MASK_CONST(0x80000107)
#define PMC_IMPL_PART_PCIEX4A_POWER_GATE_CONTROL_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX4A_POWER_GATE_CONTROL_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX4A_POWER_GATE_CONTROL_0_READ_MASK                    MK_MASK_CONST(0x80000107)
#define PMC_IMPL_PART_PCIEX4A_POWER_GATE_CONTROL_0_WRITE_MASK                   MK_MASK_CONST(0x80000105)
#define PMC_IMPL_PART_PCIEX4A_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SHIFT                    MK_SHIFT_CONST(31)
#define PMC_IMPL_PART_PCIEX4A_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_FIELD                    MK_FIELD_CONST(0x1, PMC_IMPL_PART_PCIEX4A_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SHIFT)
#define PMC_IMPL_PART_PCIEX4A_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_RANGE                    31:31
#define PMC_IMPL_PART_PCIEX4A_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_MSB                      MK_SHIFT_CONST(31)
#define PMC_IMPL_PART_PCIEX4A_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_LSB                      MK_SHIFT_CONST(31)
#define PMC_IMPL_PART_PCIEX4A_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_WOFFSET                  0x0
#define PMC_IMPL_PART_PCIEX4A_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_DEFAULT                  MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PCIEX4A_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PCIEX4A_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX4A_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX4A_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX4A_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PCIEX4A_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_INIT_ENUM                        ENABLE
#define PMC_IMPL_PART_PCIEX4A_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_DISABLE                  MK_ENUM_CONST(0)
#define PMC_IMPL_PART_PCIEX4A_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_ENABLE                   MK_ENUM_CONST(1)

#define PMC_IMPL_PART_PCIEX4A_POWER_GATE_CONTROL_0_START_SHIFT                  MK_SHIFT_CONST(8)
#define PMC_IMPL_PART_PCIEX4A_POWER_GATE_CONTROL_0_START_FIELD                  MK_FIELD_CONST(0x1, PMC_IMPL_PART_PCIEX4A_POWER_GATE_CONTROL_0_START_SHIFT)
#define PMC_IMPL_PART_PCIEX4A_POWER_GATE_CONTROL_0_START_RANGE                  8:8
#define PMC_IMPL_PART_PCIEX4A_POWER_GATE_CONTROL_0_START_MSB                    MK_SHIFT_CONST(8)
#define PMC_IMPL_PART_PCIEX4A_POWER_GATE_CONTROL_0_START_LSB                    MK_SHIFT_CONST(8)
#define PMC_IMPL_PART_PCIEX4A_POWER_GATE_CONTROL_0_START_WOFFSET                        0x0
#define PMC_IMPL_PART_PCIEX4A_POWER_GATE_CONTROL_0_START_DEFAULT                        MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX4A_POWER_GATE_CONTROL_0_START_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PCIEX4A_POWER_GATE_CONTROL_0_START_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX4A_POWER_GATE_CONTROL_0_START_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX4A_POWER_GATE_CONTROL_0_START_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX4A_POWER_GATE_CONTROL_0_START_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PCIEX4A_POWER_GATE_CONTROL_0_START_INIT_ENUM                      DONE
#define PMC_IMPL_PART_PCIEX4A_POWER_GATE_CONTROL_0_START_DONE                   MK_ENUM_CONST(0)
#define PMC_IMPL_PART_PCIEX4A_POWER_GATE_CONTROL_0_START_PENDING                        MK_ENUM_CONST(1)

#define PMC_IMPL_PART_PCIEX4A_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SHIFT                  MK_SHIFT_CONST(2)
#define PMC_IMPL_PART_PCIEX4A_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_FIELD                  MK_FIELD_CONST(0x1, PMC_IMPL_PART_PCIEX4A_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SHIFT)
#define PMC_IMPL_PART_PCIEX4A_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_RANGE                  2:2
#define PMC_IMPL_PART_PCIEX4A_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_MSB                    MK_SHIFT_CONST(2)
#define PMC_IMPL_PART_PCIEX4A_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_LSB                    MK_SHIFT_CONST(2)
#define PMC_IMPL_PART_PCIEX4A_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_WOFFSET                        0x0
#define PMC_IMPL_PART_PCIEX4A_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_DEFAULT                        MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PCIEX4A_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PCIEX4A_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX4A_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX4A_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX4A_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PCIEX4A_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_INIT_ENUM                      ON
#define PMC_IMPL_PART_PCIEX4A_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_OFF                    MK_ENUM_CONST(0)
#define PMC_IMPL_PART_PCIEX4A_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_ON                     MK_ENUM_CONST(1)

#define PMC_IMPL_PART_PCIEX4A_POWER_GATE_CONTROL_0_SRAM_RET_EN_SHIFT                    MK_SHIFT_CONST(1)
#define PMC_IMPL_PART_PCIEX4A_POWER_GATE_CONTROL_0_SRAM_RET_EN_FIELD                    MK_FIELD_CONST(0x1, PMC_IMPL_PART_PCIEX4A_POWER_GATE_CONTROL_0_SRAM_RET_EN_SHIFT)
#define PMC_IMPL_PART_PCIEX4A_POWER_GATE_CONTROL_0_SRAM_RET_EN_RANGE                    1:1
#define PMC_IMPL_PART_PCIEX4A_POWER_GATE_CONTROL_0_SRAM_RET_EN_MSB                      MK_SHIFT_CONST(1)
#define PMC_IMPL_PART_PCIEX4A_POWER_GATE_CONTROL_0_SRAM_RET_EN_LSB                      MK_SHIFT_CONST(1)
#define PMC_IMPL_PART_PCIEX4A_POWER_GATE_CONTROL_0_SRAM_RET_EN_WOFFSET                  0x0
#define PMC_IMPL_PART_PCIEX4A_POWER_GATE_CONTROL_0_SRAM_RET_EN_DEFAULT                  MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX4A_POWER_GATE_CONTROL_0_SRAM_RET_EN_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PCIEX4A_POWER_GATE_CONTROL_0_SRAM_RET_EN_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX4A_POWER_GATE_CONTROL_0_SRAM_RET_EN_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX4A_POWER_GATE_CONTROL_0_SRAM_RET_EN_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX4A_POWER_GATE_CONTROL_0_SRAM_RET_EN_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PCIEX4A_POWER_GATE_CONTROL_0_SRAM_RET_EN_INIT_ENUM                        OFF
#define PMC_IMPL_PART_PCIEX4A_POWER_GATE_CONTROL_0_SRAM_RET_EN_OFF                      MK_ENUM_CONST(0)
#define PMC_IMPL_PART_PCIEX4A_POWER_GATE_CONTROL_0_SRAM_RET_EN_ON                       MK_ENUM_CONST(1)

#define PMC_IMPL_PART_PCIEX4A_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SHIFT                    MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_PCIEX4A_POWER_GATE_CONTROL_0_LOGIC_SLEEP_FIELD                    MK_FIELD_CONST(0x1, PMC_IMPL_PART_PCIEX4A_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SHIFT)
#define PMC_IMPL_PART_PCIEX4A_POWER_GATE_CONTROL_0_LOGIC_SLEEP_RANGE                    0:0
#define PMC_IMPL_PART_PCIEX4A_POWER_GATE_CONTROL_0_LOGIC_SLEEP_MSB                      MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_PCIEX4A_POWER_GATE_CONTROL_0_LOGIC_SLEEP_LSB                      MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_PCIEX4A_POWER_GATE_CONTROL_0_LOGIC_SLEEP_WOFFSET                  0x0
#define PMC_IMPL_PART_PCIEX4A_POWER_GATE_CONTROL_0_LOGIC_SLEEP_DEFAULT                  MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PCIEX4A_POWER_GATE_CONTROL_0_LOGIC_SLEEP_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PCIEX4A_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX4A_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX4A_POWER_GATE_CONTROL_0_LOGIC_SLEEP_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX4A_POWER_GATE_CONTROL_0_LOGIC_SLEEP_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PCIEX4A_POWER_GATE_CONTROL_0_LOGIC_SLEEP_INIT_ENUM                        ON
#define PMC_IMPL_PART_PCIEX4A_POWER_GATE_CONTROL_0_LOGIC_SLEEP_OFF                      MK_ENUM_CONST(0)
#define PMC_IMPL_PART_PCIEX4A_POWER_GATE_CONTROL_0_LOGIC_SLEEP_ON                       MK_ENUM_CONST(1)


// Register PMC_IMPL_PART_PCIEX4A_POWER_GATE_STATUS_0
#define PMC_IMPL_PART_PCIEX4A_POWER_GATE_STATUS_0                       MK_ADDR_CONST(0x434)
#define PMC_IMPL_PART_PCIEX4A_POWER_GATE_STATUS_0_SECURE                        0x0
#define PMC_IMPL_PART_PCIEX4A_POWER_GATE_STATUS_0_DUAL                  0x0
#define PMC_IMPL_PART_PCIEX4A_POWER_GATE_STATUS_0_SCR                   PG_PCIEX4A_SCR_0
#define PMC_IMPL_PART_PCIEX4A_POWER_GATE_STATUS_0_SCRREG                        PMC_IMPL_SCR_PG_PCIEX4A_SCR_0
#define PMC_IMPL_PART_PCIEX4A_POWER_GATE_STATUS_0_WORD_COUNT                    0x1
#define PMC_IMPL_PART_PCIEX4A_POWER_GATE_STATUS_0_RESET_VAL                     MK_MASK_CONST(0x5)
#define PMC_IMPL_PART_PCIEX4A_POWER_GATE_STATUS_0_RESET_MASK                    MK_MASK_CONST(0x7)
#define PMC_IMPL_PART_PCIEX4A_POWER_GATE_STATUS_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX4A_POWER_GATE_STATUS_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX4A_POWER_GATE_STATUS_0_READ_MASK                     MK_MASK_CONST(0x7)
#define PMC_IMPL_PART_PCIEX4A_POWER_GATE_STATUS_0_WRITE_MASK                    MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX4A_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SHIFT                  MK_SHIFT_CONST(2)
#define PMC_IMPL_PART_PCIEX4A_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_FIELD                  MK_FIELD_CONST(0x1, PMC_IMPL_PART_PCIEX4A_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SHIFT)
#define PMC_IMPL_PART_PCIEX4A_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_RANGE                  2:2
#define PMC_IMPL_PART_PCIEX4A_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_MSB                    MK_SHIFT_CONST(2)
#define PMC_IMPL_PART_PCIEX4A_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_LSB                    MK_SHIFT_CONST(2)
#define PMC_IMPL_PART_PCIEX4A_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_WOFFSET                        0x0
#define PMC_IMPL_PART_PCIEX4A_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_DEFAULT                        MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PCIEX4A_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PCIEX4A_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX4A_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX4A_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX4A_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PCIEX4A_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_INIT_ENUM                      ON
#define PMC_IMPL_PART_PCIEX4A_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_OFF                    MK_ENUM_CONST(0)
#define PMC_IMPL_PART_PCIEX4A_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_ON                     MK_ENUM_CONST(1)

#define PMC_IMPL_PART_PCIEX4A_POWER_GATE_STATUS_0_SRAM_RET_STS_SHIFT                    MK_SHIFT_CONST(1)
#define PMC_IMPL_PART_PCIEX4A_POWER_GATE_STATUS_0_SRAM_RET_STS_FIELD                    MK_FIELD_CONST(0x1, PMC_IMPL_PART_PCIEX4A_POWER_GATE_STATUS_0_SRAM_RET_STS_SHIFT)
#define PMC_IMPL_PART_PCIEX4A_POWER_GATE_STATUS_0_SRAM_RET_STS_RANGE                    1:1
#define PMC_IMPL_PART_PCIEX4A_POWER_GATE_STATUS_0_SRAM_RET_STS_MSB                      MK_SHIFT_CONST(1)
#define PMC_IMPL_PART_PCIEX4A_POWER_GATE_STATUS_0_SRAM_RET_STS_LSB                      MK_SHIFT_CONST(1)
#define PMC_IMPL_PART_PCIEX4A_POWER_GATE_STATUS_0_SRAM_RET_STS_WOFFSET                  0x0
#define PMC_IMPL_PART_PCIEX4A_POWER_GATE_STATUS_0_SRAM_RET_STS_DEFAULT                  MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX4A_POWER_GATE_STATUS_0_SRAM_RET_STS_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PCIEX4A_POWER_GATE_STATUS_0_SRAM_RET_STS_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX4A_POWER_GATE_STATUS_0_SRAM_RET_STS_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX4A_POWER_GATE_STATUS_0_SRAM_RET_STS_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX4A_POWER_GATE_STATUS_0_SRAM_RET_STS_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PCIEX4A_POWER_GATE_STATUS_0_SRAM_RET_STS_INIT_ENUM                        OFF
#define PMC_IMPL_PART_PCIEX4A_POWER_GATE_STATUS_0_SRAM_RET_STS_OFF                      MK_ENUM_CONST(0)
#define PMC_IMPL_PART_PCIEX4A_POWER_GATE_STATUS_0_SRAM_RET_STS_ON                       MK_ENUM_CONST(1)

#define PMC_IMPL_PART_PCIEX4A_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SHIFT                 MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_PCIEX4A_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_FIELD                 MK_FIELD_CONST(0x1, PMC_IMPL_PART_PCIEX4A_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SHIFT)
#define PMC_IMPL_PART_PCIEX4A_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_RANGE                 0:0
#define PMC_IMPL_PART_PCIEX4A_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_MSB                   MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_PCIEX4A_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_LSB                   MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_PCIEX4A_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_WOFFSET                       0x0
#define PMC_IMPL_PART_PCIEX4A_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_DEFAULT                       MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PCIEX4A_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PCIEX4A_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX4A_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX4A_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX4A_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PCIEX4A_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_INIT_ENUM                     ON
#define PMC_IMPL_PART_PCIEX4A_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_OFF                   MK_ENUM_CONST(0)
#define PMC_IMPL_PART_PCIEX4A_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_ON                    MK_ENUM_CONST(1)


// Register PMC_IMPL_PART_PCIEX4A_CLAMP_CONTROL_0
#define PMC_IMPL_PART_PCIEX4A_CLAMP_CONTROL_0                   MK_ADDR_CONST(0x438)
#define PMC_IMPL_PART_PCIEX4A_CLAMP_CONTROL_0_SECURE                    0x0
#define PMC_IMPL_PART_PCIEX4A_CLAMP_CONTROL_0_DUAL                      0x0
#define PMC_IMPL_PART_PCIEX4A_CLAMP_CONTROL_0_SCR                       PG_PCIEX4A_SCR_0
#define PMC_IMPL_PART_PCIEX4A_CLAMP_CONTROL_0_SCRREG                    PMC_IMPL_SCR_PG_PCIEX4A_SCR_0
#define PMC_IMPL_PART_PCIEX4A_CLAMP_CONTROL_0_WORD_COUNT                        0x1
#define PMC_IMPL_PART_PCIEX4A_CLAMP_CONTROL_0_RESET_VAL                         MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PCIEX4A_CLAMP_CONTROL_0_RESET_MASK                        MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PCIEX4A_CLAMP_CONTROL_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX4A_CLAMP_CONTROL_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX4A_CLAMP_CONTROL_0_READ_MASK                         MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PCIEX4A_CLAMP_CONTROL_0_WRITE_MASK                        MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PCIEX4A_CLAMP_CONTROL_0_CLAMP_SHIFT                       MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_PCIEX4A_CLAMP_CONTROL_0_CLAMP_FIELD                       MK_FIELD_CONST(0x1, PMC_IMPL_PART_PCIEX4A_CLAMP_CONTROL_0_CLAMP_SHIFT)
#define PMC_IMPL_PART_PCIEX4A_CLAMP_CONTROL_0_CLAMP_RANGE                       0:0
#define PMC_IMPL_PART_PCIEX4A_CLAMP_CONTROL_0_CLAMP_MSB                 MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_PCIEX4A_CLAMP_CONTROL_0_CLAMP_LSB                 MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_PCIEX4A_CLAMP_CONTROL_0_CLAMP_WOFFSET                     0x0
#define PMC_IMPL_PART_PCIEX4A_CLAMP_CONTROL_0_CLAMP_DEFAULT                     MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PCIEX4A_CLAMP_CONTROL_0_CLAMP_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PCIEX4A_CLAMP_CONTROL_0_CLAMP_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX4A_CLAMP_CONTROL_0_CLAMP_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX4A_CLAMP_CONTROL_0_CLAMP_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX4A_CLAMP_CONTROL_0_CLAMP_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PCIEX4A_CLAMP_CONTROL_0_CLAMP_INIT_ENUM                   ON
#define PMC_IMPL_PART_PCIEX4A_CLAMP_CONTROL_0_CLAMP_OFF                 MK_ENUM_CONST(0)
#define PMC_IMPL_PART_PCIEX4A_CLAMP_CONTROL_0_CLAMP_ON                  MK_ENUM_CONST(1)


// Register PMC_IMPL_PART_PCIEX1A_POWER_GATE_CONTROL_0
#define PMC_IMPL_PART_PCIEX1A_POWER_GATE_CONTROL_0                      MK_ADDR_CONST(0x43c)
#define PMC_IMPL_PART_PCIEX1A_POWER_GATE_CONTROL_0_SECURE                       0x0
#define PMC_IMPL_PART_PCIEX1A_POWER_GATE_CONTROL_0_DUAL                         0x0
#define PMC_IMPL_PART_PCIEX1A_POWER_GATE_CONTROL_0_SCR                  PG_PCIEX1A_SCR_0
#define PMC_IMPL_PART_PCIEX1A_POWER_GATE_CONTROL_0_SCRREG                       PMC_IMPL_SCR_PG_PCIEX1A_SCR_0
#define PMC_IMPL_PART_PCIEX1A_POWER_GATE_CONTROL_0_WORD_COUNT                   0x1
#define PMC_IMPL_PART_PCIEX1A_POWER_GATE_CONTROL_0_RESET_VAL                    MK_MASK_CONST(0x80000005)
#define PMC_IMPL_PART_PCIEX1A_POWER_GATE_CONTROL_0_RESET_MASK                   MK_MASK_CONST(0x80000107)
#define PMC_IMPL_PART_PCIEX1A_POWER_GATE_CONTROL_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX1A_POWER_GATE_CONTROL_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX1A_POWER_GATE_CONTROL_0_READ_MASK                    MK_MASK_CONST(0x80000107)
#define PMC_IMPL_PART_PCIEX1A_POWER_GATE_CONTROL_0_WRITE_MASK                   MK_MASK_CONST(0x80000105)
#define PMC_IMPL_PART_PCIEX1A_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SHIFT                    MK_SHIFT_CONST(31)
#define PMC_IMPL_PART_PCIEX1A_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_FIELD                    MK_FIELD_CONST(0x1, PMC_IMPL_PART_PCIEX1A_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SHIFT)
#define PMC_IMPL_PART_PCIEX1A_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_RANGE                    31:31
#define PMC_IMPL_PART_PCIEX1A_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_MSB                      MK_SHIFT_CONST(31)
#define PMC_IMPL_PART_PCIEX1A_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_LSB                      MK_SHIFT_CONST(31)
#define PMC_IMPL_PART_PCIEX1A_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_WOFFSET                  0x0
#define PMC_IMPL_PART_PCIEX1A_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_DEFAULT                  MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PCIEX1A_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PCIEX1A_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX1A_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX1A_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX1A_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PCIEX1A_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_INIT_ENUM                        ENABLE
#define PMC_IMPL_PART_PCIEX1A_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_DISABLE                  MK_ENUM_CONST(0)
#define PMC_IMPL_PART_PCIEX1A_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_ENABLE                   MK_ENUM_CONST(1)

#define PMC_IMPL_PART_PCIEX1A_POWER_GATE_CONTROL_0_START_SHIFT                  MK_SHIFT_CONST(8)
#define PMC_IMPL_PART_PCIEX1A_POWER_GATE_CONTROL_0_START_FIELD                  MK_FIELD_CONST(0x1, PMC_IMPL_PART_PCIEX1A_POWER_GATE_CONTROL_0_START_SHIFT)
#define PMC_IMPL_PART_PCIEX1A_POWER_GATE_CONTROL_0_START_RANGE                  8:8
#define PMC_IMPL_PART_PCIEX1A_POWER_GATE_CONTROL_0_START_MSB                    MK_SHIFT_CONST(8)
#define PMC_IMPL_PART_PCIEX1A_POWER_GATE_CONTROL_0_START_LSB                    MK_SHIFT_CONST(8)
#define PMC_IMPL_PART_PCIEX1A_POWER_GATE_CONTROL_0_START_WOFFSET                        0x0
#define PMC_IMPL_PART_PCIEX1A_POWER_GATE_CONTROL_0_START_DEFAULT                        MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX1A_POWER_GATE_CONTROL_0_START_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PCIEX1A_POWER_GATE_CONTROL_0_START_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX1A_POWER_GATE_CONTROL_0_START_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX1A_POWER_GATE_CONTROL_0_START_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX1A_POWER_GATE_CONTROL_0_START_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PCIEX1A_POWER_GATE_CONTROL_0_START_INIT_ENUM                      DONE
#define PMC_IMPL_PART_PCIEX1A_POWER_GATE_CONTROL_0_START_DONE                   MK_ENUM_CONST(0)
#define PMC_IMPL_PART_PCIEX1A_POWER_GATE_CONTROL_0_START_PENDING                        MK_ENUM_CONST(1)

#define PMC_IMPL_PART_PCIEX1A_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SHIFT                  MK_SHIFT_CONST(2)
#define PMC_IMPL_PART_PCIEX1A_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_FIELD                  MK_FIELD_CONST(0x1, PMC_IMPL_PART_PCIEX1A_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SHIFT)
#define PMC_IMPL_PART_PCIEX1A_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_RANGE                  2:2
#define PMC_IMPL_PART_PCIEX1A_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_MSB                    MK_SHIFT_CONST(2)
#define PMC_IMPL_PART_PCIEX1A_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_LSB                    MK_SHIFT_CONST(2)
#define PMC_IMPL_PART_PCIEX1A_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_WOFFSET                        0x0
#define PMC_IMPL_PART_PCIEX1A_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_DEFAULT                        MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PCIEX1A_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PCIEX1A_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX1A_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX1A_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX1A_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PCIEX1A_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_INIT_ENUM                      ON
#define PMC_IMPL_PART_PCIEX1A_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_OFF                    MK_ENUM_CONST(0)
#define PMC_IMPL_PART_PCIEX1A_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_ON                     MK_ENUM_CONST(1)

#define PMC_IMPL_PART_PCIEX1A_POWER_GATE_CONTROL_0_SRAM_RET_EN_SHIFT                    MK_SHIFT_CONST(1)
#define PMC_IMPL_PART_PCIEX1A_POWER_GATE_CONTROL_0_SRAM_RET_EN_FIELD                    MK_FIELD_CONST(0x1, PMC_IMPL_PART_PCIEX1A_POWER_GATE_CONTROL_0_SRAM_RET_EN_SHIFT)
#define PMC_IMPL_PART_PCIEX1A_POWER_GATE_CONTROL_0_SRAM_RET_EN_RANGE                    1:1
#define PMC_IMPL_PART_PCIEX1A_POWER_GATE_CONTROL_0_SRAM_RET_EN_MSB                      MK_SHIFT_CONST(1)
#define PMC_IMPL_PART_PCIEX1A_POWER_GATE_CONTROL_0_SRAM_RET_EN_LSB                      MK_SHIFT_CONST(1)
#define PMC_IMPL_PART_PCIEX1A_POWER_GATE_CONTROL_0_SRAM_RET_EN_WOFFSET                  0x0
#define PMC_IMPL_PART_PCIEX1A_POWER_GATE_CONTROL_0_SRAM_RET_EN_DEFAULT                  MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX1A_POWER_GATE_CONTROL_0_SRAM_RET_EN_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PCIEX1A_POWER_GATE_CONTROL_0_SRAM_RET_EN_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX1A_POWER_GATE_CONTROL_0_SRAM_RET_EN_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX1A_POWER_GATE_CONTROL_0_SRAM_RET_EN_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX1A_POWER_GATE_CONTROL_0_SRAM_RET_EN_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PCIEX1A_POWER_GATE_CONTROL_0_SRAM_RET_EN_INIT_ENUM                        OFF
#define PMC_IMPL_PART_PCIEX1A_POWER_GATE_CONTROL_0_SRAM_RET_EN_OFF                      MK_ENUM_CONST(0)
#define PMC_IMPL_PART_PCIEX1A_POWER_GATE_CONTROL_0_SRAM_RET_EN_ON                       MK_ENUM_CONST(1)

#define PMC_IMPL_PART_PCIEX1A_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SHIFT                    MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_PCIEX1A_POWER_GATE_CONTROL_0_LOGIC_SLEEP_FIELD                    MK_FIELD_CONST(0x1, PMC_IMPL_PART_PCIEX1A_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SHIFT)
#define PMC_IMPL_PART_PCIEX1A_POWER_GATE_CONTROL_0_LOGIC_SLEEP_RANGE                    0:0
#define PMC_IMPL_PART_PCIEX1A_POWER_GATE_CONTROL_0_LOGIC_SLEEP_MSB                      MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_PCIEX1A_POWER_GATE_CONTROL_0_LOGIC_SLEEP_LSB                      MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_PCIEX1A_POWER_GATE_CONTROL_0_LOGIC_SLEEP_WOFFSET                  0x0
#define PMC_IMPL_PART_PCIEX1A_POWER_GATE_CONTROL_0_LOGIC_SLEEP_DEFAULT                  MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PCIEX1A_POWER_GATE_CONTROL_0_LOGIC_SLEEP_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PCIEX1A_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX1A_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX1A_POWER_GATE_CONTROL_0_LOGIC_SLEEP_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX1A_POWER_GATE_CONTROL_0_LOGIC_SLEEP_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PCIEX1A_POWER_GATE_CONTROL_0_LOGIC_SLEEP_INIT_ENUM                        ON
#define PMC_IMPL_PART_PCIEX1A_POWER_GATE_CONTROL_0_LOGIC_SLEEP_OFF                      MK_ENUM_CONST(0)
#define PMC_IMPL_PART_PCIEX1A_POWER_GATE_CONTROL_0_LOGIC_SLEEP_ON                       MK_ENUM_CONST(1)


// Register PMC_IMPL_PART_PCIEX1A_POWER_GATE_STATUS_0
#define PMC_IMPL_PART_PCIEX1A_POWER_GATE_STATUS_0                       MK_ADDR_CONST(0x440)
#define PMC_IMPL_PART_PCIEX1A_POWER_GATE_STATUS_0_SECURE                        0x0
#define PMC_IMPL_PART_PCIEX1A_POWER_GATE_STATUS_0_DUAL                  0x0
#define PMC_IMPL_PART_PCIEX1A_POWER_GATE_STATUS_0_SCR                   PG_PCIEX1A_SCR_0
#define PMC_IMPL_PART_PCIEX1A_POWER_GATE_STATUS_0_SCRREG                        PMC_IMPL_SCR_PG_PCIEX1A_SCR_0
#define PMC_IMPL_PART_PCIEX1A_POWER_GATE_STATUS_0_WORD_COUNT                    0x1
#define PMC_IMPL_PART_PCIEX1A_POWER_GATE_STATUS_0_RESET_VAL                     MK_MASK_CONST(0x5)
#define PMC_IMPL_PART_PCIEX1A_POWER_GATE_STATUS_0_RESET_MASK                    MK_MASK_CONST(0x7)
#define PMC_IMPL_PART_PCIEX1A_POWER_GATE_STATUS_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX1A_POWER_GATE_STATUS_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX1A_POWER_GATE_STATUS_0_READ_MASK                     MK_MASK_CONST(0x7)
#define PMC_IMPL_PART_PCIEX1A_POWER_GATE_STATUS_0_WRITE_MASK                    MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX1A_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SHIFT                  MK_SHIFT_CONST(2)
#define PMC_IMPL_PART_PCIEX1A_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_FIELD                  MK_FIELD_CONST(0x1, PMC_IMPL_PART_PCIEX1A_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SHIFT)
#define PMC_IMPL_PART_PCIEX1A_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_RANGE                  2:2
#define PMC_IMPL_PART_PCIEX1A_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_MSB                    MK_SHIFT_CONST(2)
#define PMC_IMPL_PART_PCIEX1A_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_LSB                    MK_SHIFT_CONST(2)
#define PMC_IMPL_PART_PCIEX1A_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_WOFFSET                        0x0
#define PMC_IMPL_PART_PCIEX1A_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_DEFAULT                        MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PCIEX1A_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PCIEX1A_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX1A_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX1A_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX1A_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PCIEX1A_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_INIT_ENUM                      ON
#define PMC_IMPL_PART_PCIEX1A_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_OFF                    MK_ENUM_CONST(0)
#define PMC_IMPL_PART_PCIEX1A_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_ON                     MK_ENUM_CONST(1)

#define PMC_IMPL_PART_PCIEX1A_POWER_GATE_STATUS_0_SRAM_RET_STS_SHIFT                    MK_SHIFT_CONST(1)
#define PMC_IMPL_PART_PCIEX1A_POWER_GATE_STATUS_0_SRAM_RET_STS_FIELD                    MK_FIELD_CONST(0x1, PMC_IMPL_PART_PCIEX1A_POWER_GATE_STATUS_0_SRAM_RET_STS_SHIFT)
#define PMC_IMPL_PART_PCIEX1A_POWER_GATE_STATUS_0_SRAM_RET_STS_RANGE                    1:1
#define PMC_IMPL_PART_PCIEX1A_POWER_GATE_STATUS_0_SRAM_RET_STS_MSB                      MK_SHIFT_CONST(1)
#define PMC_IMPL_PART_PCIEX1A_POWER_GATE_STATUS_0_SRAM_RET_STS_LSB                      MK_SHIFT_CONST(1)
#define PMC_IMPL_PART_PCIEX1A_POWER_GATE_STATUS_0_SRAM_RET_STS_WOFFSET                  0x0
#define PMC_IMPL_PART_PCIEX1A_POWER_GATE_STATUS_0_SRAM_RET_STS_DEFAULT                  MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX1A_POWER_GATE_STATUS_0_SRAM_RET_STS_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PCIEX1A_POWER_GATE_STATUS_0_SRAM_RET_STS_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX1A_POWER_GATE_STATUS_0_SRAM_RET_STS_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX1A_POWER_GATE_STATUS_0_SRAM_RET_STS_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX1A_POWER_GATE_STATUS_0_SRAM_RET_STS_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PCIEX1A_POWER_GATE_STATUS_0_SRAM_RET_STS_INIT_ENUM                        OFF
#define PMC_IMPL_PART_PCIEX1A_POWER_GATE_STATUS_0_SRAM_RET_STS_OFF                      MK_ENUM_CONST(0)
#define PMC_IMPL_PART_PCIEX1A_POWER_GATE_STATUS_0_SRAM_RET_STS_ON                       MK_ENUM_CONST(1)

#define PMC_IMPL_PART_PCIEX1A_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SHIFT                 MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_PCIEX1A_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_FIELD                 MK_FIELD_CONST(0x1, PMC_IMPL_PART_PCIEX1A_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SHIFT)
#define PMC_IMPL_PART_PCIEX1A_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_RANGE                 0:0
#define PMC_IMPL_PART_PCIEX1A_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_MSB                   MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_PCIEX1A_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_LSB                   MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_PCIEX1A_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_WOFFSET                       0x0
#define PMC_IMPL_PART_PCIEX1A_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_DEFAULT                       MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PCIEX1A_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PCIEX1A_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX1A_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX1A_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX1A_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PCIEX1A_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_INIT_ENUM                     ON
#define PMC_IMPL_PART_PCIEX1A_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_OFF                   MK_ENUM_CONST(0)
#define PMC_IMPL_PART_PCIEX1A_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_ON                    MK_ENUM_CONST(1)


// Register PMC_IMPL_PART_PCIEX1A_CLAMP_CONTROL_0
#define PMC_IMPL_PART_PCIEX1A_CLAMP_CONTROL_0                   MK_ADDR_CONST(0x444)
#define PMC_IMPL_PART_PCIEX1A_CLAMP_CONTROL_0_SECURE                    0x0
#define PMC_IMPL_PART_PCIEX1A_CLAMP_CONTROL_0_DUAL                      0x0
#define PMC_IMPL_PART_PCIEX1A_CLAMP_CONTROL_0_SCR                       PG_PCIEX1A_SCR_0
#define PMC_IMPL_PART_PCIEX1A_CLAMP_CONTROL_0_SCRREG                    PMC_IMPL_SCR_PG_PCIEX1A_SCR_0
#define PMC_IMPL_PART_PCIEX1A_CLAMP_CONTROL_0_WORD_COUNT                        0x1
#define PMC_IMPL_PART_PCIEX1A_CLAMP_CONTROL_0_RESET_VAL                         MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PCIEX1A_CLAMP_CONTROL_0_RESET_MASK                        MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PCIEX1A_CLAMP_CONTROL_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX1A_CLAMP_CONTROL_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX1A_CLAMP_CONTROL_0_READ_MASK                         MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PCIEX1A_CLAMP_CONTROL_0_WRITE_MASK                        MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PCIEX1A_CLAMP_CONTROL_0_CLAMP_SHIFT                       MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_PCIEX1A_CLAMP_CONTROL_0_CLAMP_FIELD                       MK_FIELD_CONST(0x1, PMC_IMPL_PART_PCIEX1A_CLAMP_CONTROL_0_CLAMP_SHIFT)
#define PMC_IMPL_PART_PCIEX1A_CLAMP_CONTROL_0_CLAMP_RANGE                       0:0
#define PMC_IMPL_PART_PCIEX1A_CLAMP_CONTROL_0_CLAMP_MSB                 MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_PCIEX1A_CLAMP_CONTROL_0_CLAMP_LSB                 MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_PCIEX1A_CLAMP_CONTROL_0_CLAMP_WOFFSET                     0x0
#define PMC_IMPL_PART_PCIEX1A_CLAMP_CONTROL_0_CLAMP_DEFAULT                     MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PCIEX1A_CLAMP_CONTROL_0_CLAMP_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PCIEX1A_CLAMP_CONTROL_0_CLAMP_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX1A_CLAMP_CONTROL_0_CLAMP_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX1A_CLAMP_CONTROL_0_CLAMP_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX1A_CLAMP_CONTROL_0_CLAMP_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PCIEX1A_CLAMP_CONTROL_0_CLAMP_INIT_ENUM                   ON
#define PMC_IMPL_PART_PCIEX1A_CLAMP_CONTROL_0_CLAMP_OFF                 MK_ENUM_CONST(0)
#define PMC_IMPL_PART_PCIEX1A_CLAMP_CONTROL_0_CLAMP_ON                  MK_ENUM_CONST(1)


// Reserved address 0x448

// Reserved address 0x44c

// Reserved address 0x450

// Register PMC_IMPL_PART_PCIEX8B_POWER_GATE_CONTROL_0
#define PMC_IMPL_PART_PCIEX8B_POWER_GATE_CONTROL_0                      MK_ADDR_CONST(0x454)
#define PMC_IMPL_PART_PCIEX8B_POWER_GATE_CONTROL_0_SECURE                       0x0
#define PMC_IMPL_PART_PCIEX8B_POWER_GATE_CONTROL_0_DUAL                         0x0
#define PMC_IMPL_PART_PCIEX8B_POWER_GATE_CONTROL_0_SCR                  PG_PCIEX8B_SCR_0
#define PMC_IMPL_PART_PCIEX8B_POWER_GATE_CONTROL_0_SCRREG                       PMC_IMPL_SCR_PG_PCIEX8B_SCR_0
#define PMC_IMPL_PART_PCIEX8B_POWER_GATE_CONTROL_0_WORD_COUNT                   0x1
#define PMC_IMPL_PART_PCIEX8B_POWER_GATE_CONTROL_0_RESET_VAL                    MK_MASK_CONST(0x80000005)
#define PMC_IMPL_PART_PCIEX8B_POWER_GATE_CONTROL_0_RESET_MASK                   MK_MASK_CONST(0x80000107)
#define PMC_IMPL_PART_PCIEX8B_POWER_GATE_CONTROL_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX8B_POWER_GATE_CONTROL_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX8B_POWER_GATE_CONTROL_0_READ_MASK                    MK_MASK_CONST(0x80000107)
#define PMC_IMPL_PART_PCIEX8B_POWER_GATE_CONTROL_0_WRITE_MASK                   MK_MASK_CONST(0x80000105)
#define PMC_IMPL_PART_PCIEX8B_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SHIFT                    MK_SHIFT_CONST(31)
#define PMC_IMPL_PART_PCIEX8B_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_FIELD                    MK_FIELD_CONST(0x1, PMC_IMPL_PART_PCIEX8B_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SHIFT)
#define PMC_IMPL_PART_PCIEX8B_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_RANGE                    31:31
#define PMC_IMPL_PART_PCIEX8B_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_MSB                      MK_SHIFT_CONST(31)
#define PMC_IMPL_PART_PCIEX8B_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_LSB                      MK_SHIFT_CONST(31)
#define PMC_IMPL_PART_PCIEX8B_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_WOFFSET                  0x0
#define PMC_IMPL_PART_PCIEX8B_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_DEFAULT                  MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PCIEX8B_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PCIEX8B_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX8B_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX8B_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX8B_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PCIEX8B_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_INIT_ENUM                        ENABLE
#define PMC_IMPL_PART_PCIEX8B_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_DISABLE                  MK_ENUM_CONST(0)
#define PMC_IMPL_PART_PCIEX8B_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_ENABLE                   MK_ENUM_CONST(1)

#define PMC_IMPL_PART_PCIEX8B_POWER_GATE_CONTROL_0_START_SHIFT                  MK_SHIFT_CONST(8)
#define PMC_IMPL_PART_PCIEX8B_POWER_GATE_CONTROL_0_START_FIELD                  MK_FIELD_CONST(0x1, PMC_IMPL_PART_PCIEX8B_POWER_GATE_CONTROL_0_START_SHIFT)
#define PMC_IMPL_PART_PCIEX8B_POWER_GATE_CONTROL_0_START_RANGE                  8:8
#define PMC_IMPL_PART_PCIEX8B_POWER_GATE_CONTROL_0_START_MSB                    MK_SHIFT_CONST(8)
#define PMC_IMPL_PART_PCIEX8B_POWER_GATE_CONTROL_0_START_LSB                    MK_SHIFT_CONST(8)
#define PMC_IMPL_PART_PCIEX8B_POWER_GATE_CONTROL_0_START_WOFFSET                        0x0
#define PMC_IMPL_PART_PCIEX8B_POWER_GATE_CONTROL_0_START_DEFAULT                        MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX8B_POWER_GATE_CONTROL_0_START_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PCIEX8B_POWER_GATE_CONTROL_0_START_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX8B_POWER_GATE_CONTROL_0_START_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX8B_POWER_GATE_CONTROL_0_START_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX8B_POWER_GATE_CONTROL_0_START_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PCIEX8B_POWER_GATE_CONTROL_0_START_INIT_ENUM                      DONE
#define PMC_IMPL_PART_PCIEX8B_POWER_GATE_CONTROL_0_START_DONE                   MK_ENUM_CONST(0)
#define PMC_IMPL_PART_PCIEX8B_POWER_GATE_CONTROL_0_START_PENDING                        MK_ENUM_CONST(1)

#define PMC_IMPL_PART_PCIEX8B_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SHIFT                  MK_SHIFT_CONST(2)
#define PMC_IMPL_PART_PCIEX8B_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_FIELD                  MK_FIELD_CONST(0x1, PMC_IMPL_PART_PCIEX8B_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SHIFT)
#define PMC_IMPL_PART_PCIEX8B_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_RANGE                  2:2
#define PMC_IMPL_PART_PCIEX8B_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_MSB                    MK_SHIFT_CONST(2)
#define PMC_IMPL_PART_PCIEX8B_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_LSB                    MK_SHIFT_CONST(2)
#define PMC_IMPL_PART_PCIEX8B_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_WOFFSET                        0x0
#define PMC_IMPL_PART_PCIEX8B_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_DEFAULT                        MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PCIEX8B_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PCIEX8B_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX8B_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX8B_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX8B_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PCIEX8B_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_INIT_ENUM                      ON
#define PMC_IMPL_PART_PCIEX8B_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_OFF                    MK_ENUM_CONST(0)
#define PMC_IMPL_PART_PCIEX8B_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_ON                     MK_ENUM_CONST(1)

#define PMC_IMPL_PART_PCIEX8B_POWER_GATE_CONTROL_0_SRAM_RET_EN_SHIFT                    MK_SHIFT_CONST(1)
#define PMC_IMPL_PART_PCIEX8B_POWER_GATE_CONTROL_0_SRAM_RET_EN_FIELD                    MK_FIELD_CONST(0x1, PMC_IMPL_PART_PCIEX8B_POWER_GATE_CONTROL_0_SRAM_RET_EN_SHIFT)
#define PMC_IMPL_PART_PCIEX8B_POWER_GATE_CONTROL_0_SRAM_RET_EN_RANGE                    1:1
#define PMC_IMPL_PART_PCIEX8B_POWER_GATE_CONTROL_0_SRAM_RET_EN_MSB                      MK_SHIFT_CONST(1)
#define PMC_IMPL_PART_PCIEX8B_POWER_GATE_CONTROL_0_SRAM_RET_EN_LSB                      MK_SHIFT_CONST(1)
#define PMC_IMPL_PART_PCIEX8B_POWER_GATE_CONTROL_0_SRAM_RET_EN_WOFFSET                  0x0
#define PMC_IMPL_PART_PCIEX8B_POWER_GATE_CONTROL_0_SRAM_RET_EN_DEFAULT                  MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX8B_POWER_GATE_CONTROL_0_SRAM_RET_EN_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PCIEX8B_POWER_GATE_CONTROL_0_SRAM_RET_EN_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX8B_POWER_GATE_CONTROL_0_SRAM_RET_EN_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX8B_POWER_GATE_CONTROL_0_SRAM_RET_EN_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX8B_POWER_GATE_CONTROL_0_SRAM_RET_EN_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PCIEX8B_POWER_GATE_CONTROL_0_SRAM_RET_EN_INIT_ENUM                        OFF
#define PMC_IMPL_PART_PCIEX8B_POWER_GATE_CONTROL_0_SRAM_RET_EN_OFF                      MK_ENUM_CONST(0)
#define PMC_IMPL_PART_PCIEX8B_POWER_GATE_CONTROL_0_SRAM_RET_EN_ON                       MK_ENUM_CONST(1)

#define PMC_IMPL_PART_PCIEX8B_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SHIFT                    MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_PCIEX8B_POWER_GATE_CONTROL_0_LOGIC_SLEEP_FIELD                    MK_FIELD_CONST(0x1, PMC_IMPL_PART_PCIEX8B_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SHIFT)
#define PMC_IMPL_PART_PCIEX8B_POWER_GATE_CONTROL_0_LOGIC_SLEEP_RANGE                    0:0
#define PMC_IMPL_PART_PCIEX8B_POWER_GATE_CONTROL_0_LOGIC_SLEEP_MSB                      MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_PCIEX8B_POWER_GATE_CONTROL_0_LOGIC_SLEEP_LSB                      MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_PCIEX8B_POWER_GATE_CONTROL_0_LOGIC_SLEEP_WOFFSET                  0x0
#define PMC_IMPL_PART_PCIEX8B_POWER_GATE_CONTROL_0_LOGIC_SLEEP_DEFAULT                  MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PCIEX8B_POWER_GATE_CONTROL_0_LOGIC_SLEEP_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PCIEX8B_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX8B_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX8B_POWER_GATE_CONTROL_0_LOGIC_SLEEP_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX8B_POWER_GATE_CONTROL_0_LOGIC_SLEEP_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PCIEX8B_POWER_GATE_CONTROL_0_LOGIC_SLEEP_INIT_ENUM                        ON
#define PMC_IMPL_PART_PCIEX8B_POWER_GATE_CONTROL_0_LOGIC_SLEEP_OFF                      MK_ENUM_CONST(0)
#define PMC_IMPL_PART_PCIEX8B_POWER_GATE_CONTROL_0_LOGIC_SLEEP_ON                       MK_ENUM_CONST(1)


// Register PMC_IMPL_PART_PCIEX8B_POWER_GATE_STATUS_0
#define PMC_IMPL_PART_PCIEX8B_POWER_GATE_STATUS_0                       MK_ADDR_CONST(0x458)
#define PMC_IMPL_PART_PCIEX8B_POWER_GATE_STATUS_0_SECURE                        0x0
#define PMC_IMPL_PART_PCIEX8B_POWER_GATE_STATUS_0_DUAL                  0x0
#define PMC_IMPL_PART_PCIEX8B_POWER_GATE_STATUS_0_SCR                   PG_PCIEX8B_SCR_0
#define PMC_IMPL_PART_PCIEX8B_POWER_GATE_STATUS_0_SCRREG                        PMC_IMPL_SCR_PG_PCIEX8B_SCR_0
#define PMC_IMPL_PART_PCIEX8B_POWER_GATE_STATUS_0_WORD_COUNT                    0x1
#define PMC_IMPL_PART_PCIEX8B_POWER_GATE_STATUS_0_RESET_VAL                     MK_MASK_CONST(0x5)
#define PMC_IMPL_PART_PCIEX8B_POWER_GATE_STATUS_0_RESET_MASK                    MK_MASK_CONST(0x7)
#define PMC_IMPL_PART_PCIEX8B_POWER_GATE_STATUS_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX8B_POWER_GATE_STATUS_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX8B_POWER_GATE_STATUS_0_READ_MASK                     MK_MASK_CONST(0x7)
#define PMC_IMPL_PART_PCIEX8B_POWER_GATE_STATUS_0_WRITE_MASK                    MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX8B_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SHIFT                  MK_SHIFT_CONST(2)
#define PMC_IMPL_PART_PCIEX8B_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_FIELD                  MK_FIELD_CONST(0x1, PMC_IMPL_PART_PCIEX8B_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SHIFT)
#define PMC_IMPL_PART_PCIEX8B_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_RANGE                  2:2
#define PMC_IMPL_PART_PCIEX8B_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_MSB                    MK_SHIFT_CONST(2)
#define PMC_IMPL_PART_PCIEX8B_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_LSB                    MK_SHIFT_CONST(2)
#define PMC_IMPL_PART_PCIEX8B_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_WOFFSET                        0x0
#define PMC_IMPL_PART_PCIEX8B_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_DEFAULT                        MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PCIEX8B_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PCIEX8B_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX8B_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX8B_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX8B_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PCIEX8B_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_INIT_ENUM                      ON
#define PMC_IMPL_PART_PCIEX8B_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_OFF                    MK_ENUM_CONST(0)
#define PMC_IMPL_PART_PCIEX8B_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_ON                     MK_ENUM_CONST(1)

#define PMC_IMPL_PART_PCIEX8B_POWER_GATE_STATUS_0_SRAM_RET_STS_SHIFT                    MK_SHIFT_CONST(1)
#define PMC_IMPL_PART_PCIEX8B_POWER_GATE_STATUS_0_SRAM_RET_STS_FIELD                    MK_FIELD_CONST(0x1, PMC_IMPL_PART_PCIEX8B_POWER_GATE_STATUS_0_SRAM_RET_STS_SHIFT)
#define PMC_IMPL_PART_PCIEX8B_POWER_GATE_STATUS_0_SRAM_RET_STS_RANGE                    1:1
#define PMC_IMPL_PART_PCIEX8B_POWER_GATE_STATUS_0_SRAM_RET_STS_MSB                      MK_SHIFT_CONST(1)
#define PMC_IMPL_PART_PCIEX8B_POWER_GATE_STATUS_0_SRAM_RET_STS_LSB                      MK_SHIFT_CONST(1)
#define PMC_IMPL_PART_PCIEX8B_POWER_GATE_STATUS_0_SRAM_RET_STS_WOFFSET                  0x0
#define PMC_IMPL_PART_PCIEX8B_POWER_GATE_STATUS_0_SRAM_RET_STS_DEFAULT                  MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX8B_POWER_GATE_STATUS_0_SRAM_RET_STS_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PCIEX8B_POWER_GATE_STATUS_0_SRAM_RET_STS_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX8B_POWER_GATE_STATUS_0_SRAM_RET_STS_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX8B_POWER_GATE_STATUS_0_SRAM_RET_STS_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX8B_POWER_GATE_STATUS_0_SRAM_RET_STS_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PCIEX8B_POWER_GATE_STATUS_0_SRAM_RET_STS_INIT_ENUM                        OFF
#define PMC_IMPL_PART_PCIEX8B_POWER_GATE_STATUS_0_SRAM_RET_STS_OFF                      MK_ENUM_CONST(0)
#define PMC_IMPL_PART_PCIEX8B_POWER_GATE_STATUS_0_SRAM_RET_STS_ON                       MK_ENUM_CONST(1)

#define PMC_IMPL_PART_PCIEX8B_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SHIFT                 MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_PCIEX8B_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_FIELD                 MK_FIELD_CONST(0x1, PMC_IMPL_PART_PCIEX8B_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SHIFT)
#define PMC_IMPL_PART_PCIEX8B_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_RANGE                 0:0
#define PMC_IMPL_PART_PCIEX8B_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_MSB                   MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_PCIEX8B_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_LSB                   MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_PCIEX8B_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_WOFFSET                       0x0
#define PMC_IMPL_PART_PCIEX8B_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_DEFAULT                       MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PCIEX8B_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PCIEX8B_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX8B_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX8B_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX8B_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PCIEX8B_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_INIT_ENUM                     ON
#define PMC_IMPL_PART_PCIEX8B_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_OFF                   MK_ENUM_CONST(0)
#define PMC_IMPL_PART_PCIEX8B_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_ON                    MK_ENUM_CONST(1)


// Register PMC_IMPL_PART_PCIEX8B_CLAMP_CONTROL_0
#define PMC_IMPL_PART_PCIEX8B_CLAMP_CONTROL_0                   MK_ADDR_CONST(0x45c)
#define PMC_IMPL_PART_PCIEX8B_CLAMP_CONTROL_0_SECURE                    0x0
#define PMC_IMPL_PART_PCIEX8B_CLAMP_CONTROL_0_DUAL                      0x0
#define PMC_IMPL_PART_PCIEX8B_CLAMP_CONTROL_0_SCR                       PG_PCIEX8B_SCR_0
#define PMC_IMPL_PART_PCIEX8B_CLAMP_CONTROL_0_SCRREG                    PMC_IMPL_SCR_PG_PCIEX8B_SCR_0
#define PMC_IMPL_PART_PCIEX8B_CLAMP_CONTROL_0_WORD_COUNT                        0x1
#define PMC_IMPL_PART_PCIEX8B_CLAMP_CONTROL_0_RESET_VAL                         MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PCIEX8B_CLAMP_CONTROL_0_RESET_MASK                        MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PCIEX8B_CLAMP_CONTROL_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX8B_CLAMP_CONTROL_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX8B_CLAMP_CONTROL_0_READ_MASK                         MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PCIEX8B_CLAMP_CONTROL_0_WRITE_MASK                        MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PCIEX8B_CLAMP_CONTROL_0_CLAMP_SHIFT                       MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_PCIEX8B_CLAMP_CONTROL_0_CLAMP_FIELD                       MK_FIELD_CONST(0x1, PMC_IMPL_PART_PCIEX8B_CLAMP_CONTROL_0_CLAMP_SHIFT)
#define PMC_IMPL_PART_PCIEX8B_CLAMP_CONTROL_0_CLAMP_RANGE                       0:0
#define PMC_IMPL_PART_PCIEX8B_CLAMP_CONTROL_0_CLAMP_MSB                 MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_PCIEX8B_CLAMP_CONTROL_0_CLAMP_LSB                 MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_PCIEX8B_CLAMP_CONTROL_0_CLAMP_WOFFSET                     0x0
#define PMC_IMPL_PART_PCIEX8B_CLAMP_CONTROL_0_CLAMP_DEFAULT                     MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PCIEX8B_CLAMP_CONTROL_0_CLAMP_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PCIEX8B_CLAMP_CONTROL_0_CLAMP_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX8B_CLAMP_CONTROL_0_CLAMP_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX8B_CLAMP_CONTROL_0_CLAMP_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX8B_CLAMP_CONTROL_0_CLAMP_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PCIEX8B_CLAMP_CONTROL_0_CLAMP_INIT_ENUM                   ON
#define PMC_IMPL_PART_PCIEX8B_CLAMP_CONTROL_0_CLAMP_OFF                 MK_ENUM_CONST(0)
#define PMC_IMPL_PART_PCIEX8B_CLAMP_CONTROL_0_CLAMP_ON                  MK_ENUM_CONST(1)


// Reserved address 0x460

// Reserved address 0x464

// Reserved address 0x468

// Reserved address 0x46c

// Reserved address 0x470

// Reserved address 0x474

// Register PMC_IMPL_PART_DLAA_POWER_GATE_CONTROL_0
#define PMC_IMPL_PART_DLAA_POWER_GATE_CONTROL_0                 MK_ADDR_CONST(0x478)
#define PMC_IMPL_PART_DLAA_POWER_GATE_CONTROL_0_SECURE                  0x0
#define PMC_IMPL_PART_DLAA_POWER_GATE_CONTROL_0_DUAL                    0x0
#define PMC_IMPL_PART_DLAA_POWER_GATE_CONTROL_0_SCR                     PG_DLAA_SCR_0
#define PMC_IMPL_PART_DLAA_POWER_GATE_CONTROL_0_SCRREG                  PMC_IMPL_SCR_PG_DLAA_SCR_0
#define PMC_IMPL_PART_DLAA_POWER_GATE_CONTROL_0_WORD_COUNT                      0x1
#define PMC_IMPL_PART_DLAA_POWER_GATE_CONTROL_0_RESET_VAL                       MK_MASK_CONST(0x80000005)
#define PMC_IMPL_PART_DLAA_POWER_GATE_CONTROL_0_RESET_MASK                      MK_MASK_CONST(0x80000107)
#define PMC_IMPL_PART_DLAA_POWER_GATE_CONTROL_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_DLAA_POWER_GATE_CONTROL_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_DLAA_POWER_GATE_CONTROL_0_READ_MASK                       MK_MASK_CONST(0x80000107)
#define PMC_IMPL_PART_DLAA_POWER_GATE_CONTROL_0_WRITE_MASK                      MK_MASK_CONST(0x80000105)
#define PMC_IMPL_PART_DLAA_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SHIFT                       MK_SHIFT_CONST(31)
#define PMC_IMPL_PART_DLAA_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_FIELD                       MK_FIELD_CONST(0x1, PMC_IMPL_PART_DLAA_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SHIFT)
#define PMC_IMPL_PART_DLAA_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_RANGE                       31:31
#define PMC_IMPL_PART_DLAA_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_MSB                 MK_SHIFT_CONST(31)
#define PMC_IMPL_PART_DLAA_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_LSB                 MK_SHIFT_CONST(31)
#define PMC_IMPL_PART_DLAA_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_WOFFSET                     0x0
#define PMC_IMPL_PART_DLAA_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_DEFAULT                     MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_DLAA_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_DLAA_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_DLAA_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_DLAA_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_DLAA_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_DLAA_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_INIT_ENUM                   ENABLE
#define PMC_IMPL_PART_DLAA_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_DISABLE                     MK_ENUM_CONST(0)
#define PMC_IMPL_PART_DLAA_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_ENABLE                      MK_ENUM_CONST(1)

#define PMC_IMPL_PART_DLAA_POWER_GATE_CONTROL_0_START_SHIFT                     MK_SHIFT_CONST(8)
#define PMC_IMPL_PART_DLAA_POWER_GATE_CONTROL_0_START_FIELD                     MK_FIELD_CONST(0x1, PMC_IMPL_PART_DLAA_POWER_GATE_CONTROL_0_START_SHIFT)
#define PMC_IMPL_PART_DLAA_POWER_GATE_CONTROL_0_START_RANGE                     8:8
#define PMC_IMPL_PART_DLAA_POWER_GATE_CONTROL_0_START_MSB                       MK_SHIFT_CONST(8)
#define PMC_IMPL_PART_DLAA_POWER_GATE_CONTROL_0_START_LSB                       MK_SHIFT_CONST(8)
#define PMC_IMPL_PART_DLAA_POWER_GATE_CONTROL_0_START_WOFFSET                   0x0
#define PMC_IMPL_PART_DLAA_POWER_GATE_CONTROL_0_START_DEFAULT                   MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_DLAA_POWER_GATE_CONTROL_0_START_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_DLAA_POWER_GATE_CONTROL_0_START_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_DLAA_POWER_GATE_CONTROL_0_START_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_DLAA_POWER_GATE_CONTROL_0_START_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_DLAA_POWER_GATE_CONTROL_0_START_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_DLAA_POWER_GATE_CONTROL_0_START_INIT_ENUM                 DONE
#define PMC_IMPL_PART_DLAA_POWER_GATE_CONTROL_0_START_DONE                      MK_ENUM_CONST(0)
#define PMC_IMPL_PART_DLAA_POWER_GATE_CONTROL_0_START_PENDING                   MK_ENUM_CONST(1)

#define PMC_IMPL_PART_DLAA_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SHIFT                     MK_SHIFT_CONST(2)
#define PMC_IMPL_PART_DLAA_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_FIELD                     MK_FIELD_CONST(0x1, PMC_IMPL_PART_DLAA_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SHIFT)
#define PMC_IMPL_PART_DLAA_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_RANGE                     2:2
#define PMC_IMPL_PART_DLAA_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_MSB                       MK_SHIFT_CONST(2)
#define PMC_IMPL_PART_DLAA_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_LSB                       MK_SHIFT_CONST(2)
#define PMC_IMPL_PART_DLAA_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_WOFFSET                   0x0
#define PMC_IMPL_PART_DLAA_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_DEFAULT                   MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_DLAA_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_DLAA_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_DLAA_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_DLAA_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_DLAA_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_DLAA_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_INIT_ENUM                 ON
#define PMC_IMPL_PART_DLAA_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_OFF                       MK_ENUM_CONST(0)
#define PMC_IMPL_PART_DLAA_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_ON                        MK_ENUM_CONST(1)

#define PMC_IMPL_PART_DLAA_POWER_GATE_CONTROL_0_SRAM_RET_EN_SHIFT                       MK_SHIFT_CONST(1)
#define PMC_IMPL_PART_DLAA_POWER_GATE_CONTROL_0_SRAM_RET_EN_FIELD                       MK_FIELD_CONST(0x1, PMC_IMPL_PART_DLAA_POWER_GATE_CONTROL_0_SRAM_RET_EN_SHIFT)
#define PMC_IMPL_PART_DLAA_POWER_GATE_CONTROL_0_SRAM_RET_EN_RANGE                       1:1
#define PMC_IMPL_PART_DLAA_POWER_GATE_CONTROL_0_SRAM_RET_EN_MSB                 MK_SHIFT_CONST(1)
#define PMC_IMPL_PART_DLAA_POWER_GATE_CONTROL_0_SRAM_RET_EN_LSB                 MK_SHIFT_CONST(1)
#define PMC_IMPL_PART_DLAA_POWER_GATE_CONTROL_0_SRAM_RET_EN_WOFFSET                     0x0
#define PMC_IMPL_PART_DLAA_POWER_GATE_CONTROL_0_SRAM_RET_EN_DEFAULT                     MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_DLAA_POWER_GATE_CONTROL_0_SRAM_RET_EN_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_DLAA_POWER_GATE_CONTROL_0_SRAM_RET_EN_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_DLAA_POWER_GATE_CONTROL_0_SRAM_RET_EN_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_DLAA_POWER_GATE_CONTROL_0_SRAM_RET_EN_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_DLAA_POWER_GATE_CONTROL_0_SRAM_RET_EN_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_DLAA_POWER_GATE_CONTROL_0_SRAM_RET_EN_INIT_ENUM                   OFF
#define PMC_IMPL_PART_DLAA_POWER_GATE_CONTROL_0_SRAM_RET_EN_OFF                 MK_ENUM_CONST(0)
#define PMC_IMPL_PART_DLAA_POWER_GATE_CONTROL_0_SRAM_RET_EN_ON                  MK_ENUM_CONST(1)

#define PMC_IMPL_PART_DLAA_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SHIFT                       MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_DLAA_POWER_GATE_CONTROL_0_LOGIC_SLEEP_FIELD                       MK_FIELD_CONST(0x1, PMC_IMPL_PART_DLAA_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SHIFT)
#define PMC_IMPL_PART_DLAA_POWER_GATE_CONTROL_0_LOGIC_SLEEP_RANGE                       0:0
#define PMC_IMPL_PART_DLAA_POWER_GATE_CONTROL_0_LOGIC_SLEEP_MSB                 MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_DLAA_POWER_GATE_CONTROL_0_LOGIC_SLEEP_LSB                 MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_DLAA_POWER_GATE_CONTROL_0_LOGIC_SLEEP_WOFFSET                     0x0
#define PMC_IMPL_PART_DLAA_POWER_GATE_CONTROL_0_LOGIC_SLEEP_DEFAULT                     MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_DLAA_POWER_GATE_CONTROL_0_LOGIC_SLEEP_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_DLAA_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_DLAA_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_DLAA_POWER_GATE_CONTROL_0_LOGIC_SLEEP_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_DLAA_POWER_GATE_CONTROL_0_LOGIC_SLEEP_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_DLAA_POWER_GATE_CONTROL_0_LOGIC_SLEEP_INIT_ENUM                   ON
#define PMC_IMPL_PART_DLAA_POWER_GATE_CONTROL_0_LOGIC_SLEEP_OFF                 MK_ENUM_CONST(0)
#define PMC_IMPL_PART_DLAA_POWER_GATE_CONTROL_0_LOGIC_SLEEP_ON                  MK_ENUM_CONST(1)


// Register PMC_IMPL_PART_DLAA_POWER_GATE_STATUS_0
#define PMC_IMPL_PART_DLAA_POWER_GATE_STATUS_0                  MK_ADDR_CONST(0x47c)
#define PMC_IMPL_PART_DLAA_POWER_GATE_STATUS_0_SECURE                   0x0
#define PMC_IMPL_PART_DLAA_POWER_GATE_STATUS_0_DUAL                     0x0
#define PMC_IMPL_PART_DLAA_POWER_GATE_STATUS_0_SCR                      PG_DLAA_SCR_0
#define PMC_IMPL_PART_DLAA_POWER_GATE_STATUS_0_SCRREG                   PMC_IMPL_SCR_PG_DLAA_SCR_0
#define PMC_IMPL_PART_DLAA_POWER_GATE_STATUS_0_WORD_COUNT                       0x1
#define PMC_IMPL_PART_DLAA_POWER_GATE_STATUS_0_RESET_VAL                        MK_MASK_CONST(0x5)
#define PMC_IMPL_PART_DLAA_POWER_GATE_STATUS_0_RESET_MASK                       MK_MASK_CONST(0x7)
#define PMC_IMPL_PART_DLAA_POWER_GATE_STATUS_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_DLAA_POWER_GATE_STATUS_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_DLAA_POWER_GATE_STATUS_0_READ_MASK                        MK_MASK_CONST(0x7)
#define PMC_IMPL_PART_DLAA_POWER_GATE_STATUS_0_WRITE_MASK                       MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_DLAA_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SHIFT                     MK_SHIFT_CONST(2)
#define PMC_IMPL_PART_DLAA_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_FIELD                     MK_FIELD_CONST(0x1, PMC_IMPL_PART_DLAA_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SHIFT)
#define PMC_IMPL_PART_DLAA_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_RANGE                     2:2
#define PMC_IMPL_PART_DLAA_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_MSB                       MK_SHIFT_CONST(2)
#define PMC_IMPL_PART_DLAA_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_LSB                       MK_SHIFT_CONST(2)
#define PMC_IMPL_PART_DLAA_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_WOFFSET                   0x0
#define PMC_IMPL_PART_DLAA_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_DEFAULT                   MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_DLAA_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_DLAA_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_DLAA_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_DLAA_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_DLAA_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_DLAA_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_INIT_ENUM                 ON
#define PMC_IMPL_PART_DLAA_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_OFF                       MK_ENUM_CONST(0)
#define PMC_IMPL_PART_DLAA_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_ON                        MK_ENUM_CONST(1)

#define PMC_IMPL_PART_DLAA_POWER_GATE_STATUS_0_SRAM_RET_STS_SHIFT                       MK_SHIFT_CONST(1)
#define PMC_IMPL_PART_DLAA_POWER_GATE_STATUS_0_SRAM_RET_STS_FIELD                       MK_FIELD_CONST(0x1, PMC_IMPL_PART_DLAA_POWER_GATE_STATUS_0_SRAM_RET_STS_SHIFT)
#define PMC_IMPL_PART_DLAA_POWER_GATE_STATUS_0_SRAM_RET_STS_RANGE                       1:1
#define PMC_IMPL_PART_DLAA_POWER_GATE_STATUS_0_SRAM_RET_STS_MSB                 MK_SHIFT_CONST(1)
#define PMC_IMPL_PART_DLAA_POWER_GATE_STATUS_0_SRAM_RET_STS_LSB                 MK_SHIFT_CONST(1)
#define PMC_IMPL_PART_DLAA_POWER_GATE_STATUS_0_SRAM_RET_STS_WOFFSET                     0x0
#define PMC_IMPL_PART_DLAA_POWER_GATE_STATUS_0_SRAM_RET_STS_DEFAULT                     MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_DLAA_POWER_GATE_STATUS_0_SRAM_RET_STS_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_DLAA_POWER_GATE_STATUS_0_SRAM_RET_STS_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_DLAA_POWER_GATE_STATUS_0_SRAM_RET_STS_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_DLAA_POWER_GATE_STATUS_0_SRAM_RET_STS_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_DLAA_POWER_GATE_STATUS_0_SRAM_RET_STS_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_DLAA_POWER_GATE_STATUS_0_SRAM_RET_STS_INIT_ENUM                   OFF
#define PMC_IMPL_PART_DLAA_POWER_GATE_STATUS_0_SRAM_RET_STS_OFF                 MK_ENUM_CONST(0)
#define PMC_IMPL_PART_DLAA_POWER_GATE_STATUS_0_SRAM_RET_STS_ON                  MK_ENUM_CONST(1)

#define PMC_IMPL_PART_DLAA_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SHIFT                    MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_DLAA_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_FIELD                    MK_FIELD_CONST(0x1, PMC_IMPL_PART_DLAA_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SHIFT)
#define PMC_IMPL_PART_DLAA_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_RANGE                    0:0
#define PMC_IMPL_PART_DLAA_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_MSB                      MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_DLAA_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_LSB                      MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_DLAA_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_WOFFSET                  0x0
#define PMC_IMPL_PART_DLAA_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_DEFAULT                  MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_DLAA_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_DLAA_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_DLAA_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_DLAA_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_DLAA_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_DLAA_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_INIT_ENUM                        ON
#define PMC_IMPL_PART_DLAA_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_OFF                      MK_ENUM_CONST(0)
#define PMC_IMPL_PART_DLAA_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_ON                       MK_ENUM_CONST(1)


// Register PMC_IMPL_PART_DLAA_CLAMP_CONTROL_0
#define PMC_IMPL_PART_DLAA_CLAMP_CONTROL_0                      MK_ADDR_CONST(0x480)
#define PMC_IMPL_PART_DLAA_CLAMP_CONTROL_0_SECURE                       0x0
#define PMC_IMPL_PART_DLAA_CLAMP_CONTROL_0_DUAL                         0x0
#define PMC_IMPL_PART_DLAA_CLAMP_CONTROL_0_SCR                  PG_DLAA_SCR_0
#define PMC_IMPL_PART_DLAA_CLAMP_CONTROL_0_SCRREG                       PMC_IMPL_SCR_PG_DLAA_SCR_0
#define PMC_IMPL_PART_DLAA_CLAMP_CONTROL_0_WORD_COUNT                   0x1
#define PMC_IMPL_PART_DLAA_CLAMP_CONTROL_0_RESET_VAL                    MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_DLAA_CLAMP_CONTROL_0_RESET_MASK                   MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_DLAA_CLAMP_CONTROL_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_DLAA_CLAMP_CONTROL_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_DLAA_CLAMP_CONTROL_0_READ_MASK                    MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_DLAA_CLAMP_CONTROL_0_WRITE_MASK                   MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_DLAA_CLAMP_CONTROL_0_CLAMP_SHIFT                  MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_DLAA_CLAMP_CONTROL_0_CLAMP_FIELD                  MK_FIELD_CONST(0x1, PMC_IMPL_PART_DLAA_CLAMP_CONTROL_0_CLAMP_SHIFT)
#define PMC_IMPL_PART_DLAA_CLAMP_CONTROL_0_CLAMP_RANGE                  0:0
#define PMC_IMPL_PART_DLAA_CLAMP_CONTROL_0_CLAMP_MSB                    MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_DLAA_CLAMP_CONTROL_0_CLAMP_LSB                    MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_DLAA_CLAMP_CONTROL_0_CLAMP_WOFFSET                        0x0
#define PMC_IMPL_PART_DLAA_CLAMP_CONTROL_0_CLAMP_DEFAULT                        MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_DLAA_CLAMP_CONTROL_0_CLAMP_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_DLAA_CLAMP_CONTROL_0_CLAMP_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_DLAA_CLAMP_CONTROL_0_CLAMP_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_DLAA_CLAMP_CONTROL_0_CLAMP_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_DLAA_CLAMP_CONTROL_0_CLAMP_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_DLAA_CLAMP_CONTROL_0_CLAMP_INIT_ENUM                      ON
#define PMC_IMPL_PART_DLAA_CLAMP_CONTROL_0_CLAMP_OFF                    MK_ENUM_CONST(0)
#define PMC_IMPL_PART_DLAA_CLAMP_CONTROL_0_CLAMP_ON                     MK_ENUM_CONST(1)


// Register PMC_IMPL_PART_DLAB_POWER_GATE_CONTROL_0
#define PMC_IMPL_PART_DLAB_POWER_GATE_CONTROL_0                 MK_ADDR_CONST(0x484)
#define PMC_IMPL_PART_DLAB_POWER_GATE_CONTROL_0_SECURE                  0x0
#define PMC_IMPL_PART_DLAB_POWER_GATE_CONTROL_0_DUAL                    0x0
#define PMC_IMPL_PART_DLAB_POWER_GATE_CONTROL_0_SCR                     PG_DLAB_SCR_0
#define PMC_IMPL_PART_DLAB_POWER_GATE_CONTROL_0_SCRREG                  PMC_IMPL_SCR_PG_DLAB_SCR_0
#define PMC_IMPL_PART_DLAB_POWER_GATE_CONTROL_0_WORD_COUNT                      0x1
#define PMC_IMPL_PART_DLAB_POWER_GATE_CONTROL_0_RESET_VAL                       MK_MASK_CONST(0x80000005)
#define PMC_IMPL_PART_DLAB_POWER_GATE_CONTROL_0_RESET_MASK                      MK_MASK_CONST(0x80000107)
#define PMC_IMPL_PART_DLAB_POWER_GATE_CONTROL_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_DLAB_POWER_GATE_CONTROL_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_DLAB_POWER_GATE_CONTROL_0_READ_MASK                       MK_MASK_CONST(0x80000107)
#define PMC_IMPL_PART_DLAB_POWER_GATE_CONTROL_0_WRITE_MASK                      MK_MASK_CONST(0x80000105)
#define PMC_IMPL_PART_DLAB_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SHIFT                       MK_SHIFT_CONST(31)
#define PMC_IMPL_PART_DLAB_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_FIELD                       MK_FIELD_CONST(0x1, PMC_IMPL_PART_DLAB_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SHIFT)
#define PMC_IMPL_PART_DLAB_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_RANGE                       31:31
#define PMC_IMPL_PART_DLAB_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_MSB                 MK_SHIFT_CONST(31)
#define PMC_IMPL_PART_DLAB_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_LSB                 MK_SHIFT_CONST(31)
#define PMC_IMPL_PART_DLAB_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_WOFFSET                     0x0
#define PMC_IMPL_PART_DLAB_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_DEFAULT                     MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_DLAB_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_DLAB_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_DLAB_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_DLAB_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_DLAB_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_DLAB_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_INIT_ENUM                   ENABLE
#define PMC_IMPL_PART_DLAB_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_DISABLE                     MK_ENUM_CONST(0)
#define PMC_IMPL_PART_DLAB_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_ENABLE                      MK_ENUM_CONST(1)

#define PMC_IMPL_PART_DLAB_POWER_GATE_CONTROL_0_START_SHIFT                     MK_SHIFT_CONST(8)
#define PMC_IMPL_PART_DLAB_POWER_GATE_CONTROL_0_START_FIELD                     MK_FIELD_CONST(0x1, PMC_IMPL_PART_DLAB_POWER_GATE_CONTROL_0_START_SHIFT)
#define PMC_IMPL_PART_DLAB_POWER_GATE_CONTROL_0_START_RANGE                     8:8
#define PMC_IMPL_PART_DLAB_POWER_GATE_CONTROL_0_START_MSB                       MK_SHIFT_CONST(8)
#define PMC_IMPL_PART_DLAB_POWER_GATE_CONTROL_0_START_LSB                       MK_SHIFT_CONST(8)
#define PMC_IMPL_PART_DLAB_POWER_GATE_CONTROL_0_START_WOFFSET                   0x0
#define PMC_IMPL_PART_DLAB_POWER_GATE_CONTROL_0_START_DEFAULT                   MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_DLAB_POWER_GATE_CONTROL_0_START_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_DLAB_POWER_GATE_CONTROL_0_START_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_DLAB_POWER_GATE_CONTROL_0_START_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_DLAB_POWER_GATE_CONTROL_0_START_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_DLAB_POWER_GATE_CONTROL_0_START_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_DLAB_POWER_GATE_CONTROL_0_START_INIT_ENUM                 DONE
#define PMC_IMPL_PART_DLAB_POWER_GATE_CONTROL_0_START_DONE                      MK_ENUM_CONST(0)
#define PMC_IMPL_PART_DLAB_POWER_GATE_CONTROL_0_START_PENDING                   MK_ENUM_CONST(1)

#define PMC_IMPL_PART_DLAB_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SHIFT                     MK_SHIFT_CONST(2)
#define PMC_IMPL_PART_DLAB_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_FIELD                     MK_FIELD_CONST(0x1, PMC_IMPL_PART_DLAB_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SHIFT)
#define PMC_IMPL_PART_DLAB_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_RANGE                     2:2
#define PMC_IMPL_PART_DLAB_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_MSB                       MK_SHIFT_CONST(2)
#define PMC_IMPL_PART_DLAB_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_LSB                       MK_SHIFT_CONST(2)
#define PMC_IMPL_PART_DLAB_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_WOFFSET                   0x0
#define PMC_IMPL_PART_DLAB_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_DEFAULT                   MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_DLAB_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_DLAB_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_DLAB_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_DLAB_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_DLAB_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_DLAB_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_INIT_ENUM                 ON
#define PMC_IMPL_PART_DLAB_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_OFF                       MK_ENUM_CONST(0)
#define PMC_IMPL_PART_DLAB_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_ON                        MK_ENUM_CONST(1)

#define PMC_IMPL_PART_DLAB_POWER_GATE_CONTROL_0_SRAM_RET_EN_SHIFT                       MK_SHIFT_CONST(1)
#define PMC_IMPL_PART_DLAB_POWER_GATE_CONTROL_0_SRAM_RET_EN_FIELD                       MK_FIELD_CONST(0x1, PMC_IMPL_PART_DLAB_POWER_GATE_CONTROL_0_SRAM_RET_EN_SHIFT)
#define PMC_IMPL_PART_DLAB_POWER_GATE_CONTROL_0_SRAM_RET_EN_RANGE                       1:1
#define PMC_IMPL_PART_DLAB_POWER_GATE_CONTROL_0_SRAM_RET_EN_MSB                 MK_SHIFT_CONST(1)
#define PMC_IMPL_PART_DLAB_POWER_GATE_CONTROL_0_SRAM_RET_EN_LSB                 MK_SHIFT_CONST(1)
#define PMC_IMPL_PART_DLAB_POWER_GATE_CONTROL_0_SRAM_RET_EN_WOFFSET                     0x0
#define PMC_IMPL_PART_DLAB_POWER_GATE_CONTROL_0_SRAM_RET_EN_DEFAULT                     MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_DLAB_POWER_GATE_CONTROL_0_SRAM_RET_EN_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_DLAB_POWER_GATE_CONTROL_0_SRAM_RET_EN_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_DLAB_POWER_GATE_CONTROL_0_SRAM_RET_EN_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_DLAB_POWER_GATE_CONTROL_0_SRAM_RET_EN_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_DLAB_POWER_GATE_CONTROL_0_SRAM_RET_EN_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_DLAB_POWER_GATE_CONTROL_0_SRAM_RET_EN_INIT_ENUM                   OFF
#define PMC_IMPL_PART_DLAB_POWER_GATE_CONTROL_0_SRAM_RET_EN_OFF                 MK_ENUM_CONST(0)
#define PMC_IMPL_PART_DLAB_POWER_GATE_CONTROL_0_SRAM_RET_EN_ON                  MK_ENUM_CONST(1)

#define PMC_IMPL_PART_DLAB_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SHIFT                       MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_DLAB_POWER_GATE_CONTROL_0_LOGIC_SLEEP_FIELD                       MK_FIELD_CONST(0x1, PMC_IMPL_PART_DLAB_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SHIFT)
#define PMC_IMPL_PART_DLAB_POWER_GATE_CONTROL_0_LOGIC_SLEEP_RANGE                       0:0
#define PMC_IMPL_PART_DLAB_POWER_GATE_CONTROL_0_LOGIC_SLEEP_MSB                 MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_DLAB_POWER_GATE_CONTROL_0_LOGIC_SLEEP_LSB                 MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_DLAB_POWER_GATE_CONTROL_0_LOGIC_SLEEP_WOFFSET                     0x0
#define PMC_IMPL_PART_DLAB_POWER_GATE_CONTROL_0_LOGIC_SLEEP_DEFAULT                     MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_DLAB_POWER_GATE_CONTROL_0_LOGIC_SLEEP_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_DLAB_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_DLAB_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_DLAB_POWER_GATE_CONTROL_0_LOGIC_SLEEP_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_DLAB_POWER_GATE_CONTROL_0_LOGIC_SLEEP_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_DLAB_POWER_GATE_CONTROL_0_LOGIC_SLEEP_INIT_ENUM                   ON
#define PMC_IMPL_PART_DLAB_POWER_GATE_CONTROL_0_LOGIC_SLEEP_OFF                 MK_ENUM_CONST(0)
#define PMC_IMPL_PART_DLAB_POWER_GATE_CONTROL_0_LOGIC_SLEEP_ON                  MK_ENUM_CONST(1)


// Register PMC_IMPL_PART_DLAB_POWER_GATE_STATUS_0
#define PMC_IMPL_PART_DLAB_POWER_GATE_STATUS_0                  MK_ADDR_CONST(0x488)
#define PMC_IMPL_PART_DLAB_POWER_GATE_STATUS_0_SECURE                   0x0
#define PMC_IMPL_PART_DLAB_POWER_GATE_STATUS_0_DUAL                     0x0
#define PMC_IMPL_PART_DLAB_POWER_GATE_STATUS_0_SCR                      PG_DLAB_SCR_0
#define PMC_IMPL_PART_DLAB_POWER_GATE_STATUS_0_SCRREG                   PMC_IMPL_SCR_PG_DLAB_SCR_0
#define PMC_IMPL_PART_DLAB_POWER_GATE_STATUS_0_WORD_COUNT                       0x1
#define PMC_IMPL_PART_DLAB_POWER_GATE_STATUS_0_RESET_VAL                        MK_MASK_CONST(0x5)
#define PMC_IMPL_PART_DLAB_POWER_GATE_STATUS_0_RESET_MASK                       MK_MASK_CONST(0x7)
#define PMC_IMPL_PART_DLAB_POWER_GATE_STATUS_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_DLAB_POWER_GATE_STATUS_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_DLAB_POWER_GATE_STATUS_0_READ_MASK                        MK_MASK_CONST(0x7)
#define PMC_IMPL_PART_DLAB_POWER_GATE_STATUS_0_WRITE_MASK                       MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_DLAB_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SHIFT                     MK_SHIFT_CONST(2)
#define PMC_IMPL_PART_DLAB_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_FIELD                     MK_FIELD_CONST(0x1, PMC_IMPL_PART_DLAB_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SHIFT)
#define PMC_IMPL_PART_DLAB_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_RANGE                     2:2
#define PMC_IMPL_PART_DLAB_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_MSB                       MK_SHIFT_CONST(2)
#define PMC_IMPL_PART_DLAB_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_LSB                       MK_SHIFT_CONST(2)
#define PMC_IMPL_PART_DLAB_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_WOFFSET                   0x0
#define PMC_IMPL_PART_DLAB_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_DEFAULT                   MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_DLAB_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_DLAB_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_DLAB_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_DLAB_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_DLAB_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_DLAB_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_INIT_ENUM                 ON
#define PMC_IMPL_PART_DLAB_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_OFF                       MK_ENUM_CONST(0)
#define PMC_IMPL_PART_DLAB_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_ON                        MK_ENUM_CONST(1)

#define PMC_IMPL_PART_DLAB_POWER_GATE_STATUS_0_SRAM_RET_STS_SHIFT                       MK_SHIFT_CONST(1)
#define PMC_IMPL_PART_DLAB_POWER_GATE_STATUS_0_SRAM_RET_STS_FIELD                       MK_FIELD_CONST(0x1, PMC_IMPL_PART_DLAB_POWER_GATE_STATUS_0_SRAM_RET_STS_SHIFT)
#define PMC_IMPL_PART_DLAB_POWER_GATE_STATUS_0_SRAM_RET_STS_RANGE                       1:1
#define PMC_IMPL_PART_DLAB_POWER_GATE_STATUS_0_SRAM_RET_STS_MSB                 MK_SHIFT_CONST(1)
#define PMC_IMPL_PART_DLAB_POWER_GATE_STATUS_0_SRAM_RET_STS_LSB                 MK_SHIFT_CONST(1)
#define PMC_IMPL_PART_DLAB_POWER_GATE_STATUS_0_SRAM_RET_STS_WOFFSET                     0x0
#define PMC_IMPL_PART_DLAB_POWER_GATE_STATUS_0_SRAM_RET_STS_DEFAULT                     MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_DLAB_POWER_GATE_STATUS_0_SRAM_RET_STS_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_DLAB_POWER_GATE_STATUS_0_SRAM_RET_STS_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_DLAB_POWER_GATE_STATUS_0_SRAM_RET_STS_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_DLAB_POWER_GATE_STATUS_0_SRAM_RET_STS_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_DLAB_POWER_GATE_STATUS_0_SRAM_RET_STS_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_DLAB_POWER_GATE_STATUS_0_SRAM_RET_STS_INIT_ENUM                   OFF
#define PMC_IMPL_PART_DLAB_POWER_GATE_STATUS_0_SRAM_RET_STS_OFF                 MK_ENUM_CONST(0)
#define PMC_IMPL_PART_DLAB_POWER_GATE_STATUS_0_SRAM_RET_STS_ON                  MK_ENUM_CONST(1)

#define PMC_IMPL_PART_DLAB_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SHIFT                    MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_DLAB_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_FIELD                    MK_FIELD_CONST(0x1, PMC_IMPL_PART_DLAB_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SHIFT)
#define PMC_IMPL_PART_DLAB_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_RANGE                    0:0
#define PMC_IMPL_PART_DLAB_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_MSB                      MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_DLAB_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_LSB                      MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_DLAB_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_WOFFSET                  0x0
#define PMC_IMPL_PART_DLAB_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_DEFAULT                  MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_DLAB_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_DLAB_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_DLAB_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_DLAB_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_DLAB_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_DLAB_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_INIT_ENUM                        ON
#define PMC_IMPL_PART_DLAB_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_OFF                      MK_ENUM_CONST(0)
#define PMC_IMPL_PART_DLAB_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_ON                       MK_ENUM_CONST(1)


// Register PMC_IMPL_PART_DLAB_CLAMP_CONTROL_0
#define PMC_IMPL_PART_DLAB_CLAMP_CONTROL_0                      MK_ADDR_CONST(0x48c)
#define PMC_IMPL_PART_DLAB_CLAMP_CONTROL_0_SECURE                       0x0
#define PMC_IMPL_PART_DLAB_CLAMP_CONTROL_0_DUAL                         0x0
#define PMC_IMPL_PART_DLAB_CLAMP_CONTROL_0_SCR                  PG_DLAB_SCR_0
#define PMC_IMPL_PART_DLAB_CLAMP_CONTROL_0_SCRREG                       PMC_IMPL_SCR_PG_DLAB_SCR_0
#define PMC_IMPL_PART_DLAB_CLAMP_CONTROL_0_WORD_COUNT                   0x1
#define PMC_IMPL_PART_DLAB_CLAMP_CONTROL_0_RESET_VAL                    MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_DLAB_CLAMP_CONTROL_0_RESET_MASK                   MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_DLAB_CLAMP_CONTROL_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_DLAB_CLAMP_CONTROL_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_DLAB_CLAMP_CONTROL_0_READ_MASK                    MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_DLAB_CLAMP_CONTROL_0_WRITE_MASK                   MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_DLAB_CLAMP_CONTROL_0_CLAMP_SHIFT                  MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_DLAB_CLAMP_CONTROL_0_CLAMP_FIELD                  MK_FIELD_CONST(0x1, PMC_IMPL_PART_DLAB_CLAMP_CONTROL_0_CLAMP_SHIFT)
#define PMC_IMPL_PART_DLAB_CLAMP_CONTROL_0_CLAMP_RANGE                  0:0
#define PMC_IMPL_PART_DLAB_CLAMP_CONTROL_0_CLAMP_MSB                    MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_DLAB_CLAMP_CONTROL_0_CLAMP_LSB                    MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_DLAB_CLAMP_CONTROL_0_CLAMP_WOFFSET                        0x0
#define PMC_IMPL_PART_DLAB_CLAMP_CONTROL_0_CLAMP_DEFAULT                        MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_DLAB_CLAMP_CONTROL_0_CLAMP_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_DLAB_CLAMP_CONTROL_0_CLAMP_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_DLAB_CLAMP_CONTROL_0_CLAMP_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_DLAB_CLAMP_CONTROL_0_CLAMP_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_DLAB_CLAMP_CONTROL_0_CLAMP_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_DLAB_CLAMP_CONTROL_0_CLAMP_INIT_ENUM                      ON
#define PMC_IMPL_PART_DLAB_CLAMP_CONTROL_0_CLAMP_OFF                    MK_ENUM_CONST(0)
#define PMC_IMPL_PART_DLAB_CLAMP_CONTROL_0_CLAMP_ON                     MK_ENUM_CONST(1)


// Reserved address 0x490

// Reserved address 0x494

// Reserved address 0x498

// Reserved address 0x49c

// Reserved address 0x4a0

// Reserved address 0x4a4

// Reserved address 0x4a8

// Reserved address 0x4ac

// Reserved address 0x4b0

// Reserved address 0x4b4

// Reserved address 0x4b8

// Reserved address 0x4bc

// Register PMC_IMPL_PART_ISP_POWER_GATE_CONTROL_0
#define PMC_IMPL_PART_ISP_POWER_GATE_CONTROL_0                  MK_ADDR_CONST(0x4c0)
#define PMC_IMPL_PART_ISP_POWER_GATE_CONTROL_0_SECURE                   0x0
#define PMC_IMPL_PART_ISP_POWER_GATE_CONTROL_0_DUAL                     0x0
#define PMC_IMPL_PART_ISP_POWER_GATE_CONTROL_0_SCR                      PG_ISP_SCR_0
#define PMC_IMPL_PART_ISP_POWER_GATE_CONTROL_0_SCRREG                   PMC_IMPL_SCR_PG_ISP_SCR_0
#define PMC_IMPL_PART_ISP_POWER_GATE_CONTROL_0_WORD_COUNT                       0x1
#define PMC_IMPL_PART_ISP_POWER_GATE_CONTROL_0_RESET_VAL                        MK_MASK_CONST(0x80000005)
#define PMC_IMPL_PART_ISP_POWER_GATE_CONTROL_0_RESET_MASK                       MK_MASK_CONST(0x80000107)
#define PMC_IMPL_PART_ISP_POWER_GATE_CONTROL_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_ISP_POWER_GATE_CONTROL_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_ISP_POWER_GATE_CONTROL_0_READ_MASK                        MK_MASK_CONST(0x80000107)
#define PMC_IMPL_PART_ISP_POWER_GATE_CONTROL_0_WRITE_MASK                       MK_MASK_CONST(0x80000105)
#define PMC_IMPL_PART_ISP_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SHIFT                        MK_SHIFT_CONST(31)
#define PMC_IMPL_PART_ISP_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_FIELD                        MK_FIELD_CONST(0x1, PMC_IMPL_PART_ISP_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SHIFT)
#define PMC_IMPL_PART_ISP_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_RANGE                        31:31
#define PMC_IMPL_PART_ISP_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_MSB                  MK_SHIFT_CONST(31)
#define PMC_IMPL_PART_ISP_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_LSB                  MK_SHIFT_CONST(31)
#define PMC_IMPL_PART_ISP_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_WOFFSET                      0x0
#define PMC_IMPL_PART_ISP_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_DEFAULT                      MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_ISP_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_ISP_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_ISP_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_ISP_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_ISP_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_ISP_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_INIT_ENUM                    ENABLE
#define PMC_IMPL_PART_ISP_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_DISABLE                      MK_ENUM_CONST(0)
#define PMC_IMPL_PART_ISP_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_ENABLE                       MK_ENUM_CONST(1)

#define PMC_IMPL_PART_ISP_POWER_GATE_CONTROL_0_START_SHIFT                      MK_SHIFT_CONST(8)
#define PMC_IMPL_PART_ISP_POWER_GATE_CONTROL_0_START_FIELD                      MK_FIELD_CONST(0x1, PMC_IMPL_PART_ISP_POWER_GATE_CONTROL_0_START_SHIFT)
#define PMC_IMPL_PART_ISP_POWER_GATE_CONTROL_0_START_RANGE                      8:8
#define PMC_IMPL_PART_ISP_POWER_GATE_CONTROL_0_START_MSB                        MK_SHIFT_CONST(8)
#define PMC_IMPL_PART_ISP_POWER_GATE_CONTROL_0_START_LSB                        MK_SHIFT_CONST(8)
#define PMC_IMPL_PART_ISP_POWER_GATE_CONTROL_0_START_WOFFSET                    0x0
#define PMC_IMPL_PART_ISP_POWER_GATE_CONTROL_0_START_DEFAULT                    MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_ISP_POWER_GATE_CONTROL_0_START_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_ISP_POWER_GATE_CONTROL_0_START_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_ISP_POWER_GATE_CONTROL_0_START_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_ISP_POWER_GATE_CONTROL_0_START_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_ISP_POWER_GATE_CONTROL_0_START_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_ISP_POWER_GATE_CONTROL_0_START_INIT_ENUM                  DONE
#define PMC_IMPL_PART_ISP_POWER_GATE_CONTROL_0_START_DONE                       MK_ENUM_CONST(0)
#define PMC_IMPL_PART_ISP_POWER_GATE_CONTROL_0_START_PENDING                    MK_ENUM_CONST(1)

#define PMC_IMPL_PART_ISP_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SHIFT                      MK_SHIFT_CONST(2)
#define PMC_IMPL_PART_ISP_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_FIELD                      MK_FIELD_CONST(0x1, PMC_IMPL_PART_ISP_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SHIFT)
#define PMC_IMPL_PART_ISP_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_RANGE                      2:2
#define PMC_IMPL_PART_ISP_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_MSB                        MK_SHIFT_CONST(2)
#define PMC_IMPL_PART_ISP_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_LSB                        MK_SHIFT_CONST(2)
#define PMC_IMPL_PART_ISP_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_WOFFSET                    0x0
#define PMC_IMPL_PART_ISP_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_DEFAULT                    MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_ISP_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_ISP_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_ISP_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_ISP_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_ISP_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_ISP_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_INIT_ENUM                  ON
#define PMC_IMPL_PART_ISP_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_OFF                        MK_ENUM_CONST(0)
#define PMC_IMPL_PART_ISP_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_ON                 MK_ENUM_CONST(1)

#define PMC_IMPL_PART_ISP_POWER_GATE_CONTROL_0_SRAM_RET_EN_SHIFT                        MK_SHIFT_CONST(1)
#define PMC_IMPL_PART_ISP_POWER_GATE_CONTROL_0_SRAM_RET_EN_FIELD                        MK_FIELD_CONST(0x1, PMC_IMPL_PART_ISP_POWER_GATE_CONTROL_0_SRAM_RET_EN_SHIFT)
#define PMC_IMPL_PART_ISP_POWER_GATE_CONTROL_0_SRAM_RET_EN_RANGE                        1:1
#define PMC_IMPL_PART_ISP_POWER_GATE_CONTROL_0_SRAM_RET_EN_MSB                  MK_SHIFT_CONST(1)
#define PMC_IMPL_PART_ISP_POWER_GATE_CONTROL_0_SRAM_RET_EN_LSB                  MK_SHIFT_CONST(1)
#define PMC_IMPL_PART_ISP_POWER_GATE_CONTROL_0_SRAM_RET_EN_WOFFSET                      0x0
#define PMC_IMPL_PART_ISP_POWER_GATE_CONTROL_0_SRAM_RET_EN_DEFAULT                      MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_ISP_POWER_GATE_CONTROL_0_SRAM_RET_EN_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_ISP_POWER_GATE_CONTROL_0_SRAM_RET_EN_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_ISP_POWER_GATE_CONTROL_0_SRAM_RET_EN_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_ISP_POWER_GATE_CONTROL_0_SRAM_RET_EN_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_ISP_POWER_GATE_CONTROL_0_SRAM_RET_EN_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_ISP_POWER_GATE_CONTROL_0_SRAM_RET_EN_INIT_ENUM                    OFF
#define PMC_IMPL_PART_ISP_POWER_GATE_CONTROL_0_SRAM_RET_EN_OFF                  MK_ENUM_CONST(0)
#define PMC_IMPL_PART_ISP_POWER_GATE_CONTROL_0_SRAM_RET_EN_ON                   MK_ENUM_CONST(1)

#define PMC_IMPL_PART_ISP_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SHIFT                        MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_ISP_POWER_GATE_CONTROL_0_LOGIC_SLEEP_FIELD                        MK_FIELD_CONST(0x1, PMC_IMPL_PART_ISP_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SHIFT)
#define PMC_IMPL_PART_ISP_POWER_GATE_CONTROL_0_LOGIC_SLEEP_RANGE                        0:0
#define PMC_IMPL_PART_ISP_POWER_GATE_CONTROL_0_LOGIC_SLEEP_MSB                  MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_ISP_POWER_GATE_CONTROL_0_LOGIC_SLEEP_LSB                  MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_ISP_POWER_GATE_CONTROL_0_LOGIC_SLEEP_WOFFSET                      0x0
#define PMC_IMPL_PART_ISP_POWER_GATE_CONTROL_0_LOGIC_SLEEP_DEFAULT                      MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_ISP_POWER_GATE_CONTROL_0_LOGIC_SLEEP_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_ISP_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_ISP_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_ISP_POWER_GATE_CONTROL_0_LOGIC_SLEEP_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_ISP_POWER_GATE_CONTROL_0_LOGIC_SLEEP_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_ISP_POWER_GATE_CONTROL_0_LOGIC_SLEEP_INIT_ENUM                    ON
#define PMC_IMPL_PART_ISP_POWER_GATE_CONTROL_0_LOGIC_SLEEP_OFF                  MK_ENUM_CONST(0)
#define PMC_IMPL_PART_ISP_POWER_GATE_CONTROL_0_LOGIC_SLEEP_ON                   MK_ENUM_CONST(1)


// Register PMC_IMPL_PART_ISP_POWER_GATE_STATUS_0
#define PMC_IMPL_PART_ISP_POWER_GATE_STATUS_0                   MK_ADDR_CONST(0x4c4)
#define PMC_IMPL_PART_ISP_POWER_GATE_STATUS_0_SECURE                    0x0
#define PMC_IMPL_PART_ISP_POWER_GATE_STATUS_0_DUAL                      0x0
#define PMC_IMPL_PART_ISP_POWER_GATE_STATUS_0_SCR                       PG_ISP_SCR_0
#define PMC_IMPL_PART_ISP_POWER_GATE_STATUS_0_SCRREG                    PMC_IMPL_SCR_PG_ISP_SCR_0
#define PMC_IMPL_PART_ISP_POWER_GATE_STATUS_0_WORD_COUNT                        0x1
#define PMC_IMPL_PART_ISP_POWER_GATE_STATUS_0_RESET_VAL                         MK_MASK_CONST(0x5)
#define PMC_IMPL_PART_ISP_POWER_GATE_STATUS_0_RESET_MASK                        MK_MASK_CONST(0x7)
#define PMC_IMPL_PART_ISP_POWER_GATE_STATUS_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_ISP_POWER_GATE_STATUS_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_ISP_POWER_GATE_STATUS_0_READ_MASK                         MK_MASK_CONST(0x7)
#define PMC_IMPL_PART_ISP_POWER_GATE_STATUS_0_WRITE_MASK                        MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_ISP_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SHIFT                      MK_SHIFT_CONST(2)
#define PMC_IMPL_PART_ISP_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_FIELD                      MK_FIELD_CONST(0x1, PMC_IMPL_PART_ISP_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SHIFT)
#define PMC_IMPL_PART_ISP_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_RANGE                      2:2
#define PMC_IMPL_PART_ISP_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_MSB                        MK_SHIFT_CONST(2)
#define PMC_IMPL_PART_ISP_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_LSB                        MK_SHIFT_CONST(2)
#define PMC_IMPL_PART_ISP_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_WOFFSET                    0x0
#define PMC_IMPL_PART_ISP_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_DEFAULT                    MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_ISP_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_ISP_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_ISP_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_ISP_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_ISP_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_ISP_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_INIT_ENUM                  ON
#define PMC_IMPL_PART_ISP_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_OFF                        MK_ENUM_CONST(0)
#define PMC_IMPL_PART_ISP_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_ON                 MK_ENUM_CONST(1)

#define PMC_IMPL_PART_ISP_POWER_GATE_STATUS_0_SRAM_RET_STS_SHIFT                        MK_SHIFT_CONST(1)
#define PMC_IMPL_PART_ISP_POWER_GATE_STATUS_0_SRAM_RET_STS_FIELD                        MK_FIELD_CONST(0x1, PMC_IMPL_PART_ISP_POWER_GATE_STATUS_0_SRAM_RET_STS_SHIFT)
#define PMC_IMPL_PART_ISP_POWER_GATE_STATUS_0_SRAM_RET_STS_RANGE                        1:1
#define PMC_IMPL_PART_ISP_POWER_GATE_STATUS_0_SRAM_RET_STS_MSB                  MK_SHIFT_CONST(1)
#define PMC_IMPL_PART_ISP_POWER_GATE_STATUS_0_SRAM_RET_STS_LSB                  MK_SHIFT_CONST(1)
#define PMC_IMPL_PART_ISP_POWER_GATE_STATUS_0_SRAM_RET_STS_WOFFSET                      0x0
#define PMC_IMPL_PART_ISP_POWER_GATE_STATUS_0_SRAM_RET_STS_DEFAULT                      MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_ISP_POWER_GATE_STATUS_0_SRAM_RET_STS_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_ISP_POWER_GATE_STATUS_0_SRAM_RET_STS_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_ISP_POWER_GATE_STATUS_0_SRAM_RET_STS_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_ISP_POWER_GATE_STATUS_0_SRAM_RET_STS_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_ISP_POWER_GATE_STATUS_0_SRAM_RET_STS_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_ISP_POWER_GATE_STATUS_0_SRAM_RET_STS_INIT_ENUM                    OFF
#define PMC_IMPL_PART_ISP_POWER_GATE_STATUS_0_SRAM_RET_STS_OFF                  MK_ENUM_CONST(0)
#define PMC_IMPL_PART_ISP_POWER_GATE_STATUS_0_SRAM_RET_STS_ON                   MK_ENUM_CONST(1)

#define PMC_IMPL_PART_ISP_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SHIFT                     MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_ISP_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_FIELD                     MK_FIELD_CONST(0x1, PMC_IMPL_PART_ISP_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SHIFT)
#define PMC_IMPL_PART_ISP_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_RANGE                     0:0
#define PMC_IMPL_PART_ISP_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_MSB                       MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_ISP_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_LSB                       MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_ISP_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_WOFFSET                   0x0
#define PMC_IMPL_PART_ISP_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_DEFAULT                   MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_ISP_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_ISP_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_ISP_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_ISP_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_ISP_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_ISP_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_INIT_ENUM                 ON
#define PMC_IMPL_PART_ISP_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_OFF                       MK_ENUM_CONST(0)
#define PMC_IMPL_PART_ISP_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_ON                        MK_ENUM_CONST(1)


// Register PMC_IMPL_PART_ISP_CLAMP_CONTROL_0
#define PMC_IMPL_PART_ISP_CLAMP_CONTROL_0                       MK_ADDR_CONST(0x4c8)
#define PMC_IMPL_PART_ISP_CLAMP_CONTROL_0_SECURE                        0x0
#define PMC_IMPL_PART_ISP_CLAMP_CONTROL_0_DUAL                  0x0
#define PMC_IMPL_PART_ISP_CLAMP_CONTROL_0_SCR                   PG_ISP_SCR_0
#define PMC_IMPL_PART_ISP_CLAMP_CONTROL_0_SCRREG                        PMC_IMPL_SCR_PG_ISP_SCR_0
#define PMC_IMPL_PART_ISP_CLAMP_CONTROL_0_WORD_COUNT                    0x1
#define PMC_IMPL_PART_ISP_CLAMP_CONTROL_0_RESET_VAL                     MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_ISP_CLAMP_CONTROL_0_RESET_MASK                    MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_ISP_CLAMP_CONTROL_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_ISP_CLAMP_CONTROL_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_ISP_CLAMP_CONTROL_0_READ_MASK                     MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_ISP_CLAMP_CONTROL_0_WRITE_MASK                    MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_ISP_CLAMP_CONTROL_0_CLAMP_SHIFT                   MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_ISP_CLAMP_CONTROL_0_CLAMP_FIELD                   MK_FIELD_CONST(0x1, PMC_IMPL_PART_ISP_CLAMP_CONTROL_0_CLAMP_SHIFT)
#define PMC_IMPL_PART_ISP_CLAMP_CONTROL_0_CLAMP_RANGE                   0:0
#define PMC_IMPL_PART_ISP_CLAMP_CONTROL_0_CLAMP_MSB                     MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_ISP_CLAMP_CONTROL_0_CLAMP_LSB                     MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_ISP_CLAMP_CONTROL_0_CLAMP_WOFFSET                 0x0
#define PMC_IMPL_PART_ISP_CLAMP_CONTROL_0_CLAMP_DEFAULT                 MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_ISP_CLAMP_CONTROL_0_CLAMP_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_ISP_CLAMP_CONTROL_0_CLAMP_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_ISP_CLAMP_CONTROL_0_CLAMP_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_ISP_CLAMP_CONTROL_0_CLAMP_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_ISP_CLAMP_CONTROL_0_CLAMP_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_ISP_CLAMP_CONTROL_0_CLAMP_INIT_ENUM                       ON
#define PMC_IMPL_PART_ISP_CLAMP_CONTROL_0_CLAMP_OFF                     MK_ENUM_CONST(0)
#define PMC_IMPL_PART_ISP_CLAMP_CONTROL_0_CLAMP_ON                      MK_ENUM_CONST(1)


// Register PMC_IMPL_PART_NVDEC_POWER_GATE_CONTROL_0
#define PMC_IMPL_PART_NVDEC_POWER_GATE_CONTROL_0                        MK_ADDR_CONST(0x4cc)
#define PMC_IMPL_PART_NVDEC_POWER_GATE_CONTROL_0_SECURE                         0x0
#define PMC_IMPL_PART_NVDEC_POWER_GATE_CONTROL_0_DUAL                   0x0
#define PMC_IMPL_PART_NVDEC_POWER_GATE_CONTROL_0_SCR                    PG_NVDEC_SCR_0
#define PMC_IMPL_PART_NVDEC_POWER_GATE_CONTROL_0_SCRREG                         PMC_IMPL_SCR_PG_NVDEC_SCR_0
#define PMC_IMPL_PART_NVDEC_POWER_GATE_CONTROL_0_WORD_COUNT                     0x1
#define PMC_IMPL_PART_NVDEC_POWER_GATE_CONTROL_0_RESET_VAL                      MK_MASK_CONST(0x80000005)
#define PMC_IMPL_PART_NVDEC_POWER_GATE_CONTROL_0_RESET_MASK                     MK_MASK_CONST(0x80000107)
#define PMC_IMPL_PART_NVDEC_POWER_GATE_CONTROL_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_NVDEC_POWER_GATE_CONTROL_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_NVDEC_POWER_GATE_CONTROL_0_READ_MASK                      MK_MASK_CONST(0x80000107)
#define PMC_IMPL_PART_NVDEC_POWER_GATE_CONTROL_0_WRITE_MASK                     MK_MASK_CONST(0x80000105)
#define PMC_IMPL_PART_NVDEC_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SHIFT                      MK_SHIFT_CONST(31)
#define PMC_IMPL_PART_NVDEC_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_FIELD                      MK_FIELD_CONST(0x1, PMC_IMPL_PART_NVDEC_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SHIFT)
#define PMC_IMPL_PART_NVDEC_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_RANGE                      31:31
#define PMC_IMPL_PART_NVDEC_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_MSB                        MK_SHIFT_CONST(31)
#define PMC_IMPL_PART_NVDEC_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_LSB                        MK_SHIFT_CONST(31)
#define PMC_IMPL_PART_NVDEC_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_WOFFSET                    0x0
#define PMC_IMPL_PART_NVDEC_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_DEFAULT                    MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_NVDEC_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_NVDEC_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_NVDEC_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_NVDEC_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_NVDEC_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_NVDEC_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_INIT_ENUM                  ENABLE
#define PMC_IMPL_PART_NVDEC_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_DISABLE                    MK_ENUM_CONST(0)
#define PMC_IMPL_PART_NVDEC_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_ENABLE                     MK_ENUM_CONST(1)

#define PMC_IMPL_PART_NVDEC_POWER_GATE_CONTROL_0_START_SHIFT                    MK_SHIFT_CONST(8)
#define PMC_IMPL_PART_NVDEC_POWER_GATE_CONTROL_0_START_FIELD                    MK_FIELD_CONST(0x1, PMC_IMPL_PART_NVDEC_POWER_GATE_CONTROL_0_START_SHIFT)
#define PMC_IMPL_PART_NVDEC_POWER_GATE_CONTROL_0_START_RANGE                    8:8
#define PMC_IMPL_PART_NVDEC_POWER_GATE_CONTROL_0_START_MSB                      MK_SHIFT_CONST(8)
#define PMC_IMPL_PART_NVDEC_POWER_GATE_CONTROL_0_START_LSB                      MK_SHIFT_CONST(8)
#define PMC_IMPL_PART_NVDEC_POWER_GATE_CONTROL_0_START_WOFFSET                  0x0
#define PMC_IMPL_PART_NVDEC_POWER_GATE_CONTROL_0_START_DEFAULT                  MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_NVDEC_POWER_GATE_CONTROL_0_START_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_NVDEC_POWER_GATE_CONTROL_0_START_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_NVDEC_POWER_GATE_CONTROL_0_START_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_NVDEC_POWER_GATE_CONTROL_0_START_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_NVDEC_POWER_GATE_CONTROL_0_START_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_NVDEC_POWER_GATE_CONTROL_0_START_INIT_ENUM                        DONE
#define PMC_IMPL_PART_NVDEC_POWER_GATE_CONTROL_0_START_DONE                     MK_ENUM_CONST(0)
#define PMC_IMPL_PART_NVDEC_POWER_GATE_CONTROL_0_START_PENDING                  MK_ENUM_CONST(1)

#define PMC_IMPL_PART_NVDEC_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SHIFT                    MK_SHIFT_CONST(2)
#define PMC_IMPL_PART_NVDEC_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_FIELD                    MK_FIELD_CONST(0x1, PMC_IMPL_PART_NVDEC_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SHIFT)
#define PMC_IMPL_PART_NVDEC_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_RANGE                    2:2
#define PMC_IMPL_PART_NVDEC_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_MSB                      MK_SHIFT_CONST(2)
#define PMC_IMPL_PART_NVDEC_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_LSB                      MK_SHIFT_CONST(2)
#define PMC_IMPL_PART_NVDEC_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_WOFFSET                  0x0
#define PMC_IMPL_PART_NVDEC_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_DEFAULT                  MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_NVDEC_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_NVDEC_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_NVDEC_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_NVDEC_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_NVDEC_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_NVDEC_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_INIT_ENUM                        ON
#define PMC_IMPL_PART_NVDEC_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_OFF                      MK_ENUM_CONST(0)
#define PMC_IMPL_PART_NVDEC_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_ON                       MK_ENUM_CONST(1)

#define PMC_IMPL_PART_NVDEC_POWER_GATE_CONTROL_0_SRAM_RET_EN_SHIFT                      MK_SHIFT_CONST(1)
#define PMC_IMPL_PART_NVDEC_POWER_GATE_CONTROL_0_SRAM_RET_EN_FIELD                      MK_FIELD_CONST(0x1, PMC_IMPL_PART_NVDEC_POWER_GATE_CONTROL_0_SRAM_RET_EN_SHIFT)
#define PMC_IMPL_PART_NVDEC_POWER_GATE_CONTROL_0_SRAM_RET_EN_RANGE                      1:1
#define PMC_IMPL_PART_NVDEC_POWER_GATE_CONTROL_0_SRAM_RET_EN_MSB                        MK_SHIFT_CONST(1)
#define PMC_IMPL_PART_NVDEC_POWER_GATE_CONTROL_0_SRAM_RET_EN_LSB                        MK_SHIFT_CONST(1)
#define PMC_IMPL_PART_NVDEC_POWER_GATE_CONTROL_0_SRAM_RET_EN_WOFFSET                    0x0
#define PMC_IMPL_PART_NVDEC_POWER_GATE_CONTROL_0_SRAM_RET_EN_DEFAULT                    MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_NVDEC_POWER_GATE_CONTROL_0_SRAM_RET_EN_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_NVDEC_POWER_GATE_CONTROL_0_SRAM_RET_EN_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_NVDEC_POWER_GATE_CONTROL_0_SRAM_RET_EN_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_NVDEC_POWER_GATE_CONTROL_0_SRAM_RET_EN_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_NVDEC_POWER_GATE_CONTROL_0_SRAM_RET_EN_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_NVDEC_POWER_GATE_CONTROL_0_SRAM_RET_EN_INIT_ENUM                  OFF
#define PMC_IMPL_PART_NVDEC_POWER_GATE_CONTROL_0_SRAM_RET_EN_OFF                        MK_ENUM_CONST(0)
#define PMC_IMPL_PART_NVDEC_POWER_GATE_CONTROL_0_SRAM_RET_EN_ON                 MK_ENUM_CONST(1)

#define PMC_IMPL_PART_NVDEC_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SHIFT                      MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_NVDEC_POWER_GATE_CONTROL_0_LOGIC_SLEEP_FIELD                      MK_FIELD_CONST(0x1, PMC_IMPL_PART_NVDEC_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SHIFT)
#define PMC_IMPL_PART_NVDEC_POWER_GATE_CONTROL_0_LOGIC_SLEEP_RANGE                      0:0
#define PMC_IMPL_PART_NVDEC_POWER_GATE_CONTROL_0_LOGIC_SLEEP_MSB                        MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_NVDEC_POWER_GATE_CONTROL_0_LOGIC_SLEEP_LSB                        MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_NVDEC_POWER_GATE_CONTROL_0_LOGIC_SLEEP_WOFFSET                    0x0
#define PMC_IMPL_PART_NVDEC_POWER_GATE_CONTROL_0_LOGIC_SLEEP_DEFAULT                    MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_NVDEC_POWER_GATE_CONTROL_0_LOGIC_SLEEP_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_NVDEC_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_NVDEC_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_NVDEC_POWER_GATE_CONTROL_0_LOGIC_SLEEP_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_NVDEC_POWER_GATE_CONTROL_0_LOGIC_SLEEP_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_NVDEC_POWER_GATE_CONTROL_0_LOGIC_SLEEP_INIT_ENUM                  ON
#define PMC_IMPL_PART_NVDEC_POWER_GATE_CONTROL_0_LOGIC_SLEEP_OFF                        MK_ENUM_CONST(0)
#define PMC_IMPL_PART_NVDEC_POWER_GATE_CONTROL_0_LOGIC_SLEEP_ON                 MK_ENUM_CONST(1)


// Register PMC_IMPL_PART_NVDEC_POWER_GATE_STATUS_0
#define PMC_IMPL_PART_NVDEC_POWER_GATE_STATUS_0                 MK_ADDR_CONST(0x4d0)
#define PMC_IMPL_PART_NVDEC_POWER_GATE_STATUS_0_SECURE                  0x0
#define PMC_IMPL_PART_NVDEC_POWER_GATE_STATUS_0_DUAL                    0x0
#define PMC_IMPL_PART_NVDEC_POWER_GATE_STATUS_0_SCR                     PG_NVDEC_SCR_0
#define PMC_IMPL_PART_NVDEC_POWER_GATE_STATUS_0_SCRREG                  PMC_IMPL_SCR_PG_NVDEC_SCR_0
#define PMC_IMPL_PART_NVDEC_POWER_GATE_STATUS_0_WORD_COUNT                      0x1
#define PMC_IMPL_PART_NVDEC_POWER_GATE_STATUS_0_RESET_VAL                       MK_MASK_CONST(0x5)
#define PMC_IMPL_PART_NVDEC_POWER_GATE_STATUS_0_RESET_MASK                      MK_MASK_CONST(0x7)
#define PMC_IMPL_PART_NVDEC_POWER_GATE_STATUS_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_NVDEC_POWER_GATE_STATUS_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_NVDEC_POWER_GATE_STATUS_0_READ_MASK                       MK_MASK_CONST(0x7)
#define PMC_IMPL_PART_NVDEC_POWER_GATE_STATUS_0_WRITE_MASK                      MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_NVDEC_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SHIFT                    MK_SHIFT_CONST(2)
#define PMC_IMPL_PART_NVDEC_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_FIELD                    MK_FIELD_CONST(0x1, PMC_IMPL_PART_NVDEC_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SHIFT)
#define PMC_IMPL_PART_NVDEC_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_RANGE                    2:2
#define PMC_IMPL_PART_NVDEC_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_MSB                      MK_SHIFT_CONST(2)
#define PMC_IMPL_PART_NVDEC_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_LSB                      MK_SHIFT_CONST(2)
#define PMC_IMPL_PART_NVDEC_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_WOFFSET                  0x0
#define PMC_IMPL_PART_NVDEC_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_DEFAULT                  MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_NVDEC_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_NVDEC_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_NVDEC_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_NVDEC_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_NVDEC_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_NVDEC_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_INIT_ENUM                        ON
#define PMC_IMPL_PART_NVDEC_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_OFF                      MK_ENUM_CONST(0)
#define PMC_IMPL_PART_NVDEC_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_ON                       MK_ENUM_CONST(1)

#define PMC_IMPL_PART_NVDEC_POWER_GATE_STATUS_0_SRAM_RET_STS_SHIFT                      MK_SHIFT_CONST(1)
#define PMC_IMPL_PART_NVDEC_POWER_GATE_STATUS_0_SRAM_RET_STS_FIELD                      MK_FIELD_CONST(0x1, PMC_IMPL_PART_NVDEC_POWER_GATE_STATUS_0_SRAM_RET_STS_SHIFT)
#define PMC_IMPL_PART_NVDEC_POWER_GATE_STATUS_0_SRAM_RET_STS_RANGE                      1:1
#define PMC_IMPL_PART_NVDEC_POWER_GATE_STATUS_0_SRAM_RET_STS_MSB                        MK_SHIFT_CONST(1)
#define PMC_IMPL_PART_NVDEC_POWER_GATE_STATUS_0_SRAM_RET_STS_LSB                        MK_SHIFT_CONST(1)
#define PMC_IMPL_PART_NVDEC_POWER_GATE_STATUS_0_SRAM_RET_STS_WOFFSET                    0x0
#define PMC_IMPL_PART_NVDEC_POWER_GATE_STATUS_0_SRAM_RET_STS_DEFAULT                    MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_NVDEC_POWER_GATE_STATUS_0_SRAM_RET_STS_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_NVDEC_POWER_GATE_STATUS_0_SRAM_RET_STS_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_NVDEC_POWER_GATE_STATUS_0_SRAM_RET_STS_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_NVDEC_POWER_GATE_STATUS_0_SRAM_RET_STS_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_NVDEC_POWER_GATE_STATUS_0_SRAM_RET_STS_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_NVDEC_POWER_GATE_STATUS_0_SRAM_RET_STS_INIT_ENUM                  OFF
#define PMC_IMPL_PART_NVDEC_POWER_GATE_STATUS_0_SRAM_RET_STS_OFF                        MK_ENUM_CONST(0)
#define PMC_IMPL_PART_NVDEC_POWER_GATE_STATUS_0_SRAM_RET_STS_ON                 MK_ENUM_CONST(1)

#define PMC_IMPL_PART_NVDEC_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SHIFT                   MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_NVDEC_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_FIELD                   MK_FIELD_CONST(0x1, PMC_IMPL_PART_NVDEC_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SHIFT)
#define PMC_IMPL_PART_NVDEC_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_RANGE                   0:0
#define PMC_IMPL_PART_NVDEC_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_MSB                     MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_NVDEC_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_LSB                     MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_NVDEC_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_WOFFSET                 0x0
#define PMC_IMPL_PART_NVDEC_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_DEFAULT                 MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_NVDEC_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_NVDEC_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_NVDEC_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_NVDEC_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_NVDEC_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_NVDEC_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_INIT_ENUM                       ON
#define PMC_IMPL_PART_NVDEC_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_OFF                     MK_ENUM_CONST(0)
#define PMC_IMPL_PART_NVDEC_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_ON                      MK_ENUM_CONST(1)


// Register PMC_IMPL_PART_NVDEC_CLAMP_CONTROL_0
#define PMC_IMPL_PART_NVDEC_CLAMP_CONTROL_0                     MK_ADDR_CONST(0x4d4)
#define PMC_IMPL_PART_NVDEC_CLAMP_CONTROL_0_SECURE                      0x0
#define PMC_IMPL_PART_NVDEC_CLAMP_CONTROL_0_DUAL                        0x0
#define PMC_IMPL_PART_NVDEC_CLAMP_CONTROL_0_SCR                         PG_NVDEC_SCR_0
#define PMC_IMPL_PART_NVDEC_CLAMP_CONTROL_0_SCRREG                      PMC_IMPL_SCR_PG_NVDEC_SCR_0
#define PMC_IMPL_PART_NVDEC_CLAMP_CONTROL_0_WORD_COUNT                  0x1
#define PMC_IMPL_PART_NVDEC_CLAMP_CONTROL_0_RESET_VAL                   MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_NVDEC_CLAMP_CONTROL_0_RESET_MASK                  MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_NVDEC_CLAMP_CONTROL_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_NVDEC_CLAMP_CONTROL_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_NVDEC_CLAMP_CONTROL_0_READ_MASK                   MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_NVDEC_CLAMP_CONTROL_0_WRITE_MASK                  MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_NVDEC_CLAMP_CONTROL_0_CLAMP_SHIFT                 MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_NVDEC_CLAMP_CONTROL_0_CLAMP_FIELD                 MK_FIELD_CONST(0x1, PMC_IMPL_PART_NVDEC_CLAMP_CONTROL_0_CLAMP_SHIFT)
#define PMC_IMPL_PART_NVDEC_CLAMP_CONTROL_0_CLAMP_RANGE                 0:0
#define PMC_IMPL_PART_NVDEC_CLAMP_CONTROL_0_CLAMP_MSB                   MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_NVDEC_CLAMP_CONTROL_0_CLAMP_LSB                   MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_NVDEC_CLAMP_CONTROL_0_CLAMP_WOFFSET                       0x0
#define PMC_IMPL_PART_NVDEC_CLAMP_CONTROL_0_CLAMP_DEFAULT                       MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_NVDEC_CLAMP_CONTROL_0_CLAMP_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_NVDEC_CLAMP_CONTROL_0_CLAMP_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_NVDEC_CLAMP_CONTROL_0_CLAMP_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_NVDEC_CLAMP_CONTROL_0_CLAMP_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_NVDEC_CLAMP_CONTROL_0_CLAMP_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_NVDEC_CLAMP_CONTROL_0_CLAMP_INIT_ENUM                     ON
#define PMC_IMPL_PART_NVDEC_CLAMP_CONTROL_0_CLAMP_OFF                   MK_ENUM_CONST(0)
#define PMC_IMPL_PART_NVDEC_CLAMP_CONTROL_0_CLAMP_ON                    MK_ENUM_CONST(1)


// Register PMC_IMPL_PART_NVJPGA_POWER_GATE_CONTROL_0
#define PMC_IMPL_PART_NVJPGA_POWER_GATE_CONTROL_0                       MK_ADDR_CONST(0x4d8)
#define PMC_IMPL_PART_NVJPGA_POWER_GATE_CONTROL_0_SECURE                        0x0
#define PMC_IMPL_PART_NVJPGA_POWER_GATE_CONTROL_0_DUAL                  0x0
#define PMC_IMPL_PART_NVJPGA_POWER_GATE_CONTROL_0_SCR                   PG_NVJPGA_SCR_0
#define PMC_IMPL_PART_NVJPGA_POWER_GATE_CONTROL_0_SCRREG                        PMC_IMPL_SCR_PG_NVJPGA_SCR_0
#define PMC_IMPL_PART_NVJPGA_POWER_GATE_CONTROL_0_WORD_COUNT                    0x1
#define PMC_IMPL_PART_NVJPGA_POWER_GATE_CONTROL_0_RESET_VAL                     MK_MASK_CONST(0x80000005)
#define PMC_IMPL_PART_NVJPGA_POWER_GATE_CONTROL_0_RESET_MASK                    MK_MASK_CONST(0x80000107)
#define PMC_IMPL_PART_NVJPGA_POWER_GATE_CONTROL_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_NVJPGA_POWER_GATE_CONTROL_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_NVJPGA_POWER_GATE_CONTROL_0_READ_MASK                     MK_MASK_CONST(0x80000107)
#define PMC_IMPL_PART_NVJPGA_POWER_GATE_CONTROL_0_WRITE_MASK                    MK_MASK_CONST(0x80000105)
#define PMC_IMPL_PART_NVJPGA_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SHIFT                     MK_SHIFT_CONST(31)
#define PMC_IMPL_PART_NVJPGA_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_FIELD                     MK_FIELD_CONST(0x1, PMC_IMPL_PART_NVJPGA_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SHIFT)
#define PMC_IMPL_PART_NVJPGA_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_RANGE                     31:31
#define PMC_IMPL_PART_NVJPGA_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_MSB                       MK_SHIFT_CONST(31)
#define PMC_IMPL_PART_NVJPGA_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_LSB                       MK_SHIFT_CONST(31)
#define PMC_IMPL_PART_NVJPGA_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_WOFFSET                   0x0
#define PMC_IMPL_PART_NVJPGA_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_DEFAULT                   MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_NVJPGA_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_NVJPGA_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_NVJPGA_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_NVJPGA_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_NVJPGA_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_NVJPGA_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_INIT_ENUM                 ENABLE
#define PMC_IMPL_PART_NVJPGA_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_DISABLE                   MK_ENUM_CONST(0)
#define PMC_IMPL_PART_NVJPGA_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_ENABLE                    MK_ENUM_CONST(1)

#define PMC_IMPL_PART_NVJPGA_POWER_GATE_CONTROL_0_START_SHIFT                   MK_SHIFT_CONST(8)
#define PMC_IMPL_PART_NVJPGA_POWER_GATE_CONTROL_0_START_FIELD                   MK_FIELD_CONST(0x1, PMC_IMPL_PART_NVJPGA_POWER_GATE_CONTROL_0_START_SHIFT)
#define PMC_IMPL_PART_NVJPGA_POWER_GATE_CONTROL_0_START_RANGE                   8:8
#define PMC_IMPL_PART_NVJPGA_POWER_GATE_CONTROL_0_START_MSB                     MK_SHIFT_CONST(8)
#define PMC_IMPL_PART_NVJPGA_POWER_GATE_CONTROL_0_START_LSB                     MK_SHIFT_CONST(8)
#define PMC_IMPL_PART_NVJPGA_POWER_GATE_CONTROL_0_START_WOFFSET                 0x0
#define PMC_IMPL_PART_NVJPGA_POWER_GATE_CONTROL_0_START_DEFAULT                 MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_NVJPGA_POWER_GATE_CONTROL_0_START_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_NVJPGA_POWER_GATE_CONTROL_0_START_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_NVJPGA_POWER_GATE_CONTROL_0_START_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_NVJPGA_POWER_GATE_CONTROL_0_START_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_NVJPGA_POWER_GATE_CONTROL_0_START_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_NVJPGA_POWER_GATE_CONTROL_0_START_INIT_ENUM                       DONE
#define PMC_IMPL_PART_NVJPGA_POWER_GATE_CONTROL_0_START_DONE                    MK_ENUM_CONST(0)
#define PMC_IMPL_PART_NVJPGA_POWER_GATE_CONTROL_0_START_PENDING                 MK_ENUM_CONST(1)

#define PMC_IMPL_PART_NVJPGA_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SHIFT                   MK_SHIFT_CONST(2)
#define PMC_IMPL_PART_NVJPGA_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_FIELD                   MK_FIELD_CONST(0x1, PMC_IMPL_PART_NVJPGA_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SHIFT)
#define PMC_IMPL_PART_NVJPGA_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_RANGE                   2:2
#define PMC_IMPL_PART_NVJPGA_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_MSB                     MK_SHIFT_CONST(2)
#define PMC_IMPL_PART_NVJPGA_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_LSB                     MK_SHIFT_CONST(2)
#define PMC_IMPL_PART_NVJPGA_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_WOFFSET                 0x0
#define PMC_IMPL_PART_NVJPGA_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_DEFAULT                 MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_NVJPGA_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_NVJPGA_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_NVJPGA_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_NVJPGA_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_NVJPGA_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_NVJPGA_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_INIT_ENUM                       ON
#define PMC_IMPL_PART_NVJPGA_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_OFF                     MK_ENUM_CONST(0)
#define PMC_IMPL_PART_NVJPGA_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_ON                      MK_ENUM_CONST(1)

#define PMC_IMPL_PART_NVJPGA_POWER_GATE_CONTROL_0_SRAM_RET_EN_SHIFT                     MK_SHIFT_CONST(1)
#define PMC_IMPL_PART_NVJPGA_POWER_GATE_CONTROL_0_SRAM_RET_EN_FIELD                     MK_FIELD_CONST(0x1, PMC_IMPL_PART_NVJPGA_POWER_GATE_CONTROL_0_SRAM_RET_EN_SHIFT)
#define PMC_IMPL_PART_NVJPGA_POWER_GATE_CONTROL_0_SRAM_RET_EN_RANGE                     1:1
#define PMC_IMPL_PART_NVJPGA_POWER_GATE_CONTROL_0_SRAM_RET_EN_MSB                       MK_SHIFT_CONST(1)
#define PMC_IMPL_PART_NVJPGA_POWER_GATE_CONTROL_0_SRAM_RET_EN_LSB                       MK_SHIFT_CONST(1)
#define PMC_IMPL_PART_NVJPGA_POWER_GATE_CONTROL_0_SRAM_RET_EN_WOFFSET                   0x0
#define PMC_IMPL_PART_NVJPGA_POWER_GATE_CONTROL_0_SRAM_RET_EN_DEFAULT                   MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_NVJPGA_POWER_GATE_CONTROL_0_SRAM_RET_EN_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_NVJPGA_POWER_GATE_CONTROL_0_SRAM_RET_EN_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_NVJPGA_POWER_GATE_CONTROL_0_SRAM_RET_EN_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_NVJPGA_POWER_GATE_CONTROL_0_SRAM_RET_EN_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_NVJPGA_POWER_GATE_CONTROL_0_SRAM_RET_EN_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_NVJPGA_POWER_GATE_CONTROL_0_SRAM_RET_EN_INIT_ENUM                 OFF
#define PMC_IMPL_PART_NVJPGA_POWER_GATE_CONTROL_0_SRAM_RET_EN_OFF                       MK_ENUM_CONST(0)
#define PMC_IMPL_PART_NVJPGA_POWER_GATE_CONTROL_0_SRAM_RET_EN_ON                        MK_ENUM_CONST(1)

#define PMC_IMPL_PART_NVJPGA_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SHIFT                     MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_NVJPGA_POWER_GATE_CONTROL_0_LOGIC_SLEEP_FIELD                     MK_FIELD_CONST(0x1, PMC_IMPL_PART_NVJPGA_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SHIFT)
#define PMC_IMPL_PART_NVJPGA_POWER_GATE_CONTROL_0_LOGIC_SLEEP_RANGE                     0:0
#define PMC_IMPL_PART_NVJPGA_POWER_GATE_CONTROL_0_LOGIC_SLEEP_MSB                       MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_NVJPGA_POWER_GATE_CONTROL_0_LOGIC_SLEEP_LSB                       MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_NVJPGA_POWER_GATE_CONTROL_0_LOGIC_SLEEP_WOFFSET                   0x0
#define PMC_IMPL_PART_NVJPGA_POWER_GATE_CONTROL_0_LOGIC_SLEEP_DEFAULT                   MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_NVJPGA_POWER_GATE_CONTROL_0_LOGIC_SLEEP_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_NVJPGA_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_NVJPGA_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_NVJPGA_POWER_GATE_CONTROL_0_LOGIC_SLEEP_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_NVJPGA_POWER_GATE_CONTROL_0_LOGIC_SLEEP_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_NVJPGA_POWER_GATE_CONTROL_0_LOGIC_SLEEP_INIT_ENUM                 ON
#define PMC_IMPL_PART_NVJPGA_POWER_GATE_CONTROL_0_LOGIC_SLEEP_OFF                       MK_ENUM_CONST(0)
#define PMC_IMPL_PART_NVJPGA_POWER_GATE_CONTROL_0_LOGIC_SLEEP_ON                        MK_ENUM_CONST(1)


// Register PMC_IMPL_PART_NVJPGA_POWER_GATE_STATUS_0
#define PMC_IMPL_PART_NVJPGA_POWER_GATE_STATUS_0                        MK_ADDR_CONST(0x4dc)
#define PMC_IMPL_PART_NVJPGA_POWER_GATE_STATUS_0_SECURE                         0x0
#define PMC_IMPL_PART_NVJPGA_POWER_GATE_STATUS_0_DUAL                   0x0
#define PMC_IMPL_PART_NVJPGA_POWER_GATE_STATUS_0_SCR                    PG_NVJPGA_SCR_0
#define PMC_IMPL_PART_NVJPGA_POWER_GATE_STATUS_0_SCRREG                         PMC_IMPL_SCR_PG_NVJPGA_SCR_0
#define PMC_IMPL_PART_NVJPGA_POWER_GATE_STATUS_0_WORD_COUNT                     0x1
#define PMC_IMPL_PART_NVJPGA_POWER_GATE_STATUS_0_RESET_VAL                      MK_MASK_CONST(0x5)
#define PMC_IMPL_PART_NVJPGA_POWER_GATE_STATUS_0_RESET_MASK                     MK_MASK_CONST(0x7)
#define PMC_IMPL_PART_NVJPGA_POWER_GATE_STATUS_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_NVJPGA_POWER_GATE_STATUS_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_NVJPGA_POWER_GATE_STATUS_0_READ_MASK                      MK_MASK_CONST(0x7)
#define PMC_IMPL_PART_NVJPGA_POWER_GATE_STATUS_0_WRITE_MASK                     MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_NVJPGA_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SHIFT                   MK_SHIFT_CONST(2)
#define PMC_IMPL_PART_NVJPGA_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_FIELD                   MK_FIELD_CONST(0x1, PMC_IMPL_PART_NVJPGA_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SHIFT)
#define PMC_IMPL_PART_NVJPGA_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_RANGE                   2:2
#define PMC_IMPL_PART_NVJPGA_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_MSB                     MK_SHIFT_CONST(2)
#define PMC_IMPL_PART_NVJPGA_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_LSB                     MK_SHIFT_CONST(2)
#define PMC_IMPL_PART_NVJPGA_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_WOFFSET                 0x0
#define PMC_IMPL_PART_NVJPGA_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_DEFAULT                 MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_NVJPGA_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_NVJPGA_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_NVJPGA_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_NVJPGA_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_NVJPGA_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_NVJPGA_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_INIT_ENUM                       ON
#define PMC_IMPL_PART_NVJPGA_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_OFF                     MK_ENUM_CONST(0)
#define PMC_IMPL_PART_NVJPGA_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_ON                      MK_ENUM_CONST(1)

#define PMC_IMPL_PART_NVJPGA_POWER_GATE_STATUS_0_SRAM_RET_STS_SHIFT                     MK_SHIFT_CONST(1)
#define PMC_IMPL_PART_NVJPGA_POWER_GATE_STATUS_0_SRAM_RET_STS_FIELD                     MK_FIELD_CONST(0x1, PMC_IMPL_PART_NVJPGA_POWER_GATE_STATUS_0_SRAM_RET_STS_SHIFT)
#define PMC_IMPL_PART_NVJPGA_POWER_GATE_STATUS_0_SRAM_RET_STS_RANGE                     1:1
#define PMC_IMPL_PART_NVJPGA_POWER_GATE_STATUS_0_SRAM_RET_STS_MSB                       MK_SHIFT_CONST(1)
#define PMC_IMPL_PART_NVJPGA_POWER_GATE_STATUS_0_SRAM_RET_STS_LSB                       MK_SHIFT_CONST(1)
#define PMC_IMPL_PART_NVJPGA_POWER_GATE_STATUS_0_SRAM_RET_STS_WOFFSET                   0x0
#define PMC_IMPL_PART_NVJPGA_POWER_GATE_STATUS_0_SRAM_RET_STS_DEFAULT                   MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_NVJPGA_POWER_GATE_STATUS_0_SRAM_RET_STS_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_NVJPGA_POWER_GATE_STATUS_0_SRAM_RET_STS_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_NVJPGA_POWER_GATE_STATUS_0_SRAM_RET_STS_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_NVJPGA_POWER_GATE_STATUS_0_SRAM_RET_STS_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_NVJPGA_POWER_GATE_STATUS_0_SRAM_RET_STS_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_NVJPGA_POWER_GATE_STATUS_0_SRAM_RET_STS_INIT_ENUM                 OFF
#define PMC_IMPL_PART_NVJPGA_POWER_GATE_STATUS_0_SRAM_RET_STS_OFF                       MK_ENUM_CONST(0)
#define PMC_IMPL_PART_NVJPGA_POWER_GATE_STATUS_0_SRAM_RET_STS_ON                        MK_ENUM_CONST(1)

#define PMC_IMPL_PART_NVJPGA_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SHIFT                  MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_NVJPGA_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_FIELD                  MK_FIELD_CONST(0x1, PMC_IMPL_PART_NVJPGA_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SHIFT)
#define PMC_IMPL_PART_NVJPGA_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_RANGE                  0:0
#define PMC_IMPL_PART_NVJPGA_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_MSB                    MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_NVJPGA_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_LSB                    MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_NVJPGA_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_WOFFSET                        0x0
#define PMC_IMPL_PART_NVJPGA_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_DEFAULT                        MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_NVJPGA_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_NVJPGA_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_NVJPGA_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_NVJPGA_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_NVJPGA_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_NVJPGA_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_INIT_ENUM                      ON
#define PMC_IMPL_PART_NVJPGA_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_OFF                    MK_ENUM_CONST(0)
#define PMC_IMPL_PART_NVJPGA_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_ON                     MK_ENUM_CONST(1)


// Register PMC_IMPL_PART_NVJPGA_CLAMP_CONTROL_0
#define PMC_IMPL_PART_NVJPGA_CLAMP_CONTROL_0                    MK_ADDR_CONST(0x4e0)
#define PMC_IMPL_PART_NVJPGA_CLAMP_CONTROL_0_SECURE                     0x0
#define PMC_IMPL_PART_NVJPGA_CLAMP_CONTROL_0_DUAL                       0x0
#define PMC_IMPL_PART_NVJPGA_CLAMP_CONTROL_0_SCR                        PG_NVJPGA_SCR_0
#define PMC_IMPL_PART_NVJPGA_CLAMP_CONTROL_0_SCRREG                     PMC_IMPL_SCR_PG_NVJPGA_SCR_0
#define PMC_IMPL_PART_NVJPGA_CLAMP_CONTROL_0_WORD_COUNT                         0x1
#define PMC_IMPL_PART_NVJPGA_CLAMP_CONTROL_0_RESET_VAL                  MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_NVJPGA_CLAMP_CONTROL_0_RESET_MASK                         MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_NVJPGA_CLAMP_CONTROL_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_NVJPGA_CLAMP_CONTROL_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_NVJPGA_CLAMP_CONTROL_0_READ_MASK                  MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_NVJPGA_CLAMP_CONTROL_0_WRITE_MASK                         MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_NVJPGA_CLAMP_CONTROL_0_CLAMP_SHIFT                        MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_NVJPGA_CLAMP_CONTROL_0_CLAMP_FIELD                        MK_FIELD_CONST(0x1, PMC_IMPL_PART_NVJPGA_CLAMP_CONTROL_0_CLAMP_SHIFT)
#define PMC_IMPL_PART_NVJPGA_CLAMP_CONTROL_0_CLAMP_RANGE                        0:0
#define PMC_IMPL_PART_NVJPGA_CLAMP_CONTROL_0_CLAMP_MSB                  MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_NVJPGA_CLAMP_CONTROL_0_CLAMP_LSB                  MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_NVJPGA_CLAMP_CONTROL_0_CLAMP_WOFFSET                      0x0
#define PMC_IMPL_PART_NVJPGA_CLAMP_CONTROL_0_CLAMP_DEFAULT                      MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_NVJPGA_CLAMP_CONTROL_0_CLAMP_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_NVJPGA_CLAMP_CONTROL_0_CLAMP_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_NVJPGA_CLAMP_CONTROL_0_CLAMP_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_NVJPGA_CLAMP_CONTROL_0_CLAMP_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_NVJPGA_CLAMP_CONTROL_0_CLAMP_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_NVJPGA_CLAMP_CONTROL_0_CLAMP_INIT_ENUM                    ON
#define PMC_IMPL_PART_NVJPGA_CLAMP_CONTROL_0_CLAMP_OFF                  MK_ENUM_CONST(0)
#define PMC_IMPL_PART_NVJPGA_CLAMP_CONTROL_0_CLAMP_ON                   MK_ENUM_CONST(1)


// Register PMC_IMPL_PART_NVJPGB_POWER_GATE_CONTROL_0
#define PMC_IMPL_PART_NVJPGB_POWER_GATE_CONTROL_0                       MK_ADDR_CONST(0x4e4)
#define PMC_IMPL_PART_NVJPGB_POWER_GATE_CONTROL_0_SECURE                        0x0
#define PMC_IMPL_PART_NVJPGB_POWER_GATE_CONTROL_0_DUAL                  0x0
#define PMC_IMPL_PART_NVJPGB_POWER_GATE_CONTROL_0_SCR                   PG_NVJPGB_SCR_0
#define PMC_IMPL_PART_NVJPGB_POWER_GATE_CONTROL_0_SCRREG                        PMC_IMPL_SCR_PG_NVJPGB_SCR_0
#define PMC_IMPL_PART_NVJPGB_POWER_GATE_CONTROL_0_WORD_COUNT                    0x1
#define PMC_IMPL_PART_NVJPGB_POWER_GATE_CONTROL_0_RESET_VAL                     MK_MASK_CONST(0x80000005)
#define PMC_IMPL_PART_NVJPGB_POWER_GATE_CONTROL_0_RESET_MASK                    MK_MASK_CONST(0x80000107)
#define PMC_IMPL_PART_NVJPGB_POWER_GATE_CONTROL_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_NVJPGB_POWER_GATE_CONTROL_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_NVJPGB_POWER_GATE_CONTROL_0_READ_MASK                     MK_MASK_CONST(0x80000107)
#define PMC_IMPL_PART_NVJPGB_POWER_GATE_CONTROL_0_WRITE_MASK                    MK_MASK_CONST(0x80000105)
#define PMC_IMPL_PART_NVJPGB_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SHIFT                     MK_SHIFT_CONST(31)
#define PMC_IMPL_PART_NVJPGB_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_FIELD                     MK_FIELD_CONST(0x1, PMC_IMPL_PART_NVJPGB_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SHIFT)
#define PMC_IMPL_PART_NVJPGB_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_RANGE                     31:31
#define PMC_IMPL_PART_NVJPGB_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_MSB                       MK_SHIFT_CONST(31)
#define PMC_IMPL_PART_NVJPGB_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_LSB                       MK_SHIFT_CONST(31)
#define PMC_IMPL_PART_NVJPGB_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_WOFFSET                   0x0
#define PMC_IMPL_PART_NVJPGB_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_DEFAULT                   MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_NVJPGB_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_NVJPGB_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_NVJPGB_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_NVJPGB_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_NVJPGB_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_NVJPGB_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_INIT_ENUM                 ENABLE
#define PMC_IMPL_PART_NVJPGB_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_DISABLE                   MK_ENUM_CONST(0)
#define PMC_IMPL_PART_NVJPGB_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_ENABLE                    MK_ENUM_CONST(1)

#define PMC_IMPL_PART_NVJPGB_POWER_GATE_CONTROL_0_START_SHIFT                   MK_SHIFT_CONST(8)
#define PMC_IMPL_PART_NVJPGB_POWER_GATE_CONTROL_0_START_FIELD                   MK_FIELD_CONST(0x1, PMC_IMPL_PART_NVJPGB_POWER_GATE_CONTROL_0_START_SHIFT)
#define PMC_IMPL_PART_NVJPGB_POWER_GATE_CONTROL_0_START_RANGE                   8:8
#define PMC_IMPL_PART_NVJPGB_POWER_GATE_CONTROL_0_START_MSB                     MK_SHIFT_CONST(8)
#define PMC_IMPL_PART_NVJPGB_POWER_GATE_CONTROL_0_START_LSB                     MK_SHIFT_CONST(8)
#define PMC_IMPL_PART_NVJPGB_POWER_GATE_CONTROL_0_START_WOFFSET                 0x0
#define PMC_IMPL_PART_NVJPGB_POWER_GATE_CONTROL_0_START_DEFAULT                 MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_NVJPGB_POWER_GATE_CONTROL_0_START_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_NVJPGB_POWER_GATE_CONTROL_0_START_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_NVJPGB_POWER_GATE_CONTROL_0_START_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_NVJPGB_POWER_GATE_CONTROL_0_START_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_NVJPGB_POWER_GATE_CONTROL_0_START_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_NVJPGB_POWER_GATE_CONTROL_0_START_INIT_ENUM                       DONE
#define PMC_IMPL_PART_NVJPGB_POWER_GATE_CONTROL_0_START_DONE                    MK_ENUM_CONST(0)
#define PMC_IMPL_PART_NVJPGB_POWER_GATE_CONTROL_0_START_PENDING                 MK_ENUM_CONST(1)

#define PMC_IMPL_PART_NVJPGB_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SHIFT                   MK_SHIFT_CONST(2)
#define PMC_IMPL_PART_NVJPGB_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_FIELD                   MK_FIELD_CONST(0x1, PMC_IMPL_PART_NVJPGB_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SHIFT)
#define PMC_IMPL_PART_NVJPGB_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_RANGE                   2:2
#define PMC_IMPL_PART_NVJPGB_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_MSB                     MK_SHIFT_CONST(2)
#define PMC_IMPL_PART_NVJPGB_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_LSB                     MK_SHIFT_CONST(2)
#define PMC_IMPL_PART_NVJPGB_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_WOFFSET                 0x0
#define PMC_IMPL_PART_NVJPGB_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_DEFAULT                 MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_NVJPGB_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_NVJPGB_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_NVJPGB_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_NVJPGB_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_NVJPGB_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_NVJPGB_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_INIT_ENUM                       ON
#define PMC_IMPL_PART_NVJPGB_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_OFF                     MK_ENUM_CONST(0)
#define PMC_IMPL_PART_NVJPGB_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_ON                      MK_ENUM_CONST(1)

#define PMC_IMPL_PART_NVJPGB_POWER_GATE_CONTROL_0_SRAM_RET_EN_SHIFT                     MK_SHIFT_CONST(1)
#define PMC_IMPL_PART_NVJPGB_POWER_GATE_CONTROL_0_SRAM_RET_EN_FIELD                     MK_FIELD_CONST(0x1, PMC_IMPL_PART_NVJPGB_POWER_GATE_CONTROL_0_SRAM_RET_EN_SHIFT)
#define PMC_IMPL_PART_NVJPGB_POWER_GATE_CONTROL_0_SRAM_RET_EN_RANGE                     1:1
#define PMC_IMPL_PART_NVJPGB_POWER_GATE_CONTROL_0_SRAM_RET_EN_MSB                       MK_SHIFT_CONST(1)
#define PMC_IMPL_PART_NVJPGB_POWER_GATE_CONTROL_0_SRAM_RET_EN_LSB                       MK_SHIFT_CONST(1)
#define PMC_IMPL_PART_NVJPGB_POWER_GATE_CONTROL_0_SRAM_RET_EN_WOFFSET                   0x0
#define PMC_IMPL_PART_NVJPGB_POWER_GATE_CONTROL_0_SRAM_RET_EN_DEFAULT                   MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_NVJPGB_POWER_GATE_CONTROL_0_SRAM_RET_EN_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_NVJPGB_POWER_GATE_CONTROL_0_SRAM_RET_EN_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_NVJPGB_POWER_GATE_CONTROL_0_SRAM_RET_EN_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_NVJPGB_POWER_GATE_CONTROL_0_SRAM_RET_EN_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_NVJPGB_POWER_GATE_CONTROL_0_SRAM_RET_EN_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_NVJPGB_POWER_GATE_CONTROL_0_SRAM_RET_EN_INIT_ENUM                 OFF
#define PMC_IMPL_PART_NVJPGB_POWER_GATE_CONTROL_0_SRAM_RET_EN_OFF                       MK_ENUM_CONST(0)
#define PMC_IMPL_PART_NVJPGB_POWER_GATE_CONTROL_0_SRAM_RET_EN_ON                        MK_ENUM_CONST(1)

#define PMC_IMPL_PART_NVJPGB_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SHIFT                     MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_NVJPGB_POWER_GATE_CONTROL_0_LOGIC_SLEEP_FIELD                     MK_FIELD_CONST(0x1, PMC_IMPL_PART_NVJPGB_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SHIFT)
#define PMC_IMPL_PART_NVJPGB_POWER_GATE_CONTROL_0_LOGIC_SLEEP_RANGE                     0:0
#define PMC_IMPL_PART_NVJPGB_POWER_GATE_CONTROL_0_LOGIC_SLEEP_MSB                       MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_NVJPGB_POWER_GATE_CONTROL_0_LOGIC_SLEEP_LSB                       MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_NVJPGB_POWER_GATE_CONTROL_0_LOGIC_SLEEP_WOFFSET                   0x0
#define PMC_IMPL_PART_NVJPGB_POWER_GATE_CONTROL_0_LOGIC_SLEEP_DEFAULT                   MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_NVJPGB_POWER_GATE_CONTROL_0_LOGIC_SLEEP_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_NVJPGB_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_NVJPGB_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_NVJPGB_POWER_GATE_CONTROL_0_LOGIC_SLEEP_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_NVJPGB_POWER_GATE_CONTROL_0_LOGIC_SLEEP_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_NVJPGB_POWER_GATE_CONTROL_0_LOGIC_SLEEP_INIT_ENUM                 ON
#define PMC_IMPL_PART_NVJPGB_POWER_GATE_CONTROL_0_LOGIC_SLEEP_OFF                       MK_ENUM_CONST(0)
#define PMC_IMPL_PART_NVJPGB_POWER_GATE_CONTROL_0_LOGIC_SLEEP_ON                        MK_ENUM_CONST(1)


// Register PMC_IMPL_PART_NVJPGB_POWER_GATE_STATUS_0
#define PMC_IMPL_PART_NVJPGB_POWER_GATE_STATUS_0                        MK_ADDR_CONST(0x4e8)
#define PMC_IMPL_PART_NVJPGB_POWER_GATE_STATUS_0_SECURE                         0x0
#define PMC_IMPL_PART_NVJPGB_POWER_GATE_STATUS_0_DUAL                   0x0
#define PMC_IMPL_PART_NVJPGB_POWER_GATE_STATUS_0_SCR                    PG_NVJPGB_SCR_0
#define PMC_IMPL_PART_NVJPGB_POWER_GATE_STATUS_0_SCRREG                         PMC_IMPL_SCR_PG_NVJPGB_SCR_0
#define PMC_IMPL_PART_NVJPGB_POWER_GATE_STATUS_0_WORD_COUNT                     0x1
#define PMC_IMPL_PART_NVJPGB_POWER_GATE_STATUS_0_RESET_VAL                      MK_MASK_CONST(0x5)
#define PMC_IMPL_PART_NVJPGB_POWER_GATE_STATUS_0_RESET_MASK                     MK_MASK_CONST(0x7)
#define PMC_IMPL_PART_NVJPGB_POWER_GATE_STATUS_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_NVJPGB_POWER_GATE_STATUS_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_NVJPGB_POWER_GATE_STATUS_0_READ_MASK                      MK_MASK_CONST(0x7)
#define PMC_IMPL_PART_NVJPGB_POWER_GATE_STATUS_0_WRITE_MASK                     MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_NVJPGB_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SHIFT                   MK_SHIFT_CONST(2)
#define PMC_IMPL_PART_NVJPGB_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_FIELD                   MK_FIELD_CONST(0x1, PMC_IMPL_PART_NVJPGB_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SHIFT)
#define PMC_IMPL_PART_NVJPGB_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_RANGE                   2:2
#define PMC_IMPL_PART_NVJPGB_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_MSB                     MK_SHIFT_CONST(2)
#define PMC_IMPL_PART_NVJPGB_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_LSB                     MK_SHIFT_CONST(2)
#define PMC_IMPL_PART_NVJPGB_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_WOFFSET                 0x0
#define PMC_IMPL_PART_NVJPGB_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_DEFAULT                 MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_NVJPGB_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_NVJPGB_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_NVJPGB_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_NVJPGB_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_NVJPGB_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_NVJPGB_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_INIT_ENUM                       ON
#define PMC_IMPL_PART_NVJPGB_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_OFF                     MK_ENUM_CONST(0)
#define PMC_IMPL_PART_NVJPGB_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_ON                      MK_ENUM_CONST(1)

#define PMC_IMPL_PART_NVJPGB_POWER_GATE_STATUS_0_SRAM_RET_STS_SHIFT                     MK_SHIFT_CONST(1)
#define PMC_IMPL_PART_NVJPGB_POWER_GATE_STATUS_0_SRAM_RET_STS_FIELD                     MK_FIELD_CONST(0x1, PMC_IMPL_PART_NVJPGB_POWER_GATE_STATUS_0_SRAM_RET_STS_SHIFT)
#define PMC_IMPL_PART_NVJPGB_POWER_GATE_STATUS_0_SRAM_RET_STS_RANGE                     1:1
#define PMC_IMPL_PART_NVJPGB_POWER_GATE_STATUS_0_SRAM_RET_STS_MSB                       MK_SHIFT_CONST(1)
#define PMC_IMPL_PART_NVJPGB_POWER_GATE_STATUS_0_SRAM_RET_STS_LSB                       MK_SHIFT_CONST(1)
#define PMC_IMPL_PART_NVJPGB_POWER_GATE_STATUS_0_SRAM_RET_STS_WOFFSET                   0x0
#define PMC_IMPL_PART_NVJPGB_POWER_GATE_STATUS_0_SRAM_RET_STS_DEFAULT                   MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_NVJPGB_POWER_GATE_STATUS_0_SRAM_RET_STS_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_NVJPGB_POWER_GATE_STATUS_0_SRAM_RET_STS_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_NVJPGB_POWER_GATE_STATUS_0_SRAM_RET_STS_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_NVJPGB_POWER_GATE_STATUS_0_SRAM_RET_STS_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_NVJPGB_POWER_GATE_STATUS_0_SRAM_RET_STS_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_NVJPGB_POWER_GATE_STATUS_0_SRAM_RET_STS_INIT_ENUM                 OFF
#define PMC_IMPL_PART_NVJPGB_POWER_GATE_STATUS_0_SRAM_RET_STS_OFF                       MK_ENUM_CONST(0)
#define PMC_IMPL_PART_NVJPGB_POWER_GATE_STATUS_0_SRAM_RET_STS_ON                        MK_ENUM_CONST(1)

#define PMC_IMPL_PART_NVJPGB_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SHIFT                  MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_NVJPGB_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_FIELD                  MK_FIELD_CONST(0x1, PMC_IMPL_PART_NVJPGB_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SHIFT)
#define PMC_IMPL_PART_NVJPGB_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_RANGE                  0:0
#define PMC_IMPL_PART_NVJPGB_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_MSB                    MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_NVJPGB_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_LSB                    MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_NVJPGB_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_WOFFSET                        0x0
#define PMC_IMPL_PART_NVJPGB_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_DEFAULT                        MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_NVJPGB_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_NVJPGB_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_NVJPGB_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_NVJPGB_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_NVJPGB_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_NVJPGB_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_INIT_ENUM                      ON
#define PMC_IMPL_PART_NVJPGB_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_OFF                    MK_ENUM_CONST(0)
#define PMC_IMPL_PART_NVJPGB_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_ON                     MK_ENUM_CONST(1)


// Register PMC_IMPL_PART_NVJPGB_CLAMP_CONTROL_0
#define PMC_IMPL_PART_NVJPGB_CLAMP_CONTROL_0                    MK_ADDR_CONST(0x4ec)
#define PMC_IMPL_PART_NVJPGB_CLAMP_CONTROL_0_SECURE                     0x0
#define PMC_IMPL_PART_NVJPGB_CLAMP_CONTROL_0_DUAL                       0x0
#define PMC_IMPL_PART_NVJPGB_CLAMP_CONTROL_0_SCR                        PG_NVJPGB_SCR_0
#define PMC_IMPL_PART_NVJPGB_CLAMP_CONTROL_0_SCRREG                     PMC_IMPL_SCR_PG_NVJPGB_SCR_0
#define PMC_IMPL_PART_NVJPGB_CLAMP_CONTROL_0_WORD_COUNT                         0x1
#define PMC_IMPL_PART_NVJPGB_CLAMP_CONTROL_0_RESET_VAL                  MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_NVJPGB_CLAMP_CONTROL_0_RESET_MASK                         MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_NVJPGB_CLAMP_CONTROL_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_NVJPGB_CLAMP_CONTROL_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_NVJPGB_CLAMP_CONTROL_0_READ_MASK                  MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_NVJPGB_CLAMP_CONTROL_0_WRITE_MASK                         MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_NVJPGB_CLAMP_CONTROL_0_CLAMP_SHIFT                        MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_NVJPGB_CLAMP_CONTROL_0_CLAMP_FIELD                        MK_FIELD_CONST(0x1, PMC_IMPL_PART_NVJPGB_CLAMP_CONTROL_0_CLAMP_SHIFT)
#define PMC_IMPL_PART_NVJPGB_CLAMP_CONTROL_0_CLAMP_RANGE                        0:0
#define PMC_IMPL_PART_NVJPGB_CLAMP_CONTROL_0_CLAMP_MSB                  MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_NVJPGB_CLAMP_CONTROL_0_CLAMP_LSB                  MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_NVJPGB_CLAMP_CONTROL_0_CLAMP_WOFFSET                      0x0
#define PMC_IMPL_PART_NVJPGB_CLAMP_CONTROL_0_CLAMP_DEFAULT                      MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_NVJPGB_CLAMP_CONTROL_0_CLAMP_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_NVJPGB_CLAMP_CONTROL_0_CLAMP_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_NVJPGB_CLAMP_CONTROL_0_CLAMP_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_NVJPGB_CLAMP_CONTROL_0_CLAMP_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_NVJPGB_CLAMP_CONTROL_0_CLAMP_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_NVJPGB_CLAMP_CONTROL_0_CLAMP_INIT_ENUM                    ON
#define PMC_IMPL_PART_NVJPGB_CLAMP_CONTROL_0_CLAMP_OFF                  MK_ENUM_CONST(0)
#define PMC_IMPL_PART_NVJPGB_CLAMP_CONTROL_0_CLAMP_ON                   MK_ENUM_CONST(1)


// Register PMC_IMPL_PART_NVENC_POWER_GATE_CONTROL_0
#define PMC_IMPL_PART_NVENC_POWER_GATE_CONTROL_0                        MK_ADDR_CONST(0x4f0)
#define PMC_IMPL_PART_NVENC_POWER_GATE_CONTROL_0_SECURE                         0x0
#define PMC_IMPL_PART_NVENC_POWER_GATE_CONTROL_0_DUAL                   0x0
#define PMC_IMPL_PART_NVENC_POWER_GATE_CONTROL_0_SCR                    PG_NVENC_SCR_0
#define PMC_IMPL_PART_NVENC_POWER_GATE_CONTROL_0_SCRREG                         PMC_IMPL_SCR_PG_NVENC_SCR_0
#define PMC_IMPL_PART_NVENC_POWER_GATE_CONTROL_0_WORD_COUNT                     0x1
#define PMC_IMPL_PART_NVENC_POWER_GATE_CONTROL_0_RESET_VAL                      MK_MASK_CONST(0x80000005)
#define PMC_IMPL_PART_NVENC_POWER_GATE_CONTROL_0_RESET_MASK                     MK_MASK_CONST(0x80000107)
#define PMC_IMPL_PART_NVENC_POWER_GATE_CONTROL_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_NVENC_POWER_GATE_CONTROL_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_NVENC_POWER_GATE_CONTROL_0_READ_MASK                      MK_MASK_CONST(0x80000107)
#define PMC_IMPL_PART_NVENC_POWER_GATE_CONTROL_0_WRITE_MASK                     MK_MASK_CONST(0x80000105)
#define PMC_IMPL_PART_NVENC_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SHIFT                      MK_SHIFT_CONST(31)
#define PMC_IMPL_PART_NVENC_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_FIELD                      MK_FIELD_CONST(0x1, PMC_IMPL_PART_NVENC_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SHIFT)
#define PMC_IMPL_PART_NVENC_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_RANGE                      31:31
#define PMC_IMPL_PART_NVENC_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_MSB                        MK_SHIFT_CONST(31)
#define PMC_IMPL_PART_NVENC_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_LSB                        MK_SHIFT_CONST(31)
#define PMC_IMPL_PART_NVENC_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_WOFFSET                    0x0
#define PMC_IMPL_PART_NVENC_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_DEFAULT                    MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_NVENC_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_NVENC_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_NVENC_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_NVENC_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_NVENC_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_NVENC_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_INIT_ENUM                  ENABLE
#define PMC_IMPL_PART_NVENC_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_DISABLE                    MK_ENUM_CONST(0)
#define PMC_IMPL_PART_NVENC_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_ENABLE                     MK_ENUM_CONST(1)

#define PMC_IMPL_PART_NVENC_POWER_GATE_CONTROL_0_START_SHIFT                    MK_SHIFT_CONST(8)
#define PMC_IMPL_PART_NVENC_POWER_GATE_CONTROL_0_START_FIELD                    MK_FIELD_CONST(0x1, PMC_IMPL_PART_NVENC_POWER_GATE_CONTROL_0_START_SHIFT)
#define PMC_IMPL_PART_NVENC_POWER_GATE_CONTROL_0_START_RANGE                    8:8
#define PMC_IMPL_PART_NVENC_POWER_GATE_CONTROL_0_START_MSB                      MK_SHIFT_CONST(8)
#define PMC_IMPL_PART_NVENC_POWER_GATE_CONTROL_0_START_LSB                      MK_SHIFT_CONST(8)
#define PMC_IMPL_PART_NVENC_POWER_GATE_CONTROL_0_START_WOFFSET                  0x0
#define PMC_IMPL_PART_NVENC_POWER_GATE_CONTROL_0_START_DEFAULT                  MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_NVENC_POWER_GATE_CONTROL_0_START_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_NVENC_POWER_GATE_CONTROL_0_START_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_NVENC_POWER_GATE_CONTROL_0_START_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_NVENC_POWER_GATE_CONTROL_0_START_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_NVENC_POWER_GATE_CONTROL_0_START_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_NVENC_POWER_GATE_CONTROL_0_START_INIT_ENUM                        DONE
#define PMC_IMPL_PART_NVENC_POWER_GATE_CONTROL_0_START_DONE                     MK_ENUM_CONST(0)
#define PMC_IMPL_PART_NVENC_POWER_GATE_CONTROL_0_START_PENDING                  MK_ENUM_CONST(1)

#define PMC_IMPL_PART_NVENC_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SHIFT                    MK_SHIFT_CONST(2)
#define PMC_IMPL_PART_NVENC_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_FIELD                    MK_FIELD_CONST(0x1, PMC_IMPL_PART_NVENC_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SHIFT)
#define PMC_IMPL_PART_NVENC_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_RANGE                    2:2
#define PMC_IMPL_PART_NVENC_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_MSB                      MK_SHIFT_CONST(2)
#define PMC_IMPL_PART_NVENC_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_LSB                      MK_SHIFT_CONST(2)
#define PMC_IMPL_PART_NVENC_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_WOFFSET                  0x0
#define PMC_IMPL_PART_NVENC_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_DEFAULT                  MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_NVENC_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_NVENC_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_NVENC_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_NVENC_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_NVENC_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_NVENC_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_INIT_ENUM                        ON
#define PMC_IMPL_PART_NVENC_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_OFF                      MK_ENUM_CONST(0)
#define PMC_IMPL_PART_NVENC_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_ON                       MK_ENUM_CONST(1)

#define PMC_IMPL_PART_NVENC_POWER_GATE_CONTROL_0_SRAM_RET_EN_SHIFT                      MK_SHIFT_CONST(1)
#define PMC_IMPL_PART_NVENC_POWER_GATE_CONTROL_0_SRAM_RET_EN_FIELD                      MK_FIELD_CONST(0x1, PMC_IMPL_PART_NVENC_POWER_GATE_CONTROL_0_SRAM_RET_EN_SHIFT)
#define PMC_IMPL_PART_NVENC_POWER_GATE_CONTROL_0_SRAM_RET_EN_RANGE                      1:1
#define PMC_IMPL_PART_NVENC_POWER_GATE_CONTROL_0_SRAM_RET_EN_MSB                        MK_SHIFT_CONST(1)
#define PMC_IMPL_PART_NVENC_POWER_GATE_CONTROL_0_SRAM_RET_EN_LSB                        MK_SHIFT_CONST(1)
#define PMC_IMPL_PART_NVENC_POWER_GATE_CONTROL_0_SRAM_RET_EN_WOFFSET                    0x0
#define PMC_IMPL_PART_NVENC_POWER_GATE_CONTROL_0_SRAM_RET_EN_DEFAULT                    MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_NVENC_POWER_GATE_CONTROL_0_SRAM_RET_EN_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_NVENC_POWER_GATE_CONTROL_0_SRAM_RET_EN_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_NVENC_POWER_GATE_CONTROL_0_SRAM_RET_EN_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_NVENC_POWER_GATE_CONTROL_0_SRAM_RET_EN_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_NVENC_POWER_GATE_CONTROL_0_SRAM_RET_EN_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_NVENC_POWER_GATE_CONTROL_0_SRAM_RET_EN_INIT_ENUM                  OFF
#define PMC_IMPL_PART_NVENC_POWER_GATE_CONTROL_0_SRAM_RET_EN_OFF                        MK_ENUM_CONST(0)
#define PMC_IMPL_PART_NVENC_POWER_GATE_CONTROL_0_SRAM_RET_EN_ON                 MK_ENUM_CONST(1)

#define PMC_IMPL_PART_NVENC_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SHIFT                      MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_NVENC_POWER_GATE_CONTROL_0_LOGIC_SLEEP_FIELD                      MK_FIELD_CONST(0x1, PMC_IMPL_PART_NVENC_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SHIFT)
#define PMC_IMPL_PART_NVENC_POWER_GATE_CONTROL_0_LOGIC_SLEEP_RANGE                      0:0
#define PMC_IMPL_PART_NVENC_POWER_GATE_CONTROL_0_LOGIC_SLEEP_MSB                        MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_NVENC_POWER_GATE_CONTROL_0_LOGIC_SLEEP_LSB                        MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_NVENC_POWER_GATE_CONTROL_0_LOGIC_SLEEP_WOFFSET                    0x0
#define PMC_IMPL_PART_NVENC_POWER_GATE_CONTROL_0_LOGIC_SLEEP_DEFAULT                    MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_NVENC_POWER_GATE_CONTROL_0_LOGIC_SLEEP_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_NVENC_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_NVENC_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_NVENC_POWER_GATE_CONTROL_0_LOGIC_SLEEP_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_NVENC_POWER_GATE_CONTROL_0_LOGIC_SLEEP_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_NVENC_POWER_GATE_CONTROL_0_LOGIC_SLEEP_INIT_ENUM                  ON
#define PMC_IMPL_PART_NVENC_POWER_GATE_CONTROL_0_LOGIC_SLEEP_OFF                        MK_ENUM_CONST(0)
#define PMC_IMPL_PART_NVENC_POWER_GATE_CONTROL_0_LOGIC_SLEEP_ON                 MK_ENUM_CONST(1)


// Register PMC_IMPL_PART_NVENC_POWER_GATE_STATUS_0
#define PMC_IMPL_PART_NVENC_POWER_GATE_STATUS_0                 MK_ADDR_CONST(0x4f4)
#define PMC_IMPL_PART_NVENC_POWER_GATE_STATUS_0_SECURE                  0x0
#define PMC_IMPL_PART_NVENC_POWER_GATE_STATUS_0_DUAL                    0x0
#define PMC_IMPL_PART_NVENC_POWER_GATE_STATUS_0_SCR                     PG_NVENC_SCR_0
#define PMC_IMPL_PART_NVENC_POWER_GATE_STATUS_0_SCRREG                  PMC_IMPL_SCR_PG_NVENC_SCR_0
#define PMC_IMPL_PART_NVENC_POWER_GATE_STATUS_0_WORD_COUNT                      0x1
#define PMC_IMPL_PART_NVENC_POWER_GATE_STATUS_0_RESET_VAL                       MK_MASK_CONST(0x5)
#define PMC_IMPL_PART_NVENC_POWER_GATE_STATUS_0_RESET_MASK                      MK_MASK_CONST(0x7)
#define PMC_IMPL_PART_NVENC_POWER_GATE_STATUS_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_NVENC_POWER_GATE_STATUS_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_NVENC_POWER_GATE_STATUS_0_READ_MASK                       MK_MASK_CONST(0x7)
#define PMC_IMPL_PART_NVENC_POWER_GATE_STATUS_0_WRITE_MASK                      MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_NVENC_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SHIFT                    MK_SHIFT_CONST(2)
#define PMC_IMPL_PART_NVENC_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_FIELD                    MK_FIELD_CONST(0x1, PMC_IMPL_PART_NVENC_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SHIFT)
#define PMC_IMPL_PART_NVENC_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_RANGE                    2:2
#define PMC_IMPL_PART_NVENC_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_MSB                      MK_SHIFT_CONST(2)
#define PMC_IMPL_PART_NVENC_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_LSB                      MK_SHIFT_CONST(2)
#define PMC_IMPL_PART_NVENC_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_WOFFSET                  0x0
#define PMC_IMPL_PART_NVENC_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_DEFAULT                  MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_NVENC_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_NVENC_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_NVENC_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_NVENC_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_NVENC_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_NVENC_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_INIT_ENUM                        ON
#define PMC_IMPL_PART_NVENC_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_OFF                      MK_ENUM_CONST(0)
#define PMC_IMPL_PART_NVENC_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_ON                       MK_ENUM_CONST(1)

#define PMC_IMPL_PART_NVENC_POWER_GATE_STATUS_0_SRAM_RET_STS_SHIFT                      MK_SHIFT_CONST(1)
#define PMC_IMPL_PART_NVENC_POWER_GATE_STATUS_0_SRAM_RET_STS_FIELD                      MK_FIELD_CONST(0x1, PMC_IMPL_PART_NVENC_POWER_GATE_STATUS_0_SRAM_RET_STS_SHIFT)
#define PMC_IMPL_PART_NVENC_POWER_GATE_STATUS_0_SRAM_RET_STS_RANGE                      1:1
#define PMC_IMPL_PART_NVENC_POWER_GATE_STATUS_0_SRAM_RET_STS_MSB                        MK_SHIFT_CONST(1)
#define PMC_IMPL_PART_NVENC_POWER_GATE_STATUS_0_SRAM_RET_STS_LSB                        MK_SHIFT_CONST(1)
#define PMC_IMPL_PART_NVENC_POWER_GATE_STATUS_0_SRAM_RET_STS_WOFFSET                    0x0
#define PMC_IMPL_PART_NVENC_POWER_GATE_STATUS_0_SRAM_RET_STS_DEFAULT                    MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_NVENC_POWER_GATE_STATUS_0_SRAM_RET_STS_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_NVENC_POWER_GATE_STATUS_0_SRAM_RET_STS_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_NVENC_POWER_GATE_STATUS_0_SRAM_RET_STS_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_NVENC_POWER_GATE_STATUS_0_SRAM_RET_STS_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_NVENC_POWER_GATE_STATUS_0_SRAM_RET_STS_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_NVENC_POWER_GATE_STATUS_0_SRAM_RET_STS_INIT_ENUM                  OFF
#define PMC_IMPL_PART_NVENC_POWER_GATE_STATUS_0_SRAM_RET_STS_OFF                        MK_ENUM_CONST(0)
#define PMC_IMPL_PART_NVENC_POWER_GATE_STATUS_0_SRAM_RET_STS_ON                 MK_ENUM_CONST(1)

#define PMC_IMPL_PART_NVENC_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SHIFT                   MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_NVENC_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_FIELD                   MK_FIELD_CONST(0x1, PMC_IMPL_PART_NVENC_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SHIFT)
#define PMC_IMPL_PART_NVENC_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_RANGE                   0:0
#define PMC_IMPL_PART_NVENC_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_MSB                     MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_NVENC_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_LSB                     MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_NVENC_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_WOFFSET                 0x0
#define PMC_IMPL_PART_NVENC_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_DEFAULT                 MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_NVENC_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_NVENC_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_NVENC_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_NVENC_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_NVENC_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_NVENC_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_INIT_ENUM                       ON
#define PMC_IMPL_PART_NVENC_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_OFF                     MK_ENUM_CONST(0)
#define PMC_IMPL_PART_NVENC_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_ON                      MK_ENUM_CONST(1)


// Register PMC_IMPL_PART_NVENC_CLAMP_CONTROL_0
#define PMC_IMPL_PART_NVENC_CLAMP_CONTROL_0                     MK_ADDR_CONST(0x4f8)
#define PMC_IMPL_PART_NVENC_CLAMP_CONTROL_0_SECURE                      0x0
#define PMC_IMPL_PART_NVENC_CLAMP_CONTROL_0_DUAL                        0x0
#define PMC_IMPL_PART_NVENC_CLAMP_CONTROL_0_SCR                         PG_NVENC_SCR_0
#define PMC_IMPL_PART_NVENC_CLAMP_CONTROL_0_SCRREG                      PMC_IMPL_SCR_PG_NVENC_SCR_0
#define PMC_IMPL_PART_NVENC_CLAMP_CONTROL_0_WORD_COUNT                  0x1
#define PMC_IMPL_PART_NVENC_CLAMP_CONTROL_0_RESET_VAL                   MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_NVENC_CLAMP_CONTROL_0_RESET_MASK                  MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_NVENC_CLAMP_CONTROL_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_NVENC_CLAMP_CONTROL_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_NVENC_CLAMP_CONTROL_0_READ_MASK                   MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_NVENC_CLAMP_CONTROL_0_WRITE_MASK                  MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_NVENC_CLAMP_CONTROL_0_CLAMP_SHIFT                 MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_NVENC_CLAMP_CONTROL_0_CLAMP_FIELD                 MK_FIELD_CONST(0x1, PMC_IMPL_PART_NVENC_CLAMP_CONTROL_0_CLAMP_SHIFT)
#define PMC_IMPL_PART_NVENC_CLAMP_CONTROL_0_CLAMP_RANGE                 0:0
#define PMC_IMPL_PART_NVENC_CLAMP_CONTROL_0_CLAMP_MSB                   MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_NVENC_CLAMP_CONTROL_0_CLAMP_LSB                   MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_NVENC_CLAMP_CONTROL_0_CLAMP_WOFFSET                       0x0
#define PMC_IMPL_PART_NVENC_CLAMP_CONTROL_0_CLAMP_DEFAULT                       MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_NVENC_CLAMP_CONTROL_0_CLAMP_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_NVENC_CLAMP_CONTROL_0_CLAMP_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_NVENC_CLAMP_CONTROL_0_CLAMP_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_NVENC_CLAMP_CONTROL_0_CLAMP_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_NVENC_CLAMP_CONTROL_0_CLAMP_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_NVENC_CLAMP_CONTROL_0_CLAMP_INIT_ENUM                     ON
#define PMC_IMPL_PART_NVENC_CLAMP_CONTROL_0_CLAMP_OFF                   MK_ENUM_CONST(0)
#define PMC_IMPL_PART_NVENC_CLAMP_CONTROL_0_CLAMP_ON                    MK_ENUM_CONST(1)


// Register PMC_IMPL_PART_VI_POWER_GATE_CONTROL_0
#define PMC_IMPL_PART_VI_POWER_GATE_CONTROL_0                   MK_ADDR_CONST(0x4fc)
#define PMC_IMPL_PART_VI_POWER_GATE_CONTROL_0_SECURE                    0x0
#define PMC_IMPL_PART_VI_POWER_GATE_CONTROL_0_DUAL                      0x0
#define PMC_IMPL_PART_VI_POWER_GATE_CONTROL_0_SCR                       PG_VI_SCR_0
#define PMC_IMPL_PART_VI_POWER_GATE_CONTROL_0_SCRREG                    PMC_IMPL_SCR_PG_VI_SCR_0
#define PMC_IMPL_PART_VI_POWER_GATE_CONTROL_0_WORD_COUNT                        0x1
#define PMC_IMPL_PART_VI_POWER_GATE_CONTROL_0_RESET_VAL                         MK_MASK_CONST(0x80000005)
#define PMC_IMPL_PART_VI_POWER_GATE_CONTROL_0_RESET_MASK                        MK_MASK_CONST(0x80000107)
#define PMC_IMPL_PART_VI_POWER_GATE_CONTROL_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_VI_POWER_GATE_CONTROL_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_VI_POWER_GATE_CONTROL_0_READ_MASK                         MK_MASK_CONST(0x80000107)
#define PMC_IMPL_PART_VI_POWER_GATE_CONTROL_0_WRITE_MASK                        MK_MASK_CONST(0x80000105)
#define PMC_IMPL_PART_VI_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SHIFT                 MK_SHIFT_CONST(31)
#define PMC_IMPL_PART_VI_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_FIELD                 MK_FIELD_CONST(0x1, PMC_IMPL_PART_VI_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SHIFT)
#define PMC_IMPL_PART_VI_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_RANGE                 31:31
#define PMC_IMPL_PART_VI_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_MSB                   MK_SHIFT_CONST(31)
#define PMC_IMPL_PART_VI_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_LSB                   MK_SHIFT_CONST(31)
#define PMC_IMPL_PART_VI_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_WOFFSET                       0x0
#define PMC_IMPL_PART_VI_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_DEFAULT                       MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_VI_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_VI_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_VI_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_VI_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_VI_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_VI_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_INIT_ENUM                     ENABLE
#define PMC_IMPL_PART_VI_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_DISABLE                       MK_ENUM_CONST(0)
#define PMC_IMPL_PART_VI_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_ENABLE                        MK_ENUM_CONST(1)

#define PMC_IMPL_PART_VI_POWER_GATE_CONTROL_0_START_SHIFT                       MK_SHIFT_CONST(8)
#define PMC_IMPL_PART_VI_POWER_GATE_CONTROL_0_START_FIELD                       MK_FIELD_CONST(0x1, PMC_IMPL_PART_VI_POWER_GATE_CONTROL_0_START_SHIFT)
#define PMC_IMPL_PART_VI_POWER_GATE_CONTROL_0_START_RANGE                       8:8
#define PMC_IMPL_PART_VI_POWER_GATE_CONTROL_0_START_MSB                 MK_SHIFT_CONST(8)
#define PMC_IMPL_PART_VI_POWER_GATE_CONTROL_0_START_LSB                 MK_SHIFT_CONST(8)
#define PMC_IMPL_PART_VI_POWER_GATE_CONTROL_0_START_WOFFSET                     0x0
#define PMC_IMPL_PART_VI_POWER_GATE_CONTROL_0_START_DEFAULT                     MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_VI_POWER_GATE_CONTROL_0_START_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_VI_POWER_GATE_CONTROL_0_START_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_VI_POWER_GATE_CONTROL_0_START_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_VI_POWER_GATE_CONTROL_0_START_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_VI_POWER_GATE_CONTROL_0_START_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_VI_POWER_GATE_CONTROL_0_START_INIT_ENUM                   DONE
#define PMC_IMPL_PART_VI_POWER_GATE_CONTROL_0_START_DONE                        MK_ENUM_CONST(0)
#define PMC_IMPL_PART_VI_POWER_GATE_CONTROL_0_START_PENDING                     MK_ENUM_CONST(1)

#define PMC_IMPL_PART_VI_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SHIFT                       MK_SHIFT_CONST(2)
#define PMC_IMPL_PART_VI_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_FIELD                       MK_FIELD_CONST(0x1, PMC_IMPL_PART_VI_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SHIFT)
#define PMC_IMPL_PART_VI_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_RANGE                       2:2
#define PMC_IMPL_PART_VI_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_MSB                 MK_SHIFT_CONST(2)
#define PMC_IMPL_PART_VI_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_LSB                 MK_SHIFT_CONST(2)
#define PMC_IMPL_PART_VI_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_WOFFSET                     0x0
#define PMC_IMPL_PART_VI_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_DEFAULT                     MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_VI_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_VI_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_VI_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_VI_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_VI_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_VI_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_INIT_ENUM                   ON
#define PMC_IMPL_PART_VI_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_OFF                 MK_ENUM_CONST(0)
#define PMC_IMPL_PART_VI_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_ON                  MK_ENUM_CONST(1)

#define PMC_IMPL_PART_VI_POWER_GATE_CONTROL_0_SRAM_RET_EN_SHIFT                 MK_SHIFT_CONST(1)
#define PMC_IMPL_PART_VI_POWER_GATE_CONTROL_0_SRAM_RET_EN_FIELD                 MK_FIELD_CONST(0x1, PMC_IMPL_PART_VI_POWER_GATE_CONTROL_0_SRAM_RET_EN_SHIFT)
#define PMC_IMPL_PART_VI_POWER_GATE_CONTROL_0_SRAM_RET_EN_RANGE                 1:1
#define PMC_IMPL_PART_VI_POWER_GATE_CONTROL_0_SRAM_RET_EN_MSB                   MK_SHIFT_CONST(1)
#define PMC_IMPL_PART_VI_POWER_GATE_CONTROL_0_SRAM_RET_EN_LSB                   MK_SHIFT_CONST(1)
#define PMC_IMPL_PART_VI_POWER_GATE_CONTROL_0_SRAM_RET_EN_WOFFSET                       0x0
#define PMC_IMPL_PART_VI_POWER_GATE_CONTROL_0_SRAM_RET_EN_DEFAULT                       MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_VI_POWER_GATE_CONTROL_0_SRAM_RET_EN_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_VI_POWER_GATE_CONTROL_0_SRAM_RET_EN_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_VI_POWER_GATE_CONTROL_0_SRAM_RET_EN_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_VI_POWER_GATE_CONTROL_0_SRAM_RET_EN_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_VI_POWER_GATE_CONTROL_0_SRAM_RET_EN_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_VI_POWER_GATE_CONTROL_0_SRAM_RET_EN_INIT_ENUM                     OFF
#define PMC_IMPL_PART_VI_POWER_GATE_CONTROL_0_SRAM_RET_EN_OFF                   MK_ENUM_CONST(0)
#define PMC_IMPL_PART_VI_POWER_GATE_CONTROL_0_SRAM_RET_EN_ON                    MK_ENUM_CONST(1)

#define PMC_IMPL_PART_VI_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SHIFT                 MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_VI_POWER_GATE_CONTROL_0_LOGIC_SLEEP_FIELD                 MK_FIELD_CONST(0x1, PMC_IMPL_PART_VI_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SHIFT)
#define PMC_IMPL_PART_VI_POWER_GATE_CONTROL_0_LOGIC_SLEEP_RANGE                 0:0
#define PMC_IMPL_PART_VI_POWER_GATE_CONTROL_0_LOGIC_SLEEP_MSB                   MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_VI_POWER_GATE_CONTROL_0_LOGIC_SLEEP_LSB                   MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_VI_POWER_GATE_CONTROL_0_LOGIC_SLEEP_WOFFSET                       0x0
#define PMC_IMPL_PART_VI_POWER_GATE_CONTROL_0_LOGIC_SLEEP_DEFAULT                       MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_VI_POWER_GATE_CONTROL_0_LOGIC_SLEEP_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_VI_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_VI_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_VI_POWER_GATE_CONTROL_0_LOGIC_SLEEP_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_VI_POWER_GATE_CONTROL_0_LOGIC_SLEEP_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_VI_POWER_GATE_CONTROL_0_LOGIC_SLEEP_INIT_ENUM                     ON
#define PMC_IMPL_PART_VI_POWER_GATE_CONTROL_0_LOGIC_SLEEP_OFF                   MK_ENUM_CONST(0)
#define PMC_IMPL_PART_VI_POWER_GATE_CONTROL_0_LOGIC_SLEEP_ON                    MK_ENUM_CONST(1)


// Register PMC_IMPL_PART_VI_POWER_GATE_STATUS_0
#define PMC_IMPL_PART_VI_POWER_GATE_STATUS_0                    MK_ADDR_CONST(0x500)
#define PMC_IMPL_PART_VI_POWER_GATE_STATUS_0_SECURE                     0x0
#define PMC_IMPL_PART_VI_POWER_GATE_STATUS_0_DUAL                       0x0
#define PMC_IMPL_PART_VI_POWER_GATE_STATUS_0_SCR                        PG_VI_SCR_0
#define PMC_IMPL_PART_VI_POWER_GATE_STATUS_0_SCRREG                     PMC_IMPL_SCR_PG_VI_SCR_0
#define PMC_IMPL_PART_VI_POWER_GATE_STATUS_0_WORD_COUNT                         0x1
#define PMC_IMPL_PART_VI_POWER_GATE_STATUS_0_RESET_VAL                  MK_MASK_CONST(0x5)
#define PMC_IMPL_PART_VI_POWER_GATE_STATUS_0_RESET_MASK                         MK_MASK_CONST(0x7)
#define PMC_IMPL_PART_VI_POWER_GATE_STATUS_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_VI_POWER_GATE_STATUS_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_VI_POWER_GATE_STATUS_0_READ_MASK                  MK_MASK_CONST(0x7)
#define PMC_IMPL_PART_VI_POWER_GATE_STATUS_0_WRITE_MASK                         MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_VI_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SHIFT                       MK_SHIFT_CONST(2)
#define PMC_IMPL_PART_VI_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_FIELD                       MK_FIELD_CONST(0x1, PMC_IMPL_PART_VI_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SHIFT)
#define PMC_IMPL_PART_VI_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_RANGE                       2:2
#define PMC_IMPL_PART_VI_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_MSB                 MK_SHIFT_CONST(2)
#define PMC_IMPL_PART_VI_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_LSB                 MK_SHIFT_CONST(2)
#define PMC_IMPL_PART_VI_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_WOFFSET                     0x0
#define PMC_IMPL_PART_VI_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_DEFAULT                     MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_VI_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_VI_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_VI_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_VI_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_VI_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_VI_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_INIT_ENUM                   ON
#define PMC_IMPL_PART_VI_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_OFF                 MK_ENUM_CONST(0)
#define PMC_IMPL_PART_VI_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_ON                  MK_ENUM_CONST(1)

#define PMC_IMPL_PART_VI_POWER_GATE_STATUS_0_SRAM_RET_STS_SHIFT                 MK_SHIFT_CONST(1)
#define PMC_IMPL_PART_VI_POWER_GATE_STATUS_0_SRAM_RET_STS_FIELD                 MK_FIELD_CONST(0x1, PMC_IMPL_PART_VI_POWER_GATE_STATUS_0_SRAM_RET_STS_SHIFT)
#define PMC_IMPL_PART_VI_POWER_GATE_STATUS_0_SRAM_RET_STS_RANGE                 1:1
#define PMC_IMPL_PART_VI_POWER_GATE_STATUS_0_SRAM_RET_STS_MSB                   MK_SHIFT_CONST(1)
#define PMC_IMPL_PART_VI_POWER_GATE_STATUS_0_SRAM_RET_STS_LSB                   MK_SHIFT_CONST(1)
#define PMC_IMPL_PART_VI_POWER_GATE_STATUS_0_SRAM_RET_STS_WOFFSET                       0x0
#define PMC_IMPL_PART_VI_POWER_GATE_STATUS_0_SRAM_RET_STS_DEFAULT                       MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_VI_POWER_GATE_STATUS_0_SRAM_RET_STS_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_VI_POWER_GATE_STATUS_0_SRAM_RET_STS_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_VI_POWER_GATE_STATUS_0_SRAM_RET_STS_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_VI_POWER_GATE_STATUS_0_SRAM_RET_STS_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_VI_POWER_GATE_STATUS_0_SRAM_RET_STS_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_VI_POWER_GATE_STATUS_0_SRAM_RET_STS_INIT_ENUM                     OFF
#define PMC_IMPL_PART_VI_POWER_GATE_STATUS_0_SRAM_RET_STS_OFF                   MK_ENUM_CONST(0)
#define PMC_IMPL_PART_VI_POWER_GATE_STATUS_0_SRAM_RET_STS_ON                    MK_ENUM_CONST(1)

#define PMC_IMPL_PART_VI_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SHIFT                      MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_VI_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_FIELD                      MK_FIELD_CONST(0x1, PMC_IMPL_PART_VI_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SHIFT)
#define PMC_IMPL_PART_VI_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_RANGE                      0:0
#define PMC_IMPL_PART_VI_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_MSB                        MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_VI_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_LSB                        MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_VI_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_WOFFSET                    0x0
#define PMC_IMPL_PART_VI_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_DEFAULT                    MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_VI_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_VI_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_VI_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_VI_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_VI_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_VI_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_INIT_ENUM                  ON
#define PMC_IMPL_PART_VI_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_OFF                        MK_ENUM_CONST(0)
#define PMC_IMPL_PART_VI_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_ON                 MK_ENUM_CONST(1)


// Register PMC_IMPL_PART_VI_CLAMP_CONTROL_0
#define PMC_IMPL_PART_VI_CLAMP_CONTROL_0                        MK_ADDR_CONST(0x504)
#define PMC_IMPL_PART_VI_CLAMP_CONTROL_0_SECURE                         0x0
#define PMC_IMPL_PART_VI_CLAMP_CONTROL_0_DUAL                   0x0
#define PMC_IMPL_PART_VI_CLAMP_CONTROL_0_SCR                    PG_VI_SCR_0
#define PMC_IMPL_PART_VI_CLAMP_CONTROL_0_SCRREG                         PMC_IMPL_SCR_PG_VI_SCR_0
#define PMC_IMPL_PART_VI_CLAMP_CONTROL_0_WORD_COUNT                     0x1
#define PMC_IMPL_PART_VI_CLAMP_CONTROL_0_RESET_VAL                      MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_VI_CLAMP_CONTROL_0_RESET_MASK                     MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_VI_CLAMP_CONTROL_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_VI_CLAMP_CONTROL_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_VI_CLAMP_CONTROL_0_READ_MASK                      MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_VI_CLAMP_CONTROL_0_WRITE_MASK                     MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_VI_CLAMP_CONTROL_0_CLAMP_SHIFT                    MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_VI_CLAMP_CONTROL_0_CLAMP_FIELD                    MK_FIELD_CONST(0x1, PMC_IMPL_PART_VI_CLAMP_CONTROL_0_CLAMP_SHIFT)
#define PMC_IMPL_PART_VI_CLAMP_CONTROL_0_CLAMP_RANGE                    0:0
#define PMC_IMPL_PART_VI_CLAMP_CONTROL_0_CLAMP_MSB                      MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_VI_CLAMP_CONTROL_0_CLAMP_LSB                      MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_VI_CLAMP_CONTROL_0_CLAMP_WOFFSET                  0x0
#define PMC_IMPL_PART_VI_CLAMP_CONTROL_0_CLAMP_DEFAULT                  MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_VI_CLAMP_CONTROL_0_CLAMP_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_VI_CLAMP_CONTROL_0_CLAMP_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_VI_CLAMP_CONTROL_0_CLAMP_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_VI_CLAMP_CONTROL_0_CLAMP_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_VI_CLAMP_CONTROL_0_CLAMP_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_VI_CLAMP_CONTROL_0_CLAMP_INIT_ENUM                        ON
#define PMC_IMPL_PART_VI_CLAMP_CONTROL_0_CLAMP_OFF                      MK_ENUM_CONST(0)
#define PMC_IMPL_PART_VI_CLAMP_CONTROL_0_CLAMP_ON                       MK_ENUM_CONST(1)


// Register PMC_IMPL_PART_PCIEX4BA_POWER_GATE_CONTROL_0
#define PMC_IMPL_PART_PCIEX4BA_POWER_GATE_CONTROL_0                     MK_ADDR_CONST(0x508)
#define PMC_IMPL_PART_PCIEX4BA_POWER_GATE_CONTROL_0_SECURE                      0x0
#define PMC_IMPL_PART_PCIEX4BA_POWER_GATE_CONTROL_0_DUAL                        0x0
#define PMC_IMPL_PART_PCIEX4BA_POWER_GATE_CONTROL_0_SCR                         PG_PCIEX4BA_SCR_0
#define PMC_IMPL_PART_PCIEX4BA_POWER_GATE_CONTROL_0_SCRREG                      PMC_IMPL_SCR_PG_PCIEX4BA_SCR_0
#define PMC_IMPL_PART_PCIEX4BA_POWER_GATE_CONTROL_0_WORD_COUNT                  0x1
#define PMC_IMPL_PART_PCIEX4BA_POWER_GATE_CONTROL_0_RESET_VAL                   MK_MASK_CONST(0x80000005)
#define PMC_IMPL_PART_PCIEX4BA_POWER_GATE_CONTROL_0_RESET_MASK                  MK_MASK_CONST(0x80000107)
#define PMC_IMPL_PART_PCIEX4BA_POWER_GATE_CONTROL_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX4BA_POWER_GATE_CONTROL_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX4BA_POWER_GATE_CONTROL_0_READ_MASK                   MK_MASK_CONST(0x80000107)
#define PMC_IMPL_PART_PCIEX4BA_POWER_GATE_CONTROL_0_WRITE_MASK                  MK_MASK_CONST(0x80000105)
#define PMC_IMPL_PART_PCIEX4BA_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SHIFT                   MK_SHIFT_CONST(31)
#define PMC_IMPL_PART_PCIEX4BA_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_FIELD                   MK_FIELD_CONST(0x1, PMC_IMPL_PART_PCIEX4BA_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SHIFT)
#define PMC_IMPL_PART_PCIEX4BA_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_RANGE                   31:31
#define PMC_IMPL_PART_PCIEX4BA_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_MSB                     MK_SHIFT_CONST(31)
#define PMC_IMPL_PART_PCIEX4BA_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_LSB                     MK_SHIFT_CONST(31)
#define PMC_IMPL_PART_PCIEX4BA_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_WOFFSET                 0x0
#define PMC_IMPL_PART_PCIEX4BA_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_DEFAULT                 MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PCIEX4BA_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PCIEX4BA_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX4BA_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX4BA_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX4BA_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PCIEX4BA_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_INIT_ENUM                       ENABLE
#define PMC_IMPL_PART_PCIEX4BA_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_DISABLE                 MK_ENUM_CONST(0)
#define PMC_IMPL_PART_PCIEX4BA_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_ENABLE                  MK_ENUM_CONST(1)

#define PMC_IMPL_PART_PCIEX4BA_POWER_GATE_CONTROL_0_START_SHIFT                 MK_SHIFT_CONST(8)
#define PMC_IMPL_PART_PCIEX4BA_POWER_GATE_CONTROL_0_START_FIELD                 MK_FIELD_CONST(0x1, PMC_IMPL_PART_PCIEX4BA_POWER_GATE_CONTROL_0_START_SHIFT)
#define PMC_IMPL_PART_PCIEX4BA_POWER_GATE_CONTROL_0_START_RANGE                 8:8
#define PMC_IMPL_PART_PCIEX4BA_POWER_GATE_CONTROL_0_START_MSB                   MK_SHIFT_CONST(8)
#define PMC_IMPL_PART_PCIEX4BA_POWER_GATE_CONTROL_0_START_LSB                   MK_SHIFT_CONST(8)
#define PMC_IMPL_PART_PCIEX4BA_POWER_GATE_CONTROL_0_START_WOFFSET                       0x0
#define PMC_IMPL_PART_PCIEX4BA_POWER_GATE_CONTROL_0_START_DEFAULT                       MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX4BA_POWER_GATE_CONTROL_0_START_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PCIEX4BA_POWER_GATE_CONTROL_0_START_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX4BA_POWER_GATE_CONTROL_0_START_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX4BA_POWER_GATE_CONTROL_0_START_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX4BA_POWER_GATE_CONTROL_0_START_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PCIEX4BA_POWER_GATE_CONTROL_0_START_INIT_ENUM                     DONE
#define PMC_IMPL_PART_PCIEX4BA_POWER_GATE_CONTROL_0_START_DONE                  MK_ENUM_CONST(0)
#define PMC_IMPL_PART_PCIEX4BA_POWER_GATE_CONTROL_0_START_PENDING                       MK_ENUM_CONST(1)

#define PMC_IMPL_PART_PCIEX4BA_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SHIFT                 MK_SHIFT_CONST(2)
#define PMC_IMPL_PART_PCIEX4BA_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_FIELD                 MK_FIELD_CONST(0x1, PMC_IMPL_PART_PCIEX4BA_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SHIFT)
#define PMC_IMPL_PART_PCIEX4BA_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_RANGE                 2:2
#define PMC_IMPL_PART_PCIEX4BA_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_MSB                   MK_SHIFT_CONST(2)
#define PMC_IMPL_PART_PCIEX4BA_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_LSB                   MK_SHIFT_CONST(2)
#define PMC_IMPL_PART_PCIEX4BA_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_WOFFSET                       0x0
#define PMC_IMPL_PART_PCIEX4BA_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_DEFAULT                       MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PCIEX4BA_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PCIEX4BA_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX4BA_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX4BA_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX4BA_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PCIEX4BA_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_INIT_ENUM                     ON
#define PMC_IMPL_PART_PCIEX4BA_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_OFF                   MK_ENUM_CONST(0)
#define PMC_IMPL_PART_PCIEX4BA_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_ON                    MK_ENUM_CONST(1)

#define PMC_IMPL_PART_PCIEX4BA_POWER_GATE_CONTROL_0_SRAM_RET_EN_SHIFT                   MK_SHIFT_CONST(1)
#define PMC_IMPL_PART_PCIEX4BA_POWER_GATE_CONTROL_0_SRAM_RET_EN_FIELD                   MK_FIELD_CONST(0x1, PMC_IMPL_PART_PCIEX4BA_POWER_GATE_CONTROL_0_SRAM_RET_EN_SHIFT)
#define PMC_IMPL_PART_PCIEX4BA_POWER_GATE_CONTROL_0_SRAM_RET_EN_RANGE                   1:1
#define PMC_IMPL_PART_PCIEX4BA_POWER_GATE_CONTROL_0_SRAM_RET_EN_MSB                     MK_SHIFT_CONST(1)
#define PMC_IMPL_PART_PCIEX4BA_POWER_GATE_CONTROL_0_SRAM_RET_EN_LSB                     MK_SHIFT_CONST(1)
#define PMC_IMPL_PART_PCIEX4BA_POWER_GATE_CONTROL_0_SRAM_RET_EN_WOFFSET                 0x0
#define PMC_IMPL_PART_PCIEX4BA_POWER_GATE_CONTROL_0_SRAM_RET_EN_DEFAULT                 MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX4BA_POWER_GATE_CONTROL_0_SRAM_RET_EN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PCIEX4BA_POWER_GATE_CONTROL_0_SRAM_RET_EN_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX4BA_POWER_GATE_CONTROL_0_SRAM_RET_EN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX4BA_POWER_GATE_CONTROL_0_SRAM_RET_EN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX4BA_POWER_GATE_CONTROL_0_SRAM_RET_EN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PCIEX4BA_POWER_GATE_CONTROL_0_SRAM_RET_EN_INIT_ENUM                       OFF
#define PMC_IMPL_PART_PCIEX4BA_POWER_GATE_CONTROL_0_SRAM_RET_EN_OFF                     MK_ENUM_CONST(0)
#define PMC_IMPL_PART_PCIEX4BA_POWER_GATE_CONTROL_0_SRAM_RET_EN_ON                      MK_ENUM_CONST(1)

#define PMC_IMPL_PART_PCIEX4BA_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SHIFT                   MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_PCIEX4BA_POWER_GATE_CONTROL_0_LOGIC_SLEEP_FIELD                   MK_FIELD_CONST(0x1, PMC_IMPL_PART_PCIEX4BA_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SHIFT)
#define PMC_IMPL_PART_PCIEX4BA_POWER_GATE_CONTROL_0_LOGIC_SLEEP_RANGE                   0:0
#define PMC_IMPL_PART_PCIEX4BA_POWER_GATE_CONTROL_0_LOGIC_SLEEP_MSB                     MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_PCIEX4BA_POWER_GATE_CONTROL_0_LOGIC_SLEEP_LSB                     MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_PCIEX4BA_POWER_GATE_CONTROL_0_LOGIC_SLEEP_WOFFSET                 0x0
#define PMC_IMPL_PART_PCIEX4BA_POWER_GATE_CONTROL_0_LOGIC_SLEEP_DEFAULT                 MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PCIEX4BA_POWER_GATE_CONTROL_0_LOGIC_SLEEP_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PCIEX4BA_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX4BA_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX4BA_POWER_GATE_CONTROL_0_LOGIC_SLEEP_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX4BA_POWER_GATE_CONTROL_0_LOGIC_SLEEP_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PCIEX4BA_POWER_GATE_CONTROL_0_LOGIC_SLEEP_INIT_ENUM                       ON
#define PMC_IMPL_PART_PCIEX4BA_POWER_GATE_CONTROL_0_LOGIC_SLEEP_OFF                     MK_ENUM_CONST(0)
#define PMC_IMPL_PART_PCIEX4BA_POWER_GATE_CONTROL_0_LOGIC_SLEEP_ON                      MK_ENUM_CONST(1)


// Register PMC_IMPL_PART_PCIEX4BA_POWER_GATE_STATUS_0
#define PMC_IMPL_PART_PCIEX4BA_POWER_GATE_STATUS_0                      MK_ADDR_CONST(0x50c)
#define PMC_IMPL_PART_PCIEX4BA_POWER_GATE_STATUS_0_SECURE                       0x0
#define PMC_IMPL_PART_PCIEX4BA_POWER_GATE_STATUS_0_DUAL                         0x0
#define PMC_IMPL_PART_PCIEX4BA_POWER_GATE_STATUS_0_SCR                  PG_PCIEX4BA_SCR_0
#define PMC_IMPL_PART_PCIEX4BA_POWER_GATE_STATUS_0_SCRREG                       PMC_IMPL_SCR_PG_PCIEX4BA_SCR_0
#define PMC_IMPL_PART_PCIEX4BA_POWER_GATE_STATUS_0_WORD_COUNT                   0x1
#define PMC_IMPL_PART_PCIEX4BA_POWER_GATE_STATUS_0_RESET_VAL                    MK_MASK_CONST(0x5)
#define PMC_IMPL_PART_PCIEX4BA_POWER_GATE_STATUS_0_RESET_MASK                   MK_MASK_CONST(0x7)
#define PMC_IMPL_PART_PCIEX4BA_POWER_GATE_STATUS_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX4BA_POWER_GATE_STATUS_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX4BA_POWER_GATE_STATUS_0_READ_MASK                    MK_MASK_CONST(0x7)
#define PMC_IMPL_PART_PCIEX4BA_POWER_GATE_STATUS_0_WRITE_MASK                   MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX4BA_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SHIFT                 MK_SHIFT_CONST(2)
#define PMC_IMPL_PART_PCIEX4BA_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_FIELD                 MK_FIELD_CONST(0x1, PMC_IMPL_PART_PCIEX4BA_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SHIFT)
#define PMC_IMPL_PART_PCIEX4BA_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_RANGE                 2:2
#define PMC_IMPL_PART_PCIEX4BA_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_MSB                   MK_SHIFT_CONST(2)
#define PMC_IMPL_PART_PCIEX4BA_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_LSB                   MK_SHIFT_CONST(2)
#define PMC_IMPL_PART_PCIEX4BA_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_WOFFSET                       0x0
#define PMC_IMPL_PART_PCIEX4BA_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_DEFAULT                       MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PCIEX4BA_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PCIEX4BA_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX4BA_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX4BA_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX4BA_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PCIEX4BA_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_INIT_ENUM                     ON
#define PMC_IMPL_PART_PCIEX4BA_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_OFF                   MK_ENUM_CONST(0)
#define PMC_IMPL_PART_PCIEX4BA_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_ON                    MK_ENUM_CONST(1)

#define PMC_IMPL_PART_PCIEX4BA_POWER_GATE_STATUS_0_SRAM_RET_STS_SHIFT                   MK_SHIFT_CONST(1)
#define PMC_IMPL_PART_PCIEX4BA_POWER_GATE_STATUS_0_SRAM_RET_STS_FIELD                   MK_FIELD_CONST(0x1, PMC_IMPL_PART_PCIEX4BA_POWER_GATE_STATUS_0_SRAM_RET_STS_SHIFT)
#define PMC_IMPL_PART_PCIEX4BA_POWER_GATE_STATUS_0_SRAM_RET_STS_RANGE                   1:1
#define PMC_IMPL_PART_PCIEX4BA_POWER_GATE_STATUS_0_SRAM_RET_STS_MSB                     MK_SHIFT_CONST(1)
#define PMC_IMPL_PART_PCIEX4BA_POWER_GATE_STATUS_0_SRAM_RET_STS_LSB                     MK_SHIFT_CONST(1)
#define PMC_IMPL_PART_PCIEX4BA_POWER_GATE_STATUS_0_SRAM_RET_STS_WOFFSET                 0x0
#define PMC_IMPL_PART_PCIEX4BA_POWER_GATE_STATUS_0_SRAM_RET_STS_DEFAULT                 MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX4BA_POWER_GATE_STATUS_0_SRAM_RET_STS_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PCIEX4BA_POWER_GATE_STATUS_0_SRAM_RET_STS_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX4BA_POWER_GATE_STATUS_0_SRAM_RET_STS_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX4BA_POWER_GATE_STATUS_0_SRAM_RET_STS_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX4BA_POWER_GATE_STATUS_0_SRAM_RET_STS_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PCIEX4BA_POWER_GATE_STATUS_0_SRAM_RET_STS_INIT_ENUM                       OFF
#define PMC_IMPL_PART_PCIEX4BA_POWER_GATE_STATUS_0_SRAM_RET_STS_OFF                     MK_ENUM_CONST(0)
#define PMC_IMPL_PART_PCIEX4BA_POWER_GATE_STATUS_0_SRAM_RET_STS_ON                      MK_ENUM_CONST(1)

#define PMC_IMPL_PART_PCIEX4BA_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SHIFT                        MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_PCIEX4BA_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_FIELD                        MK_FIELD_CONST(0x1, PMC_IMPL_PART_PCIEX4BA_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SHIFT)
#define PMC_IMPL_PART_PCIEX4BA_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_RANGE                        0:0
#define PMC_IMPL_PART_PCIEX4BA_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_MSB                  MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_PCIEX4BA_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_LSB                  MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_PCIEX4BA_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_WOFFSET                      0x0
#define PMC_IMPL_PART_PCIEX4BA_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_DEFAULT                      MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PCIEX4BA_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PCIEX4BA_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX4BA_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX4BA_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX4BA_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PCIEX4BA_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_INIT_ENUM                    ON
#define PMC_IMPL_PART_PCIEX4BA_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_OFF                  MK_ENUM_CONST(0)
#define PMC_IMPL_PART_PCIEX4BA_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_ON                   MK_ENUM_CONST(1)


// Register PMC_IMPL_PART_PCIEX4BA_CLAMP_CONTROL_0
#define PMC_IMPL_PART_PCIEX4BA_CLAMP_CONTROL_0                  MK_ADDR_CONST(0x510)
#define PMC_IMPL_PART_PCIEX4BA_CLAMP_CONTROL_0_SECURE                   0x0
#define PMC_IMPL_PART_PCIEX4BA_CLAMP_CONTROL_0_DUAL                     0x0
#define PMC_IMPL_PART_PCIEX4BA_CLAMP_CONTROL_0_SCR                      PG_PCIEX4BA_SCR_0
#define PMC_IMPL_PART_PCIEX4BA_CLAMP_CONTROL_0_SCRREG                   PMC_IMPL_SCR_PG_PCIEX4BA_SCR_0
#define PMC_IMPL_PART_PCIEX4BA_CLAMP_CONTROL_0_WORD_COUNT                       0x1
#define PMC_IMPL_PART_PCIEX4BA_CLAMP_CONTROL_0_RESET_VAL                        MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PCIEX4BA_CLAMP_CONTROL_0_RESET_MASK                       MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PCIEX4BA_CLAMP_CONTROL_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX4BA_CLAMP_CONTROL_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX4BA_CLAMP_CONTROL_0_READ_MASK                        MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PCIEX4BA_CLAMP_CONTROL_0_WRITE_MASK                       MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PCIEX4BA_CLAMP_CONTROL_0_CLAMP_SHIFT                      MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_PCIEX4BA_CLAMP_CONTROL_0_CLAMP_FIELD                      MK_FIELD_CONST(0x1, PMC_IMPL_PART_PCIEX4BA_CLAMP_CONTROL_0_CLAMP_SHIFT)
#define PMC_IMPL_PART_PCIEX4BA_CLAMP_CONTROL_0_CLAMP_RANGE                      0:0
#define PMC_IMPL_PART_PCIEX4BA_CLAMP_CONTROL_0_CLAMP_MSB                        MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_PCIEX4BA_CLAMP_CONTROL_0_CLAMP_LSB                        MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_PCIEX4BA_CLAMP_CONTROL_0_CLAMP_WOFFSET                    0x0
#define PMC_IMPL_PART_PCIEX4BA_CLAMP_CONTROL_0_CLAMP_DEFAULT                    MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PCIEX4BA_CLAMP_CONTROL_0_CLAMP_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PCIEX4BA_CLAMP_CONTROL_0_CLAMP_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX4BA_CLAMP_CONTROL_0_CLAMP_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX4BA_CLAMP_CONTROL_0_CLAMP_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX4BA_CLAMP_CONTROL_0_CLAMP_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PCIEX4BA_CLAMP_CONTROL_0_CLAMP_INIT_ENUM                  ON
#define PMC_IMPL_PART_PCIEX4BA_CLAMP_CONTROL_0_CLAMP_OFF                        MK_ENUM_CONST(0)
#define PMC_IMPL_PART_PCIEX4BA_CLAMP_CONTROL_0_CLAMP_ON                 MK_ENUM_CONST(1)


// Register PMC_IMPL_PART_PCIEX4BB_POWER_GATE_CONTROL_0
#define PMC_IMPL_PART_PCIEX4BB_POWER_GATE_CONTROL_0                     MK_ADDR_CONST(0x514)
#define PMC_IMPL_PART_PCIEX4BB_POWER_GATE_CONTROL_0_SECURE                      0x0
#define PMC_IMPL_PART_PCIEX4BB_POWER_GATE_CONTROL_0_DUAL                        0x0
#define PMC_IMPL_PART_PCIEX4BB_POWER_GATE_CONTROL_0_SCR                         PG_PCIEX4BB_SCR_0
#define PMC_IMPL_PART_PCIEX4BB_POWER_GATE_CONTROL_0_SCRREG                      PMC_IMPL_SCR_PG_PCIEX4BB_SCR_0
#define PMC_IMPL_PART_PCIEX4BB_POWER_GATE_CONTROL_0_WORD_COUNT                  0x1
#define PMC_IMPL_PART_PCIEX4BB_POWER_GATE_CONTROL_0_RESET_VAL                   MK_MASK_CONST(0x80000005)
#define PMC_IMPL_PART_PCIEX4BB_POWER_GATE_CONTROL_0_RESET_MASK                  MK_MASK_CONST(0x80000107)
#define PMC_IMPL_PART_PCIEX4BB_POWER_GATE_CONTROL_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX4BB_POWER_GATE_CONTROL_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX4BB_POWER_GATE_CONTROL_0_READ_MASK                   MK_MASK_CONST(0x80000107)
#define PMC_IMPL_PART_PCIEX4BB_POWER_GATE_CONTROL_0_WRITE_MASK                  MK_MASK_CONST(0x80000105)
#define PMC_IMPL_PART_PCIEX4BB_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SHIFT                   MK_SHIFT_CONST(31)
#define PMC_IMPL_PART_PCIEX4BB_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_FIELD                   MK_FIELD_CONST(0x1, PMC_IMPL_PART_PCIEX4BB_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SHIFT)
#define PMC_IMPL_PART_PCIEX4BB_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_RANGE                   31:31
#define PMC_IMPL_PART_PCIEX4BB_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_MSB                     MK_SHIFT_CONST(31)
#define PMC_IMPL_PART_PCIEX4BB_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_LSB                     MK_SHIFT_CONST(31)
#define PMC_IMPL_PART_PCIEX4BB_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_WOFFSET                 0x0
#define PMC_IMPL_PART_PCIEX4BB_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_DEFAULT                 MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PCIEX4BB_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PCIEX4BB_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX4BB_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX4BB_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX4BB_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PCIEX4BB_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_INIT_ENUM                       ENABLE
#define PMC_IMPL_PART_PCIEX4BB_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_DISABLE                 MK_ENUM_CONST(0)
#define PMC_IMPL_PART_PCIEX4BB_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_ENABLE                  MK_ENUM_CONST(1)

#define PMC_IMPL_PART_PCIEX4BB_POWER_GATE_CONTROL_0_START_SHIFT                 MK_SHIFT_CONST(8)
#define PMC_IMPL_PART_PCIEX4BB_POWER_GATE_CONTROL_0_START_FIELD                 MK_FIELD_CONST(0x1, PMC_IMPL_PART_PCIEX4BB_POWER_GATE_CONTROL_0_START_SHIFT)
#define PMC_IMPL_PART_PCIEX4BB_POWER_GATE_CONTROL_0_START_RANGE                 8:8
#define PMC_IMPL_PART_PCIEX4BB_POWER_GATE_CONTROL_0_START_MSB                   MK_SHIFT_CONST(8)
#define PMC_IMPL_PART_PCIEX4BB_POWER_GATE_CONTROL_0_START_LSB                   MK_SHIFT_CONST(8)
#define PMC_IMPL_PART_PCIEX4BB_POWER_GATE_CONTROL_0_START_WOFFSET                       0x0
#define PMC_IMPL_PART_PCIEX4BB_POWER_GATE_CONTROL_0_START_DEFAULT                       MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX4BB_POWER_GATE_CONTROL_0_START_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PCIEX4BB_POWER_GATE_CONTROL_0_START_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX4BB_POWER_GATE_CONTROL_0_START_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX4BB_POWER_GATE_CONTROL_0_START_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX4BB_POWER_GATE_CONTROL_0_START_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PCIEX4BB_POWER_GATE_CONTROL_0_START_INIT_ENUM                     DONE
#define PMC_IMPL_PART_PCIEX4BB_POWER_GATE_CONTROL_0_START_DONE                  MK_ENUM_CONST(0)
#define PMC_IMPL_PART_PCIEX4BB_POWER_GATE_CONTROL_0_START_PENDING                       MK_ENUM_CONST(1)

#define PMC_IMPL_PART_PCIEX4BB_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SHIFT                 MK_SHIFT_CONST(2)
#define PMC_IMPL_PART_PCIEX4BB_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_FIELD                 MK_FIELD_CONST(0x1, PMC_IMPL_PART_PCIEX4BB_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SHIFT)
#define PMC_IMPL_PART_PCIEX4BB_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_RANGE                 2:2
#define PMC_IMPL_PART_PCIEX4BB_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_MSB                   MK_SHIFT_CONST(2)
#define PMC_IMPL_PART_PCIEX4BB_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_LSB                   MK_SHIFT_CONST(2)
#define PMC_IMPL_PART_PCIEX4BB_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_WOFFSET                       0x0
#define PMC_IMPL_PART_PCIEX4BB_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_DEFAULT                       MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PCIEX4BB_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PCIEX4BB_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX4BB_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX4BB_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX4BB_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PCIEX4BB_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_INIT_ENUM                     ON
#define PMC_IMPL_PART_PCIEX4BB_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_OFF                   MK_ENUM_CONST(0)
#define PMC_IMPL_PART_PCIEX4BB_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_ON                    MK_ENUM_CONST(1)

#define PMC_IMPL_PART_PCIEX4BB_POWER_GATE_CONTROL_0_SRAM_RET_EN_SHIFT                   MK_SHIFT_CONST(1)
#define PMC_IMPL_PART_PCIEX4BB_POWER_GATE_CONTROL_0_SRAM_RET_EN_FIELD                   MK_FIELD_CONST(0x1, PMC_IMPL_PART_PCIEX4BB_POWER_GATE_CONTROL_0_SRAM_RET_EN_SHIFT)
#define PMC_IMPL_PART_PCIEX4BB_POWER_GATE_CONTROL_0_SRAM_RET_EN_RANGE                   1:1
#define PMC_IMPL_PART_PCIEX4BB_POWER_GATE_CONTROL_0_SRAM_RET_EN_MSB                     MK_SHIFT_CONST(1)
#define PMC_IMPL_PART_PCIEX4BB_POWER_GATE_CONTROL_0_SRAM_RET_EN_LSB                     MK_SHIFT_CONST(1)
#define PMC_IMPL_PART_PCIEX4BB_POWER_GATE_CONTROL_0_SRAM_RET_EN_WOFFSET                 0x0
#define PMC_IMPL_PART_PCIEX4BB_POWER_GATE_CONTROL_0_SRAM_RET_EN_DEFAULT                 MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX4BB_POWER_GATE_CONTROL_0_SRAM_RET_EN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PCIEX4BB_POWER_GATE_CONTROL_0_SRAM_RET_EN_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX4BB_POWER_GATE_CONTROL_0_SRAM_RET_EN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX4BB_POWER_GATE_CONTROL_0_SRAM_RET_EN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX4BB_POWER_GATE_CONTROL_0_SRAM_RET_EN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PCIEX4BB_POWER_GATE_CONTROL_0_SRAM_RET_EN_INIT_ENUM                       OFF
#define PMC_IMPL_PART_PCIEX4BB_POWER_GATE_CONTROL_0_SRAM_RET_EN_OFF                     MK_ENUM_CONST(0)
#define PMC_IMPL_PART_PCIEX4BB_POWER_GATE_CONTROL_0_SRAM_RET_EN_ON                      MK_ENUM_CONST(1)

#define PMC_IMPL_PART_PCIEX4BB_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SHIFT                   MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_PCIEX4BB_POWER_GATE_CONTROL_0_LOGIC_SLEEP_FIELD                   MK_FIELD_CONST(0x1, PMC_IMPL_PART_PCIEX4BB_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SHIFT)
#define PMC_IMPL_PART_PCIEX4BB_POWER_GATE_CONTROL_0_LOGIC_SLEEP_RANGE                   0:0
#define PMC_IMPL_PART_PCIEX4BB_POWER_GATE_CONTROL_0_LOGIC_SLEEP_MSB                     MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_PCIEX4BB_POWER_GATE_CONTROL_0_LOGIC_SLEEP_LSB                     MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_PCIEX4BB_POWER_GATE_CONTROL_0_LOGIC_SLEEP_WOFFSET                 0x0
#define PMC_IMPL_PART_PCIEX4BB_POWER_GATE_CONTROL_0_LOGIC_SLEEP_DEFAULT                 MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PCIEX4BB_POWER_GATE_CONTROL_0_LOGIC_SLEEP_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PCIEX4BB_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX4BB_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX4BB_POWER_GATE_CONTROL_0_LOGIC_SLEEP_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX4BB_POWER_GATE_CONTROL_0_LOGIC_SLEEP_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PCIEX4BB_POWER_GATE_CONTROL_0_LOGIC_SLEEP_INIT_ENUM                       ON
#define PMC_IMPL_PART_PCIEX4BB_POWER_GATE_CONTROL_0_LOGIC_SLEEP_OFF                     MK_ENUM_CONST(0)
#define PMC_IMPL_PART_PCIEX4BB_POWER_GATE_CONTROL_0_LOGIC_SLEEP_ON                      MK_ENUM_CONST(1)


// Register PMC_IMPL_PART_PCIEX4BB_POWER_GATE_STATUS_0
#define PMC_IMPL_PART_PCIEX4BB_POWER_GATE_STATUS_0                      MK_ADDR_CONST(0x518)
#define PMC_IMPL_PART_PCIEX4BB_POWER_GATE_STATUS_0_SECURE                       0x0
#define PMC_IMPL_PART_PCIEX4BB_POWER_GATE_STATUS_0_DUAL                         0x0
#define PMC_IMPL_PART_PCIEX4BB_POWER_GATE_STATUS_0_SCR                  PG_PCIEX4BB_SCR_0
#define PMC_IMPL_PART_PCIEX4BB_POWER_GATE_STATUS_0_SCRREG                       PMC_IMPL_SCR_PG_PCIEX4BB_SCR_0
#define PMC_IMPL_PART_PCIEX4BB_POWER_GATE_STATUS_0_WORD_COUNT                   0x1
#define PMC_IMPL_PART_PCIEX4BB_POWER_GATE_STATUS_0_RESET_VAL                    MK_MASK_CONST(0x5)
#define PMC_IMPL_PART_PCIEX4BB_POWER_GATE_STATUS_0_RESET_MASK                   MK_MASK_CONST(0x7)
#define PMC_IMPL_PART_PCIEX4BB_POWER_GATE_STATUS_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX4BB_POWER_GATE_STATUS_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX4BB_POWER_GATE_STATUS_0_READ_MASK                    MK_MASK_CONST(0x7)
#define PMC_IMPL_PART_PCIEX4BB_POWER_GATE_STATUS_0_WRITE_MASK                   MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX4BB_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SHIFT                 MK_SHIFT_CONST(2)
#define PMC_IMPL_PART_PCIEX4BB_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_FIELD                 MK_FIELD_CONST(0x1, PMC_IMPL_PART_PCIEX4BB_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SHIFT)
#define PMC_IMPL_PART_PCIEX4BB_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_RANGE                 2:2
#define PMC_IMPL_PART_PCIEX4BB_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_MSB                   MK_SHIFT_CONST(2)
#define PMC_IMPL_PART_PCIEX4BB_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_LSB                   MK_SHIFT_CONST(2)
#define PMC_IMPL_PART_PCIEX4BB_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_WOFFSET                       0x0
#define PMC_IMPL_PART_PCIEX4BB_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_DEFAULT                       MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PCIEX4BB_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PCIEX4BB_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX4BB_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX4BB_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX4BB_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PCIEX4BB_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_INIT_ENUM                     ON
#define PMC_IMPL_PART_PCIEX4BB_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_OFF                   MK_ENUM_CONST(0)
#define PMC_IMPL_PART_PCIEX4BB_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_ON                    MK_ENUM_CONST(1)

#define PMC_IMPL_PART_PCIEX4BB_POWER_GATE_STATUS_0_SRAM_RET_STS_SHIFT                   MK_SHIFT_CONST(1)
#define PMC_IMPL_PART_PCIEX4BB_POWER_GATE_STATUS_0_SRAM_RET_STS_FIELD                   MK_FIELD_CONST(0x1, PMC_IMPL_PART_PCIEX4BB_POWER_GATE_STATUS_0_SRAM_RET_STS_SHIFT)
#define PMC_IMPL_PART_PCIEX4BB_POWER_GATE_STATUS_0_SRAM_RET_STS_RANGE                   1:1
#define PMC_IMPL_PART_PCIEX4BB_POWER_GATE_STATUS_0_SRAM_RET_STS_MSB                     MK_SHIFT_CONST(1)
#define PMC_IMPL_PART_PCIEX4BB_POWER_GATE_STATUS_0_SRAM_RET_STS_LSB                     MK_SHIFT_CONST(1)
#define PMC_IMPL_PART_PCIEX4BB_POWER_GATE_STATUS_0_SRAM_RET_STS_WOFFSET                 0x0
#define PMC_IMPL_PART_PCIEX4BB_POWER_GATE_STATUS_0_SRAM_RET_STS_DEFAULT                 MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX4BB_POWER_GATE_STATUS_0_SRAM_RET_STS_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PCIEX4BB_POWER_GATE_STATUS_0_SRAM_RET_STS_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX4BB_POWER_GATE_STATUS_0_SRAM_RET_STS_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX4BB_POWER_GATE_STATUS_0_SRAM_RET_STS_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX4BB_POWER_GATE_STATUS_0_SRAM_RET_STS_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PCIEX4BB_POWER_GATE_STATUS_0_SRAM_RET_STS_INIT_ENUM                       OFF
#define PMC_IMPL_PART_PCIEX4BB_POWER_GATE_STATUS_0_SRAM_RET_STS_OFF                     MK_ENUM_CONST(0)
#define PMC_IMPL_PART_PCIEX4BB_POWER_GATE_STATUS_0_SRAM_RET_STS_ON                      MK_ENUM_CONST(1)

#define PMC_IMPL_PART_PCIEX4BB_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SHIFT                        MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_PCIEX4BB_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_FIELD                        MK_FIELD_CONST(0x1, PMC_IMPL_PART_PCIEX4BB_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SHIFT)
#define PMC_IMPL_PART_PCIEX4BB_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_RANGE                        0:0
#define PMC_IMPL_PART_PCIEX4BB_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_MSB                  MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_PCIEX4BB_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_LSB                  MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_PCIEX4BB_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_WOFFSET                      0x0
#define PMC_IMPL_PART_PCIEX4BB_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_DEFAULT                      MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PCIEX4BB_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PCIEX4BB_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX4BB_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX4BB_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX4BB_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PCIEX4BB_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_INIT_ENUM                    ON
#define PMC_IMPL_PART_PCIEX4BB_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_OFF                  MK_ENUM_CONST(0)
#define PMC_IMPL_PART_PCIEX4BB_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_ON                   MK_ENUM_CONST(1)


// Register PMC_IMPL_PART_PCIEX4BB_CLAMP_CONTROL_0
#define PMC_IMPL_PART_PCIEX4BB_CLAMP_CONTROL_0                  MK_ADDR_CONST(0x51c)
#define PMC_IMPL_PART_PCIEX4BB_CLAMP_CONTROL_0_SECURE                   0x0
#define PMC_IMPL_PART_PCIEX4BB_CLAMP_CONTROL_0_DUAL                     0x0
#define PMC_IMPL_PART_PCIEX4BB_CLAMP_CONTROL_0_SCR                      PG_PCIEX4BB_SCR_0
#define PMC_IMPL_PART_PCIEX4BB_CLAMP_CONTROL_0_SCRREG                   PMC_IMPL_SCR_PG_PCIEX4BB_SCR_0
#define PMC_IMPL_PART_PCIEX4BB_CLAMP_CONTROL_0_WORD_COUNT                       0x1
#define PMC_IMPL_PART_PCIEX4BB_CLAMP_CONTROL_0_RESET_VAL                        MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PCIEX4BB_CLAMP_CONTROL_0_RESET_MASK                       MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PCIEX4BB_CLAMP_CONTROL_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX4BB_CLAMP_CONTROL_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX4BB_CLAMP_CONTROL_0_READ_MASK                        MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PCIEX4BB_CLAMP_CONTROL_0_WRITE_MASK                       MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PCIEX4BB_CLAMP_CONTROL_0_CLAMP_SHIFT                      MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_PCIEX4BB_CLAMP_CONTROL_0_CLAMP_FIELD                      MK_FIELD_CONST(0x1, PMC_IMPL_PART_PCIEX4BB_CLAMP_CONTROL_0_CLAMP_SHIFT)
#define PMC_IMPL_PART_PCIEX4BB_CLAMP_CONTROL_0_CLAMP_RANGE                      0:0
#define PMC_IMPL_PART_PCIEX4BB_CLAMP_CONTROL_0_CLAMP_MSB                        MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_PCIEX4BB_CLAMP_CONTROL_0_CLAMP_LSB                        MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_PCIEX4BB_CLAMP_CONTROL_0_CLAMP_WOFFSET                    0x0
#define PMC_IMPL_PART_PCIEX4BB_CLAMP_CONTROL_0_CLAMP_DEFAULT                    MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PCIEX4BB_CLAMP_CONTROL_0_CLAMP_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PCIEX4BB_CLAMP_CONTROL_0_CLAMP_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX4BB_CLAMP_CONTROL_0_CLAMP_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX4BB_CLAMP_CONTROL_0_CLAMP_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX4BB_CLAMP_CONTROL_0_CLAMP_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PCIEX4BB_CLAMP_CONTROL_0_CLAMP_INIT_ENUM                  ON
#define PMC_IMPL_PART_PCIEX4BB_CLAMP_CONTROL_0_CLAMP_OFF                        MK_ENUM_CONST(0)
#define PMC_IMPL_PART_PCIEX4BB_CLAMP_CONTROL_0_CLAMP_ON                 MK_ENUM_CONST(1)


// Register PMC_IMPL_PART_PCIEX4CA_POWER_GATE_CONTROL_0
#define PMC_IMPL_PART_PCIEX4CA_POWER_GATE_CONTROL_0                     MK_ADDR_CONST(0x520)
#define PMC_IMPL_PART_PCIEX4CA_POWER_GATE_CONTROL_0_SECURE                      0x0
#define PMC_IMPL_PART_PCIEX4CA_POWER_GATE_CONTROL_0_DUAL                        0x0
#define PMC_IMPL_PART_PCIEX4CA_POWER_GATE_CONTROL_0_SCR                         PG_PCIEX4CA_SCR_0
#define PMC_IMPL_PART_PCIEX4CA_POWER_GATE_CONTROL_0_SCRREG                      PMC_IMPL_SCR_PG_PCIEX4CA_SCR_0
#define PMC_IMPL_PART_PCIEX4CA_POWER_GATE_CONTROL_0_WORD_COUNT                  0x1
#define PMC_IMPL_PART_PCIEX4CA_POWER_GATE_CONTROL_0_RESET_VAL                   MK_MASK_CONST(0x80000005)
#define PMC_IMPL_PART_PCIEX4CA_POWER_GATE_CONTROL_0_RESET_MASK                  MK_MASK_CONST(0x80000107)
#define PMC_IMPL_PART_PCIEX4CA_POWER_GATE_CONTROL_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX4CA_POWER_GATE_CONTROL_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX4CA_POWER_GATE_CONTROL_0_READ_MASK                   MK_MASK_CONST(0x80000107)
#define PMC_IMPL_PART_PCIEX4CA_POWER_GATE_CONTROL_0_WRITE_MASK                  MK_MASK_CONST(0x80000105)
#define PMC_IMPL_PART_PCIEX4CA_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SHIFT                   MK_SHIFT_CONST(31)
#define PMC_IMPL_PART_PCIEX4CA_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_FIELD                   MK_FIELD_CONST(0x1, PMC_IMPL_PART_PCIEX4CA_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SHIFT)
#define PMC_IMPL_PART_PCIEX4CA_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_RANGE                   31:31
#define PMC_IMPL_PART_PCIEX4CA_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_MSB                     MK_SHIFT_CONST(31)
#define PMC_IMPL_PART_PCIEX4CA_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_LSB                     MK_SHIFT_CONST(31)
#define PMC_IMPL_PART_PCIEX4CA_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_WOFFSET                 0x0
#define PMC_IMPL_PART_PCIEX4CA_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_DEFAULT                 MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PCIEX4CA_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PCIEX4CA_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX4CA_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX4CA_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX4CA_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PCIEX4CA_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_INIT_ENUM                       ENABLE
#define PMC_IMPL_PART_PCIEX4CA_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_DISABLE                 MK_ENUM_CONST(0)
#define PMC_IMPL_PART_PCIEX4CA_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_ENABLE                  MK_ENUM_CONST(1)

#define PMC_IMPL_PART_PCIEX4CA_POWER_GATE_CONTROL_0_START_SHIFT                 MK_SHIFT_CONST(8)
#define PMC_IMPL_PART_PCIEX4CA_POWER_GATE_CONTROL_0_START_FIELD                 MK_FIELD_CONST(0x1, PMC_IMPL_PART_PCIEX4CA_POWER_GATE_CONTROL_0_START_SHIFT)
#define PMC_IMPL_PART_PCIEX4CA_POWER_GATE_CONTROL_0_START_RANGE                 8:8
#define PMC_IMPL_PART_PCIEX4CA_POWER_GATE_CONTROL_0_START_MSB                   MK_SHIFT_CONST(8)
#define PMC_IMPL_PART_PCIEX4CA_POWER_GATE_CONTROL_0_START_LSB                   MK_SHIFT_CONST(8)
#define PMC_IMPL_PART_PCIEX4CA_POWER_GATE_CONTROL_0_START_WOFFSET                       0x0
#define PMC_IMPL_PART_PCIEX4CA_POWER_GATE_CONTROL_0_START_DEFAULT                       MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX4CA_POWER_GATE_CONTROL_0_START_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PCIEX4CA_POWER_GATE_CONTROL_0_START_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX4CA_POWER_GATE_CONTROL_0_START_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX4CA_POWER_GATE_CONTROL_0_START_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX4CA_POWER_GATE_CONTROL_0_START_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PCIEX4CA_POWER_GATE_CONTROL_0_START_INIT_ENUM                     DONE
#define PMC_IMPL_PART_PCIEX4CA_POWER_GATE_CONTROL_0_START_DONE                  MK_ENUM_CONST(0)
#define PMC_IMPL_PART_PCIEX4CA_POWER_GATE_CONTROL_0_START_PENDING                       MK_ENUM_CONST(1)

#define PMC_IMPL_PART_PCIEX4CA_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SHIFT                 MK_SHIFT_CONST(2)
#define PMC_IMPL_PART_PCIEX4CA_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_FIELD                 MK_FIELD_CONST(0x1, PMC_IMPL_PART_PCIEX4CA_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SHIFT)
#define PMC_IMPL_PART_PCIEX4CA_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_RANGE                 2:2
#define PMC_IMPL_PART_PCIEX4CA_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_MSB                   MK_SHIFT_CONST(2)
#define PMC_IMPL_PART_PCIEX4CA_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_LSB                   MK_SHIFT_CONST(2)
#define PMC_IMPL_PART_PCIEX4CA_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_WOFFSET                       0x0
#define PMC_IMPL_PART_PCIEX4CA_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_DEFAULT                       MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PCIEX4CA_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PCIEX4CA_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX4CA_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX4CA_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX4CA_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PCIEX4CA_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_INIT_ENUM                     ON
#define PMC_IMPL_PART_PCIEX4CA_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_OFF                   MK_ENUM_CONST(0)
#define PMC_IMPL_PART_PCIEX4CA_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_ON                    MK_ENUM_CONST(1)

#define PMC_IMPL_PART_PCIEX4CA_POWER_GATE_CONTROL_0_SRAM_RET_EN_SHIFT                   MK_SHIFT_CONST(1)
#define PMC_IMPL_PART_PCIEX4CA_POWER_GATE_CONTROL_0_SRAM_RET_EN_FIELD                   MK_FIELD_CONST(0x1, PMC_IMPL_PART_PCIEX4CA_POWER_GATE_CONTROL_0_SRAM_RET_EN_SHIFT)
#define PMC_IMPL_PART_PCIEX4CA_POWER_GATE_CONTROL_0_SRAM_RET_EN_RANGE                   1:1
#define PMC_IMPL_PART_PCIEX4CA_POWER_GATE_CONTROL_0_SRAM_RET_EN_MSB                     MK_SHIFT_CONST(1)
#define PMC_IMPL_PART_PCIEX4CA_POWER_GATE_CONTROL_0_SRAM_RET_EN_LSB                     MK_SHIFT_CONST(1)
#define PMC_IMPL_PART_PCIEX4CA_POWER_GATE_CONTROL_0_SRAM_RET_EN_WOFFSET                 0x0
#define PMC_IMPL_PART_PCIEX4CA_POWER_GATE_CONTROL_0_SRAM_RET_EN_DEFAULT                 MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX4CA_POWER_GATE_CONTROL_0_SRAM_RET_EN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PCIEX4CA_POWER_GATE_CONTROL_0_SRAM_RET_EN_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX4CA_POWER_GATE_CONTROL_0_SRAM_RET_EN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX4CA_POWER_GATE_CONTROL_0_SRAM_RET_EN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX4CA_POWER_GATE_CONTROL_0_SRAM_RET_EN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PCIEX4CA_POWER_GATE_CONTROL_0_SRAM_RET_EN_INIT_ENUM                       OFF
#define PMC_IMPL_PART_PCIEX4CA_POWER_GATE_CONTROL_0_SRAM_RET_EN_OFF                     MK_ENUM_CONST(0)
#define PMC_IMPL_PART_PCIEX4CA_POWER_GATE_CONTROL_0_SRAM_RET_EN_ON                      MK_ENUM_CONST(1)

#define PMC_IMPL_PART_PCIEX4CA_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SHIFT                   MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_PCIEX4CA_POWER_GATE_CONTROL_0_LOGIC_SLEEP_FIELD                   MK_FIELD_CONST(0x1, PMC_IMPL_PART_PCIEX4CA_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SHIFT)
#define PMC_IMPL_PART_PCIEX4CA_POWER_GATE_CONTROL_0_LOGIC_SLEEP_RANGE                   0:0
#define PMC_IMPL_PART_PCIEX4CA_POWER_GATE_CONTROL_0_LOGIC_SLEEP_MSB                     MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_PCIEX4CA_POWER_GATE_CONTROL_0_LOGIC_SLEEP_LSB                     MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_PCIEX4CA_POWER_GATE_CONTROL_0_LOGIC_SLEEP_WOFFSET                 0x0
#define PMC_IMPL_PART_PCIEX4CA_POWER_GATE_CONTROL_0_LOGIC_SLEEP_DEFAULT                 MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PCIEX4CA_POWER_GATE_CONTROL_0_LOGIC_SLEEP_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PCIEX4CA_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX4CA_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX4CA_POWER_GATE_CONTROL_0_LOGIC_SLEEP_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX4CA_POWER_GATE_CONTROL_0_LOGIC_SLEEP_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PCIEX4CA_POWER_GATE_CONTROL_0_LOGIC_SLEEP_INIT_ENUM                       ON
#define PMC_IMPL_PART_PCIEX4CA_POWER_GATE_CONTROL_0_LOGIC_SLEEP_OFF                     MK_ENUM_CONST(0)
#define PMC_IMPL_PART_PCIEX4CA_POWER_GATE_CONTROL_0_LOGIC_SLEEP_ON                      MK_ENUM_CONST(1)


// Register PMC_IMPL_PART_PCIEX4CA_POWER_GATE_STATUS_0
#define PMC_IMPL_PART_PCIEX4CA_POWER_GATE_STATUS_0                      MK_ADDR_CONST(0x524)
#define PMC_IMPL_PART_PCIEX4CA_POWER_GATE_STATUS_0_SECURE                       0x0
#define PMC_IMPL_PART_PCIEX4CA_POWER_GATE_STATUS_0_DUAL                         0x0
#define PMC_IMPL_PART_PCIEX4CA_POWER_GATE_STATUS_0_SCR                  PG_PCIEX4CA_SCR_0
#define PMC_IMPL_PART_PCIEX4CA_POWER_GATE_STATUS_0_SCRREG                       PMC_IMPL_SCR_PG_PCIEX4CA_SCR_0
#define PMC_IMPL_PART_PCIEX4CA_POWER_GATE_STATUS_0_WORD_COUNT                   0x1
#define PMC_IMPL_PART_PCIEX4CA_POWER_GATE_STATUS_0_RESET_VAL                    MK_MASK_CONST(0x5)
#define PMC_IMPL_PART_PCIEX4CA_POWER_GATE_STATUS_0_RESET_MASK                   MK_MASK_CONST(0x7)
#define PMC_IMPL_PART_PCIEX4CA_POWER_GATE_STATUS_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX4CA_POWER_GATE_STATUS_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX4CA_POWER_GATE_STATUS_0_READ_MASK                    MK_MASK_CONST(0x7)
#define PMC_IMPL_PART_PCIEX4CA_POWER_GATE_STATUS_0_WRITE_MASK                   MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX4CA_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SHIFT                 MK_SHIFT_CONST(2)
#define PMC_IMPL_PART_PCIEX4CA_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_FIELD                 MK_FIELD_CONST(0x1, PMC_IMPL_PART_PCIEX4CA_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SHIFT)
#define PMC_IMPL_PART_PCIEX4CA_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_RANGE                 2:2
#define PMC_IMPL_PART_PCIEX4CA_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_MSB                   MK_SHIFT_CONST(2)
#define PMC_IMPL_PART_PCIEX4CA_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_LSB                   MK_SHIFT_CONST(2)
#define PMC_IMPL_PART_PCIEX4CA_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_WOFFSET                       0x0
#define PMC_IMPL_PART_PCIEX4CA_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_DEFAULT                       MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PCIEX4CA_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PCIEX4CA_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX4CA_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX4CA_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX4CA_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PCIEX4CA_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_INIT_ENUM                     ON
#define PMC_IMPL_PART_PCIEX4CA_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_OFF                   MK_ENUM_CONST(0)
#define PMC_IMPL_PART_PCIEX4CA_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_ON                    MK_ENUM_CONST(1)

#define PMC_IMPL_PART_PCIEX4CA_POWER_GATE_STATUS_0_SRAM_RET_STS_SHIFT                   MK_SHIFT_CONST(1)
#define PMC_IMPL_PART_PCIEX4CA_POWER_GATE_STATUS_0_SRAM_RET_STS_FIELD                   MK_FIELD_CONST(0x1, PMC_IMPL_PART_PCIEX4CA_POWER_GATE_STATUS_0_SRAM_RET_STS_SHIFT)
#define PMC_IMPL_PART_PCIEX4CA_POWER_GATE_STATUS_0_SRAM_RET_STS_RANGE                   1:1
#define PMC_IMPL_PART_PCIEX4CA_POWER_GATE_STATUS_0_SRAM_RET_STS_MSB                     MK_SHIFT_CONST(1)
#define PMC_IMPL_PART_PCIEX4CA_POWER_GATE_STATUS_0_SRAM_RET_STS_LSB                     MK_SHIFT_CONST(1)
#define PMC_IMPL_PART_PCIEX4CA_POWER_GATE_STATUS_0_SRAM_RET_STS_WOFFSET                 0x0
#define PMC_IMPL_PART_PCIEX4CA_POWER_GATE_STATUS_0_SRAM_RET_STS_DEFAULT                 MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX4CA_POWER_GATE_STATUS_0_SRAM_RET_STS_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PCIEX4CA_POWER_GATE_STATUS_0_SRAM_RET_STS_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX4CA_POWER_GATE_STATUS_0_SRAM_RET_STS_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX4CA_POWER_GATE_STATUS_0_SRAM_RET_STS_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX4CA_POWER_GATE_STATUS_0_SRAM_RET_STS_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PCIEX4CA_POWER_GATE_STATUS_0_SRAM_RET_STS_INIT_ENUM                       OFF
#define PMC_IMPL_PART_PCIEX4CA_POWER_GATE_STATUS_0_SRAM_RET_STS_OFF                     MK_ENUM_CONST(0)
#define PMC_IMPL_PART_PCIEX4CA_POWER_GATE_STATUS_0_SRAM_RET_STS_ON                      MK_ENUM_CONST(1)

#define PMC_IMPL_PART_PCIEX4CA_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SHIFT                        MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_PCIEX4CA_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_FIELD                        MK_FIELD_CONST(0x1, PMC_IMPL_PART_PCIEX4CA_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SHIFT)
#define PMC_IMPL_PART_PCIEX4CA_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_RANGE                        0:0
#define PMC_IMPL_PART_PCIEX4CA_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_MSB                  MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_PCIEX4CA_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_LSB                  MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_PCIEX4CA_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_WOFFSET                      0x0
#define PMC_IMPL_PART_PCIEX4CA_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_DEFAULT                      MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PCIEX4CA_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PCIEX4CA_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX4CA_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX4CA_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX4CA_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PCIEX4CA_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_INIT_ENUM                    ON
#define PMC_IMPL_PART_PCIEX4CA_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_OFF                  MK_ENUM_CONST(0)
#define PMC_IMPL_PART_PCIEX4CA_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_ON                   MK_ENUM_CONST(1)


// Register PMC_IMPL_PART_PCIEX4CA_CLAMP_CONTROL_0
#define PMC_IMPL_PART_PCIEX4CA_CLAMP_CONTROL_0                  MK_ADDR_CONST(0x528)
#define PMC_IMPL_PART_PCIEX4CA_CLAMP_CONTROL_0_SECURE                   0x0
#define PMC_IMPL_PART_PCIEX4CA_CLAMP_CONTROL_0_DUAL                     0x0
#define PMC_IMPL_PART_PCIEX4CA_CLAMP_CONTROL_0_SCR                      PG_PCIEX4CA_SCR_0
#define PMC_IMPL_PART_PCIEX4CA_CLAMP_CONTROL_0_SCRREG                   PMC_IMPL_SCR_PG_PCIEX4CA_SCR_0
#define PMC_IMPL_PART_PCIEX4CA_CLAMP_CONTROL_0_WORD_COUNT                       0x1
#define PMC_IMPL_PART_PCIEX4CA_CLAMP_CONTROL_0_RESET_VAL                        MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PCIEX4CA_CLAMP_CONTROL_0_RESET_MASK                       MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PCIEX4CA_CLAMP_CONTROL_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX4CA_CLAMP_CONTROL_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX4CA_CLAMP_CONTROL_0_READ_MASK                        MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PCIEX4CA_CLAMP_CONTROL_0_WRITE_MASK                       MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PCIEX4CA_CLAMP_CONTROL_0_CLAMP_SHIFT                      MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_PCIEX4CA_CLAMP_CONTROL_0_CLAMP_FIELD                      MK_FIELD_CONST(0x1, PMC_IMPL_PART_PCIEX4CA_CLAMP_CONTROL_0_CLAMP_SHIFT)
#define PMC_IMPL_PART_PCIEX4CA_CLAMP_CONTROL_0_CLAMP_RANGE                      0:0
#define PMC_IMPL_PART_PCIEX4CA_CLAMP_CONTROL_0_CLAMP_MSB                        MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_PCIEX4CA_CLAMP_CONTROL_0_CLAMP_LSB                        MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_PCIEX4CA_CLAMP_CONTROL_0_CLAMP_WOFFSET                    0x0
#define PMC_IMPL_PART_PCIEX4CA_CLAMP_CONTROL_0_CLAMP_DEFAULT                    MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PCIEX4CA_CLAMP_CONTROL_0_CLAMP_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PCIEX4CA_CLAMP_CONTROL_0_CLAMP_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX4CA_CLAMP_CONTROL_0_CLAMP_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX4CA_CLAMP_CONTROL_0_CLAMP_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX4CA_CLAMP_CONTROL_0_CLAMP_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PCIEX4CA_CLAMP_CONTROL_0_CLAMP_INIT_ENUM                  ON
#define PMC_IMPL_PART_PCIEX4CA_CLAMP_CONTROL_0_CLAMP_OFF                        MK_ENUM_CONST(0)
#define PMC_IMPL_PART_PCIEX4CA_CLAMP_CONTROL_0_CLAMP_ON                 MK_ENUM_CONST(1)


// Register PMC_IMPL_PART_PCIEX4CB_POWER_GATE_CONTROL_0
#define PMC_IMPL_PART_PCIEX4CB_POWER_GATE_CONTROL_0                     MK_ADDR_CONST(0x52c)
#define PMC_IMPL_PART_PCIEX4CB_POWER_GATE_CONTROL_0_SECURE                      0x0
#define PMC_IMPL_PART_PCIEX4CB_POWER_GATE_CONTROL_0_DUAL                        0x0
#define PMC_IMPL_PART_PCIEX4CB_POWER_GATE_CONTROL_0_SCR                         PG_PCIEX4CB_SCR_0
#define PMC_IMPL_PART_PCIEX4CB_POWER_GATE_CONTROL_0_SCRREG                      PMC_IMPL_SCR_PG_PCIEX4CB_SCR_0
#define PMC_IMPL_PART_PCIEX4CB_POWER_GATE_CONTROL_0_WORD_COUNT                  0x1
#define PMC_IMPL_PART_PCIEX4CB_POWER_GATE_CONTROL_0_RESET_VAL                   MK_MASK_CONST(0x80000005)
#define PMC_IMPL_PART_PCIEX4CB_POWER_GATE_CONTROL_0_RESET_MASK                  MK_MASK_CONST(0x80000107)
#define PMC_IMPL_PART_PCIEX4CB_POWER_GATE_CONTROL_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX4CB_POWER_GATE_CONTROL_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX4CB_POWER_GATE_CONTROL_0_READ_MASK                   MK_MASK_CONST(0x80000107)
#define PMC_IMPL_PART_PCIEX4CB_POWER_GATE_CONTROL_0_WRITE_MASK                  MK_MASK_CONST(0x80000105)
#define PMC_IMPL_PART_PCIEX4CB_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SHIFT                   MK_SHIFT_CONST(31)
#define PMC_IMPL_PART_PCIEX4CB_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_FIELD                   MK_FIELD_CONST(0x1, PMC_IMPL_PART_PCIEX4CB_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SHIFT)
#define PMC_IMPL_PART_PCIEX4CB_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_RANGE                   31:31
#define PMC_IMPL_PART_PCIEX4CB_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_MSB                     MK_SHIFT_CONST(31)
#define PMC_IMPL_PART_PCIEX4CB_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_LSB                     MK_SHIFT_CONST(31)
#define PMC_IMPL_PART_PCIEX4CB_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_WOFFSET                 0x0
#define PMC_IMPL_PART_PCIEX4CB_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_DEFAULT                 MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PCIEX4CB_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PCIEX4CB_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX4CB_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX4CB_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX4CB_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PCIEX4CB_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_INIT_ENUM                       ENABLE
#define PMC_IMPL_PART_PCIEX4CB_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_DISABLE                 MK_ENUM_CONST(0)
#define PMC_IMPL_PART_PCIEX4CB_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_ENABLE                  MK_ENUM_CONST(1)

#define PMC_IMPL_PART_PCIEX4CB_POWER_GATE_CONTROL_0_START_SHIFT                 MK_SHIFT_CONST(8)
#define PMC_IMPL_PART_PCIEX4CB_POWER_GATE_CONTROL_0_START_FIELD                 MK_FIELD_CONST(0x1, PMC_IMPL_PART_PCIEX4CB_POWER_GATE_CONTROL_0_START_SHIFT)
#define PMC_IMPL_PART_PCIEX4CB_POWER_GATE_CONTROL_0_START_RANGE                 8:8
#define PMC_IMPL_PART_PCIEX4CB_POWER_GATE_CONTROL_0_START_MSB                   MK_SHIFT_CONST(8)
#define PMC_IMPL_PART_PCIEX4CB_POWER_GATE_CONTROL_0_START_LSB                   MK_SHIFT_CONST(8)
#define PMC_IMPL_PART_PCIEX4CB_POWER_GATE_CONTROL_0_START_WOFFSET                       0x0
#define PMC_IMPL_PART_PCIEX4CB_POWER_GATE_CONTROL_0_START_DEFAULT                       MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX4CB_POWER_GATE_CONTROL_0_START_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PCIEX4CB_POWER_GATE_CONTROL_0_START_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX4CB_POWER_GATE_CONTROL_0_START_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX4CB_POWER_GATE_CONTROL_0_START_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX4CB_POWER_GATE_CONTROL_0_START_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PCIEX4CB_POWER_GATE_CONTROL_0_START_INIT_ENUM                     DONE
#define PMC_IMPL_PART_PCIEX4CB_POWER_GATE_CONTROL_0_START_DONE                  MK_ENUM_CONST(0)
#define PMC_IMPL_PART_PCIEX4CB_POWER_GATE_CONTROL_0_START_PENDING                       MK_ENUM_CONST(1)

#define PMC_IMPL_PART_PCIEX4CB_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SHIFT                 MK_SHIFT_CONST(2)
#define PMC_IMPL_PART_PCIEX4CB_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_FIELD                 MK_FIELD_CONST(0x1, PMC_IMPL_PART_PCIEX4CB_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SHIFT)
#define PMC_IMPL_PART_PCIEX4CB_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_RANGE                 2:2
#define PMC_IMPL_PART_PCIEX4CB_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_MSB                   MK_SHIFT_CONST(2)
#define PMC_IMPL_PART_PCIEX4CB_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_LSB                   MK_SHIFT_CONST(2)
#define PMC_IMPL_PART_PCIEX4CB_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_WOFFSET                       0x0
#define PMC_IMPL_PART_PCIEX4CB_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_DEFAULT                       MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PCIEX4CB_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PCIEX4CB_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX4CB_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX4CB_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX4CB_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PCIEX4CB_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_INIT_ENUM                     ON
#define PMC_IMPL_PART_PCIEX4CB_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_OFF                   MK_ENUM_CONST(0)
#define PMC_IMPL_PART_PCIEX4CB_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_ON                    MK_ENUM_CONST(1)

#define PMC_IMPL_PART_PCIEX4CB_POWER_GATE_CONTROL_0_SRAM_RET_EN_SHIFT                   MK_SHIFT_CONST(1)
#define PMC_IMPL_PART_PCIEX4CB_POWER_GATE_CONTROL_0_SRAM_RET_EN_FIELD                   MK_FIELD_CONST(0x1, PMC_IMPL_PART_PCIEX4CB_POWER_GATE_CONTROL_0_SRAM_RET_EN_SHIFT)
#define PMC_IMPL_PART_PCIEX4CB_POWER_GATE_CONTROL_0_SRAM_RET_EN_RANGE                   1:1
#define PMC_IMPL_PART_PCIEX4CB_POWER_GATE_CONTROL_0_SRAM_RET_EN_MSB                     MK_SHIFT_CONST(1)
#define PMC_IMPL_PART_PCIEX4CB_POWER_GATE_CONTROL_0_SRAM_RET_EN_LSB                     MK_SHIFT_CONST(1)
#define PMC_IMPL_PART_PCIEX4CB_POWER_GATE_CONTROL_0_SRAM_RET_EN_WOFFSET                 0x0
#define PMC_IMPL_PART_PCIEX4CB_POWER_GATE_CONTROL_0_SRAM_RET_EN_DEFAULT                 MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX4CB_POWER_GATE_CONTROL_0_SRAM_RET_EN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PCIEX4CB_POWER_GATE_CONTROL_0_SRAM_RET_EN_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX4CB_POWER_GATE_CONTROL_0_SRAM_RET_EN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX4CB_POWER_GATE_CONTROL_0_SRAM_RET_EN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX4CB_POWER_GATE_CONTROL_0_SRAM_RET_EN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PCIEX4CB_POWER_GATE_CONTROL_0_SRAM_RET_EN_INIT_ENUM                       OFF
#define PMC_IMPL_PART_PCIEX4CB_POWER_GATE_CONTROL_0_SRAM_RET_EN_OFF                     MK_ENUM_CONST(0)
#define PMC_IMPL_PART_PCIEX4CB_POWER_GATE_CONTROL_0_SRAM_RET_EN_ON                      MK_ENUM_CONST(1)

#define PMC_IMPL_PART_PCIEX4CB_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SHIFT                   MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_PCIEX4CB_POWER_GATE_CONTROL_0_LOGIC_SLEEP_FIELD                   MK_FIELD_CONST(0x1, PMC_IMPL_PART_PCIEX4CB_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SHIFT)
#define PMC_IMPL_PART_PCIEX4CB_POWER_GATE_CONTROL_0_LOGIC_SLEEP_RANGE                   0:0
#define PMC_IMPL_PART_PCIEX4CB_POWER_GATE_CONTROL_0_LOGIC_SLEEP_MSB                     MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_PCIEX4CB_POWER_GATE_CONTROL_0_LOGIC_SLEEP_LSB                     MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_PCIEX4CB_POWER_GATE_CONTROL_0_LOGIC_SLEEP_WOFFSET                 0x0
#define PMC_IMPL_PART_PCIEX4CB_POWER_GATE_CONTROL_0_LOGIC_SLEEP_DEFAULT                 MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PCIEX4CB_POWER_GATE_CONTROL_0_LOGIC_SLEEP_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PCIEX4CB_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX4CB_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX4CB_POWER_GATE_CONTROL_0_LOGIC_SLEEP_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX4CB_POWER_GATE_CONTROL_0_LOGIC_SLEEP_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PCIEX4CB_POWER_GATE_CONTROL_0_LOGIC_SLEEP_INIT_ENUM                       ON
#define PMC_IMPL_PART_PCIEX4CB_POWER_GATE_CONTROL_0_LOGIC_SLEEP_OFF                     MK_ENUM_CONST(0)
#define PMC_IMPL_PART_PCIEX4CB_POWER_GATE_CONTROL_0_LOGIC_SLEEP_ON                      MK_ENUM_CONST(1)


// Register PMC_IMPL_PART_PCIEX4CB_POWER_GATE_STATUS_0
#define PMC_IMPL_PART_PCIEX4CB_POWER_GATE_STATUS_0                      MK_ADDR_CONST(0x530)
#define PMC_IMPL_PART_PCIEX4CB_POWER_GATE_STATUS_0_SECURE                       0x0
#define PMC_IMPL_PART_PCIEX4CB_POWER_GATE_STATUS_0_DUAL                         0x0
#define PMC_IMPL_PART_PCIEX4CB_POWER_GATE_STATUS_0_SCR                  PG_PCIEX4CB_SCR_0
#define PMC_IMPL_PART_PCIEX4CB_POWER_GATE_STATUS_0_SCRREG                       PMC_IMPL_SCR_PG_PCIEX4CB_SCR_0
#define PMC_IMPL_PART_PCIEX4CB_POWER_GATE_STATUS_0_WORD_COUNT                   0x1
#define PMC_IMPL_PART_PCIEX4CB_POWER_GATE_STATUS_0_RESET_VAL                    MK_MASK_CONST(0x5)
#define PMC_IMPL_PART_PCIEX4CB_POWER_GATE_STATUS_0_RESET_MASK                   MK_MASK_CONST(0x7)
#define PMC_IMPL_PART_PCIEX4CB_POWER_GATE_STATUS_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX4CB_POWER_GATE_STATUS_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX4CB_POWER_GATE_STATUS_0_READ_MASK                    MK_MASK_CONST(0x7)
#define PMC_IMPL_PART_PCIEX4CB_POWER_GATE_STATUS_0_WRITE_MASK                   MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX4CB_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SHIFT                 MK_SHIFT_CONST(2)
#define PMC_IMPL_PART_PCIEX4CB_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_FIELD                 MK_FIELD_CONST(0x1, PMC_IMPL_PART_PCIEX4CB_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SHIFT)
#define PMC_IMPL_PART_PCIEX4CB_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_RANGE                 2:2
#define PMC_IMPL_PART_PCIEX4CB_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_MSB                   MK_SHIFT_CONST(2)
#define PMC_IMPL_PART_PCIEX4CB_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_LSB                   MK_SHIFT_CONST(2)
#define PMC_IMPL_PART_PCIEX4CB_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_WOFFSET                       0x0
#define PMC_IMPL_PART_PCIEX4CB_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_DEFAULT                       MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PCIEX4CB_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PCIEX4CB_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX4CB_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX4CB_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX4CB_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PCIEX4CB_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_INIT_ENUM                     ON
#define PMC_IMPL_PART_PCIEX4CB_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_OFF                   MK_ENUM_CONST(0)
#define PMC_IMPL_PART_PCIEX4CB_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_ON                    MK_ENUM_CONST(1)

#define PMC_IMPL_PART_PCIEX4CB_POWER_GATE_STATUS_0_SRAM_RET_STS_SHIFT                   MK_SHIFT_CONST(1)
#define PMC_IMPL_PART_PCIEX4CB_POWER_GATE_STATUS_0_SRAM_RET_STS_FIELD                   MK_FIELD_CONST(0x1, PMC_IMPL_PART_PCIEX4CB_POWER_GATE_STATUS_0_SRAM_RET_STS_SHIFT)
#define PMC_IMPL_PART_PCIEX4CB_POWER_GATE_STATUS_0_SRAM_RET_STS_RANGE                   1:1
#define PMC_IMPL_PART_PCIEX4CB_POWER_GATE_STATUS_0_SRAM_RET_STS_MSB                     MK_SHIFT_CONST(1)
#define PMC_IMPL_PART_PCIEX4CB_POWER_GATE_STATUS_0_SRAM_RET_STS_LSB                     MK_SHIFT_CONST(1)
#define PMC_IMPL_PART_PCIEX4CB_POWER_GATE_STATUS_0_SRAM_RET_STS_WOFFSET                 0x0
#define PMC_IMPL_PART_PCIEX4CB_POWER_GATE_STATUS_0_SRAM_RET_STS_DEFAULT                 MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX4CB_POWER_GATE_STATUS_0_SRAM_RET_STS_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PCIEX4CB_POWER_GATE_STATUS_0_SRAM_RET_STS_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX4CB_POWER_GATE_STATUS_0_SRAM_RET_STS_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX4CB_POWER_GATE_STATUS_0_SRAM_RET_STS_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX4CB_POWER_GATE_STATUS_0_SRAM_RET_STS_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PCIEX4CB_POWER_GATE_STATUS_0_SRAM_RET_STS_INIT_ENUM                       OFF
#define PMC_IMPL_PART_PCIEX4CB_POWER_GATE_STATUS_0_SRAM_RET_STS_OFF                     MK_ENUM_CONST(0)
#define PMC_IMPL_PART_PCIEX4CB_POWER_GATE_STATUS_0_SRAM_RET_STS_ON                      MK_ENUM_CONST(1)

#define PMC_IMPL_PART_PCIEX4CB_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SHIFT                        MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_PCIEX4CB_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_FIELD                        MK_FIELD_CONST(0x1, PMC_IMPL_PART_PCIEX4CB_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SHIFT)
#define PMC_IMPL_PART_PCIEX4CB_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_RANGE                        0:0
#define PMC_IMPL_PART_PCIEX4CB_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_MSB                  MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_PCIEX4CB_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_LSB                  MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_PCIEX4CB_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_WOFFSET                      0x0
#define PMC_IMPL_PART_PCIEX4CB_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_DEFAULT                      MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PCIEX4CB_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PCIEX4CB_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX4CB_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX4CB_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX4CB_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PCIEX4CB_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_INIT_ENUM                    ON
#define PMC_IMPL_PART_PCIEX4CB_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_OFF                  MK_ENUM_CONST(0)
#define PMC_IMPL_PART_PCIEX4CB_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_ON                   MK_ENUM_CONST(1)


// Register PMC_IMPL_PART_PCIEX4CB_CLAMP_CONTROL_0
#define PMC_IMPL_PART_PCIEX4CB_CLAMP_CONTROL_0                  MK_ADDR_CONST(0x534)
#define PMC_IMPL_PART_PCIEX4CB_CLAMP_CONTROL_0_SECURE                   0x0
#define PMC_IMPL_PART_PCIEX4CB_CLAMP_CONTROL_0_DUAL                     0x0
#define PMC_IMPL_PART_PCIEX4CB_CLAMP_CONTROL_0_SCR                      PG_PCIEX4CB_SCR_0
#define PMC_IMPL_PART_PCIEX4CB_CLAMP_CONTROL_0_SCRREG                   PMC_IMPL_SCR_PG_PCIEX4CB_SCR_0
#define PMC_IMPL_PART_PCIEX4CB_CLAMP_CONTROL_0_WORD_COUNT                       0x1
#define PMC_IMPL_PART_PCIEX4CB_CLAMP_CONTROL_0_RESET_VAL                        MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PCIEX4CB_CLAMP_CONTROL_0_RESET_MASK                       MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PCIEX4CB_CLAMP_CONTROL_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX4CB_CLAMP_CONTROL_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX4CB_CLAMP_CONTROL_0_READ_MASK                        MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PCIEX4CB_CLAMP_CONTROL_0_WRITE_MASK                       MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PCIEX4CB_CLAMP_CONTROL_0_CLAMP_SHIFT                      MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_PCIEX4CB_CLAMP_CONTROL_0_CLAMP_FIELD                      MK_FIELD_CONST(0x1, PMC_IMPL_PART_PCIEX4CB_CLAMP_CONTROL_0_CLAMP_SHIFT)
#define PMC_IMPL_PART_PCIEX4CB_CLAMP_CONTROL_0_CLAMP_RANGE                      0:0
#define PMC_IMPL_PART_PCIEX4CB_CLAMP_CONTROL_0_CLAMP_MSB                        MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_PCIEX4CB_CLAMP_CONTROL_0_CLAMP_LSB                        MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_PCIEX4CB_CLAMP_CONTROL_0_CLAMP_WOFFSET                    0x0
#define PMC_IMPL_PART_PCIEX4CB_CLAMP_CONTROL_0_CLAMP_DEFAULT                    MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PCIEX4CB_CLAMP_CONTROL_0_CLAMP_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PCIEX4CB_CLAMP_CONTROL_0_CLAMP_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX4CB_CLAMP_CONTROL_0_CLAMP_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX4CB_CLAMP_CONTROL_0_CLAMP_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX4CB_CLAMP_CONTROL_0_CLAMP_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PCIEX4CB_CLAMP_CONTROL_0_CLAMP_INIT_ENUM                  ON
#define PMC_IMPL_PART_PCIEX4CB_CLAMP_CONTROL_0_CLAMP_OFF                        MK_ENUM_CONST(0)
#define PMC_IMPL_PART_PCIEX4CB_CLAMP_CONTROL_0_CLAMP_ON                 MK_ENUM_CONST(1)


// Register PMC_IMPL_PART_PCIEX4CC_POWER_GATE_CONTROL_0
#define PMC_IMPL_PART_PCIEX4CC_POWER_GATE_CONTROL_0                     MK_ADDR_CONST(0x538)
#define PMC_IMPL_PART_PCIEX4CC_POWER_GATE_CONTROL_0_SECURE                      0x0
#define PMC_IMPL_PART_PCIEX4CC_POWER_GATE_CONTROL_0_DUAL                        0x0
#define PMC_IMPL_PART_PCIEX4CC_POWER_GATE_CONTROL_0_SCR                         PG_PCIEX4CC_SCR_0
#define PMC_IMPL_PART_PCIEX4CC_POWER_GATE_CONTROL_0_SCRREG                      PMC_IMPL_SCR_PG_PCIEX4CC_SCR_0
#define PMC_IMPL_PART_PCIEX4CC_POWER_GATE_CONTROL_0_WORD_COUNT                  0x1
#define PMC_IMPL_PART_PCIEX4CC_POWER_GATE_CONTROL_0_RESET_VAL                   MK_MASK_CONST(0x80000005)
#define PMC_IMPL_PART_PCIEX4CC_POWER_GATE_CONTROL_0_RESET_MASK                  MK_MASK_CONST(0x80000107)
#define PMC_IMPL_PART_PCIEX4CC_POWER_GATE_CONTROL_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX4CC_POWER_GATE_CONTROL_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX4CC_POWER_GATE_CONTROL_0_READ_MASK                   MK_MASK_CONST(0x80000107)
#define PMC_IMPL_PART_PCIEX4CC_POWER_GATE_CONTROL_0_WRITE_MASK                  MK_MASK_CONST(0x80000105)
#define PMC_IMPL_PART_PCIEX4CC_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SHIFT                   MK_SHIFT_CONST(31)
#define PMC_IMPL_PART_PCIEX4CC_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_FIELD                   MK_FIELD_CONST(0x1, PMC_IMPL_PART_PCIEX4CC_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SHIFT)
#define PMC_IMPL_PART_PCIEX4CC_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_RANGE                   31:31
#define PMC_IMPL_PART_PCIEX4CC_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_MSB                     MK_SHIFT_CONST(31)
#define PMC_IMPL_PART_PCIEX4CC_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_LSB                     MK_SHIFT_CONST(31)
#define PMC_IMPL_PART_PCIEX4CC_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_WOFFSET                 0x0
#define PMC_IMPL_PART_PCIEX4CC_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_DEFAULT                 MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PCIEX4CC_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PCIEX4CC_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX4CC_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX4CC_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX4CC_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PCIEX4CC_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_INIT_ENUM                       ENABLE
#define PMC_IMPL_PART_PCIEX4CC_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_DISABLE                 MK_ENUM_CONST(0)
#define PMC_IMPL_PART_PCIEX4CC_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_ENABLE                  MK_ENUM_CONST(1)

#define PMC_IMPL_PART_PCIEX4CC_POWER_GATE_CONTROL_0_START_SHIFT                 MK_SHIFT_CONST(8)
#define PMC_IMPL_PART_PCIEX4CC_POWER_GATE_CONTROL_0_START_FIELD                 MK_FIELD_CONST(0x1, PMC_IMPL_PART_PCIEX4CC_POWER_GATE_CONTROL_0_START_SHIFT)
#define PMC_IMPL_PART_PCIEX4CC_POWER_GATE_CONTROL_0_START_RANGE                 8:8
#define PMC_IMPL_PART_PCIEX4CC_POWER_GATE_CONTROL_0_START_MSB                   MK_SHIFT_CONST(8)
#define PMC_IMPL_PART_PCIEX4CC_POWER_GATE_CONTROL_0_START_LSB                   MK_SHIFT_CONST(8)
#define PMC_IMPL_PART_PCIEX4CC_POWER_GATE_CONTROL_0_START_WOFFSET                       0x0
#define PMC_IMPL_PART_PCIEX4CC_POWER_GATE_CONTROL_0_START_DEFAULT                       MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX4CC_POWER_GATE_CONTROL_0_START_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PCIEX4CC_POWER_GATE_CONTROL_0_START_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX4CC_POWER_GATE_CONTROL_0_START_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX4CC_POWER_GATE_CONTROL_0_START_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX4CC_POWER_GATE_CONTROL_0_START_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PCIEX4CC_POWER_GATE_CONTROL_0_START_INIT_ENUM                     DONE
#define PMC_IMPL_PART_PCIEX4CC_POWER_GATE_CONTROL_0_START_DONE                  MK_ENUM_CONST(0)
#define PMC_IMPL_PART_PCIEX4CC_POWER_GATE_CONTROL_0_START_PENDING                       MK_ENUM_CONST(1)

#define PMC_IMPL_PART_PCIEX4CC_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SHIFT                 MK_SHIFT_CONST(2)
#define PMC_IMPL_PART_PCIEX4CC_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_FIELD                 MK_FIELD_CONST(0x1, PMC_IMPL_PART_PCIEX4CC_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SHIFT)
#define PMC_IMPL_PART_PCIEX4CC_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_RANGE                 2:2
#define PMC_IMPL_PART_PCIEX4CC_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_MSB                   MK_SHIFT_CONST(2)
#define PMC_IMPL_PART_PCIEX4CC_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_LSB                   MK_SHIFT_CONST(2)
#define PMC_IMPL_PART_PCIEX4CC_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_WOFFSET                       0x0
#define PMC_IMPL_PART_PCIEX4CC_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_DEFAULT                       MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PCIEX4CC_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PCIEX4CC_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX4CC_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX4CC_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX4CC_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PCIEX4CC_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_INIT_ENUM                     ON
#define PMC_IMPL_PART_PCIEX4CC_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_OFF                   MK_ENUM_CONST(0)
#define PMC_IMPL_PART_PCIEX4CC_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_ON                    MK_ENUM_CONST(1)

#define PMC_IMPL_PART_PCIEX4CC_POWER_GATE_CONTROL_0_SRAM_RET_EN_SHIFT                   MK_SHIFT_CONST(1)
#define PMC_IMPL_PART_PCIEX4CC_POWER_GATE_CONTROL_0_SRAM_RET_EN_FIELD                   MK_FIELD_CONST(0x1, PMC_IMPL_PART_PCIEX4CC_POWER_GATE_CONTROL_0_SRAM_RET_EN_SHIFT)
#define PMC_IMPL_PART_PCIEX4CC_POWER_GATE_CONTROL_0_SRAM_RET_EN_RANGE                   1:1
#define PMC_IMPL_PART_PCIEX4CC_POWER_GATE_CONTROL_0_SRAM_RET_EN_MSB                     MK_SHIFT_CONST(1)
#define PMC_IMPL_PART_PCIEX4CC_POWER_GATE_CONTROL_0_SRAM_RET_EN_LSB                     MK_SHIFT_CONST(1)
#define PMC_IMPL_PART_PCIEX4CC_POWER_GATE_CONTROL_0_SRAM_RET_EN_WOFFSET                 0x0
#define PMC_IMPL_PART_PCIEX4CC_POWER_GATE_CONTROL_0_SRAM_RET_EN_DEFAULT                 MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX4CC_POWER_GATE_CONTROL_0_SRAM_RET_EN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PCIEX4CC_POWER_GATE_CONTROL_0_SRAM_RET_EN_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX4CC_POWER_GATE_CONTROL_0_SRAM_RET_EN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX4CC_POWER_GATE_CONTROL_0_SRAM_RET_EN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX4CC_POWER_GATE_CONTROL_0_SRAM_RET_EN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PCIEX4CC_POWER_GATE_CONTROL_0_SRAM_RET_EN_INIT_ENUM                       OFF
#define PMC_IMPL_PART_PCIEX4CC_POWER_GATE_CONTROL_0_SRAM_RET_EN_OFF                     MK_ENUM_CONST(0)
#define PMC_IMPL_PART_PCIEX4CC_POWER_GATE_CONTROL_0_SRAM_RET_EN_ON                      MK_ENUM_CONST(1)

#define PMC_IMPL_PART_PCIEX4CC_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SHIFT                   MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_PCIEX4CC_POWER_GATE_CONTROL_0_LOGIC_SLEEP_FIELD                   MK_FIELD_CONST(0x1, PMC_IMPL_PART_PCIEX4CC_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SHIFT)
#define PMC_IMPL_PART_PCIEX4CC_POWER_GATE_CONTROL_0_LOGIC_SLEEP_RANGE                   0:0
#define PMC_IMPL_PART_PCIEX4CC_POWER_GATE_CONTROL_0_LOGIC_SLEEP_MSB                     MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_PCIEX4CC_POWER_GATE_CONTROL_0_LOGIC_SLEEP_LSB                     MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_PCIEX4CC_POWER_GATE_CONTROL_0_LOGIC_SLEEP_WOFFSET                 0x0
#define PMC_IMPL_PART_PCIEX4CC_POWER_GATE_CONTROL_0_LOGIC_SLEEP_DEFAULT                 MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PCIEX4CC_POWER_GATE_CONTROL_0_LOGIC_SLEEP_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PCIEX4CC_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX4CC_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX4CC_POWER_GATE_CONTROL_0_LOGIC_SLEEP_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX4CC_POWER_GATE_CONTROL_0_LOGIC_SLEEP_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PCIEX4CC_POWER_GATE_CONTROL_0_LOGIC_SLEEP_INIT_ENUM                       ON
#define PMC_IMPL_PART_PCIEX4CC_POWER_GATE_CONTROL_0_LOGIC_SLEEP_OFF                     MK_ENUM_CONST(0)
#define PMC_IMPL_PART_PCIEX4CC_POWER_GATE_CONTROL_0_LOGIC_SLEEP_ON                      MK_ENUM_CONST(1)


// Register PMC_IMPL_PART_PCIEX4CC_POWER_GATE_STATUS_0
#define PMC_IMPL_PART_PCIEX4CC_POWER_GATE_STATUS_0                      MK_ADDR_CONST(0x53c)
#define PMC_IMPL_PART_PCIEX4CC_POWER_GATE_STATUS_0_SECURE                       0x0
#define PMC_IMPL_PART_PCIEX4CC_POWER_GATE_STATUS_0_DUAL                         0x0
#define PMC_IMPL_PART_PCIEX4CC_POWER_GATE_STATUS_0_SCR                  PG_PCIEX4CC_SCR_0
#define PMC_IMPL_PART_PCIEX4CC_POWER_GATE_STATUS_0_SCRREG                       PMC_IMPL_SCR_PG_PCIEX4CC_SCR_0
#define PMC_IMPL_PART_PCIEX4CC_POWER_GATE_STATUS_0_WORD_COUNT                   0x1
#define PMC_IMPL_PART_PCIEX4CC_POWER_GATE_STATUS_0_RESET_VAL                    MK_MASK_CONST(0x5)
#define PMC_IMPL_PART_PCIEX4CC_POWER_GATE_STATUS_0_RESET_MASK                   MK_MASK_CONST(0x7)
#define PMC_IMPL_PART_PCIEX4CC_POWER_GATE_STATUS_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX4CC_POWER_GATE_STATUS_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX4CC_POWER_GATE_STATUS_0_READ_MASK                    MK_MASK_CONST(0x7)
#define PMC_IMPL_PART_PCIEX4CC_POWER_GATE_STATUS_0_WRITE_MASK                   MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX4CC_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SHIFT                 MK_SHIFT_CONST(2)
#define PMC_IMPL_PART_PCIEX4CC_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_FIELD                 MK_FIELD_CONST(0x1, PMC_IMPL_PART_PCIEX4CC_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SHIFT)
#define PMC_IMPL_PART_PCIEX4CC_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_RANGE                 2:2
#define PMC_IMPL_PART_PCIEX4CC_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_MSB                   MK_SHIFT_CONST(2)
#define PMC_IMPL_PART_PCIEX4CC_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_LSB                   MK_SHIFT_CONST(2)
#define PMC_IMPL_PART_PCIEX4CC_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_WOFFSET                       0x0
#define PMC_IMPL_PART_PCIEX4CC_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_DEFAULT                       MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PCIEX4CC_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PCIEX4CC_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX4CC_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX4CC_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX4CC_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PCIEX4CC_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_INIT_ENUM                     ON
#define PMC_IMPL_PART_PCIEX4CC_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_OFF                   MK_ENUM_CONST(0)
#define PMC_IMPL_PART_PCIEX4CC_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_ON                    MK_ENUM_CONST(1)

#define PMC_IMPL_PART_PCIEX4CC_POWER_GATE_STATUS_0_SRAM_RET_STS_SHIFT                   MK_SHIFT_CONST(1)
#define PMC_IMPL_PART_PCIEX4CC_POWER_GATE_STATUS_0_SRAM_RET_STS_FIELD                   MK_FIELD_CONST(0x1, PMC_IMPL_PART_PCIEX4CC_POWER_GATE_STATUS_0_SRAM_RET_STS_SHIFT)
#define PMC_IMPL_PART_PCIEX4CC_POWER_GATE_STATUS_0_SRAM_RET_STS_RANGE                   1:1
#define PMC_IMPL_PART_PCIEX4CC_POWER_GATE_STATUS_0_SRAM_RET_STS_MSB                     MK_SHIFT_CONST(1)
#define PMC_IMPL_PART_PCIEX4CC_POWER_GATE_STATUS_0_SRAM_RET_STS_LSB                     MK_SHIFT_CONST(1)
#define PMC_IMPL_PART_PCIEX4CC_POWER_GATE_STATUS_0_SRAM_RET_STS_WOFFSET                 0x0
#define PMC_IMPL_PART_PCIEX4CC_POWER_GATE_STATUS_0_SRAM_RET_STS_DEFAULT                 MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX4CC_POWER_GATE_STATUS_0_SRAM_RET_STS_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PCIEX4CC_POWER_GATE_STATUS_0_SRAM_RET_STS_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX4CC_POWER_GATE_STATUS_0_SRAM_RET_STS_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX4CC_POWER_GATE_STATUS_0_SRAM_RET_STS_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX4CC_POWER_GATE_STATUS_0_SRAM_RET_STS_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PCIEX4CC_POWER_GATE_STATUS_0_SRAM_RET_STS_INIT_ENUM                       OFF
#define PMC_IMPL_PART_PCIEX4CC_POWER_GATE_STATUS_0_SRAM_RET_STS_OFF                     MK_ENUM_CONST(0)
#define PMC_IMPL_PART_PCIEX4CC_POWER_GATE_STATUS_0_SRAM_RET_STS_ON                      MK_ENUM_CONST(1)

#define PMC_IMPL_PART_PCIEX4CC_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SHIFT                        MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_PCIEX4CC_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_FIELD                        MK_FIELD_CONST(0x1, PMC_IMPL_PART_PCIEX4CC_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SHIFT)
#define PMC_IMPL_PART_PCIEX4CC_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_RANGE                        0:0
#define PMC_IMPL_PART_PCIEX4CC_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_MSB                  MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_PCIEX4CC_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_LSB                  MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_PCIEX4CC_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_WOFFSET                      0x0
#define PMC_IMPL_PART_PCIEX4CC_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_DEFAULT                      MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PCIEX4CC_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PCIEX4CC_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX4CC_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX4CC_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX4CC_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PCIEX4CC_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_INIT_ENUM                    ON
#define PMC_IMPL_PART_PCIEX4CC_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_OFF                  MK_ENUM_CONST(0)
#define PMC_IMPL_PART_PCIEX4CC_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_ON                   MK_ENUM_CONST(1)


// Register PMC_IMPL_PART_PCIEX4CC_CLAMP_CONTROL_0
#define PMC_IMPL_PART_PCIEX4CC_CLAMP_CONTROL_0                  MK_ADDR_CONST(0x540)
#define PMC_IMPL_PART_PCIEX4CC_CLAMP_CONTROL_0_SECURE                   0x0
#define PMC_IMPL_PART_PCIEX4CC_CLAMP_CONTROL_0_DUAL                     0x0
#define PMC_IMPL_PART_PCIEX4CC_CLAMP_CONTROL_0_SCR                      PG_PCIEX4CC_SCR_0
#define PMC_IMPL_PART_PCIEX4CC_CLAMP_CONTROL_0_SCRREG                   PMC_IMPL_SCR_PG_PCIEX4CC_SCR_0
#define PMC_IMPL_PART_PCIEX4CC_CLAMP_CONTROL_0_WORD_COUNT                       0x1
#define PMC_IMPL_PART_PCIEX4CC_CLAMP_CONTROL_0_RESET_VAL                        MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PCIEX4CC_CLAMP_CONTROL_0_RESET_MASK                       MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PCIEX4CC_CLAMP_CONTROL_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX4CC_CLAMP_CONTROL_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX4CC_CLAMP_CONTROL_0_READ_MASK                        MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PCIEX4CC_CLAMP_CONTROL_0_WRITE_MASK                       MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PCIEX4CC_CLAMP_CONTROL_0_CLAMP_SHIFT                      MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_PCIEX4CC_CLAMP_CONTROL_0_CLAMP_FIELD                      MK_FIELD_CONST(0x1, PMC_IMPL_PART_PCIEX4CC_CLAMP_CONTROL_0_CLAMP_SHIFT)
#define PMC_IMPL_PART_PCIEX4CC_CLAMP_CONTROL_0_CLAMP_RANGE                      0:0
#define PMC_IMPL_PART_PCIEX4CC_CLAMP_CONTROL_0_CLAMP_MSB                        MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_PCIEX4CC_CLAMP_CONTROL_0_CLAMP_LSB                        MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_PCIEX4CC_CLAMP_CONTROL_0_CLAMP_WOFFSET                    0x0
#define PMC_IMPL_PART_PCIEX4CC_CLAMP_CONTROL_0_CLAMP_DEFAULT                    MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PCIEX4CC_CLAMP_CONTROL_0_CLAMP_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PCIEX4CC_CLAMP_CONTROL_0_CLAMP_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX4CC_CLAMP_CONTROL_0_CLAMP_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX4CC_CLAMP_CONTROL_0_CLAMP_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX4CC_CLAMP_CONTROL_0_CLAMP_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PCIEX4CC_CLAMP_CONTROL_0_CLAMP_INIT_ENUM                  ON
#define PMC_IMPL_PART_PCIEX4CC_CLAMP_CONTROL_0_CLAMP_OFF                        MK_ENUM_CONST(0)
#define PMC_IMPL_PART_PCIEX4CC_CLAMP_CONTROL_0_CLAMP_ON                 MK_ENUM_CONST(1)


// Register PMC_IMPL_PART_PVA_POWER_GATE_CONTROL_0
#define PMC_IMPL_PART_PVA_POWER_GATE_CONTROL_0                  MK_ADDR_CONST(0x544)
#define PMC_IMPL_PART_PVA_POWER_GATE_CONTROL_0_SECURE                   0x0
#define PMC_IMPL_PART_PVA_POWER_GATE_CONTROL_0_DUAL                     0x0
#define PMC_IMPL_PART_PVA_POWER_GATE_CONTROL_0_SCR                      PG_PVA_SCR_0
#define PMC_IMPL_PART_PVA_POWER_GATE_CONTROL_0_SCRREG                   PMC_IMPL_SCR_PG_PVA_SCR_0
#define PMC_IMPL_PART_PVA_POWER_GATE_CONTROL_0_WORD_COUNT                       0x1
#define PMC_IMPL_PART_PVA_POWER_GATE_CONTROL_0_RESET_VAL                        MK_MASK_CONST(0x80000005)
#define PMC_IMPL_PART_PVA_POWER_GATE_CONTROL_0_RESET_MASK                       MK_MASK_CONST(0x80000107)
#define PMC_IMPL_PART_PVA_POWER_GATE_CONTROL_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PVA_POWER_GATE_CONTROL_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PVA_POWER_GATE_CONTROL_0_READ_MASK                        MK_MASK_CONST(0x80000107)
#define PMC_IMPL_PART_PVA_POWER_GATE_CONTROL_0_WRITE_MASK                       MK_MASK_CONST(0x80000105)
#define PMC_IMPL_PART_PVA_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SHIFT                        MK_SHIFT_CONST(31)
#define PMC_IMPL_PART_PVA_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_FIELD                        MK_FIELD_CONST(0x1, PMC_IMPL_PART_PVA_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SHIFT)
#define PMC_IMPL_PART_PVA_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_RANGE                        31:31
#define PMC_IMPL_PART_PVA_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_MSB                  MK_SHIFT_CONST(31)
#define PMC_IMPL_PART_PVA_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_LSB                  MK_SHIFT_CONST(31)
#define PMC_IMPL_PART_PVA_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_WOFFSET                      0x0
#define PMC_IMPL_PART_PVA_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_DEFAULT                      MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PVA_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PVA_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PVA_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PVA_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PVA_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PVA_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_INIT_ENUM                    ENABLE
#define PMC_IMPL_PART_PVA_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_DISABLE                      MK_ENUM_CONST(0)
#define PMC_IMPL_PART_PVA_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_ENABLE                       MK_ENUM_CONST(1)

#define PMC_IMPL_PART_PVA_POWER_GATE_CONTROL_0_START_SHIFT                      MK_SHIFT_CONST(8)
#define PMC_IMPL_PART_PVA_POWER_GATE_CONTROL_0_START_FIELD                      MK_FIELD_CONST(0x1, PMC_IMPL_PART_PVA_POWER_GATE_CONTROL_0_START_SHIFT)
#define PMC_IMPL_PART_PVA_POWER_GATE_CONTROL_0_START_RANGE                      8:8
#define PMC_IMPL_PART_PVA_POWER_GATE_CONTROL_0_START_MSB                        MK_SHIFT_CONST(8)
#define PMC_IMPL_PART_PVA_POWER_GATE_CONTROL_0_START_LSB                        MK_SHIFT_CONST(8)
#define PMC_IMPL_PART_PVA_POWER_GATE_CONTROL_0_START_WOFFSET                    0x0
#define PMC_IMPL_PART_PVA_POWER_GATE_CONTROL_0_START_DEFAULT                    MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PVA_POWER_GATE_CONTROL_0_START_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PVA_POWER_GATE_CONTROL_0_START_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PVA_POWER_GATE_CONTROL_0_START_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PVA_POWER_GATE_CONTROL_0_START_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PVA_POWER_GATE_CONTROL_0_START_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PVA_POWER_GATE_CONTROL_0_START_INIT_ENUM                  DONE
#define PMC_IMPL_PART_PVA_POWER_GATE_CONTROL_0_START_DONE                       MK_ENUM_CONST(0)
#define PMC_IMPL_PART_PVA_POWER_GATE_CONTROL_0_START_PENDING                    MK_ENUM_CONST(1)

#define PMC_IMPL_PART_PVA_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SHIFT                      MK_SHIFT_CONST(2)
#define PMC_IMPL_PART_PVA_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_FIELD                      MK_FIELD_CONST(0x1, PMC_IMPL_PART_PVA_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SHIFT)
#define PMC_IMPL_PART_PVA_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_RANGE                      2:2
#define PMC_IMPL_PART_PVA_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_MSB                        MK_SHIFT_CONST(2)
#define PMC_IMPL_PART_PVA_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_LSB                        MK_SHIFT_CONST(2)
#define PMC_IMPL_PART_PVA_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_WOFFSET                    0x0
#define PMC_IMPL_PART_PVA_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_DEFAULT                    MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PVA_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PVA_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PVA_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PVA_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PVA_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PVA_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_INIT_ENUM                  ON
#define PMC_IMPL_PART_PVA_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_OFF                        MK_ENUM_CONST(0)
#define PMC_IMPL_PART_PVA_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_ON                 MK_ENUM_CONST(1)

#define PMC_IMPL_PART_PVA_POWER_GATE_CONTROL_0_SRAM_RET_EN_SHIFT                        MK_SHIFT_CONST(1)
#define PMC_IMPL_PART_PVA_POWER_GATE_CONTROL_0_SRAM_RET_EN_FIELD                        MK_FIELD_CONST(0x1, PMC_IMPL_PART_PVA_POWER_GATE_CONTROL_0_SRAM_RET_EN_SHIFT)
#define PMC_IMPL_PART_PVA_POWER_GATE_CONTROL_0_SRAM_RET_EN_RANGE                        1:1
#define PMC_IMPL_PART_PVA_POWER_GATE_CONTROL_0_SRAM_RET_EN_MSB                  MK_SHIFT_CONST(1)
#define PMC_IMPL_PART_PVA_POWER_GATE_CONTROL_0_SRAM_RET_EN_LSB                  MK_SHIFT_CONST(1)
#define PMC_IMPL_PART_PVA_POWER_GATE_CONTROL_0_SRAM_RET_EN_WOFFSET                      0x0
#define PMC_IMPL_PART_PVA_POWER_GATE_CONTROL_0_SRAM_RET_EN_DEFAULT                      MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PVA_POWER_GATE_CONTROL_0_SRAM_RET_EN_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PVA_POWER_GATE_CONTROL_0_SRAM_RET_EN_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PVA_POWER_GATE_CONTROL_0_SRAM_RET_EN_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PVA_POWER_GATE_CONTROL_0_SRAM_RET_EN_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PVA_POWER_GATE_CONTROL_0_SRAM_RET_EN_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PVA_POWER_GATE_CONTROL_0_SRAM_RET_EN_INIT_ENUM                    OFF
#define PMC_IMPL_PART_PVA_POWER_GATE_CONTROL_0_SRAM_RET_EN_OFF                  MK_ENUM_CONST(0)
#define PMC_IMPL_PART_PVA_POWER_GATE_CONTROL_0_SRAM_RET_EN_ON                   MK_ENUM_CONST(1)

#define PMC_IMPL_PART_PVA_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SHIFT                        MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_PVA_POWER_GATE_CONTROL_0_LOGIC_SLEEP_FIELD                        MK_FIELD_CONST(0x1, PMC_IMPL_PART_PVA_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SHIFT)
#define PMC_IMPL_PART_PVA_POWER_GATE_CONTROL_0_LOGIC_SLEEP_RANGE                        0:0
#define PMC_IMPL_PART_PVA_POWER_GATE_CONTROL_0_LOGIC_SLEEP_MSB                  MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_PVA_POWER_GATE_CONTROL_0_LOGIC_SLEEP_LSB                  MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_PVA_POWER_GATE_CONTROL_0_LOGIC_SLEEP_WOFFSET                      0x0
#define PMC_IMPL_PART_PVA_POWER_GATE_CONTROL_0_LOGIC_SLEEP_DEFAULT                      MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PVA_POWER_GATE_CONTROL_0_LOGIC_SLEEP_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PVA_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PVA_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PVA_POWER_GATE_CONTROL_0_LOGIC_SLEEP_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PVA_POWER_GATE_CONTROL_0_LOGIC_SLEEP_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PVA_POWER_GATE_CONTROL_0_LOGIC_SLEEP_INIT_ENUM                    ON
#define PMC_IMPL_PART_PVA_POWER_GATE_CONTROL_0_LOGIC_SLEEP_OFF                  MK_ENUM_CONST(0)
#define PMC_IMPL_PART_PVA_POWER_GATE_CONTROL_0_LOGIC_SLEEP_ON                   MK_ENUM_CONST(1)


// Register PMC_IMPL_PART_PVA_POWER_GATE_STATUS_0
#define PMC_IMPL_PART_PVA_POWER_GATE_STATUS_0                   MK_ADDR_CONST(0x548)
#define PMC_IMPL_PART_PVA_POWER_GATE_STATUS_0_SECURE                    0x0
#define PMC_IMPL_PART_PVA_POWER_GATE_STATUS_0_DUAL                      0x0
#define PMC_IMPL_PART_PVA_POWER_GATE_STATUS_0_SCR                       PG_PVA_SCR_0
#define PMC_IMPL_PART_PVA_POWER_GATE_STATUS_0_SCRREG                    PMC_IMPL_SCR_PG_PVA_SCR_0
#define PMC_IMPL_PART_PVA_POWER_GATE_STATUS_0_WORD_COUNT                        0x1
#define PMC_IMPL_PART_PVA_POWER_GATE_STATUS_0_RESET_VAL                         MK_MASK_CONST(0x5)
#define PMC_IMPL_PART_PVA_POWER_GATE_STATUS_0_RESET_MASK                        MK_MASK_CONST(0x7)
#define PMC_IMPL_PART_PVA_POWER_GATE_STATUS_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PVA_POWER_GATE_STATUS_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PVA_POWER_GATE_STATUS_0_READ_MASK                         MK_MASK_CONST(0x7)
#define PMC_IMPL_PART_PVA_POWER_GATE_STATUS_0_WRITE_MASK                        MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PVA_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SHIFT                      MK_SHIFT_CONST(2)
#define PMC_IMPL_PART_PVA_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_FIELD                      MK_FIELD_CONST(0x1, PMC_IMPL_PART_PVA_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SHIFT)
#define PMC_IMPL_PART_PVA_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_RANGE                      2:2
#define PMC_IMPL_PART_PVA_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_MSB                        MK_SHIFT_CONST(2)
#define PMC_IMPL_PART_PVA_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_LSB                        MK_SHIFT_CONST(2)
#define PMC_IMPL_PART_PVA_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_WOFFSET                    0x0
#define PMC_IMPL_PART_PVA_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_DEFAULT                    MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PVA_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PVA_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PVA_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PVA_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PVA_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PVA_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_INIT_ENUM                  ON
#define PMC_IMPL_PART_PVA_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_OFF                        MK_ENUM_CONST(0)
#define PMC_IMPL_PART_PVA_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_ON                 MK_ENUM_CONST(1)

#define PMC_IMPL_PART_PVA_POWER_GATE_STATUS_0_SRAM_RET_STS_SHIFT                        MK_SHIFT_CONST(1)
#define PMC_IMPL_PART_PVA_POWER_GATE_STATUS_0_SRAM_RET_STS_FIELD                        MK_FIELD_CONST(0x1, PMC_IMPL_PART_PVA_POWER_GATE_STATUS_0_SRAM_RET_STS_SHIFT)
#define PMC_IMPL_PART_PVA_POWER_GATE_STATUS_0_SRAM_RET_STS_RANGE                        1:1
#define PMC_IMPL_PART_PVA_POWER_GATE_STATUS_0_SRAM_RET_STS_MSB                  MK_SHIFT_CONST(1)
#define PMC_IMPL_PART_PVA_POWER_GATE_STATUS_0_SRAM_RET_STS_LSB                  MK_SHIFT_CONST(1)
#define PMC_IMPL_PART_PVA_POWER_GATE_STATUS_0_SRAM_RET_STS_WOFFSET                      0x0
#define PMC_IMPL_PART_PVA_POWER_GATE_STATUS_0_SRAM_RET_STS_DEFAULT                      MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PVA_POWER_GATE_STATUS_0_SRAM_RET_STS_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PVA_POWER_GATE_STATUS_0_SRAM_RET_STS_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PVA_POWER_GATE_STATUS_0_SRAM_RET_STS_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PVA_POWER_GATE_STATUS_0_SRAM_RET_STS_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PVA_POWER_GATE_STATUS_0_SRAM_RET_STS_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PVA_POWER_GATE_STATUS_0_SRAM_RET_STS_INIT_ENUM                    OFF
#define PMC_IMPL_PART_PVA_POWER_GATE_STATUS_0_SRAM_RET_STS_OFF                  MK_ENUM_CONST(0)
#define PMC_IMPL_PART_PVA_POWER_GATE_STATUS_0_SRAM_RET_STS_ON                   MK_ENUM_CONST(1)

#define PMC_IMPL_PART_PVA_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SHIFT                     MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_PVA_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_FIELD                     MK_FIELD_CONST(0x1, PMC_IMPL_PART_PVA_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SHIFT)
#define PMC_IMPL_PART_PVA_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_RANGE                     0:0
#define PMC_IMPL_PART_PVA_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_MSB                       MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_PVA_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_LSB                       MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_PVA_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_WOFFSET                   0x0
#define PMC_IMPL_PART_PVA_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_DEFAULT                   MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PVA_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PVA_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PVA_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PVA_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PVA_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PVA_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_INIT_ENUM                 ON
#define PMC_IMPL_PART_PVA_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_OFF                       MK_ENUM_CONST(0)
#define PMC_IMPL_PART_PVA_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_ON                        MK_ENUM_CONST(1)


// Register PMC_IMPL_PART_PVA_CLAMP_CONTROL_0
#define PMC_IMPL_PART_PVA_CLAMP_CONTROL_0                       MK_ADDR_CONST(0x54c)
#define PMC_IMPL_PART_PVA_CLAMP_CONTROL_0_SECURE                        0x0
#define PMC_IMPL_PART_PVA_CLAMP_CONTROL_0_DUAL                  0x0
#define PMC_IMPL_PART_PVA_CLAMP_CONTROL_0_SCR                   PG_PVA_SCR_0
#define PMC_IMPL_PART_PVA_CLAMP_CONTROL_0_SCRREG                        PMC_IMPL_SCR_PG_PVA_SCR_0
#define PMC_IMPL_PART_PVA_CLAMP_CONTROL_0_WORD_COUNT                    0x1
#define PMC_IMPL_PART_PVA_CLAMP_CONTROL_0_RESET_VAL                     MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PVA_CLAMP_CONTROL_0_RESET_MASK                    MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PVA_CLAMP_CONTROL_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PVA_CLAMP_CONTROL_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PVA_CLAMP_CONTROL_0_READ_MASK                     MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PVA_CLAMP_CONTROL_0_WRITE_MASK                    MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PVA_CLAMP_CONTROL_0_CLAMP_SHIFT                   MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_PVA_CLAMP_CONTROL_0_CLAMP_FIELD                   MK_FIELD_CONST(0x1, PMC_IMPL_PART_PVA_CLAMP_CONTROL_0_CLAMP_SHIFT)
#define PMC_IMPL_PART_PVA_CLAMP_CONTROL_0_CLAMP_RANGE                   0:0
#define PMC_IMPL_PART_PVA_CLAMP_CONTROL_0_CLAMP_MSB                     MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_PVA_CLAMP_CONTROL_0_CLAMP_LSB                     MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_PVA_CLAMP_CONTROL_0_CLAMP_WOFFSET                 0x0
#define PMC_IMPL_PART_PVA_CLAMP_CONTROL_0_CLAMP_DEFAULT                 MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PVA_CLAMP_CONTROL_0_CLAMP_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PVA_CLAMP_CONTROL_0_CLAMP_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PVA_CLAMP_CONTROL_0_CLAMP_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PVA_CLAMP_CONTROL_0_CLAMP_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PVA_CLAMP_CONTROL_0_CLAMP_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PVA_CLAMP_CONTROL_0_CLAMP_INIT_ENUM                       ON
#define PMC_IMPL_PART_PVA_CLAMP_CONTROL_0_CLAMP_OFF                     MK_ENUM_CONST(0)
#define PMC_IMPL_PART_PVA_CLAMP_CONTROL_0_CLAMP_ON                      MK_ENUM_CONST(1)


// Register PMC_IMPL_PART_OFA_POWER_GATE_CONTROL_0
#define PMC_IMPL_PART_OFA_POWER_GATE_CONTROL_0                  MK_ADDR_CONST(0x550)
#define PMC_IMPL_PART_OFA_POWER_GATE_CONTROL_0_SECURE                   0x0
#define PMC_IMPL_PART_OFA_POWER_GATE_CONTROL_0_DUAL                     0x0
#define PMC_IMPL_PART_OFA_POWER_GATE_CONTROL_0_SCR                      PG_OFA_SCR_0
#define PMC_IMPL_PART_OFA_POWER_GATE_CONTROL_0_SCRREG                   PMC_IMPL_SCR_PG_OFA_SCR_0
#define PMC_IMPL_PART_OFA_POWER_GATE_CONTROL_0_WORD_COUNT                       0x1
#define PMC_IMPL_PART_OFA_POWER_GATE_CONTROL_0_RESET_VAL                        MK_MASK_CONST(0x80000005)
#define PMC_IMPL_PART_OFA_POWER_GATE_CONTROL_0_RESET_MASK                       MK_MASK_CONST(0x80000107)
#define PMC_IMPL_PART_OFA_POWER_GATE_CONTROL_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_OFA_POWER_GATE_CONTROL_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_OFA_POWER_GATE_CONTROL_0_READ_MASK                        MK_MASK_CONST(0x80000107)
#define PMC_IMPL_PART_OFA_POWER_GATE_CONTROL_0_WRITE_MASK                       MK_MASK_CONST(0x80000105)
#define PMC_IMPL_PART_OFA_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SHIFT                        MK_SHIFT_CONST(31)
#define PMC_IMPL_PART_OFA_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_FIELD                        MK_FIELD_CONST(0x1, PMC_IMPL_PART_OFA_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SHIFT)
#define PMC_IMPL_PART_OFA_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_RANGE                        31:31
#define PMC_IMPL_PART_OFA_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_MSB                  MK_SHIFT_CONST(31)
#define PMC_IMPL_PART_OFA_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_LSB                  MK_SHIFT_CONST(31)
#define PMC_IMPL_PART_OFA_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_WOFFSET                      0x0
#define PMC_IMPL_PART_OFA_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_DEFAULT                      MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_OFA_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_OFA_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_OFA_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_OFA_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_OFA_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_OFA_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_INIT_ENUM                    ENABLE
#define PMC_IMPL_PART_OFA_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_DISABLE                      MK_ENUM_CONST(0)
#define PMC_IMPL_PART_OFA_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_ENABLE                       MK_ENUM_CONST(1)

#define PMC_IMPL_PART_OFA_POWER_GATE_CONTROL_0_START_SHIFT                      MK_SHIFT_CONST(8)
#define PMC_IMPL_PART_OFA_POWER_GATE_CONTROL_0_START_FIELD                      MK_FIELD_CONST(0x1, PMC_IMPL_PART_OFA_POWER_GATE_CONTROL_0_START_SHIFT)
#define PMC_IMPL_PART_OFA_POWER_GATE_CONTROL_0_START_RANGE                      8:8
#define PMC_IMPL_PART_OFA_POWER_GATE_CONTROL_0_START_MSB                        MK_SHIFT_CONST(8)
#define PMC_IMPL_PART_OFA_POWER_GATE_CONTROL_0_START_LSB                        MK_SHIFT_CONST(8)
#define PMC_IMPL_PART_OFA_POWER_GATE_CONTROL_0_START_WOFFSET                    0x0
#define PMC_IMPL_PART_OFA_POWER_GATE_CONTROL_0_START_DEFAULT                    MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_OFA_POWER_GATE_CONTROL_0_START_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_OFA_POWER_GATE_CONTROL_0_START_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_OFA_POWER_GATE_CONTROL_0_START_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_OFA_POWER_GATE_CONTROL_0_START_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_OFA_POWER_GATE_CONTROL_0_START_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_OFA_POWER_GATE_CONTROL_0_START_INIT_ENUM                  DONE
#define PMC_IMPL_PART_OFA_POWER_GATE_CONTROL_0_START_DONE                       MK_ENUM_CONST(0)
#define PMC_IMPL_PART_OFA_POWER_GATE_CONTROL_0_START_PENDING                    MK_ENUM_CONST(1)

#define PMC_IMPL_PART_OFA_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SHIFT                      MK_SHIFT_CONST(2)
#define PMC_IMPL_PART_OFA_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_FIELD                      MK_FIELD_CONST(0x1, PMC_IMPL_PART_OFA_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SHIFT)
#define PMC_IMPL_PART_OFA_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_RANGE                      2:2
#define PMC_IMPL_PART_OFA_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_MSB                        MK_SHIFT_CONST(2)
#define PMC_IMPL_PART_OFA_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_LSB                        MK_SHIFT_CONST(2)
#define PMC_IMPL_PART_OFA_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_WOFFSET                    0x0
#define PMC_IMPL_PART_OFA_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_DEFAULT                    MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_OFA_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_OFA_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_OFA_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_OFA_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_OFA_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_OFA_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_INIT_ENUM                  ON
#define PMC_IMPL_PART_OFA_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_OFF                        MK_ENUM_CONST(0)
#define PMC_IMPL_PART_OFA_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_ON                 MK_ENUM_CONST(1)

#define PMC_IMPL_PART_OFA_POWER_GATE_CONTROL_0_SRAM_RET_EN_SHIFT                        MK_SHIFT_CONST(1)
#define PMC_IMPL_PART_OFA_POWER_GATE_CONTROL_0_SRAM_RET_EN_FIELD                        MK_FIELD_CONST(0x1, PMC_IMPL_PART_OFA_POWER_GATE_CONTROL_0_SRAM_RET_EN_SHIFT)
#define PMC_IMPL_PART_OFA_POWER_GATE_CONTROL_0_SRAM_RET_EN_RANGE                        1:1
#define PMC_IMPL_PART_OFA_POWER_GATE_CONTROL_0_SRAM_RET_EN_MSB                  MK_SHIFT_CONST(1)
#define PMC_IMPL_PART_OFA_POWER_GATE_CONTROL_0_SRAM_RET_EN_LSB                  MK_SHIFT_CONST(1)
#define PMC_IMPL_PART_OFA_POWER_GATE_CONTROL_0_SRAM_RET_EN_WOFFSET                      0x0
#define PMC_IMPL_PART_OFA_POWER_GATE_CONTROL_0_SRAM_RET_EN_DEFAULT                      MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_OFA_POWER_GATE_CONTROL_0_SRAM_RET_EN_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_OFA_POWER_GATE_CONTROL_0_SRAM_RET_EN_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_OFA_POWER_GATE_CONTROL_0_SRAM_RET_EN_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_OFA_POWER_GATE_CONTROL_0_SRAM_RET_EN_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_OFA_POWER_GATE_CONTROL_0_SRAM_RET_EN_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_OFA_POWER_GATE_CONTROL_0_SRAM_RET_EN_INIT_ENUM                    OFF
#define PMC_IMPL_PART_OFA_POWER_GATE_CONTROL_0_SRAM_RET_EN_OFF                  MK_ENUM_CONST(0)
#define PMC_IMPL_PART_OFA_POWER_GATE_CONTROL_0_SRAM_RET_EN_ON                   MK_ENUM_CONST(1)

#define PMC_IMPL_PART_OFA_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SHIFT                        MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_OFA_POWER_GATE_CONTROL_0_LOGIC_SLEEP_FIELD                        MK_FIELD_CONST(0x1, PMC_IMPL_PART_OFA_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SHIFT)
#define PMC_IMPL_PART_OFA_POWER_GATE_CONTROL_0_LOGIC_SLEEP_RANGE                        0:0
#define PMC_IMPL_PART_OFA_POWER_GATE_CONTROL_0_LOGIC_SLEEP_MSB                  MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_OFA_POWER_GATE_CONTROL_0_LOGIC_SLEEP_LSB                  MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_OFA_POWER_GATE_CONTROL_0_LOGIC_SLEEP_WOFFSET                      0x0
#define PMC_IMPL_PART_OFA_POWER_GATE_CONTROL_0_LOGIC_SLEEP_DEFAULT                      MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_OFA_POWER_GATE_CONTROL_0_LOGIC_SLEEP_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_OFA_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_OFA_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_OFA_POWER_GATE_CONTROL_0_LOGIC_SLEEP_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_OFA_POWER_GATE_CONTROL_0_LOGIC_SLEEP_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_OFA_POWER_GATE_CONTROL_0_LOGIC_SLEEP_INIT_ENUM                    ON
#define PMC_IMPL_PART_OFA_POWER_GATE_CONTROL_0_LOGIC_SLEEP_OFF                  MK_ENUM_CONST(0)
#define PMC_IMPL_PART_OFA_POWER_GATE_CONTROL_0_LOGIC_SLEEP_ON                   MK_ENUM_CONST(1)


// Register PMC_IMPL_PART_OFA_POWER_GATE_STATUS_0
#define PMC_IMPL_PART_OFA_POWER_GATE_STATUS_0                   MK_ADDR_CONST(0x554)
#define PMC_IMPL_PART_OFA_POWER_GATE_STATUS_0_SECURE                    0x0
#define PMC_IMPL_PART_OFA_POWER_GATE_STATUS_0_DUAL                      0x0
#define PMC_IMPL_PART_OFA_POWER_GATE_STATUS_0_SCR                       PG_OFA_SCR_0
#define PMC_IMPL_PART_OFA_POWER_GATE_STATUS_0_SCRREG                    PMC_IMPL_SCR_PG_OFA_SCR_0
#define PMC_IMPL_PART_OFA_POWER_GATE_STATUS_0_WORD_COUNT                        0x1
#define PMC_IMPL_PART_OFA_POWER_GATE_STATUS_0_RESET_VAL                         MK_MASK_CONST(0x5)
#define PMC_IMPL_PART_OFA_POWER_GATE_STATUS_0_RESET_MASK                        MK_MASK_CONST(0x7)
#define PMC_IMPL_PART_OFA_POWER_GATE_STATUS_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_OFA_POWER_GATE_STATUS_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_OFA_POWER_GATE_STATUS_0_READ_MASK                         MK_MASK_CONST(0x7)
#define PMC_IMPL_PART_OFA_POWER_GATE_STATUS_0_WRITE_MASK                        MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_OFA_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SHIFT                      MK_SHIFT_CONST(2)
#define PMC_IMPL_PART_OFA_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_FIELD                      MK_FIELD_CONST(0x1, PMC_IMPL_PART_OFA_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SHIFT)
#define PMC_IMPL_PART_OFA_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_RANGE                      2:2
#define PMC_IMPL_PART_OFA_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_MSB                        MK_SHIFT_CONST(2)
#define PMC_IMPL_PART_OFA_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_LSB                        MK_SHIFT_CONST(2)
#define PMC_IMPL_PART_OFA_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_WOFFSET                    0x0
#define PMC_IMPL_PART_OFA_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_DEFAULT                    MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_OFA_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_OFA_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_OFA_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_OFA_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_OFA_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_OFA_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_INIT_ENUM                  ON
#define PMC_IMPL_PART_OFA_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_OFF                        MK_ENUM_CONST(0)
#define PMC_IMPL_PART_OFA_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_ON                 MK_ENUM_CONST(1)

#define PMC_IMPL_PART_OFA_POWER_GATE_STATUS_0_SRAM_RET_STS_SHIFT                        MK_SHIFT_CONST(1)
#define PMC_IMPL_PART_OFA_POWER_GATE_STATUS_0_SRAM_RET_STS_FIELD                        MK_FIELD_CONST(0x1, PMC_IMPL_PART_OFA_POWER_GATE_STATUS_0_SRAM_RET_STS_SHIFT)
#define PMC_IMPL_PART_OFA_POWER_GATE_STATUS_0_SRAM_RET_STS_RANGE                        1:1
#define PMC_IMPL_PART_OFA_POWER_GATE_STATUS_0_SRAM_RET_STS_MSB                  MK_SHIFT_CONST(1)
#define PMC_IMPL_PART_OFA_POWER_GATE_STATUS_0_SRAM_RET_STS_LSB                  MK_SHIFT_CONST(1)
#define PMC_IMPL_PART_OFA_POWER_GATE_STATUS_0_SRAM_RET_STS_WOFFSET                      0x0
#define PMC_IMPL_PART_OFA_POWER_GATE_STATUS_0_SRAM_RET_STS_DEFAULT                      MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_OFA_POWER_GATE_STATUS_0_SRAM_RET_STS_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_OFA_POWER_GATE_STATUS_0_SRAM_RET_STS_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_OFA_POWER_GATE_STATUS_0_SRAM_RET_STS_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_OFA_POWER_GATE_STATUS_0_SRAM_RET_STS_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_OFA_POWER_GATE_STATUS_0_SRAM_RET_STS_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_OFA_POWER_GATE_STATUS_0_SRAM_RET_STS_INIT_ENUM                    OFF
#define PMC_IMPL_PART_OFA_POWER_GATE_STATUS_0_SRAM_RET_STS_OFF                  MK_ENUM_CONST(0)
#define PMC_IMPL_PART_OFA_POWER_GATE_STATUS_0_SRAM_RET_STS_ON                   MK_ENUM_CONST(1)

#define PMC_IMPL_PART_OFA_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SHIFT                     MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_OFA_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_FIELD                     MK_FIELD_CONST(0x1, PMC_IMPL_PART_OFA_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SHIFT)
#define PMC_IMPL_PART_OFA_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_RANGE                     0:0
#define PMC_IMPL_PART_OFA_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_MSB                       MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_OFA_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_LSB                       MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_OFA_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_WOFFSET                   0x0
#define PMC_IMPL_PART_OFA_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_DEFAULT                   MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_OFA_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_OFA_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_OFA_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_OFA_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_OFA_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_OFA_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_INIT_ENUM                 ON
#define PMC_IMPL_PART_OFA_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_OFF                       MK_ENUM_CONST(0)
#define PMC_IMPL_PART_OFA_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_ON                        MK_ENUM_CONST(1)


// Register PMC_IMPL_PART_OFA_CLAMP_CONTROL_0
#define PMC_IMPL_PART_OFA_CLAMP_CONTROL_0                       MK_ADDR_CONST(0x558)
#define PMC_IMPL_PART_OFA_CLAMP_CONTROL_0_SECURE                        0x0
#define PMC_IMPL_PART_OFA_CLAMP_CONTROL_0_DUAL                  0x0
#define PMC_IMPL_PART_OFA_CLAMP_CONTROL_0_SCR                   PG_OFA_SCR_0
#define PMC_IMPL_PART_OFA_CLAMP_CONTROL_0_SCRREG                        PMC_IMPL_SCR_PG_OFA_SCR_0
#define PMC_IMPL_PART_OFA_CLAMP_CONTROL_0_WORD_COUNT                    0x1
#define PMC_IMPL_PART_OFA_CLAMP_CONTROL_0_RESET_VAL                     MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_OFA_CLAMP_CONTROL_0_RESET_MASK                    MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_OFA_CLAMP_CONTROL_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_OFA_CLAMP_CONTROL_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_OFA_CLAMP_CONTROL_0_READ_MASK                     MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_OFA_CLAMP_CONTROL_0_WRITE_MASK                    MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_OFA_CLAMP_CONTROL_0_CLAMP_SHIFT                   MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_OFA_CLAMP_CONTROL_0_CLAMP_FIELD                   MK_FIELD_CONST(0x1, PMC_IMPL_PART_OFA_CLAMP_CONTROL_0_CLAMP_SHIFT)
#define PMC_IMPL_PART_OFA_CLAMP_CONTROL_0_CLAMP_RANGE                   0:0
#define PMC_IMPL_PART_OFA_CLAMP_CONTROL_0_CLAMP_MSB                     MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_OFA_CLAMP_CONTROL_0_CLAMP_LSB                     MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_OFA_CLAMP_CONTROL_0_CLAMP_WOFFSET                 0x0
#define PMC_IMPL_PART_OFA_CLAMP_CONTROL_0_CLAMP_DEFAULT                 MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_OFA_CLAMP_CONTROL_0_CLAMP_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_OFA_CLAMP_CONTROL_0_CLAMP_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_OFA_CLAMP_CONTROL_0_CLAMP_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_OFA_CLAMP_CONTROL_0_CLAMP_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_OFA_CLAMP_CONTROL_0_CLAMP_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_OFA_CLAMP_CONTROL_0_CLAMP_INIT_ENUM                       ON
#define PMC_IMPL_PART_OFA_CLAMP_CONTROL_0_CLAMP_OFF                     MK_ENUM_CONST(0)
#define PMC_IMPL_PART_OFA_CLAMP_CONTROL_0_CLAMP_ON                      MK_ENUM_CONST(1)


// Register PMC_IMPL_PART_MGBEA_POWER_GATE_CONTROL_0
#define PMC_IMPL_PART_MGBEA_POWER_GATE_CONTROL_0                        MK_ADDR_CONST(0x55c)
#define PMC_IMPL_PART_MGBEA_POWER_GATE_CONTROL_0_SECURE                         0x0
#define PMC_IMPL_PART_MGBEA_POWER_GATE_CONTROL_0_DUAL                   0x0
#define PMC_IMPL_PART_MGBEA_POWER_GATE_CONTROL_0_SCR                    PG_MGBEA_SCR_0
#define PMC_IMPL_PART_MGBEA_POWER_GATE_CONTROL_0_SCRREG                         PMC_IMPL_SCR_PG_MGBEA_SCR_0
#define PMC_IMPL_PART_MGBEA_POWER_GATE_CONTROL_0_WORD_COUNT                     0x1
#define PMC_IMPL_PART_MGBEA_POWER_GATE_CONTROL_0_RESET_VAL                      MK_MASK_CONST(0x80000005)
#define PMC_IMPL_PART_MGBEA_POWER_GATE_CONTROL_0_RESET_MASK                     MK_MASK_CONST(0x80000107)
#define PMC_IMPL_PART_MGBEA_POWER_GATE_CONTROL_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_MGBEA_POWER_GATE_CONTROL_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_MGBEA_POWER_GATE_CONTROL_0_READ_MASK                      MK_MASK_CONST(0x80000107)
#define PMC_IMPL_PART_MGBEA_POWER_GATE_CONTROL_0_WRITE_MASK                     MK_MASK_CONST(0x80000105)
#define PMC_IMPL_PART_MGBEA_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SHIFT                      MK_SHIFT_CONST(31)
#define PMC_IMPL_PART_MGBEA_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_FIELD                      MK_FIELD_CONST(0x1, PMC_IMPL_PART_MGBEA_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SHIFT)
#define PMC_IMPL_PART_MGBEA_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_RANGE                      31:31
#define PMC_IMPL_PART_MGBEA_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_MSB                        MK_SHIFT_CONST(31)
#define PMC_IMPL_PART_MGBEA_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_LSB                        MK_SHIFT_CONST(31)
#define PMC_IMPL_PART_MGBEA_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_WOFFSET                    0x0
#define PMC_IMPL_PART_MGBEA_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_DEFAULT                    MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_MGBEA_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_MGBEA_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_MGBEA_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_MGBEA_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_MGBEA_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_MGBEA_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_INIT_ENUM                  ENABLE
#define PMC_IMPL_PART_MGBEA_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_DISABLE                    MK_ENUM_CONST(0)
#define PMC_IMPL_PART_MGBEA_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_ENABLE                     MK_ENUM_CONST(1)

#define PMC_IMPL_PART_MGBEA_POWER_GATE_CONTROL_0_START_SHIFT                    MK_SHIFT_CONST(8)
#define PMC_IMPL_PART_MGBEA_POWER_GATE_CONTROL_0_START_FIELD                    MK_FIELD_CONST(0x1, PMC_IMPL_PART_MGBEA_POWER_GATE_CONTROL_0_START_SHIFT)
#define PMC_IMPL_PART_MGBEA_POWER_GATE_CONTROL_0_START_RANGE                    8:8
#define PMC_IMPL_PART_MGBEA_POWER_GATE_CONTROL_0_START_MSB                      MK_SHIFT_CONST(8)
#define PMC_IMPL_PART_MGBEA_POWER_GATE_CONTROL_0_START_LSB                      MK_SHIFT_CONST(8)
#define PMC_IMPL_PART_MGBEA_POWER_GATE_CONTROL_0_START_WOFFSET                  0x0
#define PMC_IMPL_PART_MGBEA_POWER_GATE_CONTROL_0_START_DEFAULT                  MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_MGBEA_POWER_GATE_CONTROL_0_START_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_MGBEA_POWER_GATE_CONTROL_0_START_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_MGBEA_POWER_GATE_CONTROL_0_START_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_MGBEA_POWER_GATE_CONTROL_0_START_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_MGBEA_POWER_GATE_CONTROL_0_START_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_MGBEA_POWER_GATE_CONTROL_0_START_INIT_ENUM                        DONE
#define PMC_IMPL_PART_MGBEA_POWER_GATE_CONTROL_0_START_DONE                     MK_ENUM_CONST(0)
#define PMC_IMPL_PART_MGBEA_POWER_GATE_CONTROL_0_START_PENDING                  MK_ENUM_CONST(1)

#define PMC_IMPL_PART_MGBEA_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SHIFT                    MK_SHIFT_CONST(2)
#define PMC_IMPL_PART_MGBEA_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_FIELD                    MK_FIELD_CONST(0x1, PMC_IMPL_PART_MGBEA_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SHIFT)
#define PMC_IMPL_PART_MGBEA_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_RANGE                    2:2
#define PMC_IMPL_PART_MGBEA_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_MSB                      MK_SHIFT_CONST(2)
#define PMC_IMPL_PART_MGBEA_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_LSB                      MK_SHIFT_CONST(2)
#define PMC_IMPL_PART_MGBEA_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_WOFFSET                  0x0
#define PMC_IMPL_PART_MGBEA_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_DEFAULT                  MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_MGBEA_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_MGBEA_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_MGBEA_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_MGBEA_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_MGBEA_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_MGBEA_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_INIT_ENUM                        ON
#define PMC_IMPL_PART_MGBEA_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_OFF                      MK_ENUM_CONST(0)
#define PMC_IMPL_PART_MGBEA_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_ON                       MK_ENUM_CONST(1)

#define PMC_IMPL_PART_MGBEA_POWER_GATE_CONTROL_0_SRAM_RET_EN_SHIFT                      MK_SHIFT_CONST(1)
#define PMC_IMPL_PART_MGBEA_POWER_GATE_CONTROL_0_SRAM_RET_EN_FIELD                      MK_FIELD_CONST(0x1, PMC_IMPL_PART_MGBEA_POWER_GATE_CONTROL_0_SRAM_RET_EN_SHIFT)
#define PMC_IMPL_PART_MGBEA_POWER_GATE_CONTROL_0_SRAM_RET_EN_RANGE                      1:1
#define PMC_IMPL_PART_MGBEA_POWER_GATE_CONTROL_0_SRAM_RET_EN_MSB                        MK_SHIFT_CONST(1)
#define PMC_IMPL_PART_MGBEA_POWER_GATE_CONTROL_0_SRAM_RET_EN_LSB                        MK_SHIFT_CONST(1)
#define PMC_IMPL_PART_MGBEA_POWER_GATE_CONTROL_0_SRAM_RET_EN_WOFFSET                    0x0
#define PMC_IMPL_PART_MGBEA_POWER_GATE_CONTROL_0_SRAM_RET_EN_DEFAULT                    MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_MGBEA_POWER_GATE_CONTROL_0_SRAM_RET_EN_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_MGBEA_POWER_GATE_CONTROL_0_SRAM_RET_EN_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_MGBEA_POWER_GATE_CONTROL_0_SRAM_RET_EN_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_MGBEA_POWER_GATE_CONTROL_0_SRAM_RET_EN_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_MGBEA_POWER_GATE_CONTROL_0_SRAM_RET_EN_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_MGBEA_POWER_GATE_CONTROL_0_SRAM_RET_EN_INIT_ENUM                  OFF
#define PMC_IMPL_PART_MGBEA_POWER_GATE_CONTROL_0_SRAM_RET_EN_OFF                        MK_ENUM_CONST(0)
#define PMC_IMPL_PART_MGBEA_POWER_GATE_CONTROL_0_SRAM_RET_EN_ON                 MK_ENUM_CONST(1)

#define PMC_IMPL_PART_MGBEA_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SHIFT                      MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_MGBEA_POWER_GATE_CONTROL_0_LOGIC_SLEEP_FIELD                      MK_FIELD_CONST(0x1, PMC_IMPL_PART_MGBEA_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SHIFT)
#define PMC_IMPL_PART_MGBEA_POWER_GATE_CONTROL_0_LOGIC_SLEEP_RANGE                      0:0
#define PMC_IMPL_PART_MGBEA_POWER_GATE_CONTROL_0_LOGIC_SLEEP_MSB                        MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_MGBEA_POWER_GATE_CONTROL_0_LOGIC_SLEEP_LSB                        MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_MGBEA_POWER_GATE_CONTROL_0_LOGIC_SLEEP_WOFFSET                    0x0
#define PMC_IMPL_PART_MGBEA_POWER_GATE_CONTROL_0_LOGIC_SLEEP_DEFAULT                    MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_MGBEA_POWER_GATE_CONTROL_0_LOGIC_SLEEP_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_MGBEA_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_MGBEA_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_MGBEA_POWER_GATE_CONTROL_0_LOGIC_SLEEP_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_MGBEA_POWER_GATE_CONTROL_0_LOGIC_SLEEP_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_MGBEA_POWER_GATE_CONTROL_0_LOGIC_SLEEP_INIT_ENUM                  ON
#define PMC_IMPL_PART_MGBEA_POWER_GATE_CONTROL_0_LOGIC_SLEEP_OFF                        MK_ENUM_CONST(0)
#define PMC_IMPL_PART_MGBEA_POWER_GATE_CONTROL_0_LOGIC_SLEEP_ON                 MK_ENUM_CONST(1)


// Register PMC_IMPL_PART_MGBEA_POWER_GATE_STATUS_0
#define PMC_IMPL_PART_MGBEA_POWER_GATE_STATUS_0                 MK_ADDR_CONST(0x560)
#define PMC_IMPL_PART_MGBEA_POWER_GATE_STATUS_0_SECURE                  0x0
#define PMC_IMPL_PART_MGBEA_POWER_GATE_STATUS_0_DUAL                    0x0
#define PMC_IMPL_PART_MGBEA_POWER_GATE_STATUS_0_SCR                     PG_MGBEA_SCR_0
#define PMC_IMPL_PART_MGBEA_POWER_GATE_STATUS_0_SCRREG                  PMC_IMPL_SCR_PG_MGBEA_SCR_0
#define PMC_IMPL_PART_MGBEA_POWER_GATE_STATUS_0_WORD_COUNT                      0x1
#define PMC_IMPL_PART_MGBEA_POWER_GATE_STATUS_0_RESET_VAL                       MK_MASK_CONST(0x5)
#define PMC_IMPL_PART_MGBEA_POWER_GATE_STATUS_0_RESET_MASK                      MK_MASK_CONST(0x7)
#define PMC_IMPL_PART_MGBEA_POWER_GATE_STATUS_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_MGBEA_POWER_GATE_STATUS_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_MGBEA_POWER_GATE_STATUS_0_READ_MASK                       MK_MASK_CONST(0x7)
#define PMC_IMPL_PART_MGBEA_POWER_GATE_STATUS_0_WRITE_MASK                      MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_MGBEA_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SHIFT                    MK_SHIFT_CONST(2)
#define PMC_IMPL_PART_MGBEA_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_FIELD                    MK_FIELD_CONST(0x1, PMC_IMPL_PART_MGBEA_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SHIFT)
#define PMC_IMPL_PART_MGBEA_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_RANGE                    2:2
#define PMC_IMPL_PART_MGBEA_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_MSB                      MK_SHIFT_CONST(2)
#define PMC_IMPL_PART_MGBEA_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_LSB                      MK_SHIFT_CONST(2)
#define PMC_IMPL_PART_MGBEA_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_WOFFSET                  0x0
#define PMC_IMPL_PART_MGBEA_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_DEFAULT                  MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_MGBEA_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_MGBEA_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_MGBEA_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_MGBEA_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_MGBEA_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_MGBEA_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_INIT_ENUM                        ON
#define PMC_IMPL_PART_MGBEA_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_OFF                      MK_ENUM_CONST(0)
#define PMC_IMPL_PART_MGBEA_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_ON                       MK_ENUM_CONST(1)

#define PMC_IMPL_PART_MGBEA_POWER_GATE_STATUS_0_SRAM_RET_STS_SHIFT                      MK_SHIFT_CONST(1)
#define PMC_IMPL_PART_MGBEA_POWER_GATE_STATUS_0_SRAM_RET_STS_FIELD                      MK_FIELD_CONST(0x1, PMC_IMPL_PART_MGBEA_POWER_GATE_STATUS_0_SRAM_RET_STS_SHIFT)
#define PMC_IMPL_PART_MGBEA_POWER_GATE_STATUS_0_SRAM_RET_STS_RANGE                      1:1
#define PMC_IMPL_PART_MGBEA_POWER_GATE_STATUS_0_SRAM_RET_STS_MSB                        MK_SHIFT_CONST(1)
#define PMC_IMPL_PART_MGBEA_POWER_GATE_STATUS_0_SRAM_RET_STS_LSB                        MK_SHIFT_CONST(1)
#define PMC_IMPL_PART_MGBEA_POWER_GATE_STATUS_0_SRAM_RET_STS_WOFFSET                    0x0
#define PMC_IMPL_PART_MGBEA_POWER_GATE_STATUS_0_SRAM_RET_STS_DEFAULT                    MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_MGBEA_POWER_GATE_STATUS_0_SRAM_RET_STS_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_MGBEA_POWER_GATE_STATUS_0_SRAM_RET_STS_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_MGBEA_POWER_GATE_STATUS_0_SRAM_RET_STS_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_MGBEA_POWER_GATE_STATUS_0_SRAM_RET_STS_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_MGBEA_POWER_GATE_STATUS_0_SRAM_RET_STS_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_MGBEA_POWER_GATE_STATUS_0_SRAM_RET_STS_INIT_ENUM                  OFF
#define PMC_IMPL_PART_MGBEA_POWER_GATE_STATUS_0_SRAM_RET_STS_OFF                        MK_ENUM_CONST(0)
#define PMC_IMPL_PART_MGBEA_POWER_GATE_STATUS_0_SRAM_RET_STS_ON                 MK_ENUM_CONST(1)

#define PMC_IMPL_PART_MGBEA_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SHIFT                   MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_MGBEA_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_FIELD                   MK_FIELD_CONST(0x1, PMC_IMPL_PART_MGBEA_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SHIFT)
#define PMC_IMPL_PART_MGBEA_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_RANGE                   0:0
#define PMC_IMPL_PART_MGBEA_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_MSB                     MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_MGBEA_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_LSB                     MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_MGBEA_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_WOFFSET                 0x0
#define PMC_IMPL_PART_MGBEA_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_DEFAULT                 MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_MGBEA_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_MGBEA_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_MGBEA_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_MGBEA_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_MGBEA_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_MGBEA_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_INIT_ENUM                       ON
#define PMC_IMPL_PART_MGBEA_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_OFF                     MK_ENUM_CONST(0)
#define PMC_IMPL_PART_MGBEA_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_ON                      MK_ENUM_CONST(1)


// Register PMC_IMPL_PART_MGBEA_CLAMP_CONTROL_0
#define PMC_IMPL_PART_MGBEA_CLAMP_CONTROL_0                     MK_ADDR_CONST(0x564)
#define PMC_IMPL_PART_MGBEA_CLAMP_CONTROL_0_SECURE                      0x0
#define PMC_IMPL_PART_MGBEA_CLAMP_CONTROL_0_DUAL                        0x0
#define PMC_IMPL_PART_MGBEA_CLAMP_CONTROL_0_SCR                         PG_MGBEA_SCR_0
#define PMC_IMPL_PART_MGBEA_CLAMP_CONTROL_0_SCRREG                      PMC_IMPL_SCR_PG_MGBEA_SCR_0
#define PMC_IMPL_PART_MGBEA_CLAMP_CONTROL_0_WORD_COUNT                  0x1
#define PMC_IMPL_PART_MGBEA_CLAMP_CONTROL_0_RESET_VAL                   MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_MGBEA_CLAMP_CONTROL_0_RESET_MASK                  MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_MGBEA_CLAMP_CONTROL_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_MGBEA_CLAMP_CONTROL_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_MGBEA_CLAMP_CONTROL_0_READ_MASK                   MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_MGBEA_CLAMP_CONTROL_0_WRITE_MASK                  MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_MGBEA_CLAMP_CONTROL_0_CLAMP_SHIFT                 MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_MGBEA_CLAMP_CONTROL_0_CLAMP_FIELD                 MK_FIELD_CONST(0x1, PMC_IMPL_PART_MGBEA_CLAMP_CONTROL_0_CLAMP_SHIFT)
#define PMC_IMPL_PART_MGBEA_CLAMP_CONTROL_0_CLAMP_RANGE                 0:0
#define PMC_IMPL_PART_MGBEA_CLAMP_CONTROL_0_CLAMP_MSB                   MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_MGBEA_CLAMP_CONTROL_0_CLAMP_LSB                   MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_MGBEA_CLAMP_CONTROL_0_CLAMP_WOFFSET                       0x0
#define PMC_IMPL_PART_MGBEA_CLAMP_CONTROL_0_CLAMP_DEFAULT                       MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_MGBEA_CLAMP_CONTROL_0_CLAMP_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_MGBEA_CLAMP_CONTROL_0_CLAMP_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_MGBEA_CLAMP_CONTROL_0_CLAMP_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_MGBEA_CLAMP_CONTROL_0_CLAMP_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_MGBEA_CLAMP_CONTROL_0_CLAMP_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_MGBEA_CLAMP_CONTROL_0_CLAMP_INIT_ENUM                     ON
#define PMC_IMPL_PART_MGBEA_CLAMP_CONTROL_0_CLAMP_OFF                   MK_ENUM_CONST(0)
#define PMC_IMPL_PART_MGBEA_CLAMP_CONTROL_0_CLAMP_ON                    MK_ENUM_CONST(1)


// Register PMC_IMPL_PART_MGBEBA_POWER_GATE_CONTROL_0
#define PMC_IMPL_PART_MGBEBA_POWER_GATE_CONTROL_0                       MK_ADDR_CONST(0x568)
#define PMC_IMPL_PART_MGBEBA_POWER_GATE_CONTROL_0_SECURE                        0x0
#define PMC_IMPL_PART_MGBEBA_POWER_GATE_CONTROL_0_DUAL                  0x0
#define PMC_IMPL_PART_MGBEBA_POWER_GATE_CONTROL_0_SCR                   PG_MGBEBA_SCR_0
#define PMC_IMPL_PART_MGBEBA_POWER_GATE_CONTROL_0_SCRREG                        PMC_IMPL_SCR_PG_MGBEBA_SCR_0
#define PMC_IMPL_PART_MGBEBA_POWER_GATE_CONTROL_0_WORD_COUNT                    0x1
#define PMC_IMPL_PART_MGBEBA_POWER_GATE_CONTROL_0_RESET_VAL                     MK_MASK_CONST(0x80000005)
#define PMC_IMPL_PART_MGBEBA_POWER_GATE_CONTROL_0_RESET_MASK                    MK_MASK_CONST(0x80000107)
#define PMC_IMPL_PART_MGBEBA_POWER_GATE_CONTROL_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_MGBEBA_POWER_GATE_CONTROL_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_MGBEBA_POWER_GATE_CONTROL_0_READ_MASK                     MK_MASK_CONST(0x80000107)
#define PMC_IMPL_PART_MGBEBA_POWER_GATE_CONTROL_0_WRITE_MASK                    MK_MASK_CONST(0x80000105)
#define PMC_IMPL_PART_MGBEBA_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SHIFT                     MK_SHIFT_CONST(31)
#define PMC_IMPL_PART_MGBEBA_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_FIELD                     MK_FIELD_CONST(0x1, PMC_IMPL_PART_MGBEBA_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SHIFT)
#define PMC_IMPL_PART_MGBEBA_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_RANGE                     31:31
#define PMC_IMPL_PART_MGBEBA_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_MSB                       MK_SHIFT_CONST(31)
#define PMC_IMPL_PART_MGBEBA_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_LSB                       MK_SHIFT_CONST(31)
#define PMC_IMPL_PART_MGBEBA_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_WOFFSET                   0x0
#define PMC_IMPL_PART_MGBEBA_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_DEFAULT                   MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_MGBEBA_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_MGBEBA_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_MGBEBA_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_MGBEBA_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_MGBEBA_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_MGBEBA_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_INIT_ENUM                 ENABLE
#define PMC_IMPL_PART_MGBEBA_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_DISABLE                   MK_ENUM_CONST(0)
#define PMC_IMPL_PART_MGBEBA_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_ENABLE                    MK_ENUM_CONST(1)

#define PMC_IMPL_PART_MGBEBA_POWER_GATE_CONTROL_0_START_SHIFT                   MK_SHIFT_CONST(8)
#define PMC_IMPL_PART_MGBEBA_POWER_GATE_CONTROL_0_START_FIELD                   MK_FIELD_CONST(0x1, PMC_IMPL_PART_MGBEBA_POWER_GATE_CONTROL_0_START_SHIFT)
#define PMC_IMPL_PART_MGBEBA_POWER_GATE_CONTROL_0_START_RANGE                   8:8
#define PMC_IMPL_PART_MGBEBA_POWER_GATE_CONTROL_0_START_MSB                     MK_SHIFT_CONST(8)
#define PMC_IMPL_PART_MGBEBA_POWER_GATE_CONTROL_0_START_LSB                     MK_SHIFT_CONST(8)
#define PMC_IMPL_PART_MGBEBA_POWER_GATE_CONTROL_0_START_WOFFSET                 0x0
#define PMC_IMPL_PART_MGBEBA_POWER_GATE_CONTROL_0_START_DEFAULT                 MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_MGBEBA_POWER_GATE_CONTROL_0_START_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_MGBEBA_POWER_GATE_CONTROL_0_START_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_MGBEBA_POWER_GATE_CONTROL_0_START_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_MGBEBA_POWER_GATE_CONTROL_0_START_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_MGBEBA_POWER_GATE_CONTROL_0_START_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_MGBEBA_POWER_GATE_CONTROL_0_START_INIT_ENUM                       DONE
#define PMC_IMPL_PART_MGBEBA_POWER_GATE_CONTROL_0_START_DONE                    MK_ENUM_CONST(0)
#define PMC_IMPL_PART_MGBEBA_POWER_GATE_CONTROL_0_START_PENDING                 MK_ENUM_CONST(1)

#define PMC_IMPL_PART_MGBEBA_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SHIFT                   MK_SHIFT_CONST(2)
#define PMC_IMPL_PART_MGBEBA_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_FIELD                   MK_FIELD_CONST(0x1, PMC_IMPL_PART_MGBEBA_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SHIFT)
#define PMC_IMPL_PART_MGBEBA_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_RANGE                   2:2
#define PMC_IMPL_PART_MGBEBA_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_MSB                     MK_SHIFT_CONST(2)
#define PMC_IMPL_PART_MGBEBA_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_LSB                     MK_SHIFT_CONST(2)
#define PMC_IMPL_PART_MGBEBA_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_WOFFSET                 0x0
#define PMC_IMPL_PART_MGBEBA_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_DEFAULT                 MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_MGBEBA_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_MGBEBA_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_MGBEBA_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_MGBEBA_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_MGBEBA_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_MGBEBA_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_INIT_ENUM                       ON
#define PMC_IMPL_PART_MGBEBA_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_OFF                     MK_ENUM_CONST(0)
#define PMC_IMPL_PART_MGBEBA_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_ON                      MK_ENUM_CONST(1)

#define PMC_IMPL_PART_MGBEBA_POWER_GATE_CONTROL_0_SRAM_RET_EN_SHIFT                     MK_SHIFT_CONST(1)
#define PMC_IMPL_PART_MGBEBA_POWER_GATE_CONTROL_0_SRAM_RET_EN_FIELD                     MK_FIELD_CONST(0x1, PMC_IMPL_PART_MGBEBA_POWER_GATE_CONTROL_0_SRAM_RET_EN_SHIFT)
#define PMC_IMPL_PART_MGBEBA_POWER_GATE_CONTROL_0_SRAM_RET_EN_RANGE                     1:1
#define PMC_IMPL_PART_MGBEBA_POWER_GATE_CONTROL_0_SRAM_RET_EN_MSB                       MK_SHIFT_CONST(1)
#define PMC_IMPL_PART_MGBEBA_POWER_GATE_CONTROL_0_SRAM_RET_EN_LSB                       MK_SHIFT_CONST(1)
#define PMC_IMPL_PART_MGBEBA_POWER_GATE_CONTROL_0_SRAM_RET_EN_WOFFSET                   0x0
#define PMC_IMPL_PART_MGBEBA_POWER_GATE_CONTROL_0_SRAM_RET_EN_DEFAULT                   MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_MGBEBA_POWER_GATE_CONTROL_0_SRAM_RET_EN_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_MGBEBA_POWER_GATE_CONTROL_0_SRAM_RET_EN_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_MGBEBA_POWER_GATE_CONTROL_0_SRAM_RET_EN_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_MGBEBA_POWER_GATE_CONTROL_0_SRAM_RET_EN_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_MGBEBA_POWER_GATE_CONTROL_0_SRAM_RET_EN_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_MGBEBA_POWER_GATE_CONTROL_0_SRAM_RET_EN_INIT_ENUM                 OFF
#define PMC_IMPL_PART_MGBEBA_POWER_GATE_CONTROL_0_SRAM_RET_EN_OFF                       MK_ENUM_CONST(0)
#define PMC_IMPL_PART_MGBEBA_POWER_GATE_CONTROL_0_SRAM_RET_EN_ON                        MK_ENUM_CONST(1)

#define PMC_IMPL_PART_MGBEBA_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SHIFT                     MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_MGBEBA_POWER_GATE_CONTROL_0_LOGIC_SLEEP_FIELD                     MK_FIELD_CONST(0x1, PMC_IMPL_PART_MGBEBA_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SHIFT)
#define PMC_IMPL_PART_MGBEBA_POWER_GATE_CONTROL_0_LOGIC_SLEEP_RANGE                     0:0
#define PMC_IMPL_PART_MGBEBA_POWER_GATE_CONTROL_0_LOGIC_SLEEP_MSB                       MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_MGBEBA_POWER_GATE_CONTROL_0_LOGIC_SLEEP_LSB                       MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_MGBEBA_POWER_GATE_CONTROL_0_LOGIC_SLEEP_WOFFSET                   0x0
#define PMC_IMPL_PART_MGBEBA_POWER_GATE_CONTROL_0_LOGIC_SLEEP_DEFAULT                   MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_MGBEBA_POWER_GATE_CONTROL_0_LOGIC_SLEEP_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_MGBEBA_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_MGBEBA_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_MGBEBA_POWER_GATE_CONTROL_0_LOGIC_SLEEP_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_MGBEBA_POWER_GATE_CONTROL_0_LOGIC_SLEEP_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_MGBEBA_POWER_GATE_CONTROL_0_LOGIC_SLEEP_INIT_ENUM                 ON
#define PMC_IMPL_PART_MGBEBA_POWER_GATE_CONTROL_0_LOGIC_SLEEP_OFF                       MK_ENUM_CONST(0)
#define PMC_IMPL_PART_MGBEBA_POWER_GATE_CONTROL_0_LOGIC_SLEEP_ON                        MK_ENUM_CONST(1)


// Register PMC_IMPL_PART_MGBEBA_POWER_GATE_STATUS_0
#define PMC_IMPL_PART_MGBEBA_POWER_GATE_STATUS_0                        MK_ADDR_CONST(0x56c)
#define PMC_IMPL_PART_MGBEBA_POWER_GATE_STATUS_0_SECURE                         0x0
#define PMC_IMPL_PART_MGBEBA_POWER_GATE_STATUS_0_DUAL                   0x0
#define PMC_IMPL_PART_MGBEBA_POWER_GATE_STATUS_0_SCR                    PG_MGBEBA_SCR_0
#define PMC_IMPL_PART_MGBEBA_POWER_GATE_STATUS_0_SCRREG                         PMC_IMPL_SCR_PG_MGBEBA_SCR_0
#define PMC_IMPL_PART_MGBEBA_POWER_GATE_STATUS_0_WORD_COUNT                     0x1
#define PMC_IMPL_PART_MGBEBA_POWER_GATE_STATUS_0_RESET_VAL                      MK_MASK_CONST(0x5)
#define PMC_IMPL_PART_MGBEBA_POWER_GATE_STATUS_0_RESET_MASK                     MK_MASK_CONST(0x7)
#define PMC_IMPL_PART_MGBEBA_POWER_GATE_STATUS_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_MGBEBA_POWER_GATE_STATUS_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_MGBEBA_POWER_GATE_STATUS_0_READ_MASK                      MK_MASK_CONST(0x7)
#define PMC_IMPL_PART_MGBEBA_POWER_GATE_STATUS_0_WRITE_MASK                     MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_MGBEBA_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SHIFT                   MK_SHIFT_CONST(2)
#define PMC_IMPL_PART_MGBEBA_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_FIELD                   MK_FIELD_CONST(0x1, PMC_IMPL_PART_MGBEBA_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SHIFT)
#define PMC_IMPL_PART_MGBEBA_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_RANGE                   2:2
#define PMC_IMPL_PART_MGBEBA_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_MSB                     MK_SHIFT_CONST(2)
#define PMC_IMPL_PART_MGBEBA_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_LSB                     MK_SHIFT_CONST(2)
#define PMC_IMPL_PART_MGBEBA_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_WOFFSET                 0x0
#define PMC_IMPL_PART_MGBEBA_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_DEFAULT                 MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_MGBEBA_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_MGBEBA_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_MGBEBA_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_MGBEBA_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_MGBEBA_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_MGBEBA_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_INIT_ENUM                       ON
#define PMC_IMPL_PART_MGBEBA_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_OFF                     MK_ENUM_CONST(0)
#define PMC_IMPL_PART_MGBEBA_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_ON                      MK_ENUM_CONST(1)

#define PMC_IMPL_PART_MGBEBA_POWER_GATE_STATUS_0_SRAM_RET_STS_SHIFT                     MK_SHIFT_CONST(1)
#define PMC_IMPL_PART_MGBEBA_POWER_GATE_STATUS_0_SRAM_RET_STS_FIELD                     MK_FIELD_CONST(0x1, PMC_IMPL_PART_MGBEBA_POWER_GATE_STATUS_0_SRAM_RET_STS_SHIFT)
#define PMC_IMPL_PART_MGBEBA_POWER_GATE_STATUS_0_SRAM_RET_STS_RANGE                     1:1
#define PMC_IMPL_PART_MGBEBA_POWER_GATE_STATUS_0_SRAM_RET_STS_MSB                       MK_SHIFT_CONST(1)
#define PMC_IMPL_PART_MGBEBA_POWER_GATE_STATUS_0_SRAM_RET_STS_LSB                       MK_SHIFT_CONST(1)
#define PMC_IMPL_PART_MGBEBA_POWER_GATE_STATUS_0_SRAM_RET_STS_WOFFSET                   0x0
#define PMC_IMPL_PART_MGBEBA_POWER_GATE_STATUS_0_SRAM_RET_STS_DEFAULT                   MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_MGBEBA_POWER_GATE_STATUS_0_SRAM_RET_STS_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_MGBEBA_POWER_GATE_STATUS_0_SRAM_RET_STS_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_MGBEBA_POWER_GATE_STATUS_0_SRAM_RET_STS_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_MGBEBA_POWER_GATE_STATUS_0_SRAM_RET_STS_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_MGBEBA_POWER_GATE_STATUS_0_SRAM_RET_STS_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_MGBEBA_POWER_GATE_STATUS_0_SRAM_RET_STS_INIT_ENUM                 OFF
#define PMC_IMPL_PART_MGBEBA_POWER_GATE_STATUS_0_SRAM_RET_STS_OFF                       MK_ENUM_CONST(0)
#define PMC_IMPL_PART_MGBEBA_POWER_GATE_STATUS_0_SRAM_RET_STS_ON                        MK_ENUM_CONST(1)

#define PMC_IMPL_PART_MGBEBA_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SHIFT                  MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_MGBEBA_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_FIELD                  MK_FIELD_CONST(0x1, PMC_IMPL_PART_MGBEBA_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SHIFT)
#define PMC_IMPL_PART_MGBEBA_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_RANGE                  0:0
#define PMC_IMPL_PART_MGBEBA_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_MSB                    MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_MGBEBA_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_LSB                    MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_MGBEBA_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_WOFFSET                        0x0
#define PMC_IMPL_PART_MGBEBA_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_DEFAULT                        MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_MGBEBA_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_MGBEBA_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_MGBEBA_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_MGBEBA_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_MGBEBA_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_MGBEBA_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_INIT_ENUM                      ON
#define PMC_IMPL_PART_MGBEBA_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_OFF                    MK_ENUM_CONST(0)
#define PMC_IMPL_PART_MGBEBA_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_ON                     MK_ENUM_CONST(1)


// Register PMC_IMPL_PART_MGBEBA_CLAMP_CONTROL_0
#define PMC_IMPL_PART_MGBEBA_CLAMP_CONTROL_0                    MK_ADDR_CONST(0x570)
#define PMC_IMPL_PART_MGBEBA_CLAMP_CONTROL_0_SECURE                     0x0
#define PMC_IMPL_PART_MGBEBA_CLAMP_CONTROL_0_DUAL                       0x0
#define PMC_IMPL_PART_MGBEBA_CLAMP_CONTROL_0_SCR                        PG_MGBEBA_SCR_0
#define PMC_IMPL_PART_MGBEBA_CLAMP_CONTROL_0_SCRREG                     PMC_IMPL_SCR_PG_MGBEBA_SCR_0
#define PMC_IMPL_PART_MGBEBA_CLAMP_CONTROL_0_WORD_COUNT                         0x1
#define PMC_IMPL_PART_MGBEBA_CLAMP_CONTROL_0_RESET_VAL                  MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_MGBEBA_CLAMP_CONTROL_0_RESET_MASK                         MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_MGBEBA_CLAMP_CONTROL_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_MGBEBA_CLAMP_CONTROL_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_MGBEBA_CLAMP_CONTROL_0_READ_MASK                  MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_MGBEBA_CLAMP_CONTROL_0_WRITE_MASK                         MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_MGBEBA_CLAMP_CONTROL_0_CLAMP_SHIFT                        MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_MGBEBA_CLAMP_CONTROL_0_CLAMP_FIELD                        MK_FIELD_CONST(0x1, PMC_IMPL_PART_MGBEBA_CLAMP_CONTROL_0_CLAMP_SHIFT)
#define PMC_IMPL_PART_MGBEBA_CLAMP_CONTROL_0_CLAMP_RANGE                        0:0
#define PMC_IMPL_PART_MGBEBA_CLAMP_CONTROL_0_CLAMP_MSB                  MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_MGBEBA_CLAMP_CONTROL_0_CLAMP_LSB                  MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_MGBEBA_CLAMP_CONTROL_0_CLAMP_WOFFSET                      0x0
#define PMC_IMPL_PART_MGBEBA_CLAMP_CONTROL_0_CLAMP_DEFAULT                      MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_MGBEBA_CLAMP_CONTROL_0_CLAMP_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_MGBEBA_CLAMP_CONTROL_0_CLAMP_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_MGBEBA_CLAMP_CONTROL_0_CLAMP_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_MGBEBA_CLAMP_CONTROL_0_CLAMP_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_MGBEBA_CLAMP_CONTROL_0_CLAMP_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_MGBEBA_CLAMP_CONTROL_0_CLAMP_INIT_ENUM                    ON
#define PMC_IMPL_PART_MGBEBA_CLAMP_CONTROL_0_CLAMP_OFF                  MK_ENUM_CONST(0)
#define PMC_IMPL_PART_MGBEBA_CLAMP_CONTROL_0_CLAMP_ON                   MK_ENUM_CONST(1)


// Register PMC_IMPL_PART_MGBEBB_POWER_GATE_CONTROL_0
#define PMC_IMPL_PART_MGBEBB_POWER_GATE_CONTROL_0                       MK_ADDR_CONST(0x574)
#define PMC_IMPL_PART_MGBEBB_POWER_GATE_CONTROL_0_SECURE                        0x0
#define PMC_IMPL_PART_MGBEBB_POWER_GATE_CONTROL_0_DUAL                  0x0
#define PMC_IMPL_PART_MGBEBB_POWER_GATE_CONTROL_0_SCR                   PG_MGBEBB_SCR_0
#define PMC_IMPL_PART_MGBEBB_POWER_GATE_CONTROL_0_SCRREG                        PMC_IMPL_SCR_PG_MGBEBB_SCR_0
#define PMC_IMPL_PART_MGBEBB_POWER_GATE_CONTROL_0_WORD_COUNT                    0x1
#define PMC_IMPL_PART_MGBEBB_POWER_GATE_CONTROL_0_RESET_VAL                     MK_MASK_CONST(0x80000005)
#define PMC_IMPL_PART_MGBEBB_POWER_GATE_CONTROL_0_RESET_MASK                    MK_MASK_CONST(0x80000107)
#define PMC_IMPL_PART_MGBEBB_POWER_GATE_CONTROL_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_MGBEBB_POWER_GATE_CONTROL_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_MGBEBB_POWER_GATE_CONTROL_0_READ_MASK                     MK_MASK_CONST(0x80000107)
#define PMC_IMPL_PART_MGBEBB_POWER_GATE_CONTROL_0_WRITE_MASK                    MK_MASK_CONST(0x80000105)
#define PMC_IMPL_PART_MGBEBB_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SHIFT                     MK_SHIFT_CONST(31)
#define PMC_IMPL_PART_MGBEBB_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_FIELD                     MK_FIELD_CONST(0x1, PMC_IMPL_PART_MGBEBB_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SHIFT)
#define PMC_IMPL_PART_MGBEBB_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_RANGE                     31:31
#define PMC_IMPL_PART_MGBEBB_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_MSB                       MK_SHIFT_CONST(31)
#define PMC_IMPL_PART_MGBEBB_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_LSB                       MK_SHIFT_CONST(31)
#define PMC_IMPL_PART_MGBEBB_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_WOFFSET                   0x0
#define PMC_IMPL_PART_MGBEBB_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_DEFAULT                   MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_MGBEBB_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_MGBEBB_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_MGBEBB_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_MGBEBB_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_MGBEBB_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_MGBEBB_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_INIT_ENUM                 ENABLE
#define PMC_IMPL_PART_MGBEBB_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_DISABLE                   MK_ENUM_CONST(0)
#define PMC_IMPL_PART_MGBEBB_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_ENABLE                    MK_ENUM_CONST(1)

#define PMC_IMPL_PART_MGBEBB_POWER_GATE_CONTROL_0_START_SHIFT                   MK_SHIFT_CONST(8)
#define PMC_IMPL_PART_MGBEBB_POWER_GATE_CONTROL_0_START_FIELD                   MK_FIELD_CONST(0x1, PMC_IMPL_PART_MGBEBB_POWER_GATE_CONTROL_0_START_SHIFT)
#define PMC_IMPL_PART_MGBEBB_POWER_GATE_CONTROL_0_START_RANGE                   8:8
#define PMC_IMPL_PART_MGBEBB_POWER_GATE_CONTROL_0_START_MSB                     MK_SHIFT_CONST(8)
#define PMC_IMPL_PART_MGBEBB_POWER_GATE_CONTROL_0_START_LSB                     MK_SHIFT_CONST(8)
#define PMC_IMPL_PART_MGBEBB_POWER_GATE_CONTROL_0_START_WOFFSET                 0x0
#define PMC_IMPL_PART_MGBEBB_POWER_GATE_CONTROL_0_START_DEFAULT                 MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_MGBEBB_POWER_GATE_CONTROL_0_START_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_MGBEBB_POWER_GATE_CONTROL_0_START_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_MGBEBB_POWER_GATE_CONTROL_0_START_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_MGBEBB_POWER_GATE_CONTROL_0_START_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_MGBEBB_POWER_GATE_CONTROL_0_START_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_MGBEBB_POWER_GATE_CONTROL_0_START_INIT_ENUM                       DONE
#define PMC_IMPL_PART_MGBEBB_POWER_GATE_CONTROL_0_START_DONE                    MK_ENUM_CONST(0)
#define PMC_IMPL_PART_MGBEBB_POWER_GATE_CONTROL_0_START_PENDING                 MK_ENUM_CONST(1)

#define PMC_IMPL_PART_MGBEBB_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SHIFT                   MK_SHIFT_CONST(2)
#define PMC_IMPL_PART_MGBEBB_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_FIELD                   MK_FIELD_CONST(0x1, PMC_IMPL_PART_MGBEBB_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SHIFT)
#define PMC_IMPL_PART_MGBEBB_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_RANGE                   2:2
#define PMC_IMPL_PART_MGBEBB_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_MSB                     MK_SHIFT_CONST(2)
#define PMC_IMPL_PART_MGBEBB_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_LSB                     MK_SHIFT_CONST(2)
#define PMC_IMPL_PART_MGBEBB_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_WOFFSET                 0x0
#define PMC_IMPL_PART_MGBEBB_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_DEFAULT                 MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_MGBEBB_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_MGBEBB_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_MGBEBB_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_MGBEBB_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_MGBEBB_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_MGBEBB_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_INIT_ENUM                       ON
#define PMC_IMPL_PART_MGBEBB_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_OFF                     MK_ENUM_CONST(0)
#define PMC_IMPL_PART_MGBEBB_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_ON                      MK_ENUM_CONST(1)

#define PMC_IMPL_PART_MGBEBB_POWER_GATE_CONTROL_0_SRAM_RET_EN_SHIFT                     MK_SHIFT_CONST(1)
#define PMC_IMPL_PART_MGBEBB_POWER_GATE_CONTROL_0_SRAM_RET_EN_FIELD                     MK_FIELD_CONST(0x1, PMC_IMPL_PART_MGBEBB_POWER_GATE_CONTROL_0_SRAM_RET_EN_SHIFT)
#define PMC_IMPL_PART_MGBEBB_POWER_GATE_CONTROL_0_SRAM_RET_EN_RANGE                     1:1
#define PMC_IMPL_PART_MGBEBB_POWER_GATE_CONTROL_0_SRAM_RET_EN_MSB                       MK_SHIFT_CONST(1)
#define PMC_IMPL_PART_MGBEBB_POWER_GATE_CONTROL_0_SRAM_RET_EN_LSB                       MK_SHIFT_CONST(1)
#define PMC_IMPL_PART_MGBEBB_POWER_GATE_CONTROL_0_SRAM_RET_EN_WOFFSET                   0x0
#define PMC_IMPL_PART_MGBEBB_POWER_GATE_CONTROL_0_SRAM_RET_EN_DEFAULT                   MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_MGBEBB_POWER_GATE_CONTROL_0_SRAM_RET_EN_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_MGBEBB_POWER_GATE_CONTROL_0_SRAM_RET_EN_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_MGBEBB_POWER_GATE_CONTROL_0_SRAM_RET_EN_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_MGBEBB_POWER_GATE_CONTROL_0_SRAM_RET_EN_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_MGBEBB_POWER_GATE_CONTROL_0_SRAM_RET_EN_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_MGBEBB_POWER_GATE_CONTROL_0_SRAM_RET_EN_INIT_ENUM                 OFF
#define PMC_IMPL_PART_MGBEBB_POWER_GATE_CONTROL_0_SRAM_RET_EN_OFF                       MK_ENUM_CONST(0)
#define PMC_IMPL_PART_MGBEBB_POWER_GATE_CONTROL_0_SRAM_RET_EN_ON                        MK_ENUM_CONST(1)

#define PMC_IMPL_PART_MGBEBB_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SHIFT                     MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_MGBEBB_POWER_GATE_CONTROL_0_LOGIC_SLEEP_FIELD                     MK_FIELD_CONST(0x1, PMC_IMPL_PART_MGBEBB_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SHIFT)
#define PMC_IMPL_PART_MGBEBB_POWER_GATE_CONTROL_0_LOGIC_SLEEP_RANGE                     0:0
#define PMC_IMPL_PART_MGBEBB_POWER_GATE_CONTROL_0_LOGIC_SLEEP_MSB                       MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_MGBEBB_POWER_GATE_CONTROL_0_LOGIC_SLEEP_LSB                       MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_MGBEBB_POWER_GATE_CONTROL_0_LOGIC_SLEEP_WOFFSET                   0x0
#define PMC_IMPL_PART_MGBEBB_POWER_GATE_CONTROL_0_LOGIC_SLEEP_DEFAULT                   MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_MGBEBB_POWER_GATE_CONTROL_0_LOGIC_SLEEP_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_MGBEBB_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_MGBEBB_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_MGBEBB_POWER_GATE_CONTROL_0_LOGIC_SLEEP_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_MGBEBB_POWER_GATE_CONTROL_0_LOGIC_SLEEP_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_MGBEBB_POWER_GATE_CONTROL_0_LOGIC_SLEEP_INIT_ENUM                 ON
#define PMC_IMPL_PART_MGBEBB_POWER_GATE_CONTROL_0_LOGIC_SLEEP_OFF                       MK_ENUM_CONST(0)
#define PMC_IMPL_PART_MGBEBB_POWER_GATE_CONTROL_0_LOGIC_SLEEP_ON                        MK_ENUM_CONST(1)


// Register PMC_IMPL_PART_MGBEBB_POWER_GATE_STATUS_0
#define PMC_IMPL_PART_MGBEBB_POWER_GATE_STATUS_0                        MK_ADDR_CONST(0x578)
#define PMC_IMPL_PART_MGBEBB_POWER_GATE_STATUS_0_SECURE                         0x0
#define PMC_IMPL_PART_MGBEBB_POWER_GATE_STATUS_0_DUAL                   0x0
#define PMC_IMPL_PART_MGBEBB_POWER_GATE_STATUS_0_SCR                    PG_MGBEBB_SCR_0
#define PMC_IMPL_PART_MGBEBB_POWER_GATE_STATUS_0_SCRREG                         PMC_IMPL_SCR_PG_MGBEBB_SCR_0
#define PMC_IMPL_PART_MGBEBB_POWER_GATE_STATUS_0_WORD_COUNT                     0x1
#define PMC_IMPL_PART_MGBEBB_POWER_GATE_STATUS_0_RESET_VAL                      MK_MASK_CONST(0x5)
#define PMC_IMPL_PART_MGBEBB_POWER_GATE_STATUS_0_RESET_MASK                     MK_MASK_CONST(0x7)
#define PMC_IMPL_PART_MGBEBB_POWER_GATE_STATUS_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_MGBEBB_POWER_GATE_STATUS_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_MGBEBB_POWER_GATE_STATUS_0_READ_MASK                      MK_MASK_CONST(0x7)
#define PMC_IMPL_PART_MGBEBB_POWER_GATE_STATUS_0_WRITE_MASK                     MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_MGBEBB_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SHIFT                   MK_SHIFT_CONST(2)
#define PMC_IMPL_PART_MGBEBB_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_FIELD                   MK_FIELD_CONST(0x1, PMC_IMPL_PART_MGBEBB_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SHIFT)
#define PMC_IMPL_PART_MGBEBB_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_RANGE                   2:2
#define PMC_IMPL_PART_MGBEBB_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_MSB                     MK_SHIFT_CONST(2)
#define PMC_IMPL_PART_MGBEBB_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_LSB                     MK_SHIFT_CONST(2)
#define PMC_IMPL_PART_MGBEBB_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_WOFFSET                 0x0
#define PMC_IMPL_PART_MGBEBB_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_DEFAULT                 MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_MGBEBB_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_MGBEBB_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_MGBEBB_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_MGBEBB_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_MGBEBB_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_MGBEBB_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_INIT_ENUM                       ON
#define PMC_IMPL_PART_MGBEBB_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_OFF                     MK_ENUM_CONST(0)
#define PMC_IMPL_PART_MGBEBB_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_ON                      MK_ENUM_CONST(1)

#define PMC_IMPL_PART_MGBEBB_POWER_GATE_STATUS_0_SRAM_RET_STS_SHIFT                     MK_SHIFT_CONST(1)
#define PMC_IMPL_PART_MGBEBB_POWER_GATE_STATUS_0_SRAM_RET_STS_FIELD                     MK_FIELD_CONST(0x1, PMC_IMPL_PART_MGBEBB_POWER_GATE_STATUS_0_SRAM_RET_STS_SHIFT)
#define PMC_IMPL_PART_MGBEBB_POWER_GATE_STATUS_0_SRAM_RET_STS_RANGE                     1:1
#define PMC_IMPL_PART_MGBEBB_POWER_GATE_STATUS_0_SRAM_RET_STS_MSB                       MK_SHIFT_CONST(1)
#define PMC_IMPL_PART_MGBEBB_POWER_GATE_STATUS_0_SRAM_RET_STS_LSB                       MK_SHIFT_CONST(1)
#define PMC_IMPL_PART_MGBEBB_POWER_GATE_STATUS_0_SRAM_RET_STS_WOFFSET                   0x0
#define PMC_IMPL_PART_MGBEBB_POWER_GATE_STATUS_0_SRAM_RET_STS_DEFAULT                   MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_MGBEBB_POWER_GATE_STATUS_0_SRAM_RET_STS_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_MGBEBB_POWER_GATE_STATUS_0_SRAM_RET_STS_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_MGBEBB_POWER_GATE_STATUS_0_SRAM_RET_STS_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_MGBEBB_POWER_GATE_STATUS_0_SRAM_RET_STS_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_MGBEBB_POWER_GATE_STATUS_0_SRAM_RET_STS_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_MGBEBB_POWER_GATE_STATUS_0_SRAM_RET_STS_INIT_ENUM                 OFF
#define PMC_IMPL_PART_MGBEBB_POWER_GATE_STATUS_0_SRAM_RET_STS_OFF                       MK_ENUM_CONST(0)
#define PMC_IMPL_PART_MGBEBB_POWER_GATE_STATUS_0_SRAM_RET_STS_ON                        MK_ENUM_CONST(1)

#define PMC_IMPL_PART_MGBEBB_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SHIFT                  MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_MGBEBB_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_FIELD                  MK_FIELD_CONST(0x1, PMC_IMPL_PART_MGBEBB_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SHIFT)
#define PMC_IMPL_PART_MGBEBB_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_RANGE                  0:0
#define PMC_IMPL_PART_MGBEBB_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_MSB                    MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_MGBEBB_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_LSB                    MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_MGBEBB_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_WOFFSET                        0x0
#define PMC_IMPL_PART_MGBEBB_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_DEFAULT                        MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_MGBEBB_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_MGBEBB_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_MGBEBB_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_MGBEBB_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_MGBEBB_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_MGBEBB_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_INIT_ENUM                      ON
#define PMC_IMPL_PART_MGBEBB_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_OFF                    MK_ENUM_CONST(0)
#define PMC_IMPL_PART_MGBEBB_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_ON                     MK_ENUM_CONST(1)


// Register PMC_IMPL_PART_MGBEBB_CLAMP_CONTROL_0
#define PMC_IMPL_PART_MGBEBB_CLAMP_CONTROL_0                    MK_ADDR_CONST(0x57c)
#define PMC_IMPL_PART_MGBEBB_CLAMP_CONTROL_0_SECURE                     0x0
#define PMC_IMPL_PART_MGBEBB_CLAMP_CONTROL_0_DUAL                       0x0
#define PMC_IMPL_PART_MGBEBB_CLAMP_CONTROL_0_SCR                        PG_MGBEBB_SCR_0
#define PMC_IMPL_PART_MGBEBB_CLAMP_CONTROL_0_SCRREG                     PMC_IMPL_SCR_PG_MGBEBB_SCR_0
#define PMC_IMPL_PART_MGBEBB_CLAMP_CONTROL_0_WORD_COUNT                         0x1
#define PMC_IMPL_PART_MGBEBB_CLAMP_CONTROL_0_RESET_VAL                  MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_MGBEBB_CLAMP_CONTROL_0_RESET_MASK                         MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_MGBEBB_CLAMP_CONTROL_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_MGBEBB_CLAMP_CONTROL_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_MGBEBB_CLAMP_CONTROL_0_READ_MASK                  MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_MGBEBB_CLAMP_CONTROL_0_WRITE_MASK                         MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_MGBEBB_CLAMP_CONTROL_0_CLAMP_SHIFT                        MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_MGBEBB_CLAMP_CONTROL_0_CLAMP_FIELD                        MK_FIELD_CONST(0x1, PMC_IMPL_PART_MGBEBB_CLAMP_CONTROL_0_CLAMP_SHIFT)
#define PMC_IMPL_PART_MGBEBB_CLAMP_CONTROL_0_CLAMP_RANGE                        0:0
#define PMC_IMPL_PART_MGBEBB_CLAMP_CONTROL_0_CLAMP_MSB                  MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_MGBEBB_CLAMP_CONTROL_0_CLAMP_LSB                  MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_MGBEBB_CLAMP_CONTROL_0_CLAMP_WOFFSET                      0x0
#define PMC_IMPL_PART_MGBEBB_CLAMP_CONTROL_0_CLAMP_DEFAULT                      MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_MGBEBB_CLAMP_CONTROL_0_CLAMP_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_MGBEBB_CLAMP_CONTROL_0_CLAMP_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_MGBEBB_CLAMP_CONTROL_0_CLAMP_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_MGBEBB_CLAMP_CONTROL_0_CLAMP_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_MGBEBB_CLAMP_CONTROL_0_CLAMP_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_MGBEBB_CLAMP_CONTROL_0_CLAMP_INIT_ENUM                    ON
#define PMC_IMPL_PART_MGBEBB_CLAMP_CONTROL_0_CLAMP_OFF                  MK_ENUM_CONST(0)
#define PMC_IMPL_PART_MGBEBB_CLAMP_CONTROL_0_CLAMP_ON                   MK_ENUM_CONST(1)


// Register PMC_IMPL_PART_MGBEBC_POWER_GATE_CONTROL_0
#define PMC_IMPL_PART_MGBEBC_POWER_GATE_CONTROL_0                       MK_ADDR_CONST(0x580)
#define PMC_IMPL_PART_MGBEBC_POWER_GATE_CONTROL_0_SECURE                        0x0
#define PMC_IMPL_PART_MGBEBC_POWER_GATE_CONTROL_0_DUAL                  0x0
#define PMC_IMPL_PART_MGBEBC_POWER_GATE_CONTROL_0_SCR                   PG_MGBEBC_SCR_0
#define PMC_IMPL_PART_MGBEBC_POWER_GATE_CONTROL_0_SCRREG                        PMC_IMPL_SCR_PG_MGBEBC_SCR_0
#define PMC_IMPL_PART_MGBEBC_POWER_GATE_CONTROL_0_WORD_COUNT                    0x1
#define PMC_IMPL_PART_MGBEBC_POWER_GATE_CONTROL_0_RESET_VAL                     MK_MASK_CONST(0x80000005)
#define PMC_IMPL_PART_MGBEBC_POWER_GATE_CONTROL_0_RESET_MASK                    MK_MASK_CONST(0x80000107)
#define PMC_IMPL_PART_MGBEBC_POWER_GATE_CONTROL_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_MGBEBC_POWER_GATE_CONTROL_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_MGBEBC_POWER_GATE_CONTROL_0_READ_MASK                     MK_MASK_CONST(0x80000107)
#define PMC_IMPL_PART_MGBEBC_POWER_GATE_CONTROL_0_WRITE_MASK                    MK_MASK_CONST(0x80000105)
#define PMC_IMPL_PART_MGBEBC_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SHIFT                     MK_SHIFT_CONST(31)
#define PMC_IMPL_PART_MGBEBC_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_FIELD                     MK_FIELD_CONST(0x1, PMC_IMPL_PART_MGBEBC_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SHIFT)
#define PMC_IMPL_PART_MGBEBC_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_RANGE                     31:31
#define PMC_IMPL_PART_MGBEBC_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_MSB                       MK_SHIFT_CONST(31)
#define PMC_IMPL_PART_MGBEBC_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_LSB                       MK_SHIFT_CONST(31)
#define PMC_IMPL_PART_MGBEBC_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_WOFFSET                   0x0
#define PMC_IMPL_PART_MGBEBC_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_DEFAULT                   MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_MGBEBC_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_MGBEBC_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_MGBEBC_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_MGBEBC_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_MGBEBC_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_MGBEBC_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_INIT_ENUM                 ENABLE
#define PMC_IMPL_PART_MGBEBC_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_DISABLE                   MK_ENUM_CONST(0)
#define PMC_IMPL_PART_MGBEBC_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_ENABLE                    MK_ENUM_CONST(1)

#define PMC_IMPL_PART_MGBEBC_POWER_GATE_CONTROL_0_START_SHIFT                   MK_SHIFT_CONST(8)
#define PMC_IMPL_PART_MGBEBC_POWER_GATE_CONTROL_0_START_FIELD                   MK_FIELD_CONST(0x1, PMC_IMPL_PART_MGBEBC_POWER_GATE_CONTROL_0_START_SHIFT)
#define PMC_IMPL_PART_MGBEBC_POWER_GATE_CONTROL_0_START_RANGE                   8:8
#define PMC_IMPL_PART_MGBEBC_POWER_GATE_CONTROL_0_START_MSB                     MK_SHIFT_CONST(8)
#define PMC_IMPL_PART_MGBEBC_POWER_GATE_CONTROL_0_START_LSB                     MK_SHIFT_CONST(8)
#define PMC_IMPL_PART_MGBEBC_POWER_GATE_CONTROL_0_START_WOFFSET                 0x0
#define PMC_IMPL_PART_MGBEBC_POWER_GATE_CONTROL_0_START_DEFAULT                 MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_MGBEBC_POWER_GATE_CONTROL_0_START_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_MGBEBC_POWER_GATE_CONTROL_0_START_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_MGBEBC_POWER_GATE_CONTROL_0_START_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_MGBEBC_POWER_GATE_CONTROL_0_START_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_MGBEBC_POWER_GATE_CONTROL_0_START_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_MGBEBC_POWER_GATE_CONTROL_0_START_INIT_ENUM                       DONE
#define PMC_IMPL_PART_MGBEBC_POWER_GATE_CONTROL_0_START_DONE                    MK_ENUM_CONST(0)
#define PMC_IMPL_PART_MGBEBC_POWER_GATE_CONTROL_0_START_PENDING                 MK_ENUM_CONST(1)

#define PMC_IMPL_PART_MGBEBC_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SHIFT                   MK_SHIFT_CONST(2)
#define PMC_IMPL_PART_MGBEBC_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_FIELD                   MK_FIELD_CONST(0x1, PMC_IMPL_PART_MGBEBC_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SHIFT)
#define PMC_IMPL_PART_MGBEBC_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_RANGE                   2:2
#define PMC_IMPL_PART_MGBEBC_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_MSB                     MK_SHIFT_CONST(2)
#define PMC_IMPL_PART_MGBEBC_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_LSB                     MK_SHIFT_CONST(2)
#define PMC_IMPL_PART_MGBEBC_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_WOFFSET                 0x0
#define PMC_IMPL_PART_MGBEBC_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_DEFAULT                 MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_MGBEBC_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_MGBEBC_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_MGBEBC_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_MGBEBC_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_MGBEBC_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_MGBEBC_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_INIT_ENUM                       ON
#define PMC_IMPL_PART_MGBEBC_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_OFF                     MK_ENUM_CONST(0)
#define PMC_IMPL_PART_MGBEBC_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_ON                      MK_ENUM_CONST(1)

#define PMC_IMPL_PART_MGBEBC_POWER_GATE_CONTROL_0_SRAM_RET_EN_SHIFT                     MK_SHIFT_CONST(1)
#define PMC_IMPL_PART_MGBEBC_POWER_GATE_CONTROL_0_SRAM_RET_EN_FIELD                     MK_FIELD_CONST(0x1, PMC_IMPL_PART_MGBEBC_POWER_GATE_CONTROL_0_SRAM_RET_EN_SHIFT)
#define PMC_IMPL_PART_MGBEBC_POWER_GATE_CONTROL_0_SRAM_RET_EN_RANGE                     1:1
#define PMC_IMPL_PART_MGBEBC_POWER_GATE_CONTROL_0_SRAM_RET_EN_MSB                       MK_SHIFT_CONST(1)
#define PMC_IMPL_PART_MGBEBC_POWER_GATE_CONTROL_0_SRAM_RET_EN_LSB                       MK_SHIFT_CONST(1)
#define PMC_IMPL_PART_MGBEBC_POWER_GATE_CONTROL_0_SRAM_RET_EN_WOFFSET                   0x0
#define PMC_IMPL_PART_MGBEBC_POWER_GATE_CONTROL_0_SRAM_RET_EN_DEFAULT                   MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_MGBEBC_POWER_GATE_CONTROL_0_SRAM_RET_EN_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_MGBEBC_POWER_GATE_CONTROL_0_SRAM_RET_EN_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_MGBEBC_POWER_GATE_CONTROL_0_SRAM_RET_EN_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_MGBEBC_POWER_GATE_CONTROL_0_SRAM_RET_EN_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_MGBEBC_POWER_GATE_CONTROL_0_SRAM_RET_EN_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_MGBEBC_POWER_GATE_CONTROL_0_SRAM_RET_EN_INIT_ENUM                 OFF
#define PMC_IMPL_PART_MGBEBC_POWER_GATE_CONTROL_0_SRAM_RET_EN_OFF                       MK_ENUM_CONST(0)
#define PMC_IMPL_PART_MGBEBC_POWER_GATE_CONTROL_0_SRAM_RET_EN_ON                        MK_ENUM_CONST(1)

#define PMC_IMPL_PART_MGBEBC_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SHIFT                     MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_MGBEBC_POWER_GATE_CONTROL_0_LOGIC_SLEEP_FIELD                     MK_FIELD_CONST(0x1, PMC_IMPL_PART_MGBEBC_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SHIFT)
#define PMC_IMPL_PART_MGBEBC_POWER_GATE_CONTROL_0_LOGIC_SLEEP_RANGE                     0:0
#define PMC_IMPL_PART_MGBEBC_POWER_GATE_CONTROL_0_LOGIC_SLEEP_MSB                       MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_MGBEBC_POWER_GATE_CONTROL_0_LOGIC_SLEEP_LSB                       MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_MGBEBC_POWER_GATE_CONTROL_0_LOGIC_SLEEP_WOFFSET                   0x0
#define PMC_IMPL_PART_MGBEBC_POWER_GATE_CONTROL_0_LOGIC_SLEEP_DEFAULT                   MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_MGBEBC_POWER_GATE_CONTROL_0_LOGIC_SLEEP_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_MGBEBC_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_MGBEBC_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_MGBEBC_POWER_GATE_CONTROL_0_LOGIC_SLEEP_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_MGBEBC_POWER_GATE_CONTROL_0_LOGIC_SLEEP_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_MGBEBC_POWER_GATE_CONTROL_0_LOGIC_SLEEP_INIT_ENUM                 ON
#define PMC_IMPL_PART_MGBEBC_POWER_GATE_CONTROL_0_LOGIC_SLEEP_OFF                       MK_ENUM_CONST(0)
#define PMC_IMPL_PART_MGBEBC_POWER_GATE_CONTROL_0_LOGIC_SLEEP_ON                        MK_ENUM_CONST(1)


// Register PMC_IMPL_PART_MGBEBC_POWER_GATE_STATUS_0
#define PMC_IMPL_PART_MGBEBC_POWER_GATE_STATUS_0                        MK_ADDR_CONST(0x584)
#define PMC_IMPL_PART_MGBEBC_POWER_GATE_STATUS_0_SECURE                         0x0
#define PMC_IMPL_PART_MGBEBC_POWER_GATE_STATUS_0_DUAL                   0x0
#define PMC_IMPL_PART_MGBEBC_POWER_GATE_STATUS_0_SCR                    PG_MGBEBC_SCR_0
#define PMC_IMPL_PART_MGBEBC_POWER_GATE_STATUS_0_SCRREG                         PMC_IMPL_SCR_PG_MGBEBC_SCR_0
#define PMC_IMPL_PART_MGBEBC_POWER_GATE_STATUS_0_WORD_COUNT                     0x1
#define PMC_IMPL_PART_MGBEBC_POWER_GATE_STATUS_0_RESET_VAL                      MK_MASK_CONST(0x5)
#define PMC_IMPL_PART_MGBEBC_POWER_GATE_STATUS_0_RESET_MASK                     MK_MASK_CONST(0x7)
#define PMC_IMPL_PART_MGBEBC_POWER_GATE_STATUS_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_MGBEBC_POWER_GATE_STATUS_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_MGBEBC_POWER_GATE_STATUS_0_READ_MASK                      MK_MASK_CONST(0x7)
#define PMC_IMPL_PART_MGBEBC_POWER_GATE_STATUS_0_WRITE_MASK                     MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_MGBEBC_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SHIFT                   MK_SHIFT_CONST(2)
#define PMC_IMPL_PART_MGBEBC_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_FIELD                   MK_FIELD_CONST(0x1, PMC_IMPL_PART_MGBEBC_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SHIFT)
#define PMC_IMPL_PART_MGBEBC_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_RANGE                   2:2
#define PMC_IMPL_PART_MGBEBC_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_MSB                     MK_SHIFT_CONST(2)
#define PMC_IMPL_PART_MGBEBC_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_LSB                     MK_SHIFT_CONST(2)
#define PMC_IMPL_PART_MGBEBC_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_WOFFSET                 0x0
#define PMC_IMPL_PART_MGBEBC_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_DEFAULT                 MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_MGBEBC_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_MGBEBC_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_MGBEBC_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_MGBEBC_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_MGBEBC_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_MGBEBC_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_INIT_ENUM                       ON
#define PMC_IMPL_PART_MGBEBC_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_OFF                     MK_ENUM_CONST(0)
#define PMC_IMPL_PART_MGBEBC_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_ON                      MK_ENUM_CONST(1)

#define PMC_IMPL_PART_MGBEBC_POWER_GATE_STATUS_0_SRAM_RET_STS_SHIFT                     MK_SHIFT_CONST(1)
#define PMC_IMPL_PART_MGBEBC_POWER_GATE_STATUS_0_SRAM_RET_STS_FIELD                     MK_FIELD_CONST(0x1, PMC_IMPL_PART_MGBEBC_POWER_GATE_STATUS_0_SRAM_RET_STS_SHIFT)
#define PMC_IMPL_PART_MGBEBC_POWER_GATE_STATUS_0_SRAM_RET_STS_RANGE                     1:1
#define PMC_IMPL_PART_MGBEBC_POWER_GATE_STATUS_0_SRAM_RET_STS_MSB                       MK_SHIFT_CONST(1)
#define PMC_IMPL_PART_MGBEBC_POWER_GATE_STATUS_0_SRAM_RET_STS_LSB                       MK_SHIFT_CONST(1)
#define PMC_IMPL_PART_MGBEBC_POWER_GATE_STATUS_0_SRAM_RET_STS_WOFFSET                   0x0
#define PMC_IMPL_PART_MGBEBC_POWER_GATE_STATUS_0_SRAM_RET_STS_DEFAULT                   MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_MGBEBC_POWER_GATE_STATUS_0_SRAM_RET_STS_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_MGBEBC_POWER_GATE_STATUS_0_SRAM_RET_STS_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_MGBEBC_POWER_GATE_STATUS_0_SRAM_RET_STS_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_MGBEBC_POWER_GATE_STATUS_0_SRAM_RET_STS_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_MGBEBC_POWER_GATE_STATUS_0_SRAM_RET_STS_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_MGBEBC_POWER_GATE_STATUS_0_SRAM_RET_STS_INIT_ENUM                 OFF
#define PMC_IMPL_PART_MGBEBC_POWER_GATE_STATUS_0_SRAM_RET_STS_OFF                       MK_ENUM_CONST(0)
#define PMC_IMPL_PART_MGBEBC_POWER_GATE_STATUS_0_SRAM_RET_STS_ON                        MK_ENUM_CONST(1)

#define PMC_IMPL_PART_MGBEBC_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SHIFT                  MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_MGBEBC_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_FIELD                  MK_FIELD_CONST(0x1, PMC_IMPL_PART_MGBEBC_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SHIFT)
#define PMC_IMPL_PART_MGBEBC_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_RANGE                  0:0
#define PMC_IMPL_PART_MGBEBC_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_MSB                    MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_MGBEBC_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_LSB                    MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_MGBEBC_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_WOFFSET                        0x0
#define PMC_IMPL_PART_MGBEBC_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_DEFAULT                        MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_MGBEBC_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_MGBEBC_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_MGBEBC_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_MGBEBC_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_MGBEBC_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_MGBEBC_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_INIT_ENUM                      ON
#define PMC_IMPL_PART_MGBEBC_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_OFF                    MK_ENUM_CONST(0)
#define PMC_IMPL_PART_MGBEBC_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_ON                     MK_ENUM_CONST(1)


// Register PMC_IMPL_PART_MGBEBC_CLAMP_CONTROL_0
#define PMC_IMPL_PART_MGBEBC_CLAMP_CONTROL_0                    MK_ADDR_CONST(0x588)
#define PMC_IMPL_PART_MGBEBC_CLAMP_CONTROL_0_SECURE                     0x0
#define PMC_IMPL_PART_MGBEBC_CLAMP_CONTROL_0_DUAL                       0x0
#define PMC_IMPL_PART_MGBEBC_CLAMP_CONTROL_0_SCR                        PG_MGBEBC_SCR_0
#define PMC_IMPL_PART_MGBEBC_CLAMP_CONTROL_0_SCRREG                     PMC_IMPL_SCR_PG_MGBEBC_SCR_0
#define PMC_IMPL_PART_MGBEBC_CLAMP_CONTROL_0_WORD_COUNT                         0x1
#define PMC_IMPL_PART_MGBEBC_CLAMP_CONTROL_0_RESET_VAL                  MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_MGBEBC_CLAMP_CONTROL_0_RESET_MASK                         MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_MGBEBC_CLAMP_CONTROL_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_MGBEBC_CLAMP_CONTROL_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_MGBEBC_CLAMP_CONTROL_0_READ_MASK                  MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_MGBEBC_CLAMP_CONTROL_0_WRITE_MASK                         MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_MGBEBC_CLAMP_CONTROL_0_CLAMP_SHIFT                        MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_MGBEBC_CLAMP_CONTROL_0_CLAMP_FIELD                        MK_FIELD_CONST(0x1, PMC_IMPL_PART_MGBEBC_CLAMP_CONTROL_0_CLAMP_SHIFT)
#define PMC_IMPL_PART_MGBEBC_CLAMP_CONTROL_0_CLAMP_RANGE                        0:0
#define PMC_IMPL_PART_MGBEBC_CLAMP_CONTROL_0_CLAMP_MSB                  MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_MGBEBC_CLAMP_CONTROL_0_CLAMP_LSB                  MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_MGBEBC_CLAMP_CONTROL_0_CLAMP_WOFFSET                      0x0
#define PMC_IMPL_PART_MGBEBC_CLAMP_CONTROL_0_CLAMP_DEFAULT                      MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_MGBEBC_CLAMP_CONTROL_0_CLAMP_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_MGBEBC_CLAMP_CONTROL_0_CLAMP_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_MGBEBC_CLAMP_CONTROL_0_CLAMP_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_MGBEBC_CLAMP_CONTROL_0_CLAMP_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_MGBEBC_CLAMP_CONTROL_0_CLAMP_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_MGBEBC_CLAMP_CONTROL_0_CLAMP_INIT_ENUM                    ON
#define PMC_IMPL_PART_MGBEBC_CLAMP_CONTROL_0_CLAMP_OFF                  MK_ENUM_CONST(0)
#define PMC_IMPL_PART_MGBEBC_CLAMP_CONTROL_0_CLAMP_ON                   MK_ENUM_CONST(1)


// Reserved address 0x58c

// Reserved address 0x590

// Reserved address 0x594

// Reserved address 0x598

// Reserved address 0x59c

// Reserved address 0x5a0

// Reserved address 0x5a4

// Reserved address 0x5a8

// Reserved address 0x5ac

// Reserved address 0x5b0

// Reserved address 0x5b4

// Reserved address 0x5b8

// Reserved address 0x5bc

// Reserved address 0x5c0

// Reserved address 0x5c4

// Register PMC_IMPL_PART_DBBRAM_POWER_GATE_CONTROL_0
#define PMC_IMPL_PART_DBBRAM_POWER_GATE_CONTROL_0                       MK_ADDR_CONST(0x5c8)
#define PMC_IMPL_PART_DBBRAM_POWER_GATE_CONTROL_0_SECURE                        0x0
#define PMC_IMPL_PART_DBBRAM_POWER_GATE_CONTROL_0_DUAL                  0x0
#define PMC_IMPL_PART_DBBRAM_POWER_GATE_CONTROL_0_SCR                   PG_DBBRAM_SCR_0
#define PMC_IMPL_PART_DBBRAM_POWER_GATE_CONTROL_0_SCRREG                        PMC_IMPL_SCR_PG_DBBRAM_SCR_0
#define PMC_IMPL_PART_DBBRAM_POWER_GATE_CONTROL_0_WORD_COUNT                    0x1
#define PMC_IMPL_PART_DBBRAM_POWER_GATE_CONTROL_0_RESET_VAL                     MK_MASK_CONST(0x80000000)
#define PMC_IMPL_PART_DBBRAM_POWER_GATE_CONTROL_0_RESET_MASK                    MK_MASK_CONST(0x80000107)
#define PMC_IMPL_PART_DBBRAM_POWER_GATE_CONTROL_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_DBBRAM_POWER_GATE_CONTROL_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_DBBRAM_POWER_GATE_CONTROL_0_READ_MASK                     MK_MASK_CONST(0x80000107)
#define PMC_IMPL_PART_DBBRAM_POWER_GATE_CONTROL_0_WRITE_MASK                    MK_MASK_CONST(0x80000106)
#define PMC_IMPL_PART_DBBRAM_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SHIFT                     MK_SHIFT_CONST(31)
#define PMC_IMPL_PART_DBBRAM_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_FIELD                     MK_FIELD_CONST(0x1, PMC_IMPL_PART_DBBRAM_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SHIFT)
#define PMC_IMPL_PART_DBBRAM_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_RANGE                     31:31
#define PMC_IMPL_PART_DBBRAM_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_MSB                       MK_SHIFT_CONST(31)
#define PMC_IMPL_PART_DBBRAM_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_LSB                       MK_SHIFT_CONST(31)
#define PMC_IMPL_PART_DBBRAM_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_WOFFSET                   0x0
#define PMC_IMPL_PART_DBBRAM_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_DEFAULT                   MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_DBBRAM_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_DBBRAM_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_DBBRAM_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_DBBRAM_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_DBBRAM_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_DBBRAM_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_INIT_ENUM                 ENABLE
#define PMC_IMPL_PART_DBBRAM_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_DISABLE                   MK_ENUM_CONST(0)
#define PMC_IMPL_PART_DBBRAM_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_ENABLE                    MK_ENUM_CONST(1)

#define PMC_IMPL_PART_DBBRAM_POWER_GATE_CONTROL_0_START_SHIFT                   MK_SHIFT_CONST(8)
#define PMC_IMPL_PART_DBBRAM_POWER_GATE_CONTROL_0_START_FIELD                   MK_FIELD_CONST(0x1, PMC_IMPL_PART_DBBRAM_POWER_GATE_CONTROL_0_START_SHIFT)
#define PMC_IMPL_PART_DBBRAM_POWER_GATE_CONTROL_0_START_RANGE                   8:8
#define PMC_IMPL_PART_DBBRAM_POWER_GATE_CONTROL_0_START_MSB                     MK_SHIFT_CONST(8)
#define PMC_IMPL_PART_DBBRAM_POWER_GATE_CONTROL_0_START_LSB                     MK_SHIFT_CONST(8)
#define PMC_IMPL_PART_DBBRAM_POWER_GATE_CONTROL_0_START_WOFFSET                 0x0
#define PMC_IMPL_PART_DBBRAM_POWER_GATE_CONTROL_0_START_DEFAULT                 MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_DBBRAM_POWER_GATE_CONTROL_0_START_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_DBBRAM_POWER_GATE_CONTROL_0_START_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_DBBRAM_POWER_GATE_CONTROL_0_START_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_DBBRAM_POWER_GATE_CONTROL_0_START_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_DBBRAM_POWER_GATE_CONTROL_0_START_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_DBBRAM_POWER_GATE_CONTROL_0_START_INIT_ENUM                       DONE
#define PMC_IMPL_PART_DBBRAM_POWER_GATE_CONTROL_0_START_DONE                    MK_ENUM_CONST(0)
#define PMC_IMPL_PART_DBBRAM_POWER_GATE_CONTROL_0_START_PENDING                 MK_ENUM_CONST(1)

#define PMC_IMPL_PART_DBBRAM_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SHIFT                   MK_SHIFT_CONST(2)
#define PMC_IMPL_PART_DBBRAM_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_FIELD                   MK_FIELD_CONST(0x1, PMC_IMPL_PART_DBBRAM_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SHIFT)
#define PMC_IMPL_PART_DBBRAM_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_RANGE                   2:2
#define PMC_IMPL_PART_DBBRAM_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_MSB                     MK_SHIFT_CONST(2)
#define PMC_IMPL_PART_DBBRAM_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_LSB                     MK_SHIFT_CONST(2)
#define PMC_IMPL_PART_DBBRAM_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_WOFFSET                 0x0
#define PMC_IMPL_PART_DBBRAM_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_DEFAULT                 MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_DBBRAM_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_DBBRAM_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_DBBRAM_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_DBBRAM_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_DBBRAM_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_DBBRAM_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_INIT_ENUM                       OFF
#define PMC_IMPL_PART_DBBRAM_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_OFF                     MK_ENUM_CONST(0)
#define PMC_IMPL_PART_DBBRAM_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_ON                      MK_ENUM_CONST(1)

#define PMC_IMPL_PART_DBBRAM_POWER_GATE_CONTROL_0_SRAM_RET_EN_SHIFT                     MK_SHIFT_CONST(1)
#define PMC_IMPL_PART_DBBRAM_POWER_GATE_CONTROL_0_SRAM_RET_EN_FIELD                     MK_FIELD_CONST(0x1, PMC_IMPL_PART_DBBRAM_POWER_GATE_CONTROL_0_SRAM_RET_EN_SHIFT)
#define PMC_IMPL_PART_DBBRAM_POWER_GATE_CONTROL_0_SRAM_RET_EN_RANGE                     1:1
#define PMC_IMPL_PART_DBBRAM_POWER_GATE_CONTROL_0_SRAM_RET_EN_MSB                       MK_SHIFT_CONST(1)
#define PMC_IMPL_PART_DBBRAM_POWER_GATE_CONTROL_0_SRAM_RET_EN_LSB                       MK_SHIFT_CONST(1)
#define PMC_IMPL_PART_DBBRAM_POWER_GATE_CONTROL_0_SRAM_RET_EN_WOFFSET                   0x0
#define PMC_IMPL_PART_DBBRAM_POWER_GATE_CONTROL_0_SRAM_RET_EN_DEFAULT                   MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_DBBRAM_POWER_GATE_CONTROL_0_SRAM_RET_EN_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_DBBRAM_POWER_GATE_CONTROL_0_SRAM_RET_EN_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_DBBRAM_POWER_GATE_CONTROL_0_SRAM_RET_EN_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_DBBRAM_POWER_GATE_CONTROL_0_SRAM_RET_EN_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_DBBRAM_POWER_GATE_CONTROL_0_SRAM_RET_EN_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_DBBRAM_POWER_GATE_CONTROL_0_SRAM_RET_EN_INIT_ENUM                 OFF
#define PMC_IMPL_PART_DBBRAM_POWER_GATE_CONTROL_0_SRAM_RET_EN_OFF                       MK_ENUM_CONST(0)
#define PMC_IMPL_PART_DBBRAM_POWER_GATE_CONTROL_0_SRAM_RET_EN_ON                        MK_ENUM_CONST(1)

#define PMC_IMPL_PART_DBBRAM_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SHIFT                     MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_DBBRAM_POWER_GATE_CONTROL_0_LOGIC_SLEEP_FIELD                     MK_FIELD_CONST(0x1, PMC_IMPL_PART_DBBRAM_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SHIFT)
#define PMC_IMPL_PART_DBBRAM_POWER_GATE_CONTROL_0_LOGIC_SLEEP_RANGE                     0:0
#define PMC_IMPL_PART_DBBRAM_POWER_GATE_CONTROL_0_LOGIC_SLEEP_MSB                       MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_DBBRAM_POWER_GATE_CONTROL_0_LOGIC_SLEEP_LSB                       MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_DBBRAM_POWER_GATE_CONTROL_0_LOGIC_SLEEP_WOFFSET                   0x0
#define PMC_IMPL_PART_DBBRAM_POWER_GATE_CONTROL_0_LOGIC_SLEEP_DEFAULT                   MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_DBBRAM_POWER_GATE_CONTROL_0_LOGIC_SLEEP_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_DBBRAM_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_DBBRAM_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_DBBRAM_POWER_GATE_CONTROL_0_LOGIC_SLEEP_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_DBBRAM_POWER_GATE_CONTROL_0_LOGIC_SLEEP_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_DBBRAM_POWER_GATE_CONTROL_0_LOGIC_SLEEP_INIT_ENUM                 OFF
#define PMC_IMPL_PART_DBBRAM_POWER_GATE_CONTROL_0_LOGIC_SLEEP_OFF                       MK_ENUM_CONST(0)
#define PMC_IMPL_PART_DBBRAM_POWER_GATE_CONTROL_0_LOGIC_SLEEP_ON                        MK_ENUM_CONST(1)


// Register PMC_IMPL_PART_DBBRAM_POWER_GATE_STATUS_0
#define PMC_IMPL_PART_DBBRAM_POWER_GATE_STATUS_0                        MK_ADDR_CONST(0x5cc)
#define PMC_IMPL_PART_DBBRAM_POWER_GATE_STATUS_0_SECURE                         0x0
#define PMC_IMPL_PART_DBBRAM_POWER_GATE_STATUS_0_DUAL                   0x0
#define PMC_IMPL_PART_DBBRAM_POWER_GATE_STATUS_0_SCR                    PG_DBBRAM_SCR_0
#define PMC_IMPL_PART_DBBRAM_POWER_GATE_STATUS_0_SCRREG                         PMC_IMPL_SCR_PG_DBBRAM_SCR_0
#define PMC_IMPL_PART_DBBRAM_POWER_GATE_STATUS_0_WORD_COUNT                     0x1
#define PMC_IMPL_PART_DBBRAM_POWER_GATE_STATUS_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_DBBRAM_POWER_GATE_STATUS_0_RESET_MASK                     MK_MASK_CONST(0x7)
#define PMC_IMPL_PART_DBBRAM_POWER_GATE_STATUS_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_DBBRAM_POWER_GATE_STATUS_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_DBBRAM_POWER_GATE_STATUS_0_READ_MASK                      MK_MASK_CONST(0x7)
#define PMC_IMPL_PART_DBBRAM_POWER_GATE_STATUS_0_WRITE_MASK                     MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_DBBRAM_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SHIFT                   MK_SHIFT_CONST(2)
#define PMC_IMPL_PART_DBBRAM_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_FIELD                   MK_FIELD_CONST(0x1, PMC_IMPL_PART_DBBRAM_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SHIFT)
#define PMC_IMPL_PART_DBBRAM_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_RANGE                   2:2
#define PMC_IMPL_PART_DBBRAM_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_MSB                     MK_SHIFT_CONST(2)
#define PMC_IMPL_PART_DBBRAM_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_LSB                     MK_SHIFT_CONST(2)
#define PMC_IMPL_PART_DBBRAM_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_WOFFSET                 0x0
#define PMC_IMPL_PART_DBBRAM_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_DEFAULT                 MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_DBBRAM_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_DBBRAM_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_DBBRAM_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_DBBRAM_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_DBBRAM_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_DBBRAM_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_INIT_ENUM                       OFF
#define PMC_IMPL_PART_DBBRAM_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_OFF                     MK_ENUM_CONST(0)
#define PMC_IMPL_PART_DBBRAM_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_ON                      MK_ENUM_CONST(1)

#define PMC_IMPL_PART_DBBRAM_POWER_GATE_STATUS_0_SRAM_RET_STS_SHIFT                     MK_SHIFT_CONST(1)
#define PMC_IMPL_PART_DBBRAM_POWER_GATE_STATUS_0_SRAM_RET_STS_FIELD                     MK_FIELD_CONST(0x1, PMC_IMPL_PART_DBBRAM_POWER_GATE_STATUS_0_SRAM_RET_STS_SHIFT)
#define PMC_IMPL_PART_DBBRAM_POWER_GATE_STATUS_0_SRAM_RET_STS_RANGE                     1:1
#define PMC_IMPL_PART_DBBRAM_POWER_GATE_STATUS_0_SRAM_RET_STS_MSB                       MK_SHIFT_CONST(1)
#define PMC_IMPL_PART_DBBRAM_POWER_GATE_STATUS_0_SRAM_RET_STS_LSB                       MK_SHIFT_CONST(1)
#define PMC_IMPL_PART_DBBRAM_POWER_GATE_STATUS_0_SRAM_RET_STS_WOFFSET                   0x0
#define PMC_IMPL_PART_DBBRAM_POWER_GATE_STATUS_0_SRAM_RET_STS_DEFAULT                   MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_DBBRAM_POWER_GATE_STATUS_0_SRAM_RET_STS_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_DBBRAM_POWER_GATE_STATUS_0_SRAM_RET_STS_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_DBBRAM_POWER_GATE_STATUS_0_SRAM_RET_STS_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_DBBRAM_POWER_GATE_STATUS_0_SRAM_RET_STS_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_DBBRAM_POWER_GATE_STATUS_0_SRAM_RET_STS_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_DBBRAM_POWER_GATE_STATUS_0_SRAM_RET_STS_INIT_ENUM                 OFF
#define PMC_IMPL_PART_DBBRAM_POWER_GATE_STATUS_0_SRAM_RET_STS_OFF                       MK_ENUM_CONST(0)
#define PMC_IMPL_PART_DBBRAM_POWER_GATE_STATUS_0_SRAM_RET_STS_ON                        MK_ENUM_CONST(1)

#define PMC_IMPL_PART_DBBRAM_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SHIFT                  MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_DBBRAM_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_FIELD                  MK_FIELD_CONST(0x1, PMC_IMPL_PART_DBBRAM_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SHIFT)
#define PMC_IMPL_PART_DBBRAM_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_RANGE                  0:0
#define PMC_IMPL_PART_DBBRAM_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_MSB                    MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_DBBRAM_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_LSB                    MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_DBBRAM_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_WOFFSET                        0x0
#define PMC_IMPL_PART_DBBRAM_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_DEFAULT                        MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_DBBRAM_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_DBBRAM_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_DBBRAM_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_DBBRAM_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_DBBRAM_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_DBBRAM_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_INIT_ENUM                      OFF
#define PMC_IMPL_PART_DBBRAM_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_OFF                    MK_ENUM_CONST(0)
#define PMC_IMPL_PART_DBBRAM_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_ON                     MK_ENUM_CONST(1)


// Register PMC_IMPL_PART_DBBRAM_CLAMP_CONTROL_0
#define PMC_IMPL_PART_DBBRAM_CLAMP_CONTROL_0                    MK_ADDR_CONST(0x5d0)
#define PMC_IMPL_PART_DBBRAM_CLAMP_CONTROL_0_SECURE                     0x0
#define PMC_IMPL_PART_DBBRAM_CLAMP_CONTROL_0_DUAL                       0x0
#define PMC_IMPL_PART_DBBRAM_CLAMP_CONTROL_0_SCR                        PG_DBBRAM_SCR_0
#define PMC_IMPL_PART_DBBRAM_CLAMP_CONTROL_0_SCRREG                     PMC_IMPL_SCR_PG_DBBRAM_SCR_0
#define PMC_IMPL_PART_DBBRAM_CLAMP_CONTROL_0_WORD_COUNT                         0x1
#define PMC_IMPL_PART_DBBRAM_CLAMP_CONTROL_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_DBBRAM_CLAMP_CONTROL_0_RESET_MASK                         MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_DBBRAM_CLAMP_CONTROL_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_DBBRAM_CLAMP_CONTROL_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_DBBRAM_CLAMP_CONTROL_0_READ_MASK                  MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_DBBRAM_CLAMP_CONTROL_0_WRITE_MASK                         MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_DBBRAM_CLAMP_CONTROL_0_CLAMP_SHIFT                        MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_DBBRAM_CLAMP_CONTROL_0_CLAMP_FIELD                        MK_FIELD_CONST(0x1, PMC_IMPL_PART_DBBRAM_CLAMP_CONTROL_0_CLAMP_SHIFT)
#define PMC_IMPL_PART_DBBRAM_CLAMP_CONTROL_0_CLAMP_RANGE                        0:0
#define PMC_IMPL_PART_DBBRAM_CLAMP_CONTROL_0_CLAMP_MSB                  MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_DBBRAM_CLAMP_CONTROL_0_CLAMP_LSB                  MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_DBBRAM_CLAMP_CONTROL_0_CLAMP_WOFFSET                      0x0
#define PMC_IMPL_PART_DBBRAM_CLAMP_CONTROL_0_CLAMP_DEFAULT                      MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_DBBRAM_CLAMP_CONTROL_0_CLAMP_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_DBBRAM_CLAMP_CONTROL_0_CLAMP_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_DBBRAM_CLAMP_CONTROL_0_CLAMP_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_DBBRAM_CLAMP_CONTROL_0_CLAMP_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_DBBRAM_CLAMP_CONTROL_0_CLAMP_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_DBBRAM_CLAMP_CONTROL_0_CLAMP_INIT_ENUM                    OFF
#define PMC_IMPL_PART_DBBRAM_CLAMP_CONTROL_0_CLAMP_OFF                  MK_ENUM_CONST(0)
#define PMC_IMPL_PART_DBBRAM_CLAMP_CONTROL_0_CLAMP_ON                   MK_ENUM_CONST(1)


// Register PMC_IMPL_PART_AUD_PWRDWN_REQ_CONTROL_0
#define PMC_IMPL_PART_AUD_PWRDWN_REQ_CONTROL_0                  MK_ADDR_CONST(0x5d4)
#define PMC_IMPL_PART_AUD_PWRDWN_REQ_CONTROL_0_SECURE                   0x0
#define PMC_IMPL_PART_AUD_PWRDWN_REQ_CONTROL_0_DUAL                     0x0
#define PMC_IMPL_PART_AUD_PWRDWN_REQ_CONTROL_0_SCR                      PG_AUD_SCR_0
#define PMC_IMPL_PART_AUD_PWRDWN_REQ_CONTROL_0_SCRREG                   PMC_IMPL_SCR_PG_AUD_SCR_0
#define PMC_IMPL_PART_AUD_PWRDWN_REQ_CONTROL_0_WORD_COUNT                       0x1
#define PMC_IMPL_PART_AUD_PWRDWN_REQ_CONTROL_0_RESET_VAL                        MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AUD_PWRDWN_REQ_CONTROL_0_RESET_MASK                       MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AUD_PWRDWN_REQ_CONTROL_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AUD_PWRDWN_REQ_CONTROL_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AUD_PWRDWN_REQ_CONTROL_0_READ_MASK                        MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AUD_PWRDWN_REQ_CONTROL_0_WRITE_MASK                       MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AUD_PWRDWN_REQ_CONTROL_0_REQ_SHIFT                        MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_AUD_PWRDWN_REQ_CONTROL_0_REQ_FIELD                        MK_FIELD_CONST(0x1, PMC_IMPL_PART_AUD_PWRDWN_REQ_CONTROL_0_REQ_SHIFT)
#define PMC_IMPL_PART_AUD_PWRDWN_REQ_CONTROL_0_REQ_RANGE                        0:0
#define PMC_IMPL_PART_AUD_PWRDWN_REQ_CONTROL_0_REQ_MSB                  MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_AUD_PWRDWN_REQ_CONTROL_0_REQ_LSB                  MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_AUD_PWRDWN_REQ_CONTROL_0_REQ_WOFFSET                      0x0
#define PMC_IMPL_PART_AUD_PWRDWN_REQ_CONTROL_0_REQ_DEFAULT                      MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AUD_PWRDWN_REQ_CONTROL_0_REQ_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AUD_PWRDWN_REQ_CONTROL_0_REQ_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AUD_PWRDWN_REQ_CONTROL_0_REQ_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AUD_PWRDWN_REQ_CONTROL_0_REQ_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AUD_PWRDWN_REQ_CONTROL_0_REQ_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AUD_PWRDWN_REQ_CONTROL_0_REQ_INIT_ENUM                    PWRDWN
#define PMC_IMPL_PART_AUD_PWRDWN_REQ_CONTROL_0_REQ_PWRDWN                       MK_ENUM_CONST(1)
#define PMC_IMPL_PART_AUD_PWRDWN_REQ_CONTROL_0_REQ_PWRUP                        MK_ENUM_CONST(0)


// Register PMC_IMPL_PART_AUD_PWRDWN_ACK_STATUS_0
#define PMC_IMPL_PART_AUD_PWRDWN_ACK_STATUS_0                   MK_ADDR_CONST(0x5d8)
#define PMC_IMPL_PART_AUD_PWRDWN_ACK_STATUS_0_SECURE                    0x0
#define PMC_IMPL_PART_AUD_PWRDWN_ACK_STATUS_0_DUAL                      0x0
#define PMC_IMPL_PART_AUD_PWRDWN_ACK_STATUS_0_SCR                       PG_AUD_SCR_0
#define PMC_IMPL_PART_AUD_PWRDWN_ACK_STATUS_0_SCRREG                    PMC_IMPL_SCR_PG_AUD_SCR_0
#define PMC_IMPL_PART_AUD_PWRDWN_ACK_STATUS_0_WORD_COUNT                        0x1
#define PMC_IMPL_PART_AUD_PWRDWN_ACK_STATUS_0_RESET_VAL                         MK_MASK_CONST(0x7)
#define PMC_IMPL_PART_AUD_PWRDWN_ACK_STATUS_0_RESET_MASK                        MK_MASK_CONST(0x7)
#define PMC_IMPL_PART_AUD_PWRDWN_ACK_STATUS_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AUD_PWRDWN_ACK_STATUS_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AUD_PWRDWN_ACK_STATUS_0_READ_MASK                         MK_MASK_CONST(0x7)
#define PMC_IMPL_PART_AUD_PWRDWN_ACK_STATUS_0_WRITE_MASK                        MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AUD_PWRDWN_ACK_STATUS_0_CBB_ACK_SHIFT                     MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_AUD_PWRDWN_ACK_STATUS_0_CBB_ACK_FIELD                     MK_FIELD_CONST(0x1, PMC_IMPL_PART_AUD_PWRDWN_ACK_STATUS_0_CBB_ACK_SHIFT)
#define PMC_IMPL_PART_AUD_PWRDWN_ACK_STATUS_0_CBB_ACK_RANGE                     0:0
#define PMC_IMPL_PART_AUD_PWRDWN_ACK_STATUS_0_CBB_ACK_MSB                       MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_AUD_PWRDWN_ACK_STATUS_0_CBB_ACK_LSB                       MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_AUD_PWRDWN_ACK_STATUS_0_CBB_ACK_WOFFSET                   0x0
#define PMC_IMPL_PART_AUD_PWRDWN_ACK_STATUS_0_CBB_ACK_DEFAULT                   MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AUD_PWRDWN_ACK_STATUS_0_CBB_ACK_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AUD_PWRDWN_ACK_STATUS_0_CBB_ACK_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AUD_PWRDWN_ACK_STATUS_0_CBB_ACK_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AUD_PWRDWN_ACK_STATUS_0_CBB_ACK_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AUD_PWRDWN_ACK_STATUS_0_CBB_ACK_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AUD_PWRDWN_ACK_STATUS_0_CBB_ACK_INIT_ENUM                 PWRDWN
#define PMC_IMPL_PART_AUD_PWRDWN_ACK_STATUS_0_CBB_ACK_PWRDWN                    MK_ENUM_CONST(1)
#define PMC_IMPL_PART_AUD_PWRDWN_ACK_STATUS_0_CBB_ACK_PWRUP                     MK_ENUM_CONST(0)

#define PMC_IMPL_PART_AUD_PWRDWN_ACK_STATUS_0_DBB_ACK_SHIFT                     MK_SHIFT_CONST(1)
#define PMC_IMPL_PART_AUD_PWRDWN_ACK_STATUS_0_DBB_ACK_FIELD                     MK_FIELD_CONST(0x1, PMC_IMPL_PART_AUD_PWRDWN_ACK_STATUS_0_DBB_ACK_SHIFT)
#define PMC_IMPL_PART_AUD_PWRDWN_ACK_STATUS_0_DBB_ACK_RANGE                     1:1
#define PMC_IMPL_PART_AUD_PWRDWN_ACK_STATUS_0_DBB_ACK_MSB                       MK_SHIFT_CONST(1)
#define PMC_IMPL_PART_AUD_PWRDWN_ACK_STATUS_0_DBB_ACK_LSB                       MK_SHIFT_CONST(1)
#define PMC_IMPL_PART_AUD_PWRDWN_ACK_STATUS_0_DBB_ACK_WOFFSET                   0x0
#define PMC_IMPL_PART_AUD_PWRDWN_ACK_STATUS_0_DBB_ACK_DEFAULT                   MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AUD_PWRDWN_ACK_STATUS_0_DBB_ACK_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AUD_PWRDWN_ACK_STATUS_0_DBB_ACK_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AUD_PWRDWN_ACK_STATUS_0_DBB_ACK_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AUD_PWRDWN_ACK_STATUS_0_DBB_ACK_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AUD_PWRDWN_ACK_STATUS_0_DBB_ACK_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AUD_PWRDWN_ACK_STATUS_0_DBB_ACK_INIT_ENUM                 PWRDWN
#define PMC_IMPL_PART_AUD_PWRDWN_ACK_STATUS_0_DBB_ACK_PWRDWN                    MK_ENUM_CONST(1)
#define PMC_IMPL_PART_AUD_PWRDWN_ACK_STATUS_0_DBB_ACK_PWRUP                     MK_ENUM_CONST(0)

#define PMC_IMPL_PART_AUD_PWRDWN_ACK_STATUS_0_H1X_ACK_SHIFT                     MK_SHIFT_CONST(2)
#define PMC_IMPL_PART_AUD_PWRDWN_ACK_STATUS_0_H1X_ACK_FIELD                     MK_FIELD_CONST(0x1, PMC_IMPL_PART_AUD_PWRDWN_ACK_STATUS_0_H1X_ACK_SHIFT)
#define PMC_IMPL_PART_AUD_PWRDWN_ACK_STATUS_0_H1X_ACK_RANGE                     2:2
#define PMC_IMPL_PART_AUD_PWRDWN_ACK_STATUS_0_H1X_ACK_MSB                       MK_SHIFT_CONST(2)
#define PMC_IMPL_PART_AUD_PWRDWN_ACK_STATUS_0_H1X_ACK_LSB                       MK_SHIFT_CONST(2)
#define PMC_IMPL_PART_AUD_PWRDWN_ACK_STATUS_0_H1X_ACK_WOFFSET                   0x0
#define PMC_IMPL_PART_AUD_PWRDWN_ACK_STATUS_0_H1X_ACK_DEFAULT                   MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AUD_PWRDWN_ACK_STATUS_0_H1X_ACK_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AUD_PWRDWN_ACK_STATUS_0_H1X_ACK_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AUD_PWRDWN_ACK_STATUS_0_H1X_ACK_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AUD_PWRDWN_ACK_STATUS_0_H1X_ACK_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AUD_PWRDWN_ACK_STATUS_0_H1X_ACK_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AUD_PWRDWN_ACK_STATUS_0_H1X_ACK_INIT_ENUM                 PWRDWN
#define PMC_IMPL_PART_AUD_PWRDWN_ACK_STATUS_0_H1X_ACK_PWRDWN                    MK_ENUM_CONST(1)
#define PMC_IMPL_PART_AUD_PWRDWN_ACK_STATUS_0_H1X_ACK_PWRUP                     MK_ENUM_CONST(0)


// Register PMC_IMPL_PART_DISP_PWRDWN_REQ_CONTROL_0
#define PMC_IMPL_PART_DISP_PWRDWN_REQ_CONTROL_0                 MK_ADDR_CONST(0x5dc)
#define PMC_IMPL_PART_DISP_PWRDWN_REQ_CONTROL_0_SECURE                  0x0
#define PMC_IMPL_PART_DISP_PWRDWN_REQ_CONTROL_0_DUAL                    0x0
#define PMC_IMPL_PART_DISP_PWRDWN_REQ_CONTROL_0_SCR                     PG_DISP_SCR_0
#define PMC_IMPL_PART_DISP_PWRDWN_REQ_CONTROL_0_SCRREG                  PMC_IMPL_SCR_PG_DISP_SCR_0
#define PMC_IMPL_PART_DISP_PWRDWN_REQ_CONTROL_0_WORD_COUNT                      0x1
#define PMC_IMPL_PART_DISP_PWRDWN_REQ_CONTROL_0_RESET_VAL                       MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_DISP_PWRDWN_REQ_CONTROL_0_RESET_MASK                      MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_DISP_PWRDWN_REQ_CONTROL_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_DISP_PWRDWN_REQ_CONTROL_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_DISP_PWRDWN_REQ_CONTROL_0_READ_MASK                       MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_DISP_PWRDWN_REQ_CONTROL_0_WRITE_MASK                      MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_DISP_PWRDWN_REQ_CONTROL_0_REQ_SHIFT                       MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_DISP_PWRDWN_REQ_CONTROL_0_REQ_FIELD                       MK_FIELD_CONST(0x1, PMC_IMPL_PART_DISP_PWRDWN_REQ_CONTROL_0_REQ_SHIFT)
#define PMC_IMPL_PART_DISP_PWRDWN_REQ_CONTROL_0_REQ_RANGE                       0:0
#define PMC_IMPL_PART_DISP_PWRDWN_REQ_CONTROL_0_REQ_MSB                 MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_DISP_PWRDWN_REQ_CONTROL_0_REQ_LSB                 MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_DISP_PWRDWN_REQ_CONTROL_0_REQ_WOFFSET                     0x0
#define PMC_IMPL_PART_DISP_PWRDWN_REQ_CONTROL_0_REQ_DEFAULT                     MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_DISP_PWRDWN_REQ_CONTROL_0_REQ_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_DISP_PWRDWN_REQ_CONTROL_0_REQ_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_DISP_PWRDWN_REQ_CONTROL_0_REQ_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_DISP_PWRDWN_REQ_CONTROL_0_REQ_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_DISP_PWRDWN_REQ_CONTROL_0_REQ_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_DISP_PWRDWN_REQ_CONTROL_0_REQ_INIT_ENUM                   PWRDWN
#define PMC_IMPL_PART_DISP_PWRDWN_REQ_CONTROL_0_REQ_PWRDWN                      MK_ENUM_CONST(1)
#define PMC_IMPL_PART_DISP_PWRDWN_REQ_CONTROL_0_REQ_PWRUP                       MK_ENUM_CONST(0)


// Register PMC_IMPL_PART_DISP_PWRDWN_ACK_STATUS_0
#define PMC_IMPL_PART_DISP_PWRDWN_ACK_STATUS_0                  MK_ADDR_CONST(0x5e0)
#define PMC_IMPL_PART_DISP_PWRDWN_ACK_STATUS_0_SECURE                   0x0
#define PMC_IMPL_PART_DISP_PWRDWN_ACK_STATUS_0_DUAL                     0x0
#define PMC_IMPL_PART_DISP_PWRDWN_ACK_STATUS_0_SCR                      PG_DISP_SCR_0
#define PMC_IMPL_PART_DISP_PWRDWN_ACK_STATUS_0_SCRREG                   PMC_IMPL_SCR_PG_DISP_SCR_0
#define PMC_IMPL_PART_DISP_PWRDWN_ACK_STATUS_0_WORD_COUNT                       0x1
#define PMC_IMPL_PART_DISP_PWRDWN_ACK_STATUS_0_RESET_VAL                        MK_MASK_CONST(0x7)
#define PMC_IMPL_PART_DISP_PWRDWN_ACK_STATUS_0_RESET_MASK                       MK_MASK_CONST(0x7)
#define PMC_IMPL_PART_DISP_PWRDWN_ACK_STATUS_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_DISP_PWRDWN_ACK_STATUS_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_DISP_PWRDWN_ACK_STATUS_0_READ_MASK                        MK_MASK_CONST(0x7)
#define PMC_IMPL_PART_DISP_PWRDWN_ACK_STATUS_0_WRITE_MASK                       MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_DISP_PWRDWN_ACK_STATUS_0_CBB_ACK_SHIFT                    MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_DISP_PWRDWN_ACK_STATUS_0_CBB_ACK_FIELD                    MK_FIELD_CONST(0x1, PMC_IMPL_PART_DISP_PWRDWN_ACK_STATUS_0_CBB_ACK_SHIFT)
#define PMC_IMPL_PART_DISP_PWRDWN_ACK_STATUS_0_CBB_ACK_RANGE                    0:0
#define PMC_IMPL_PART_DISP_PWRDWN_ACK_STATUS_0_CBB_ACK_MSB                      MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_DISP_PWRDWN_ACK_STATUS_0_CBB_ACK_LSB                      MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_DISP_PWRDWN_ACK_STATUS_0_CBB_ACK_WOFFSET                  0x0
#define PMC_IMPL_PART_DISP_PWRDWN_ACK_STATUS_0_CBB_ACK_DEFAULT                  MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_DISP_PWRDWN_ACK_STATUS_0_CBB_ACK_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_DISP_PWRDWN_ACK_STATUS_0_CBB_ACK_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_DISP_PWRDWN_ACK_STATUS_0_CBB_ACK_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_DISP_PWRDWN_ACK_STATUS_0_CBB_ACK_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_DISP_PWRDWN_ACK_STATUS_0_CBB_ACK_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_DISP_PWRDWN_ACK_STATUS_0_CBB_ACK_INIT_ENUM                        PWRDWN
#define PMC_IMPL_PART_DISP_PWRDWN_ACK_STATUS_0_CBB_ACK_PWRDWN                   MK_ENUM_CONST(1)
#define PMC_IMPL_PART_DISP_PWRDWN_ACK_STATUS_0_CBB_ACK_PWRUP                    MK_ENUM_CONST(0)

#define PMC_IMPL_PART_DISP_PWRDWN_ACK_STATUS_0_DBB_ACK_SHIFT                    MK_SHIFT_CONST(1)
#define PMC_IMPL_PART_DISP_PWRDWN_ACK_STATUS_0_DBB_ACK_FIELD                    MK_FIELD_CONST(0x1, PMC_IMPL_PART_DISP_PWRDWN_ACK_STATUS_0_DBB_ACK_SHIFT)
#define PMC_IMPL_PART_DISP_PWRDWN_ACK_STATUS_0_DBB_ACK_RANGE                    1:1
#define PMC_IMPL_PART_DISP_PWRDWN_ACK_STATUS_0_DBB_ACK_MSB                      MK_SHIFT_CONST(1)
#define PMC_IMPL_PART_DISP_PWRDWN_ACK_STATUS_0_DBB_ACK_LSB                      MK_SHIFT_CONST(1)
#define PMC_IMPL_PART_DISP_PWRDWN_ACK_STATUS_0_DBB_ACK_WOFFSET                  0x0
#define PMC_IMPL_PART_DISP_PWRDWN_ACK_STATUS_0_DBB_ACK_DEFAULT                  MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_DISP_PWRDWN_ACK_STATUS_0_DBB_ACK_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_DISP_PWRDWN_ACK_STATUS_0_DBB_ACK_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_DISP_PWRDWN_ACK_STATUS_0_DBB_ACK_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_DISP_PWRDWN_ACK_STATUS_0_DBB_ACK_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_DISP_PWRDWN_ACK_STATUS_0_DBB_ACK_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_DISP_PWRDWN_ACK_STATUS_0_DBB_ACK_INIT_ENUM                        PWRDWN
#define PMC_IMPL_PART_DISP_PWRDWN_ACK_STATUS_0_DBB_ACK_PWRDWN                   MK_ENUM_CONST(1)
#define PMC_IMPL_PART_DISP_PWRDWN_ACK_STATUS_0_DBB_ACK_PWRUP                    MK_ENUM_CONST(0)

#define PMC_IMPL_PART_DISP_PWRDWN_ACK_STATUS_0_H1X_ACK_SHIFT                    MK_SHIFT_CONST(2)
#define PMC_IMPL_PART_DISP_PWRDWN_ACK_STATUS_0_H1X_ACK_FIELD                    MK_FIELD_CONST(0x1, PMC_IMPL_PART_DISP_PWRDWN_ACK_STATUS_0_H1X_ACK_SHIFT)
#define PMC_IMPL_PART_DISP_PWRDWN_ACK_STATUS_0_H1X_ACK_RANGE                    2:2
#define PMC_IMPL_PART_DISP_PWRDWN_ACK_STATUS_0_H1X_ACK_MSB                      MK_SHIFT_CONST(2)
#define PMC_IMPL_PART_DISP_PWRDWN_ACK_STATUS_0_H1X_ACK_LSB                      MK_SHIFT_CONST(2)
#define PMC_IMPL_PART_DISP_PWRDWN_ACK_STATUS_0_H1X_ACK_WOFFSET                  0x0
#define PMC_IMPL_PART_DISP_PWRDWN_ACK_STATUS_0_H1X_ACK_DEFAULT                  MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_DISP_PWRDWN_ACK_STATUS_0_H1X_ACK_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_DISP_PWRDWN_ACK_STATUS_0_H1X_ACK_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_DISP_PWRDWN_ACK_STATUS_0_H1X_ACK_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_DISP_PWRDWN_ACK_STATUS_0_H1X_ACK_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_DISP_PWRDWN_ACK_STATUS_0_H1X_ACK_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_DISP_PWRDWN_ACK_STATUS_0_H1X_ACK_INIT_ENUM                        PWRDWN
#define PMC_IMPL_PART_DISP_PWRDWN_ACK_STATUS_0_H1X_ACK_PWRDWN                   MK_ENUM_CONST(1)
#define PMC_IMPL_PART_DISP_PWRDWN_ACK_STATUS_0_H1X_ACK_PWRUP                    MK_ENUM_CONST(0)


// Register PMC_IMPL_PART_ISP_PWRDWN_REQ_CONTROL_0
#define PMC_IMPL_PART_ISP_PWRDWN_REQ_CONTROL_0                  MK_ADDR_CONST(0x5e4)
#define PMC_IMPL_PART_ISP_PWRDWN_REQ_CONTROL_0_SECURE                   0x0
#define PMC_IMPL_PART_ISP_PWRDWN_REQ_CONTROL_0_DUAL                     0x0
#define PMC_IMPL_PART_ISP_PWRDWN_REQ_CONTROL_0_SCR                      PG_ISP_SCR_0
#define PMC_IMPL_PART_ISP_PWRDWN_REQ_CONTROL_0_SCRREG                   PMC_IMPL_SCR_PG_ISP_SCR_0
#define PMC_IMPL_PART_ISP_PWRDWN_REQ_CONTROL_0_WORD_COUNT                       0x1
#define PMC_IMPL_PART_ISP_PWRDWN_REQ_CONTROL_0_RESET_VAL                        MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_ISP_PWRDWN_REQ_CONTROL_0_RESET_MASK                       MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_ISP_PWRDWN_REQ_CONTROL_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_ISP_PWRDWN_REQ_CONTROL_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_ISP_PWRDWN_REQ_CONTROL_0_READ_MASK                        MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_ISP_PWRDWN_REQ_CONTROL_0_WRITE_MASK                       MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_ISP_PWRDWN_REQ_CONTROL_0_REQ_SHIFT                        MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_ISP_PWRDWN_REQ_CONTROL_0_REQ_FIELD                        MK_FIELD_CONST(0x1, PMC_IMPL_PART_ISP_PWRDWN_REQ_CONTROL_0_REQ_SHIFT)
#define PMC_IMPL_PART_ISP_PWRDWN_REQ_CONTROL_0_REQ_RANGE                        0:0
#define PMC_IMPL_PART_ISP_PWRDWN_REQ_CONTROL_0_REQ_MSB                  MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_ISP_PWRDWN_REQ_CONTROL_0_REQ_LSB                  MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_ISP_PWRDWN_REQ_CONTROL_0_REQ_WOFFSET                      0x0
#define PMC_IMPL_PART_ISP_PWRDWN_REQ_CONTROL_0_REQ_DEFAULT                      MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_ISP_PWRDWN_REQ_CONTROL_0_REQ_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_ISP_PWRDWN_REQ_CONTROL_0_REQ_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_ISP_PWRDWN_REQ_CONTROL_0_REQ_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_ISP_PWRDWN_REQ_CONTROL_0_REQ_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_ISP_PWRDWN_REQ_CONTROL_0_REQ_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_ISP_PWRDWN_REQ_CONTROL_0_REQ_INIT_ENUM                    PWRDWN
#define PMC_IMPL_PART_ISP_PWRDWN_REQ_CONTROL_0_REQ_PWRDWN                       MK_ENUM_CONST(1)
#define PMC_IMPL_PART_ISP_PWRDWN_REQ_CONTROL_0_REQ_PWRUP                        MK_ENUM_CONST(0)


// Register PMC_IMPL_PART_ISP_PWRDWN_ACK_STATUS_0
#define PMC_IMPL_PART_ISP_PWRDWN_ACK_STATUS_0                   MK_ADDR_CONST(0x5e8)
#define PMC_IMPL_PART_ISP_PWRDWN_ACK_STATUS_0_SECURE                    0x0
#define PMC_IMPL_PART_ISP_PWRDWN_ACK_STATUS_0_DUAL                      0x0
#define PMC_IMPL_PART_ISP_PWRDWN_ACK_STATUS_0_SCR                       PG_ISP_SCR_0
#define PMC_IMPL_PART_ISP_PWRDWN_ACK_STATUS_0_SCRREG                    PMC_IMPL_SCR_PG_ISP_SCR_0
#define PMC_IMPL_PART_ISP_PWRDWN_ACK_STATUS_0_WORD_COUNT                        0x1
#define PMC_IMPL_PART_ISP_PWRDWN_ACK_STATUS_0_RESET_VAL                         MK_MASK_CONST(0x7)
#define PMC_IMPL_PART_ISP_PWRDWN_ACK_STATUS_0_RESET_MASK                        MK_MASK_CONST(0x7)
#define PMC_IMPL_PART_ISP_PWRDWN_ACK_STATUS_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_ISP_PWRDWN_ACK_STATUS_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_ISP_PWRDWN_ACK_STATUS_0_READ_MASK                         MK_MASK_CONST(0x7)
#define PMC_IMPL_PART_ISP_PWRDWN_ACK_STATUS_0_WRITE_MASK                        MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_ISP_PWRDWN_ACK_STATUS_0_CBB_ACK_SHIFT                     MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_ISP_PWRDWN_ACK_STATUS_0_CBB_ACK_FIELD                     MK_FIELD_CONST(0x1, PMC_IMPL_PART_ISP_PWRDWN_ACK_STATUS_0_CBB_ACK_SHIFT)
#define PMC_IMPL_PART_ISP_PWRDWN_ACK_STATUS_0_CBB_ACK_RANGE                     0:0
#define PMC_IMPL_PART_ISP_PWRDWN_ACK_STATUS_0_CBB_ACK_MSB                       MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_ISP_PWRDWN_ACK_STATUS_0_CBB_ACK_LSB                       MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_ISP_PWRDWN_ACK_STATUS_0_CBB_ACK_WOFFSET                   0x0
#define PMC_IMPL_PART_ISP_PWRDWN_ACK_STATUS_0_CBB_ACK_DEFAULT                   MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_ISP_PWRDWN_ACK_STATUS_0_CBB_ACK_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_ISP_PWRDWN_ACK_STATUS_0_CBB_ACK_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_ISP_PWRDWN_ACK_STATUS_0_CBB_ACK_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_ISP_PWRDWN_ACK_STATUS_0_CBB_ACK_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_ISP_PWRDWN_ACK_STATUS_0_CBB_ACK_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_ISP_PWRDWN_ACK_STATUS_0_CBB_ACK_INIT_ENUM                 PWRDWN
#define PMC_IMPL_PART_ISP_PWRDWN_ACK_STATUS_0_CBB_ACK_PWRDWN                    MK_ENUM_CONST(1)
#define PMC_IMPL_PART_ISP_PWRDWN_ACK_STATUS_0_CBB_ACK_PWRUP                     MK_ENUM_CONST(0)

#define PMC_IMPL_PART_ISP_PWRDWN_ACK_STATUS_0_DBB_ACK_SHIFT                     MK_SHIFT_CONST(1)
#define PMC_IMPL_PART_ISP_PWRDWN_ACK_STATUS_0_DBB_ACK_FIELD                     MK_FIELD_CONST(0x1, PMC_IMPL_PART_ISP_PWRDWN_ACK_STATUS_0_DBB_ACK_SHIFT)
#define PMC_IMPL_PART_ISP_PWRDWN_ACK_STATUS_0_DBB_ACK_RANGE                     1:1
#define PMC_IMPL_PART_ISP_PWRDWN_ACK_STATUS_0_DBB_ACK_MSB                       MK_SHIFT_CONST(1)
#define PMC_IMPL_PART_ISP_PWRDWN_ACK_STATUS_0_DBB_ACK_LSB                       MK_SHIFT_CONST(1)
#define PMC_IMPL_PART_ISP_PWRDWN_ACK_STATUS_0_DBB_ACK_WOFFSET                   0x0
#define PMC_IMPL_PART_ISP_PWRDWN_ACK_STATUS_0_DBB_ACK_DEFAULT                   MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_ISP_PWRDWN_ACK_STATUS_0_DBB_ACK_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_ISP_PWRDWN_ACK_STATUS_0_DBB_ACK_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_ISP_PWRDWN_ACK_STATUS_0_DBB_ACK_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_ISP_PWRDWN_ACK_STATUS_0_DBB_ACK_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_ISP_PWRDWN_ACK_STATUS_0_DBB_ACK_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_ISP_PWRDWN_ACK_STATUS_0_DBB_ACK_INIT_ENUM                 PWRDWN
#define PMC_IMPL_PART_ISP_PWRDWN_ACK_STATUS_0_DBB_ACK_PWRDWN                    MK_ENUM_CONST(1)
#define PMC_IMPL_PART_ISP_PWRDWN_ACK_STATUS_0_DBB_ACK_PWRUP                     MK_ENUM_CONST(0)

#define PMC_IMPL_PART_ISP_PWRDWN_ACK_STATUS_0_H1X_ACK_SHIFT                     MK_SHIFT_CONST(2)
#define PMC_IMPL_PART_ISP_PWRDWN_ACK_STATUS_0_H1X_ACK_FIELD                     MK_FIELD_CONST(0x1, PMC_IMPL_PART_ISP_PWRDWN_ACK_STATUS_0_H1X_ACK_SHIFT)
#define PMC_IMPL_PART_ISP_PWRDWN_ACK_STATUS_0_H1X_ACK_RANGE                     2:2
#define PMC_IMPL_PART_ISP_PWRDWN_ACK_STATUS_0_H1X_ACK_MSB                       MK_SHIFT_CONST(2)
#define PMC_IMPL_PART_ISP_PWRDWN_ACK_STATUS_0_H1X_ACK_LSB                       MK_SHIFT_CONST(2)
#define PMC_IMPL_PART_ISP_PWRDWN_ACK_STATUS_0_H1X_ACK_WOFFSET                   0x0
#define PMC_IMPL_PART_ISP_PWRDWN_ACK_STATUS_0_H1X_ACK_DEFAULT                   MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_ISP_PWRDWN_ACK_STATUS_0_H1X_ACK_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_ISP_PWRDWN_ACK_STATUS_0_H1X_ACK_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_ISP_PWRDWN_ACK_STATUS_0_H1X_ACK_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_ISP_PWRDWN_ACK_STATUS_0_H1X_ACK_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_ISP_PWRDWN_ACK_STATUS_0_H1X_ACK_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_ISP_PWRDWN_ACK_STATUS_0_H1X_ACK_INIT_ENUM                 PWRDWN
#define PMC_IMPL_PART_ISP_PWRDWN_ACK_STATUS_0_H1X_ACK_PWRDWN                    MK_ENUM_CONST(1)
#define PMC_IMPL_PART_ISP_PWRDWN_ACK_STATUS_0_H1X_ACK_PWRUP                     MK_ENUM_CONST(0)


// Register PMC_IMPL_PART_NVDEC_PWRDWN_REQ_CONTROL_0
#define PMC_IMPL_PART_NVDEC_PWRDWN_REQ_CONTROL_0                        MK_ADDR_CONST(0x5ec)
#define PMC_IMPL_PART_NVDEC_PWRDWN_REQ_CONTROL_0_SECURE                         0x0
#define PMC_IMPL_PART_NVDEC_PWRDWN_REQ_CONTROL_0_DUAL                   0x0
#define PMC_IMPL_PART_NVDEC_PWRDWN_REQ_CONTROL_0_SCR                    PG_NVDEC_SCR_0
#define PMC_IMPL_PART_NVDEC_PWRDWN_REQ_CONTROL_0_SCRREG                         PMC_IMPL_SCR_PG_NVDEC_SCR_0
#define PMC_IMPL_PART_NVDEC_PWRDWN_REQ_CONTROL_0_WORD_COUNT                     0x1
#define PMC_IMPL_PART_NVDEC_PWRDWN_REQ_CONTROL_0_RESET_VAL                      MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_NVDEC_PWRDWN_REQ_CONTROL_0_RESET_MASK                     MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_NVDEC_PWRDWN_REQ_CONTROL_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_NVDEC_PWRDWN_REQ_CONTROL_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_NVDEC_PWRDWN_REQ_CONTROL_0_READ_MASK                      MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_NVDEC_PWRDWN_REQ_CONTROL_0_WRITE_MASK                     MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_NVDEC_PWRDWN_REQ_CONTROL_0_REQ_SHIFT                      MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_NVDEC_PWRDWN_REQ_CONTROL_0_REQ_FIELD                      MK_FIELD_CONST(0x1, PMC_IMPL_PART_NVDEC_PWRDWN_REQ_CONTROL_0_REQ_SHIFT)
#define PMC_IMPL_PART_NVDEC_PWRDWN_REQ_CONTROL_0_REQ_RANGE                      0:0
#define PMC_IMPL_PART_NVDEC_PWRDWN_REQ_CONTROL_0_REQ_MSB                        MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_NVDEC_PWRDWN_REQ_CONTROL_0_REQ_LSB                        MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_NVDEC_PWRDWN_REQ_CONTROL_0_REQ_WOFFSET                    0x0
#define PMC_IMPL_PART_NVDEC_PWRDWN_REQ_CONTROL_0_REQ_DEFAULT                    MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_NVDEC_PWRDWN_REQ_CONTROL_0_REQ_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_NVDEC_PWRDWN_REQ_CONTROL_0_REQ_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_NVDEC_PWRDWN_REQ_CONTROL_0_REQ_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_NVDEC_PWRDWN_REQ_CONTROL_0_REQ_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_NVDEC_PWRDWN_REQ_CONTROL_0_REQ_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_NVDEC_PWRDWN_REQ_CONTROL_0_REQ_INIT_ENUM                  PWRDWN
#define PMC_IMPL_PART_NVDEC_PWRDWN_REQ_CONTROL_0_REQ_PWRDWN                     MK_ENUM_CONST(1)
#define PMC_IMPL_PART_NVDEC_PWRDWN_REQ_CONTROL_0_REQ_PWRUP                      MK_ENUM_CONST(0)


// Register PMC_IMPL_PART_NVDEC_PWRDWN_ACK_STATUS_0
#define PMC_IMPL_PART_NVDEC_PWRDWN_ACK_STATUS_0                 MK_ADDR_CONST(0x5f0)
#define PMC_IMPL_PART_NVDEC_PWRDWN_ACK_STATUS_0_SECURE                  0x0
#define PMC_IMPL_PART_NVDEC_PWRDWN_ACK_STATUS_0_DUAL                    0x0
#define PMC_IMPL_PART_NVDEC_PWRDWN_ACK_STATUS_0_SCR                     PG_NVDEC_SCR_0
#define PMC_IMPL_PART_NVDEC_PWRDWN_ACK_STATUS_0_SCRREG                  PMC_IMPL_SCR_PG_NVDEC_SCR_0
#define PMC_IMPL_PART_NVDEC_PWRDWN_ACK_STATUS_0_WORD_COUNT                      0x1
#define PMC_IMPL_PART_NVDEC_PWRDWN_ACK_STATUS_0_RESET_VAL                       MK_MASK_CONST(0x7)
#define PMC_IMPL_PART_NVDEC_PWRDWN_ACK_STATUS_0_RESET_MASK                      MK_MASK_CONST(0x7)
#define PMC_IMPL_PART_NVDEC_PWRDWN_ACK_STATUS_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_NVDEC_PWRDWN_ACK_STATUS_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_NVDEC_PWRDWN_ACK_STATUS_0_READ_MASK                       MK_MASK_CONST(0x7)
#define PMC_IMPL_PART_NVDEC_PWRDWN_ACK_STATUS_0_WRITE_MASK                      MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_NVDEC_PWRDWN_ACK_STATUS_0_CBB_ACK_SHIFT                   MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_NVDEC_PWRDWN_ACK_STATUS_0_CBB_ACK_FIELD                   MK_FIELD_CONST(0x1, PMC_IMPL_PART_NVDEC_PWRDWN_ACK_STATUS_0_CBB_ACK_SHIFT)
#define PMC_IMPL_PART_NVDEC_PWRDWN_ACK_STATUS_0_CBB_ACK_RANGE                   0:0
#define PMC_IMPL_PART_NVDEC_PWRDWN_ACK_STATUS_0_CBB_ACK_MSB                     MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_NVDEC_PWRDWN_ACK_STATUS_0_CBB_ACK_LSB                     MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_NVDEC_PWRDWN_ACK_STATUS_0_CBB_ACK_WOFFSET                 0x0
#define PMC_IMPL_PART_NVDEC_PWRDWN_ACK_STATUS_0_CBB_ACK_DEFAULT                 MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_NVDEC_PWRDWN_ACK_STATUS_0_CBB_ACK_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_NVDEC_PWRDWN_ACK_STATUS_0_CBB_ACK_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_NVDEC_PWRDWN_ACK_STATUS_0_CBB_ACK_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_NVDEC_PWRDWN_ACK_STATUS_0_CBB_ACK_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_NVDEC_PWRDWN_ACK_STATUS_0_CBB_ACK_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_NVDEC_PWRDWN_ACK_STATUS_0_CBB_ACK_INIT_ENUM                       PWRDWN
#define PMC_IMPL_PART_NVDEC_PWRDWN_ACK_STATUS_0_CBB_ACK_PWRDWN                  MK_ENUM_CONST(1)
#define PMC_IMPL_PART_NVDEC_PWRDWN_ACK_STATUS_0_CBB_ACK_PWRUP                   MK_ENUM_CONST(0)

#define PMC_IMPL_PART_NVDEC_PWRDWN_ACK_STATUS_0_DBB_ACK_SHIFT                   MK_SHIFT_CONST(1)
#define PMC_IMPL_PART_NVDEC_PWRDWN_ACK_STATUS_0_DBB_ACK_FIELD                   MK_FIELD_CONST(0x1, PMC_IMPL_PART_NVDEC_PWRDWN_ACK_STATUS_0_DBB_ACK_SHIFT)
#define PMC_IMPL_PART_NVDEC_PWRDWN_ACK_STATUS_0_DBB_ACK_RANGE                   1:1
#define PMC_IMPL_PART_NVDEC_PWRDWN_ACK_STATUS_0_DBB_ACK_MSB                     MK_SHIFT_CONST(1)
#define PMC_IMPL_PART_NVDEC_PWRDWN_ACK_STATUS_0_DBB_ACK_LSB                     MK_SHIFT_CONST(1)
#define PMC_IMPL_PART_NVDEC_PWRDWN_ACK_STATUS_0_DBB_ACK_WOFFSET                 0x0
#define PMC_IMPL_PART_NVDEC_PWRDWN_ACK_STATUS_0_DBB_ACK_DEFAULT                 MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_NVDEC_PWRDWN_ACK_STATUS_0_DBB_ACK_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_NVDEC_PWRDWN_ACK_STATUS_0_DBB_ACK_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_NVDEC_PWRDWN_ACK_STATUS_0_DBB_ACK_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_NVDEC_PWRDWN_ACK_STATUS_0_DBB_ACK_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_NVDEC_PWRDWN_ACK_STATUS_0_DBB_ACK_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_NVDEC_PWRDWN_ACK_STATUS_0_DBB_ACK_INIT_ENUM                       PWRDWN
#define PMC_IMPL_PART_NVDEC_PWRDWN_ACK_STATUS_0_DBB_ACK_PWRDWN                  MK_ENUM_CONST(1)
#define PMC_IMPL_PART_NVDEC_PWRDWN_ACK_STATUS_0_DBB_ACK_PWRUP                   MK_ENUM_CONST(0)

#define PMC_IMPL_PART_NVDEC_PWRDWN_ACK_STATUS_0_H1X_ACK_SHIFT                   MK_SHIFT_CONST(2)
#define PMC_IMPL_PART_NVDEC_PWRDWN_ACK_STATUS_0_H1X_ACK_FIELD                   MK_FIELD_CONST(0x1, PMC_IMPL_PART_NVDEC_PWRDWN_ACK_STATUS_0_H1X_ACK_SHIFT)
#define PMC_IMPL_PART_NVDEC_PWRDWN_ACK_STATUS_0_H1X_ACK_RANGE                   2:2
#define PMC_IMPL_PART_NVDEC_PWRDWN_ACK_STATUS_0_H1X_ACK_MSB                     MK_SHIFT_CONST(2)
#define PMC_IMPL_PART_NVDEC_PWRDWN_ACK_STATUS_0_H1X_ACK_LSB                     MK_SHIFT_CONST(2)
#define PMC_IMPL_PART_NVDEC_PWRDWN_ACK_STATUS_0_H1X_ACK_WOFFSET                 0x0
#define PMC_IMPL_PART_NVDEC_PWRDWN_ACK_STATUS_0_H1X_ACK_DEFAULT                 MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_NVDEC_PWRDWN_ACK_STATUS_0_H1X_ACK_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_NVDEC_PWRDWN_ACK_STATUS_0_H1X_ACK_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_NVDEC_PWRDWN_ACK_STATUS_0_H1X_ACK_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_NVDEC_PWRDWN_ACK_STATUS_0_H1X_ACK_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_NVDEC_PWRDWN_ACK_STATUS_0_H1X_ACK_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_NVDEC_PWRDWN_ACK_STATUS_0_H1X_ACK_INIT_ENUM                       PWRDWN
#define PMC_IMPL_PART_NVDEC_PWRDWN_ACK_STATUS_0_H1X_ACK_PWRDWN                  MK_ENUM_CONST(1)
#define PMC_IMPL_PART_NVDEC_PWRDWN_ACK_STATUS_0_H1X_ACK_PWRUP                   MK_ENUM_CONST(0)


// Register PMC_IMPL_PART_NVJPGA_PWRDWN_REQ_CONTROL_0
#define PMC_IMPL_PART_NVJPGA_PWRDWN_REQ_CONTROL_0                       MK_ADDR_CONST(0x5f4)
#define PMC_IMPL_PART_NVJPGA_PWRDWN_REQ_CONTROL_0_SECURE                        0x0
#define PMC_IMPL_PART_NVJPGA_PWRDWN_REQ_CONTROL_0_DUAL                  0x0
#define PMC_IMPL_PART_NVJPGA_PWRDWN_REQ_CONTROL_0_SCR                   PG_NVJPGA_SCR_0
#define PMC_IMPL_PART_NVJPGA_PWRDWN_REQ_CONTROL_0_SCRREG                        PMC_IMPL_SCR_PG_NVJPGA_SCR_0
#define PMC_IMPL_PART_NVJPGA_PWRDWN_REQ_CONTROL_0_WORD_COUNT                    0x1
#define PMC_IMPL_PART_NVJPGA_PWRDWN_REQ_CONTROL_0_RESET_VAL                     MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_NVJPGA_PWRDWN_REQ_CONTROL_0_RESET_MASK                    MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_NVJPGA_PWRDWN_REQ_CONTROL_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_NVJPGA_PWRDWN_REQ_CONTROL_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_NVJPGA_PWRDWN_REQ_CONTROL_0_READ_MASK                     MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_NVJPGA_PWRDWN_REQ_CONTROL_0_WRITE_MASK                    MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_NVJPGA_PWRDWN_REQ_CONTROL_0_REQ_SHIFT                     MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_NVJPGA_PWRDWN_REQ_CONTROL_0_REQ_FIELD                     MK_FIELD_CONST(0x1, PMC_IMPL_PART_NVJPGA_PWRDWN_REQ_CONTROL_0_REQ_SHIFT)
#define PMC_IMPL_PART_NVJPGA_PWRDWN_REQ_CONTROL_0_REQ_RANGE                     0:0
#define PMC_IMPL_PART_NVJPGA_PWRDWN_REQ_CONTROL_0_REQ_MSB                       MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_NVJPGA_PWRDWN_REQ_CONTROL_0_REQ_LSB                       MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_NVJPGA_PWRDWN_REQ_CONTROL_0_REQ_WOFFSET                   0x0
#define PMC_IMPL_PART_NVJPGA_PWRDWN_REQ_CONTROL_0_REQ_DEFAULT                   MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_NVJPGA_PWRDWN_REQ_CONTROL_0_REQ_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_NVJPGA_PWRDWN_REQ_CONTROL_0_REQ_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_NVJPGA_PWRDWN_REQ_CONTROL_0_REQ_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_NVJPGA_PWRDWN_REQ_CONTROL_0_REQ_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_NVJPGA_PWRDWN_REQ_CONTROL_0_REQ_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_NVJPGA_PWRDWN_REQ_CONTROL_0_REQ_INIT_ENUM                 PWRDWN
#define PMC_IMPL_PART_NVJPGA_PWRDWN_REQ_CONTROL_0_REQ_PWRDWN                    MK_ENUM_CONST(1)
#define PMC_IMPL_PART_NVJPGA_PWRDWN_REQ_CONTROL_0_REQ_PWRUP                     MK_ENUM_CONST(0)


// Register PMC_IMPL_PART_NVJPGA_PWRDWN_ACK_STATUS_0
#define PMC_IMPL_PART_NVJPGA_PWRDWN_ACK_STATUS_0                        MK_ADDR_CONST(0x5f8)
#define PMC_IMPL_PART_NVJPGA_PWRDWN_ACK_STATUS_0_SECURE                         0x0
#define PMC_IMPL_PART_NVJPGA_PWRDWN_ACK_STATUS_0_DUAL                   0x0
#define PMC_IMPL_PART_NVJPGA_PWRDWN_ACK_STATUS_0_SCR                    PG_NVJPGA_SCR_0
#define PMC_IMPL_PART_NVJPGA_PWRDWN_ACK_STATUS_0_SCRREG                         PMC_IMPL_SCR_PG_NVJPGA_SCR_0
#define PMC_IMPL_PART_NVJPGA_PWRDWN_ACK_STATUS_0_WORD_COUNT                     0x1
#define PMC_IMPL_PART_NVJPGA_PWRDWN_ACK_STATUS_0_RESET_VAL                      MK_MASK_CONST(0x7)
#define PMC_IMPL_PART_NVJPGA_PWRDWN_ACK_STATUS_0_RESET_MASK                     MK_MASK_CONST(0x7)
#define PMC_IMPL_PART_NVJPGA_PWRDWN_ACK_STATUS_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_NVJPGA_PWRDWN_ACK_STATUS_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_NVJPGA_PWRDWN_ACK_STATUS_0_READ_MASK                      MK_MASK_CONST(0x7)
#define PMC_IMPL_PART_NVJPGA_PWRDWN_ACK_STATUS_0_WRITE_MASK                     MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_NVJPGA_PWRDWN_ACK_STATUS_0_CBB_ACK_SHIFT                  MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_NVJPGA_PWRDWN_ACK_STATUS_0_CBB_ACK_FIELD                  MK_FIELD_CONST(0x1, PMC_IMPL_PART_NVJPGA_PWRDWN_ACK_STATUS_0_CBB_ACK_SHIFT)
#define PMC_IMPL_PART_NVJPGA_PWRDWN_ACK_STATUS_0_CBB_ACK_RANGE                  0:0
#define PMC_IMPL_PART_NVJPGA_PWRDWN_ACK_STATUS_0_CBB_ACK_MSB                    MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_NVJPGA_PWRDWN_ACK_STATUS_0_CBB_ACK_LSB                    MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_NVJPGA_PWRDWN_ACK_STATUS_0_CBB_ACK_WOFFSET                        0x0
#define PMC_IMPL_PART_NVJPGA_PWRDWN_ACK_STATUS_0_CBB_ACK_DEFAULT                        MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_NVJPGA_PWRDWN_ACK_STATUS_0_CBB_ACK_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_NVJPGA_PWRDWN_ACK_STATUS_0_CBB_ACK_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_NVJPGA_PWRDWN_ACK_STATUS_0_CBB_ACK_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_NVJPGA_PWRDWN_ACK_STATUS_0_CBB_ACK_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_NVJPGA_PWRDWN_ACK_STATUS_0_CBB_ACK_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_NVJPGA_PWRDWN_ACK_STATUS_0_CBB_ACK_INIT_ENUM                      PWRDWN
#define PMC_IMPL_PART_NVJPGA_PWRDWN_ACK_STATUS_0_CBB_ACK_PWRDWN                 MK_ENUM_CONST(1)
#define PMC_IMPL_PART_NVJPGA_PWRDWN_ACK_STATUS_0_CBB_ACK_PWRUP                  MK_ENUM_CONST(0)

#define PMC_IMPL_PART_NVJPGA_PWRDWN_ACK_STATUS_0_DBB_ACK_SHIFT                  MK_SHIFT_CONST(1)
#define PMC_IMPL_PART_NVJPGA_PWRDWN_ACK_STATUS_0_DBB_ACK_FIELD                  MK_FIELD_CONST(0x1, PMC_IMPL_PART_NVJPGA_PWRDWN_ACK_STATUS_0_DBB_ACK_SHIFT)
#define PMC_IMPL_PART_NVJPGA_PWRDWN_ACK_STATUS_0_DBB_ACK_RANGE                  1:1
#define PMC_IMPL_PART_NVJPGA_PWRDWN_ACK_STATUS_0_DBB_ACK_MSB                    MK_SHIFT_CONST(1)
#define PMC_IMPL_PART_NVJPGA_PWRDWN_ACK_STATUS_0_DBB_ACK_LSB                    MK_SHIFT_CONST(1)
#define PMC_IMPL_PART_NVJPGA_PWRDWN_ACK_STATUS_0_DBB_ACK_WOFFSET                        0x0
#define PMC_IMPL_PART_NVJPGA_PWRDWN_ACK_STATUS_0_DBB_ACK_DEFAULT                        MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_NVJPGA_PWRDWN_ACK_STATUS_0_DBB_ACK_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_NVJPGA_PWRDWN_ACK_STATUS_0_DBB_ACK_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_NVJPGA_PWRDWN_ACK_STATUS_0_DBB_ACK_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_NVJPGA_PWRDWN_ACK_STATUS_0_DBB_ACK_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_NVJPGA_PWRDWN_ACK_STATUS_0_DBB_ACK_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_NVJPGA_PWRDWN_ACK_STATUS_0_DBB_ACK_INIT_ENUM                      PWRDWN
#define PMC_IMPL_PART_NVJPGA_PWRDWN_ACK_STATUS_0_DBB_ACK_PWRDWN                 MK_ENUM_CONST(1)
#define PMC_IMPL_PART_NVJPGA_PWRDWN_ACK_STATUS_0_DBB_ACK_PWRUP                  MK_ENUM_CONST(0)

#define PMC_IMPL_PART_NVJPGA_PWRDWN_ACK_STATUS_0_H1X_ACK_SHIFT                  MK_SHIFT_CONST(2)
#define PMC_IMPL_PART_NVJPGA_PWRDWN_ACK_STATUS_0_H1X_ACK_FIELD                  MK_FIELD_CONST(0x1, PMC_IMPL_PART_NVJPGA_PWRDWN_ACK_STATUS_0_H1X_ACK_SHIFT)
#define PMC_IMPL_PART_NVJPGA_PWRDWN_ACK_STATUS_0_H1X_ACK_RANGE                  2:2
#define PMC_IMPL_PART_NVJPGA_PWRDWN_ACK_STATUS_0_H1X_ACK_MSB                    MK_SHIFT_CONST(2)
#define PMC_IMPL_PART_NVJPGA_PWRDWN_ACK_STATUS_0_H1X_ACK_LSB                    MK_SHIFT_CONST(2)
#define PMC_IMPL_PART_NVJPGA_PWRDWN_ACK_STATUS_0_H1X_ACK_WOFFSET                        0x0
#define PMC_IMPL_PART_NVJPGA_PWRDWN_ACK_STATUS_0_H1X_ACK_DEFAULT                        MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_NVJPGA_PWRDWN_ACK_STATUS_0_H1X_ACK_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_NVJPGA_PWRDWN_ACK_STATUS_0_H1X_ACK_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_NVJPGA_PWRDWN_ACK_STATUS_0_H1X_ACK_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_NVJPGA_PWRDWN_ACK_STATUS_0_H1X_ACK_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_NVJPGA_PWRDWN_ACK_STATUS_0_H1X_ACK_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_NVJPGA_PWRDWN_ACK_STATUS_0_H1X_ACK_INIT_ENUM                      PWRDWN
#define PMC_IMPL_PART_NVJPGA_PWRDWN_ACK_STATUS_0_H1X_ACK_PWRDWN                 MK_ENUM_CONST(1)
#define PMC_IMPL_PART_NVJPGA_PWRDWN_ACK_STATUS_0_H1X_ACK_PWRUP                  MK_ENUM_CONST(0)


// Register PMC_IMPL_PART_NVJPGB_PWRDWN_REQ_CONTROL_0
#define PMC_IMPL_PART_NVJPGB_PWRDWN_REQ_CONTROL_0                       MK_ADDR_CONST(0x5fc)
#define PMC_IMPL_PART_NVJPGB_PWRDWN_REQ_CONTROL_0_SECURE                        0x0
#define PMC_IMPL_PART_NVJPGB_PWRDWN_REQ_CONTROL_0_DUAL                  0x0
#define PMC_IMPL_PART_NVJPGB_PWRDWN_REQ_CONTROL_0_SCR                   PG_NVJPGB_SCR_0
#define PMC_IMPL_PART_NVJPGB_PWRDWN_REQ_CONTROL_0_SCRREG                        PMC_IMPL_SCR_PG_NVJPGB_SCR_0
#define PMC_IMPL_PART_NVJPGB_PWRDWN_REQ_CONTROL_0_WORD_COUNT                    0x1
#define PMC_IMPL_PART_NVJPGB_PWRDWN_REQ_CONTROL_0_RESET_VAL                     MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_NVJPGB_PWRDWN_REQ_CONTROL_0_RESET_MASK                    MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_NVJPGB_PWRDWN_REQ_CONTROL_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_NVJPGB_PWRDWN_REQ_CONTROL_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_NVJPGB_PWRDWN_REQ_CONTROL_0_READ_MASK                     MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_NVJPGB_PWRDWN_REQ_CONTROL_0_WRITE_MASK                    MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_NVJPGB_PWRDWN_REQ_CONTROL_0_REQ_SHIFT                     MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_NVJPGB_PWRDWN_REQ_CONTROL_0_REQ_FIELD                     MK_FIELD_CONST(0x1, PMC_IMPL_PART_NVJPGB_PWRDWN_REQ_CONTROL_0_REQ_SHIFT)
#define PMC_IMPL_PART_NVJPGB_PWRDWN_REQ_CONTROL_0_REQ_RANGE                     0:0
#define PMC_IMPL_PART_NVJPGB_PWRDWN_REQ_CONTROL_0_REQ_MSB                       MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_NVJPGB_PWRDWN_REQ_CONTROL_0_REQ_LSB                       MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_NVJPGB_PWRDWN_REQ_CONTROL_0_REQ_WOFFSET                   0x0
#define PMC_IMPL_PART_NVJPGB_PWRDWN_REQ_CONTROL_0_REQ_DEFAULT                   MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_NVJPGB_PWRDWN_REQ_CONTROL_0_REQ_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_NVJPGB_PWRDWN_REQ_CONTROL_0_REQ_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_NVJPGB_PWRDWN_REQ_CONTROL_0_REQ_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_NVJPGB_PWRDWN_REQ_CONTROL_0_REQ_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_NVJPGB_PWRDWN_REQ_CONTROL_0_REQ_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_NVJPGB_PWRDWN_REQ_CONTROL_0_REQ_INIT_ENUM                 PWRDWN
#define PMC_IMPL_PART_NVJPGB_PWRDWN_REQ_CONTROL_0_REQ_PWRDWN                    MK_ENUM_CONST(1)
#define PMC_IMPL_PART_NVJPGB_PWRDWN_REQ_CONTROL_0_REQ_PWRUP                     MK_ENUM_CONST(0)


// Register PMC_IMPL_PART_NVJPGB_PWRDWN_ACK_STATUS_0
#define PMC_IMPL_PART_NVJPGB_PWRDWN_ACK_STATUS_0                        MK_ADDR_CONST(0x600)
#define PMC_IMPL_PART_NVJPGB_PWRDWN_ACK_STATUS_0_SECURE                         0x0
#define PMC_IMPL_PART_NVJPGB_PWRDWN_ACK_STATUS_0_DUAL                   0x0
#define PMC_IMPL_PART_NVJPGB_PWRDWN_ACK_STATUS_0_SCR                    PG_NVJPGB_SCR_0
#define PMC_IMPL_PART_NVJPGB_PWRDWN_ACK_STATUS_0_SCRREG                         PMC_IMPL_SCR_PG_NVJPGB_SCR_0
#define PMC_IMPL_PART_NVJPGB_PWRDWN_ACK_STATUS_0_WORD_COUNT                     0x1
#define PMC_IMPL_PART_NVJPGB_PWRDWN_ACK_STATUS_0_RESET_VAL                      MK_MASK_CONST(0x7)
#define PMC_IMPL_PART_NVJPGB_PWRDWN_ACK_STATUS_0_RESET_MASK                     MK_MASK_CONST(0x7)
#define PMC_IMPL_PART_NVJPGB_PWRDWN_ACK_STATUS_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_NVJPGB_PWRDWN_ACK_STATUS_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_NVJPGB_PWRDWN_ACK_STATUS_0_READ_MASK                      MK_MASK_CONST(0x7)
#define PMC_IMPL_PART_NVJPGB_PWRDWN_ACK_STATUS_0_WRITE_MASK                     MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_NVJPGB_PWRDWN_ACK_STATUS_0_CBB_ACK_SHIFT                  MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_NVJPGB_PWRDWN_ACK_STATUS_0_CBB_ACK_FIELD                  MK_FIELD_CONST(0x1, PMC_IMPL_PART_NVJPGB_PWRDWN_ACK_STATUS_0_CBB_ACK_SHIFT)
#define PMC_IMPL_PART_NVJPGB_PWRDWN_ACK_STATUS_0_CBB_ACK_RANGE                  0:0
#define PMC_IMPL_PART_NVJPGB_PWRDWN_ACK_STATUS_0_CBB_ACK_MSB                    MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_NVJPGB_PWRDWN_ACK_STATUS_0_CBB_ACK_LSB                    MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_NVJPGB_PWRDWN_ACK_STATUS_0_CBB_ACK_WOFFSET                        0x0
#define PMC_IMPL_PART_NVJPGB_PWRDWN_ACK_STATUS_0_CBB_ACK_DEFAULT                        MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_NVJPGB_PWRDWN_ACK_STATUS_0_CBB_ACK_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_NVJPGB_PWRDWN_ACK_STATUS_0_CBB_ACK_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_NVJPGB_PWRDWN_ACK_STATUS_0_CBB_ACK_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_NVJPGB_PWRDWN_ACK_STATUS_0_CBB_ACK_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_NVJPGB_PWRDWN_ACK_STATUS_0_CBB_ACK_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_NVJPGB_PWRDWN_ACK_STATUS_0_CBB_ACK_INIT_ENUM                      PWRDWN
#define PMC_IMPL_PART_NVJPGB_PWRDWN_ACK_STATUS_0_CBB_ACK_PWRDWN                 MK_ENUM_CONST(1)
#define PMC_IMPL_PART_NVJPGB_PWRDWN_ACK_STATUS_0_CBB_ACK_PWRUP                  MK_ENUM_CONST(0)

#define PMC_IMPL_PART_NVJPGB_PWRDWN_ACK_STATUS_0_DBB_ACK_SHIFT                  MK_SHIFT_CONST(1)
#define PMC_IMPL_PART_NVJPGB_PWRDWN_ACK_STATUS_0_DBB_ACK_FIELD                  MK_FIELD_CONST(0x1, PMC_IMPL_PART_NVJPGB_PWRDWN_ACK_STATUS_0_DBB_ACK_SHIFT)
#define PMC_IMPL_PART_NVJPGB_PWRDWN_ACK_STATUS_0_DBB_ACK_RANGE                  1:1
#define PMC_IMPL_PART_NVJPGB_PWRDWN_ACK_STATUS_0_DBB_ACK_MSB                    MK_SHIFT_CONST(1)
#define PMC_IMPL_PART_NVJPGB_PWRDWN_ACK_STATUS_0_DBB_ACK_LSB                    MK_SHIFT_CONST(1)
#define PMC_IMPL_PART_NVJPGB_PWRDWN_ACK_STATUS_0_DBB_ACK_WOFFSET                        0x0
#define PMC_IMPL_PART_NVJPGB_PWRDWN_ACK_STATUS_0_DBB_ACK_DEFAULT                        MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_NVJPGB_PWRDWN_ACK_STATUS_0_DBB_ACK_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_NVJPGB_PWRDWN_ACK_STATUS_0_DBB_ACK_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_NVJPGB_PWRDWN_ACK_STATUS_0_DBB_ACK_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_NVJPGB_PWRDWN_ACK_STATUS_0_DBB_ACK_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_NVJPGB_PWRDWN_ACK_STATUS_0_DBB_ACK_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_NVJPGB_PWRDWN_ACK_STATUS_0_DBB_ACK_INIT_ENUM                      PWRDWN
#define PMC_IMPL_PART_NVJPGB_PWRDWN_ACK_STATUS_0_DBB_ACK_PWRDWN                 MK_ENUM_CONST(1)
#define PMC_IMPL_PART_NVJPGB_PWRDWN_ACK_STATUS_0_DBB_ACK_PWRUP                  MK_ENUM_CONST(0)

#define PMC_IMPL_PART_NVJPGB_PWRDWN_ACK_STATUS_0_H1X_ACK_SHIFT                  MK_SHIFT_CONST(2)
#define PMC_IMPL_PART_NVJPGB_PWRDWN_ACK_STATUS_0_H1X_ACK_FIELD                  MK_FIELD_CONST(0x1, PMC_IMPL_PART_NVJPGB_PWRDWN_ACK_STATUS_0_H1X_ACK_SHIFT)
#define PMC_IMPL_PART_NVJPGB_PWRDWN_ACK_STATUS_0_H1X_ACK_RANGE                  2:2
#define PMC_IMPL_PART_NVJPGB_PWRDWN_ACK_STATUS_0_H1X_ACK_MSB                    MK_SHIFT_CONST(2)
#define PMC_IMPL_PART_NVJPGB_PWRDWN_ACK_STATUS_0_H1X_ACK_LSB                    MK_SHIFT_CONST(2)
#define PMC_IMPL_PART_NVJPGB_PWRDWN_ACK_STATUS_0_H1X_ACK_WOFFSET                        0x0
#define PMC_IMPL_PART_NVJPGB_PWRDWN_ACK_STATUS_0_H1X_ACK_DEFAULT                        MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_NVJPGB_PWRDWN_ACK_STATUS_0_H1X_ACK_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_NVJPGB_PWRDWN_ACK_STATUS_0_H1X_ACK_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_NVJPGB_PWRDWN_ACK_STATUS_0_H1X_ACK_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_NVJPGB_PWRDWN_ACK_STATUS_0_H1X_ACK_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_NVJPGB_PWRDWN_ACK_STATUS_0_H1X_ACK_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_NVJPGB_PWRDWN_ACK_STATUS_0_H1X_ACK_INIT_ENUM                      PWRDWN
#define PMC_IMPL_PART_NVJPGB_PWRDWN_ACK_STATUS_0_H1X_ACK_PWRDWN                 MK_ENUM_CONST(1)
#define PMC_IMPL_PART_NVJPGB_PWRDWN_ACK_STATUS_0_H1X_ACK_PWRUP                  MK_ENUM_CONST(0)


// Register PMC_IMPL_PART_NVENC_PWRDWN_REQ_CONTROL_0
#define PMC_IMPL_PART_NVENC_PWRDWN_REQ_CONTROL_0                        MK_ADDR_CONST(0x604)
#define PMC_IMPL_PART_NVENC_PWRDWN_REQ_CONTROL_0_SECURE                         0x0
#define PMC_IMPL_PART_NVENC_PWRDWN_REQ_CONTROL_0_DUAL                   0x0
#define PMC_IMPL_PART_NVENC_PWRDWN_REQ_CONTROL_0_SCR                    PG_NVENC_SCR_0
#define PMC_IMPL_PART_NVENC_PWRDWN_REQ_CONTROL_0_SCRREG                         PMC_IMPL_SCR_PG_NVENC_SCR_0
#define PMC_IMPL_PART_NVENC_PWRDWN_REQ_CONTROL_0_WORD_COUNT                     0x1
#define PMC_IMPL_PART_NVENC_PWRDWN_REQ_CONTROL_0_RESET_VAL                      MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_NVENC_PWRDWN_REQ_CONTROL_0_RESET_MASK                     MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_NVENC_PWRDWN_REQ_CONTROL_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_NVENC_PWRDWN_REQ_CONTROL_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_NVENC_PWRDWN_REQ_CONTROL_0_READ_MASK                      MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_NVENC_PWRDWN_REQ_CONTROL_0_WRITE_MASK                     MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_NVENC_PWRDWN_REQ_CONTROL_0_REQ_SHIFT                      MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_NVENC_PWRDWN_REQ_CONTROL_0_REQ_FIELD                      MK_FIELD_CONST(0x1, PMC_IMPL_PART_NVENC_PWRDWN_REQ_CONTROL_0_REQ_SHIFT)
#define PMC_IMPL_PART_NVENC_PWRDWN_REQ_CONTROL_0_REQ_RANGE                      0:0
#define PMC_IMPL_PART_NVENC_PWRDWN_REQ_CONTROL_0_REQ_MSB                        MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_NVENC_PWRDWN_REQ_CONTROL_0_REQ_LSB                        MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_NVENC_PWRDWN_REQ_CONTROL_0_REQ_WOFFSET                    0x0
#define PMC_IMPL_PART_NVENC_PWRDWN_REQ_CONTROL_0_REQ_DEFAULT                    MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_NVENC_PWRDWN_REQ_CONTROL_0_REQ_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_NVENC_PWRDWN_REQ_CONTROL_0_REQ_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_NVENC_PWRDWN_REQ_CONTROL_0_REQ_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_NVENC_PWRDWN_REQ_CONTROL_0_REQ_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_NVENC_PWRDWN_REQ_CONTROL_0_REQ_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_NVENC_PWRDWN_REQ_CONTROL_0_REQ_INIT_ENUM                  PWRDWN
#define PMC_IMPL_PART_NVENC_PWRDWN_REQ_CONTROL_0_REQ_PWRDWN                     MK_ENUM_CONST(1)
#define PMC_IMPL_PART_NVENC_PWRDWN_REQ_CONTROL_0_REQ_PWRUP                      MK_ENUM_CONST(0)


// Register PMC_IMPL_PART_NVENC_PWRDWN_ACK_STATUS_0
#define PMC_IMPL_PART_NVENC_PWRDWN_ACK_STATUS_0                 MK_ADDR_CONST(0x608)
#define PMC_IMPL_PART_NVENC_PWRDWN_ACK_STATUS_0_SECURE                  0x0
#define PMC_IMPL_PART_NVENC_PWRDWN_ACK_STATUS_0_DUAL                    0x0
#define PMC_IMPL_PART_NVENC_PWRDWN_ACK_STATUS_0_SCR                     PG_NVENC_SCR_0
#define PMC_IMPL_PART_NVENC_PWRDWN_ACK_STATUS_0_SCRREG                  PMC_IMPL_SCR_PG_NVENC_SCR_0
#define PMC_IMPL_PART_NVENC_PWRDWN_ACK_STATUS_0_WORD_COUNT                      0x1
#define PMC_IMPL_PART_NVENC_PWRDWN_ACK_STATUS_0_RESET_VAL                       MK_MASK_CONST(0x7)
#define PMC_IMPL_PART_NVENC_PWRDWN_ACK_STATUS_0_RESET_MASK                      MK_MASK_CONST(0x7)
#define PMC_IMPL_PART_NVENC_PWRDWN_ACK_STATUS_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_NVENC_PWRDWN_ACK_STATUS_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_NVENC_PWRDWN_ACK_STATUS_0_READ_MASK                       MK_MASK_CONST(0x7)
#define PMC_IMPL_PART_NVENC_PWRDWN_ACK_STATUS_0_WRITE_MASK                      MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_NVENC_PWRDWN_ACK_STATUS_0_CBB_ACK_SHIFT                   MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_NVENC_PWRDWN_ACK_STATUS_0_CBB_ACK_FIELD                   MK_FIELD_CONST(0x1, PMC_IMPL_PART_NVENC_PWRDWN_ACK_STATUS_0_CBB_ACK_SHIFT)
#define PMC_IMPL_PART_NVENC_PWRDWN_ACK_STATUS_0_CBB_ACK_RANGE                   0:0
#define PMC_IMPL_PART_NVENC_PWRDWN_ACK_STATUS_0_CBB_ACK_MSB                     MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_NVENC_PWRDWN_ACK_STATUS_0_CBB_ACK_LSB                     MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_NVENC_PWRDWN_ACK_STATUS_0_CBB_ACK_WOFFSET                 0x0
#define PMC_IMPL_PART_NVENC_PWRDWN_ACK_STATUS_0_CBB_ACK_DEFAULT                 MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_NVENC_PWRDWN_ACK_STATUS_0_CBB_ACK_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_NVENC_PWRDWN_ACK_STATUS_0_CBB_ACK_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_NVENC_PWRDWN_ACK_STATUS_0_CBB_ACK_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_NVENC_PWRDWN_ACK_STATUS_0_CBB_ACK_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_NVENC_PWRDWN_ACK_STATUS_0_CBB_ACK_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_NVENC_PWRDWN_ACK_STATUS_0_CBB_ACK_INIT_ENUM                       PWRDWN
#define PMC_IMPL_PART_NVENC_PWRDWN_ACK_STATUS_0_CBB_ACK_PWRDWN                  MK_ENUM_CONST(1)
#define PMC_IMPL_PART_NVENC_PWRDWN_ACK_STATUS_0_CBB_ACK_PWRUP                   MK_ENUM_CONST(0)

#define PMC_IMPL_PART_NVENC_PWRDWN_ACK_STATUS_0_DBB_ACK_SHIFT                   MK_SHIFT_CONST(1)
#define PMC_IMPL_PART_NVENC_PWRDWN_ACK_STATUS_0_DBB_ACK_FIELD                   MK_FIELD_CONST(0x1, PMC_IMPL_PART_NVENC_PWRDWN_ACK_STATUS_0_DBB_ACK_SHIFT)
#define PMC_IMPL_PART_NVENC_PWRDWN_ACK_STATUS_0_DBB_ACK_RANGE                   1:1
#define PMC_IMPL_PART_NVENC_PWRDWN_ACK_STATUS_0_DBB_ACK_MSB                     MK_SHIFT_CONST(1)
#define PMC_IMPL_PART_NVENC_PWRDWN_ACK_STATUS_0_DBB_ACK_LSB                     MK_SHIFT_CONST(1)
#define PMC_IMPL_PART_NVENC_PWRDWN_ACK_STATUS_0_DBB_ACK_WOFFSET                 0x0
#define PMC_IMPL_PART_NVENC_PWRDWN_ACK_STATUS_0_DBB_ACK_DEFAULT                 MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_NVENC_PWRDWN_ACK_STATUS_0_DBB_ACK_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_NVENC_PWRDWN_ACK_STATUS_0_DBB_ACK_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_NVENC_PWRDWN_ACK_STATUS_0_DBB_ACK_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_NVENC_PWRDWN_ACK_STATUS_0_DBB_ACK_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_NVENC_PWRDWN_ACK_STATUS_0_DBB_ACK_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_NVENC_PWRDWN_ACK_STATUS_0_DBB_ACK_INIT_ENUM                       PWRDWN
#define PMC_IMPL_PART_NVENC_PWRDWN_ACK_STATUS_0_DBB_ACK_PWRDWN                  MK_ENUM_CONST(1)
#define PMC_IMPL_PART_NVENC_PWRDWN_ACK_STATUS_0_DBB_ACK_PWRUP                   MK_ENUM_CONST(0)

#define PMC_IMPL_PART_NVENC_PWRDWN_ACK_STATUS_0_H1X_ACK_SHIFT                   MK_SHIFT_CONST(2)
#define PMC_IMPL_PART_NVENC_PWRDWN_ACK_STATUS_0_H1X_ACK_FIELD                   MK_FIELD_CONST(0x1, PMC_IMPL_PART_NVENC_PWRDWN_ACK_STATUS_0_H1X_ACK_SHIFT)
#define PMC_IMPL_PART_NVENC_PWRDWN_ACK_STATUS_0_H1X_ACK_RANGE                   2:2
#define PMC_IMPL_PART_NVENC_PWRDWN_ACK_STATUS_0_H1X_ACK_MSB                     MK_SHIFT_CONST(2)
#define PMC_IMPL_PART_NVENC_PWRDWN_ACK_STATUS_0_H1X_ACK_LSB                     MK_SHIFT_CONST(2)
#define PMC_IMPL_PART_NVENC_PWRDWN_ACK_STATUS_0_H1X_ACK_WOFFSET                 0x0
#define PMC_IMPL_PART_NVENC_PWRDWN_ACK_STATUS_0_H1X_ACK_DEFAULT                 MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_NVENC_PWRDWN_ACK_STATUS_0_H1X_ACK_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_NVENC_PWRDWN_ACK_STATUS_0_H1X_ACK_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_NVENC_PWRDWN_ACK_STATUS_0_H1X_ACK_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_NVENC_PWRDWN_ACK_STATUS_0_H1X_ACK_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_NVENC_PWRDWN_ACK_STATUS_0_H1X_ACK_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_NVENC_PWRDWN_ACK_STATUS_0_H1X_ACK_INIT_ENUM                       PWRDWN
#define PMC_IMPL_PART_NVENC_PWRDWN_ACK_STATUS_0_H1X_ACK_PWRDWN                  MK_ENUM_CONST(1)
#define PMC_IMPL_PART_NVENC_PWRDWN_ACK_STATUS_0_H1X_ACK_PWRUP                   MK_ENUM_CONST(0)


// Register PMC_IMPL_PART_VI_PWRDWN_REQ_CONTROL_0
#define PMC_IMPL_PART_VI_PWRDWN_REQ_CONTROL_0                   MK_ADDR_CONST(0x60c)
#define PMC_IMPL_PART_VI_PWRDWN_REQ_CONTROL_0_SECURE                    0x0
#define PMC_IMPL_PART_VI_PWRDWN_REQ_CONTROL_0_DUAL                      0x0
#define PMC_IMPL_PART_VI_PWRDWN_REQ_CONTROL_0_SCR                       PG_VI_SCR_0
#define PMC_IMPL_PART_VI_PWRDWN_REQ_CONTROL_0_SCRREG                    PMC_IMPL_SCR_PG_VI_SCR_0
#define PMC_IMPL_PART_VI_PWRDWN_REQ_CONTROL_0_WORD_COUNT                        0x1
#define PMC_IMPL_PART_VI_PWRDWN_REQ_CONTROL_0_RESET_VAL                         MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_VI_PWRDWN_REQ_CONTROL_0_RESET_MASK                        MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_VI_PWRDWN_REQ_CONTROL_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_VI_PWRDWN_REQ_CONTROL_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_VI_PWRDWN_REQ_CONTROL_0_READ_MASK                         MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_VI_PWRDWN_REQ_CONTROL_0_WRITE_MASK                        MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_VI_PWRDWN_REQ_CONTROL_0_REQ_SHIFT                 MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_VI_PWRDWN_REQ_CONTROL_0_REQ_FIELD                 MK_FIELD_CONST(0x1, PMC_IMPL_PART_VI_PWRDWN_REQ_CONTROL_0_REQ_SHIFT)
#define PMC_IMPL_PART_VI_PWRDWN_REQ_CONTROL_0_REQ_RANGE                 0:0
#define PMC_IMPL_PART_VI_PWRDWN_REQ_CONTROL_0_REQ_MSB                   MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_VI_PWRDWN_REQ_CONTROL_0_REQ_LSB                   MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_VI_PWRDWN_REQ_CONTROL_0_REQ_WOFFSET                       0x0
#define PMC_IMPL_PART_VI_PWRDWN_REQ_CONTROL_0_REQ_DEFAULT                       MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_VI_PWRDWN_REQ_CONTROL_0_REQ_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_VI_PWRDWN_REQ_CONTROL_0_REQ_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_VI_PWRDWN_REQ_CONTROL_0_REQ_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_VI_PWRDWN_REQ_CONTROL_0_REQ_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_VI_PWRDWN_REQ_CONTROL_0_REQ_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_VI_PWRDWN_REQ_CONTROL_0_REQ_INIT_ENUM                     PWRDWN
#define PMC_IMPL_PART_VI_PWRDWN_REQ_CONTROL_0_REQ_PWRDWN                        MK_ENUM_CONST(1)
#define PMC_IMPL_PART_VI_PWRDWN_REQ_CONTROL_0_REQ_PWRUP                 MK_ENUM_CONST(0)


// Register PMC_IMPL_PART_VI_PWRDWN_ACK_STATUS_0
#define PMC_IMPL_PART_VI_PWRDWN_ACK_STATUS_0                    MK_ADDR_CONST(0x610)
#define PMC_IMPL_PART_VI_PWRDWN_ACK_STATUS_0_SECURE                     0x0
#define PMC_IMPL_PART_VI_PWRDWN_ACK_STATUS_0_DUAL                       0x0
#define PMC_IMPL_PART_VI_PWRDWN_ACK_STATUS_0_SCR                        PG_VI_SCR_0
#define PMC_IMPL_PART_VI_PWRDWN_ACK_STATUS_0_SCRREG                     PMC_IMPL_SCR_PG_VI_SCR_0
#define PMC_IMPL_PART_VI_PWRDWN_ACK_STATUS_0_WORD_COUNT                         0x1
#define PMC_IMPL_PART_VI_PWRDWN_ACK_STATUS_0_RESET_VAL                  MK_MASK_CONST(0x7)
#define PMC_IMPL_PART_VI_PWRDWN_ACK_STATUS_0_RESET_MASK                         MK_MASK_CONST(0x7)
#define PMC_IMPL_PART_VI_PWRDWN_ACK_STATUS_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_VI_PWRDWN_ACK_STATUS_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_VI_PWRDWN_ACK_STATUS_0_READ_MASK                  MK_MASK_CONST(0x7)
#define PMC_IMPL_PART_VI_PWRDWN_ACK_STATUS_0_WRITE_MASK                         MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_VI_PWRDWN_ACK_STATUS_0_CBB_ACK_SHIFT                      MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_VI_PWRDWN_ACK_STATUS_0_CBB_ACK_FIELD                      MK_FIELD_CONST(0x1, PMC_IMPL_PART_VI_PWRDWN_ACK_STATUS_0_CBB_ACK_SHIFT)
#define PMC_IMPL_PART_VI_PWRDWN_ACK_STATUS_0_CBB_ACK_RANGE                      0:0
#define PMC_IMPL_PART_VI_PWRDWN_ACK_STATUS_0_CBB_ACK_MSB                        MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_VI_PWRDWN_ACK_STATUS_0_CBB_ACK_LSB                        MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_VI_PWRDWN_ACK_STATUS_0_CBB_ACK_WOFFSET                    0x0
#define PMC_IMPL_PART_VI_PWRDWN_ACK_STATUS_0_CBB_ACK_DEFAULT                    MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_VI_PWRDWN_ACK_STATUS_0_CBB_ACK_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_VI_PWRDWN_ACK_STATUS_0_CBB_ACK_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_VI_PWRDWN_ACK_STATUS_0_CBB_ACK_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_VI_PWRDWN_ACK_STATUS_0_CBB_ACK_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_VI_PWRDWN_ACK_STATUS_0_CBB_ACK_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_VI_PWRDWN_ACK_STATUS_0_CBB_ACK_INIT_ENUM                  PWRDWN
#define PMC_IMPL_PART_VI_PWRDWN_ACK_STATUS_0_CBB_ACK_PWRDWN                     MK_ENUM_CONST(1)
#define PMC_IMPL_PART_VI_PWRDWN_ACK_STATUS_0_CBB_ACK_PWRUP                      MK_ENUM_CONST(0)

#define PMC_IMPL_PART_VI_PWRDWN_ACK_STATUS_0_DBB_ACK_SHIFT                      MK_SHIFT_CONST(1)
#define PMC_IMPL_PART_VI_PWRDWN_ACK_STATUS_0_DBB_ACK_FIELD                      MK_FIELD_CONST(0x1, PMC_IMPL_PART_VI_PWRDWN_ACK_STATUS_0_DBB_ACK_SHIFT)
#define PMC_IMPL_PART_VI_PWRDWN_ACK_STATUS_0_DBB_ACK_RANGE                      1:1
#define PMC_IMPL_PART_VI_PWRDWN_ACK_STATUS_0_DBB_ACK_MSB                        MK_SHIFT_CONST(1)
#define PMC_IMPL_PART_VI_PWRDWN_ACK_STATUS_0_DBB_ACK_LSB                        MK_SHIFT_CONST(1)
#define PMC_IMPL_PART_VI_PWRDWN_ACK_STATUS_0_DBB_ACK_WOFFSET                    0x0
#define PMC_IMPL_PART_VI_PWRDWN_ACK_STATUS_0_DBB_ACK_DEFAULT                    MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_VI_PWRDWN_ACK_STATUS_0_DBB_ACK_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_VI_PWRDWN_ACK_STATUS_0_DBB_ACK_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_VI_PWRDWN_ACK_STATUS_0_DBB_ACK_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_VI_PWRDWN_ACK_STATUS_0_DBB_ACK_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_VI_PWRDWN_ACK_STATUS_0_DBB_ACK_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_VI_PWRDWN_ACK_STATUS_0_DBB_ACK_INIT_ENUM                  PWRDWN
#define PMC_IMPL_PART_VI_PWRDWN_ACK_STATUS_0_DBB_ACK_PWRDWN                     MK_ENUM_CONST(1)
#define PMC_IMPL_PART_VI_PWRDWN_ACK_STATUS_0_DBB_ACK_PWRUP                      MK_ENUM_CONST(0)

#define PMC_IMPL_PART_VI_PWRDWN_ACK_STATUS_0_H1X_ACK_SHIFT                      MK_SHIFT_CONST(2)
#define PMC_IMPL_PART_VI_PWRDWN_ACK_STATUS_0_H1X_ACK_FIELD                      MK_FIELD_CONST(0x1, PMC_IMPL_PART_VI_PWRDWN_ACK_STATUS_0_H1X_ACK_SHIFT)
#define PMC_IMPL_PART_VI_PWRDWN_ACK_STATUS_0_H1X_ACK_RANGE                      2:2
#define PMC_IMPL_PART_VI_PWRDWN_ACK_STATUS_0_H1X_ACK_MSB                        MK_SHIFT_CONST(2)
#define PMC_IMPL_PART_VI_PWRDWN_ACK_STATUS_0_H1X_ACK_LSB                        MK_SHIFT_CONST(2)
#define PMC_IMPL_PART_VI_PWRDWN_ACK_STATUS_0_H1X_ACK_WOFFSET                    0x0
#define PMC_IMPL_PART_VI_PWRDWN_ACK_STATUS_0_H1X_ACK_DEFAULT                    MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_VI_PWRDWN_ACK_STATUS_0_H1X_ACK_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_VI_PWRDWN_ACK_STATUS_0_H1X_ACK_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_VI_PWRDWN_ACK_STATUS_0_H1X_ACK_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_VI_PWRDWN_ACK_STATUS_0_H1X_ACK_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_VI_PWRDWN_ACK_STATUS_0_H1X_ACK_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_VI_PWRDWN_ACK_STATUS_0_H1X_ACK_INIT_ENUM                  PWRDWN
#define PMC_IMPL_PART_VI_PWRDWN_ACK_STATUS_0_H1X_ACK_PWRDWN                     MK_ENUM_CONST(1)
#define PMC_IMPL_PART_VI_PWRDWN_ACK_STATUS_0_H1X_ACK_PWRUP                      MK_ENUM_CONST(0)


// Register PMC_IMPL_PART_VIC_PWRDWN_REQ_CONTROL_0
#define PMC_IMPL_PART_VIC_PWRDWN_REQ_CONTROL_0                  MK_ADDR_CONST(0x614)
#define PMC_IMPL_PART_VIC_PWRDWN_REQ_CONTROL_0_SECURE                   0x0
#define PMC_IMPL_PART_VIC_PWRDWN_REQ_CONTROL_0_DUAL                     0x0
#define PMC_IMPL_PART_VIC_PWRDWN_REQ_CONTROL_0_SCR                      PG_VIC_SCR_0
#define PMC_IMPL_PART_VIC_PWRDWN_REQ_CONTROL_0_SCRREG                   PMC_IMPL_SCR_PG_VIC_SCR_0
#define PMC_IMPL_PART_VIC_PWRDWN_REQ_CONTROL_0_WORD_COUNT                       0x1
#define PMC_IMPL_PART_VIC_PWRDWN_REQ_CONTROL_0_RESET_VAL                        MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_VIC_PWRDWN_REQ_CONTROL_0_RESET_MASK                       MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_VIC_PWRDWN_REQ_CONTROL_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_VIC_PWRDWN_REQ_CONTROL_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_VIC_PWRDWN_REQ_CONTROL_0_READ_MASK                        MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_VIC_PWRDWN_REQ_CONTROL_0_WRITE_MASK                       MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_VIC_PWRDWN_REQ_CONTROL_0_REQ_SHIFT                        MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_VIC_PWRDWN_REQ_CONTROL_0_REQ_FIELD                        MK_FIELD_CONST(0x1, PMC_IMPL_PART_VIC_PWRDWN_REQ_CONTROL_0_REQ_SHIFT)
#define PMC_IMPL_PART_VIC_PWRDWN_REQ_CONTROL_0_REQ_RANGE                        0:0
#define PMC_IMPL_PART_VIC_PWRDWN_REQ_CONTROL_0_REQ_MSB                  MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_VIC_PWRDWN_REQ_CONTROL_0_REQ_LSB                  MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_VIC_PWRDWN_REQ_CONTROL_0_REQ_WOFFSET                      0x0
#define PMC_IMPL_PART_VIC_PWRDWN_REQ_CONTROL_0_REQ_DEFAULT                      MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_VIC_PWRDWN_REQ_CONTROL_0_REQ_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_VIC_PWRDWN_REQ_CONTROL_0_REQ_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_VIC_PWRDWN_REQ_CONTROL_0_REQ_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_VIC_PWRDWN_REQ_CONTROL_0_REQ_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_VIC_PWRDWN_REQ_CONTROL_0_REQ_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_VIC_PWRDWN_REQ_CONTROL_0_REQ_INIT_ENUM                    PWRDWN
#define PMC_IMPL_PART_VIC_PWRDWN_REQ_CONTROL_0_REQ_PWRDWN                       MK_ENUM_CONST(1)
#define PMC_IMPL_PART_VIC_PWRDWN_REQ_CONTROL_0_REQ_PWRUP                        MK_ENUM_CONST(0)


// Register PMC_IMPL_PART_VIC_PWRDWN_ACK_STATUS_0
#define PMC_IMPL_PART_VIC_PWRDWN_ACK_STATUS_0                   MK_ADDR_CONST(0x618)
#define PMC_IMPL_PART_VIC_PWRDWN_ACK_STATUS_0_SECURE                    0x0
#define PMC_IMPL_PART_VIC_PWRDWN_ACK_STATUS_0_DUAL                      0x0
#define PMC_IMPL_PART_VIC_PWRDWN_ACK_STATUS_0_SCR                       PG_VIC_SCR_0
#define PMC_IMPL_PART_VIC_PWRDWN_ACK_STATUS_0_SCRREG                    PMC_IMPL_SCR_PG_VIC_SCR_0
#define PMC_IMPL_PART_VIC_PWRDWN_ACK_STATUS_0_WORD_COUNT                        0x1
#define PMC_IMPL_PART_VIC_PWRDWN_ACK_STATUS_0_RESET_VAL                         MK_MASK_CONST(0x7)
#define PMC_IMPL_PART_VIC_PWRDWN_ACK_STATUS_0_RESET_MASK                        MK_MASK_CONST(0x7)
#define PMC_IMPL_PART_VIC_PWRDWN_ACK_STATUS_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_VIC_PWRDWN_ACK_STATUS_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_VIC_PWRDWN_ACK_STATUS_0_READ_MASK                         MK_MASK_CONST(0x7)
#define PMC_IMPL_PART_VIC_PWRDWN_ACK_STATUS_0_WRITE_MASK                        MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_VIC_PWRDWN_ACK_STATUS_0_CBB_ACK_SHIFT                     MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_VIC_PWRDWN_ACK_STATUS_0_CBB_ACK_FIELD                     MK_FIELD_CONST(0x1, PMC_IMPL_PART_VIC_PWRDWN_ACK_STATUS_0_CBB_ACK_SHIFT)
#define PMC_IMPL_PART_VIC_PWRDWN_ACK_STATUS_0_CBB_ACK_RANGE                     0:0
#define PMC_IMPL_PART_VIC_PWRDWN_ACK_STATUS_0_CBB_ACK_MSB                       MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_VIC_PWRDWN_ACK_STATUS_0_CBB_ACK_LSB                       MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_VIC_PWRDWN_ACK_STATUS_0_CBB_ACK_WOFFSET                   0x0
#define PMC_IMPL_PART_VIC_PWRDWN_ACK_STATUS_0_CBB_ACK_DEFAULT                   MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_VIC_PWRDWN_ACK_STATUS_0_CBB_ACK_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_VIC_PWRDWN_ACK_STATUS_0_CBB_ACK_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_VIC_PWRDWN_ACK_STATUS_0_CBB_ACK_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_VIC_PWRDWN_ACK_STATUS_0_CBB_ACK_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_VIC_PWRDWN_ACK_STATUS_0_CBB_ACK_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_VIC_PWRDWN_ACK_STATUS_0_CBB_ACK_INIT_ENUM                 PWRDWN
#define PMC_IMPL_PART_VIC_PWRDWN_ACK_STATUS_0_CBB_ACK_PWRDWN                    MK_ENUM_CONST(1)
#define PMC_IMPL_PART_VIC_PWRDWN_ACK_STATUS_0_CBB_ACK_PWRUP                     MK_ENUM_CONST(0)

#define PMC_IMPL_PART_VIC_PWRDWN_ACK_STATUS_0_DBB_ACK_SHIFT                     MK_SHIFT_CONST(1)
#define PMC_IMPL_PART_VIC_PWRDWN_ACK_STATUS_0_DBB_ACK_FIELD                     MK_FIELD_CONST(0x1, PMC_IMPL_PART_VIC_PWRDWN_ACK_STATUS_0_DBB_ACK_SHIFT)
#define PMC_IMPL_PART_VIC_PWRDWN_ACK_STATUS_0_DBB_ACK_RANGE                     1:1
#define PMC_IMPL_PART_VIC_PWRDWN_ACK_STATUS_0_DBB_ACK_MSB                       MK_SHIFT_CONST(1)
#define PMC_IMPL_PART_VIC_PWRDWN_ACK_STATUS_0_DBB_ACK_LSB                       MK_SHIFT_CONST(1)
#define PMC_IMPL_PART_VIC_PWRDWN_ACK_STATUS_0_DBB_ACK_WOFFSET                   0x0
#define PMC_IMPL_PART_VIC_PWRDWN_ACK_STATUS_0_DBB_ACK_DEFAULT                   MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_VIC_PWRDWN_ACK_STATUS_0_DBB_ACK_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_VIC_PWRDWN_ACK_STATUS_0_DBB_ACK_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_VIC_PWRDWN_ACK_STATUS_0_DBB_ACK_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_VIC_PWRDWN_ACK_STATUS_0_DBB_ACK_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_VIC_PWRDWN_ACK_STATUS_0_DBB_ACK_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_VIC_PWRDWN_ACK_STATUS_0_DBB_ACK_INIT_ENUM                 PWRDWN
#define PMC_IMPL_PART_VIC_PWRDWN_ACK_STATUS_0_DBB_ACK_PWRDWN                    MK_ENUM_CONST(1)
#define PMC_IMPL_PART_VIC_PWRDWN_ACK_STATUS_0_DBB_ACK_PWRUP                     MK_ENUM_CONST(0)

#define PMC_IMPL_PART_VIC_PWRDWN_ACK_STATUS_0_H1X_ACK_SHIFT                     MK_SHIFT_CONST(2)
#define PMC_IMPL_PART_VIC_PWRDWN_ACK_STATUS_0_H1X_ACK_FIELD                     MK_FIELD_CONST(0x1, PMC_IMPL_PART_VIC_PWRDWN_ACK_STATUS_0_H1X_ACK_SHIFT)
#define PMC_IMPL_PART_VIC_PWRDWN_ACK_STATUS_0_H1X_ACK_RANGE                     2:2
#define PMC_IMPL_PART_VIC_PWRDWN_ACK_STATUS_0_H1X_ACK_MSB                       MK_SHIFT_CONST(2)
#define PMC_IMPL_PART_VIC_PWRDWN_ACK_STATUS_0_H1X_ACK_LSB                       MK_SHIFT_CONST(2)
#define PMC_IMPL_PART_VIC_PWRDWN_ACK_STATUS_0_H1X_ACK_WOFFSET                   0x0
#define PMC_IMPL_PART_VIC_PWRDWN_ACK_STATUS_0_H1X_ACK_DEFAULT                   MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_VIC_PWRDWN_ACK_STATUS_0_H1X_ACK_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_VIC_PWRDWN_ACK_STATUS_0_H1X_ACK_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_VIC_PWRDWN_ACK_STATUS_0_H1X_ACK_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_VIC_PWRDWN_ACK_STATUS_0_H1X_ACK_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_VIC_PWRDWN_ACK_STATUS_0_H1X_ACK_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_VIC_PWRDWN_ACK_STATUS_0_H1X_ACK_INIT_ENUM                 PWRDWN
#define PMC_IMPL_PART_VIC_PWRDWN_ACK_STATUS_0_H1X_ACK_PWRDWN                    MK_ENUM_CONST(1)
#define PMC_IMPL_PART_VIC_PWRDWN_ACK_STATUS_0_H1X_ACK_PWRUP                     MK_ENUM_CONST(0)


// Register PMC_IMPL_PART_XUSBA_PWRDWN_REQ_CONTROL_0
#define PMC_IMPL_PART_XUSBA_PWRDWN_REQ_CONTROL_0                        MK_ADDR_CONST(0x61c)
#define PMC_IMPL_PART_XUSBA_PWRDWN_REQ_CONTROL_0_SECURE                         0x0
#define PMC_IMPL_PART_XUSBA_PWRDWN_REQ_CONTROL_0_DUAL                   0x0
#define PMC_IMPL_PART_XUSBA_PWRDWN_REQ_CONTROL_0_SCR                    PG_XUSBA_SCR_0
#define PMC_IMPL_PART_XUSBA_PWRDWN_REQ_CONTROL_0_SCRREG                         PMC_IMPL_SCR_PG_XUSBA_SCR_0
#define PMC_IMPL_PART_XUSBA_PWRDWN_REQ_CONTROL_0_WORD_COUNT                     0x1
#define PMC_IMPL_PART_XUSBA_PWRDWN_REQ_CONTROL_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_XUSBA_PWRDWN_REQ_CONTROL_0_RESET_MASK                     MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_XUSBA_PWRDWN_REQ_CONTROL_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_XUSBA_PWRDWN_REQ_CONTROL_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_XUSBA_PWRDWN_REQ_CONTROL_0_READ_MASK                      MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_XUSBA_PWRDWN_REQ_CONTROL_0_WRITE_MASK                     MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_XUSBA_PWRDWN_REQ_CONTROL_0_REQ_SHIFT                      MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_XUSBA_PWRDWN_REQ_CONTROL_0_REQ_FIELD                      MK_FIELD_CONST(0x1, PMC_IMPL_PART_XUSBA_PWRDWN_REQ_CONTROL_0_REQ_SHIFT)
#define PMC_IMPL_PART_XUSBA_PWRDWN_REQ_CONTROL_0_REQ_RANGE                      0:0
#define PMC_IMPL_PART_XUSBA_PWRDWN_REQ_CONTROL_0_REQ_MSB                        MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_XUSBA_PWRDWN_REQ_CONTROL_0_REQ_LSB                        MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_XUSBA_PWRDWN_REQ_CONTROL_0_REQ_WOFFSET                    0x0
#define PMC_IMPL_PART_XUSBA_PWRDWN_REQ_CONTROL_0_REQ_DEFAULT                    MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_XUSBA_PWRDWN_REQ_CONTROL_0_REQ_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_XUSBA_PWRDWN_REQ_CONTROL_0_REQ_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_XUSBA_PWRDWN_REQ_CONTROL_0_REQ_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_XUSBA_PWRDWN_REQ_CONTROL_0_REQ_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_XUSBA_PWRDWN_REQ_CONTROL_0_REQ_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_XUSBA_PWRDWN_REQ_CONTROL_0_REQ_INIT_ENUM                  PWRUP
#define PMC_IMPL_PART_XUSBA_PWRDWN_REQ_CONTROL_0_REQ_PWRDWN                     MK_ENUM_CONST(1)
#define PMC_IMPL_PART_XUSBA_PWRDWN_REQ_CONTROL_0_REQ_PWRUP                      MK_ENUM_CONST(0)


// Register PMC_IMPL_PART_XUSBA_PWRDWN_ACK_STATUS_0
#define PMC_IMPL_PART_XUSBA_PWRDWN_ACK_STATUS_0                 MK_ADDR_CONST(0x620)
#define PMC_IMPL_PART_XUSBA_PWRDWN_ACK_STATUS_0_SECURE                  0x0
#define PMC_IMPL_PART_XUSBA_PWRDWN_ACK_STATUS_0_DUAL                    0x0
#define PMC_IMPL_PART_XUSBA_PWRDWN_ACK_STATUS_0_SCR                     PG_XUSBA_SCR_0
#define PMC_IMPL_PART_XUSBA_PWRDWN_ACK_STATUS_0_SCRREG                  PMC_IMPL_SCR_PG_XUSBA_SCR_0
#define PMC_IMPL_PART_XUSBA_PWRDWN_ACK_STATUS_0_WORD_COUNT                      0x1
#define PMC_IMPL_PART_XUSBA_PWRDWN_ACK_STATUS_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_XUSBA_PWRDWN_ACK_STATUS_0_RESET_MASK                      MK_MASK_CONST(0x7)
#define PMC_IMPL_PART_XUSBA_PWRDWN_ACK_STATUS_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_XUSBA_PWRDWN_ACK_STATUS_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_XUSBA_PWRDWN_ACK_STATUS_0_READ_MASK                       MK_MASK_CONST(0x7)
#define PMC_IMPL_PART_XUSBA_PWRDWN_ACK_STATUS_0_WRITE_MASK                      MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_XUSBA_PWRDWN_ACK_STATUS_0_CBB_ACK_SHIFT                   MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_XUSBA_PWRDWN_ACK_STATUS_0_CBB_ACK_FIELD                   MK_FIELD_CONST(0x1, PMC_IMPL_PART_XUSBA_PWRDWN_ACK_STATUS_0_CBB_ACK_SHIFT)
#define PMC_IMPL_PART_XUSBA_PWRDWN_ACK_STATUS_0_CBB_ACK_RANGE                   0:0
#define PMC_IMPL_PART_XUSBA_PWRDWN_ACK_STATUS_0_CBB_ACK_MSB                     MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_XUSBA_PWRDWN_ACK_STATUS_0_CBB_ACK_LSB                     MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_XUSBA_PWRDWN_ACK_STATUS_0_CBB_ACK_WOFFSET                 0x0
#define PMC_IMPL_PART_XUSBA_PWRDWN_ACK_STATUS_0_CBB_ACK_DEFAULT                 MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_XUSBA_PWRDWN_ACK_STATUS_0_CBB_ACK_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_XUSBA_PWRDWN_ACK_STATUS_0_CBB_ACK_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_XUSBA_PWRDWN_ACK_STATUS_0_CBB_ACK_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_XUSBA_PWRDWN_ACK_STATUS_0_CBB_ACK_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_XUSBA_PWRDWN_ACK_STATUS_0_CBB_ACK_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_XUSBA_PWRDWN_ACK_STATUS_0_CBB_ACK_INIT_ENUM                       PWRUP
#define PMC_IMPL_PART_XUSBA_PWRDWN_ACK_STATUS_0_CBB_ACK_PWRDWN                  MK_ENUM_CONST(1)
#define PMC_IMPL_PART_XUSBA_PWRDWN_ACK_STATUS_0_CBB_ACK_PWRUP                   MK_ENUM_CONST(0)

#define PMC_IMPL_PART_XUSBA_PWRDWN_ACK_STATUS_0_DBB_ACK_SHIFT                   MK_SHIFT_CONST(1)
#define PMC_IMPL_PART_XUSBA_PWRDWN_ACK_STATUS_0_DBB_ACK_FIELD                   MK_FIELD_CONST(0x1, PMC_IMPL_PART_XUSBA_PWRDWN_ACK_STATUS_0_DBB_ACK_SHIFT)
#define PMC_IMPL_PART_XUSBA_PWRDWN_ACK_STATUS_0_DBB_ACK_RANGE                   1:1
#define PMC_IMPL_PART_XUSBA_PWRDWN_ACK_STATUS_0_DBB_ACK_MSB                     MK_SHIFT_CONST(1)
#define PMC_IMPL_PART_XUSBA_PWRDWN_ACK_STATUS_0_DBB_ACK_LSB                     MK_SHIFT_CONST(1)
#define PMC_IMPL_PART_XUSBA_PWRDWN_ACK_STATUS_0_DBB_ACK_WOFFSET                 0x0
#define PMC_IMPL_PART_XUSBA_PWRDWN_ACK_STATUS_0_DBB_ACK_DEFAULT                 MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_XUSBA_PWRDWN_ACK_STATUS_0_DBB_ACK_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_XUSBA_PWRDWN_ACK_STATUS_0_DBB_ACK_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_XUSBA_PWRDWN_ACK_STATUS_0_DBB_ACK_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_XUSBA_PWRDWN_ACK_STATUS_0_DBB_ACK_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_XUSBA_PWRDWN_ACK_STATUS_0_DBB_ACK_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_XUSBA_PWRDWN_ACK_STATUS_0_DBB_ACK_INIT_ENUM                       PWRUP
#define PMC_IMPL_PART_XUSBA_PWRDWN_ACK_STATUS_0_DBB_ACK_PWRDWN                  MK_ENUM_CONST(1)
#define PMC_IMPL_PART_XUSBA_PWRDWN_ACK_STATUS_0_DBB_ACK_PWRUP                   MK_ENUM_CONST(0)

#define PMC_IMPL_PART_XUSBA_PWRDWN_ACK_STATUS_0_H1X_ACK_SHIFT                   MK_SHIFT_CONST(2)
#define PMC_IMPL_PART_XUSBA_PWRDWN_ACK_STATUS_0_H1X_ACK_FIELD                   MK_FIELD_CONST(0x1, PMC_IMPL_PART_XUSBA_PWRDWN_ACK_STATUS_0_H1X_ACK_SHIFT)
#define PMC_IMPL_PART_XUSBA_PWRDWN_ACK_STATUS_0_H1X_ACK_RANGE                   2:2
#define PMC_IMPL_PART_XUSBA_PWRDWN_ACK_STATUS_0_H1X_ACK_MSB                     MK_SHIFT_CONST(2)
#define PMC_IMPL_PART_XUSBA_PWRDWN_ACK_STATUS_0_H1X_ACK_LSB                     MK_SHIFT_CONST(2)
#define PMC_IMPL_PART_XUSBA_PWRDWN_ACK_STATUS_0_H1X_ACK_WOFFSET                 0x0
#define PMC_IMPL_PART_XUSBA_PWRDWN_ACK_STATUS_0_H1X_ACK_DEFAULT                 MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_XUSBA_PWRDWN_ACK_STATUS_0_H1X_ACK_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_XUSBA_PWRDWN_ACK_STATUS_0_H1X_ACK_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_XUSBA_PWRDWN_ACK_STATUS_0_H1X_ACK_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_XUSBA_PWRDWN_ACK_STATUS_0_H1X_ACK_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_XUSBA_PWRDWN_ACK_STATUS_0_H1X_ACK_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_XUSBA_PWRDWN_ACK_STATUS_0_H1X_ACK_INIT_ENUM                       PWRUP
#define PMC_IMPL_PART_XUSBA_PWRDWN_ACK_STATUS_0_H1X_ACK_PWRDWN                  MK_ENUM_CONST(1)
#define PMC_IMPL_PART_XUSBA_PWRDWN_ACK_STATUS_0_H1X_ACK_PWRUP                   MK_ENUM_CONST(0)


// Register PMC_IMPL_PART_XUSBB_PWRDWN_REQ_CONTROL_0
#define PMC_IMPL_PART_XUSBB_PWRDWN_REQ_CONTROL_0                        MK_ADDR_CONST(0x624)
#define PMC_IMPL_PART_XUSBB_PWRDWN_REQ_CONTROL_0_SECURE                         0x0
#define PMC_IMPL_PART_XUSBB_PWRDWN_REQ_CONTROL_0_DUAL                   0x0
#define PMC_IMPL_PART_XUSBB_PWRDWN_REQ_CONTROL_0_SCR                    PG_XUSBB_SCR_0
#define PMC_IMPL_PART_XUSBB_PWRDWN_REQ_CONTROL_0_SCRREG                         PMC_IMPL_SCR_PG_XUSBB_SCR_0
#define PMC_IMPL_PART_XUSBB_PWRDWN_REQ_CONTROL_0_WORD_COUNT                     0x1
#define PMC_IMPL_PART_XUSBB_PWRDWN_REQ_CONTROL_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_XUSBB_PWRDWN_REQ_CONTROL_0_RESET_MASK                     MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_XUSBB_PWRDWN_REQ_CONTROL_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_XUSBB_PWRDWN_REQ_CONTROL_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_XUSBB_PWRDWN_REQ_CONTROL_0_READ_MASK                      MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_XUSBB_PWRDWN_REQ_CONTROL_0_WRITE_MASK                     MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_XUSBB_PWRDWN_REQ_CONTROL_0_REQ_SHIFT                      MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_XUSBB_PWRDWN_REQ_CONTROL_0_REQ_FIELD                      MK_FIELD_CONST(0x1, PMC_IMPL_PART_XUSBB_PWRDWN_REQ_CONTROL_0_REQ_SHIFT)
#define PMC_IMPL_PART_XUSBB_PWRDWN_REQ_CONTROL_0_REQ_RANGE                      0:0
#define PMC_IMPL_PART_XUSBB_PWRDWN_REQ_CONTROL_0_REQ_MSB                        MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_XUSBB_PWRDWN_REQ_CONTROL_0_REQ_LSB                        MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_XUSBB_PWRDWN_REQ_CONTROL_0_REQ_WOFFSET                    0x0
#define PMC_IMPL_PART_XUSBB_PWRDWN_REQ_CONTROL_0_REQ_DEFAULT                    MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_XUSBB_PWRDWN_REQ_CONTROL_0_REQ_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_XUSBB_PWRDWN_REQ_CONTROL_0_REQ_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_XUSBB_PWRDWN_REQ_CONTROL_0_REQ_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_XUSBB_PWRDWN_REQ_CONTROL_0_REQ_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_XUSBB_PWRDWN_REQ_CONTROL_0_REQ_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_XUSBB_PWRDWN_REQ_CONTROL_0_REQ_INIT_ENUM                  PWRUP
#define PMC_IMPL_PART_XUSBB_PWRDWN_REQ_CONTROL_0_REQ_PWRDWN                     MK_ENUM_CONST(1)
#define PMC_IMPL_PART_XUSBB_PWRDWN_REQ_CONTROL_0_REQ_PWRUP                      MK_ENUM_CONST(0)


// Register PMC_IMPL_PART_XUSBB_PWRDWN_ACK_STATUS_0
#define PMC_IMPL_PART_XUSBB_PWRDWN_ACK_STATUS_0                 MK_ADDR_CONST(0x628)
#define PMC_IMPL_PART_XUSBB_PWRDWN_ACK_STATUS_0_SECURE                  0x0
#define PMC_IMPL_PART_XUSBB_PWRDWN_ACK_STATUS_0_DUAL                    0x0
#define PMC_IMPL_PART_XUSBB_PWRDWN_ACK_STATUS_0_SCR                     PG_XUSBB_SCR_0
#define PMC_IMPL_PART_XUSBB_PWRDWN_ACK_STATUS_0_SCRREG                  PMC_IMPL_SCR_PG_XUSBB_SCR_0
#define PMC_IMPL_PART_XUSBB_PWRDWN_ACK_STATUS_0_WORD_COUNT                      0x1
#define PMC_IMPL_PART_XUSBB_PWRDWN_ACK_STATUS_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_XUSBB_PWRDWN_ACK_STATUS_0_RESET_MASK                      MK_MASK_CONST(0x7)
#define PMC_IMPL_PART_XUSBB_PWRDWN_ACK_STATUS_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_XUSBB_PWRDWN_ACK_STATUS_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_XUSBB_PWRDWN_ACK_STATUS_0_READ_MASK                       MK_MASK_CONST(0x7)
#define PMC_IMPL_PART_XUSBB_PWRDWN_ACK_STATUS_0_WRITE_MASK                      MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_XUSBB_PWRDWN_ACK_STATUS_0_CBB_ACK_SHIFT                   MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_XUSBB_PWRDWN_ACK_STATUS_0_CBB_ACK_FIELD                   MK_FIELD_CONST(0x1, PMC_IMPL_PART_XUSBB_PWRDWN_ACK_STATUS_0_CBB_ACK_SHIFT)
#define PMC_IMPL_PART_XUSBB_PWRDWN_ACK_STATUS_0_CBB_ACK_RANGE                   0:0
#define PMC_IMPL_PART_XUSBB_PWRDWN_ACK_STATUS_0_CBB_ACK_MSB                     MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_XUSBB_PWRDWN_ACK_STATUS_0_CBB_ACK_LSB                     MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_XUSBB_PWRDWN_ACK_STATUS_0_CBB_ACK_WOFFSET                 0x0
#define PMC_IMPL_PART_XUSBB_PWRDWN_ACK_STATUS_0_CBB_ACK_DEFAULT                 MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_XUSBB_PWRDWN_ACK_STATUS_0_CBB_ACK_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_XUSBB_PWRDWN_ACK_STATUS_0_CBB_ACK_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_XUSBB_PWRDWN_ACK_STATUS_0_CBB_ACK_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_XUSBB_PWRDWN_ACK_STATUS_0_CBB_ACK_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_XUSBB_PWRDWN_ACK_STATUS_0_CBB_ACK_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_XUSBB_PWRDWN_ACK_STATUS_0_CBB_ACK_INIT_ENUM                       PWRUP
#define PMC_IMPL_PART_XUSBB_PWRDWN_ACK_STATUS_0_CBB_ACK_PWRDWN                  MK_ENUM_CONST(1)
#define PMC_IMPL_PART_XUSBB_PWRDWN_ACK_STATUS_0_CBB_ACK_PWRUP                   MK_ENUM_CONST(0)

#define PMC_IMPL_PART_XUSBB_PWRDWN_ACK_STATUS_0_DBB_ACK_SHIFT                   MK_SHIFT_CONST(1)
#define PMC_IMPL_PART_XUSBB_PWRDWN_ACK_STATUS_0_DBB_ACK_FIELD                   MK_FIELD_CONST(0x1, PMC_IMPL_PART_XUSBB_PWRDWN_ACK_STATUS_0_DBB_ACK_SHIFT)
#define PMC_IMPL_PART_XUSBB_PWRDWN_ACK_STATUS_0_DBB_ACK_RANGE                   1:1
#define PMC_IMPL_PART_XUSBB_PWRDWN_ACK_STATUS_0_DBB_ACK_MSB                     MK_SHIFT_CONST(1)
#define PMC_IMPL_PART_XUSBB_PWRDWN_ACK_STATUS_0_DBB_ACK_LSB                     MK_SHIFT_CONST(1)
#define PMC_IMPL_PART_XUSBB_PWRDWN_ACK_STATUS_0_DBB_ACK_WOFFSET                 0x0
#define PMC_IMPL_PART_XUSBB_PWRDWN_ACK_STATUS_0_DBB_ACK_DEFAULT                 MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_XUSBB_PWRDWN_ACK_STATUS_0_DBB_ACK_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_XUSBB_PWRDWN_ACK_STATUS_0_DBB_ACK_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_XUSBB_PWRDWN_ACK_STATUS_0_DBB_ACK_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_XUSBB_PWRDWN_ACK_STATUS_0_DBB_ACK_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_XUSBB_PWRDWN_ACK_STATUS_0_DBB_ACK_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_XUSBB_PWRDWN_ACK_STATUS_0_DBB_ACK_INIT_ENUM                       PWRUP
#define PMC_IMPL_PART_XUSBB_PWRDWN_ACK_STATUS_0_DBB_ACK_PWRDWN                  MK_ENUM_CONST(1)
#define PMC_IMPL_PART_XUSBB_PWRDWN_ACK_STATUS_0_DBB_ACK_PWRUP                   MK_ENUM_CONST(0)

#define PMC_IMPL_PART_XUSBB_PWRDWN_ACK_STATUS_0_H1X_ACK_SHIFT                   MK_SHIFT_CONST(2)
#define PMC_IMPL_PART_XUSBB_PWRDWN_ACK_STATUS_0_H1X_ACK_FIELD                   MK_FIELD_CONST(0x1, PMC_IMPL_PART_XUSBB_PWRDWN_ACK_STATUS_0_H1X_ACK_SHIFT)
#define PMC_IMPL_PART_XUSBB_PWRDWN_ACK_STATUS_0_H1X_ACK_RANGE                   2:2
#define PMC_IMPL_PART_XUSBB_PWRDWN_ACK_STATUS_0_H1X_ACK_MSB                     MK_SHIFT_CONST(2)
#define PMC_IMPL_PART_XUSBB_PWRDWN_ACK_STATUS_0_H1X_ACK_LSB                     MK_SHIFT_CONST(2)
#define PMC_IMPL_PART_XUSBB_PWRDWN_ACK_STATUS_0_H1X_ACK_WOFFSET                 0x0
#define PMC_IMPL_PART_XUSBB_PWRDWN_ACK_STATUS_0_H1X_ACK_DEFAULT                 MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_XUSBB_PWRDWN_ACK_STATUS_0_H1X_ACK_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_XUSBB_PWRDWN_ACK_STATUS_0_H1X_ACK_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_XUSBB_PWRDWN_ACK_STATUS_0_H1X_ACK_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_XUSBB_PWRDWN_ACK_STATUS_0_H1X_ACK_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_XUSBB_PWRDWN_ACK_STATUS_0_H1X_ACK_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_XUSBB_PWRDWN_ACK_STATUS_0_H1X_ACK_INIT_ENUM                       PWRUP
#define PMC_IMPL_PART_XUSBB_PWRDWN_ACK_STATUS_0_H1X_ACK_PWRDWN                  MK_ENUM_CONST(1)
#define PMC_IMPL_PART_XUSBB_PWRDWN_ACK_STATUS_0_H1X_ACK_PWRUP                   MK_ENUM_CONST(0)


// Register PMC_IMPL_PART_XUSBC_PWRDWN_REQ_CONTROL_0
#define PMC_IMPL_PART_XUSBC_PWRDWN_REQ_CONTROL_0                        MK_ADDR_CONST(0x62c)
#define PMC_IMPL_PART_XUSBC_PWRDWN_REQ_CONTROL_0_SECURE                         0x0
#define PMC_IMPL_PART_XUSBC_PWRDWN_REQ_CONTROL_0_DUAL                   0x0
#define PMC_IMPL_PART_XUSBC_PWRDWN_REQ_CONTROL_0_SCR                    PG_XUSBC_SCR_0
#define PMC_IMPL_PART_XUSBC_PWRDWN_REQ_CONTROL_0_SCRREG                         PMC_IMPL_SCR_PG_XUSBC_SCR_0
#define PMC_IMPL_PART_XUSBC_PWRDWN_REQ_CONTROL_0_WORD_COUNT                     0x1
#define PMC_IMPL_PART_XUSBC_PWRDWN_REQ_CONTROL_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_XUSBC_PWRDWN_REQ_CONTROL_0_RESET_MASK                     MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_XUSBC_PWRDWN_REQ_CONTROL_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_XUSBC_PWRDWN_REQ_CONTROL_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_XUSBC_PWRDWN_REQ_CONTROL_0_READ_MASK                      MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_XUSBC_PWRDWN_REQ_CONTROL_0_WRITE_MASK                     MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_XUSBC_PWRDWN_REQ_CONTROL_0_REQ_SHIFT                      MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_XUSBC_PWRDWN_REQ_CONTROL_0_REQ_FIELD                      MK_FIELD_CONST(0x1, PMC_IMPL_PART_XUSBC_PWRDWN_REQ_CONTROL_0_REQ_SHIFT)
#define PMC_IMPL_PART_XUSBC_PWRDWN_REQ_CONTROL_0_REQ_RANGE                      0:0
#define PMC_IMPL_PART_XUSBC_PWRDWN_REQ_CONTROL_0_REQ_MSB                        MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_XUSBC_PWRDWN_REQ_CONTROL_0_REQ_LSB                        MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_XUSBC_PWRDWN_REQ_CONTROL_0_REQ_WOFFSET                    0x0
#define PMC_IMPL_PART_XUSBC_PWRDWN_REQ_CONTROL_0_REQ_DEFAULT                    MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_XUSBC_PWRDWN_REQ_CONTROL_0_REQ_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_XUSBC_PWRDWN_REQ_CONTROL_0_REQ_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_XUSBC_PWRDWN_REQ_CONTROL_0_REQ_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_XUSBC_PWRDWN_REQ_CONTROL_0_REQ_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_XUSBC_PWRDWN_REQ_CONTROL_0_REQ_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_XUSBC_PWRDWN_REQ_CONTROL_0_REQ_INIT_ENUM                  PWRUP
#define PMC_IMPL_PART_XUSBC_PWRDWN_REQ_CONTROL_0_REQ_PWRDWN                     MK_ENUM_CONST(1)
#define PMC_IMPL_PART_XUSBC_PWRDWN_REQ_CONTROL_0_REQ_PWRUP                      MK_ENUM_CONST(0)


// Register PMC_IMPL_PART_XUSBC_PWRDWN_ACK_STATUS_0
#define PMC_IMPL_PART_XUSBC_PWRDWN_ACK_STATUS_0                 MK_ADDR_CONST(0x630)
#define PMC_IMPL_PART_XUSBC_PWRDWN_ACK_STATUS_0_SECURE                  0x0
#define PMC_IMPL_PART_XUSBC_PWRDWN_ACK_STATUS_0_DUAL                    0x0
#define PMC_IMPL_PART_XUSBC_PWRDWN_ACK_STATUS_0_SCR                     PG_XUSBC_SCR_0
#define PMC_IMPL_PART_XUSBC_PWRDWN_ACK_STATUS_0_SCRREG                  PMC_IMPL_SCR_PG_XUSBC_SCR_0
#define PMC_IMPL_PART_XUSBC_PWRDWN_ACK_STATUS_0_WORD_COUNT                      0x1
#define PMC_IMPL_PART_XUSBC_PWRDWN_ACK_STATUS_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_XUSBC_PWRDWN_ACK_STATUS_0_RESET_MASK                      MK_MASK_CONST(0x7)
#define PMC_IMPL_PART_XUSBC_PWRDWN_ACK_STATUS_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_XUSBC_PWRDWN_ACK_STATUS_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_XUSBC_PWRDWN_ACK_STATUS_0_READ_MASK                       MK_MASK_CONST(0x7)
#define PMC_IMPL_PART_XUSBC_PWRDWN_ACK_STATUS_0_WRITE_MASK                      MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_XUSBC_PWRDWN_ACK_STATUS_0_CBB_ACK_SHIFT                   MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_XUSBC_PWRDWN_ACK_STATUS_0_CBB_ACK_FIELD                   MK_FIELD_CONST(0x1, PMC_IMPL_PART_XUSBC_PWRDWN_ACK_STATUS_0_CBB_ACK_SHIFT)
#define PMC_IMPL_PART_XUSBC_PWRDWN_ACK_STATUS_0_CBB_ACK_RANGE                   0:0
#define PMC_IMPL_PART_XUSBC_PWRDWN_ACK_STATUS_0_CBB_ACK_MSB                     MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_XUSBC_PWRDWN_ACK_STATUS_0_CBB_ACK_LSB                     MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_XUSBC_PWRDWN_ACK_STATUS_0_CBB_ACK_WOFFSET                 0x0
#define PMC_IMPL_PART_XUSBC_PWRDWN_ACK_STATUS_0_CBB_ACK_DEFAULT                 MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_XUSBC_PWRDWN_ACK_STATUS_0_CBB_ACK_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_XUSBC_PWRDWN_ACK_STATUS_0_CBB_ACK_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_XUSBC_PWRDWN_ACK_STATUS_0_CBB_ACK_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_XUSBC_PWRDWN_ACK_STATUS_0_CBB_ACK_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_XUSBC_PWRDWN_ACK_STATUS_0_CBB_ACK_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_XUSBC_PWRDWN_ACK_STATUS_0_CBB_ACK_INIT_ENUM                       PWRUP
#define PMC_IMPL_PART_XUSBC_PWRDWN_ACK_STATUS_0_CBB_ACK_PWRDWN                  MK_ENUM_CONST(1)
#define PMC_IMPL_PART_XUSBC_PWRDWN_ACK_STATUS_0_CBB_ACK_PWRUP                   MK_ENUM_CONST(0)

#define PMC_IMPL_PART_XUSBC_PWRDWN_ACK_STATUS_0_DBB_ACK_SHIFT                   MK_SHIFT_CONST(1)
#define PMC_IMPL_PART_XUSBC_PWRDWN_ACK_STATUS_0_DBB_ACK_FIELD                   MK_FIELD_CONST(0x1, PMC_IMPL_PART_XUSBC_PWRDWN_ACK_STATUS_0_DBB_ACK_SHIFT)
#define PMC_IMPL_PART_XUSBC_PWRDWN_ACK_STATUS_0_DBB_ACK_RANGE                   1:1
#define PMC_IMPL_PART_XUSBC_PWRDWN_ACK_STATUS_0_DBB_ACK_MSB                     MK_SHIFT_CONST(1)
#define PMC_IMPL_PART_XUSBC_PWRDWN_ACK_STATUS_0_DBB_ACK_LSB                     MK_SHIFT_CONST(1)
#define PMC_IMPL_PART_XUSBC_PWRDWN_ACK_STATUS_0_DBB_ACK_WOFFSET                 0x0
#define PMC_IMPL_PART_XUSBC_PWRDWN_ACK_STATUS_0_DBB_ACK_DEFAULT                 MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_XUSBC_PWRDWN_ACK_STATUS_0_DBB_ACK_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_XUSBC_PWRDWN_ACK_STATUS_0_DBB_ACK_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_XUSBC_PWRDWN_ACK_STATUS_0_DBB_ACK_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_XUSBC_PWRDWN_ACK_STATUS_0_DBB_ACK_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_XUSBC_PWRDWN_ACK_STATUS_0_DBB_ACK_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_XUSBC_PWRDWN_ACK_STATUS_0_DBB_ACK_INIT_ENUM                       PWRUP
#define PMC_IMPL_PART_XUSBC_PWRDWN_ACK_STATUS_0_DBB_ACK_PWRDWN                  MK_ENUM_CONST(1)
#define PMC_IMPL_PART_XUSBC_PWRDWN_ACK_STATUS_0_DBB_ACK_PWRUP                   MK_ENUM_CONST(0)

#define PMC_IMPL_PART_XUSBC_PWRDWN_ACK_STATUS_0_H1X_ACK_SHIFT                   MK_SHIFT_CONST(2)
#define PMC_IMPL_PART_XUSBC_PWRDWN_ACK_STATUS_0_H1X_ACK_FIELD                   MK_FIELD_CONST(0x1, PMC_IMPL_PART_XUSBC_PWRDWN_ACK_STATUS_0_H1X_ACK_SHIFT)
#define PMC_IMPL_PART_XUSBC_PWRDWN_ACK_STATUS_0_H1X_ACK_RANGE                   2:2
#define PMC_IMPL_PART_XUSBC_PWRDWN_ACK_STATUS_0_H1X_ACK_MSB                     MK_SHIFT_CONST(2)
#define PMC_IMPL_PART_XUSBC_PWRDWN_ACK_STATUS_0_H1X_ACK_LSB                     MK_SHIFT_CONST(2)
#define PMC_IMPL_PART_XUSBC_PWRDWN_ACK_STATUS_0_H1X_ACK_WOFFSET                 0x0
#define PMC_IMPL_PART_XUSBC_PWRDWN_ACK_STATUS_0_H1X_ACK_DEFAULT                 MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_XUSBC_PWRDWN_ACK_STATUS_0_H1X_ACK_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_XUSBC_PWRDWN_ACK_STATUS_0_H1X_ACK_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_XUSBC_PWRDWN_ACK_STATUS_0_H1X_ACK_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_XUSBC_PWRDWN_ACK_STATUS_0_H1X_ACK_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_XUSBC_PWRDWN_ACK_STATUS_0_H1X_ACK_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_XUSBC_PWRDWN_ACK_STATUS_0_H1X_ACK_INIT_ENUM                       PWRUP
#define PMC_IMPL_PART_XUSBC_PWRDWN_ACK_STATUS_0_H1X_ACK_PWRDWN                  MK_ENUM_CONST(1)
#define PMC_IMPL_PART_XUSBC_PWRDWN_ACK_STATUS_0_H1X_ACK_PWRUP                   MK_ENUM_CONST(0)


// Register PMC_IMPL_PART_PCIEX8A_PWRDWN_REQ_CONTROL_0
#define PMC_IMPL_PART_PCIEX8A_PWRDWN_REQ_CONTROL_0                      MK_ADDR_CONST(0x634)
#define PMC_IMPL_PART_PCIEX8A_PWRDWN_REQ_CONTROL_0_SECURE                       0x0
#define PMC_IMPL_PART_PCIEX8A_PWRDWN_REQ_CONTROL_0_DUAL                         0x0
#define PMC_IMPL_PART_PCIEX8A_PWRDWN_REQ_CONTROL_0_SCR                  PG_PCIEX8A_SCR_0
#define PMC_IMPL_PART_PCIEX8A_PWRDWN_REQ_CONTROL_0_SCRREG                       PMC_IMPL_SCR_PG_PCIEX8A_SCR_0
#define PMC_IMPL_PART_PCIEX8A_PWRDWN_REQ_CONTROL_0_WORD_COUNT                   0x1
#define PMC_IMPL_PART_PCIEX8A_PWRDWN_REQ_CONTROL_0_RESET_VAL                    MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PCIEX8A_PWRDWN_REQ_CONTROL_0_RESET_MASK                   MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PCIEX8A_PWRDWN_REQ_CONTROL_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX8A_PWRDWN_REQ_CONTROL_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX8A_PWRDWN_REQ_CONTROL_0_READ_MASK                    MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PCIEX8A_PWRDWN_REQ_CONTROL_0_WRITE_MASK                   MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PCIEX8A_PWRDWN_REQ_CONTROL_0_REQ_SHIFT                    MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_PCIEX8A_PWRDWN_REQ_CONTROL_0_REQ_FIELD                    MK_FIELD_CONST(0x1, PMC_IMPL_PART_PCIEX8A_PWRDWN_REQ_CONTROL_0_REQ_SHIFT)
#define PMC_IMPL_PART_PCIEX8A_PWRDWN_REQ_CONTROL_0_REQ_RANGE                    0:0
#define PMC_IMPL_PART_PCIEX8A_PWRDWN_REQ_CONTROL_0_REQ_MSB                      MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_PCIEX8A_PWRDWN_REQ_CONTROL_0_REQ_LSB                      MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_PCIEX8A_PWRDWN_REQ_CONTROL_0_REQ_WOFFSET                  0x0
#define PMC_IMPL_PART_PCIEX8A_PWRDWN_REQ_CONTROL_0_REQ_DEFAULT                  MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PCIEX8A_PWRDWN_REQ_CONTROL_0_REQ_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PCIEX8A_PWRDWN_REQ_CONTROL_0_REQ_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX8A_PWRDWN_REQ_CONTROL_0_REQ_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX8A_PWRDWN_REQ_CONTROL_0_REQ_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PCIEX8A_PWRDWN_REQ_CONTROL_0_REQ_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PCIEX8A_PWRDWN_REQ_CONTROL_0_REQ_INIT_ENUM                        PWRDWN
#define PMC_IMPL_PART_PCIEX8A_PWRDWN_REQ_CONTROL_0_REQ_PWRDWN                   MK_ENUM_CONST(1)
#define PMC_IMPL_PART_PCIEX8A_PWRDWN_REQ_CONTROL_0_REQ_PWRUP                    MK_ENUM_CONST(0)


// Register PMC_IMPL_PART_PCIEX8A_PWRDWN_ACK_STATUS_0
#define PMC_IMPL_PART_PCIEX8A_PWRDWN_ACK_STATUS_0                       MK_ADDR_CONST(0x638)
#define PMC_IMPL_PART_PCIEX8A_PWRDWN_ACK_STATUS_0_SECURE                        0x0
#define PMC_IMPL_PART_PCIEX8A_PWRDWN_ACK_STATUS_0_DUAL                  0x0
#define PMC_IMPL_PART_PCIEX8A_PWRDWN_ACK_STATUS_0_SCR                   PG_PCIEX8A_SCR_0
#define PMC_IMPL_PART_PCIEX8A_PWRDWN_ACK_STATUS_0_SCRREG                        PMC_IMPL_SCR_PG_PCIEX8A_SCR_0
#define PMC_IMPL_PART_PCIEX8A_PWRDWN_ACK_STATUS_0_WORD_COUNT                    0x1
#define PMC_IMPL_PART_PCIEX8A_PWRDWN_ACK_STATUS_0_RESET_VAL                     MK_MASK_CONST(0x7)
#define PMC_IMPL_PART_PCIEX8A_PWRDWN_ACK_STATUS_0_RESET_MASK                    MK_MASK_CONST(0x7)
#define PMC_IMPL_PART_PCIEX8A_PWRDWN_ACK_STATUS_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX8A_PWRDWN_ACK_STATUS_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX8A_PWRDWN_ACK_STATUS_0_READ_MASK                     MK_MASK_CONST(0x7)
#define PMC_IMPL_PART_PCIEX8A_PWRDWN_ACK_STATUS_0_WRITE_MASK                    MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX8A_PWRDWN_ACK_STATUS_0_CBB_ACK_SHIFT                 MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_PCIEX8A_PWRDWN_ACK_STATUS_0_CBB_ACK_FIELD                 MK_FIELD_CONST(0x1, PMC_IMPL_PART_PCIEX8A_PWRDWN_ACK_STATUS_0_CBB_ACK_SHIFT)
#define PMC_IMPL_PART_PCIEX8A_PWRDWN_ACK_STATUS_0_CBB_ACK_RANGE                 0:0
#define PMC_IMPL_PART_PCIEX8A_PWRDWN_ACK_STATUS_0_CBB_ACK_MSB                   MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_PCIEX8A_PWRDWN_ACK_STATUS_0_CBB_ACK_LSB                   MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_PCIEX8A_PWRDWN_ACK_STATUS_0_CBB_ACK_WOFFSET                       0x0
#define PMC_IMPL_PART_PCIEX8A_PWRDWN_ACK_STATUS_0_CBB_ACK_DEFAULT                       MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PCIEX8A_PWRDWN_ACK_STATUS_0_CBB_ACK_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PCIEX8A_PWRDWN_ACK_STATUS_0_CBB_ACK_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX8A_PWRDWN_ACK_STATUS_0_CBB_ACK_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX8A_PWRDWN_ACK_STATUS_0_CBB_ACK_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX8A_PWRDWN_ACK_STATUS_0_CBB_ACK_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PCIEX8A_PWRDWN_ACK_STATUS_0_CBB_ACK_INIT_ENUM                     PWRDWN
#define PMC_IMPL_PART_PCIEX8A_PWRDWN_ACK_STATUS_0_CBB_ACK_PWRDWN                        MK_ENUM_CONST(1)
#define PMC_IMPL_PART_PCIEX8A_PWRDWN_ACK_STATUS_0_CBB_ACK_PWRUP                 MK_ENUM_CONST(0)

#define PMC_IMPL_PART_PCIEX8A_PWRDWN_ACK_STATUS_0_DBB_ACK_SHIFT                 MK_SHIFT_CONST(1)
#define PMC_IMPL_PART_PCIEX8A_PWRDWN_ACK_STATUS_0_DBB_ACK_FIELD                 MK_FIELD_CONST(0x1, PMC_IMPL_PART_PCIEX8A_PWRDWN_ACK_STATUS_0_DBB_ACK_SHIFT)
#define PMC_IMPL_PART_PCIEX8A_PWRDWN_ACK_STATUS_0_DBB_ACK_RANGE                 1:1
#define PMC_IMPL_PART_PCIEX8A_PWRDWN_ACK_STATUS_0_DBB_ACK_MSB                   MK_SHIFT_CONST(1)
#define PMC_IMPL_PART_PCIEX8A_PWRDWN_ACK_STATUS_0_DBB_ACK_LSB                   MK_SHIFT_CONST(1)
#define PMC_IMPL_PART_PCIEX8A_PWRDWN_ACK_STATUS_0_DBB_ACK_WOFFSET                       0x0
#define PMC_IMPL_PART_PCIEX8A_PWRDWN_ACK_STATUS_0_DBB_ACK_DEFAULT                       MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PCIEX8A_PWRDWN_ACK_STATUS_0_DBB_ACK_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PCIEX8A_PWRDWN_ACK_STATUS_0_DBB_ACK_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX8A_PWRDWN_ACK_STATUS_0_DBB_ACK_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX8A_PWRDWN_ACK_STATUS_0_DBB_ACK_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX8A_PWRDWN_ACK_STATUS_0_DBB_ACK_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PCIEX8A_PWRDWN_ACK_STATUS_0_DBB_ACK_INIT_ENUM                     PWRDWN
#define PMC_IMPL_PART_PCIEX8A_PWRDWN_ACK_STATUS_0_DBB_ACK_PWRDWN                        MK_ENUM_CONST(1)
#define PMC_IMPL_PART_PCIEX8A_PWRDWN_ACK_STATUS_0_DBB_ACK_PWRUP                 MK_ENUM_CONST(0)

#define PMC_IMPL_PART_PCIEX8A_PWRDWN_ACK_STATUS_0_H1X_ACK_SHIFT                 MK_SHIFT_CONST(2)
#define PMC_IMPL_PART_PCIEX8A_PWRDWN_ACK_STATUS_0_H1X_ACK_FIELD                 MK_FIELD_CONST(0x1, PMC_IMPL_PART_PCIEX8A_PWRDWN_ACK_STATUS_0_H1X_ACK_SHIFT)
#define PMC_IMPL_PART_PCIEX8A_PWRDWN_ACK_STATUS_0_H1X_ACK_RANGE                 2:2
#define PMC_IMPL_PART_PCIEX8A_PWRDWN_ACK_STATUS_0_H1X_ACK_MSB                   MK_SHIFT_CONST(2)
#define PMC_IMPL_PART_PCIEX8A_PWRDWN_ACK_STATUS_0_H1X_ACK_LSB                   MK_SHIFT_CONST(2)
#define PMC_IMPL_PART_PCIEX8A_PWRDWN_ACK_STATUS_0_H1X_ACK_WOFFSET                       0x0
#define PMC_IMPL_PART_PCIEX8A_PWRDWN_ACK_STATUS_0_H1X_ACK_DEFAULT                       MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PCIEX8A_PWRDWN_ACK_STATUS_0_H1X_ACK_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PCIEX8A_PWRDWN_ACK_STATUS_0_H1X_ACK_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX8A_PWRDWN_ACK_STATUS_0_H1X_ACK_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX8A_PWRDWN_ACK_STATUS_0_H1X_ACK_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX8A_PWRDWN_ACK_STATUS_0_H1X_ACK_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PCIEX8A_PWRDWN_ACK_STATUS_0_H1X_ACK_INIT_ENUM                     PWRDWN
#define PMC_IMPL_PART_PCIEX8A_PWRDWN_ACK_STATUS_0_H1X_ACK_PWRDWN                        MK_ENUM_CONST(1)
#define PMC_IMPL_PART_PCIEX8A_PWRDWN_ACK_STATUS_0_H1X_ACK_PWRUP                 MK_ENUM_CONST(0)


// Register PMC_IMPL_PART_PCIEX4A_PWRDWN_REQ_CONTROL_0
#define PMC_IMPL_PART_PCIEX4A_PWRDWN_REQ_CONTROL_0                      MK_ADDR_CONST(0x63c)
#define PMC_IMPL_PART_PCIEX4A_PWRDWN_REQ_CONTROL_0_SECURE                       0x0
#define PMC_IMPL_PART_PCIEX4A_PWRDWN_REQ_CONTROL_0_DUAL                         0x0
#define PMC_IMPL_PART_PCIEX4A_PWRDWN_REQ_CONTROL_0_SCR                  PG_PCIEX4A_SCR_0
#define PMC_IMPL_PART_PCIEX4A_PWRDWN_REQ_CONTROL_0_SCRREG                       PMC_IMPL_SCR_PG_PCIEX4A_SCR_0
#define PMC_IMPL_PART_PCIEX4A_PWRDWN_REQ_CONTROL_0_WORD_COUNT                   0x1
#define PMC_IMPL_PART_PCIEX4A_PWRDWN_REQ_CONTROL_0_RESET_VAL                    MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PCIEX4A_PWRDWN_REQ_CONTROL_0_RESET_MASK                   MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PCIEX4A_PWRDWN_REQ_CONTROL_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX4A_PWRDWN_REQ_CONTROL_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX4A_PWRDWN_REQ_CONTROL_0_READ_MASK                    MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PCIEX4A_PWRDWN_REQ_CONTROL_0_WRITE_MASK                   MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PCIEX4A_PWRDWN_REQ_CONTROL_0_REQ_SHIFT                    MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_PCIEX4A_PWRDWN_REQ_CONTROL_0_REQ_FIELD                    MK_FIELD_CONST(0x1, PMC_IMPL_PART_PCIEX4A_PWRDWN_REQ_CONTROL_0_REQ_SHIFT)
#define PMC_IMPL_PART_PCIEX4A_PWRDWN_REQ_CONTROL_0_REQ_RANGE                    0:0
#define PMC_IMPL_PART_PCIEX4A_PWRDWN_REQ_CONTROL_0_REQ_MSB                      MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_PCIEX4A_PWRDWN_REQ_CONTROL_0_REQ_LSB                      MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_PCIEX4A_PWRDWN_REQ_CONTROL_0_REQ_WOFFSET                  0x0
#define PMC_IMPL_PART_PCIEX4A_PWRDWN_REQ_CONTROL_0_REQ_DEFAULT                  MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PCIEX4A_PWRDWN_REQ_CONTROL_0_REQ_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PCIEX4A_PWRDWN_REQ_CONTROL_0_REQ_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX4A_PWRDWN_REQ_CONTROL_0_REQ_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX4A_PWRDWN_REQ_CONTROL_0_REQ_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PCIEX4A_PWRDWN_REQ_CONTROL_0_REQ_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PCIEX4A_PWRDWN_REQ_CONTROL_0_REQ_INIT_ENUM                        PWRDWN
#define PMC_IMPL_PART_PCIEX4A_PWRDWN_REQ_CONTROL_0_REQ_PWRDWN                   MK_ENUM_CONST(1)
#define PMC_IMPL_PART_PCIEX4A_PWRDWN_REQ_CONTROL_0_REQ_PWRUP                    MK_ENUM_CONST(0)


// Register PMC_IMPL_PART_PCIEX4A_PWRDWN_ACK_STATUS_0
#define PMC_IMPL_PART_PCIEX4A_PWRDWN_ACK_STATUS_0                       MK_ADDR_CONST(0x640)
#define PMC_IMPL_PART_PCIEX4A_PWRDWN_ACK_STATUS_0_SECURE                        0x0
#define PMC_IMPL_PART_PCIEX4A_PWRDWN_ACK_STATUS_0_DUAL                  0x0
#define PMC_IMPL_PART_PCIEX4A_PWRDWN_ACK_STATUS_0_SCR                   PG_PCIEX4A_SCR_0
#define PMC_IMPL_PART_PCIEX4A_PWRDWN_ACK_STATUS_0_SCRREG                        PMC_IMPL_SCR_PG_PCIEX4A_SCR_0
#define PMC_IMPL_PART_PCIEX4A_PWRDWN_ACK_STATUS_0_WORD_COUNT                    0x1
#define PMC_IMPL_PART_PCIEX4A_PWRDWN_ACK_STATUS_0_RESET_VAL                     MK_MASK_CONST(0x7)
#define PMC_IMPL_PART_PCIEX4A_PWRDWN_ACK_STATUS_0_RESET_MASK                    MK_MASK_CONST(0x7)
#define PMC_IMPL_PART_PCIEX4A_PWRDWN_ACK_STATUS_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX4A_PWRDWN_ACK_STATUS_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX4A_PWRDWN_ACK_STATUS_0_READ_MASK                     MK_MASK_CONST(0x7)
#define PMC_IMPL_PART_PCIEX4A_PWRDWN_ACK_STATUS_0_WRITE_MASK                    MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX4A_PWRDWN_ACK_STATUS_0_CBB_ACK_SHIFT                 MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_PCIEX4A_PWRDWN_ACK_STATUS_0_CBB_ACK_FIELD                 MK_FIELD_CONST(0x1, PMC_IMPL_PART_PCIEX4A_PWRDWN_ACK_STATUS_0_CBB_ACK_SHIFT)
#define PMC_IMPL_PART_PCIEX4A_PWRDWN_ACK_STATUS_0_CBB_ACK_RANGE                 0:0
#define PMC_IMPL_PART_PCIEX4A_PWRDWN_ACK_STATUS_0_CBB_ACK_MSB                   MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_PCIEX4A_PWRDWN_ACK_STATUS_0_CBB_ACK_LSB                   MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_PCIEX4A_PWRDWN_ACK_STATUS_0_CBB_ACK_WOFFSET                       0x0
#define PMC_IMPL_PART_PCIEX4A_PWRDWN_ACK_STATUS_0_CBB_ACK_DEFAULT                       MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PCIEX4A_PWRDWN_ACK_STATUS_0_CBB_ACK_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PCIEX4A_PWRDWN_ACK_STATUS_0_CBB_ACK_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX4A_PWRDWN_ACK_STATUS_0_CBB_ACK_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX4A_PWRDWN_ACK_STATUS_0_CBB_ACK_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX4A_PWRDWN_ACK_STATUS_0_CBB_ACK_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PCIEX4A_PWRDWN_ACK_STATUS_0_CBB_ACK_INIT_ENUM                     PWRDWN
#define PMC_IMPL_PART_PCIEX4A_PWRDWN_ACK_STATUS_0_CBB_ACK_PWRDWN                        MK_ENUM_CONST(1)
#define PMC_IMPL_PART_PCIEX4A_PWRDWN_ACK_STATUS_0_CBB_ACK_PWRUP                 MK_ENUM_CONST(0)

#define PMC_IMPL_PART_PCIEX4A_PWRDWN_ACK_STATUS_0_DBB_ACK_SHIFT                 MK_SHIFT_CONST(1)
#define PMC_IMPL_PART_PCIEX4A_PWRDWN_ACK_STATUS_0_DBB_ACK_FIELD                 MK_FIELD_CONST(0x1, PMC_IMPL_PART_PCIEX4A_PWRDWN_ACK_STATUS_0_DBB_ACK_SHIFT)
#define PMC_IMPL_PART_PCIEX4A_PWRDWN_ACK_STATUS_0_DBB_ACK_RANGE                 1:1
#define PMC_IMPL_PART_PCIEX4A_PWRDWN_ACK_STATUS_0_DBB_ACK_MSB                   MK_SHIFT_CONST(1)
#define PMC_IMPL_PART_PCIEX4A_PWRDWN_ACK_STATUS_0_DBB_ACK_LSB                   MK_SHIFT_CONST(1)
#define PMC_IMPL_PART_PCIEX4A_PWRDWN_ACK_STATUS_0_DBB_ACK_WOFFSET                       0x0
#define PMC_IMPL_PART_PCIEX4A_PWRDWN_ACK_STATUS_0_DBB_ACK_DEFAULT                       MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PCIEX4A_PWRDWN_ACK_STATUS_0_DBB_ACK_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PCIEX4A_PWRDWN_ACK_STATUS_0_DBB_ACK_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX4A_PWRDWN_ACK_STATUS_0_DBB_ACK_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX4A_PWRDWN_ACK_STATUS_0_DBB_ACK_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX4A_PWRDWN_ACK_STATUS_0_DBB_ACK_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PCIEX4A_PWRDWN_ACK_STATUS_0_DBB_ACK_INIT_ENUM                     PWRDWN
#define PMC_IMPL_PART_PCIEX4A_PWRDWN_ACK_STATUS_0_DBB_ACK_PWRDWN                        MK_ENUM_CONST(1)
#define PMC_IMPL_PART_PCIEX4A_PWRDWN_ACK_STATUS_0_DBB_ACK_PWRUP                 MK_ENUM_CONST(0)

#define PMC_IMPL_PART_PCIEX4A_PWRDWN_ACK_STATUS_0_H1X_ACK_SHIFT                 MK_SHIFT_CONST(2)
#define PMC_IMPL_PART_PCIEX4A_PWRDWN_ACK_STATUS_0_H1X_ACK_FIELD                 MK_FIELD_CONST(0x1, PMC_IMPL_PART_PCIEX4A_PWRDWN_ACK_STATUS_0_H1X_ACK_SHIFT)
#define PMC_IMPL_PART_PCIEX4A_PWRDWN_ACK_STATUS_0_H1X_ACK_RANGE                 2:2
#define PMC_IMPL_PART_PCIEX4A_PWRDWN_ACK_STATUS_0_H1X_ACK_MSB                   MK_SHIFT_CONST(2)
#define PMC_IMPL_PART_PCIEX4A_PWRDWN_ACK_STATUS_0_H1X_ACK_LSB                   MK_SHIFT_CONST(2)
#define PMC_IMPL_PART_PCIEX4A_PWRDWN_ACK_STATUS_0_H1X_ACK_WOFFSET                       0x0
#define PMC_IMPL_PART_PCIEX4A_PWRDWN_ACK_STATUS_0_H1X_ACK_DEFAULT                       MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PCIEX4A_PWRDWN_ACK_STATUS_0_H1X_ACK_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PCIEX4A_PWRDWN_ACK_STATUS_0_H1X_ACK_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX4A_PWRDWN_ACK_STATUS_0_H1X_ACK_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX4A_PWRDWN_ACK_STATUS_0_H1X_ACK_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX4A_PWRDWN_ACK_STATUS_0_H1X_ACK_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PCIEX4A_PWRDWN_ACK_STATUS_0_H1X_ACK_INIT_ENUM                     PWRDWN
#define PMC_IMPL_PART_PCIEX4A_PWRDWN_ACK_STATUS_0_H1X_ACK_PWRDWN                        MK_ENUM_CONST(1)
#define PMC_IMPL_PART_PCIEX4A_PWRDWN_ACK_STATUS_0_H1X_ACK_PWRUP                 MK_ENUM_CONST(0)


// Register PMC_IMPL_PART_PCIEX4BA_PWRDWN_REQ_CONTROL_0
#define PMC_IMPL_PART_PCIEX4BA_PWRDWN_REQ_CONTROL_0                     MK_ADDR_CONST(0x644)
#define PMC_IMPL_PART_PCIEX4BA_PWRDWN_REQ_CONTROL_0_SECURE                      0x0
#define PMC_IMPL_PART_PCIEX4BA_PWRDWN_REQ_CONTROL_0_DUAL                        0x0
#define PMC_IMPL_PART_PCIEX4BA_PWRDWN_REQ_CONTROL_0_SCR                         PG_PCIEX4BA_SCR_0
#define PMC_IMPL_PART_PCIEX4BA_PWRDWN_REQ_CONTROL_0_SCRREG                      PMC_IMPL_SCR_PG_PCIEX4BA_SCR_0
#define PMC_IMPL_PART_PCIEX4BA_PWRDWN_REQ_CONTROL_0_WORD_COUNT                  0x1
#define PMC_IMPL_PART_PCIEX4BA_PWRDWN_REQ_CONTROL_0_RESET_VAL                   MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PCIEX4BA_PWRDWN_REQ_CONTROL_0_RESET_MASK                  MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PCIEX4BA_PWRDWN_REQ_CONTROL_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX4BA_PWRDWN_REQ_CONTROL_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX4BA_PWRDWN_REQ_CONTROL_0_READ_MASK                   MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PCIEX4BA_PWRDWN_REQ_CONTROL_0_WRITE_MASK                  MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PCIEX4BA_PWRDWN_REQ_CONTROL_0_REQ_SHIFT                   MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_PCIEX4BA_PWRDWN_REQ_CONTROL_0_REQ_FIELD                   MK_FIELD_CONST(0x1, PMC_IMPL_PART_PCIEX4BA_PWRDWN_REQ_CONTROL_0_REQ_SHIFT)
#define PMC_IMPL_PART_PCIEX4BA_PWRDWN_REQ_CONTROL_0_REQ_RANGE                   0:0
#define PMC_IMPL_PART_PCIEX4BA_PWRDWN_REQ_CONTROL_0_REQ_MSB                     MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_PCIEX4BA_PWRDWN_REQ_CONTROL_0_REQ_LSB                     MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_PCIEX4BA_PWRDWN_REQ_CONTROL_0_REQ_WOFFSET                 0x0
#define PMC_IMPL_PART_PCIEX4BA_PWRDWN_REQ_CONTROL_0_REQ_DEFAULT                 MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PCIEX4BA_PWRDWN_REQ_CONTROL_0_REQ_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PCIEX4BA_PWRDWN_REQ_CONTROL_0_REQ_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX4BA_PWRDWN_REQ_CONTROL_0_REQ_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX4BA_PWRDWN_REQ_CONTROL_0_REQ_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PCIEX4BA_PWRDWN_REQ_CONTROL_0_REQ_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PCIEX4BA_PWRDWN_REQ_CONTROL_0_REQ_INIT_ENUM                       PWRDWN
#define PMC_IMPL_PART_PCIEX4BA_PWRDWN_REQ_CONTROL_0_REQ_PWRDWN                  MK_ENUM_CONST(1)
#define PMC_IMPL_PART_PCIEX4BA_PWRDWN_REQ_CONTROL_0_REQ_PWRUP                   MK_ENUM_CONST(0)


// Register PMC_IMPL_PART_PCIEX4BA_PWRDWN_ACK_STATUS_0
#define PMC_IMPL_PART_PCIEX4BA_PWRDWN_ACK_STATUS_0                      MK_ADDR_CONST(0x648)
#define PMC_IMPL_PART_PCIEX4BA_PWRDWN_ACK_STATUS_0_SECURE                       0x0
#define PMC_IMPL_PART_PCIEX4BA_PWRDWN_ACK_STATUS_0_DUAL                         0x0
#define PMC_IMPL_PART_PCIEX4BA_PWRDWN_ACK_STATUS_0_SCR                  PG_PCIEX4BA_SCR_0
#define PMC_IMPL_PART_PCIEX4BA_PWRDWN_ACK_STATUS_0_SCRREG                       PMC_IMPL_SCR_PG_PCIEX4BA_SCR_0
#define PMC_IMPL_PART_PCIEX4BA_PWRDWN_ACK_STATUS_0_WORD_COUNT                   0x1
#define PMC_IMPL_PART_PCIEX4BA_PWRDWN_ACK_STATUS_0_RESET_VAL                    MK_MASK_CONST(0x7)
#define PMC_IMPL_PART_PCIEX4BA_PWRDWN_ACK_STATUS_0_RESET_MASK                   MK_MASK_CONST(0x7)
#define PMC_IMPL_PART_PCIEX4BA_PWRDWN_ACK_STATUS_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX4BA_PWRDWN_ACK_STATUS_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX4BA_PWRDWN_ACK_STATUS_0_READ_MASK                    MK_MASK_CONST(0x7)
#define PMC_IMPL_PART_PCIEX4BA_PWRDWN_ACK_STATUS_0_WRITE_MASK                   MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX4BA_PWRDWN_ACK_STATUS_0_CBB_ACK_SHIFT                        MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_PCIEX4BA_PWRDWN_ACK_STATUS_0_CBB_ACK_FIELD                        MK_FIELD_CONST(0x1, PMC_IMPL_PART_PCIEX4BA_PWRDWN_ACK_STATUS_0_CBB_ACK_SHIFT)
#define PMC_IMPL_PART_PCIEX4BA_PWRDWN_ACK_STATUS_0_CBB_ACK_RANGE                        0:0
#define PMC_IMPL_PART_PCIEX4BA_PWRDWN_ACK_STATUS_0_CBB_ACK_MSB                  MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_PCIEX4BA_PWRDWN_ACK_STATUS_0_CBB_ACK_LSB                  MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_PCIEX4BA_PWRDWN_ACK_STATUS_0_CBB_ACK_WOFFSET                      0x0
#define PMC_IMPL_PART_PCIEX4BA_PWRDWN_ACK_STATUS_0_CBB_ACK_DEFAULT                      MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PCIEX4BA_PWRDWN_ACK_STATUS_0_CBB_ACK_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PCIEX4BA_PWRDWN_ACK_STATUS_0_CBB_ACK_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX4BA_PWRDWN_ACK_STATUS_0_CBB_ACK_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX4BA_PWRDWN_ACK_STATUS_0_CBB_ACK_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX4BA_PWRDWN_ACK_STATUS_0_CBB_ACK_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PCIEX4BA_PWRDWN_ACK_STATUS_0_CBB_ACK_INIT_ENUM                    PWRDWN
#define PMC_IMPL_PART_PCIEX4BA_PWRDWN_ACK_STATUS_0_CBB_ACK_PWRDWN                       MK_ENUM_CONST(1)
#define PMC_IMPL_PART_PCIEX4BA_PWRDWN_ACK_STATUS_0_CBB_ACK_PWRUP                        MK_ENUM_CONST(0)

#define PMC_IMPL_PART_PCIEX4BA_PWRDWN_ACK_STATUS_0_DBB_ACK_SHIFT                        MK_SHIFT_CONST(1)
#define PMC_IMPL_PART_PCIEX4BA_PWRDWN_ACK_STATUS_0_DBB_ACK_FIELD                        MK_FIELD_CONST(0x1, PMC_IMPL_PART_PCIEX4BA_PWRDWN_ACK_STATUS_0_DBB_ACK_SHIFT)
#define PMC_IMPL_PART_PCIEX4BA_PWRDWN_ACK_STATUS_0_DBB_ACK_RANGE                        1:1
#define PMC_IMPL_PART_PCIEX4BA_PWRDWN_ACK_STATUS_0_DBB_ACK_MSB                  MK_SHIFT_CONST(1)
#define PMC_IMPL_PART_PCIEX4BA_PWRDWN_ACK_STATUS_0_DBB_ACK_LSB                  MK_SHIFT_CONST(1)
#define PMC_IMPL_PART_PCIEX4BA_PWRDWN_ACK_STATUS_0_DBB_ACK_WOFFSET                      0x0
#define PMC_IMPL_PART_PCIEX4BA_PWRDWN_ACK_STATUS_0_DBB_ACK_DEFAULT                      MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PCIEX4BA_PWRDWN_ACK_STATUS_0_DBB_ACK_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PCIEX4BA_PWRDWN_ACK_STATUS_0_DBB_ACK_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX4BA_PWRDWN_ACK_STATUS_0_DBB_ACK_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX4BA_PWRDWN_ACK_STATUS_0_DBB_ACK_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX4BA_PWRDWN_ACK_STATUS_0_DBB_ACK_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PCIEX4BA_PWRDWN_ACK_STATUS_0_DBB_ACK_INIT_ENUM                    PWRDWN
#define PMC_IMPL_PART_PCIEX4BA_PWRDWN_ACK_STATUS_0_DBB_ACK_PWRDWN                       MK_ENUM_CONST(1)
#define PMC_IMPL_PART_PCIEX4BA_PWRDWN_ACK_STATUS_0_DBB_ACK_PWRUP                        MK_ENUM_CONST(0)

#define PMC_IMPL_PART_PCIEX4BA_PWRDWN_ACK_STATUS_0_H1X_ACK_SHIFT                        MK_SHIFT_CONST(2)
#define PMC_IMPL_PART_PCIEX4BA_PWRDWN_ACK_STATUS_0_H1X_ACK_FIELD                        MK_FIELD_CONST(0x1, PMC_IMPL_PART_PCIEX4BA_PWRDWN_ACK_STATUS_0_H1X_ACK_SHIFT)
#define PMC_IMPL_PART_PCIEX4BA_PWRDWN_ACK_STATUS_0_H1X_ACK_RANGE                        2:2
#define PMC_IMPL_PART_PCIEX4BA_PWRDWN_ACK_STATUS_0_H1X_ACK_MSB                  MK_SHIFT_CONST(2)
#define PMC_IMPL_PART_PCIEX4BA_PWRDWN_ACK_STATUS_0_H1X_ACK_LSB                  MK_SHIFT_CONST(2)
#define PMC_IMPL_PART_PCIEX4BA_PWRDWN_ACK_STATUS_0_H1X_ACK_WOFFSET                      0x0
#define PMC_IMPL_PART_PCIEX4BA_PWRDWN_ACK_STATUS_0_H1X_ACK_DEFAULT                      MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PCIEX4BA_PWRDWN_ACK_STATUS_0_H1X_ACK_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PCIEX4BA_PWRDWN_ACK_STATUS_0_H1X_ACK_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX4BA_PWRDWN_ACK_STATUS_0_H1X_ACK_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX4BA_PWRDWN_ACK_STATUS_0_H1X_ACK_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX4BA_PWRDWN_ACK_STATUS_0_H1X_ACK_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PCIEX4BA_PWRDWN_ACK_STATUS_0_H1X_ACK_INIT_ENUM                    PWRDWN
#define PMC_IMPL_PART_PCIEX4BA_PWRDWN_ACK_STATUS_0_H1X_ACK_PWRDWN                       MK_ENUM_CONST(1)
#define PMC_IMPL_PART_PCIEX4BA_PWRDWN_ACK_STATUS_0_H1X_ACK_PWRUP                        MK_ENUM_CONST(0)


// Register PMC_IMPL_PART_PCIEX4BB_PWRDWN_REQ_CONTROL_0
#define PMC_IMPL_PART_PCIEX4BB_PWRDWN_REQ_CONTROL_0                     MK_ADDR_CONST(0x64c)
#define PMC_IMPL_PART_PCIEX4BB_PWRDWN_REQ_CONTROL_0_SECURE                      0x0
#define PMC_IMPL_PART_PCIEX4BB_PWRDWN_REQ_CONTROL_0_DUAL                        0x0
#define PMC_IMPL_PART_PCIEX4BB_PWRDWN_REQ_CONTROL_0_SCR                         PG_PCIEX4BB_SCR_0
#define PMC_IMPL_PART_PCIEX4BB_PWRDWN_REQ_CONTROL_0_SCRREG                      PMC_IMPL_SCR_PG_PCIEX4BB_SCR_0
#define PMC_IMPL_PART_PCIEX4BB_PWRDWN_REQ_CONTROL_0_WORD_COUNT                  0x1
#define PMC_IMPL_PART_PCIEX4BB_PWRDWN_REQ_CONTROL_0_RESET_VAL                   MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PCIEX4BB_PWRDWN_REQ_CONTROL_0_RESET_MASK                  MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PCIEX4BB_PWRDWN_REQ_CONTROL_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX4BB_PWRDWN_REQ_CONTROL_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX4BB_PWRDWN_REQ_CONTROL_0_READ_MASK                   MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PCIEX4BB_PWRDWN_REQ_CONTROL_0_WRITE_MASK                  MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PCIEX4BB_PWRDWN_REQ_CONTROL_0_REQ_SHIFT                   MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_PCIEX4BB_PWRDWN_REQ_CONTROL_0_REQ_FIELD                   MK_FIELD_CONST(0x1, PMC_IMPL_PART_PCIEX4BB_PWRDWN_REQ_CONTROL_0_REQ_SHIFT)
#define PMC_IMPL_PART_PCIEX4BB_PWRDWN_REQ_CONTROL_0_REQ_RANGE                   0:0
#define PMC_IMPL_PART_PCIEX4BB_PWRDWN_REQ_CONTROL_0_REQ_MSB                     MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_PCIEX4BB_PWRDWN_REQ_CONTROL_0_REQ_LSB                     MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_PCIEX4BB_PWRDWN_REQ_CONTROL_0_REQ_WOFFSET                 0x0
#define PMC_IMPL_PART_PCIEX4BB_PWRDWN_REQ_CONTROL_0_REQ_DEFAULT                 MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PCIEX4BB_PWRDWN_REQ_CONTROL_0_REQ_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PCIEX4BB_PWRDWN_REQ_CONTROL_0_REQ_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX4BB_PWRDWN_REQ_CONTROL_0_REQ_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX4BB_PWRDWN_REQ_CONTROL_0_REQ_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PCIEX4BB_PWRDWN_REQ_CONTROL_0_REQ_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PCIEX4BB_PWRDWN_REQ_CONTROL_0_REQ_INIT_ENUM                       PWRDWN
#define PMC_IMPL_PART_PCIEX4BB_PWRDWN_REQ_CONTROL_0_REQ_PWRDWN                  MK_ENUM_CONST(1)
#define PMC_IMPL_PART_PCIEX4BB_PWRDWN_REQ_CONTROL_0_REQ_PWRUP                   MK_ENUM_CONST(0)


// Register PMC_IMPL_PART_PCIEX4BB_PWRDWN_ACK_STATUS_0
#define PMC_IMPL_PART_PCIEX4BB_PWRDWN_ACK_STATUS_0                      MK_ADDR_CONST(0x650)
#define PMC_IMPL_PART_PCIEX4BB_PWRDWN_ACK_STATUS_0_SECURE                       0x0
#define PMC_IMPL_PART_PCIEX4BB_PWRDWN_ACK_STATUS_0_DUAL                         0x0
#define PMC_IMPL_PART_PCIEX4BB_PWRDWN_ACK_STATUS_0_SCR                  PG_PCIEX4BB_SCR_0
#define PMC_IMPL_PART_PCIEX4BB_PWRDWN_ACK_STATUS_0_SCRREG                       PMC_IMPL_SCR_PG_PCIEX4BB_SCR_0
#define PMC_IMPL_PART_PCIEX4BB_PWRDWN_ACK_STATUS_0_WORD_COUNT                   0x1
#define PMC_IMPL_PART_PCIEX4BB_PWRDWN_ACK_STATUS_0_RESET_VAL                    MK_MASK_CONST(0x7)
#define PMC_IMPL_PART_PCIEX4BB_PWRDWN_ACK_STATUS_0_RESET_MASK                   MK_MASK_CONST(0x7)
#define PMC_IMPL_PART_PCIEX4BB_PWRDWN_ACK_STATUS_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX4BB_PWRDWN_ACK_STATUS_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX4BB_PWRDWN_ACK_STATUS_0_READ_MASK                    MK_MASK_CONST(0x7)
#define PMC_IMPL_PART_PCIEX4BB_PWRDWN_ACK_STATUS_0_WRITE_MASK                   MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX4BB_PWRDWN_ACK_STATUS_0_CBB_ACK_SHIFT                        MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_PCIEX4BB_PWRDWN_ACK_STATUS_0_CBB_ACK_FIELD                        MK_FIELD_CONST(0x1, PMC_IMPL_PART_PCIEX4BB_PWRDWN_ACK_STATUS_0_CBB_ACK_SHIFT)
#define PMC_IMPL_PART_PCIEX4BB_PWRDWN_ACK_STATUS_0_CBB_ACK_RANGE                        0:0
#define PMC_IMPL_PART_PCIEX4BB_PWRDWN_ACK_STATUS_0_CBB_ACK_MSB                  MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_PCIEX4BB_PWRDWN_ACK_STATUS_0_CBB_ACK_LSB                  MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_PCIEX4BB_PWRDWN_ACK_STATUS_0_CBB_ACK_WOFFSET                      0x0
#define PMC_IMPL_PART_PCIEX4BB_PWRDWN_ACK_STATUS_0_CBB_ACK_DEFAULT                      MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PCIEX4BB_PWRDWN_ACK_STATUS_0_CBB_ACK_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PCIEX4BB_PWRDWN_ACK_STATUS_0_CBB_ACK_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX4BB_PWRDWN_ACK_STATUS_0_CBB_ACK_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX4BB_PWRDWN_ACK_STATUS_0_CBB_ACK_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX4BB_PWRDWN_ACK_STATUS_0_CBB_ACK_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PCIEX4BB_PWRDWN_ACK_STATUS_0_CBB_ACK_INIT_ENUM                    PWRDWN
#define PMC_IMPL_PART_PCIEX4BB_PWRDWN_ACK_STATUS_0_CBB_ACK_PWRDWN                       MK_ENUM_CONST(1)
#define PMC_IMPL_PART_PCIEX4BB_PWRDWN_ACK_STATUS_0_CBB_ACK_PWRUP                        MK_ENUM_CONST(0)

#define PMC_IMPL_PART_PCIEX4BB_PWRDWN_ACK_STATUS_0_DBB_ACK_SHIFT                        MK_SHIFT_CONST(1)
#define PMC_IMPL_PART_PCIEX4BB_PWRDWN_ACK_STATUS_0_DBB_ACK_FIELD                        MK_FIELD_CONST(0x1, PMC_IMPL_PART_PCIEX4BB_PWRDWN_ACK_STATUS_0_DBB_ACK_SHIFT)
#define PMC_IMPL_PART_PCIEX4BB_PWRDWN_ACK_STATUS_0_DBB_ACK_RANGE                        1:1
#define PMC_IMPL_PART_PCIEX4BB_PWRDWN_ACK_STATUS_0_DBB_ACK_MSB                  MK_SHIFT_CONST(1)
#define PMC_IMPL_PART_PCIEX4BB_PWRDWN_ACK_STATUS_0_DBB_ACK_LSB                  MK_SHIFT_CONST(1)
#define PMC_IMPL_PART_PCIEX4BB_PWRDWN_ACK_STATUS_0_DBB_ACK_WOFFSET                      0x0
#define PMC_IMPL_PART_PCIEX4BB_PWRDWN_ACK_STATUS_0_DBB_ACK_DEFAULT                      MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PCIEX4BB_PWRDWN_ACK_STATUS_0_DBB_ACK_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PCIEX4BB_PWRDWN_ACK_STATUS_0_DBB_ACK_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX4BB_PWRDWN_ACK_STATUS_0_DBB_ACK_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX4BB_PWRDWN_ACK_STATUS_0_DBB_ACK_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX4BB_PWRDWN_ACK_STATUS_0_DBB_ACK_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PCIEX4BB_PWRDWN_ACK_STATUS_0_DBB_ACK_INIT_ENUM                    PWRDWN
#define PMC_IMPL_PART_PCIEX4BB_PWRDWN_ACK_STATUS_0_DBB_ACK_PWRDWN                       MK_ENUM_CONST(1)
#define PMC_IMPL_PART_PCIEX4BB_PWRDWN_ACK_STATUS_0_DBB_ACK_PWRUP                        MK_ENUM_CONST(0)

#define PMC_IMPL_PART_PCIEX4BB_PWRDWN_ACK_STATUS_0_H1X_ACK_SHIFT                        MK_SHIFT_CONST(2)
#define PMC_IMPL_PART_PCIEX4BB_PWRDWN_ACK_STATUS_0_H1X_ACK_FIELD                        MK_FIELD_CONST(0x1, PMC_IMPL_PART_PCIEX4BB_PWRDWN_ACK_STATUS_0_H1X_ACK_SHIFT)
#define PMC_IMPL_PART_PCIEX4BB_PWRDWN_ACK_STATUS_0_H1X_ACK_RANGE                        2:2
#define PMC_IMPL_PART_PCIEX4BB_PWRDWN_ACK_STATUS_0_H1X_ACK_MSB                  MK_SHIFT_CONST(2)
#define PMC_IMPL_PART_PCIEX4BB_PWRDWN_ACK_STATUS_0_H1X_ACK_LSB                  MK_SHIFT_CONST(2)
#define PMC_IMPL_PART_PCIEX4BB_PWRDWN_ACK_STATUS_0_H1X_ACK_WOFFSET                      0x0
#define PMC_IMPL_PART_PCIEX4BB_PWRDWN_ACK_STATUS_0_H1X_ACK_DEFAULT                      MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PCIEX4BB_PWRDWN_ACK_STATUS_0_H1X_ACK_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PCIEX4BB_PWRDWN_ACK_STATUS_0_H1X_ACK_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX4BB_PWRDWN_ACK_STATUS_0_H1X_ACK_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX4BB_PWRDWN_ACK_STATUS_0_H1X_ACK_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX4BB_PWRDWN_ACK_STATUS_0_H1X_ACK_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PCIEX4BB_PWRDWN_ACK_STATUS_0_H1X_ACK_INIT_ENUM                    PWRDWN
#define PMC_IMPL_PART_PCIEX4BB_PWRDWN_ACK_STATUS_0_H1X_ACK_PWRDWN                       MK_ENUM_CONST(1)
#define PMC_IMPL_PART_PCIEX4BB_PWRDWN_ACK_STATUS_0_H1X_ACK_PWRUP                        MK_ENUM_CONST(0)


// Register PMC_IMPL_PART_PCIEX4CA_PWRDWN_REQ_CONTROL_0
#define PMC_IMPL_PART_PCIEX4CA_PWRDWN_REQ_CONTROL_0                     MK_ADDR_CONST(0x654)
#define PMC_IMPL_PART_PCIEX4CA_PWRDWN_REQ_CONTROL_0_SECURE                      0x0
#define PMC_IMPL_PART_PCIEX4CA_PWRDWN_REQ_CONTROL_0_DUAL                        0x0
#define PMC_IMPL_PART_PCIEX4CA_PWRDWN_REQ_CONTROL_0_SCR                         PG_PCIEX4CA_SCR_0
#define PMC_IMPL_PART_PCIEX4CA_PWRDWN_REQ_CONTROL_0_SCRREG                      PMC_IMPL_SCR_PG_PCIEX4CA_SCR_0
#define PMC_IMPL_PART_PCIEX4CA_PWRDWN_REQ_CONTROL_0_WORD_COUNT                  0x1
#define PMC_IMPL_PART_PCIEX4CA_PWRDWN_REQ_CONTROL_0_RESET_VAL                   MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PCIEX4CA_PWRDWN_REQ_CONTROL_0_RESET_MASK                  MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PCIEX4CA_PWRDWN_REQ_CONTROL_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX4CA_PWRDWN_REQ_CONTROL_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX4CA_PWRDWN_REQ_CONTROL_0_READ_MASK                   MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PCIEX4CA_PWRDWN_REQ_CONTROL_0_WRITE_MASK                  MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PCIEX4CA_PWRDWN_REQ_CONTROL_0_REQ_SHIFT                   MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_PCIEX4CA_PWRDWN_REQ_CONTROL_0_REQ_FIELD                   MK_FIELD_CONST(0x1, PMC_IMPL_PART_PCIEX4CA_PWRDWN_REQ_CONTROL_0_REQ_SHIFT)
#define PMC_IMPL_PART_PCIEX4CA_PWRDWN_REQ_CONTROL_0_REQ_RANGE                   0:0
#define PMC_IMPL_PART_PCIEX4CA_PWRDWN_REQ_CONTROL_0_REQ_MSB                     MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_PCIEX4CA_PWRDWN_REQ_CONTROL_0_REQ_LSB                     MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_PCIEX4CA_PWRDWN_REQ_CONTROL_0_REQ_WOFFSET                 0x0
#define PMC_IMPL_PART_PCIEX4CA_PWRDWN_REQ_CONTROL_0_REQ_DEFAULT                 MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PCIEX4CA_PWRDWN_REQ_CONTROL_0_REQ_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PCIEX4CA_PWRDWN_REQ_CONTROL_0_REQ_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX4CA_PWRDWN_REQ_CONTROL_0_REQ_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX4CA_PWRDWN_REQ_CONTROL_0_REQ_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PCIEX4CA_PWRDWN_REQ_CONTROL_0_REQ_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PCIEX4CA_PWRDWN_REQ_CONTROL_0_REQ_INIT_ENUM                       PWRDWN
#define PMC_IMPL_PART_PCIEX4CA_PWRDWN_REQ_CONTROL_0_REQ_PWRDWN                  MK_ENUM_CONST(1)
#define PMC_IMPL_PART_PCIEX4CA_PWRDWN_REQ_CONTROL_0_REQ_PWRUP                   MK_ENUM_CONST(0)


// Register PMC_IMPL_PART_PCIEX4CA_PWRDWN_ACK_STATUS_0
#define PMC_IMPL_PART_PCIEX4CA_PWRDWN_ACK_STATUS_0                      MK_ADDR_CONST(0x658)
#define PMC_IMPL_PART_PCIEX4CA_PWRDWN_ACK_STATUS_0_SECURE                       0x0
#define PMC_IMPL_PART_PCIEX4CA_PWRDWN_ACK_STATUS_0_DUAL                         0x0
#define PMC_IMPL_PART_PCIEX4CA_PWRDWN_ACK_STATUS_0_SCR                  PG_PCIEX4CA_SCR_0
#define PMC_IMPL_PART_PCIEX4CA_PWRDWN_ACK_STATUS_0_SCRREG                       PMC_IMPL_SCR_PG_PCIEX4CA_SCR_0
#define PMC_IMPL_PART_PCIEX4CA_PWRDWN_ACK_STATUS_0_WORD_COUNT                   0x1
#define PMC_IMPL_PART_PCIEX4CA_PWRDWN_ACK_STATUS_0_RESET_VAL                    MK_MASK_CONST(0x7)
#define PMC_IMPL_PART_PCIEX4CA_PWRDWN_ACK_STATUS_0_RESET_MASK                   MK_MASK_CONST(0x7)
#define PMC_IMPL_PART_PCIEX4CA_PWRDWN_ACK_STATUS_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX4CA_PWRDWN_ACK_STATUS_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX4CA_PWRDWN_ACK_STATUS_0_READ_MASK                    MK_MASK_CONST(0x7)
#define PMC_IMPL_PART_PCIEX4CA_PWRDWN_ACK_STATUS_0_WRITE_MASK                   MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX4CA_PWRDWN_ACK_STATUS_0_CBB_ACK_SHIFT                        MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_PCIEX4CA_PWRDWN_ACK_STATUS_0_CBB_ACK_FIELD                        MK_FIELD_CONST(0x1, PMC_IMPL_PART_PCIEX4CA_PWRDWN_ACK_STATUS_0_CBB_ACK_SHIFT)
#define PMC_IMPL_PART_PCIEX4CA_PWRDWN_ACK_STATUS_0_CBB_ACK_RANGE                        0:0
#define PMC_IMPL_PART_PCIEX4CA_PWRDWN_ACK_STATUS_0_CBB_ACK_MSB                  MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_PCIEX4CA_PWRDWN_ACK_STATUS_0_CBB_ACK_LSB                  MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_PCIEX4CA_PWRDWN_ACK_STATUS_0_CBB_ACK_WOFFSET                      0x0
#define PMC_IMPL_PART_PCIEX4CA_PWRDWN_ACK_STATUS_0_CBB_ACK_DEFAULT                      MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PCIEX4CA_PWRDWN_ACK_STATUS_0_CBB_ACK_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PCIEX4CA_PWRDWN_ACK_STATUS_0_CBB_ACK_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX4CA_PWRDWN_ACK_STATUS_0_CBB_ACK_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX4CA_PWRDWN_ACK_STATUS_0_CBB_ACK_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX4CA_PWRDWN_ACK_STATUS_0_CBB_ACK_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PCIEX4CA_PWRDWN_ACK_STATUS_0_CBB_ACK_INIT_ENUM                    PWRDWN
#define PMC_IMPL_PART_PCIEX4CA_PWRDWN_ACK_STATUS_0_CBB_ACK_PWRDWN                       MK_ENUM_CONST(1)
#define PMC_IMPL_PART_PCIEX4CA_PWRDWN_ACK_STATUS_0_CBB_ACK_PWRUP                        MK_ENUM_CONST(0)

#define PMC_IMPL_PART_PCIEX4CA_PWRDWN_ACK_STATUS_0_DBB_ACK_SHIFT                        MK_SHIFT_CONST(1)
#define PMC_IMPL_PART_PCIEX4CA_PWRDWN_ACK_STATUS_0_DBB_ACK_FIELD                        MK_FIELD_CONST(0x1, PMC_IMPL_PART_PCIEX4CA_PWRDWN_ACK_STATUS_0_DBB_ACK_SHIFT)
#define PMC_IMPL_PART_PCIEX4CA_PWRDWN_ACK_STATUS_0_DBB_ACK_RANGE                        1:1
#define PMC_IMPL_PART_PCIEX4CA_PWRDWN_ACK_STATUS_0_DBB_ACK_MSB                  MK_SHIFT_CONST(1)
#define PMC_IMPL_PART_PCIEX4CA_PWRDWN_ACK_STATUS_0_DBB_ACK_LSB                  MK_SHIFT_CONST(1)
#define PMC_IMPL_PART_PCIEX4CA_PWRDWN_ACK_STATUS_0_DBB_ACK_WOFFSET                      0x0
#define PMC_IMPL_PART_PCIEX4CA_PWRDWN_ACK_STATUS_0_DBB_ACK_DEFAULT                      MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PCIEX4CA_PWRDWN_ACK_STATUS_0_DBB_ACK_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PCIEX4CA_PWRDWN_ACK_STATUS_0_DBB_ACK_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX4CA_PWRDWN_ACK_STATUS_0_DBB_ACK_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX4CA_PWRDWN_ACK_STATUS_0_DBB_ACK_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX4CA_PWRDWN_ACK_STATUS_0_DBB_ACK_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PCIEX4CA_PWRDWN_ACK_STATUS_0_DBB_ACK_INIT_ENUM                    PWRDWN
#define PMC_IMPL_PART_PCIEX4CA_PWRDWN_ACK_STATUS_0_DBB_ACK_PWRDWN                       MK_ENUM_CONST(1)
#define PMC_IMPL_PART_PCIEX4CA_PWRDWN_ACK_STATUS_0_DBB_ACK_PWRUP                        MK_ENUM_CONST(0)

#define PMC_IMPL_PART_PCIEX4CA_PWRDWN_ACK_STATUS_0_H1X_ACK_SHIFT                        MK_SHIFT_CONST(2)
#define PMC_IMPL_PART_PCIEX4CA_PWRDWN_ACK_STATUS_0_H1X_ACK_FIELD                        MK_FIELD_CONST(0x1, PMC_IMPL_PART_PCIEX4CA_PWRDWN_ACK_STATUS_0_H1X_ACK_SHIFT)
#define PMC_IMPL_PART_PCIEX4CA_PWRDWN_ACK_STATUS_0_H1X_ACK_RANGE                        2:2
#define PMC_IMPL_PART_PCIEX4CA_PWRDWN_ACK_STATUS_0_H1X_ACK_MSB                  MK_SHIFT_CONST(2)
#define PMC_IMPL_PART_PCIEX4CA_PWRDWN_ACK_STATUS_0_H1X_ACK_LSB                  MK_SHIFT_CONST(2)
#define PMC_IMPL_PART_PCIEX4CA_PWRDWN_ACK_STATUS_0_H1X_ACK_WOFFSET                      0x0
#define PMC_IMPL_PART_PCIEX4CA_PWRDWN_ACK_STATUS_0_H1X_ACK_DEFAULT                      MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PCIEX4CA_PWRDWN_ACK_STATUS_0_H1X_ACK_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PCIEX4CA_PWRDWN_ACK_STATUS_0_H1X_ACK_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX4CA_PWRDWN_ACK_STATUS_0_H1X_ACK_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX4CA_PWRDWN_ACK_STATUS_0_H1X_ACK_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX4CA_PWRDWN_ACK_STATUS_0_H1X_ACK_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PCIEX4CA_PWRDWN_ACK_STATUS_0_H1X_ACK_INIT_ENUM                    PWRDWN
#define PMC_IMPL_PART_PCIEX4CA_PWRDWN_ACK_STATUS_0_H1X_ACK_PWRDWN                       MK_ENUM_CONST(1)
#define PMC_IMPL_PART_PCIEX4CA_PWRDWN_ACK_STATUS_0_H1X_ACK_PWRUP                        MK_ENUM_CONST(0)


// Register PMC_IMPL_PART_PCIEX4CB_PWRDWN_REQ_CONTROL_0
#define PMC_IMPL_PART_PCIEX4CB_PWRDWN_REQ_CONTROL_0                     MK_ADDR_CONST(0x65c)
#define PMC_IMPL_PART_PCIEX4CB_PWRDWN_REQ_CONTROL_0_SECURE                      0x0
#define PMC_IMPL_PART_PCIEX4CB_PWRDWN_REQ_CONTROL_0_DUAL                        0x0
#define PMC_IMPL_PART_PCIEX4CB_PWRDWN_REQ_CONTROL_0_SCR                         PG_PCIEX4CB_SCR_0
#define PMC_IMPL_PART_PCIEX4CB_PWRDWN_REQ_CONTROL_0_SCRREG                      PMC_IMPL_SCR_PG_PCIEX4CB_SCR_0
#define PMC_IMPL_PART_PCIEX4CB_PWRDWN_REQ_CONTROL_0_WORD_COUNT                  0x1
#define PMC_IMPL_PART_PCIEX4CB_PWRDWN_REQ_CONTROL_0_RESET_VAL                   MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PCIEX4CB_PWRDWN_REQ_CONTROL_0_RESET_MASK                  MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PCIEX4CB_PWRDWN_REQ_CONTROL_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX4CB_PWRDWN_REQ_CONTROL_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX4CB_PWRDWN_REQ_CONTROL_0_READ_MASK                   MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PCIEX4CB_PWRDWN_REQ_CONTROL_0_WRITE_MASK                  MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PCIEX4CB_PWRDWN_REQ_CONTROL_0_REQ_SHIFT                   MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_PCIEX4CB_PWRDWN_REQ_CONTROL_0_REQ_FIELD                   MK_FIELD_CONST(0x1, PMC_IMPL_PART_PCIEX4CB_PWRDWN_REQ_CONTROL_0_REQ_SHIFT)
#define PMC_IMPL_PART_PCIEX4CB_PWRDWN_REQ_CONTROL_0_REQ_RANGE                   0:0
#define PMC_IMPL_PART_PCIEX4CB_PWRDWN_REQ_CONTROL_0_REQ_MSB                     MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_PCIEX4CB_PWRDWN_REQ_CONTROL_0_REQ_LSB                     MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_PCIEX4CB_PWRDWN_REQ_CONTROL_0_REQ_WOFFSET                 0x0
#define PMC_IMPL_PART_PCIEX4CB_PWRDWN_REQ_CONTROL_0_REQ_DEFAULT                 MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PCIEX4CB_PWRDWN_REQ_CONTROL_0_REQ_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PCIEX4CB_PWRDWN_REQ_CONTROL_0_REQ_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX4CB_PWRDWN_REQ_CONTROL_0_REQ_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX4CB_PWRDWN_REQ_CONTROL_0_REQ_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PCIEX4CB_PWRDWN_REQ_CONTROL_0_REQ_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PCIEX4CB_PWRDWN_REQ_CONTROL_0_REQ_INIT_ENUM                       PWRDWN
#define PMC_IMPL_PART_PCIEX4CB_PWRDWN_REQ_CONTROL_0_REQ_PWRDWN                  MK_ENUM_CONST(1)
#define PMC_IMPL_PART_PCIEX4CB_PWRDWN_REQ_CONTROL_0_REQ_PWRUP                   MK_ENUM_CONST(0)


// Register PMC_IMPL_PART_PCIEX4CB_PWRDWN_ACK_STATUS_0
#define PMC_IMPL_PART_PCIEX4CB_PWRDWN_ACK_STATUS_0                      MK_ADDR_CONST(0x660)
#define PMC_IMPL_PART_PCIEX4CB_PWRDWN_ACK_STATUS_0_SECURE                       0x0
#define PMC_IMPL_PART_PCIEX4CB_PWRDWN_ACK_STATUS_0_DUAL                         0x0
#define PMC_IMPL_PART_PCIEX4CB_PWRDWN_ACK_STATUS_0_SCR                  PG_PCIEX4CB_SCR_0
#define PMC_IMPL_PART_PCIEX4CB_PWRDWN_ACK_STATUS_0_SCRREG                       PMC_IMPL_SCR_PG_PCIEX4CB_SCR_0
#define PMC_IMPL_PART_PCIEX4CB_PWRDWN_ACK_STATUS_0_WORD_COUNT                   0x1
#define PMC_IMPL_PART_PCIEX4CB_PWRDWN_ACK_STATUS_0_RESET_VAL                    MK_MASK_CONST(0x7)
#define PMC_IMPL_PART_PCIEX4CB_PWRDWN_ACK_STATUS_0_RESET_MASK                   MK_MASK_CONST(0x7)
#define PMC_IMPL_PART_PCIEX4CB_PWRDWN_ACK_STATUS_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX4CB_PWRDWN_ACK_STATUS_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX4CB_PWRDWN_ACK_STATUS_0_READ_MASK                    MK_MASK_CONST(0x7)
#define PMC_IMPL_PART_PCIEX4CB_PWRDWN_ACK_STATUS_0_WRITE_MASK                   MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX4CB_PWRDWN_ACK_STATUS_0_CBB_ACK_SHIFT                        MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_PCIEX4CB_PWRDWN_ACK_STATUS_0_CBB_ACK_FIELD                        MK_FIELD_CONST(0x1, PMC_IMPL_PART_PCIEX4CB_PWRDWN_ACK_STATUS_0_CBB_ACK_SHIFT)
#define PMC_IMPL_PART_PCIEX4CB_PWRDWN_ACK_STATUS_0_CBB_ACK_RANGE                        0:0
#define PMC_IMPL_PART_PCIEX4CB_PWRDWN_ACK_STATUS_0_CBB_ACK_MSB                  MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_PCIEX4CB_PWRDWN_ACK_STATUS_0_CBB_ACK_LSB                  MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_PCIEX4CB_PWRDWN_ACK_STATUS_0_CBB_ACK_WOFFSET                      0x0
#define PMC_IMPL_PART_PCIEX4CB_PWRDWN_ACK_STATUS_0_CBB_ACK_DEFAULT                      MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PCIEX4CB_PWRDWN_ACK_STATUS_0_CBB_ACK_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PCIEX4CB_PWRDWN_ACK_STATUS_0_CBB_ACK_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX4CB_PWRDWN_ACK_STATUS_0_CBB_ACK_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX4CB_PWRDWN_ACK_STATUS_0_CBB_ACK_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX4CB_PWRDWN_ACK_STATUS_0_CBB_ACK_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PCIEX4CB_PWRDWN_ACK_STATUS_0_CBB_ACK_INIT_ENUM                    PWRDWN
#define PMC_IMPL_PART_PCIEX4CB_PWRDWN_ACK_STATUS_0_CBB_ACK_PWRDWN                       MK_ENUM_CONST(1)
#define PMC_IMPL_PART_PCIEX4CB_PWRDWN_ACK_STATUS_0_CBB_ACK_PWRUP                        MK_ENUM_CONST(0)

#define PMC_IMPL_PART_PCIEX4CB_PWRDWN_ACK_STATUS_0_DBB_ACK_SHIFT                        MK_SHIFT_CONST(1)
#define PMC_IMPL_PART_PCIEX4CB_PWRDWN_ACK_STATUS_0_DBB_ACK_FIELD                        MK_FIELD_CONST(0x1, PMC_IMPL_PART_PCIEX4CB_PWRDWN_ACK_STATUS_0_DBB_ACK_SHIFT)
#define PMC_IMPL_PART_PCIEX4CB_PWRDWN_ACK_STATUS_0_DBB_ACK_RANGE                        1:1
#define PMC_IMPL_PART_PCIEX4CB_PWRDWN_ACK_STATUS_0_DBB_ACK_MSB                  MK_SHIFT_CONST(1)
#define PMC_IMPL_PART_PCIEX4CB_PWRDWN_ACK_STATUS_0_DBB_ACK_LSB                  MK_SHIFT_CONST(1)
#define PMC_IMPL_PART_PCIEX4CB_PWRDWN_ACK_STATUS_0_DBB_ACK_WOFFSET                      0x0
#define PMC_IMPL_PART_PCIEX4CB_PWRDWN_ACK_STATUS_0_DBB_ACK_DEFAULT                      MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PCIEX4CB_PWRDWN_ACK_STATUS_0_DBB_ACK_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PCIEX4CB_PWRDWN_ACK_STATUS_0_DBB_ACK_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX4CB_PWRDWN_ACK_STATUS_0_DBB_ACK_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX4CB_PWRDWN_ACK_STATUS_0_DBB_ACK_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX4CB_PWRDWN_ACK_STATUS_0_DBB_ACK_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PCIEX4CB_PWRDWN_ACK_STATUS_0_DBB_ACK_INIT_ENUM                    PWRDWN
#define PMC_IMPL_PART_PCIEX4CB_PWRDWN_ACK_STATUS_0_DBB_ACK_PWRDWN                       MK_ENUM_CONST(1)
#define PMC_IMPL_PART_PCIEX4CB_PWRDWN_ACK_STATUS_0_DBB_ACK_PWRUP                        MK_ENUM_CONST(0)

#define PMC_IMPL_PART_PCIEX4CB_PWRDWN_ACK_STATUS_0_H1X_ACK_SHIFT                        MK_SHIFT_CONST(2)
#define PMC_IMPL_PART_PCIEX4CB_PWRDWN_ACK_STATUS_0_H1X_ACK_FIELD                        MK_FIELD_CONST(0x1, PMC_IMPL_PART_PCIEX4CB_PWRDWN_ACK_STATUS_0_H1X_ACK_SHIFT)
#define PMC_IMPL_PART_PCIEX4CB_PWRDWN_ACK_STATUS_0_H1X_ACK_RANGE                        2:2
#define PMC_IMPL_PART_PCIEX4CB_PWRDWN_ACK_STATUS_0_H1X_ACK_MSB                  MK_SHIFT_CONST(2)
#define PMC_IMPL_PART_PCIEX4CB_PWRDWN_ACK_STATUS_0_H1X_ACK_LSB                  MK_SHIFT_CONST(2)
#define PMC_IMPL_PART_PCIEX4CB_PWRDWN_ACK_STATUS_0_H1X_ACK_WOFFSET                      0x0
#define PMC_IMPL_PART_PCIEX4CB_PWRDWN_ACK_STATUS_0_H1X_ACK_DEFAULT                      MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PCIEX4CB_PWRDWN_ACK_STATUS_0_H1X_ACK_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PCIEX4CB_PWRDWN_ACK_STATUS_0_H1X_ACK_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX4CB_PWRDWN_ACK_STATUS_0_H1X_ACK_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX4CB_PWRDWN_ACK_STATUS_0_H1X_ACK_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX4CB_PWRDWN_ACK_STATUS_0_H1X_ACK_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PCIEX4CB_PWRDWN_ACK_STATUS_0_H1X_ACK_INIT_ENUM                    PWRDWN
#define PMC_IMPL_PART_PCIEX4CB_PWRDWN_ACK_STATUS_0_H1X_ACK_PWRDWN                       MK_ENUM_CONST(1)
#define PMC_IMPL_PART_PCIEX4CB_PWRDWN_ACK_STATUS_0_H1X_ACK_PWRUP                        MK_ENUM_CONST(0)


// Register PMC_IMPL_PART_PCIEX4CC_PWRDWN_REQ_CONTROL_0
#define PMC_IMPL_PART_PCIEX4CC_PWRDWN_REQ_CONTROL_0                     MK_ADDR_CONST(0x664)
#define PMC_IMPL_PART_PCIEX4CC_PWRDWN_REQ_CONTROL_0_SECURE                      0x0
#define PMC_IMPL_PART_PCIEX4CC_PWRDWN_REQ_CONTROL_0_DUAL                        0x0
#define PMC_IMPL_PART_PCIEX4CC_PWRDWN_REQ_CONTROL_0_SCR                         PG_PCIEX4CC_SCR_0
#define PMC_IMPL_PART_PCIEX4CC_PWRDWN_REQ_CONTROL_0_SCRREG                      PMC_IMPL_SCR_PG_PCIEX4CC_SCR_0
#define PMC_IMPL_PART_PCIEX4CC_PWRDWN_REQ_CONTROL_0_WORD_COUNT                  0x1
#define PMC_IMPL_PART_PCIEX4CC_PWRDWN_REQ_CONTROL_0_RESET_VAL                   MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PCIEX4CC_PWRDWN_REQ_CONTROL_0_RESET_MASK                  MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PCIEX4CC_PWRDWN_REQ_CONTROL_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX4CC_PWRDWN_REQ_CONTROL_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX4CC_PWRDWN_REQ_CONTROL_0_READ_MASK                   MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PCIEX4CC_PWRDWN_REQ_CONTROL_0_WRITE_MASK                  MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PCIEX4CC_PWRDWN_REQ_CONTROL_0_REQ_SHIFT                   MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_PCIEX4CC_PWRDWN_REQ_CONTROL_0_REQ_FIELD                   MK_FIELD_CONST(0x1, PMC_IMPL_PART_PCIEX4CC_PWRDWN_REQ_CONTROL_0_REQ_SHIFT)
#define PMC_IMPL_PART_PCIEX4CC_PWRDWN_REQ_CONTROL_0_REQ_RANGE                   0:0
#define PMC_IMPL_PART_PCIEX4CC_PWRDWN_REQ_CONTROL_0_REQ_MSB                     MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_PCIEX4CC_PWRDWN_REQ_CONTROL_0_REQ_LSB                     MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_PCIEX4CC_PWRDWN_REQ_CONTROL_0_REQ_WOFFSET                 0x0
#define PMC_IMPL_PART_PCIEX4CC_PWRDWN_REQ_CONTROL_0_REQ_DEFAULT                 MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PCIEX4CC_PWRDWN_REQ_CONTROL_0_REQ_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PCIEX4CC_PWRDWN_REQ_CONTROL_0_REQ_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX4CC_PWRDWN_REQ_CONTROL_0_REQ_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX4CC_PWRDWN_REQ_CONTROL_0_REQ_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PCIEX4CC_PWRDWN_REQ_CONTROL_0_REQ_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PCIEX4CC_PWRDWN_REQ_CONTROL_0_REQ_INIT_ENUM                       PWRDWN
#define PMC_IMPL_PART_PCIEX4CC_PWRDWN_REQ_CONTROL_0_REQ_PWRDWN                  MK_ENUM_CONST(1)
#define PMC_IMPL_PART_PCIEX4CC_PWRDWN_REQ_CONTROL_0_REQ_PWRUP                   MK_ENUM_CONST(0)


// Register PMC_IMPL_PART_PCIEX4CC_PWRDWN_ACK_STATUS_0
#define PMC_IMPL_PART_PCIEX4CC_PWRDWN_ACK_STATUS_0                      MK_ADDR_CONST(0x668)
#define PMC_IMPL_PART_PCIEX4CC_PWRDWN_ACK_STATUS_0_SECURE                       0x0
#define PMC_IMPL_PART_PCIEX4CC_PWRDWN_ACK_STATUS_0_DUAL                         0x0
#define PMC_IMPL_PART_PCIEX4CC_PWRDWN_ACK_STATUS_0_SCR                  PG_PCIEX4CC_SCR_0
#define PMC_IMPL_PART_PCIEX4CC_PWRDWN_ACK_STATUS_0_SCRREG                       PMC_IMPL_SCR_PG_PCIEX4CC_SCR_0
#define PMC_IMPL_PART_PCIEX4CC_PWRDWN_ACK_STATUS_0_WORD_COUNT                   0x1
#define PMC_IMPL_PART_PCIEX4CC_PWRDWN_ACK_STATUS_0_RESET_VAL                    MK_MASK_CONST(0x7)
#define PMC_IMPL_PART_PCIEX4CC_PWRDWN_ACK_STATUS_0_RESET_MASK                   MK_MASK_CONST(0x7)
#define PMC_IMPL_PART_PCIEX4CC_PWRDWN_ACK_STATUS_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX4CC_PWRDWN_ACK_STATUS_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX4CC_PWRDWN_ACK_STATUS_0_READ_MASK                    MK_MASK_CONST(0x7)
#define PMC_IMPL_PART_PCIEX4CC_PWRDWN_ACK_STATUS_0_WRITE_MASK                   MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX4CC_PWRDWN_ACK_STATUS_0_CBB_ACK_SHIFT                        MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_PCIEX4CC_PWRDWN_ACK_STATUS_0_CBB_ACK_FIELD                        MK_FIELD_CONST(0x1, PMC_IMPL_PART_PCIEX4CC_PWRDWN_ACK_STATUS_0_CBB_ACK_SHIFT)
#define PMC_IMPL_PART_PCIEX4CC_PWRDWN_ACK_STATUS_0_CBB_ACK_RANGE                        0:0
#define PMC_IMPL_PART_PCIEX4CC_PWRDWN_ACK_STATUS_0_CBB_ACK_MSB                  MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_PCIEX4CC_PWRDWN_ACK_STATUS_0_CBB_ACK_LSB                  MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_PCIEX4CC_PWRDWN_ACK_STATUS_0_CBB_ACK_WOFFSET                      0x0
#define PMC_IMPL_PART_PCIEX4CC_PWRDWN_ACK_STATUS_0_CBB_ACK_DEFAULT                      MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PCIEX4CC_PWRDWN_ACK_STATUS_0_CBB_ACK_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PCIEX4CC_PWRDWN_ACK_STATUS_0_CBB_ACK_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX4CC_PWRDWN_ACK_STATUS_0_CBB_ACK_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX4CC_PWRDWN_ACK_STATUS_0_CBB_ACK_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX4CC_PWRDWN_ACK_STATUS_0_CBB_ACK_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PCIEX4CC_PWRDWN_ACK_STATUS_0_CBB_ACK_INIT_ENUM                    PWRDWN
#define PMC_IMPL_PART_PCIEX4CC_PWRDWN_ACK_STATUS_0_CBB_ACK_PWRDWN                       MK_ENUM_CONST(1)
#define PMC_IMPL_PART_PCIEX4CC_PWRDWN_ACK_STATUS_0_CBB_ACK_PWRUP                        MK_ENUM_CONST(0)

#define PMC_IMPL_PART_PCIEX4CC_PWRDWN_ACK_STATUS_0_DBB_ACK_SHIFT                        MK_SHIFT_CONST(1)
#define PMC_IMPL_PART_PCIEX4CC_PWRDWN_ACK_STATUS_0_DBB_ACK_FIELD                        MK_FIELD_CONST(0x1, PMC_IMPL_PART_PCIEX4CC_PWRDWN_ACK_STATUS_0_DBB_ACK_SHIFT)
#define PMC_IMPL_PART_PCIEX4CC_PWRDWN_ACK_STATUS_0_DBB_ACK_RANGE                        1:1
#define PMC_IMPL_PART_PCIEX4CC_PWRDWN_ACK_STATUS_0_DBB_ACK_MSB                  MK_SHIFT_CONST(1)
#define PMC_IMPL_PART_PCIEX4CC_PWRDWN_ACK_STATUS_0_DBB_ACK_LSB                  MK_SHIFT_CONST(1)
#define PMC_IMPL_PART_PCIEX4CC_PWRDWN_ACK_STATUS_0_DBB_ACK_WOFFSET                      0x0
#define PMC_IMPL_PART_PCIEX4CC_PWRDWN_ACK_STATUS_0_DBB_ACK_DEFAULT                      MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PCIEX4CC_PWRDWN_ACK_STATUS_0_DBB_ACK_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PCIEX4CC_PWRDWN_ACK_STATUS_0_DBB_ACK_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX4CC_PWRDWN_ACK_STATUS_0_DBB_ACK_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX4CC_PWRDWN_ACK_STATUS_0_DBB_ACK_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX4CC_PWRDWN_ACK_STATUS_0_DBB_ACK_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PCIEX4CC_PWRDWN_ACK_STATUS_0_DBB_ACK_INIT_ENUM                    PWRDWN
#define PMC_IMPL_PART_PCIEX4CC_PWRDWN_ACK_STATUS_0_DBB_ACK_PWRDWN                       MK_ENUM_CONST(1)
#define PMC_IMPL_PART_PCIEX4CC_PWRDWN_ACK_STATUS_0_DBB_ACK_PWRUP                        MK_ENUM_CONST(0)

#define PMC_IMPL_PART_PCIEX4CC_PWRDWN_ACK_STATUS_0_H1X_ACK_SHIFT                        MK_SHIFT_CONST(2)
#define PMC_IMPL_PART_PCIEX4CC_PWRDWN_ACK_STATUS_0_H1X_ACK_FIELD                        MK_FIELD_CONST(0x1, PMC_IMPL_PART_PCIEX4CC_PWRDWN_ACK_STATUS_0_H1X_ACK_SHIFT)
#define PMC_IMPL_PART_PCIEX4CC_PWRDWN_ACK_STATUS_0_H1X_ACK_RANGE                        2:2
#define PMC_IMPL_PART_PCIEX4CC_PWRDWN_ACK_STATUS_0_H1X_ACK_MSB                  MK_SHIFT_CONST(2)
#define PMC_IMPL_PART_PCIEX4CC_PWRDWN_ACK_STATUS_0_H1X_ACK_LSB                  MK_SHIFT_CONST(2)
#define PMC_IMPL_PART_PCIEX4CC_PWRDWN_ACK_STATUS_0_H1X_ACK_WOFFSET                      0x0
#define PMC_IMPL_PART_PCIEX4CC_PWRDWN_ACK_STATUS_0_H1X_ACK_DEFAULT                      MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PCIEX4CC_PWRDWN_ACK_STATUS_0_H1X_ACK_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PCIEX4CC_PWRDWN_ACK_STATUS_0_H1X_ACK_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX4CC_PWRDWN_ACK_STATUS_0_H1X_ACK_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX4CC_PWRDWN_ACK_STATUS_0_H1X_ACK_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX4CC_PWRDWN_ACK_STATUS_0_H1X_ACK_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PCIEX4CC_PWRDWN_ACK_STATUS_0_H1X_ACK_INIT_ENUM                    PWRDWN
#define PMC_IMPL_PART_PCIEX4CC_PWRDWN_ACK_STATUS_0_H1X_ACK_PWRDWN                       MK_ENUM_CONST(1)
#define PMC_IMPL_PART_PCIEX4CC_PWRDWN_ACK_STATUS_0_H1X_ACK_PWRUP                        MK_ENUM_CONST(0)


// Register PMC_IMPL_PART_PCIEX1A_PWRDWN_REQ_CONTROL_0
#define PMC_IMPL_PART_PCIEX1A_PWRDWN_REQ_CONTROL_0                      MK_ADDR_CONST(0x66c)
#define PMC_IMPL_PART_PCIEX1A_PWRDWN_REQ_CONTROL_0_SECURE                       0x0
#define PMC_IMPL_PART_PCIEX1A_PWRDWN_REQ_CONTROL_0_DUAL                         0x0
#define PMC_IMPL_PART_PCIEX1A_PWRDWN_REQ_CONTROL_0_SCR                  PG_PCIEX1A_SCR_0
#define PMC_IMPL_PART_PCIEX1A_PWRDWN_REQ_CONTROL_0_SCRREG                       PMC_IMPL_SCR_PG_PCIEX1A_SCR_0
#define PMC_IMPL_PART_PCIEX1A_PWRDWN_REQ_CONTROL_0_WORD_COUNT                   0x1
#define PMC_IMPL_PART_PCIEX1A_PWRDWN_REQ_CONTROL_0_RESET_VAL                    MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PCIEX1A_PWRDWN_REQ_CONTROL_0_RESET_MASK                   MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PCIEX1A_PWRDWN_REQ_CONTROL_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX1A_PWRDWN_REQ_CONTROL_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX1A_PWRDWN_REQ_CONTROL_0_READ_MASK                    MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PCIEX1A_PWRDWN_REQ_CONTROL_0_WRITE_MASK                   MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PCIEX1A_PWRDWN_REQ_CONTROL_0_REQ_SHIFT                    MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_PCIEX1A_PWRDWN_REQ_CONTROL_0_REQ_FIELD                    MK_FIELD_CONST(0x1, PMC_IMPL_PART_PCIEX1A_PWRDWN_REQ_CONTROL_0_REQ_SHIFT)
#define PMC_IMPL_PART_PCIEX1A_PWRDWN_REQ_CONTROL_0_REQ_RANGE                    0:0
#define PMC_IMPL_PART_PCIEX1A_PWRDWN_REQ_CONTROL_0_REQ_MSB                      MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_PCIEX1A_PWRDWN_REQ_CONTROL_0_REQ_LSB                      MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_PCIEX1A_PWRDWN_REQ_CONTROL_0_REQ_WOFFSET                  0x0
#define PMC_IMPL_PART_PCIEX1A_PWRDWN_REQ_CONTROL_0_REQ_DEFAULT                  MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PCIEX1A_PWRDWN_REQ_CONTROL_0_REQ_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PCIEX1A_PWRDWN_REQ_CONTROL_0_REQ_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX1A_PWRDWN_REQ_CONTROL_0_REQ_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX1A_PWRDWN_REQ_CONTROL_0_REQ_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PCIEX1A_PWRDWN_REQ_CONTROL_0_REQ_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PCIEX1A_PWRDWN_REQ_CONTROL_0_REQ_INIT_ENUM                        PWRDWN
#define PMC_IMPL_PART_PCIEX1A_PWRDWN_REQ_CONTROL_0_REQ_PWRDWN                   MK_ENUM_CONST(1)
#define PMC_IMPL_PART_PCIEX1A_PWRDWN_REQ_CONTROL_0_REQ_PWRUP                    MK_ENUM_CONST(0)


// Register PMC_IMPL_PART_PCIEX1A_PWRDWN_ACK_STATUS_0
#define PMC_IMPL_PART_PCIEX1A_PWRDWN_ACK_STATUS_0                       MK_ADDR_CONST(0x670)
#define PMC_IMPL_PART_PCIEX1A_PWRDWN_ACK_STATUS_0_SECURE                        0x0
#define PMC_IMPL_PART_PCIEX1A_PWRDWN_ACK_STATUS_0_DUAL                  0x0
#define PMC_IMPL_PART_PCIEX1A_PWRDWN_ACK_STATUS_0_SCR                   PG_PCIEX1A_SCR_0
#define PMC_IMPL_PART_PCIEX1A_PWRDWN_ACK_STATUS_0_SCRREG                        PMC_IMPL_SCR_PG_PCIEX1A_SCR_0
#define PMC_IMPL_PART_PCIEX1A_PWRDWN_ACK_STATUS_0_WORD_COUNT                    0x1
#define PMC_IMPL_PART_PCIEX1A_PWRDWN_ACK_STATUS_0_RESET_VAL                     MK_MASK_CONST(0x7)
#define PMC_IMPL_PART_PCIEX1A_PWRDWN_ACK_STATUS_0_RESET_MASK                    MK_MASK_CONST(0x7)
#define PMC_IMPL_PART_PCIEX1A_PWRDWN_ACK_STATUS_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX1A_PWRDWN_ACK_STATUS_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX1A_PWRDWN_ACK_STATUS_0_READ_MASK                     MK_MASK_CONST(0x7)
#define PMC_IMPL_PART_PCIEX1A_PWRDWN_ACK_STATUS_0_WRITE_MASK                    MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX1A_PWRDWN_ACK_STATUS_0_CBB_ACK_SHIFT                 MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_PCIEX1A_PWRDWN_ACK_STATUS_0_CBB_ACK_FIELD                 MK_FIELD_CONST(0x1, PMC_IMPL_PART_PCIEX1A_PWRDWN_ACK_STATUS_0_CBB_ACK_SHIFT)
#define PMC_IMPL_PART_PCIEX1A_PWRDWN_ACK_STATUS_0_CBB_ACK_RANGE                 0:0
#define PMC_IMPL_PART_PCIEX1A_PWRDWN_ACK_STATUS_0_CBB_ACK_MSB                   MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_PCIEX1A_PWRDWN_ACK_STATUS_0_CBB_ACK_LSB                   MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_PCIEX1A_PWRDWN_ACK_STATUS_0_CBB_ACK_WOFFSET                       0x0
#define PMC_IMPL_PART_PCIEX1A_PWRDWN_ACK_STATUS_0_CBB_ACK_DEFAULT                       MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PCIEX1A_PWRDWN_ACK_STATUS_0_CBB_ACK_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PCIEX1A_PWRDWN_ACK_STATUS_0_CBB_ACK_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX1A_PWRDWN_ACK_STATUS_0_CBB_ACK_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX1A_PWRDWN_ACK_STATUS_0_CBB_ACK_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX1A_PWRDWN_ACK_STATUS_0_CBB_ACK_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PCIEX1A_PWRDWN_ACK_STATUS_0_CBB_ACK_INIT_ENUM                     PWRDWN
#define PMC_IMPL_PART_PCIEX1A_PWRDWN_ACK_STATUS_0_CBB_ACK_PWRDWN                        MK_ENUM_CONST(1)
#define PMC_IMPL_PART_PCIEX1A_PWRDWN_ACK_STATUS_0_CBB_ACK_PWRUP                 MK_ENUM_CONST(0)

#define PMC_IMPL_PART_PCIEX1A_PWRDWN_ACK_STATUS_0_DBB_ACK_SHIFT                 MK_SHIFT_CONST(1)
#define PMC_IMPL_PART_PCIEX1A_PWRDWN_ACK_STATUS_0_DBB_ACK_FIELD                 MK_FIELD_CONST(0x1, PMC_IMPL_PART_PCIEX1A_PWRDWN_ACK_STATUS_0_DBB_ACK_SHIFT)
#define PMC_IMPL_PART_PCIEX1A_PWRDWN_ACK_STATUS_0_DBB_ACK_RANGE                 1:1
#define PMC_IMPL_PART_PCIEX1A_PWRDWN_ACK_STATUS_0_DBB_ACK_MSB                   MK_SHIFT_CONST(1)
#define PMC_IMPL_PART_PCIEX1A_PWRDWN_ACK_STATUS_0_DBB_ACK_LSB                   MK_SHIFT_CONST(1)
#define PMC_IMPL_PART_PCIEX1A_PWRDWN_ACK_STATUS_0_DBB_ACK_WOFFSET                       0x0
#define PMC_IMPL_PART_PCIEX1A_PWRDWN_ACK_STATUS_0_DBB_ACK_DEFAULT                       MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PCIEX1A_PWRDWN_ACK_STATUS_0_DBB_ACK_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PCIEX1A_PWRDWN_ACK_STATUS_0_DBB_ACK_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX1A_PWRDWN_ACK_STATUS_0_DBB_ACK_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX1A_PWRDWN_ACK_STATUS_0_DBB_ACK_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX1A_PWRDWN_ACK_STATUS_0_DBB_ACK_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PCIEX1A_PWRDWN_ACK_STATUS_0_DBB_ACK_INIT_ENUM                     PWRDWN
#define PMC_IMPL_PART_PCIEX1A_PWRDWN_ACK_STATUS_0_DBB_ACK_PWRDWN                        MK_ENUM_CONST(1)
#define PMC_IMPL_PART_PCIEX1A_PWRDWN_ACK_STATUS_0_DBB_ACK_PWRUP                 MK_ENUM_CONST(0)

#define PMC_IMPL_PART_PCIEX1A_PWRDWN_ACK_STATUS_0_H1X_ACK_SHIFT                 MK_SHIFT_CONST(2)
#define PMC_IMPL_PART_PCIEX1A_PWRDWN_ACK_STATUS_0_H1X_ACK_FIELD                 MK_FIELD_CONST(0x1, PMC_IMPL_PART_PCIEX1A_PWRDWN_ACK_STATUS_0_H1X_ACK_SHIFT)
#define PMC_IMPL_PART_PCIEX1A_PWRDWN_ACK_STATUS_0_H1X_ACK_RANGE                 2:2
#define PMC_IMPL_PART_PCIEX1A_PWRDWN_ACK_STATUS_0_H1X_ACK_MSB                   MK_SHIFT_CONST(2)
#define PMC_IMPL_PART_PCIEX1A_PWRDWN_ACK_STATUS_0_H1X_ACK_LSB                   MK_SHIFT_CONST(2)
#define PMC_IMPL_PART_PCIEX1A_PWRDWN_ACK_STATUS_0_H1X_ACK_WOFFSET                       0x0
#define PMC_IMPL_PART_PCIEX1A_PWRDWN_ACK_STATUS_0_H1X_ACK_DEFAULT                       MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PCIEX1A_PWRDWN_ACK_STATUS_0_H1X_ACK_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PCIEX1A_PWRDWN_ACK_STATUS_0_H1X_ACK_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX1A_PWRDWN_ACK_STATUS_0_H1X_ACK_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX1A_PWRDWN_ACK_STATUS_0_H1X_ACK_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX1A_PWRDWN_ACK_STATUS_0_H1X_ACK_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PCIEX1A_PWRDWN_ACK_STATUS_0_H1X_ACK_INIT_ENUM                     PWRDWN
#define PMC_IMPL_PART_PCIEX1A_PWRDWN_ACK_STATUS_0_H1X_ACK_PWRDWN                        MK_ENUM_CONST(1)
#define PMC_IMPL_PART_PCIEX1A_PWRDWN_ACK_STATUS_0_H1X_ACK_PWRUP                 MK_ENUM_CONST(0)


// Register PMC_IMPL_PART_PCIEX8B_PWRDWN_REQ_CONTROL_0
#define PMC_IMPL_PART_PCIEX8B_PWRDWN_REQ_CONTROL_0                      MK_ADDR_CONST(0x674)
#define PMC_IMPL_PART_PCIEX8B_PWRDWN_REQ_CONTROL_0_SECURE                       0x0
#define PMC_IMPL_PART_PCIEX8B_PWRDWN_REQ_CONTROL_0_DUAL                         0x0
#define PMC_IMPL_PART_PCIEX8B_PWRDWN_REQ_CONTROL_0_SCR                  PG_PCIEX8B_SCR_0
#define PMC_IMPL_PART_PCIEX8B_PWRDWN_REQ_CONTROL_0_SCRREG                       PMC_IMPL_SCR_PG_PCIEX8B_SCR_0
#define PMC_IMPL_PART_PCIEX8B_PWRDWN_REQ_CONTROL_0_WORD_COUNT                   0x1
#define PMC_IMPL_PART_PCIEX8B_PWRDWN_REQ_CONTROL_0_RESET_VAL                    MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PCIEX8B_PWRDWN_REQ_CONTROL_0_RESET_MASK                   MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PCIEX8B_PWRDWN_REQ_CONTROL_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX8B_PWRDWN_REQ_CONTROL_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX8B_PWRDWN_REQ_CONTROL_0_READ_MASK                    MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PCIEX8B_PWRDWN_REQ_CONTROL_0_WRITE_MASK                   MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PCIEX8B_PWRDWN_REQ_CONTROL_0_REQ_SHIFT                    MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_PCIEX8B_PWRDWN_REQ_CONTROL_0_REQ_FIELD                    MK_FIELD_CONST(0x1, PMC_IMPL_PART_PCIEX8B_PWRDWN_REQ_CONTROL_0_REQ_SHIFT)
#define PMC_IMPL_PART_PCIEX8B_PWRDWN_REQ_CONTROL_0_REQ_RANGE                    0:0
#define PMC_IMPL_PART_PCIEX8B_PWRDWN_REQ_CONTROL_0_REQ_MSB                      MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_PCIEX8B_PWRDWN_REQ_CONTROL_0_REQ_LSB                      MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_PCIEX8B_PWRDWN_REQ_CONTROL_0_REQ_WOFFSET                  0x0
#define PMC_IMPL_PART_PCIEX8B_PWRDWN_REQ_CONTROL_0_REQ_DEFAULT                  MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PCIEX8B_PWRDWN_REQ_CONTROL_0_REQ_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PCIEX8B_PWRDWN_REQ_CONTROL_0_REQ_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX8B_PWRDWN_REQ_CONTROL_0_REQ_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX8B_PWRDWN_REQ_CONTROL_0_REQ_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PCIEX8B_PWRDWN_REQ_CONTROL_0_REQ_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PCIEX8B_PWRDWN_REQ_CONTROL_0_REQ_INIT_ENUM                        PWRDWN
#define PMC_IMPL_PART_PCIEX8B_PWRDWN_REQ_CONTROL_0_REQ_PWRDWN                   MK_ENUM_CONST(1)
#define PMC_IMPL_PART_PCIEX8B_PWRDWN_REQ_CONTROL_0_REQ_PWRUP                    MK_ENUM_CONST(0)


// Register PMC_IMPL_PART_PCIEX8B_PWRDWN_ACK_STATUS_0
#define PMC_IMPL_PART_PCIEX8B_PWRDWN_ACK_STATUS_0                       MK_ADDR_CONST(0x678)
#define PMC_IMPL_PART_PCIEX8B_PWRDWN_ACK_STATUS_0_SECURE                        0x0
#define PMC_IMPL_PART_PCIEX8B_PWRDWN_ACK_STATUS_0_DUAL                  0x0
#define PMC_IMPL_PART_PCIEX8B_PWRDWN_ACK_STATUS_0_SCR                   PG_PCIEX8B_SCR_0
#define PMC_IMPL_PART_PCIEX8B_PWRDWN_ACK_STATUS_0_SCRREG                        PMC_IMPL_SCR_PG_PCIEX8B_SCR_0
#define PMC_IMPL_PART_PCIEX8B_PWRDWN_ACK_STATUS_0_WORD_COUNT                    0x1
#define PMC_IMPL_PART_PCIEX8B_PWRDWN_ACK_STATUS_0_RESET_VAL                     MK_MASK_CONST(0x7)
#define PMC_IMPL_PART_PCIEX8B_PWRDWN_ACK_STATUS_0_RESET_MASK                    MK_MASK_CONST(0x7)
#define PMC_IMPL_PART_PCIEX8B_PWRDWN_ACK_STATUS_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX8B_PWRDWN_ACK_STATUS_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX8B_PWRDWN_ACK_STATUS_0_READ_MASK                     MK_MASK_CONST(0x7)
#define PMC_IMPL_PART_PCIEX8B_PWRDWN_ACK_STATUS_0_WRITE_MASK                    MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX8B_PWRDWN_ACK_STATUS_0_CBB_ACK_SHIFT                 MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_PCIEX8B_PWRDWN_ACK_STATUS_0_CBB_ACK_FIELD                 MK_FIELD_CONST(0x1, PMC_IMPL_PART_PCIEX8B_PWRDWN_ACK_STATUS_0_CBB_ACK_SHIFT)
#define PMC_IMPL_PART_PCIEX8B_PWRDWN_ACK_STATUS_0_CBB_ACK_RANGE                 0:0
#define PMC_IMPL_PART_PCIEX8B_PWRDWN_ACK_STATUS_0_CBB_ACK_MSB                   MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_PCIEX8B_PWRDWN_ACK_STATUS_0_CBB_ACK_LSB                   MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_PCIEX8B_PWRDWN_ACK_STATUS_0_CBB_ACK_WOFFSET                       0x0
#define PMC_IMPL_PART_PCIEX8B_PWRDWN_ACK_STATUS_0_CBB_ACK_DEFAULT                       MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PCIEX8B_PWRDWN_ACK_STATUS_0_CBB_ACK_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PCIEX8B_PWRDWN_ACK_STATUS_0_CBB_ACK_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX8B_PWRDWN_ACK_STATUS_0_CBB_ACK_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX8B_PWRDWN_ACK_STATUS_0_CBB_ACK_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX8B_PWRDWN_ACK_STATUS_0_CBB_ACK_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PCIEX8B_PWRDWN_ACK_STATUS_0_CBB_ACK_INIT_ENUM                     PWRDWN
#define PMC_IMPL_PART_PCIEX8B_PWRDWN_ACK_STATUS_0_CBB_ACK_PWRDWN                        MK_ENUM_CONST(1)
#define PMC_IMPL_PART_PCIEX8B_PWRDWN_ACK_STATUS_0_CBB_ACK_PWRUP                 MK_ENUM_CONST(0)

#define PMC_IMPL_PART_PCIEX8B_PWRDWN_ACK_STATUS_0_DBB_ACK_SHIFT                 MK_SHIFT_CONST(1)
#define PMC_IMPL_PART_PCIEX8B_PWRDWN_ACK_STATUS_0_DBB_ACK_FIELD                 MK_FIELD_CONST(0x1, PMC_IMPL_PART_PCIEX8B_PWRDWN_ACK_STATUS_0_DBB_ACK_SHIFT)
#define PMC_IMPL_PART_PCIEX8B_PWRDWN_ACK_STATUS_0_DBB_ACK_RANGE                 1:1
#define PMC_IMPL_PART_PCIEX8B_PWRDWN_ACK_STATUS_0_DBB_ACK_MSB                   MK_SHIFT_CONST(1)
#define PMC_IMPL_PART_PCIEX8B_PWRDWN_ACK_STATUS_0_DBB_ACK_LSB                   MK_SHIFT_CONST(1)
#define PMC_IMPL_PART_PCIEX8B_PWRDWN_ACK_STATUS_0_DBB_ACK_WOFFSET                       0x0
#define PMC_IMPL_PART_PCIEX8B_PWRDWN_ACK_STATUS_0_DBB_ACK_DEFAULT                       MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PCIEX8B_PWRDWN_ACK_STATUS_0_DBB_ACK_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PCIEX8B_PWRDWN_ACK_STATUS_0_DBB_ACK_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX8B_PWRDWN_ACK_STATUS_0_DBB_ACK_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX8B_PWRDWN_ACK_STATUS_0_DBB_ACK_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX8B_PWRDWN_ACK_STATUS_0_DBB_ACK_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PCIEX8B_PWRDWN_ACK_STATUS_0_DBB_ACK_INIT_ENUM                     PWRDWN
#define PMC_IMPL_PART_PCIEX8B_PWRDWN_ACK_STATUS_0_DBB_ACK_PWRDWN                        MK_ENUM_CONST(1)
#define PMC_IMPL_PART_PCIEX8B_PWRDWN_ACK_STATUS_0_DBB_ACK_PWRUP                 MK_ENUM_CONST(0)

#define PMC_IMPL_PART_PCIEX8B_PWRDWN_ACK_STATUS_0_H1X_ACK_SHIFT                 MK_SHIFT_CONST(2)
#define PMC_IMPL_PART_PCIEX8B_PWRDWN_ACK_STATUS_0_H1X_ACK_FIELD                 MK_FIELD_CONST(0x1, PMC_IMPL_PART_PCIEX8B_PWRDWN_ACK_STATUS_0_H1X_ACK_SHIFT)
#define PMC_IMPL_PART_PCIEX8B_PWRDWN_ACK_STATUS_0_H1X_ACK_RANGE                 2:2
#define PMC_IMPL_PART_PCIEX8B_PWRDWN_ACK_STATUS_0_H1X_ACK_MSB                   MK_SHIFT_CONST(2)
#define PMC_IMPL_PART_PCIEX8B_PWRDWN_ACK_STATUS_0_H1X_ACK_LSB                   MK_SHIFT_CONST(2)
#define PMC_IMPL_PART_PCIEX8B_PWRDWN_ACK_STATUS_0_H1X_ACK_WOFFSET                       0x0
#define PMC_IMPL_PART_PCIEX8B_PWRDWN_ACK_STATUS_0_H1X_ACK_DEFAULT                       MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PCIEX8B_PWRDWN_ACK_STATUS_0_H1X_ACK_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PCIEX8B_PWRDWN_ACK_STATUS_0_H1X_ACK_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX8B_PWRDWN_ACK_STATUS_0_H1X_ACK_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX8B_PWRDWN_ACK_STATUS_0_H1X_ACK_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX8B_PWRDWN_ACK_STATUS_0_H1X_ACK_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PCIEX8B_PWRDWN_ACK_STATUS_0_H1X_ACK_INIT_ENUM                     PWRDWN
#define PMC_IMPL_PART_PCIEX8B_PWRDWN_ACK_STATUS_0_H1X_ACK_PWRDWN                        MK_ENUM_CONST(1)
#define PMC_IMPL_PART_PCIEX8B_PWRDWN_ACK_STATUS_0_H1X_ACK_PWRUP                 MK_ENUM_CONST(0)


// Register PMC_IMPL_PART_PVA_PWRDWN_REQ_CONTROL_0
#define PMC_IMPL_PART_PVA_PWRDWN_REQ_CONTROL_0                  MK_ADDR_CONST(0x67c)
#define PMC_IMPL_PART_PVA_PWRDWN_REQ_CONTROL_0_SECURE                   0x0
#define PMC_IMPL_PART_PVA_PWRDWN_REQ_CONTROL_0_DUAL                     0x0
#define PMC_IMPL_PART_PVA_PWRDWN_REQ_CONTROL_0_SCR                      PG_PVA_SCR_0
#define PMC_IMPL_PART_PVA_PWRDWN_REQ_CONTROL_0_SCRREG                   PMC_IMPL_SCR_PG_PVA_SCR_0
#define PMC_IMPL_PART_PVA_PWRDWN_REQ_CONTROL_0_WORD_COUNT                       0x1
#define PMC_IMPL_PART_PVA_PWRDWN_REQ_CONTROL_0_RESET_VAL                        MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PVA_PWRDWN_REQ_CONTROL_0_RESET_MASK                       MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PVA_PWRDWN_REQ_CONTROL_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PVA_PWRDWN_REQ_CONTROL_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PVA_PWRDWN_REQ_CONTROL_0_READ_MASK                        MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PVA_PWRDWN_REQ_CONTROL_0_WRITE_MASK                       MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PVA_PWRDWN_REQ_CONTROL_0_REQ_SHIFT                        MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_PVA_PWRDWN_REQ_CONTROL_0_REQ_FIELD                        MK_FIELD_CONST(0x1, PMC_IMPL_PART_PVA_PWRDWN_REQ_CONTROL_0_REQ_SHIFT)
#define PMC_IMPL_PART_PVA_PWRDWN_REQ_CONTROL_0_REQ_RANGE                        0:0
#define PMC_IMPL_PART_PVA_PWRDWN_REQ_CONTROL_0_REQ_MSB                  MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_PVA_PWRDWN_REQ_CONTROL_0_REQ_LSB                  MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_PVA_PWRDWN_REQ_CONTROL_0_REQ_WOFFSET                      0x0
#define PMC_IMPL_PART_PVA_PWRDWN_REQ_CONTROL_0_REQ_DEFAULT                      MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PVA_PWRDWN_REQ_CONTROL_0_REQ_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PVA_PWRDWN_REQ_CONTROL_0_REQ_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PVA_PWRDWN_REQ_CONTROL_0_REQ_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PVA_PWRDWN_REQ_CONTROL_0_REQ_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PVA_PWRDWN_REQ_CONTROL_0_REQ_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PVA_PWRDWN_REQ_CONTROL_0_REQ_INIT_ENUM                    PWRDWN
#define PMC_IMPL_PART_PVA_PWRDWN_REQ_CONTROL_0_REQ_PWRDWN                       MK_ENUM_CONST(1)
#define PMC_IMPL_PART_PVA_PWRDWN_REQ_CONTROL_0_REQ_PWRUP                        MK_ENUM_CONST(0)


// Register PMC_IMPL_PART_PVA_PWRDWN_ACK_STATUS_0
#define PMC_IMPL_PART_PVA_PWRDWN_ACK_STATUS_0                   MK_ADDR_CONST(0x680)
#define PMC_IMPL_PART_PVA_PWRDWN_ACK_STATUS_0_SECURE                    0x0
#define PMC_IMPL_PART_PVA_PWRDWN_ACK_STATUS_0_DUAL                      0x0
#define PMC_IMPL_PART_PVA_PWRDWN_ACK_STATUS_0_SCR                       PG_PVA_SCR_0
#define PMC_IMPL_PART_PVA_PWRDWN_ACK_STATUS_0_SCRREG                    PMC_IMPL_SCR_PG_PVA_SCR_0
#define PMC_IMPL_PART_PVA_PWRDWN_ACK_STATUS_0_WORD_COUNT                        0x1
#define PMC_IMPL_PART_PVA_PWRDWN_ACK_STATUS_0_RESET_VAL                         MK_MASK_CONST(0x7)
#define PMC_IMPL_PART_PVA_PWRDWN_ACK_STATUS_0_RESET_MASK                        MK_MASK_CONST(0x7)
#define PMC_IMPL_PART_PVA_PWRDWN_ACK_STATUS_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PVA_PWRDWN_ACK_STATUS_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PVA_PWRDWN_ACK_STATUS_0_READ_MASK                         MK_MASK_CONST(0x7)
#define PMC_IMPL_PART_PVA_PWRDWN_ACK_STATUS_0_WRITE_MASK                        MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PVA_PWRDWN_ACK_STATUS_0_CBB_ACK_SHIFT                     MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_PVA_PWRDWN_ACK_STATUS_0_CBB_ACK_FIELD                     MK_FIELD_CONST(0x1, PMC_IMPL_PART_PVA_PWRDWN_ACK_STATUS_0_CBB_ACK_SHIFT)
#define PMC_IMPL_PART_PVA_PWRDWN_ACK_STATUS_0_CBB_ACK_RANGE                     0:0
#define PMC_IMPL_PART_PVA_PWRDWN_ACK_STATUS_0_CBB_ACK_MSB                       MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_PVA_PWRDWN_ACK_STATUS_0_CBB_ACK_LSB                       MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_PVA_PWRDWN_ACK_STATUS_0_CBB_ACK_WOFFSET                   0x0
#define PMC_IMPL_PART_PVA_PWRDWN_ACK_STATUS_0_CBB_ACK_DEFAULT                   MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PVA_PWRDWN_ACK_STATUS_0_CBB_ACK_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PVA_PWRDWN_ACK_STATUS_0_CBB_ACK_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PVA_PWRDWN_ACK_STATUS_0_CBB_ACK_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PVA_PWRDWN_ACK_STATUS_0_CBB_ACK_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PVA_PWRDWN_ACK_STATUS_0_CBB_ACK_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PVA_PWRDWN_ACK_STATUS_0_CBB_ACK_INIT_ENUM                 PWRDWN
#define PMC_IMPL_PART_PVA_PWRDWN_ACK_STATUS_0_CBB_ACK_PWRDWN                    MK_ENUM_CONST(1)
#define PMC_IMPL_PART_PVA_PWRDWN_ACK_STATUS_0_CBB_ACK_PWRUP                     MK_ENUM_CONST(0)

#define PMC_IMPL_PART_PVA_PWRDWN_ACK_STATUS_0_DBB_ACK_SHIFT                     MK_SHIFT_CONST(1)
#define PMC_IMPL_PART_PVA_PWRDWN_ACK_STATUS_0_DBB_ACK_FIELD                     MK_FIELD_CONST(0x1, PMC_IMPL_PART_PVA_PWRDWN_ACK_STATUS_0_DBB_ACK_SHIFT)
#define PMC_IMPL_PART_PVA_PWRDWN_ACK_STATUS_0_DBB_ACK_RANGE                     1:1
#define PMC_IMPL_PART_PVA_PWRDWN_ACK_STATUS_0_DBB_ACK_MSB                       MK_SHIFT_CONST(1)
#define PMC_IMPL_PART_PVA_PWRDWN_ACK_STATUS_0_DBB_ACK_LSB                       MK_SHIFT_CONST(1)
#define PMC_IMPL_PART_PVA_PWRDWN_ACK_STATUS_0_DBB_ACK_WOFFSET                   0x0
#define PMC_IMPL_PART_PVA_PWRDWN_ACK_STATUS_0_DBB_ACK_DEFAULT                   MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PVA_PWRDWN_ACK_STATUS_0_DBB_ACK_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PVA_PWRDWN_ACK_STATUS_0_DBB_ACK_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PVA_PWRDWN_ACK_STATUS_0_DBB_ACK_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PVA_PWRDWN_ACK_STATUS_0_DBB_ACK_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PVA_PWRDWN_ACK_STATUS_0_DBB_ACK_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PVA_PWRDWN_ACK_STATUS_0_DBB_ACK_INIT_ENUM                 PWRDWN
#define PMC_IMPL_PART_PVA_PWRDWN_ACK_STATUS_0_DBB_ACK_PWRDWN                    MK_ENUM_CONST(1)
#define PMC_IMPL_PART_PVA_PWRDWN_ACK_STATUS_0_DBB_ACK_PWRUP                     MK_ENUM_CONST(0)

#define PMC_IMPL_PART_PVA_PWRDWN_ACK_STATUS_0_H1X_ACK_SHIFT                     MK_SHIFT_CONST(2)
#define PMC_IMPL_PART_PVA_PWRDWN_ACK_STATUS_0_H1X_ACK_FIELD                     MK_FIELD_CONST(0x1, PMC_IMPL_PART_PVA_PWRDWN_ACK_STATUS_0_H1X_ACK_SHIFT)
#define PMC_IMPL_PART_PVA_PWRDWN_ACK_STATUS_0_H1X_ACK_RANGE                     2:2
#define PMC_IMPL_PART_PVA_PWRDWN_ACK_STATUS_0_H1X_ACK_MSB                       MK_SHIFT_CONST(2)
#define PMC_IMPL_PART_PVA_PWRDWN_ACK_STATUS_0_H1X_ACK_LSB                       MK_SHIFT_CONST(2)
#define PMC_IMPL_PART_PVA_PWRDWN_ACK_STATUS_0_H1X_ACK_WOFFSET                   0x0
#define PMC_IMPL_PART_PVA_PWRDWN_ACK_STATUS_0_H1X_ACK_DEFAULT                   MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PVA_PWRDWN_ACK_STATUS_0_H1X_ACK_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PVA_PWRDWN_ACK_STATUS_0_H1X_ACK_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PVA_PWRDWN_ACK_STATUS_0_H1X_ACK_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PVA_PWRDWN_ACK_STATUS_0_H1X_ACK_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PVA_PWRDWN_ACK_STATUS_0_H1X_ACK_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PVA_PWRDWN_ACK_STATUS_0_H1X_ACK_INIT_ENUM                 PWRDWN
#define PMC_IMPL_PART_PVA_PWRDWN_ACK_STATUS_0_H1X_ACK_PWRDWN                    MK_ENUM_CONST(1)
#define PMC_IMPL_PART_PVA_PWRDWN_ACK_STATUS_0_H1X_ACK_PWRUP                     MK_ENUM_CONST(0)


// Register PMC_IMPL_PART_DLAA_PWRDWN_REQ_CONTROL_0
#define PMC_IMPL_PART_DLAA_PWRDWN_REQ_CONTROL_0                 MK_ADDR_CONST(0x684)
#define PMC_IMPL_PART_DLAA_PWRDWN_REQ_CONTROL_0_SECURE                  0x0
#define PMC_IMPL_PART_DLAA_PWRDWN_REQ_CONTROL_0_DUAL                    0x0
#define PMC_IMPL_PART_DLAA_PWRDWN_REQ_CONTROL_0_SCR                     PG_DLAA_SCR_0
#define PMC_IMPL_PART_DLAA_PWRDWN_REQ_CONTROL_0_SCRREG                  PMC_IMPL_SCR_PG_DLAA_SCR_0
#define PMC_IMPL_PART_DLAA_PWRDWN_REQ_CONTROL_0_WORD_COUNT                      0x1
#define PMC_IMPL_PART_DLAA_PWRDWN_REQ_CONTROL_0_RESET_VAL                       MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_DLAA_PWRDWN_REQ_CONTROL_0_RESET_MASK                      MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_DLAA_PWRDWN_REQ_CONTROL_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_DLAA_PWRDWN_REQ_CONTROL_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_DLAA_PWRDWN_REQ_CONTROL_0_READ_MASK                       MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_DLAA_PWRDWN_REQ_CONTROL_0_WRITE_MASK                      MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_DLAA_PWRDWN_REQ_CONTROL_0_REQ_SHIFT                       MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_DLAA_PWRDWN_REQ_CONTROL_0_REQ_FIELD                       MK_FIELD_CONST(0x1, PMC_IMPL_PART_DLAA_PWRDWN_REQ_CONTROL_0_REQ_SHIFT)
#define PMC_IMPL_PART_DLAA_PWRDWN_REQ_CONTROL_0_REQ_RANGE                       0:0
#define PMC_IMPL_PART_DLAA_PWRDWN_REQ_CONTROL_0_REQ_MSB                 MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_DLAA_PWRDWN_REQ_CONTROL_0_REQ_LSB                 MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_DLAA_PWRDWN_REQ_CONTROL_0_REQ_WOFFSET                     0x0
#define PMC_IMPL_PART_DLAA_PWRDWN_REQ_CONTROL_0_REQ_DEFAULT                     MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_DLAA_PWRDWN_REQ_CONTROL_0_REQ_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_DLAA_PWRDWN_REQ_CONTROL_0_REQ_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_DLAA_PWRDWN_REQ_CONTROL_0_REQ_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_DLAA_PWRDWN_REQ_CONTROL_0_REQ_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_DLAA_PWRDWN_REQ_CONTROL_0_REQ_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_DLAA_PWRDWN_REQ_CONTROL_0_REQ_INIT_ENUM                   PWRDWN
#define PMC_IMPL_PART_DLAA_PWRDWN_REQ_CONTROL_0_REQ_PWRDWN                      MK_ENUM_CONST(1)
#define PMC_IMPL_PART_DLAA_PWRDWN_REQ_CONTROL_0_REQ_PWRUP                       MK_ENUM_CONST(0)


// Register PMC_IMPL_PART_DLAA_PWRDWN_ACK_STATUS_0
#define PMC_IMPL_PART_DLAA_PWRDWN_ACK_STATUS_0                  MK_ADDR_CONST(0x688)
#define PMC_IMPL_PART_DLAA_PWRDWN_ACK_STATUS_0_SECURE                   0x0
#define PMC_IMPL_PART_DLAA_PWRDWN_ACK_STATUS_0_DUAL                     0x0
#define PMC_IMPL_PART_DLAA_PWRDWN_ACK_STATUS_0_SCR                      PG_DLAA_SCR_0
#define PMC_IMPL_PART_DLAA_PWRDWN_ACK_STATUS_0_SCRREG                   PMC_IMPL_SCR_PG_DLAA_SCR_0
#define PMC_IMPL_PART_DLAA_PWRDWN_ACK_STATUS_0_WORD_COUNT                       0x1
#define PMC_IMPL_PART_DLAA_PWRDWN_ACK_STATUS_0_RESET_VAL                        MK_MASK_CONST(0x7)
#define PMC_IMPL_PART_DLAA_PWRDWN_ACK_STATUS_0_RESET_MASK                       MK_MASK_CONST(0x7)
#define PMC_IMPL_PART_DLAA_PWRDWN_ACK_STATUS_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_DLAA_PWRDWN_ACK_STATUS_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_DLAA_PWRDWN_ACK_STATUS_0_READ_MASK                        MK_MASK_CONST(0x7)
#define PMC_IMPL_PART_DLAA_PWRDWN_ACK_STATUS_0_WRITE_MASK                       MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_DLAA_PWRDWN_ACK_STATUS_0_CBB_ACK_SHIFT                    MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_DLAA_PWRDWN_ACK_STATUS_0_CBB_ACK_FIELD                    MK_FIELD_CONST(0x1, PMC_IMPL_PART_DLAA_PWRDWN_ACK_STATUS_0_CBB_ACK_SHIFT)
#define PMC_IMPL_PART_DLAA_PWRDWN_ACK_STATUS_0_CBB_ACK_RANGE                    0:0
#define PMC_IMPL_PART_DLAA_PWRDWN_ACK_STATUS_0_CBB_ACK_MSB                      MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_DLAA_PWRDWN_ACK_STATUS_0_CBB_ACK_LSB                      MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_DLAA_PWRDWN_ACK_STATUS_0_CBB_ACK_WOFFSET                  0x0
#define PMC_IMPL_PART_DLAA_PWRDWN_ACK_STATUS_0_CBB_ACK_DEFAULT                  MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_DLAA_PWRDWN_ACK_STATUS_0_CBB_ACK_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_DLAA_PWRDWN_ACK_STATUS_0_CBB_ACK_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_DLAA_PWRDWN_ACK_STATUS_0_CBB_ACK_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_DLAA_PWRDWN_ACK_STATUS_0_CBB_ACK_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_DLAA_PWRDWN_ACK_STATUS_0_CBB_ACK_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_DLAA_PWRDWN_ACK_STATUS_0_CBB_ACK_INIT_ENUM                        PWRDWN
#define PMC_IMPL_PART_DLAA_PWRDWN_ACK_STATUS_0_CBB_ACK_PWRDWN                   MK_ENUM_CONST(1)
#define PMC_IMPL_PART_DLAA_PWRDWN_ACK_STATUS_0_CBB_ACK_PWRUP                    MK_ENUM_CONST(0)

#define PMC_IMPL_PART_DLAA_PWRDWN_ACK_STATUS_0_DBB_ACK_SHIFT                    MK_SHIFT_CONST(1)
#define PMC_IMPL_PART_DLAA_PWRDWN_ACK_STATUS_0_DBB_ACK_FIELD                    MK_FIELD_CONST(0x1, PMC_IMPL_PART_DLAA_PWRDWN_ACK_STATUS_0_DBB_ACK_SHIFT)
#define PMC_IMPL_PART_DLAA_PWRDWN_ACK_STATUS_0_DBB_ACK_RANGE                    1:1
#define PMC_IMPL_PART_DLAA_PWRDWN_ACK_STATUS_0_DBB_ACK_MSB                      MK_SHIFT_CONST(1)
#define PMC_IMPL_PART_DLAA_PWRDWN_ACK_STATUS_0_DBB_ACK_LSB                      MK_SHIFT_CONST(1)
#define PMC_IMPL_PART_DLAA_PWRDWN_ACK_STATUS_0_DBB_ACK_WOFFSET                  0x0
#define PMC_IMPL_PART_DLAA_PWRDWN_ACK_STATUS_0_DBB_ACK_DEFAULT                  MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_DLAA_PWRDWN_ACK_STATUS_0_DBB_ACK_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_DLAA_PWRDWN_ACK_STATUS_0_DBB_ACK_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_DLAA_PWRDWN_ACK_STATUS_0_DBB_ACK_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_DLAA_PWRDWN_ACK_STATUS_0_DBB_ACK_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_DLAA_PWRDWN_ACK_STATUS_0_DBB_ACK_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_DLAA_PWRDWN_ACK_STATUS_0_DBB_ACK_INIT_ENUM                        PWRDWN
#define PMC_IMPL_PART_DLAA_PWRDWN_ACK_STATUS_0_DBB_ACK_PWRDWN                   MK_ENUM_CONST(1)
#define PMC_IMPL_PART_DLAA_PWRDWN_ACK_STATUS_0_DBB_ACK_PWRUP                    MK_ENUM_CONST(0)

#define PMC_IMPL_PART_DLAA_PWRDWN_ACK_STATUS_0_H1X_ACK_SHIFT                    MK_SHIFT_CONST(2)
#define PMC_IMPL_PART_DLAA_PWRDWN_ACK_STATUS_0_H1X_ACK_FIELD                    MK_FIELD_CONST(0x1, PMC_IMPL_PART_DLAA_PWRDWN_ACK_STATUS_0_H1X_ACK_SHIFT)
#define PMC_IMPL_PART_DLAA_PWRDWN_ACK_STATUS_0_H1X_ACK_RANGE                    2:2
#define PMC_IMPL_PART_DLAA_PWRDWN_ACK_STATUS_0_H1X_ACK_MSB                      MK_SHIFT_CONST(2)
#define PMC_IMPL_PART_DLAA_PWRDWN_ACK_STATUS_0_H1X_ACK_LSB                      MK_SHIFT_CONST(2)
#define PMC_IMPL_PART_DLAA_PWRDWN_ACK_STATUS_0_H1X_ACK_WOFFSET                  0x0
#define PMC_IMPL_PART_DLAA_PWRDWN_ACK_STATUS_0_H1X_ACK_DEFAULT                  MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_DLAA_PWRDWN_ACK_STATUS_0_H1X_ACK_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_DLAA_PWRDWN_ACK_STATUS_0_H1X_ACK_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_DLAA_PWRDWN_ACK_STATUS_0_H1X_ACK_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_DLAA_PWRDWN_ACK_STATUS_0_H1X_ACK_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_DLAA_PWRDWN_ACK_STATUS_0_H1X_ACK_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_DLAA_PWRDWN_ACK_STATUS_0_H1X_ACK_INIT_ENUM                        PWRDWN
#define PMC_IMPL_PART_DLAA_PWRDWN_ACK_STATUS_0_H1X_ACK_PWRDWN                   MK_ENUM_CONST(1)
#define PMC_IMPL_PART_DLAA_PWRDWN_ACK_STATUS_0_H1X_ACK_PWRUP                    MK_ENUM_CONST(0)


// Register PMC_IMPL_PART_DLAB_PWRDWN_REQ_CONTROL_0
#define PMC_IMPL_PART_DLAB_PWRDWN_REQ_CONTROL_0                 MK_ADDR_CONST(0x68c)
#define PMC_IMPL_PART_DLAB_PWRDWN_REQ_CONTROL_0_SECURE                  0x0
#define PMC_IMPL_PART_DLAB_PWRDWN_REQ_CONTROL_0_DUAL                    0x0
#define PMC_IMPL_PART_DLAB_PWRDWN_REQ_CONTROL_0_SCR                     PG_DLAB_SCR_0
#define PMC_IMPL_PART_DLAB_PWRDWN_REQ_CONTROL_0_SCRREG                  PMC_IMPL_SCR_PG_DLAB_SCR_0
#define PMC_IMPL_PART_DLAB_PWRDWN_REQ_CONTROL_0_WORD_COUNT                      0x1
#define PMC_IMPL_PART_DLAB_PWRDWN_REQ_CONTROL_0_RESET_VAL                       MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_DLAB_PWRDWN_REQ_CONTROL_0_RESET_MASK                      MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_DLAB_PWRDWN_REQ_CONTROL_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_DLAB_PWRDWN_REQ_CONTROL_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_DLAB_PWRDWN_REQ_CONTROL_0_READ_MASK                       MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_DLAB_PWRDWN_REQ_CONTROL_0_WRITE_MASK                      MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_DLAB_PWRDWN_REQ_CONTROL_0_REQ_SHIFT                       MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_DLAB_PWRDWN_REQ_CONTROL_0_REQ_FIELD                       MK_FIELD_CONST(0x1, PMC_IMPL_PART_DLAB_PWRDWN_REQ_CONTROL_0_REQ_SHIFT)
#define PMC_IMPL_PART_DLAB_PWRDWN_REQ_CONTROL_0_REQ_RANGE                       0:0
#define PMC_IMPL_PART_DLAB_PWRDWN_REQ_CONTROL_0_REQ_MSB                 MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_DLAB_PWRDWN_REQ_CONTROL_0_REQ_LSB                 MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_DLAB_PWRDWN_REQ_CONTROL_0_REQ_WOFFSET                     0x0
#define PMC_IMPL_PART_DLAB_PWRDWN_REQ_CONTROL_0_REQ_DEFAULT                     MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_DLAB_PWRDWN_REQ_CONTROL_0_REQ_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_DLAB_PWRDWN_REQ_CONTROL_0_REQ_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_DLAB_PWRDWN_REQ_CONTROL_0_REQ_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_DLAB_PWRDWN_REQ_CONTROL_0_REQ_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_DLAB_PWRDWN_REQ_CONTROL_0_REQ_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_DLAB_PWRDWN_REQ_CONTROL_0_REQ_INIT_ENUM                   PWRDWN
#define PMC_IMPL_PART_DLAB_PWRDWN_REQ_CONTROL_0_REQ_PWRDWN                      MK_ENUM_CONST(1)
#define PMC_IMPL_PART_DLAB_PWRDWN_REQ_CONTROL_0_REQ_PWRUP                       MK_ENUM_CONST(0)


// Register PMC_IMPL_PART_DLAB_PWRDWN_ACK_STATUS_0
#define PMC_IMPL_PART_DLAB_PWRDWN_ACK_STATUS_0                  MK_ADDR_CONST(0x690)
#define PMC_IMPL_PART_DLAB_PWRDWN_ACK_STATUS_0_SECURE                   0x0
#define PMC_IMPL_PART_DLAB_PWRDWN_ACK_STATUS_0_DUAL                     0x0
#define PMC_IMPL_PART_DLAB_PWRDWN_ACK_STATUS_0_SCR                      PG_DLAB_SCR_0
#define PMC_IMPL_PART_DLAB_PWRDWN_ACK_STATUS_0_SCRREG                   PMC_IMPL_SCR_PG_DLAB_SCR_0
#define PMC_IMPL_PART_DLAB_PWRDWN_ACK_STATUS_0_WORD_COUNT                       0x1
#define PMC_IMPL_PART_DLAB_PWRDWN_ACK_STATUS_0_RESET_VAL                        MK_MASK_CONST(0x7)
#define PMC_IMPL_PART_DLAB_PWRDWN_ACK_STATUS_0_RESET_MASK                       MK_MASK_CONST(0x7)
#define PMC_IMPL_PART_DLAB_PWRDWN_ACK_STATUS_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_DLAB_PWRDWN_ACK_STATUS_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_DLAB_PWRDWN_ACK_STATUS_0_READ_MASK                        MK_MASK_CONST(0x7)
#define PMC_IMPL_PART_DLAB_PWRDWN_ACK_STATUS_0_WRITE_MASK                       MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_DLAB_PWRDWN_ACK_STATUS_0_CBB_ACK_SHIFT                    MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_DLAB_PWRDWN_ACK_STATUS_0_CBB_ACK_FIELD                    MK_FIELD_CONST(0x1, PMC_IMPL_PART_DLAB_PWRDWN_ACK_STATUS_0_CBB_ACK_SHIFT)
#define PMC_IMPL_PART_DLAB_PWRDWN_ACK_STATUS_0_CBB_ACK_RANGE                    0:0
#define PMC_IMPL_PART_DLAB_PWRDWN_ACK_STATUS_0_CBB_ACK_MSB                      MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_DLAB_PWRDWN_ACK_STATUS_0_CBB_ACK_LSB                      MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_DLAB_PWRDWN_ACK_STATUS_0_CBB_ACK_WOFFSET                  0x0
#define PMC_IMPL_PART_DLAB_PWRDWN_ACK_STATUS_0_CBB_ACK_DEFAULT                  MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_DLAB_PWRDWN_ACK_STATUS_0_CBB_ACK_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_DLAB_PWRDWN_ACK_STATUS_0_CBB_ACK_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_DLAB_PWRDWN_ACK_STATUS_0_CBB_ACK_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_DLAB_PWRDWN_ACK_STATUS_0_CBB_ACK_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_DLAB_PWRDWN_ACK_STATUS_0_CBB_ACK_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_DLAB_PWRDWN_ACK_STATUS_0_CBB_ACK_INIT_ENUM                        PWRDWN
#define PMC_IMPL_PART_DLAB_PWRDWN_ACK_STATUS_0_CBB_ACK_PWRDWN                   MK_ENUM_CONST(1)
#define PMC_IMPL_PART_DLAB_PWRDWN_ACK_STATUS_0_CBB_ACK_PWRUP                    MK_ENUM_CONST(0)

#define PMC_IMPL_PART_DLAB_PWRDWN_ACK_STATUS_0_DBB_ACK_SHIFT                    MK_SHIFT_CONST(1)
#define PMC_IMPL_PART_DLAB_PWRDWN_ACK_STATUS_0_DBB_ACK_FIELD                    MK_FIELD_CONST(0x1, PMC_IMPL_PART_DLAB_PWRDWN_ACK_STATUS_0_DBB_ACK_SHIFT)
#define PMC_IMPL_PART_DLAB_PWRDWN_ACK_STATUS_0_DBB_ACK_RANGE                    1:1
#define PMC_IMPL_PART_DLAB_PWRDWN_ACK_STATUS_0_DBB_ACK_MSB                      MK_SHIFT_CONST(1)
#define PMC_IMPL_PART_DLAB_PWRDWN_ACK_STATUS_0_DBB_ACK_LSB                      MK_SHIFT_CONST(1)
#define PMC_IMPL_PART_DLAB_PWRDWN_ACK_STATUS_0_DBB_ACK_WOFFSET                  0x0
#define PMC_IMPL_PART_DLAB_PWRDWN_ACK_STATUS_0_DBB_ACK_DEFAULT                  MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_DLAB_PWRDWN_ACK_STATUS_0_DBB_ACK_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_DLAB_PWRDWN_ACK_STATUS_0_DBB_ACK_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_DLAB_PWRDWN_ACK_STATUS_0_DBB_ACK_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_DLAB_PWRDWN_ACK_STATUS_0_DBB_ACK_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_DLAB_PWRDWN_ACK_STATUS_0_DBB_ACK_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_DLAB_PWRDWN_ACK_STATUS_0_DBB_ACK_INIT_ENUM                        PWRDWN
#define PMC_IMPL_PART_DLAB_PWRDWN_ACK_STATUS_0_DBB_ACK_PWRDWN                   MK_ENUM_CONST(1)
#define PMC_IMPL_PART_DLAB_PWRDWN_ACK_STATUS_0_DBB_ACK_PWRUP                    MK_ENUM_CONST(0)

#define PMC_IMPL_PART_DLAB_PWRDWN_ACK_STATUS_0_H1X_ACK_SHIFT                    MK_SHIFT_CONST(2)
#define PMC_IMPL_PART_DLAB_PWRDWN_ACK_STATUS_0_H1X_ACK_FIELD                    MK_FIELD_CONST(0x1, PMC_IMPL_PART_DLAB_PWRDWN_ACK_STATUS_0_H1X_ACK_SHIFT)
#define PMC_IMPL_PART_DLAB_PWRDWN_ACK_STATUS_0_H1X_ACK_RANGE                    2:2
#define PMC_IMPL_PART_DLAB_PWRDWN_ACK_STATUS_0_H1X_ACK_MSB                      MK_SHIFT_CONST(2)
#define PMC_IMPL_PART_DLAB_PWRDWN_ACK_STATUS_0_H1X_ACK_LSB                      MK_SHIFT_CONST(2)
#define PMC_IMPL_PART_DLAB_PWRDWN_ACK_STATUS_0_H1X_ACK_WOFFSET                  0x0
#define PMC_IMPL_PART_DLAB_PWRDWN_ACK_STATUS_0_H1X_ACK_DEFAULT                  MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_DLAB_PWRDWN_ACK_STATUS_0_H1X_ACK_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_DLAB_PWRDWN_ACK_STATUS_0_H1X_ACK_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_DLAB_PWRDWN_ACK_STATUS_0_H1X_ACK_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_DLAB_PWRDWN_ACK_STATUS_0_H1X_ACK_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_DLAB_PWRDWN_ACK_STATUS_0_H1X_ACK_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_DLAB_PWRDWN_ACK_STATUS_0_H1X_ACK_INIT_ENUM                        PWRDWN
#define PMC_IMPL_PART_DLAB_PWRDWN_ACK_STATUS_0_H1X_ACK_PWRDWN                   MK_ENUM_CONST(1)
#define PMC_IMPL_PART_DLAB_PWRDWN_ACK_STATUS_0_H1X_ACK_PWRUP                    MK_ENUM_CONST(0)


// Register PMC_IMPL_PART_OFA_PWRDWN_REQ_CONTROL_0
#define PMC_IMPL_PART_OFA_PWRDWN_REQ_CONTROL_0                  MK_ADDR_CONST(0x694)
#define PMC_IMPL_PART_OFA_PWRDWN_REQ_CONTROL_0_SECURE                   0x0
#define PMC_IMPL_PART_OFA_PWRDWN_REQ_CONTROL_0_DUAL                     0x0
#define PMC_IMPL_PART_OFA_PWRDWN_REQ_CONTROL_0_SCR                      PG_OFA_SCR_0
#define PMC_IMPL_PART_OFA_PWRDWN_REQ_CONTROL_0_SCRREG                   PMC_IMPL_SCR_PG_OFA_SCR_0
#define PMC_IMPL_PART_OFA_PWRDWN_REQ_CONTROL_0_WORD_COUNT                       0x1
#define PMC_IMPL_PART_OFA_PWRDWN_REQ_CONTROL_0_RESET_VAL                        MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_OFA_PWRDWN_REQ_CONTROL_0_RESET_MASK                       MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_OFA_PWRDWN_REQ_CONTROL_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_OFA_PWRDWN_REQ_CONTROL_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_OFA_PWRDWN_REQ_CONTROL_0_READ_MASK                        MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_OFA_PWRDWN_REQ_CONTROL_0_WRITE_MASK                       MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_OFA_PWRDWN_REQ_CONTROL_0_REQ_SHIFT                        MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_OFA_PWRDWN_REQ_CONTROL_0_REQ_FIELD                        MK_FIELD_CONST(0x1, PMC_IMPL_PART_OFA_PWRDWN_REQ_CONTROL_0_REQ_SHIFT)
#define PMC_IMPL_PART_OFA_PWRDWN_REQ_CONTROL_0_REQ_RANGE                        0:0
#define PMC_IMPL_PART_OFA_PWRDWN_REQ_CONTROL_0_REQ_MSB                  MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_OFA_PWRDWN_REQ_CONTROL_0_REQ_LSB                  MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_OFA_PWRDWN_REQ_CONTROL_0_REQ_WOFFSET                      0x0
#define PMC_IMPL_PART_OFA_PWRDWN_REQ_CONTROL_0_REQ_DEFAULT                      MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_OFA_PWRDWN_REQ_CONTROL_0_REQ_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_OFA_PWRDWN_REQ_CONTROL_0_REQ_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_OFA_PWRDWN_REQ_CONTROL_0_REQ_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_OFA_PWRDWN_REQ_CONTROL_0_REQ_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_OFA_PWRDWN_REQ_CONTROL_0_REQ_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_OFA_PWRDWN_REQ_CONTROL_0_REQ_INIT_ENUM                    PWRDWN
#define PMC_IMPL_PART_OFA_PWRDWN_REQ_CONTROL_0_REQ_PWRDWN                       MK_ENUM_CONST(1)
#define PMC_IMPL_PART_OFA_PWRDWN_REQ_CONTROL_0_REQ_PWRUP                        MK_ENUM_CONST(0)


// Register PMC_IMPL_PART_OFA_PWRDWN_ACK_STATUS_0
#define PMC_IMPL_PART_OFA_PWRDWN_ACK_STATUS_0                   MK_ADDR_CONST(0x698)
#define PMC_IMPL_PART_OFA_PWRDWN_ACK_STATUS_0_SECURE                    0x0
#define PMC_IMPL_PART_OFA_PWRDWN_ACK_STATUS_0_DUAL                      0x0
#define PMC_IMPL_PART_OFA_PWRDWN_ACK_STATUS_0_SCR                       PG_OFA_SCR_0
#define PMC_IMPL_PART_OFA_PWRDWN_ACK_STATUS_0_SCRREG                    PMC_IMPL_SCR_PG_OFA_SCR_0
#define PMC_IMPL_PART_OFA_PWRDWN_ACK_STATUS_0_WORD_COUNT                        0x1
#define PMC_IMPL_PART_OFA_PWRDWN_ACK_STATUS_0_RESET_VAL                         MK_MASK_CONST(0x7)
#define PMC_IMPL_PART_OFA_PWRDWN_ACK_STATUS_0_RESET_MASK                        MK_MASK_CONST(0x7)
#define PMC_IMPL_PART_OFA_PWRDWN_ACK_STATUS_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_OFA_PWRDWN_ACK_STATUS_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_OFA_PWRDWN_ACK_STATUS_0_READ_MASK                         MK_MASK_CONST(0x7)
#define PMC_IMPL_PART_OFA_PWRDWN_ACK_STATUS_0_WRITE_MASK                        MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_OFA_PWRDWN_ACK_STATUS_0_CBB_ACK_SHIFT                     MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_OFA_PWRDWN_ACK_STATUS_0_CBB_ACK_FIELD                     MK_FIELD_CONST(0x1, PMC_IMPL_PART_OFA_PWRDWN_ACK_STATUS_0_CBB_ACK_SHIFT)
#define PMC_IMPL_PART_OFA_PWRDWN_ACK_STATUS_0_CBB_ACK_RANGE                     0:0
#define PMC_IMPL_PART_OFA_PWRDWN_ACK_STATUS_0_CBB_ACK_MSB                       MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_OFA_PWRDWN_ACK_STATUS_0_CBB_ACK_LSB                       MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_OFA_PWRDWN_ACK_STATUS_0_CBB_ACK_WOFFSET                   0x0
#define PMC_IMPL_PART_OFA_PWRDWN_ACK_STATUS_0_CBB_ACK_DEFAULT                   MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_OFA_PWRDWN_ACK_STATUS_0_CBB_ACK_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_OFA_PWRDWN_ACK_STATUS_0_CBB_ACK_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_OFA_PWRDWN_ACK_STATUS_0_CBB_ACK_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_OFA_PWRDWN_ACK_STATUS_0_CBB_ACK_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_OFA_PWRDWN_ACK_STATUS_0_CBB_ACK_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_OFA_PWRDWN_ACK_STATUS_0_CBB_ACK_INIT_ENUM                 PWRDWN
#define PMC_IMPL_PART_OFA_PWRDWN_ACK_STATUS_0_CBB_ACK_PWRDWN                    MK_ENUM_CONST(1)
#define PMC_IMPL_PART_OFA_PWRDWN_ACK_STATUS_0_CBB_ACK_PWRUP                     MK_ENUM_CONST(0)

#define PMC_IMPL_PART_OFA_PWRDWN_ACK_STATUS_0_DBB_ACK_SHIFT                     MK_SHIFT_CONST(1)
#define PMC_IMPL_PART_OFA_PWRDWN_ACK_STATUS_0_DBB_ACK_FIELD                     MK_FIELD_CONST(0x1, PMC_IMPL_PART_OFA_PWRDWN_ACK_STATUS_0_DBB_ACK_SHIFT)
#define PMC_IMPL_PART_OFA_PWRDWN_ACK_STATUS_0_DBB_ACK_RANGE                     1:1
#define PMC_IMPL_PART_OFA_PWRDWN_ACK_STATUS_0_DBB_ACK_MSB                       MK_SHIFT_CONST(1)
#define PMC_IMPL_PART_OFA_PWRDWN_ACK_STATUS_0_DBB_ACK_LSB                       MK_SHIFT_CONST(1)
#define PMC_IMPL_PART_OFA_PWRDWN_ACK_STATUS_0_DBB_ACK_WOFFSET                   0x0
#define PMC_IMPL_PART_OFA_PWRDWN_ACK_STATUS_0_DBB_ACK_DEFAULT                   MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_OFA_PWRDWN_ACK_STATUS_0_DBB_ACK_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_OFA_PWRDWN_ACK_STATUS_0_DBB_ACK_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_OFA_PWRDWN_ACK_STATUS_0_DBB_ACK_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_OFA_PWRDWN_ACK_STATUS_0_DBB_ACK_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_OFA_PWRDWN_ACK_STATUS_0_DBB_ACK_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_OFA_PWRDWN_ACK_STATUS_0_DBB_ACK_INIT_ENUM                 PWRDWN
#define PMC_IMPL_PART_OFA_PWRDWN_ACK_STATUS_0_DBB_ACK_PWRDWN                    MK_ENUM_CONST(1)
#define PMC_IMPL_PART_OFA_PWRDWN_ACK_STATUS_0_DBB_ACK_PWRUP                     MK_ENUM_CONST(0)

#define PMC_IMPL_PART_OFA_PWRDWN_ACK_STATUS_0_H1X_ACK_SHIFT                     MK_SHIFT_CONST(2)
#define PMC_IMPL_PART_OFA_PWRDWN_ACK_STATUS_0_H1X_ACK_FIELD                     MK_FIELD_CONST(0x1, PMC_IMPL_PART_OFA_PWRDWN_ACK_STATUS_0_H1X_ACK_SHIFT)
#define PMC_IMPL_PART_OFA_PWRDWN_ACK_STATUS_0_H1X_ACK_RANGE                     2:2
#define PMC_IMPL_PART_OFA_PWRDWN_ACK_STATUS_0_H1X_ACK_MSB                       MK_SHIFT_CONST(2)
#define PMC_IMPL_PART_OFA_PWRDWN_ACK_STATUS_0_H1X_ACK_LSB                       MK_SHIFT_CONST(2)
#define PMC_IMPL_PART_OFA_PWRDWN_ACK_STATUS_0_H1X_ACK_WOFFSET                   0x0
#define PMC_IMPL_PART_OFA_PWRDWN_ACK_STATUS_0_H1X_ACK_DEFAULT                   MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_OFA_PWRDWN_ACK_STATUS_0_H1X_ACK_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_OFA_PWRDWN_ACK_STATUS_0_H1X_ACK_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_OFA_PWRDWN_ACK_STATUS_0_H1X_ACK_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_OFA_PWRDWN_ACK_STATUS_0_H1X_ACK_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_OFA_PWRDWN_ACK_STATUS_0_H1X_ACK_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_OFA_PWRDWN_ACK_STATUS_0_H1X_ACK_INIT_ENUM                 PWRDWN
#define PMC_IMPL_PART_OFA_PWRDWN_ACK_STATUS_0_H1X_ACK_PWRDWN                    MK_ENUM_CONST(1)
#define PMC_IMPL_PART_OFA_PWRDWN_ACK_STATUS_0_H1X_ACK_PWRUP                     MK_ENUM_CONST(0)


// Register PMC_IMPL_PART_MGBEA_PWRDWN_REQ_CONTROL_0
#define PMC_IMPL_PART_MGBEA_PWRDWN_REQ_CONTROL_0                        MK_ADDR_CONST(0x69c)
#define PMC_IMPL_PART_MGBEA_PWRDWN_REQ_CONTROL_0_SECURE                         0x0
#define PMC_IMPL_PART_MGBEA_PWRDWN_REQ_CONTROL_0_DUAL                   0x0
#define PMC_IMPL_PART_MGBEA_PWRDWN_REQ_CONTROL_0_SCR                    PG_MGBEA_SCR_0
#define PMC_IMPL_PART_MGBEA_PWRDWN_REQ_CONTROL_0_SCRREG                         PMC_IMPL_SCR_PG_MGBEA_SCR_0
#define PMC_IMPL_PART_MGBEA_PWRDWN_REQ_CONTROL_0_WORD_COUNT                     0x1
#define PMC_IMPL_PART_MGBEA_PWRDWN_REQ_CONTROL_0_RESET_VAL                      MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_MGBEA_PWRDWN_REQ_CONTROL_0_RESET_MASK                     MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_MGBEA_PWRDWN_REQ_CONTROL_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_MGBEA_PWRDWN_REQ_CONTROL_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_MGBEA_PWRDWN_REQ_CONTROL_0_READ_MASK                      MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_MGBEA_PWRDWN_REQ_CONTROL_0_WRITE_MASK                     MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_MGBEA_PWRDWN_REQ_CONTROL_0_REQ_SHIFT                      MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_MGBEA_PWRDWN_REQ_CONTROL_0_REQ_FIELD                      MK_FIELD_CONST(0x1, PMC_IMPL_PART_MGBEA_PWRDWN_REQ_CONTROL_0_REQ_SHIFT)
#define PMC_IMPL_PART_MGBEA_PWRDWN_REQ_CONTROL_0_REQ_RANGE                      0:0
#define PMC_IMPL_PART_MGBEA_PWRDWN_REQ_CONTROL_0_REQ_MSB                        MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_MGBEA_PWRDWN_REQ_CONTROL_0_REQ_LSB                        MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_MGBEA_PWRDWN_REQ_CONTROL_0_REQ_WOFFSET                    0x0
#define PMC_IMPL_PART_MGBEA_PWRDWN_REQ_CONTROL_0_REQ_DEFAULT                    MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_MGBEA_PWRDWN_REQ_CONTROL_0_REQ_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_MGBEA_PWRDWN_REQ_CONTROL_0_REQ_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_MGBEA_PWRDWN_REQ_CONTROL_0_REQ_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_MGBEA_PWRDWN_REQ_CONTROL_0_REQ_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_MGBEA_PWRDWN_REQ_CONTROL_0_REQ_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_MGBEA_PWRDWN_REQ_CONTROL_0_REQ_INIT_ENUM                  PWRDWN
#define PMC_IMPL_PART_MGBEA_PWRDWN_REQ_CONTROL_0_REQ_PWRDWN                     MK_ENUM_CONST(1)
#define PMC_IMPL_PART_MGBEA_PWRDWN_REQ_CONTROL_0_REQ_PWRUP                      MK_ENUM_CONST(0)


// Register PMC_IMPL_PART_MGBEA_PWRDWN_ACK_STATUS_0
#define PMC_IMPL_PART_MGBEA_PWRDWN_ACK_STATUS_0                 MK_ADDR_CONST(0x6a0)
#define PMC_IMPL_PART_MGBEA_PWRDWN_ACK_STATUS_0_SECURE                  0x0
#define PMC_IMPL_PART_MGBEA_PWRDWN_ACK_STATUS_0_DUAL                    0x0
#define PMC_IMPL_PART_MGBEA_PWRDWN_ACK_STATUS_0_SCR                     PG_MGBEA_SCR_0
#define PMC_IMPL_PART_MGBEA_PWRDWN_ACK_STATUS_0_SCRREG                  PMC_IMPL_SCR_PG_MGBEA_SCR_0
#define PMC_IMPL_PART_MGBEA_PWRDWN_ACK_STATUS_0_WORD_COUNT                      0x1
#define PMC_IMPL_PART_MGBEA_PWRDWN_ACK_STATUS_0_RESET_VAL                       MK_MASK_CONST(0x7)
#define PMC_IMPL_PART_MGBEA_PWRDWN_ACK_STATUS_0_RESET_MASK                      MK_MASK_CONST(0x7)
#define PMC_IMPL_PART_MGBEA_PWRDWN_ACK_STATUS_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_MGBEA_PWRDWN_ACK_STATUS_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_MGBEA_PWRDWN_ACK_STATUS_0_READ_MASK                       MK_MASK_CONST(0x7)
#define PMC_IMPL_PART_MGBEA_PWRDWN_ACK_STATUS_0_WRITE_MASK                      MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_MGBEA_PWRDWN_ACK_STATUS_0_CBB_ACK_SHIFT                   MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_MGBEA_PWRDWN_ACK_STATUS_0_CBB_ACK_FIELD                   MK_FIELD_CONST(0x1, PMC_IMPL_PART_MGBEA_PWRDWN_ACK_STATUS_0_CBB_ACK_SHIFT)
#define PMC_IMPL_PART_MGBEA_PWRDWN_ACK_STATUS_0_CBB_ACK_RANGE                   0:0
#define PMC_IMPL_PART_MGBEA_PWRDWN_ACK_STATUS_0_CBB_ACK_MSB                     MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_MGBEA_PWRDWN_ACK_STATUS_0_CBB_ACK_LSB                     MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_MGBEA_PWRDWN_ACK_STATUS_0_CBB_ACK_WOFFSET                 0x0
#define PMC_IMPL_PART_MGBEA_PWRDWN_ACK_STATUS_0_CBB_ACK_DEFAULT                 MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_MGBEA_PWRDWN_ACK_STATUS_0_CBB_ACK_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_MGBEA_PWRDWN_ACK_STATUS_0_CBB_ACK_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_MGBEA_PWRDWN_ACK_STATUS_0_CBB_ACK_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_MGBEA_PWRDWN_ACK_STATUS_0_CBB_ACK_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_MGBEA_PWRDWN_ACK_STATUS_0_CBB_ACK_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_MGBEA_PWRDWN_ACK_STATUS_0_CBB_ACK_INIT_ENUM                       PWRDWN
#define PMC_IMPL_PART_MGBEA_PWRDWN_ACK_STATUS_0_CBB_ACK_PWRDWN                  MK_ENUM_CONST(1)
#define PMC_IMPL_PART_MGBEA_PWRDWN_ACK_STATUS_0_CBB_ACK_PWRUP                   MK_ENUM_CONST(0)

#define PMC_IMPL_PART_MGBEA_PWRDWN_ACK_STATUS_0_DBB_ACK_SHIFT                   MK_SHIFT_CONST(1)
#define PMC_IMPL_PART_MGBEA_PWRDWN_ACK_STATUS_0_DBB_ACK_FIELD                   MK_FIELD_CONST(0x1, PMC_IMPL_PART_MGBEA_PWRDWN_ACK_STATUS_0_DBB_ACK_SHIFT)
#define PMC_IMPL_PART_MGBEA_PWRDWN_ACK_STATUS_0_DBB_ACK_RANGE                   1:1
#define PMC_IMPL_PART_MGBEA_PWRDWN_ACK_STATUS_0_DBB_ACK_MSB                     MK_SHIFT_CONST(1)
#define PMC_IMPL_PART_MGBEA_PWRDWN_ACK_STATUS_0_DBB_ACK_LSB                     MK_SHIFT_CONST(1)
#define PMC_IMPL_PART_MGBEA_PWRDWN_ACK_STATUS_0_DBB_ACK_WOFFSET                 0x0
#define PMC_IMPL_PART_MGBEA_PWRDWN_ACK_STATUS_0_DBB_ACK_DEFAULT                 MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_MGBEA_PWRDWN_ACK_STATUS_0_DBB_ACK_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_MGBEA_PWRDWN_ACK_STATUS_0_DBB_ACK_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_MGBEA_PWRDWN_ACK_STATUS_0_DBB_ACK_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_MGBEA_PWRDWN_ACK_STATUS_0_DBB_ACK_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_MGBEA_PWRDWN_ACK_STATUS_0_DBB_ACK_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_MGBEA_PWRDWN_ACK_STATUS_0_DBB_ACK_INIT_ENUM                       PWRDWN
#define PMC_IMPL_PART_MGBEA_PWRDWN_ACK_STATUS_0_DBB_ACK_PWRDWN                  MK_ENUM_CONST(1)
#define PMC_IMPL_PART_MGBEA_PWRDWN_ACK_STATUS_0_DBB_ACK_PWRUP                   MK_ENUM_CONST(0)

#define PMC_IMPL_PART_MGBEA_PWRDWN_ACK_STATUS_0_H1X_ACK_SHIFT                   MK_SHIFT_CONST(2)
#define PMC_IMPL_PART_MGBEA_PWRDWN_ACK_STATUS_0_H1X_ACK_FIELD                   MK_FIELD_CONST(0x1, PMC_IMPL_PART_MGBEA_PWRDWN_ACK_STATUS_0_H1X_ACK_SHIFT)
#define PMC_IMPL_PART_MGBEA_PWRDWN_ACK_STATUS_0_H1X_ACK_RANGE                   2:2
#define PMC_IMPL_PART_MGBEA_PWRDWN_ACK_STATUS_0_H1X_ACK_MSB                     MK_SHIFT_CONST(2)
#define PMC_IMPL_PART_MGBEA_PWRDWN_ACK_STATUS_0_H1X_ACK_LSB                     MK_SHIFT_CONST(2)
#define PMC_IMPL_PART_MGBEA_PWRDWN_ACK_STATUS_0_H1X_ACK_WOFFSET                 0x0
#define PMC_IMPL_PART_MGBEA_PWRDWN_ACK_STATUS_0_H1X_ACK_DEFAULT                 MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_MGBEA_PWRDWN_ACK_STATUS_0_H1X_ACK_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_MGBEA_PWRDWN_ACK_STATUS_0_H1X_ACK_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_MGBEA_PWRDWN_ACK_STATUS_0_H1X_ACK_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_MGBEA_PWRDWN_ACK_STATUS_0_H1X_ACK_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_MGBEA_PWRDWN_ACK_STATUS_0_H1X_ACK_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_MGBEA_PWRDWN_ACK_STATUS_0_H1X_ACK_INIT_ENUM                       PWRDWN
#define PMC_IMPL_PART_MGBEA_PWRDWN_ACK_STATUS_0_H1X_ACK_PWRDWN                  MK_ENUM_CONST(1)
#define PMC_IMPL_PART_MGBEA_PWRDWN_ACK_STATUS_0_H1X_ACK_PWRUP                   MK_ENUM_CONST(0)


// Register PMC_IMPL_PART_MGBEBA_PWRDWN_REQ_CONTROL_0
#define PMC_IMPL_PART_MGBEBA_PWRDWN_REQ_CONTROL_0                       MK_ADDR_CONST(0x6a4)
#define PMC_IMPL_PART_MGBEBA_PWRDWN_REQ_CONTROL_0_SECURE                        0x0
#define PMC_IMPL_PART_MGBEBA_PWRDWN_REQ_CONTROL_0_DUAL                  0x0
#define PMC_IMPL_PART_MGBEBA_PWRDWN_REQ_CONTROL_0_SCR                   PG_MGBEBA_SCR_0
#define PMC_IMPL_PART_MGBEBA_PWRDWN_REQ_CONTROL_0_SCRREG                        PMC_IMPL_SCR_PG_MGBEBA_SCR_0
#define PMC_IMPL_PART_MGBEBA_PWRDWN_REQ_CONTROL_0_WORD_COUNT                    0x1
#define PMC_IMPL_PART_MGBEBA_PWRDWN_REQ_CONTROL_0_RESET_VAL                     MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_MGBEBA_PWRDWN_REQ_CONTROL_0_RESET_MASK                    MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_MGBEBA_PWRDWN_REQ_CONTROL_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_MGBEBA_PWRDWN_REQ_CONTROL_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_MGBEBA_PWRDWN_REQ_CONTROL_0_READ_MASK                     MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_MGBEBA_PWRDWN_REQ_CONTROL_0_WRITE_MASK                    MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_MGBEBA_PWRDWN_REQ_CONTROL_0_REQ_SHIFT                     MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_MGBEBA_PWRDWN_REQ_CONTROL_0_REQ_FIELD                     MK_FIELD_CONST(0x1, PMC_IMPL_PART_MGBEBA_PWRDWN_REQ_CONTROL_0_REQ_SHIFT)
#define PMC_IMPL_PART_MGBEBA_PWRDWN_REQ_CONTROL_0_REQ_RANGE                     0:0
#define PMC_IMPL_PART_MGBEBA_PWRDWN_REQ_CONTROL_0_REQ_MSB                       MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_MGBEBA_PWRDWN_REQ_CONTROL_0_REQ_LSB                       MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_MGBEBA_PWRDWN_REQ_CONTROL_0_REQ_WOFFSET                   0x0
#define PMC_IMPL_PART_MGBEBA_PWRDWN_REQ_CONTROL_0_REQ_DEFAULT                   MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_MGBEBA_PWRDWN_REQ_CONTROL_0_REQ_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_MGBEBA_PWRDWN_REQ_CONTROL_0_REQ_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_MGBEBA_PWRDWN_REQ_CONTROL_0_REQ_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_MGBEBA_PWRDWN_REQ_CONTROL_0_REQ_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_MGBEBA_PWRDWN_REQ_CONTROL_0_REQ_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_MGBEBA_PWRDWN_REQ_CONTROL_0_REQ_INIT_ENUM                 PWRDWN
#define PMC_IMPL_PART_MGBEBA_PWRDWN_REQ_CONTROL_0_REQ_PWRDWN                    MK_ENUM_CONST(1)
#define PMC_IMPL_PART_MGBEBA_PWRDWN_REQ_CONTROL_0_REQ_PWRUP                     MK_ENUM_CONST(0)


// Register PMC_IMPL_PART_MGBEBA_PWRDWN_ACK_STATUS_0
#define PMC_IMPL_PART_MGBEBA_PWRDWN_ACK_STATUS_0                        MK_ADDR_CONST(0x6a8)
#define PMC_IMPL_PART_MGBEBA_PWRDWN_ACK_STATUS_0_SECURE                         0x0
#define PMC_IMPL_PART_MGBEBA_PWRDWN_ACK_STATUS_0_DUAL                   0x0
#define PMC_IMPL_PART_MGBEBA_PWRDWN_ACK_STATUS_0_SCR                    PG_MGBEBA_SCR_0
#define PMC_IMPL_PART_MGBEBA_PWRDWN_ACK_STATUS_0_SCRREG                         PMC_IMPL_SCR_PG_MGBEBA_SCR_0
#define PMC_IMPL_PART_MGBEBA_PWRDWN_ACK_STATUS_0_WORD_COUNT                     0x1
#define PMC_IMPL_PART_MGBEBA_PWRDWN_ACK_STATUS_0_RESET_VAL                      MK_MASK_CONST(0x7)
#define PMC_IMPL_PART_MGBEBA_PWRDWN_ACK_STATUS_0_RESET_MASK                     MK_MASK_CONST(0x7)
#define PMC_IMPL_PART_MGBEBA_PWRDWN_ACK_STATUS_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_MGBEBA_PWRDWN_ACK_STATUS_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_MGBEBA_PWRDWN_ACK_STATUS_0_READ_MASK                      MK_MASK_CONST(0x7)
#define PMC_IMPL_PART_MGBEBA_PWRDWN_ACK_STATUS_0_WRITE_MASK                     MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_MGBEBA_PWRDWN_ACK_STATUS_0_CBB_ACK_SHIFT                  MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_MGBEBA_PWRDWN_ACK_STATUS_0_CBB_ACK_FIELD                  MK_FIELD_CONST(0x1, PMC_IMPL_PART_MGBEBA_PWRDWN_ACK_STATUS_0_CBB_ACK_SHIFT)
#define PMC_IMPL_PART_MGBEBA_PWRDWN_ACK_STATUS_0_CBB_ACK_RANGE                  0:0
#define PMC_IMPL_PART_MGBEBA_PWRDWN_ACK_STATUS_0_CBB_ACK_MSB                    MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_MGBEBA_PWRDWN_ACK_STATUS_0_CBB_ACK_LSB                    MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_MGBEBA_PWRDWN_ACK_STATUS_0_CBB_ACK_WOFFSET                        0x0
#define PMC_IMPL_PART_MGBEBA_PWRDWN_ACK_STATUS_0_CBB_ACK_DEFAULT                        MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_MGBEBA_PWRDWN_ACK_STATUS_0_CBB_ACK_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_MGBEBA_PWRDWN_ACK_STATUS_0_CBB_ACK_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_MGBEBA_PWRDWN_ACK_STATUS_0_CBB_ACK_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_MGBEBA_PWRDWN_ACK_STATUS_0_CBB_ACK_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_MGBEBA_PWRDWN_ACK_STATUS_0_CBB_ACK_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_MGBEBA_PWRDWN_ACK_STATUS_0_CBB_ACK_INIT_ENUM                      PWRDWN
#define PMC_IMPL_PART_MGBEBA_PWRDWN_ACK_STATUS_0_CBB_ACK_PWRDWN                 MK_ENUM_CONST(1)
#define PMC_IMPL_PART_MGBEBA_PWRDWN_ACK_STATUS_0_CBB_ACK_PWRUP                  MK_ENUM_CONST(0)

#define PMC_IMPL_PART_MGBEBA_PWRDWN_ACK_STATUS_0_DBB_ACK_SHIFT                  MK_SHIFT_CONST(1)
#define PMC_IMPL_PART_MGBEBA_PWRDWN_ACK_STATUS_0_DBB_ACK_FIELD                  MK_FIELD_CONST(0x1, PMC_IMPL_PART_MGBEBA_PWRDWN_ACK_STATUS_0_DBB_ACK_SHIFT)
#define PMC_IMPL_PART_MGBEBA_PWRDWN_ACK_STATUS_0_DBB_ACK_RANGE                  1:1
#define PMC_IMPL_PART_MGBEBA_PWRDWN_ACK_STATUS_0_DBB_ACK_MSB                    MK_SHIFT_CONST(1)
#define PMC_IMPL_PART_MGBEBA_PWRDWN_ACK_STATUS_0_DBB_ACK_LSB                    MK_SHIFT_CONST(1)
#define PMC_IMPL_PART_MGBEBA_PWRDWN_ACK_STATUS_0_DBB_ACK_WOFFSET                        0x0
#define PMC_IMPL_PART_MGBEBA_PWRDWN_ACK_STATUS_0_DBB_ACK_DEFAULT                        MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_MGBEBA_PWRDWN_ACK_STATUS_0_DBB_ACK_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_MGBEBA_PWRDWN_ACK_STATUS_0_DBB_ACK_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_MGBEBA_PWRDWN_ACK_STATUS_0_DBB_ACK_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_MGBEBA_PWRDWN_ACK_STATUS_0_DBB_ACK_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_MGBEBA_PWRDWN_ACK_STATUS_0_DBB_ACK_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_MGBEBA_PWRDWN_ACK_STATUS_0_DBB_ACK_INIT_ENUM                      PWRDWN
#define PMC_IMPL_PART_MGBEBA_PWRDWN_ACK_STATUS_0_DBB_ACK_PWRDWN                 MK_ENUM_CONST(1)
#define PMC_IMPL_PART_MGBEBA_PWRDWN_ACK_STATUS_0_DBB_ACK_PWRUP                  MK_ENUM_CONST(0)

#define PMC_IMPL_PART_MGBEBA_PWRDWN_ACK_STATUS_0_H1X_ACK_SHIFT                  MK_SHIFT_CONST(2)
#define PMC_IMPL_PART_MGBEBA_PWRDWN_ACK_STATUS_0_H1X_ACK_FIELD                  MK_FIELD_CONST(0x1, PMC_IMPL_PART_MGBEBA_PWRDWN_ACK_STATUS_0_H1X_ACK_SHIFT)
#define PMC_IMPL_PART_MGBEBA_PWRDWN_ACK_STATUS_0_H1X_ACK_RANGE                  2:2
#define PMC_IMPL_PART_MGBEBA_PWRDWN_ACK_STATUS_0_H1X_ACK_MSB                    MK_SHIFT_CONST(2)
#define PMC_IMPL_PART_MGBEBA_PWRDWN_ACK_STATUS_0_H1X_ACK_LSB                    MK_SHIFT_CONST(2)
#define PMC_IMPL_PART_MGBEBA_PWRDWN_ACK_STATUS_0_H1X_ACK_WOFFSET                        0x0
#define PMC_IMPL_PART_MGBEBA_PWRDWN_ACK_STATUS_0_H1X_ACK_DEFAULT                        MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_MGBEBA_PWRDWN_ACK_STATUS_0_H1X_ACK_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_MGBEBA_PWRDWN_ACK_STATUS_0_H1X_ACK_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_MGBEBA_PWRDWN_ACK_STATUS_0_H1X_ACK_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_MGBEBA_PWRDWN_ACK_STATUS_0_H1X_ACK_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_MGBEBA_PWRDWN_ACK_STATUS_0_H1X_ACK_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_MGBEBA_PWRDWN_ACK_STATUS_0_H1X_ACK_INIT_ENUM                      PWRDWN
#define PMC_IMPL_PART_MGBEBA_PWRDWN_ACK_STATUS_0_H1X_ACK_PWRDWN                 MK_ENUM_CONST(1)
#define PMC_IMPL_PART_MGBEBA_PWRDWN_ACK_STATUS_0_H1X_ACK_PWRUP                  MK_ENUM_CONST(0)


// Register PMC_IMPL_PART_MGBEBB_PWRDWN_REQ_CONTROL_0
#define PMC_IMPL_PART_MGBEBB_PWRDWN_REQ_CONTROL_0                       MK_ADDR_CONST(0x6ac)
#define PMC_IMPL_PART_MGBEBB_PWRDWN_REQ_CONTROL_0_SECURE                        0x0
#define PMC_IMPL_PART_MGBEBB_PWRDWN_REQ_CONTROL_0_DUAL                  0x0
#define PMC_IMPL_PART_MGBEBB_PWRDWN_REQ_CONTROL_0_SCR                   PG_MGBEBB_SCR_0
#define PMC_IMPL_PART_MGBEBB_PWRDWN_REQ_CONTROL_0_SCRREG                        PMC_IMPL_SCR_PG_MGBEBB_SCR_0
#define PMC_IMPL_PART_MGBEBB_PWRDWN_REQ_CONTROL_0_WORD_COUNT                    0x1
#define PMC_IMPL_PART_MGBEBB_PWRDWN_REQ_CONTROL_0_RESET_VAL                     MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_MGBEBB_PWRDWN_REQ_CONTROL_0_RESET_MASK                    MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_MGBEBB_PWRDWN_REQ_CONTROL_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_MGBEBB_PWRDWN_REQ_CONTROL_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_MGBEBB_PWRDWN_REQ_CONTROL_0_READ_MASK                     MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_MGBEBB_PWRDWN_REQ_CONTROL_0_WRITE_MASK                    MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_MGBEBB_PWRDWN_REQ_CONTROL_0_REQ_SHIFT                     MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_MGBEBB_PWRDWN_REQ_CONTROL_0_REQ_FIELD                     MK_FIELD_CONST(0x1, PMC_IMPL_PART_MGBEBB_PWRDWN_REQ_CONTROL_0_REQ_SHIFT)
#define PMC_IMPL_PART_MGBEBB_PWRDWN_REQ_CONTROL_0_REQ_RANGE                     0:0
#define PMC_IMPL_PART_MGBEBB_PWRDWN_REQ_CONTROL_0_REQ_MSB                       MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_MGBEBB_PWRDWN_REQ_CONTROL_0_REQ_LSB                       MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_MGBEBB_PWRDWN_REQ_CONTROL_0_REQ_WOFFSET                   0x0
#define PMC_IMPL_PART_MGBEBB_PWRDWN_REQ_CONTROL_0_REQ_DEFAULT                   MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_MGBEBB_PWRDWN_REQ_CONTROL_0_REQ_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_MGBEBB_PWRDWN_REQ_CONTROL_0_REQ_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_MGBEBB_PWRDWN_REQ_CONTROL_0_REQ_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_MGBEBB_PWRDWN_REQ_CONTROL_0_REQ_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_MGBEBB_PWRDWN_REQ_CONTROL_0_REQ_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_MGBEBB_PWRDWN_REQ_CONTROL_0_REQ_INIT_ENUM                 PWRDWN
#define PMC_IMPL_PART_MGBEBB_PWRDWN_REQ_CONTROL_0_REQ_PWRDWN                    MK_ENUM_CONST(1)
#define PMC_IMPL_PART_MGBEBB_PWRDWN_REQ_CONTROL_0_REQ_PWRUP                     MK_ENUM_CONST(0)


// Register PMC_IMPL_PART_MGBEBB_PWRDWN_ACK_STATUS_0
#define PMC_IMPL_PART_MGBEBB_PWRDWN_ACK_STATUS_0                        MK_ADDR_CONST(0x6b0)
#define PMC_IMPL_PART_MGBEBB_PWRDWN_ACK_STATUS_0_SECURE                         0x0
#define PMC_IMPL_PART_MGBEBB_PWRDWN_ACK_STATUS_0_DUAL                   0x0
#define PMC_IMPL_PART_MGBEBB_PWRDWN_ACK_STATUS_0_SCR                    PG_MGBEBB_SCR_0
#define PMC_IMPL_PART_MGBEBB_PWRDWN_ACK_STATUS_0_SCRREG                         PMC_IMPL_SCR_PG_MGBEBB_SCR_0
#define PMC_IMPL_PART_MGBEBB_PWRDWN_ACK_STATUS_0_WORD_COUNT                     0x1
#define PMC_IMPL_PART_MGBEBB_PWRDWN_ACK_STATUS_0_RESET_VAL                      MK_MASK_CONST(0x7)
#define PMC_IMPL_PART_MGBEBB_PWRDWN_ACK_STATUS_0_RESET_MASK                     MK_MASK_CONST(0x7)
#define PMC_IMPL_PART_MGBEBB_PWRDWN_ACK_STATUS_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_MGBEBB_PWRDWN_ACK_STATUS_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_MGBEBB_PWRDWN_ACK_STATUS_0_READ_MASK                      MK_MASK_CONST(0x7)
#define PMC_IMPL_PART_MGBEBB_PWRDWN_ACK_STATUS_0_WRITE_MASK                     MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_MGBEBB_PWRDWN_ACK_STATUS_0_CBB_ACK_SHIFT                  MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_MGBEBB_PWRDWN_ACK_STATUS_0_CBB_ACK_FIELD                  MK_FIELD_CONST(0x1, PMC_IMPL_PART_MGBEBB_PWRDWN_ACK_STATUS_0_CBB_ACK_SHIFT)
#define PMC_IMPL_PART_MGBEBB_PWRDWN_ACK_STATUS_0_CBB_ACK_RANGE                  0:0
#define PMC_IMPL_PART_MGBEBB_PWRDWN_ACK_STATUS_0_CBB_ACK_MSB                    MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_MGBEBB_PWRDWN_ACK_STATUS_0_CBB_ACK_LSB                    MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_MGBEBB_PWRDWN_ACK_STATUS_0_CBB_ACK_WOFFSET                        0x0
#define PMC_IMPL_PART_MGBEBB_PWRDWN_ACK_STATUS_0_CBB_ACK_DEFAULT                        MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_MGBEBB_PWRDWN_ACK_STATUS_0_CBB_ACK_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_MGBEBB_PWRDWN_ACK_STATUS_0_CBB_ACK_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_MGBEBB_PWRDWN_ACK_STATUS_0_CBB_ACK_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_MGBEBB_PWRDWN_ACK_STATUS_0_CBB_ACK_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_MGBEBB_PWRDWN_ACK_STATUS_0_CBB_ACK_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_MGBEBB_PWRDWN_ACK_STATUS_0_CBB_ACK_INIT_ENUM                      PWRDWN
#define PMC_IMPL_PART_MGBEBB_PWRDWN_ACK_STATUS_0_CBB_ACK_PWRDWN                 MK_ENUM_CONST(1)
#define PMC_IMPL_PART_MGBEBB_PWRDWN_ACK_STATUS_0_CBB_ACK_PWRUP                  MK_ENUM_CONST(0)

#define PMC_IMPL_PART_MGBEBB_PWRDWN_ACK_STATUS_0_DBB_ACK_SHIFT                  MK_SHIFT_CONST(1)
#define PMC_IMPL_PART_MGBEBB_PWRDWN_ACK_STATUS_0_DBB_ACK_FIELD                  MK_FIELD_CONST(0x1, PMC_IMPL_PART_MGBEBB_PWRDWN_ACK_STATUS_0_DBB_ACK_SHIFT)
#define PMC_IMPL_PART_MGBEBB_PWRDWN_ACK_STATUS_0_DBB_ACK_RANGE                  1:1
#define PMC_IMPL_PART_MGBEBB_PWRDWN_ACK_STATUS_0_DBB_ACK_MSB                    MK_SHIFT_CONST(1)
#define PMC_IMPL_PART_MGBEBB_PWRDWN_ACK_STATUS_0_DBB_ACK_LSB                    MK_SHIFT_CONST(1)
#define PMC_IMPL_PART_MGBEBB_PWRDWN_ACK_STATUS_0_DBB_ACK_WOFFSET                        0x0
#define PMC_IMPL_PART_MGBEBB_PWRDWN_ACK_STATUS_0_DBB_ACK_DEFAULT                        MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_MGBEBB_PWRDWN_ACK_STATUS_0_DBB_ACK_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_MGBEBB_PWRDWN_ACK_STATUS_0_DBB_ACK_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_MGBEBB_PWRDWN_ACK_STATUS_0_DBB_ACK_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_MGBEBB_PWRDWN_ACK_STATUS_0_DBB_ACK_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_MGBEBB_PWRDWN_ACK_STATUS_0_DBB_ACK_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_MGBEBB_PWRDWN_ACK_STATUS_0_DBB_ACK_INIT_ENUM                      PWRDWN
#define PMC_IMPL_PART_MGBEBB_PWRDWN_ACK_STATUS_0_DBB_ACK_PWRDWN                 MK_ENUM_CONST(1)
#define PMC_IMPL_PART_MGBEBB_PWRDWN_ACK_STATUS_0_DBB_ACK_PWRUP                  MK_ENUM_CONST(0)

#define PMC_IMPL_PART_MGBEBB_PWRDWN_ACK_STATUS_0_H1X_ACK_SHIFT                  MK_SHIFT_CONST(2)
#define PMC_IMPL_PART_MGBEBB_PWRDWN_ACK_STATUS_0_H1X_ACK_FIELD                  MK_FIELD_CONST(0x1, PMC_IMPL_PART_MGBEBB_PWRDWN_ACK_STATUS_0_H1X_ACK_SHIFT)
#define PMC_IMPL_PART_MGBEBB_PWRDWN_ACK_STATUS_0_H1X_ACK_RANGE                  2:2
#define PMC_IMPL_PART_MGBEBB_PWRDWN_ACK_STATUS_0_H1X_ACK_MSB                    MK_SHIFT_CONST(2)
#define PMC_IMPL_PART_MGBEBB_PWRDWN_ACK_STATUS_0_H1X_ACK_LSB                    MK_SHIFT_CONST(2)
#define PMC_IMPL_PART_MGBEBB_PWRDWN_ACK_STATUS_0_H1X_ACK_WOFFSET                        0x0
#define PMC_IMPL_PART_MGBEBB_PWRDWN_ACK_STATUS_0_H1X_ACK_DEFAULT                        MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_MGBEBB_PWRDWN_ACK_STATUS_0_H1X_ACK_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_MGBEBB_PWRDWN_ACK_STATUS_0_H1X_ACK_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_MGBEBB_PWRDWN_ACK_STATUS_0_H1X_ACK_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_MGBEBB_PWRDWN_ACK_STATUS_0_H1X_ACK_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_MGBEBB_PWRDWN_ACK_STATUS_0_H1X_ACK_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_MGBEBB_PWRDWN_ACK_STATUS_0_H1X_ACK_INIT_ENUM                      PWRDWN
#define PMC_IMPL_PART_MGBEBB_PWRDWN_ACK_STATUS_0_H1X_ACK_PWRDWN                 MK_ENUM_CONST(1)
#define PMC_IMPL_PART_MGBEBB_PWRDWN_ACK_STATUS_0_H1X_ACK_PWRUP                  MK_ENUM_CONST(0)


// Register PMC_IMPL_PART_MGBEBC_PWRDWN_REQ_CONTROL_0
#define PMC_IMPL_PART_MGBEBC_PWRDWN_REQ_CONTROL_0                       MK_ADDR_CONST(0x6b4)
#define PMC_IMPL_PART_MGBEBC_PWRDWN_REQ_CONTROL_0_SECURE                        0x0
#define PMC_IMPL_PART_MGBEBC_PWRDWN_REQ_CONTROL_0_DUAL                  0x0
#define PMC_IMPL_PART_MGBEBC_PWRDWN_REQ_CONTROL_0_SCR                   PG_MGBEBC_SCR_0
#define PMC_IMPL_PART_MGBEBC_PWRDWN_REQ_CONTROL_0_SCRREG                        PMC_IMPL_SCR_PG_MGBEBC_SCR_0
#define PMC_IMPL_PART_MGBEBC_PWRDWN_REQ_CONTROL_0_WORD_COUNT                    0x1
#define PMC_IMPL_PART_MGBEBC_PWRDWN_REQ_CONTROL_0_RESET_VAL                     MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_MGBEBC_PWRDWN_REQ_CONTROL_0_RESET_MASK                    MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_MGBEBC_PWRDWN_REQ_CONTROL_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_MGBEBC_PWRDWN_REQ_CONTROL_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_MGBEBC_PWRDWN_REQ_CONTROL_0_READ_MASK                     MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_MGBEBC_PWRDWN_REQ_CONTROL_0_WRITE_MASK                    MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_MGBEBC_PWRDWN_REQ_CONTROL_0_REQ_SHIFT                     MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_MGBEBC_PWRDWN_REQ_CONTROL_0_REQ_FIELD                     MK_FIELD_CONST(0x1, PMC_IMPL_PART_MGBEBC_PWRDWN_REQ_CONTROL_0_REQ_SHIFT)
#define PMC_IMPL_PART_MGBEBC_PWRDWN_REQ_CONTROL_0_REQ_RANGE                     0:0
#define PMC_IMPL_PART_MGBEBC_PWRDWN_REQ_CONTROL_0_REQ_MSB                       MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_MGBEBC_PWRDWN_REQ_CONTROL_0_REQ_LSB                       MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_MGBEBC_PWRDWN_REQ_CONTROL_0_REQ_WOFFSET                   0x0
#define PMC_IMPL_PART_MGBEBC_PWRDWN_REQ_CONTROL_0_REQ_DEFAULT                   MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_MGBEBC_PWRDWN_REQ_CONTROL_0_REQ_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_MGBEBC_PWRDWN_REQ_CONTROL_0_REQ_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_MGBEBC_PWRDWN_REQ_CONTROL_0_REQ_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_MGBEBC_PWRDWN_REQ_CONTROL_0_REQ_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_MGBEBC_PWRDWN_REQ_CONTROL_0_REQ_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_MGBEBC_PWRDWN_REQ_CONTROL_0_REQ_INIT_ENUM                 PWRDWN
#define PMC_IMPL_PART_MGBEBC_PWRDWN_REQ_CONTROL_0_REQ_PWRDWN                    MK_ENUM_CONST(1)
#define PMC_IMPL_PART_MGBEBC_PWRDWN_REQ_CONTROL_0_REQ_PWRUP                     MK_ENUM_CONST(0)


// Register PMC_IMPL_PART_MGBEBC_PWRDWN_ACK_STATUS_0
#define PMC_IMPL_PART_MGBEBC_PWRDWN_ACK_STATUS_0                        MK_ADDR_CONST(0x6b8)
#define PMC_IMPL_PART_MGBEBC_PWRDWN_ACK_STATUS_0_SECURE                         0x0
#define PMC_IMPL_PART_MGBEBC_PWRDWN_ACK_STATUS_0_DUAL                   0x0
#define PMC_IMPL_PART_MGBEBC_PWRDWN_ACK_STATUS_0_SCR                    PG_MGBEBC_SCR_0
#define PMC_IMPL_PART_MGBEBC_PWRDWN_ACK_STATUS_0_SCRREG                         PMC_IMPL_SCR_PG_MGBEBC_SCR_0
#define PMC_IMPL_PART_MGBEBC_PWRDWN_ACK_STATUS_0_WORD_COUNT                     0x1
#define PMC_IMPL_PART_MGBEBC_PWRDWN_ACK_STATUS_0_RESET_VAL                      MK_MASK_CONST(0x7)
#define PMC_IMPL_PART_MGBEBC_PWRDWN_ACK_STATUS_0_RESET_MASK                     MK_MASK_CONST(0x7)
#define PMC_IMPL_PART_MGBEBC_PWRDWN_ACK_STATUS_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_MGBEBC_PWRDWN_ACK_STATUS_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_MGBEBC_PWRDWN_ACK_STATUS_0_READ_MASK                      MK_MASK_CONST(0x7)
#define PMC_IMPL_PART_MGBEBC_PWRDWN_ACK_STATUS_0_WRITE_MASK                     MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_MGBEBC_PWRDWN_ACK_STATUS_0_CBB_ACK_SHIFT                  MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_MGBEBC_PWRDWN_ACK_STATUS_0_CBB_ACK_FIELD                  MK_FIELD_CONST(0x1, PMC_IMPL_PART_MGBEBC_PWRDWN_ACK_STATUS_0_CBB_ACK_SHIFT)
#define PMC_IMPL_PART_MGBEBC_PWRDWN_ACK_STATUS_0_CBB_ACK_RANGE                  0:0
#define PMC_IMPL_PART_MGBEBC_PWRDWN_ACK_STATUS_0_CBB_ACK_MSB                    MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_MGBEBC_PWRDWN_ACK_STATUS_0_CBB_ACK_LSB                    MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_MGBEBC_PWRDWN_ACK_STATUS_0_CBB_ACK_WOFFSET                        0x0
#define PMC_IMPL_PART_MGBEBC_PWRDWN_ACK_STATUS_0_CBB_ACK_DEFAULT                        MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_MGBEBC_PWRDWN_ACK_STATUS_0_CBB_ACK_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_MGBEBC_PWRDWN_ACK_STATUS_0_CBB_ACK_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_MGBEBC_PWRDWN_ACK_STATUS_0_CBB_ACK_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_MGBEBC_PWRDWN_ACK_STATUS_0_CBB_ACK_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_MGBEBC_PWRDWN_ACK_STATUS_0_CBB_ACK_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_MGBEBC_PWRDWN_ACK_STATUS_0_CBB_ACK_INIT_ENUM                      PWRDWN
#define PMC_IMPL_PART_MGBEBC_PWRDWN_ACK_STATUS_0_CBB_ACK_PWRDWN                 MK_ENUM_CONST(1)
#define PMC_IMPL_PART_MGBEBC_PWRDWN_ACK_STATUS_0_CBB_ACK_PWRUP                  MK_ENUM_CONST(0)

#define PMC_IMPL_PART_MGBEBC_PWRDWN_ACK_STATUS_0_DBB_ACK_SHIFT                  MK_SHIFT_CONST(1)
#define PMC_IMPL_PART_MGBEBC_PWRDWN_ACK_STATUS_0_DBB_ACK_FIELD                  MK_FIELD_CONST(0x1, PMC_IMPL_PART_MGBEBC_PWRDWN_ACK_STATUS_0_DBB_ACK_SHIFT)
#define PMC_IMPL_PART_MGBEBC_PWRDWN_ACK_STATUS_0_DBB_ACK_RANGE                  1:1
#define PMC_IMPL_PART_MGBEBC_PWRDWN_ACK_STATUS_0_DBB_ACK_MSB                    MK_SHIFT_CONST(1)
#define PMC_IMPL_PART_MGBEBC_PWRDWN_ACK_STATUS_0_DBB_ACK_LSB                    MK_SHIFT_CONST(1)
#define PMC_IMPL_PART_MGBEBC_PWRDWN_ACK_STATUS_0_DBB_ACK_WOFFSET                        0x0
#define PMC_IMPL_PART_MGBEBC_PWRDWN_ACK_STATUS_0_DBB_ACK_DEFAULT                        MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_MGBEBC_PWRDWN_ACK_STATUS_0_DBB_ACK_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_MGBEBC_PWRDWN_ACK_STATUS_0_DBB_ACK_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_MGBEBC_PWRDWN_ACK_STATUS_0_DBB_ACK_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_MGBEBC_PWRDWN_ACK_STATUS_0_DBB_ACK_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_MGBEBC_PWRDWN_ACK_STATUS_0_DBB_ACK_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_MGBEBC_PWRDWN_ACK_STATUS_0_DBB_ACK_INIT_ENUM                      PWRDWN
#define PMC_IMPL_PART_MGBEBC_PWRDWN_ACK_STATUS_0_DBB_ACK_PWRDWN                 MK_ENUM_CONST(1)
#define PMC_IMPL_PART_MGBEBC_PWRDWN_ACK_STATUS_0_DBB_ACK_PWRUP                  MK_ENUM_CONST(0)

#define PMC_IMPL_PART_MGBEBC_PWRDWN_ACK_STATUS_0_H1X_ACK_SHIFT                  MK_SHIFT_CONST(2)
#define PMC_IMPL_PART_MGBEBC_PWRDWN_ACK_STATUS_0_H1X_ACK_FIELD                  MK_FIELD_CONST(0x1, PMC_IMPL_PART_MGBEBC_PWRDWN_ACK_STATUS_0_H1X_ACK_SHIFT)
#define PMC_IMPL_PART_MGBEBC_PWRDWN_ACK_STATUS_0_H1X_ACK_RANGE                  2:2
#define PMC_IMPL_PART_MGBEBC_PWRDWN_ACK_STATUS_0_H1X_ACK_MSB                    MK_SHIFT_CONST(2)
#define PMC_IMPL_PART_MGBEBC_PWRDWN_ACK_STATUS_0_H1X_ACK_LSB                    MK_SHIFT_CONST(2)
#define PMC_IMPL_PART_MGBEBC_PWRDWN_ACK_STATUS_0_H1X_ACK_WOFFSET                        0x0
#define PMC_IMPL_PART_MGBEBC_PWRDWN_ACK_STATUS_0_H1X_ACK_DEFAULT                        MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_MGBEBC_PWRDWN_ACK_STATUS_0_H1X_ACK_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_MGBEBC_PWRDWN_ACK_STATUS_0_H1X_ACK_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_MGBEBC_PWRDWN_ACK_STATUS_0_H1X_ACK_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_MGBEBC_PWRDWN_ACK_STATUS_0_H1X_ACK_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_MGBEBC_PWRDWN_ACK_STATUS_0_H1X_ACK_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_MGBEBC_PWRDWN_ACK_STATUS_0_H1X_ACK_INIT_ENUM                      PWRDWN
#define PMC_IMPL_PART_MGBEBC_PWRDWN_ACK_STATUS_0_H1X_ACK_PWRDWN                 MK_ENUM_CONST(1)
#define PMC_IMPL_PART_MGBEBC_PWRDWN_ACK_STATUS_0_H1X_ACK_PWRUP                  MK_ENUM_CONST(0)


// Register PMC_IMPL_PART_EMCAA_PWRDWN_REQ_CONTROL_0
#define PMC_IMPL_PART_EMCAA_PWRDWN_REQ_CONTROL_0                        MK_ADDR_CONST(0x6bc)
#define PMC_IMPL_PART_EMCAA_PWRDWN_REQ_CONTROL_0_SECURE                         0x0
#define PMC_IMPL_PART_EMCAA_PWRDWN_REQ_CONTROL_0_DUAL                   0x0
#define PMC_IMPL_PART_EMCAA_PWRDWN_REQ_CONTROL_0_SCR                    PG_EMCAA_SCR_0
#define PMC_IMPL_PART_EMCAA_PWRDWN_REQ_CONTROL_0_SCRREG                         PMC_IMPL_SCR_PG_EMCAA_SCR_0
#define PMC_IMPL_PART_EMCAA_PWRDWN_REQ_CONTROL_0_WORD_COUNT                     0x1
#define PMC_IMPL_PART_EMCAA_PWRDWN_REQ_CONTROL_0_RESET_VAL                      MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_EMCAA_PWRDWN_REQ_CONTROL_0_RESET_MASK                     MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_EMCAA_PWRDWN_REQ_CONTROL_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_EMCAA_PWRDWN_REQ_CONTROL_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_EMCAA_PWRDWN_REQ_CONTROL_0_READ_MASK                      MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_EMCAA_PWRDWN_REQ_CONTROL_0_WRITE_MASK                     MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_EMCAA_PWRDWN_REQ_CONTROL_0_REQ_SHIFT                      MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_EMCAA_PWRDWN_REQ_CONTROL_0_REQ_FIELD                      MK_FIELD_CONST(0x1, PMC_IMPL_PART_EMCAA_PWRDWN_REQ_CONTROL_0_REQ_SHIFT)
#define PMC_IMPL_PART_EMCAA_PWRDWN_REQ_CONTROL_0_REQ_RANGE                      0:0
#define PMC_IMPL_PART_EMCAA_PWRDWN_REQ_CONTROL_0_REQ_MSB                        MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_EMCAA_PWRDWN_REQ_CONTROL_0_REQ_LSB                        MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_EMCAA_PWRDWN_REQ_CONTROL_0_REQ_WOFFSET                    0x0
#define PMC_IMPL_PART_EMCAA_PWRDWN_REQ_CONTROL_0_REQ_DEFAULT                    MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_EMCAA_PWRDWN_REQ_CONTROL_0_REQ_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_EMCAA_PWRDWN_REQ_CONTROL_0_REQ_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_EMCAA_PWRDWN_REQ_CONTROL_0_REQ_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_EMCAA_PWRDWN_REQ_CONTROL_0_REQ_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_EMCAA_PWRDWN_REQ_CONTROL_0_REQ_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_EMCAA_PWRDWN_REQ_CONTROL_0_REQ_INIT_ENUM                  PWRDWN
#define PMC_IMPL_PART_EMCAA_PWRDWN_REQ_CONTROL_0_REQ_PWRDWN                     MK_ENUM_CONST(1)
#define PMC_IMPL_PART_EMCAA_PWRDWN_REQ_CONTROL_0_REQ_PWRUP                      MK_ENUM_CONST(0)


// Register PMC_IMPL_PART_EMCAA_PWRDWN_ACK_STATUS_0
#define PMC_IMPL_PART_EMCAA_PWRDWN_ACK_STATUS_0                 MK_ADDR_CONST(0x6c0)
#define PMC_IMPL_PART_EMCAA_PWRDWN_ACK_STATUS_0_SECURE                  0x0
#define PMC_IMPL_PART_EMCAA_PWRDWN_ACK_STATUS_0_DUAL                    0x0
#define PMC_IMPL_PART_EMCAA_PWRDWN_ACK_STATUS_0_SCR                     PG_EMCAA_SCR_0
#define PMC_IMPL_PART_EMCAA_PWRDWN_ACK_STATUS_0_SCRREG                  PMC_IMPL_SCR_PG_EMCAA_SCR_0
#define PMC_IMPL_PART_EMCAA_PWRDWN_ACK_STATUS_0_WORD_COUNT                      0x1
#define PMC_IMPL_PART_EMCAA_PWRDWN_ACK_STATUS_0_RESET_VAL                       MK_MASK_CONST(0x7)
#define PMC_IMPL_PART_EMCAA_PWRDWN_ACK_STATUS_0_RESET_MASK                      MK_MASK_CONST(0x7)
#define PMC_IMPL_PART_EMCAA_PWRDWN_ACK_STATUS_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_EMCAA_PWRDWN_ACK_STATUS_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_EMCAA_PWRDWN_ACK_STATUS_0_READ_MASK                       MK_MASK_CONST(0x7)
#define PMC_IMPL_PART_EMCAA_PWRDWN_ACK_STATUS_0_WRITE_MASK                      MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_EMCAA_PWRDWN_ACK_STATUS_0_CBB_ACK_SHIFT                   MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_EMCAA_PWRDWN_ACK_STATUS_0_CBB_ACK_FIELD                   MK_FIELD_CONST(0x1, PMC_IMPL_PART_EMCAA_PWRDWN_ACK_STATUS_0_CBB_ACK_SHIFT)
#define PMC_IMPL_PART_EMCAA_PWRDWN_ACK_STATUS_0_CBB_ACK_RANGE                   0:0
#define PMC_IMPL_PART_EMCAA_PWRDWN_ACK_STATUS_0_CBB_ACK_MSB                     MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_EMCAA_PWRDWN_ACK_STATUS_0_CBB_ACK_LSB                     MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_EMCAA_PWRDWN_ACK_STATUS_0_CBB_ACK_WOFFSET                 0x0
#define PMC_IMPL_PART_EMCAA_PWRDWN_ACK_STATUS_0_CBB_ACK_DEFAULT                 MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_EMCAA_PWRDWN_ACK_STATUS_0_CBB_ACK_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_EMCAA_PWRDWN_ACK_STATUS_0_CBB_ACK_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_EMCAA_PWRDWN_ACK_STATUS_0_CBB_ACK_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_EMCAA_PWRDWN_ACK_STATUS_0_CBB_ACK_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_EMCAA_PWRDWN_ACK_STATUS_0_CBB_ACK_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_EMCAA_PWRDWN_ACK_STATUS_0_CBB_ACK_INIT_ENUM                       PWRDWN
#define PMC_IMPL_PART_EMCAA_PWRDWN_ACK_STATUS_0_CBB_ACK_PWRDWN                  MK_ENUM_CONST(1)
#define PMC_IMPL_PART_EMCAA_PWRDWN_ACK_STATUS_0_CBB_ACK_PWRUP                   MK_ENUM_CONST(0)

#define PMC_IMPL_PART_EMCAA_PWRDWN_ACK_STATUS_0_DBB_ACK_SHIFT                   MK_SHIFT_CONST(1)
#define PMC_IMPL_PART_EMCAA_PWRDWN_ACK_STATUS_0_DBB_ACK_FIELD                   MK_FIELD_CONST(0x1, PMC_IMPL_PART_EMCAA_PWRDWN_ACK_STATUS_0_DBB_ACK_SHIFT)
#define PMC_IMPL_PART_EMCAA_PWRDWN_ACK_STATUS_0_DBB_ACK_RANGE                   1:1
#define PMC_IMPL_PART_EMCAA_PWRDWN_ACK_STATUS_0_DBB_ACK_MSB                     MK_SHIFT_CONST(1)
#define PMC_IMPL_PART_EMCAA_PWRDWN_ACK_STATUS_0_DBB_ACK_LSB                     MK_SHIFT_CONST(1)
#define PMC_IMPL_PART_EMCAA_PWRDWN_ACK_STATUS_0_DBB_ACK_WOFFSET                 0x0
#define PMC_IMPL_PART_EMCAA_PWRDWN_ACK_STATUS_0_DBB_ACK_DEFAULT                 MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_EMCAA_PWRDWN_ACK_STATUS_0_DBB_ACK_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_EMCAA_PWRDWN_ACK_STATUS_0_DBB_ACK_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_EMCAA_PWRDWN_ACK_STATUS_0_DBB_ACK_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_EMCAA_PWRDWN_ACK_STATUS_0_DBB_ACK_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_EMCAA_PWRDWN_ACK_STATUS_0_DBB_ACK_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_EMCAA_PWRDWN_ACK_STATUS_0_DBB_ACK_INIT_ENUM                       PWRDWN
#define PMC_IMPL_PART_EMCAA_PWRDWN_ACK_STATUS_0_DBB_ACK_PWRDWN                  MK_ENUM_CONST(1)
#define PMC_IMPL_PART_EMCAA_PWRDWN_ACK_STATUS_0_DBB_ACK_PWRUP                   MK_ENUM_CONST(0)

#define PMC_IMPL_PART_EMCAA_PWRDWN_ACK_STATUS_0_H1X_ACK_SHIFT                   MK_SHIFT_CONST(2)
#define PMC_IMPL_PART_EMCAA_PWRDWN_ACK_STATUS_0_H1X_ACK_FIELD                   MK_FIELD_CONST(0x1, PMC_IMPL_PART_EMCAA_PWRDWN_ACK_STATUS_0_H1X_ACK_SHIFT)
#define PMC_IMPL_PART_EMCAA_PWRDWN_ACK_STATUS_0_H1X_ACK_RANGE                   2:2
#define PMC_IMPL_PART_EMCAA_PWRDWN_ACK_STATUS_0_H1X_ACK_MSB                     MK_SHIFT_CONST(2)
#define PMC_IMPL_PART_EMCAA_PWRDWN_ACK_STATUS_0_H1X_ACK_LSB                     MK_SHIFT_CONST(2)
#define PMC_IMPL_PART_EMCAA_PWRDWN_ACK_STATUS_0_H1X_ACK_WOFFSET                 0x0
#define PMC_IMPL_PART_EMCAA_PWRDWN_ACK_STATUS_0_H1X_ACK_DEFAULT                 MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_EMCAA_PWRDWN_ACK_STATUS_0_H1X_ACK_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_EMCAA_PWRDWN_ACK_STATUS_0_H1X_ACK_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_EMCAA_PWRDWN_ACK_STATUS_0_H1X_ACK_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_EMCAA_PWRDWN_ACK_STATUS_0_H1X_ACK_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_EMCAA_PWRDWN_ACK_STATUS_0_H1X_ACK_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_EMCAA_PWRDWN_ACK_STATUS_0_H1X_ACK_INIT_ENUM                       PWRDWN
#define PMC_IMPL_PART_EMCAA_PWRDWN_ACK_STATUS_0_H1X_ACK_PWRDWN                  MK_ENUM_CONST(1)
#define PMC_IMPL_PART_EMCAA_PWRDWN_ACK_STATUS_0_H1X_ACK_PWRUP                   MK_ENUM_CONST(0)


// Reserved address 0x6c4

// Reserved address 0x6c8

// Reserved address 0x6cc

// Reserved address 0x6d0

// Reserved address 0x6d4

// Reserved address 0x6d8
// The status in POWER_GATE_STATUS does not reflect the overriden values
//Reset level:l2warmrst_pmc_pclk_srstn

// Register PMC_IMPL_SW_OVERRIDE_CTRL_1_0
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0                   MK_ADDR_CONST(0x6dc)
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_SECURE                    0x0
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_DUAL                      0x0
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_SCR                       PG_OVERRIDE_SCR_0
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_SCRREG                    PMC_IMPL_SCR_PG_OVERRIDE_SCR_0
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_WORD_COUNT                        0x1
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_RESET_MASK                        MK_MASK_CONST(0xffffffff)
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
// Override RET value for AOPG RAM control signal
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM0_RET_SHIFT                   MK_SHIFT_CONST(0)
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM0_RET_FIELD                   MK_FIELD_CONST(0x1, PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM0_RET_SHIFT)
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM0_RET_RANGE                   0:0
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM0_RET_MSB                     MK_SHIFT_CONST(0)
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM0_RET_LSB                     MK_SHIFT_CONST(0)
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM0_RET_WOFFSET                 0x0
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM0_RET_DEFAULT                 MK_MASK_CONST(0x0)
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM0_RET_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM0_RET_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM0_RET_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM0_RET_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM0_RET_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM0_RET_INIT_ENUM                       DISABLE
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM0_RET_ENABLE                  MK_ENUM_CONST(1)
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM0_RET_DISABLE                 MK_ENUM_CONST(0)

// Override SLEEP value for AOPG RAM control signal
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM0_SLEEP_SHIFT                 MK_SHIFT_CONST(1)
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM0_SLEEP_FIELD                 MK_FIELD_CONST(0x3, PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM0_SLEEP_SHIFT)
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM0_SLEEP_RANGE                 2:1
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM0_SLEEP_MSB                   MK_SHIFT_CONST(2)
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM0_SLEEP_LSB                   MK_SHIFT_CONST(1)
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM0_SLEEP_WOFFSET                       0x0
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM0_SLEEP_DEFAULT                       MK_MASK_CONST(0x0)
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM0_SLEEP_DEFAULT_MASK                  MK_MASK_CONST(0x3)
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM0_SLEEP_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM0_SLEEP_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM0_SLEEP_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM0_SLEEP_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

// Override enable for AOPG RAM control signal
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_EN_AOPG_TCM0_SHIFT                        MK_SHIFT_CONST(3)
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_EN_AOPG_TCM0_FIELD                        MK_FIELD_CONST(0x1, PMC_IMPL_SW_OVERRIDE_CTRL_1_0_EN_AOPG_TCM0_SHIFT)
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_EN_AOPG_TCM0_RANGE                        3:3
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_EN_AOPG_TCM0_MSB                  MK_SHIFT_CONST(3)
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_EN_AOPG_TCM0_LSB                  MK_SHIFT_CONST(3)
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_EN_AOPG_TCM0_WOFFSET                      0x0
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_EN_AOPG_TCM0_DEFAULT                      MK_MASK_CONST(0x0)
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_EN_AOPG_TCM0_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_EN_AOPG_TCM0_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_EN_AOPG_TCM0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_EN_AOPG_TCM0_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_EN_AOPG_TCM0_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_EN_AOPG_TCM0_INIT_ENUM                    DISABLE
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_EN_AOPG_TCM0_ENABLE                       MK_ENUM_CONST(1)
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_EN_AOPG_TCM0_DISABLE                      MK_ENUM_CONST(0)

// Override RET value for AOPG RAM control signal
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM1_RET_SHIFT                   MK_SHIFT_CONST(4)
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM1_RET_FIELD                   MK_FIELD_CONST(0x1, PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM1_RET_SHIFT)
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM1_RET_RANGE                   4:4
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM1_RET_MSB                     MK_SHIFT_CONST(4)
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM1_RET_LSB                     MK_SHIFT_CONST(4)
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM1_RET_WOFFSET                 0x0
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM1_RET_DEFAULT                 MK_MASK_CONST(0x0)
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM1_RET_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM1_RET_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM1_RET_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM1_RET_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM1_RET_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM1_RET_INIT_ENUM                       DISABLE
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM1_RET_ENABLE                  MK_ENUM_CONST(1)
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM1_RET_DISABLE                 MK_ENUM_CONST(0)

// Override SLEEP value for AOPG RAM control signal
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM1_SLEEP_SHIFT                 MK_SHIFT_CONST(5)
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM1_SLEEP_FIELD                 MK_FIELD_CONST(0x3, PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM1_SLEEP_SHIFT)
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM1_SLEEP_RANGE                 6:5
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM1_SLEEP_MSB                   MK_SHIFT_CONST(6)
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM1_SLEEP_LSB                   MK_SHIFT_CONST(5)
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM1_SLEEP_WOFFSET                       0x0
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM1_SLEEP_DEFAULT                       MK_MASK_CONST(0x0)
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM1_SLEEP_DEFAULT_MASK                  MK_MASK_CONST(0x3)
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM1_SLEEP_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM1_SLEEP_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM1_SLEEP_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM1_SLEEP_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

// Override enable for AOPG RAM control signal
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_EN_AOPG_TCM1_SHIFT                        MK_SHIFT_CONST(7)
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_EN_AOPG_TCM1_FIELD                        MK_FIELD_CONST(0x1, PMC_IMPL_SW_OVERRIDE_CTRL_1_0_EN_AOPG_TCM1_SHIFT)
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_EN_AOPG_TCM1_RANGE                        7:7
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_EN_AOPG_TCM1_MSB                  MK_SHIFT_CONST(7)
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_EN_AOPG_TCM1_LSB                  MK_SHIFT_CONST(7)
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_EN_AOPG_TCM1_WOFFSET                      0x0
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_EN_AOPG_TCM1_DEFAULT                      MK_MASK_CONST(0x0)
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_EN_AOPG_TCM1_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_EN_AOPG_TCM1_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_EN_AOPG_TCM1_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_EN_AOPG_TCM1_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_EN_AOPG_TCM1_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_EN_AOPG_TCM1_INIT_ENUM                    DISABLE
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_EN_AOPG_TCM1_ENABLE                       MK_ENUM_CONST(1)
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_EN_AOPG_TCM1_DISABLE                      MK_ENUM_CONST(0)

// Override RET value for AOPG RAM control signal
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM2_RET_SHIFT                   MK_SHIFT_CONST(8)
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM2_RET_FIELD                   MK_FIELD_CONST(0x1, PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM2_RET_SHIFT)
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM2_RET_RANGE                   8:8
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM2_RET_MSB                     MK_SHIFT_CONST(8)
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM2_RET_LSB                     MK_SHIFT_CONST(8)
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM2_RET_WOFFSET                 0x0
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM2_RET_DEFAULT                 MK_MASK_CONST(0x0)
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM2_RET_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM2_RET_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM2_RET_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM2_RET_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM2_RET_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM2_RET_INIT_ENUM                       DISABLE
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM2_RET_ENABLE                  MK_ENUM_CONST(1)
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM2_RET_DISABLE                 MK_ENUM_CONST(0)

// Override SLEEP value for AOPG RAM control signal
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM2_SLEEP_SHIFT                 MK_SHIFT_CONST(9)
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM2_SLEEP_FIELD                 MK_FIELD_CONST(0x3, PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM2_SLEEP_SHIFT)
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM2_SLEEP_RANGE                 10:9
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM2_SLEEP_MSB                   MK_SHIFT_CONST(10)
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM2_SLEEP_LSB                   MK_SHIFT_CONST(9)
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM2_SLEEP_WOFFSET                       0x0
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM2_SLEEP_DEFAULT                       MK_MASK_CONST(0x0)
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM2_SLEEP_DEFAULT_MASK                  MK_MASK_CONST(0x3)
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM2_SLEEP_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM2_SLEEP_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM2_SLEEP_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM2_SLEEP_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

// Override enable for AOPG RAM control signal
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_EN_AOPG_TCM2_SHIFT                        MK_SHIFT_CONST(11)
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_EN_AOPG_TCM2_FIELD                        MK_FIELD_CONST(0x1, PMC_IMPL_SW_OVERRIDE_CTRL_1_0_EN_AOPG_TCM2_SHIFT)
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_EN_AOPG_TCM2_RANGE                        11:11
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_EN_AOPG_TCM2_MSB                  MK_SHIFT_CONST(11)
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_EN_AOPG_TCM2_LSB                  MK_SHIFT_CONST(11)
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_EN_AOPG_TCM2_WOFFSET                      0x0
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_EN_AOPG_TCM2_DEFAULT                      MK_MASK_CONST(0x0)
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_EN_AOPG_TCM2_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_EN_AOPG_TCM2_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_EN_AOPG_TCM2_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_EN_AOPG_TCM2_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_EN_AOPG_TCM2_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_EN_AOPG_TCM2_INIT_ENUM                    DISABLE
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_EN_AOPG_TCM2_ENABLE                       MK_ENUM_CONST(1)
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_EN_AOPG_TCM2_DISABLE                      MK_ENUM_CONST(0)

// Override RET value for AOPG RAM control signal
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM3_RET_SHIFT                   MK_SHIFT_CONST(12)
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM3_RET_FIELD                   MK_FIELD_CONST(0x1, PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM3_RET_SHIFT)
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM3_RET_RANGE                   12:12
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM3_RET_MSB                     MK_SHIFT_CONST(12)
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM3_RET_LSB                     MK_SHIFT_CONST(12)
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM3_RET_WOFFSET                 0x0
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM3_RET_DEFAULT                 MK_MASK_CONST(0x0)
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM3_RET_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM3_RET_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM3_RET_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM3_RET_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM3_RET_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM3_RET_INIT_ENUM                       DISABLE
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM3_RET_ENABLE                  MK_ENUM_CONST(1)
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM3_RET_DISABLE                 MK_ENUM_CONST(0)

// Override SLEEP value for AOPG RAM control signal
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM3_SLEEP_SHIFT                 MK_SHIFT_CONST(13)
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM3_SLEEP_FIELD                 MK_FIELD_CONST(0x3, PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM3_SLEEP_SHIFT)
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM3_SLEEP_RANGE                 14:13
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM3_SLEEP_MSB                   MK_SHIFT_CONST(14)
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM3_SLEEP_LSB                   MK_SHIFT_CONST(13)
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM3_SLEEP_WOFFSET                       0x0
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM3_SLEEP_DEFAULT                       MK_MASK_CONST(0x0)
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM3_SLEEP_DEFAULT_MASK                  MK_MASK_CONST(0x3)
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM3_SLEEP_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM3_SLEEP_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM3_SLEEP_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM3_SLEEP_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

// Override enable for AOPG RAM control signal
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_EN_AOPG_TCM3_SHIFT                        MK_SHIFT_CONST(15)
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_EN_AOPG_TCM3_FIELD                        MK_FIELD_CONST(0x1, PMC_IMPL_SW_OVERRIDE_CTRL_1_0_EN_AOPG_TCM3_SHIFT)
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_EN_AOPG_TCM3_RANGE                        15:15
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_EN_AOPG_TCM3_MSB                  MK_SHIFT_CONST(15)
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_EN_AOPG_TCM3_LSB                  MK_SHIFT_CONST(15)
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_EN_AOPG_TCM3_WOFFSET                      0x0
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_EN_AOPG_TCM3_DEFAULT                      MK_MASK_CONST(0x0)
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_EN_AOPG_TCM3_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_EN_AOPG_TCM3_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_EN_AOPG_TCM3_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_EN_AOPG_TCM3_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_EN_AOPG_TCM3_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_EN_AOPG_TCM3_INIT_ENUM                    DISABLE
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_EN_AOPG_TCM3_ENABLE                       MK_ENUM_CONST(1)
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_EN_AOPG_TCM3_DISABLE                      MK_ENUM_CONST(0)

// Override RET value for AOPG RAM control signal
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM4_RET_SHIFT                   MK_SHIFT_CONST(16)
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM4_RET_FIELD                   MK_FIELD_CONST(0x1, PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM4_RET_SHIFT)
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM4_RET_RANGE                   16:16
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM4_RET_MSB                     MK_SHIFT_CONST(16)
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM4_RET_LSB                     MK_SHIFT_CONST(16)
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM4_RET_WOFFSET                 0x0
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM4_RET_DEFAULT                 MK_MASK_CONST(0x0)
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM4_RET_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM4_RET_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM4_RET_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM4_RET_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM4_RET_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM4_RET_INIT_ENUM                       DISABLE
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM4_RET_ENABLE                  MK_ENUM_CONST(1)
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM4_RET_DISABLE                 MK_ENUM_CONST(0)

// Override SLEEP value for AOPG RAM control signal
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM4_SLEEP_SHIFT                 MK_SHIFT_CONST(17)
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM4_SLEEP_FIELD                 MK_FIELD_CONST(0x3, PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM4_SLEEP_SHIFT)
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM4_SLEEP_RANGE                 18:17
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM4_SLEEP_MSB                   MK_SHIFT_CONST(18)
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM4_SLEEP_LSB                   MK_SHIFT_CONST(17)
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM4_SLEEP_WOFFSET                       0x0
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM4_SLEEP_DEFAULT                       MK_MASK_CONST(0x0)
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM4_SLEEP_DEFAULT_MASK                  MK_MASK_CONST(0x3)
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM4_SLEEP_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM4_SLEEP_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM4_SLEEP_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM4_SLEEP_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

// Override enable for AOPG RAM control signal
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_EN_AOPG_TCM4_SHIFT                        MK_SHIFT_CONST(19)
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_EN_AOPG_TCM4_FIELD                        MK_FIELD_CONST(0x1, PMC_IMPL_SW_OVERRIDE_CTRL_1_0_EN_AOPG_TCM4_SHIFT)
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_EN_AOPG_TCM4_RANGE                        19:19
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_EN_AOPG_TCM4_MSB                  MK_SHIFT_CONST(19)
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_EN_AOPG_TCM4_LSB                  MK_SHIFT_CONST(19)
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_EN_AOPG_TCM4_WOFFSET                      0x0
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_EN_AOPG_TCM4_DEFAULT                      MK_MASK_CONST(0x0)
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_EN_AOPG_TCM4_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_EN_AOPG_TCM4_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_EN_AOPG_TCM4_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_EN_AOPG_TCM4_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_EN_AOPG_TCM4_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_EN_AOPG_TCM4_INIT_ENUM                    DISABLE
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_EN_AOPG_TCM4_ENABLE                       MK_ENUM_CONST(1)
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_EN_AOPG_TCM4_DISABLE                      MK_ENUM_CONST(0)

// Override RET value for AOPG RAM control signal
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM5_RET_SHIFT                   MK_SHIFT_CONST(20)
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM5_RET_FIELD                   MK_FIELD_CONST(0x1, PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM5_RET_SHIFT)
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM5_RET_RANGE                   20:20
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM5_RET_MSB                     MK_SHIFT_CONST(20)
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM5_RET_LSB                     MK_SHIFT_CONST(20)
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM5_RET_WOFFSET                 0x0
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM5_RET_DEFAULT                 MK_MASK_CONST(0x0)
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM5_RET_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM5_RET_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM5_RET_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM5_RET_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM5_RET_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM5_RET_INIT_ENUM                       DISABLE
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM5_RET_ENABLE                  MK_ENUM_CONST(1)
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM5_RET_DISABLE                 MK_ENUM_CONST(0)

// Override SLEEP value for AOPG RAM control signal
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM5_SLEEP_SHIFT                 MK_SHIFT_CONST(21)
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM5_SLEEP_FIELD                 MK_FIELD_CONST(0x3, PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM5_SLEEP_SHIFT)
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM5_SLEEP_RANGE                 22:21
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM5_SLEEP_MSB                   MK_SHIFT_CONST(22)
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM5_SLEEP_LSB                   MK_SHIFT_CONST(21)
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM5_SLEEP_WOFFSET                       0x0
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM5_SLEEP_DEFAULT                       MK_MASK_CONST(0x0)
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM5_SLEEP_DEFAULT_MASK                  MK_MASK_CONST(0x3)
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM5_SLEEP_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM5_SLEEP_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM5_SLEEP_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM5_SLEEP_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

// Override enable for AOPG RAM control signal
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_EN_AOPG_TCM5_SHIFT                        MK_SHIFT_CONST(23)
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_EN_AOPG_TCM5_FIELD                        MK_FIELD_CONST(0x1, PMC_IMPL_SW_OVERRIDE_CTRL_1_0_EN_AOPG_TCM5_SHIFT)
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_EN_AOPG_TCM5_RANGE                        23:23
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_EN_AOPG_TCM5_MSB                  MK_SHIFT_CONST(23)
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_EN_AOPG_TCM5_LSB                  MK_SHIFT_CONST(23)
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_EN_AOPG_TCM5_WOFFSET                      0x0
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_EN_AOPG_TCM5_DEFAULT                      MK_MASK_CONST(0x0)
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_EN_AOPG_TCM5_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_EN_AOPG_TCM5_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_EN_AOPG_TCM5_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_EN_AOPG_TCM5_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_EN_AOPG_TCM5_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_EN_AOPG_TCM5_INIT_ENUM                    DISABLE
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_EN_AOPG_TCM5_ENABLE                       MK_ENUM_CONST(1)
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_EN_AOPG_TCM5_DISABLE                      MK_ENUM_CONST(0)

// Override RET value for AOPG RAM control signal
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM6_RET_SHIFT                   MK_SHIFT_CONST(24)
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM6_RET_FIELD                   MK_FIELD_CONST(0x1, PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM6_RET_SHIFT)
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM6_RET_RANGE                   24:24
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM6_RET_MSB                     MK_SHIFT_CONST(24)
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM6_RET_LSB                     MK_SHIFT_CONST(24)
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM6_RET_WOFFSET                 0x0
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM6_RET_DEFAULT                 MK_MASK_CONST(0x0)
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM6_RET_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM6_RET_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM6_RET_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM6_RET_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM6_RET_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM6_RET_INIT_ENUM                       DISABLE
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM6_RET_ENABLE                  MK_ENUM_CONST(1)
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM6_RET_DISABLE                 MK_ENUM_CONST(0)

// Override SLEEP value for AOPG RAM control signal
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM6_SLEEP_SHIFT                 MK_SHIFT_CONST(25)
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM6_SLEEP_FIELD                 MK_FIELD_CONST(0x3, PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM6_SLEEP_SHIFT)
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM6_SLEEP_RANGE                 26:25
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM6_SLEEP_MSB                   MK_SHIFT_CONST(26)
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM6_SLEEP_LSB                   MK_SHIFT_CONST(25)
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM6_SLEEP_WOFFSET                       0x0
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM6_SLEEP_DEFAULT                       MK_MASK_CONST(0x0)
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM6_SLEEP_DEFAULT_MASK                  MK_MASK_CONST(0x3)
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM6_SLEEP_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM6_SLEEP_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM6_SLEEP_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM6_SLEEP_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

// Override enable for AOPG RAM control signal
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_EN_AOPG_TCM6_SHIFT                        MK_SHIFT_CONST(27)
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_EN_AOPG_TCM6_FIELD                        MK_FIELD_CONST(0x1, PMC_IMPL_SW_OVERRIDE_CTRL_1_0_EN_AOPG_TCM6_SHIFT)
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_EN_AOPG_TCM6_RANGE                        27:27
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_EN_AOPG_TCM6_MSB                  MK_SHIFT_CONST(27)
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_EN_AOPG_TCM6_LSB                  MK_SHIFT_CONST(27)
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_EN_AOPG_TCM6_WOFFSET                      0x0
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_EN_AOPG_TCM6_DEFAULT                      MK_MASK_CONST(0x0)
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_EN_AOPG_TCM6_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_EN_AOPG_TCM6_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_EN_AOPG_TCM6_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_EN_AOPG_TCM6_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_EN_AOPG_TCM6_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_EN_AOPG_TCM6_INIT_ENUM                    DISABLE
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_EN_AOPG_TCM6_ENABLE                       MK_ENUM_CONST(1)
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_EN_AOPG_TCM6_DISABLE                      MK_ENUM_CONST(0)

// Override RET value for AOPG RAM control signal
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM7_RET_SHIFT                   MK_SHIFT_CONST(28)
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM7_RET_FIELD                   MK_FIELD_CONST(0x1, PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM7_RET_SHIFT)
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM7_RET_RANGE                   28:28
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM7_RET_MSB                     MK_SHIFT_CONST(28)
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM7_RET_LSB                     MK_SHIFT_CONST(28)
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM7_RET_WOFFSET                 0x0
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM7_RET_DEFAULT                 MK_MASK_CONST(0x0)
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM7_RET_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM7_RET_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM7_RET_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM7_RET_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM7_RET_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM7_RET_INIT_ENUM                       DISABLE
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM7_RET_ENABLE                  MK_ENUM_CONST(1)
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM7_RET_DISABLE                 MK_ENUM_CONST(0)

// Override SLEEP value for AOPG RAM control signal
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM7_SLEEP_SHIFT                 MK_SHIFT_CONST(29)
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM7_SLEEP_FIELD                 MK_FIELD_CONST(0x3, PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM7_SLEEP_SHIFT)
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM7_SLEEP_RANGE                 30:29
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM7_SLEEP_MSB                   MK_SHIFT_CONST(30)
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM7_SLEEP_LSB                   MK_SHIFT_CONST(29)
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM7_SLEEP_WOFFSET                       0x0
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM7_SLEEP_DEFAULT                       MK_MASK_CONST(0x0)
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM7_SLEEP_DEFAULT_MASK                  MK_MASK_CONST(0x3)
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM7_SLEEP_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM7_SLEEP_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM7_SLEEP_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM7_SLEEP_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

// Override enable for AOPG RAM control signal
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_EN_AOPG_TCM7_SHIFT                        MK_SHIFT_CONST(31)
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_EN_AOPG_TCM7_FIELD                        MK_FIELD_CONST(0x1, PMC_IMPL_SW_OVERRIDE_CTRL_1_0_EN_AOPG_TCM7_SHIFT)
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_EN_AOPG_TCM7_RANGE                        31:31
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_EN_AOPG_TCM7_MSB                  MK_SHIFT_CONST(31)
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_EN_AOPG_TCM7_LSB                  MK_SHIFT_CONST(31)
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_EN_AOPG_TCM7_WOFFSET                      0x0
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_EN_AOPG_TCM7_DEFAULT                      MK_MASK_CONST(0x0)
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_EN_AOPG_TCM7_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_EN_AOPG_TCM7_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_EN_AOPG_TCM7_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_EN_AOPG_TCM7_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_EN_AOPG_TCM7_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_EN_AOPG_TCM7_INIT_ENUM                    DISABLE
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_EN_AOPG_TCM7_ENABLE                       MK_ENUM_CONST(1)
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_EN_AOPG_TCM7_DISABLE                      MK_ENUM_CONST(0)

//Reset level:l2warmrst_pmc_pclk_srstn

// Register PMC_IMPL_SW_OVERRIDE_CTRL_2_0
#define PMC_IMPL_SW_OVERRIDE_CTRL_2_0                   MK_ADDR_CONST(0x6e0)
#define PMC_IMPL_SW_OVERRIDE_CTRL_2_0_SECURE                    0x0
#define PMC_IMPL_SW_OVERRIDE_CTRL_2_0_DUAL                      0x0
#define PMC_IMPL_SW_OVERRIDE_CTRL_2_0_SCR                       PG_OVERRIDE_SCR_0
#define PMC_IMPL_SW_OVERRIDE_CTRL_2_0_SCRREG                    PMC_IMPL_SCR_PG_OVERRIDE_SCR_0
#define PMC_IMPL_SW_OVERRIDE_CTRL_2_0_WORD_COUNT                        0x1
#define PMC_IMPL_SW_OVERRIDE_CTRL_2_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define PMC_IMPL_SW_OVERRIDE_CTRL_2_0_RESET_MASK                        MK_MASK_CONST(0x1fffff)
#define PMC_IMPL_SW_OVERRIDE_CTRL_2_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define PMC_IMPL_SW_OVERRIDE_CTRL_2_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define PMC_IMPL_SW_OVERRIDE_CTRL_2_0_READ_MASK                         MK_MASK_CONST(0x1fffff)
#define PMC_IMPL_SW_OVERRIDE_CTRL_2_0_WRITE_MASK                        MK_MASK_CONST(0x1fffff)
// Override RET value for AOPG RAM control signal
#define PMC_IMPL_SW_OVERRIDE_CTRL_2_0_VAL_AOPG_CACHE_RET_SHIFT                  MK_SHIFT_CONST(0)
#define PMC_IMPL_SW_OVERRIDE_CTRL_2_0_VAL_AOPG_CACHE_RET_FIELD                  MK_FIELD_CONST(0x1, PMC_IMPL_SW_OVERRIDE_CTRL_2_0_VAL_AOPG_CACHE_RET_SHIFT)
#define PMC_IMPL_SW_OVERRIDE_CTRL_2_0_VAL_AOPG_CACHE_RET_RANGE                  0:0
#define PMC_IMPL_SW_OVERRIDE_CTRL_2_0_VAL_AOPG_CACHE_RET_MSB                    MK_SHIFT_CONST(0)
#define PMC_IMPL_SW_OVERRIDE_CTRL_2_0_VAL_AOPG_CACHE_RET_LSB                    MK_SHIFT_CONST(0)
#define PMC_IMPL_SW_OVERRIDE_CTRL_2_0_VAL_AOPG_CACHE_RET_WOFFSET                        0x0
#define PMC_IMPL_SW_OVERRIDE_CTRL_2_0_VAL_AOPG_CACHE_RET_DEFAULT                        MK_MASK_CONST(0x0)
#define PMC_IMPL_SW_OVERRIDE_CTRL_2_0_VAL_AOPG_CACHE_RET_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define PMC_IMPL_SW_OVERRIDE_CTRL_2_0_VAL_AOPG_CACHE_RET_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define PMC_IMPL_SW_OVERRIDE_CTRL_2_0_VAL_AOPG_CACHE_RET_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define PMC_IMPL_SW_OVERRIDE_CTRL_2_0_VAL_AOPG_CACHE_RET_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define PMC_IMPL_SW_OVERRIDE_CTRL_2_0_VAL_AOPG_CACHE_RET_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define PMC_IMPL_SW_OVERRIDE_CTRL_2_0_VAL_AOPG_CACHE_RET_INIT_ENUM                      DISABLE
#define PMC_IMPL_SW_OVERRIDE_CTRL_2_0_VAL_AOPG_CACHE_RET_ENABLE                 MK_ENUM_CONST(1)
#define PMC_IMPL_SW_OVERRIDE_CTRL_2_0_VAL_AOPG_CACHE_RET_DISABLE                        MK_ENUM_CONST(0)

// Override SLEEP value for AOPG RAM control signal
#define PMC_IMPL_SW_OVERRIDE_CTRL_2_0_VAL_AOPG_CACHE_SLEEP_SHIFT                        MK_SHIFT_CONST(1)
#define PMC_IMPL_SW_OVERRIDE_CTRL_2_0_VAL_AOPG_CACHE_SLEEP_FIELD                        MK_FIELD_CONST(0x3, PMC_IMPL_SW_OVERRIDE_CTRL_2_0_VAL_AOPG_CACHE_SLEEP_SHIFT)
#define PMC_IMPL_SW_OVERRIDE_CTRL_2_0_VAL_AOPG_CACHE_SLEEP_RANGE                        2:1
#define PMC_IMPL_SW_OVERRIDE_CTRL_2_0_VAL_AOPG_CACHE_SLEEP_MSB                  MK_SHIFT_CONST(2)
#define PMC_IMPL_SW_OVERRIDE_CTRL_2_0_VAL_AOPG_CACHE_SLEEP_LSB                  MK_SHIFT_CONST(1)
#define PMC_IMPL_SW_OVERRIDE_CTRL_2_0_VAL_AOPG_CACHE_SLEEP_WOFFSET                      0x0
#define PMC_IMPL_SW_OVERRIDE_CTRL_2_0_VAL_AOPG_CACHE_SLEEP_DEFAULT                      MK_MASK_CONST(0x0)
#define PMC_IMPL_SW_OVERRIDE_CTRL_2_0_VAL_AOPG_CACHE_SLEEP_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define PMC_IMPL_SW_OVERRIDE_CTRL_2_0_VAL_AOPG_CACHE_SLEEP_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define PMC_IMPL_SW_OVERRIDE_CTRL_2_0_VAL_AOPG_CACHE_SLEEP_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define PMC_IMPL_SW_OVERRIDE_CTRL_2_0_VAL_AOPG_CACHE_SLEEP_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define PMC_IMPL_SW_OVERRIDE_CTRL_2_0_VAL_AOPG_CACHE_SLEEP_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

// Override enable for AOPG RAM control signal
#define PMC_IMPL_SW_OVERRIDE_CTRL_2_0_EN_AOPG_CACHE_SHIFT                       MK_SHIFT_CONST(3)
#define PMC_IMPL_SW_OVERRIDE_CTRL_2_0_EN_AOPG_CACHE_FIELD                       MK_FIELD_CONST(0x1, PMC_IMPL_SW_OVERRIDE_CTRL_2_0_EN_AOPG_CACHE_SHIFT)
#define PMC_IMPL_SW_OVERRIDE_CTRL_2_0_EN_AOPG_CACHE_RANGE                       3:3
#define PMC_IMPL_SW_OVERRIDE_CTRL_2_0_EN_AOPG_CACHE_MSB                 MK_SHIFT_CONST(3)
#define PMC_IMPL_SW_OVERRIDE_CTRL_2_0_EN_AOPG_CACHE_LSB                 MK_SHIFT_CONST(3)
#define PMC_IMPL_SW_OVERRIDE_CTRL_2_0_EN_AOPG_CACHE_WOFFSET                     0x0
#define PMC_IMPL_SW_OVERRIDE_CTRL_2_0_EN_AOPG_CACHE_DEFAULT                     MK_MASK_CONST(0x0)
#define PMC_IMPL_SW_OVERRIDE_CTRL_2_0_EN_AOPG_CACHE_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define PMC_IMPL_SW_OVERRIDE_CTRL_2_0_EN_AOPG_CACHE_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define PMC_IMPL_SW_OVERRIDE_CTRL_2_0_EN_AOPG_CACHE_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define PMC_IMPL_SW_OVERRIDE_CTRL_2_0_EN_AOPG_CACHE_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define PMC_IMPL_SW_OVERRIDE_CTRL_2_0_EN_AOPG_CACHE_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define PMC_IMPL_SW_OVERRIDE_CTRL_2_0_EN_AOPG_CACHE_INIT_ENUM                   DISABLE
#define PMC_IMPL_SW_OVERRIDE_CTRL_2_0_EN_AOPG_CACHE_ENABLE                      MK_ENUM_CONST(1)
#define PMC_IMPL_SW_OVERRIDE_CTRL_2_0_EN_AOPG_CACHE_DISABLE                     MK_ENUM_CONST(0)

// Override RET value for AOPG RAM control signal
#define PMC_IMPL_SW_OVERRIDE_CTRL_2_0_VAL_AOPG_CAN0_RET_SHIFT                   MK_SHIFT_CONST(4)
#define PMC_IMPL_SW_OVERRIDE_CTRL_2_0_VAL_AOPG_CAN0_RET_FIELD                   MK_FIELD_CONST(0x1, PMC_IMPL_SW_OVERRIDE_CTRL_2_0_VAL_AOPG_CAN0_RET_SHIFT)
#define PMC_IMPL_SW_OVERRIDE_CTRL_2_0_VAL_AOPG_CAN0_RET_RANGE                   4:4
#define PMC_IMPL_SW_OVERRIDE_CTRL_2_0_VAL_AOPG_CAN0_RET_MSB                     MK_SHIFT_CONST(4)
#define PMC_IMPL_SW_OVERRIDE_CTRL_2_0_VAL_AOPG_CAN0_RET_LSB                     MK_SHIFT_CONST(4)
#define PMC_IMPL_SW_OVERRIDE_CTRL_2_0_VAL_AOPG_CAN0_RET_WOFFSET                 0x0
#define PMC_IMPL_SW_OVERRIDE_CTRL_2_0_VAL_AOPG_CAN0_RET_DEFAULT                 MK_MASK_CONST(0x0)
#define PMC_IMPL_SW_OVERRIDE_CTRL_2_0_VAL_AOPG_CAN0_RET_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define PMC_IMPL_SW_OVERRIDE_CTRL_2_0_VAL_AOPG_CAN0_RET_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define PMC_IMPL_SW_OVERRIDE_CTRL_2_0_VAL_AOPG_CAN0_RET_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define PMC_IMPL_SW_OVERRIDE_CTRL_2_0_VAL_AOPG_CAN0_RET_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define PMC_IMPL_SW_OVERRIDE_CTRL_2_0_VAL_AOPG_CAN0_RET_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define PMC_IMPL_SW_OVERRIDE_CTRL_2_0_VAL_AOPG_CAN0_RET_INIT_ENUM                       DISABLE
#define PMC_IMPL_SW_OVERRIDE_CTRL_2_0_VAL_AOPG_CAN0_RET_ENABLE                  MK_ENUM_CONST(1)
#define PMC_IMPL_SW_OVERRIDE_CTRL_2_0_VAL_AOPG_CAN0_RET_DISABLE                 MK_ENUM_CONST(0)

// Override SLEEP value for AOPG RAM control signal
#define PMC_IMPL_SW_OVERRIDE_CTRL_2_0_VAL_AOPG_CAN0_SLEEP_SHIFT                 MK_SHIFT_CONST(5)
#define PMC_IMPL_SW_OVERRIDE_CTRL_2_0_VAL_AOPG_CAN0_SLEEP_FIELD                 MK_FIELD_CONST(0x3, PMC_IMPL_SW_OVERRIDE_CTRL_2_0_VAL_AOPG_CAN0_SLEEP_SHIFT)
#define PMC_IMPL_SW_OVERRIDE_CTRL_2_0_VAL_AOPG_CAN0_SLEEP_RANGE                 6:5
#define PMC_IMPL_SW_OVERRIDE_CTRL_2_0_VAL_AOPG_CAN0_SLEEP_MSB                   MK_SHIFT_CONST(6)
#define PMC_IMPL_SW_OVERRIDE_CTRL_2_0_VAL_AOPG_CAN0_SLEEP_LSB                   MK_SHIFT_CONST(5)
#define PMC_IMPL_SW_OVERRIDE_CTRL_2_0_VAL_AOPG_CAN0_SLEEP_WOFFSET                       0x0
#define PMC_IMPL_SW_OVERRIDE_CTRL_2_0_VAL_AOPG_CAN0_SLEEP_DEFAULT                       MK_MASK_CONST(0x0)
#define PMC_IMPL_SW_OVERRIDE_CTRL_2_0_VAL_AOPG_CAN0_SLEEP_DEFAULT_MASK                  MK_MASK_CONST(0x3)
#define PMC_IMPL_SW_OVERRIDE_CTRL_2_0_VAL_AOPG_CAN0_SLEEP_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define PMC_IMPL_SW_OVERRIDE_CTRL_2_0_VAL_AOPG_CAN0_SLEEP_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define PMC_IMPL_SW_OVERRIDE_CTRL_2_0_VAL_AOPG_CAN0_SLEEP_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define PMC_IMPL_SW_OVERRIDE_CTRL_2_0_VAL_AOPG_CAN0_SLEEP_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

// Override enable for AOPG RAM control signal
#define PMC_IMPL_SW_OVERRIDE_CTRL_2_0_EN_AOPG_CAN0_SHIFT                        MK_SHIFT_CONST(7)
#define PMC_IMPL_SW_OVERRIDE_CTRL_2_0_EN_AOPG_CAN0_FIELD                        MK_FIELD_CONST(0x1, PMC_IMPL_SW_OVERRIDE_CTRL_2_0_EN_AOPG_CAN0_SHIFT)
#define PMC_IMPL_SW_OVERRIDE_CTRL_2_0_EN_AOPG_CAN0_RANGE                        7:7
#define PMC_IMPL_SW_OVERRIDE_CTRL_2_0_EN_AOPG_CAN0_MSB                  MK_SHIFT_CONST(7)
#define PMC_IMPL_SW_OVERRIDE_CTRL_2_0_EN_AOPG_CAN0_LSB                  MK_SHIFT_CONST(7)
#define PMC_IMPL_SW_OVERRIDE_CTRL_2_0_EN_AOPG_CAN0_WOFFSET                      0x0
#define PMC_IMPL_SW_OVERRIDE_CTRL_2_0_EN_AOPG_CAN0_DEFAULT                      MK_MASK_CONST(0x0)
#define PMC_IMPL_SW_OVERRIDE_CTRL_2_0_EN_AOPG_CAN0_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define PMC_IMPL_SW_OVERRIDE_CTRL_2_0_EN_AOPG_CAN0_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define PMC_IMPL_SW_OVERRIDE_CTRL_2_0_EN_AOPG_CAN0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define PMC_IMPL_SW_OVERRIDE_CTRL_2_0_EN_AOPG_CAN0_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define PMC_IMPL_SW_OVERRIDE_CTRL_2_0_EN_AOPG_CAN0_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define PMC_IMPL_SW_OVERRIDE_CTRL_2_0_EN_AOPG_CAN0_INIT_ENUM                    DISABLE
#define PMC_IMPL_SW_OVERRIDE_CTRL_2_0_EN_AOPG_CAN0_ENABLE                       MK_ENUM_CONST(1)
#define PMC_IMPL_SW_OVERRIDE_CTRL_2_0_EN_AOPG_CAN0_DISABLE                      MK_ENUM_CONST(0)

// Override RET value for AOPG RAM control signal
#define PMC_IMPL_SW_OVERRIDE_CTRL_2_0_VAL_AOPG_CAN1_RET_SHIFT                   MK_SHIFT_CONST(8)
#define PMC_IMPL_SW_OVERRIDE_CTRL_2_0_VAL_AOPG_CAN1_RET_FIELD                   MK_FIELD_CONST(0x1, PMC_IMPL_SW_OVERRIDE_CTRL_2_0_VAL_AOPG_CAN1_RET_SHIFT)
#define PMC_IMPL_SW_OVERRIDE_CTRL_2_0_VAL_AOPG_CAN1_RET_RANGE                   8:8
#define PMC_IMPL_SW_OVERRIDE_CTRL_2_0_VAL_AOPG_CAN1_RET_MSB                     MK_SHIFT_CONST(8)
#define PMC_IMPL_SW_OVERRIDE_CTRL_2_0_VAL_AOPG_CAN1_RET_LSB                     MK_SHIFT_CONST(8)
#define PMC_IMPL_SW_OVERRIDE_CTRL_2_0_VAL_AOPG_CAN1_RET_WOFFSET                 0x0
#define PMC_IMPL_SW_OVERRIDE_CTRL_2_0_VAL_AOPG_CAN1_RET_DEFAULT                 MK_MASK_CONST(0x0)
#define PMC_IMPL_SW_OVERRIDE_CTRL_2_0_VAL_AOPG_CAN1_RET_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define PMC_IMPL_SW_OVERRIDE_CTRL_2_0_VAL_AOPG_CAN1_RET_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define PMC_IMPL_SW_OVERRIDE_CTRL_2_0_VAL_AOPG_CAN1_RET_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define PMC_IMPL_SW_OVERRIDE_CTRL_2_0_VAL_AOPG_CAN1_RET_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define PMC_IMPL_SW_OVERRIDE_CTRL_2_0_VAL_AOPG_CAN1_RET_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define PMC_IMPL_SW_OVERRIDE_CTRL_2_0_VAL_AOPG_CAN1_RET_INIT_ENUM                       DISABLE
#define PMC_IMPL_SW_OVERRIDE_CTRL_2_0_VAL_AOPG_CAN1_RET_ENABLE                  MK_ENUM_CONST(1)
#define PMC_IMPL_SW_OVERRIDE_CTRL_2_0_VAL_AOPG_CAN1_RET_DISABLE                 MK_ENUM_CONST(0)

// Override SLEEP value for AOPG RAM control signal
#define PMC_IMPL_SW_OVERRIDE_CTRL_2_0_VAL_AOPG_CAN1_SLEEP_SHIFT                 MK_SHIFT_CONST(9)
#define PMC_IMPL_SW_OVERRIDE_CTRL_2_0_VAL_AOPG_CAN1_SLEEP_FIELD                 MK_FIELD_CONST(0x3, PMC_IMPL_SW_OVERRIDE_CTRL_2_0_VAL_AOPG_CAN1_SLEEP_SHIFT)
#define PMC_IMPL_SW_OVERRIDE_CTRL_2_0_VAL_AOPG_CAN1_SLEEP_RANGE                 10:9
#define PMC_IMPL_SW_OVERRIDE_CTRL_2_0_VAL_AOPG_CAN1_SLEEP_MSB                   MK_SHIFT_CONST(10)
#define PMC_IMPL_SW_OVERRIDE_CTRL_2_0_VAL_AOPG_CAN1_SLEEP_LSB                   MK_SHIFT_CONST(9)
#define PMC_IMPL_SW_OVERRIDE_CTRL_2_0_VAL_AOPG_CAN1_SLEEP_WOFFSET                       0x0
#define PMC_IMPL_SW_OVERRIDE_CTRL_2_0_VAL_AOPG_CAN1_SLEEP_DEFAULT                       MK_MASK_CONST(0x0)
#define PMC_IMPL_SW_OVERRIDE_CTRL_2_0_VAL_AOPG_CAN1_SLEEP_DEFAULT_MASK                  MK_MASK_CONST(0x3)
#define PMC_IMPL_SW_OVERRIDE_CTRL_2_0_VAL_AOPG_CAN1_SLEEP_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define PMC_IMPL_SW_OVERRIDE_CTRL_2_0_VAL_AOPG_CAN1_SLEEP_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define PMC_IMPL_SW_OVERRIDE_CTRL_2_0_VAL_AOPG_CAN1_SLEEP_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define PMC_IMPL_SW_OVERRIDE_CTRL_2_0_VAL_AOPG_CAN1_SLEEP_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

// Override enable for AOPG RAM control signal
#define PMC_IMPL_SW_OVERRIDE_CTRL_2_0_EN_AOPG_CAN1_SHIFT                        MK_SHIFT_CONST(11)
#define PMC_IMPL_SW_OVERRIDE_CTRL_2_0_EN_AOPG_CAN1_FIELD                        MK_FIELD_CONST(0x1, PMC_IMPL_SW_OVERRIDE_CTRL_2_0_EN_AOPG_CAN1_SHIFT)
#define PMC_IMPL_SW_OVERRIDE_CTRL_2_0_EN_AOPG_CAN1_RANGE                        11:11
#define PMC_IMPL_SW_OVERRIDE_CTRL_2_0_EN_AOPG_CAN1_MSB                  MK_SHIFT_CONST(11)
#define PMC_IMPL_SW_OVERRIDE_CTRL_2_0_EN_AOPG_CAN1_LSB                  MK_SHIFT_CONST(11)
#define PMC_IMPL_SW_OVERRIDE_CTRL_2_0_EN_AOPG_CAN1_WOFFSET                      0x0
#define PMC_IMPL_SW_OVERRIDE_CTRL_2_0_EN_AOPG_CAN1_DEFAULT                      MK_MASK_CONST(0x0)
#define PMC_IMPL_SW_OVERRIDE_CTRL_2_0_EN_AOPG_CAN1_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define PMC_IMPL_SW_OVERRIDE_CTRL_2_0_EN_AOPG_CAN1_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define PMC_IMPL_SW_OVERRIDE_CTRL_2_0_EN_AOPG_CAN1_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define PMC_IMPL_SW_OVERRIDE_CTRL_2_0_EN_AOPG_CAN1_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define PMC_IMPL_SW_OVERRIDE_CTRL_2_0_EN_AOPG_CAN1_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define PMC_IMPL_SW_OVERRIDE_CTRL_2_0_EN_AOPG_CAN1_INIT_ENUM                    DISABLE
#define PMC_IMPL_SW_OVERRIDE_CTRL_2_0_EN_AOPG_CAN1_ENABLE                       MK_ENUM_CONST(1)
#define PMC_IMPL_SW_OVERRIDE_CTRL_2_0_EN_AOPG_CAN1_DISABLE                      MK_ENUM_CONST(0)

// Override common zone value
#define PMC_IMPL_SW_OVERRIDE_CTRL_2_0_VAL_COMMON_ZONE_SHIFT                     MK_SHIFT_CONST(12)
#define PMC_IMPL_SW_OVERRIDE_CTRL_2_0_VAL_COMMON_ZONE_FIELD                     MK_FIELD_CONST(0xff, PMC_IMPL_SW_OVERRIDE_CTRL_2_0_VAL_COMMON_ZONE_SHIFT)
#define PMC_IMPL_SW_OVERRIDE_CTRL_2_0_VAL_COMMON_ZONE_RANGE                     19:12
#define PMC_IMPL_SW_OVERRIDE_CTRL_2_0_VAL_COMMON_ZONE_MSB                       MK_SHIFT_CONST(19)
#define PMC_IMPL_SW_OVERRIDE_CTRL_2_0_VAL_COMMON_ZONE_LSB                       MK_SHIFT_CONST(12)
#define PMC_IMPL_SW_OVERRIDE_CTRL_2_0_VAL_COMMON_ZONE_WOFFSET                   0x0
#define PMC_IMPL_SW_OVERRIDE_CTRL_2_0_VAL_COMMON_ZONE_DEFAULT                   MK_MASK_CONST(0x0)
#define PMC_IMPL_SW_OVERRIDE_CTRL_2_0_VAL_COMMON_ZONE_DEFAULT_MASK                      MK_MASK_CONST(0xff)
#define PMC_IMPL_SW_OVERRIDE_CTRL_2_0_VAL_COMMON_ZONE_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define PMC_IMPL_SW_OVERRIDE_CTRL_2_0_VAL_COMMON_ZONE_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define PMC_IMPL_SW_OVERRIDE_CTRL_2_0_VAL_COMMON_ZONE_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define PMC_IMPL_SW_OVERRIDE_CTRL_2_0_VAL_COMMON_ZONE_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

// Override enable common zone
#define PMC_IMPL_SW_OVERRIDE_CTRL_2_0_EN_COMMON_ZONE_SHIFT                      MK_SHIFT_CONST(20)
#define PMC_IMPL_SW_OVERRIDE_CTRL_2_0_EN_COMMON_ZONE_FIELD                      MK_FIELD_CONST(0x1, PMC_IMPL_SW_OVERRIDE_CTRL_2_0_EN_COMMON_ZONE_SHIFT)
#define PMC_IMPL_SW_OVERRIDE_CTRL_2_0_EN_COMMON_ZONE_RANGE                      20:20
#define PMC_IMPL_SW_OVERRIDE_CTRL_2_0_EN_COMMON_ZONE_MSB                        MK_SHIFT_CONST(20)
#define PMC_IMPL_SW_OVERRIDE_CTRL_2_0_EN_COMMON_ZONE_LSB                        MK_SHIFT_CONST(20)
#define PMC_IMPL_SW_OVERRIDE_CTRL_2_0_EN_COMMON_ZONE_WOFFSET                    0x0
#define PMC_IMPL_SW_OVERRIDE_CTRL_2_0_EN_COMMON_ZONE_DEFAULT                    MK_MASK_CONST(0x0)
#define PMC_IMPL_SW_OVERRIDE_CTRL_2_0_EN_COMMON_ZONE_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define PMC_IMPL_SW_OVERRIDE_CTRL_2_0_EN_COMMON_ZONE_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define PMC_IMPL_SW_OVERRIDE_CTRL_2_0_EN_COMMON_ZONE_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define PMC_IMPL_SW_OVERRIDE_CTRL_2_0_EN_COMMON_ZONE_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define PMC_IMPL_SW_OVERRIDE_CTRL_2_0_EN_COMMON_ZONE_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define PMC_IMPL_SW_OVERRIDE_CTRL_2_0_EN_COMMON_ZONE_INIT_ENUM                  DISABLE
#define PMC_IMPL_SW_OVERRIDE_CTRL_2_0_EN_COMMON_ZONE_ENABLE                     MK_ENUM_CONST(1)
#define PMC_IMPL_SW_OVERRIDE_CTRL_2_0_EN_COMMON_ZONE_DISABLE                    MK_ENUM_CONST(0)


// Register PMC_IMPL_MISC_CTRL_0
#define PMC_IMPL_MISC_CTRL_0                    MK_ADDR_CONST(0x6e4)
#define PMC_IMPL_MISC_CTRL_0_SECURE                     0x0
#define PMC_IMPL_MISC_CTRL_0_DUAL                       0x0
#define PMC_IMPL_MISC_CTRL_0_SCR                        PG_MISC_SCR_0
#define PMC_IMPL_MISC_CTRL_0_SCRREG                     PMC_IMPL_SCR_PG_MISC_SCR_0
#define PMC_IMPL_MISC_CTRL_0_WORD_COUNT                         0x1
#define PMC_IMPL_MISC_CTRL_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define PMC_IMPL_MISC_CTRL_0_RESET_MASK                         MK_MASK_CONST(0x1)
#define PMC_IMPL_MISC_CTRL_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define PMC_IMPL_MISC_CTRL_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define PMC_IMPL_MISC_CTRL_0_READ_MASK                  MK_MASK_CONST(0x1)
#define PMC_IMPL_MISC_CTRL_0_WRITE_MASK                         MK_MASK_CONST(0x1)
// CYA for ALL AOPG RAMs to be handled in one shot for a single HW req
#define PMC_IMPL_MISC_CTRL_0_HW_AOPG_ALLRAMS_SHIFT                      MK_SHIFT_CONST(0)
#define PMC_IMPL_MISC_CTRL_0_HW_AOPG_ALLRAMS_FIELD                      MK_FIELD_CONST(0x1, PMC_IMPL_MISC_CTRL_0_HW_AOPG_ALLRAMS_SHIFT)
#define PMC_IMPL_MISC_CTRL_0_HW_AOPG_ALLRAMS_RANGE                      0:0
#define PMC_IMPL_MISC_CTRL_0_HW_AOPG_ALLRAMS_MSB                        MK_SHIFT_CONST(0)
#define PMC_IMPL_MISC_CTRL_0_HW_AOPG_ALLRAMS_LSB                        MK_SHIFT_CONST(0)
#define PMC_IMPL_MISC_CTRL_0_HW_AOPG_ALLRAMS_WOFFSET                    0x0
#define PMC_IMPL_MISC_CTRL_0_HW_AOPG_ALLRAMS_DEFAULT                    MK_MASK_CONST(0x0)
#define PMC_IMPL_MISC_CTRL_0_HW_AOPG_ALLRAMS_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define PMC_IMPL_MISC_CTRL_0_HW_AOPG_ALLRAMS_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define PMC_IMPL_MISC_CTRL_0_HW_AOPG_ALLRAMS_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define PMC_IMPL_MISC_CTRL_0_HW_AOPG_ALLRAMS_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define PMC_IMPL_MISC_CTRL_0_HW_AOPG_ALLRAMS_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define PMC_IMPL_MISC_CTRL_0_HW_AOPG_ALLRAMS_INIT_ENUM                  DISABLE
#define PMC_IMPL_MISC_CTRL_0_HW_AOPG_ALLRAMS_ENABLE                     MK_ENUM_CONST(1)
#define PMC_IMPL_MISC_CTRL_0_HW_AOPG_ALLRAMS_DISABLE                    MK_ENUM_CONST(0)


// Reserved address 0x6e8

// Reserved address 0x6ec

// Reserved address 0x6f0

// Reserved address 0x6f4

// Reserved address 0x6f8

// Reserved address 0x6fc
//---------------------------------------------------------------------------------
//     PMC2LIC interrupt
//---------------------------------------------------------------------------------

// Register PMC_IMPL_PMC2LIC_INTR_STATUS_0
#define PMC_IMPL_PMC2LIC_INTR_STATUS_0                  MK_ADDR_CONST(0x800)
#define PMC_IMPL_PMC2LIC_INTR_STATUS_0_SECURE                   0x0
#define PMC_IMPL_PMC2LIC_INTR_STATUS_0_DUAL                     0x0
#define PMC_IMPL_PMC2LIC_INTR_STATUS_0_SCR                      CNTRL_SCR_0
#define PMC_IMPL_PMC2LIC_INTR_STATUS_0_SCRREG                   PMC_IMPL_SCR_CNTRL_SCR_0
#define PMC_IMPL_PMC2LIC_INTR_STATUS_0_WORD_COUNT                       0x1
#define PMC_IMPL_PMC2LIC_INTR_STATUS_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define PMC_IMPL_PMC2LIC_INTR_STATUS_0_RESET_MASK                       MK_MASK_CONST(0x3)
#define PMC_IMPL_PMC2LIC_INTR_STATUS_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define PMC_IMPL_PMC2LIC_INTR_STATUS_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define PMC_IMPL_PMC2LIC_INTR_STATUS_0_READ_MASK                        MK_MASK_CONST(0x3)
#define PMC_IMPL_PMC2LIC_INTR_STATUS_0_WRITE_MASK                       MK_MASK_CONST(0x3)
//Set when SW requests an illegal power control request to a partition.
//i.e. SRAM not in any power mode and logic sleep is requested.
//HW will handle this properly: automatically set SRAM into sleep mode.
//Writing "1" to this bit will cause the status cleared
#define PMC_IMPL_PMC2LIC_INTR_STATUS_0_ILLEGAL_SRAM_LOGIC_POWER_STATE_SHIFT                     MK_SHIFT_CONST(1)
#define PMC_IMPL_PMC2LIC_INTR_STATUS_0_ILLEGAL_SRAM_LOGIC_POWER_STATE_FIELD                     MK_FIELD_CONST(0x1, PMC_IMPL_PMC2LIC_INTR_STATUS_0_ILLEGAL_SRAM_LOGIC_POWER_STATE_SHIFT)
#define PMC_IMPL_PMC2LIC_INTR_STATUS_0_ILLEGAL_SRAM_LOGIC_POWER_STATE_RANGE                     1:1
#define PMC_IMPL_PMC2LIC_INTR_STATUS_0_ILLEGAL_SRAM_LOGIC_POWER_STATE_MSB                       MK_SHIFT_CONST(1)
#define PMC_IMPL_PMC2LIC_INTR_STATUS_0_ILLEGAL_SRAM_LOGIC_POWER_STATE_LSB                       MK_SHIFT_CONST(1)
#define PMC_IMPL_PMC2LIC_INTR_STATUS_0_ILLEGAL_SRAM_LOGIC_POWER_STATE_WOFFSET                   0x0
#define PMC_IMPL_PMC2LIC_INTR_STATUS_0_ILLEGAL_SRAM_LOGIC_POWER_STATE_DEFAULT                   MK_MASK_CONST(0x0)
#define PMC_IMPL_PMC2LIC_INTR_STATUS_0_ILLEGAL_SRAM_LOGIC_POWER_STATE_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define PMC_IMPL_PMC2LIC_INTR_STATUS_0_ILLEGAL_SRAM_LOGIC_POWER_STATE_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define PMC_IMPL_PMC2LIC_INTR_STATUS_0_ILLEGAL_SRAM_LOGIC_POWER_STATE_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define PMC_IMPL_PMC2LIC_INTR_STATUS_0_ILLEGAL_SRAM_LOGIC_POWER_STATE_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define PMC_IMPL_PMC2LIC_INTR_STATUS_0_ILLEGAL_SRAM_LOGIC_POWER_STATE_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

//Set when SW requests a power gating scenario, which is not supported in PG sequencer.
//i.e. Requested transition is to do some mixing transition of "do-ret/sleep/lsleep" and
// "undo-ret/sleep/lsleep"
//HW will take the "do" PG as higher priority.
//Writing "1" to this bit will cause the status cleared
#define PMC_IMPL_PMC2LIC_INTR_STATUS_0_UNSUPPORTED_PG_REQUEST_SHIFT                     MK_SHIFT_CONST(0)
#define PMC_IMPL_PMC2LIC_INTR_STATUS_0_UNSUPPORTED_PG_REQUEST_FIELD                     MK_FIELD_CONST(0x1, PMC_IMPL_PMC2LIC_INTR_STATUS_0_UNSUPPORTED_PG_REQUEST_SHIFT)
#define PMC_IMPL_PMC2LIC_INTR_STATUS_0_UNSUPPORTED_PG_REQUEST_RANGE                     0:0
#define PMC_IMPL_PMC2LIC_INTR_STATUS_0_UNSUPPORTED_PG_REQUEST_MSB                       MK_SHIFT_CONST(0)
#define PMC_IMPL_PMC2LIC_INTR_STATUS_0_UNSUPPORTED_PG_REQUEST_LSB                       MK_SHIFT_CONST(0)
#define PMC_IMPL_PMC2LIC_INTR_STATUS_0_UNSUPPORTED_PG_REQUEST_WOFFSET                   0x0
#define PMC_IMPL_PMC2LIC_INTR_STATUS_0_UNSUPPORTED_PG_REQUEST_DEFAULT                   MK_MASK_CONST(0x0)
#define PMC_IMPL_PMC2LIC_INTR_STATUS_0_UNSUPPORTED_PG_REQUEST_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define PMC_IMPL_PMC2LIC_INTR_STATUS_0_UNSUPPORTED_PG_REQUEST_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define PMC_IMPL_PMC2LIC_INTR_STATUS_0_UNSUPPORTED_PG_REQUEST_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define PMC_IMPL_PMC2LIC_INTR_STATUS_0_UNSUPPORTED_PG_REQUEST_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define PMC_IMPL_PMC2LIC_INTR_STATUS_0_UNSUPPORTED_PG_REQUEST_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register PMC_IMPL_PMC2LIC_INTR_ENABLE_0
#define PMC_IMPL_PMC2LIC_INTR_ENABLE_0                  MK_ADDR_CONST(0x804)
#define PMC_IMPL_PMC2LIC_INTR_ENABLE_0_SECURE                   0x0
#define PMC_IMPL_PMC2LIC_INTR_ENABLE_0_DUAL                     0x0
#define PMC_IMPL_PMC2LIC_INTR_ENABLE_0_SCR                      CNTRL_SCR_0
#define PMC_IMPL_PMC2LIC_INTR_ENABLE_0_SCRREG                   PMC_IMPL_SCR_CNTRL_SCR_0
#define PMC_IMPL_PMC2LIC_INTR_ENABLE_0_WORD_COUNT                       0x1
#define PMC_IMPL_PMC2LIC_INTR_ENABLE_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define PMC_IMPL_PMC2LIC_INTR_ENABLE_0_RESET_MASK                       MK_MASK_CONST(0x3)
#define PMC_IMPL_PMC2LIC_INTR_ENABLE_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define PMC_IMPL_PMC2LIC_INTR_ENABLE_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define PMC_IMPL_PMC2LIC_INTR_ENABLE_0_READ_MASK                        MK_MASK_CONST(0x3)
#define PMC_IMPL_PMC2LIC_INTR_ENABLE_0_WRITE_MASK                       MK_MASK_CONST(0x3)
//ENABLE bit for this interrupt source
#define PMC_IMPL_PMC2LIC_INTR_ENABLE_0_ILLEGAL_SRAM_LOGIC_POWER_STATE_SHIFT                     MK_SHIFT_CONST(1)
#define PMC_IMPL_PMC2LIC_INTR_ENABLE_0_ILLEGAL_SRAM_LOGIC_POWER_STATE_FIELD                     MK_FIELD_CONST(0x1, PMC_IMPL_PMC2LIC_INTR_ENABLE_0_ILLEGAL_SRAM_LOGIC_POWER_STATE_SHIFT)
#define PMC_IMPL_PMC2LIC_INTR_ENABLE_0_ILLEGAL_SRAM_LOGIC_POWER_STATE_RANGE                     1:1
#define PMC_IMPL_PMC2LIC_INTR_ENABLE_0_ILLEGAL_SRAM_LOGIC_POWER_STATE_MSB                       MK_SHIFT_CONST(1)
#define PMC_IMPL_PMC2LIC_INTR_ENABLE_0_ILLEGAL_SRAM_LOGIC_POWER_STATE_LSB                       MK_SHIFT_CONST(1)
#define PMC_IMPL_PMC2LIC_INTR_ENABLE_0_ILLEGAL_SRAM_LOGIC_POWER_STATE_WOFFSET                   0x0
#define PMC_IMPL_PMC2LIC_INTR_ENABLE_0_ILLEGAL_SRAM_LOGIC_POWER_STATE_DEFAULT                   MK_MASK_CONST(0x0)
#define PMC_IMPL_PMC2LIC_INTR_ENABLE_0_ILLEGAL_SRAM_LOGIC_POWER_STATE_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define PMC_IMPL_PMC2LIC_INTR_ENABLE_0_ILLEGAL_SRAM_LOGIC_POWER_STATE_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define PMC_IMPL_PMC2LIC_INTR_ENABLE_0_ILLEGAL_SRAM_LOGIC_POWER_STATE_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define PMC_IMPL_PMC2LIC_INTR_ENABLE_0_ILLEGAL_SRAM_LOGIC_POWER_STATE_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define PMC_IMPL_PMC2LIC_INTR_ENABLE_0_ILLEGAL_SRAM_LOGIC_POWER_STATE_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define PMC_IMPL_PMC2LIC_INTR_ENABLE_0_ILLEGAL_SRAM_LOGIC_POWER_STATE_INIT_ENUM                 DISABLE
#define PMC_IMPL_PMC2LIC_INTR_ENABLE_0_ILLEGAL_SRAM_LOGIC_POWER_STATE_DISABLE                   MK_ENUM_CONST(0)
#define PMC_IMPL_PMC2LIC_INTR_ENABLE_0_ILLEGAL_SRAM_LOGIC_POWER_STATE_ENABLE                    MK_ENUM_CONST(1)

//ENABLE bit for this interrupt source
#define PMC_IMPL_PMC2LIC_INTR_ENABLE_0_UNSUPPORTED_PG_REQUEST_SHIFT                     MK_SHIFT_CONST(0)
#define PMC_IMPL_PMC2LIC_INTR_ENABLE_0_UNSUPPORTED_PG_REQUEST_FIELD                     MK_FIELD_CONST(0x1, PMC_IMPL_PMC2LIC_INTR_ENABLE_0_UNSUPPORTED_PG_REQUEST_SHIFT)
#define PMC_IMPL_PMC2LIC_INTR_ENABLE_0_UNSUPPORTED_PG_REQUEST_RANGE                     0:0
#define PMC_IMPL_PMC2LIC_INTR_ENABLE_0_UNSUPPORTED_PG_REQUEST_MSB                       MK_SHIFT_CONST(0)
#define PMC_IMPL_PMC2LIC_INTR_ENABLE_0_UNSUPPORTED_PG_REQUEST_LSB                       MK_SHIFT_CONST(0)
#define PMC_IMPL_PMC2LIC_INTR_ENABLE_0_UNSUPPORTED_PG_REQUEST_WOFFSET                   0x0
#define PMC_IMPL_PMC2LIC_INTR_ENABLE_0_UNSUPPORTED_PG_REQUEST_DEFAULT                   MK_MASK_CONST(0x0)
#define PMC_IMPL_PMC2LIC_INTR_ENABLE_0_UNSUPPORTED_PG_REQUEST_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define PMC_IMPL_PMC2LIC_INTR_ENABLE_0_UNSUPPORTED_PG_REQUEST_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define PMC_IMPL_PMC2LIC_INTR_ENABLE_0_UNSUPPORTED_PG_REQUEST_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define PMC_IMPL_PMC2LIC_INTR_ENABLE_0_UNSUPPORTED_PG_REQUEST_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define PMC_IMPL_PMC2LIC_INTR_ENABLE_0_UNSUPPORTED_PG_REQUEST_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define PMC_IMPL_PMC2LIC_INTR_ENABLE_0_UNSUPPORTED_PG_REQUEST_INIT_ENUM                 DISABLE
#define PMC_IMPL_PMC2LIC_INTR_ENABLE_0_UNSUPPORTED_PG_REQUEST_DISABLE                   MK_ENUM_CONST(0)
#define PMC_IMPL_PMC2LIC_INTR_ENABLE_0_UNSUPPORTED_PG_REQUEST_ENABLE                    MK_ENUM_CONST(1)


// Reserved address 0x808

// Reserved address 0x80c

// Reserved address 0x810
//---------------------------------------------------------------------------------
// DPD FSM STATE register - for debug info
//---------------------------------------------------------------------------------

// Reserved address 0x814
//DPD_FSM_STATUS

// Register PMC_IMPL_RAMDUMP_FIQ_EXIT_0
#define PMC_IMPL_RAMDUMP_FIQ_EXIT_0                     MK_ADDR_CONST(0x81c)
#define PMC_IMPL_RAMDUMP_FIQ_EXIT_0_SECURE                      0x0
#define PMC_IMPL_RAMDUMP_FIQ_EXIT_0_DUAL                        0x0
#define PMC_IMPL_RAMDUMP_FIQ_EXIT_0_SCR                         RAMDUMP_COM_SCR_0
#define PMC_IMPL_RAMDUMP_FIQ_EXIT_0_SCRREG                      PMC_IMPL_SCR_RAMDUMP_COM_SCR_0
#define PMC_IMPL_RAMDUMP_FIQ_EXIT_0_WORD_COUNT                  0x1
#define PMC_IMPL_RAMDUMP_FIQ_EXIT_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define PMC_IMPL_RAMDUMP_FIQ_EXIT_0_RESET_MASK                  MK_MASK_CONST(0x1)
#define PMC_IMPL_RAMDUMP_FIQ_EXIT_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define PMC_IMPL_RAMDUMP_FIQ_EXIT_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define PMC_IMPL_RAMDUMP_FIQ_EXIT_0_READ_MASK                   MK_MASK_CONST(0x1)
#define PMC_IMPL_RAMDUMP_FIQ_EXIT_0_WRITE_MASK                  MK_MASK_CONST(0x1)
//Not used by HW
#define PMC_IMPL_RAMDUMP_FIQ_EXIT_0_PVA0_FIQ_EXITED_GRACEFULLY_SHIFT                    MK_SHIFT_CONST(0)
#define PMC_IMPL_RAMDUMP_FIQ_EXIT_0_PVA0_FIQ_EXITED_GRACEFULLY_FIELD                    MK_FIELD_CONST(0x1, PMC_IMPL_RAMDUMP_FIQ_EXIT_0_PVA0_FIQ_EXITED_GRACEFULLY_SHIFT)
#define PMC_IMPL_RAMDUMP_FIQ_EXIT_0_PVA0_FIQ_EXITED_GRACEFULLY_RANGE                    0:0
#define PMC_IMPL_RAMDUMP_FIQ_EXIT_0_PVA0_FIQ_EXITED_GRACEFULLY_MSB                      MK_SHIFT_CONST(0)
#define PMC_IMPL_RAMDUMP_FIQ_EXIT_0_PVA0_FIQ_EXITED_GRACEFULLY_LSB                      MK_SHIFT_CONST(0)
#define PMC_IMPL_RAMDUMP_FIQ_EXIT_0_PVA0_FIQ_EXITED_GRACEFULLY_WOFFSET                  0x0
#define PMC_IMPL_RAMDUMP_FIQ_EXIT_0_PVA0_FIQ_EXITED_GRACEFULLY_DEFAULT                  MK_MASK_CONST(0x0)
#define PMC_IMPL_RAMDUMP_FIQ_EXIT_0_PVA0_FIQ_EXITED_GRACEFULLY_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define PMC_IMPL_RAMDUMP_FIQ_EXIT_0_PVA0_FIQ_EXITED_GRACEFULLY_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define PMC_IMPL_RAMDUMP_FIQ_EXIT_0_PVA0_FIQ_EXITED_GRACEFULLY_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define PMC_IMPL_RAMDUMP_FIQ_EXIT_0_PVA0_FIQ_EXITED_GRACEFULLY_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define PMC_IMPL_RAMDUMP_FIQ_EXIT_0_PVA0_FIQ_EXITED_GRACEFULLY_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)


// Register PMC_IMPL_SET_RAMDUMP_FIQ_EXIT_0
#define PMC_IMPL_SET_RAMDUMP_FIQ_EXIT_0                 MK_ADDR_CONST(0x820)
#define PMC_IMPL_SET_RAMDUMP_FIQ_EXIT_0_SECURE                  0x0
#define PMC_IMPL_SET_RAMDUMP_FIQ_EXIT_0_DUAL                    0x0
#define PMC_IMPL_SET_RAMDUMP_FIQ_EXIT_0_SCR                     RAMDUMP_COM_SCR_0
#define PMC_IMPL_SET_RAMDUMP_FIQ_EXIT_0_SCRREG                  PMC_IMPL_SCR_RAMDUMP_COM_SCR_0
#define PMC_IMPL_SET_RAMDUMP_FIQ_EXIT_0_WORD_COUNT                      0x1
#define PMC_IMPL_SET_RAMDUMP_FIQ_EXIT_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define PMC_IMPL_SET_RAMDUMP_FIQ_EXIT_0_RESET_MASK                      MK_MASK_CONST(0x1)
#define PMC_IMPL_SET_RAMDUMP_FIQ_EXIT_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define PMC_IMPL_SET_RAMDUMP_FIQ_EXIT_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define PMC_IMPL_SET_RAMDUMP_FIQ_EXIT_0_READ_MASK                       MK_MASK_CONST(0x0)
#define PMC_IMPL_SET_RAMDUMP_FIQ_EXIT_0_WRITE_MASK                      MK_MASK_CONST(0x1)
//Set PVA0_FIQ_EXITED_GRACEFULLY
#define PMC_IMPL_SET_RAMDUMP_FIQ_EXIT_0_SET_PVA0_FIQ_EXITED_GRACEFULLY_SHIFT                    MK_SHIFT_CONST(0)
#define PMC_IMPL_SET_RAMDUMP_FIQ_EXIT_0_SET_PVA0_FIQ_EXITED_GRACEFULLY_FIELD                    MK_FIELD_CONST(0x1, PMC_IMPL_SET_RAMDUMP_FIQ_EXIT_0_SET_PVA0_FIQ_EXITED_GRACEFULLY_SHIFT)
#define PMC_IMPL_SET_RAMDUMP_FIQ_EXIT_0_SET_PVA0_FIQ_EXITED_GRACEFULLY_RANGE                    0:0
#define PMC_IMPL_SET_RAMDUMP_FIQ_EXIT_0_SET_PVA0_FIQ_EXITED_GRACEFULLY_MSB                      MK_SHIFT_CONST(0)
#define PMC_IMPL_SET_RAMDUMP_FIQ_EXIT_0_SET_PVA0_FIQ_EXITED_GRACEFULLY_LSB                      MK_SHIFT_CONST(0)
#define PMC_IMPL_SET_RAMDUMP_FIQ_EXIT_0_SET_PVA0_FIQ_EXITED_GRACEFULLY_WOFFSET                  0x0
#define PMC_IMPL_SET_RAMDUMP_FIQ_EXIT_0_SET_PVA0_FIQ_EXITED_GRACEFULLY_DEFAULT                  MK_MASK_CONST(0x0)
#define PMC_IMPL_SET_RAMDUMP_FIQ_EXIT_0_SET_PVA0_FIQ_EXITED_GRACEFULLY_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define PMC_IMPL_SET_RAMDUMP_FIQ_EXIT_0_SET_PVA0_FIQ_EXITED_GRACEFULLY_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define PMC_IMPL_SET_RAMDUMP_FIQ_EXIT_0_SET_PVA0_FIQ_EXITED_GRACEFULLY_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define PMC_IMPL_SET_RAMDUMP_FIQ_EXIT_0_SET_PVA0_FIQ_EXITED_GRACEFULLY_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define PMC_IMPL_SET_RAMDUMP_FIQ_EXIT_0_SET_PVA0_FIQ_EXITED_GRACEFULLY_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)


// Register PMC_IMPL_CLR_RAMDUMP_FIQ_EXIT_0
#define PMC_IMPL_CLR_RAMDUMP_FIQ_EXIT_0                 MK_ADDR_CONST(0x824)
#define PMC_IMPL_CLR_RAMDUMP_FIQ_EXIT_0_SECURE                  0x0
#define PMC_IMPL_CLR_RAMDUMP_FIQ_EXIT_0_DUAL                    0x0
#define PMC_IMPL_CLR_RAMDUMP_FIQ_EXIT_0_SCR                     RAMDUMP_COM_SCR_0
#define PMC_IMPL_CLR_RAMDUMP_FIQ_EXIT_0_SCRREG                  PMC_IMPL_SCR_RAMDUMP_COM_SCR_0
#define PMC_IMPL_CLR_RAMDUMP_FIQ_EXIT_0_WORD_COUNT                      0x1
#define PMC_IMPL_CLR_RAMDUMP_FIQ_EXIT_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define PMC_IMPL_CLR_RAMDUMP_FIQ_EXIT_0_RESET_MASK                      MK_MASK_CONST(0x1)
#define PMC_IMPL_CLR_RAMDUMP_FIQ_EXIT_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define PMC_IMPL_CLR_RAMDUMP_FIQ_EXIT_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define PMC_IMPL_CLR_RAMDUMP_FIQ_EXIT_0_READ_MASK                       MK_MASK_CONST(0x0)
#define PMC_IMPL_CLR_RAMDUMP_FIQ_EXIT_0_WRITE_MASK                      MK_MASK_CONST(0x1)
//Clear PVA0_FIQ_EXITED_GRACEFULLY
#define PMC_IMPL_CLR_RAMDUMP_FIQ_EXIT_0_CLR_PVA0_FIQ_EXITED_GRACEFULLY_SHIFT                    MK_SHIFT_CONST(0)
#define PMC_IMPL_CLR_RAMDUMP_FIQ_EXIT_0_CLR_PVA0_FIQ_EXITED_GRACEFULLY_FIELD                    MK_FIELD_CONST(0x1, PMC_IMPL_CLR_RAMDUMP_FIQ_EXIT_0_CLR_PVA0_FIQ_EXITED_GRACEFULLY_SHIFT)
#define PMC_IMPL_CLR_RAMDUMP_FIQ_EXIT_0_CLR_PVA0_FIQ_EXITED_GRACEFULLY_RANGE                    0:0
#define PMC_IMPL_CLR_RAMDUMP_FIQ_EXIT_0_CLR_PVA0_FIQ_EXITED_GRACEFULLY_MSB                      MK_SHIFT_CONST(0)
#define PMC_IMPL_CLR_RAMDUMP_FIQ_EXIT_0_CLR_PVA0_FIQ_EXITED_GRACEFULLY_LSB                      MK_SHIFT_CONST(0)
#define PMC_IMPL_CLR_RAMDUMP_FIQ_EXIT_0_CLR_PVA0_FIQ_EXITED_GRACEFULLY_WOFFSET                  0x0
#define PMC_IMPL_CLR_RAMDUMP_FIQ_EXIT_0_CLR_PVA0_FIQ_EXITED_GRACEFULLY_DEFAULT                  MK_MASK_CONST(0x0)
#define PMC_IMPL_CLR_RAMDUMP_FIQ_EXIT_0_CLR_PVA0_FIQ_EXITED_GRACEFULLY_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define PMC_IMPL_CLR_RAMDUMP_FIQ_EXIT_0_CLR_PVA0_FIQ_EXITED_GRACEFULLY_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define PMC_IMPL_CLR_RAMDUMP_FIQ_EXIT_0_CLR_PVA0_FIQ_EXITED_GRACEFULLY_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define PMC_IMPL_CLR_RAMDUMP_FIQ_EXIT_0_CLR_PVA0_FIQ_EXITED_GRACEFULLY_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define PMC_IMPL_CLR_RAMDUMP_FIQ_EXIT_0_CLR_PVA0_FIQ_EXITED_GRACEFULLY_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)


// Reserved address 0x828

// Reserved address 0x82c

// Reserved address 0x830

// Reserved address 0x834

// Reserved address 0x838

// Reserved address 0x83c

// Reserved address 0x840

// Reserved address 0x844

// Reserved address 0x848

// Reserved address 0x84c

// Reserved address 0x850

// Reserved address 0x854

// Reserved address 0x858

// Reserved address 0x85c

// Reserved address 0x860
//Reset level:l1acoldrst_pmc_pclk_srstn

// Register PMC_IMPL_FMON_THRESHOLD_HIGH_OSCnFUSE_CK_0
#define PMC_IMPL_FMON_THRESHOLD_HIGH_OSCnFUSE_CK_0                      MK_ADDR_CONST(0x864)
#define PMC_IMPL_FMON_THRESHOLD_HIGH_OSCnFUSE_CK_0_SECURE                       0x0
#define PMC_IMPL_FMON_THRESHOLD_HIGH_OSCnFUSE_CK_0_DUAL                         0x0
#define PMC_IMPL_FMON_THRESHOLD_HIGH_OSCnFUSE_CK_0_SCR                  OSCnFUSE_CK_SCR_0
#define PMC_IMPL_FMON_THRESHOLD_HIGH_OSCnFUSE_CK_0_SCRREG                       PMC_IMPL_SCR_OSCnFUSE_CK_SCR_0
#define PMC_IMPL_FMON_THRESHOLD_HIGH_OSCnFUSE_CK_0_WORD_COUNT                   0x1
#define PMC_IMPL_FMON_THRESHOLD_HIGH_OSCnFUSE_CK_0_RESET_VAL                    MK_MASK_CONST(0x48f)
#define PMC_IMPL_FMON_THRESHOLD_HIGH_OSCnFUSE_CK_0_RESET_MASK                   MK_MASK_CONST(0xffffffff)
#define PMC_IMPL_FMON_THRESHOLD_HIGH_OSCnFUSE_CK_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define PMC_IMPL_FMON_THRESHOLD_HIGH_OSCnFUSE_CK_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define PMC_IMPL_FMON_THRESHOLD_HIGH_OSCnFUSE_CK_0_READ_MASK                    MK_MASK_CONST(0xffffffff)
#define PMC_IMPL_FMON_THRESHOLD_HIGH_OSCnFUSE_CK_0_WRITE_MASK                   MK_MASK_CONST(0xffffffff)
// Threshold for threshold HIGH fault. Should be programmed before monitor is enabled.
#define PMC_IMPL_FMON_THRESHOLD_HIGH_OSCnFUSE_CK_0_FMON_COUNT_THRESH_HIGH_OSCnFUSE_CK_SHIFT                     MK_SHIFT_CONST(0)
#define PMC_IMPL_FMON_THRESHOLD_HIGH_OSCnFUSE_CK_0_FMON_COUNT_THRESH_HIGH_OSCnFUSE_CK_FIELD                     MK_FIELD_CONST(0xffffffff, PMC_IMPL_FMON_THRESHOLD_HIGH_OSCnFUSE_CK_0_FMON_COUNT_THRESH_HIGH_OSCnFUSE_CK_SHIFT)
#define PMC_IMPL_FMON_THRESHOLD_HIGH_OSCnFUSE_CK_0_FMON_COUNT_THRESH_HIGH_OSCnFUSE_CK_RANGE                     31:0
#define PMC_IMPL_FMON_THRESHOLD_HIGH_OSCnFUSE_CK_0_FMON_COUNT_THRESH_HIGH_OSCnFUSE_CK_MSB                       MK_SHIFT_CONST(31)
#define PMC_IMPL_FMON_THRESHOLD_HIGH_OSCnFUSE_CK_0_FMON_COUNT_THRESH_HIGH_OSCnFUSE_CK_LSB                       MK_SHIFT_CONST(0)
#define PMC_IMPL_FMON_THRESHOLD_HIGH_OSCnFUSE_CK_0_FMON_COUNT_THRESH_HIGH_OSCnFUSE_CK_WOFFSET                   0x0
#define PMC_IMPL_FMON_THRESHOLD_HIGH_OSCnFUSE_CK_0_FMON_COUNT_THRESH_HIGH_OSCnFUSE_CK_DEFAULT                   MK_MASK_CONST(0x48f)
#define PMC_IMPL_FMON_THRESHOLD_HIGH_OSCnFUSE_CK_0_FMON_COUNT_THRESH_HIGH_OSCnFUSE_CK_DEFAULT_MASK                      MK_MASK_CONST(0xffffffff)
#define PMC_IMPL_FMON_THRESHOLD_HIGH_OSCnFUSE_CK_0_FMON_COUNT_THRESH_HIGH_OSCnFUSE_CK_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define PMC_IMPL_FMON_THRESHOLD_HIGH_OSCnFUSE_CK_0_FMON_COUNT_THRESH_HIGH_OSCnFUSE_CK_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define PMC_IMPL_FMON_THRESHOLD_HIGH_OSCnFUSE_CK_0_FMON_COUNT_THRESH_HIGH_OSCnFUSE_CK_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define PMC_IMPL_FMON_THRESHOLD_HIGH_OSCnFUSE_CK_0_FMON_COUNT_THRESH_HIGH_OSCnFUSE_CK_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

//Reset level:l1acoldrst_pmc_pclk_srstn

// Register PMC_IMPL_FMON_THRESHOLD_LOW_OSCnFUSE_CK_0
#define PMC_IMPL_FMON_THRESHOLD_LOW_OSCnFUSE_CK_0                       MK_ADDR_CONST(0x868)
#define PMC_IMPL_FMON_THRESHOLD_LOW_OSCnFUSE_CK_0_SECURE                        0x0
#define PMC_IMPL_FMON_THRESHOLD_LOW_OSCnFUSE_CK_0_DUAL                  0x0
#define PMC_IMPL_FMON_THRESHOLD_LOW_OSCnFUSE_CK_0_SCR                   OSCnFUSE_CK_SCR_0
#define PMC_IMPL_FMON_THRESHOLD_LOW_OSCnFUSE_CK_0_SCRREG                        PMC_IMPL_SCR_OSCnFUSE_CK_SCR_0
#define PMC_IMPL_FMON_THRESHOLD_LOW_OSCnFUSE_CK_0_WORD_COUNT                    0x1
#define PMC_IMPL_FMON_THRESHOLD_LOW_OSCnFUSE_CK_0_RESET_VAL                     MK_MASK_CONST(0x1f3)
#define PMC_IMPL_FMON_THRESHOLD_LOW_OSCnFUSE_CK_0_RESET_MASK                    MK_MASK_CONST(0xffffffff)
#define PMC_IMPL_FMON_THRESHOLD_LOW_OSCnFUSE_CK_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define PMC_IMPL_FMON_THRESHOLD_LOW_OSCnFUSE_CK_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define PMC_IMPL_FMON_THRESHOLD_LOW_OSCnFUSE_CK_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
#define PMC_IMPL_FMON_THRESHOLD_LOW_OSCnFUSE_CK_0_WRITE_MASK                    MK_MASK_CONST(0xffffffff)
// Threshold for threshold LOW fault. Should be programmed before monitor is enabled.
#define PMC_IMPL_FMON_THRESHOLD_LOW_OSCnFUSE_CK_0_FMON_COUNT_THRESH_LOW_OSCnFUSE_CK_SHIFT                       MK_SHIFT_CONST(0)
#define PMC_IMPL_FMON_THRESHOLD_LOW_OSCnFUSE_CK_0_FMON_COUNT_THRESH_LOW_OSCnFUSE_CK_FIELD                       MK_FIELD_CONST(0xffffffff, PMC_IMPL_FMON_THRESHOLD_LOW_OSCnFUSE_CK_0_FMON_COUNT_THRESH_LOW_OSCnFUSE_CK_SHIFT)
#define PMC_IMPL_FMON_THRESHOLD_LOW_OSCnFUSE_CK_0_FMON_COUNT_THRESH_LOW_OSCnFUSE_CK_RANGE                       31:0
#define PMC_IMPL_FMON_THRESHOLD_LOW_OSCnFUSE_CK_0_FMON_COUNT_THRESH_LOW_OSCnFUSE_CK_MSB                 MK_SHIFT_CONST(31)
#define PMC_IMPL_FMON_THRESHOLD_LOW_OSCnFUSE_CK_0_FMON_COUNT_THRESH_LOW_OSCnFUSE_CK_LSB                 MK_SHIFT_CONST(0)
#define PMC_IMPL_FMON_THRESHOLD_LOW_OSCnFUSE_CK_0_FMON_COUNT_THRESH_LOW_OSCnFUSE_CK_WOFFSET                     0x0
#define PMC_IMPL_FMON_THRESHOLD_LOW_OSCnFUSE_CK_0_FMON_COUNT_THRESH_LOW_OSCnFUSE_CK_DEFAULT                     MK_MASK_CONST(0x1f3)
#define PMC_IMPL_FMON_THRESHOLD_LOW_OSCnFUSE_CK_0_FMON_COUNT_THRESH_LOW_OSCnFUSE_CK_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
#define PMC_IMPL_FMON_THRESHOLD_LOW_OSCnFUSE_CK_0_FMON_COUNT_THRESH_LOW_OSCnFUSE_CK_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define PMC_IMPL_FMON_THRESHOLD_LOW_OSCnFUSE_CK_0_FMON_COUNT_THRESH_LOW_OSCnFUSE_CK_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define PMC_IMPL_FMON_THRESHOLD_LOW_OSCnFUSE_CK_0_FMON_COUNT_THRESH_LOW_OSCnFUSE_CK_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define PMC_IMPL_FMON_THRESHOLD_LOW_OSCnFUSE_CK_0_FMON_COUNT_THRESH_LOW_OSCnFUSE_CK_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

//Reset level:l1acoldrst_pmc_pclk_srstn

// Register PMC_IMPL_FMON_REF_WINDOW_COUNT_OSCnFUSE_CK_0
#define PMC_IMPL_FMON_REF_WINDOW_COUNT_OSCnFUSE_CK_0                    MK_ADDR_CONST(0x86c)
#define PMC_IMPL_FMON_REF_WINDOW_COUNT_OSCnFUSE_CK_0_SECURE                     0x0
#define PMC_IMPL_FMON_REF_WINDOW_COUNT_OSCnFUSE_CK_0_DUAL                       0x0
#define PMC_IMPL_FMON_REF_WINDOW_COUNT_OSCnFUSE_CK_0_SCR                        OSCnFUSE_CK_SCR_0
#define PMC_IMPL_FMON_REF_WINDOW_COUNT_OSCnFUSE_CK_0_SCRREG                     PMC_IMPL_SCR_OSCnFUSE_CK_SCR_0
#define PMC_IMPL_FMON_REF_WINDOW_COUNT_OSCnFUSE_CK_0_WORD_COUNT                         0x1
#define PMC_IMPL_FMON_REF_WINDOW_COUNT_OSCnFUSE_CK_0_RESET_VAL                  MK_MASK_CONST(0x280)
#define PMC_IMPL_FMON_REF_WINDOW_COUNT_OSCnFUSE_CK_0_RESET_MASK                         MK_MASK_CONST(0xffffff)
#define PMC_IMPL_FMON_REF_WINDOW_COUNT_OSCnFUSE_CK_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define PMC_IMPL_FMON_REF_WINDOW_COUNT_OSCnFUSE_CK_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define PMC_IMPL_FMON_REF_WINDOW_COUNT_OSCnFUSE_CK_0_READ_MASK                  MK_MASK_CONST(0xffffff)
#define PMC_IMPL_FMON_REF_WINDOW_COUNT_OSCnFUSE_CK_0_WRITE_MASK                         MK_MASK_CONST(0xffffff)
// The count determines the number of reference clock cycles that makes up single reference window.
#define PMC_IMPL_FMON_REF_WINDOW_COUNT_OSCnFUSE_CK_0_FMON_REF_WINDOW_COUNT_OSCnFUSE_CK_SHIFT                    MK_SHIFT_CONST(0)
#define PMC_IMPL_FMON_REF_WINDOW_COUNT_OSCnFUSE_CK_0_FMON_REF_WINDOW_COUNT_OSCnFUSE_CK_FIELD                    MK_FIELD_CONST(0xffffff, PMC_IMPL_FMON_REF_WINDOW_COUNT_OSCnFUSE_CK_0_FMON_REF_WINDOW_COUNT_OSCnFUSE_CK_SHIFT)
#define PMC_IMPL_FMON_REF_WINDOW_COUNT_OSCnFUSE_CK_0_FMON_REF_WINDOW_COUNT_OSCnFUSE_CK_RANGE                    23:0
#define PMC_IMPL_FMON_REF_WINDOW_COUNT_OSCnFUSE_CK_0_FMON_REF_WINDOW_COUNT_OSCnFUSE_CK_MSB                      MK_SHIFT_CONST(23)
#define PMC_IMPL_FMON_REF_WINDOW_COUNT_OSCnFUSE_CK_0_FMON_REF_WINDOW_COUNT_OSCnFUSE_CK_LSB                      MK_SHIFT_CONST(0)
#define PMC_IMPL_FMON_REF_WINDOW_COUNT_OSCnFUSE_CK_0_FMON_REF_WINDOW_COUNT_OSCnFUSE_CK_WOFFSET                  0x0
#define PMC_IMPL_FMON_REF_WINDOW_COUNT_OSCnFUSE_CK_0_FMON_REF_WINDOW_COUNT_OSCnFUSE_CK_DEFAULT                  MK_MASK_CONST(0x280)
#define PMC_IMPL_FMON_REF_WINDOW_COUNT_OSCnFUSE_CK_0_FMON_REF_WINDOW_COUNT_OSCnFUSE_CK_DEFAULT_MASK                     MK_MASK_CONST(0xffffff)
#define PMC_IMPL_FMON_REF_WINDOW_COUNT_OSCnFUSE_CK_0_FMON_REF_WINDOW_COUNT_OSCnFUSE_CK_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define PMC_IMPL_FMON_REF_WINDOW_COUNT_OSCnFUSE_CK_0_FMON_REF_WINDOW_COUNT_OSCnFUSE_CK_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define PMC_IMPL_FMON_REF_WINDOW_COUNT_OSCnFUSE_CK_0_FMON_REF_WINDOW_COUNT_OSCnFUSE_CK_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define PMC_IMPL_FMON_REF_WINDOW_COUNT_OSCnFUSE_CK_0_FMON_REF_WINDOW_COUNT_OSCnFUSE_CK_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

//Reset level:l1acoldrst_pmc_pclk_srstn

// Register PMC_IMPL_FMON_REF_WINDOW_DC_CHECK_COUNT_OSCnFUSE_CK_0
#define PMC_IMPL_FMON_REF_WINDOW_DC_CHECK_COUNT_OSCnFUSE_CK_0                   MK_ADDR_CONST(0x870)
#define PMC_IMPL_FMON_REF_WINDOW_DC_CHECK_COUNT_OSCnFUSE_CK_0_SECURE                    0x0
#define PMC_IMPL_FMON_REF_WINDOW_DC_CHECK_COUNT_OSCnFUSE_CK_0_DUAL                      0x0
#define PMC_IMPL_FMON_REF_WINDOW_DC_CHECK_COUNT_OSCnFUSE_CK_0_SCR                       OSCnFUSE_CK_SCR_0
#define PMC_IMPL_FMON_REF_WINDOW_DC_CHECK_COUNT_OSCnFUSE_CK_0_SCRREG                    PMC_IMPL_SCR_OSCnFUSE_CK_SCR_0
#define PMC_IMPL_FMON_REF_WINDOW_DC_CHECK_COUNT_OSCnFUSE_CK_0_WORD_COUNT                        0x1
#define PMC_IMPL_FMON_REF_WINDOW_DC_CHECK_COUNT_OSCnFUSE_CK_0_RESET_VAL                         MK_MASK_CONST(0xffffff)
#define PMC_IMPL_FMON_REF_WINDOW_DC_CHECK_COUNT_OSCnFUSE_CK_0_RESET_MASK                        MK_MASK_CONST(0xffffff)
#define PMC_IMPL_FMON_REF_WINDOW_DC_CHECK_COUNT_OSCnFUSE_CK_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define PMC_IMPL_FMON_REF_WINDOW_DC_CHECK_COUNT_OSCnFUSE_CK_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define PMC_IMPL_FMON_REF_WINDOW_DC_CHECK_COUNT_OSCnFUSE_CK_0_READ_MASK                         MK_MASK_CONST(0xffffff)
#define PMC_IMPL_FMON_REF_WINDOW_DC_CHECK_COUNT_OSCnFUSE_CK_0_WRITE_MASK                        MK_MASK_CONST(0xffffff)
// The count determined the reference clock cycle edge on which DC check is performed. If the count if > ref_window_count, then the DC check is never enabled.
#define PMC_IMPL_FMON_REF_WINDOW_DC_CHECK_COUNT_OSCnFUSE_CK_0_FMON_REF_WINDOW_DC_CHECK_COUNT_OSCnFUSE_CK_SHIFT                  MK_SHIFT_CONST(0)
#define PMC_IMPL_FMON_REF_WINDOW_DC_CHECK_COUNT_OSCnFUSE_CK_0_FMON_REF_WINDOW_DC_CHECK_COUNT_OSCnFUSE_CK_FIELD                  MK_FIELD_CONST(0xffffff, PMC_IMPL_FMON_REF_WINDOW_DC_CHECK_COUNT_OSCnFUSE_CK_0_FMON_REF_WINDOW_DC_CHECK_COUNT_OSCnFUSE_CK_SHIFT)
#define PMC_IMPL_FMON_REF_WINDOW_DC_CHECK_COUNT_OSCnFUSE_CK_0_FMON_REF_WINDOW_DC_CHECK_COUNT_OSCnFUSE_CK_RANGE                  23:0
#define PMC_IMPL_FMON_REF_WINDOW_DC_CHECK_COUNT_OSCnFUSE_CK_0_FMON_REF_WINDOW_DC_CHECK_COUNT_OSCnFUSE_CK_MSB                    MK_SHIFT_CONST(23)
#define PMC_IMPL_FMON_REF_WINDOW_DC_CHECK_COUNT_OSCnFUSE_CK_0_FMON_REF_WINDOW_DC_CHECK_COUNT_OSCnFUSE_CK_LSB                    MK_SHIFT_CONST(0)
#define PMC_IMPL_FMON_REF_WINDOW_DC_CHECK_COUNT_OSCnFUSE_CK_0_FMON_REF_WINDOW_DC_CHECK_COUNT_OSCnFUSE_CK_WOFFSET                        0x0
#define PMC_IMPL_FMON_REF_WINDOW_DC_CHECK_COUNT_OSCnFUSE_CK_0_FMON_REF_WINDOW_DC_CHECK_COUNT_OSCnFUSE_CK_DEFAULT                        MK_MASK_CONST(0xffffff)
#define PMC_IMPL_FMON_REF_WINDOW_DC_CHECK_COUNT_OSCnFUSE_CK_0_FMON_REF_WINDOW_DC_CHECK_COUNT_OSCnFUSE_CK_DEFAULT_MASK                   MK_MASK_CONST(0xffffff)
#define PMC_IMPL_FMON_REF_WINDOW_DC_CHECK_COUNT_OSCnFUSE_CK_0_FMON_REF_WINDOW_DC_CHECK_COUNT_OSCnFUSE_CK_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define PMC_IMPL_FMON_REF_WINDOW_DC_CHECK_COUNT_OSCnFUSE_CK_0_FMON_REF_WINDOW_DC_CHECK_COUNT_OSCnFUSE_CK_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define PMC_IMPL_FMON_REF_WINDOW_DC_CHECK_COUNT_OSCnFUSE_CK_0_FMON_REF_WINDOW_DC_CHECK_COUNT_OSCnFUSE_CK_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define PMC_IMPL_FMON_REF_WINDOW_DC_CHECK_COUNT_OSCnFUSE_CK_0_FMON_REF_WINDOW_DC_CHECK_COUNT_OSCnFUSE_CK_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

//Reset level:l2coldrst_pmc_pclk_srstn

// Register PMC_IMPL_FMON_FAULT_ACTION_OSCnFUSE_CK_0
#define PMC_IMPL_FMON_FAULT_ACTION_OSCnFUSE_CK_0                        MK_ADDR_CONST(0x874)
#define PMC_IMPL_FMON_FAULT_ACTION_OSCnFUSE_CK_0_SECURE                         0x0
#define PMC_IMPL_FMON_FAULT_ACTION_OSCnFUSE_CK_0_DUAL                   0x0
#define PMC_IMPL_FMON_FAULT_ACTION_OSCnFUSE_CK_0_SCR                    OSCnFUSE_CK_SCR_0
#define PMC_IMPL_FMON_FAULT_ACTION_OSCnFUSE_CK_0_SCRREG                         PMC_IMPL_SCR_OSCnFUSE_CK_SCR_0
#define PMC_IMPL_FMON_FAULT_ACTION_OSCnFUSE_CK_0_WORD_COUNT                     0x1
#define PMC_IMPL_FMON_FAULT_ACTION_OSCnFUSE_CK_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define PMC_IMPL_FMON_FAULT_ACTION_OSCnFUSE_CK_0_RESET_MASK                     MK_MASK_CONST(0x7)
#define PMC_IMPL_FMON_FAULT_ACTION_OSCnFUSE_CK_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define PMC_IMPL_FMON_FAULT_ACTION_OSCnFUSE_CK_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define PMC_IMPL_FMON_FAULT_ACTION_OSCnFUSE_CK_0_READ_MASK                      MK_MASK_CONST(0x7)
#define PMC_IMPL_FMON_FAULT_ACTION_OSCnFUSE_CK_0_WRITE_MASK                     MK_MASK_CONST(0x7)
// if set, DC fault will trigger reset request on fmon_dc_reset_req
#define PMC_IMPL_FMON_FAULT_ACTION_OSCnFUSE_CK_0_FMON_ACTION_DC_RESET_REQ_OSCnFUSE_CK_SHIFT                     MK_SHIFT_CONST(2)
#define PMC_IMPL_FMON_FAULT_ACTION_OSCnFUSE_CK_0_FMON_ACTION_DC_RESET_REQ_OSCnFUSE_CK_FIELD                     MK_FIELD_CONST(0x1, PMC_IMPL_FMON_FAULT_ACTION_OSCnFUSE_CK_0_FMON_ACTION_DC_RESET_REQ_OSCnFUSE_CK_SHIFT)
#define PMC_IMPL_FMON_FAULT_ACTION_OSCnFUSE_CK_0_FMON_ACTION_DC_RESET_REQ_OSCnFUSE_CK_RANGE                     2:2
#define PMC_IMPL_FMON_FAULT_ACTION_OSCnFUSE_CK_0_FMON_ACTION_DC_RESET_REQ_OSCnFUSE_CK_MSB                       MK_SHIFT_CONST(2)
#define PMC_IMPL_FMON_FAULT_ACTION_OSCnFUSE_CK_0_FMON_ACTION_DC_RESET_REQ_OSCnFUSE_CK_LSB                       MK_SHIFT_CONST(2)
#define PMC_IMPL_FMON_FAULT_ACTION_OSCnFUSE_CK_0_FMON_ACTION_DC_RESET_REQ_OSCnFUSE_CK_WOFFSET                   0x0
#define PMC_IMPL_FMON_FAULT_ACTION_OSCnFUSE_CK_0_FMON_ACTION_DC_RESET_REQ_OSCnFUSE_CK_DEFAULT                   MK_MASK_CONST(0x0)
#define PMC_IMPL_FMON_FAULT_ACTION_OSCnFUSE_CK_0_FMON_ACTION_DC_RESET_REQ_OSCnFUSE_CK_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define PMC_IMPL_FMON_FAULT_ACTION_OSCnFUSE_CK_0_FMON_ACTION_DC_RESET_REQ_OSCnFUSE_CK_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define PMC_IMPL_FMON_FAULT_ACTION_OSCnFUSE_CK_0_FMON_ACTION_DC_RESET_REQ_OSCnFUSE_CK_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define PMC_IMPL_FMON_FAULT_ACTION_OSCnFUSE_CK_0_FMON_ACTION_DC_RESET_REQ_OSCnFUSE_CK_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define PMC_IMPL_FMON_FAULT_ACTION_OSCnFUSE_CK_0_FMON_ACTION_DC_RESET_REQ_OSCnFUSE_CK_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define PMC_IMPL_FMON_FAULT_ACTION_OSCnFUSE_CK_0_FMON_ACTION_DC_RESET_REQ_OSCnFUSE_CK_INIT_ENUM                 DISABLE
#define PMC_IMPL_FMON_FAULT_ACTION_OSCnFUSE_CK_0_FMON_ACTION_DC_RESET_REQ_OSCnFUSE_CK_DISABLE                   MK_ENUM_CONST(0)
#define PMC_IMPL_FMON_FAULT_ACTION_OSCnFUSE_CK_0_FMON_ACTION_DC_RESET_REQ_OSCnFUSE_CK_ENABLE                    MK_ENUM_CONST(1)

// if set, triggering of any fault (which are enabled) will result in pusling of fault_out_pulse pin
#define PMC_IMPL_FMON_FAULT_ACTION_OSCnFUSE_CK_0_FMON_ACTION_FAULT_REPORT_OSCnFUSE_CK_SHIFT                     MK_SHIFT_CONST(1)
#define PMC_IMPL_FMON_FAULT_ACTION_OSCnFUSE_CK_0_FMON_ACTION_FAULT_REPORT_OSCnFUSE_CK_FIELD                     MK_FIELD_CONST(0x1, PMC_IMPL_FMON_FAULT_ACTION_OSCnFUSE_CK_0_FMON_ACTION_FAULT_REPORT_OSCnFUSE_CK_SHIFT)
#define PMC_IMPL_FMON_FAULT_ACTION_OSCnFUSE_CK_0_FMON_ACTION_FAULT_REPORT_OSCnFUSE_CK_RANGE                     1:1
#define PMC_IMPL_FMON_FAULT_ACTION_OSCnFUSE_CK_0_FMON_ACTION_FAULT_REPORT_OSCnFUSE_CK_MSB                       MK_SHIFT_CONST(1)
#define PMC_IMPL_FMON_FAULT_ACTION_OSCnFUSE_CK_0_FMON_ACTION_FAULT_REPORT_OSCnFUSE_CK_LSB                       MK_SHIFT_CONST(1)
#define PMC_IMPL_FMON_FAULT_ACTION_OSCnFUSE_CK_0_FMON_ACTION_FAULT_REPORT_OSCnFUSE_CK_WOFFSET                   0x0
#define PMC_IMPL_FMON_FAULT_ACTION_OSCnFUSE_CK_0_FMON_ACTION_FAULT_REPORT_OSCnFUSE_CK_DEFAULT                   MK_MASK_CONST(0x0)
#define PMC_IMPL_FMON_FAULT_ACTION_OSCnFUSE_CK_0_FMON_ACTION_FAULT_REPORT_OSCnFUSE_CK_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define PMC_IMPL_FMON_FAULT_ACTION_OSCnFUSE_CK_0_FMON_ACTION_FAULT_REPORT_OSCnFUSE_CK_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define PMC_IMPL_FMON_FAULT_ACTION_OSCnFUSE_CK_0_FMON_ACTION_FAULT_REPORT_OSCnFUSE_CK_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define PMC_IMPL_FMON_FAULT_ACTION_OSCnFUSE_CK_0_FMON_ACTION_FAULT_REPORT_OSCnFUSE_CK_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define PMC_IMPL_FMON_FAULT_ACTION_OSCnFUSE_CK_0_FMON_ACTION_FAULT_REPORT_OSCnFUSE_CK_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define PMC_IMPL_FMON_FAULT_ACTION_OSCnFUSE_CK_0_FMON_ACTION_FAULT_REPORT_OSCnFUSE_CK_INIT_ENUM                 DISABLE
#define PMC_IMPL_FMON_FAULT_ACTION_OSCnFUSE_CK_0_FMON_ACTION_FAULT_REPORT_OSCnFUSE_CK_DISABLE                   MK_ENUM_CONST(0)
#define PMC_IMPL_FMON_FAULT_ACTION_OSCnFUSE_CK_0_FMON_ACTION_FAULT_REPORT_OSCnFUSE_CK_ENABLE                    MK_ENUM_CONST(1)

// if set, triggering of any fault (which are enabled) will result in reset request
#define PMC_IMPL_FMON_FAULT_ACTION_OSCnFUSE_CK_0_FMON_ACTION_RESET_REQ_OSCnFUSE_CK_SHIFT                        MK_SHIFT_CONST(0)
#define PMC_IMPL_FMON_FAULT_ACTION_OSCnFUSE_CK_0_FMON_ACTION_RESET_REQ_OSCnFUSE_CK_FIELD                        MK_FIELD_CONST(0x1, PMC_IMPL_FMON_FAULT_ACTION_OSCnFUSE_CK_0_FMON_ACTION_RESET_REQ_OSCnFUSE_CK_SHIFT)
#define PMC_IMPL_FMON_FAULT_ACTION_OSCnFUSE_CK_0_FMON_ACTION_RESET_REQ_OSCnFUSE_CK_RANGE                        0:0
#define PMC_IMPL_FMON_FAULT_ACTION_OSCnFUSE_CK_0_FMON_ACTION_RESET_REQ_OSCnFUSE_CK_MSB                  MK_SHIFT_CONST(0)
#define PMC_IMPL_FMON_FAULT_ACTION_OSCnFUSE_CK_0_FMON_ACTION_RESET_REQ_OSCnFUSE_CK_LSB                  MK_SHIFT_CONST(0)
#define PMC_IMPL_FMON_FAULT_ACTION_OSCnFUSE_CK_0_FMON_ACTION_RESET_REQ_OSCnFUSE_CK_WOFFSET                      0x0
#define PMC_IMPL_FMON_FAULT_ACTION_OSCnFUSE_CK_0_FMON_ACTION_RESET_REQ_OSCnFUSE_CK_DEFAULT                      MK_MASK_CONST(0x0)
#define PMC_IMPL_FMON_FAULT_ACTION_OSCnFUSE_CK_0_FMON_ACTION_RESET_REQ_OSCnFUSE_CK_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define PMC_IMPL_FMON_FAULT_ACTION_OSCnFUSE_CK_0_FMON_ACTION_RESET_REQ_OSCnFUSE_CK_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define PMC_IMPL_FMON_FAULT_ACTION_OSCnFUSE_CK_0_FMON_ACTION_RESET_REQ_OSCnFUSE_CK_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define PMC_IMPL_FMON_FAULT_ACTION_OSCnFUSE_CK_0_FMON_ACTION_RESET_REQ_OSCnFUSE_CK_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define PMC_IMPL_FMON_FAULT_ACTION_OSCnFUSE_CK_0_FMON_ACTION_RESET_REQ_OSCnFUSE_CK_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define PMC_IMPL_FMON_FAULT_ACTION_OSCnFUSE_CK_0_FMON_ACTION_RESET_REQ_OSCnFUSE_CK_INIT_ENUM                    DISABLE
#define PMC_IMPL_FMON_FAULT_ACTION_OSCnFUSE_CK_0_FMON_ACTION_RESET_REQ_OSCnFUSE_CK_DISABLE                      MK_ENUM_CONST(0)
#define PMC_IMPL_FMON_FAULT_ACTION_OSCnFUSE_CK_0_FMON_ACTION_RESET_REQ_OSCnFUSE_CK_ENABLE                       MK_ENUM_CONST(1)

//Reset level:l1acoldrst_pmc_pclk_srstn except for FMON_ENABLE_OSCnFUSE_CK
// FMON_ENABLE_OSCnFUSE_CK is on l2coldrst_pmc_pclk_srstn

// Register PMC_IMPL_FMON_CONFIG_OSCnFUSE_CK_0
#define PMC_IMPL_FMON_CONFIG_OSCnFUSE_CK_0                      MK_ADDR_CONST(0x878)
#define PMC_IMPL_FMON_CONFIG_OSCnFUSE_CK_0_SECURE                       0x0
#define PMC_IMPL_FMON_CONFIG_OSCnFUSE_CK_0_DUAL                         0x0
#define PMC_IMPL_FMON_CONFIG_OSCnFUSE_CK_0_SCR                  OSCnFUSE_CK_SCR_0
#define PMC_IMPL_FMON_CONFIG_OSCnFUSE_CK_0_SCRREG                       PMC_IMPL_SCR_OSCnFUSE_CK_SCR_0
#define PMC_IMPL_FMON_CONFIG_OSCnFUSE_CK_0_WORD_COUNT                   0x1
#define PMC_IMPL_FMON_CONFIG_OSCnFUSE_CK_0_RESET_VAL                    MK_MASK_CONST(0x7f)
#define PMC_IMPL_FMON_CONFIG_OSCnFUSE_CK_0_RESET_MASK                   MK_MASK_CONST(0x7f)
#define PMC_IMPL_FMON_CONFIG_OSCnFUSE_CK_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define PMC_IMPL_FMON_CONFIG_OSCnFUSE_CK_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define PMC_IMPL_FMON_CONFIG_OSCnFUSE_CK_0_READ_MASK                    MK_MASK_CONST(0x7f)
#define PMC_IMPL_FMON_CONFIG_OSCnFUSE_CK_0_WRITE_MASK                   MK_MASK_CONST(0x7f)
// If set, DC fault violation will be reported on fault_out_pulse
#define PMC_IMPL_FMON_CONFIG_OSCnFUSE_CK_0_FMON_REPORT_DC_FAULT_VIOL_OSCnFUSE_CK_SHIFT                  MK_SHIFT_CONST(6)
#define PMC_IMPL_FMON_CONFIG_OSCnFUSE_CK_0_FMON_REPORT_DC_FAULT_VIOL_OSCnFUSE_CK_FIELD                  MK_FIELD_CONST(0x1, PMC_IMPL_FMON_CONFIG_OSCnFUSE_CK_0_FMON_REPORT_DC_FAULT_VIOL_OSCnFUSE_CK_SHIFT)
#define PMC_IMPL_FMON_CONFIG_OSCnFUSE_CK_0_FMON_REPORT_DC_FAULT_VIOL_OSCnFUSE_CK_RANGE                  6:6
#define PMC_IMPL_FMON_CONFIG_OSCnFUSE_CK_0_FMON_REPORT_DC_FAULT_VIOL_OSCnFUSE_CK_MSB                    MK_SHIFT_CONST(6)
#define PMC_IMPL_FMON_CONFIG_OSCnFUSE_CK_0_FMON_REPORT_DC_FAULT_VIOL_OSCnFUSE_CK_LSB                    MK_SHIFT_CONST(6)
#define PMC_IMPL_FMON_CONFIG_OSCnFUSE_CK_0_FMON_REPORT_DC_FAULT_VIOL_OSCnFUSE_CK_WOFFSET                        0x0
#define PMC_IMPL_FMON_CONFIG_OSCnFUSE_CK_0_FMON_REPORT_DC_FAULT_VIOL_OSCnFUSE_CK_DEFAULT                        MK_MASK_CONST(0x1)
#define PMC_IMPL_FMON_CONFIG_OSCnFUSE_CK_0_FMON_REPORT_DC_FAULT_VIOL_OSCnFUSE_CK_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define PMC_IMPL_FMON_CONFIG_OSCnFUSE_CK_0_FMON_REPORT_DC_FAULT_VIOL_OSCnFUSE_CK_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define PMC_IMPL_FMON_CONFIG_OSCnFUSE_CK_0_FMON_REPORT_DC_FAULT_VIOL_OSCnFUSE_CK_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define PMC_IMPL_FMON_CONFIG_OSCnFUSE_CK_0_FMON_REPORT_DC_FAULT_VIOL_OSCnFUSE_CK_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define PMC_IMPL_FMON_CONFIG_OSCnFUSE_CK_0_FMON_REPORT_DC_FAULT_VIOL_OSCnFUSE_CK_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define PMC_IMPL_FMON_CONFIG_OSCnFUSE_CK_0_FMON_REPORT_DC_FAULT_VIOL_OSCnFUSE_CK_INIT_ENUM                      ENABLE
#define PMC_IMPL_FMON_CONFIG_OSCnFUSE_CK_0_FMON_REPORT_DC_FAULT_VIOL_OSCnFUSE_CK_DISABLE                        MK_ENUM_CONST(0)
#define PMC_IMPL_FMON_CONFIG_OSCnFUSE_CK_0_FMON_REPORT_DC_FAULT_VIOL_OSCnFUSE_CK_ENABLE                 MK_ENUM_CONST(1)

// If set, HIGH threshould violation will be reported on fault_out_pulse
#define PMC_IMPL_FMON_CONFIG_OSCnFUSE_CK_0_FMON_REPORT_HIGH_THRESH_VIOL_OSCnFUSE_CK_SHIFT                       MK_SHIFT_CONST(5)
#define PMC_IMPL_FMON_CONFIG_OSCnFUSE_CK_0_FMON_REPORT_HIGH_THRESH_VIOL_OSCnFUSE_CK_FIELD                       MK_FIELD_CONST(0x1, PMC_IMPL_FMON_CONFIG_OSCnFUSE_CK_0_FMON_REPORT_HIGH_THRESH_VIOL_OSCnFUSE_CK_SHIFT)
#define PMC_IMPL_FMON_CONFIG_OSCnFUSE_CK_0_FMON_REPORT_HIGH_THRESH_VIOL_OSCnFUSE_CK_RANGE                       5:5
#define PMC_IMPL_FMON_CONFIG_OSCnFUSE_CK_0_FMON_REPORT_HIGH_THRESH_VIOL_OSCnFUSE_CK_MSB                 MK_SHIFT_CONST(5)
#define PMC_IMPL_FMON_CONFIG_OSCnFUSE_CK_0_FMON_REPORT_HIGH_THRESH_VIOL_OSCnFUSE_CK_LSB                 MK_SHIFT_CONST(5)
#define PMC_IMPL_FMON_CONFIG_OSCnFUSE_CK_0_FMON_REPORT_HIGH_THRESH_VIOL_OSCnFUSE_CK_WOFFSET                     0x0
#define PMC_IMPL_FMON_CONFIG_OSCnFUSE_CK_0_FMON_REPORT_HIGH_THRESH_VIOL_OSCnFUSE_CK_DEFAULT                     MK_MASK_CONST(0x1)
#define PMC_IMPL_FMON_CONFIG_OSCnFUSE_CK_0_FMON_REPORT_HIGH_THRESH_VIOL_OSCnFUSE_CK_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define PMC_IMPL_FMON_CONFIG_OSCnFUSE_CK_0_FMON_REPORT_HIGH_THRESH_VIOL_OSCnFUSE_CK_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define PMC_IMPL_FMON_CONFIG_OSCnFUSE_CK_0_FMON_REPORT_HIGH_THRESH_VIOL_OSCnFUSE_CK_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define PMC_IMPL_FMON_CONFIG_OSCnFUSE_CK_0_FMON_REPORT_HIGH_THRESH_VIOL_OSCnFUSE_CK_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define PMC_IMPL_FMON_CONFIG_OSCnFUSE_CK_0_FMON_REPORT_HIGH_THRESH_VIOL_OSCnFUSE_CK_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define PMC_IMPL_FMON_CONFIG_OSCnFUSE_CK_0_FMON_REPORT_HIGH_THRESH_VIOL_OSCnFUSE_CK_INIT_ENUM                   ENABLE
#define PMC_IMPL_FMON_CONFIG_OSCnFUSE_CK_0_FMON_REPORT_HIGH_THRESH_VIOL_OSCnFUSE_CK_DISABLE                     MK_ENUM_CONST(0)
#define PMC_IMPL_FMON_CONFIG_OSCnFUSE_CK_0_FMON_REPORT_HIGH_THRESH_VIOL_OSCnFUSE_CK_ENABLE                      MK_ENUM_CONST(1)

// If set, LOW threshold violation will be reported on fault_out_pulse
#define PMC_IMPL_FMON_CONFIG_OSCnFUSE_CK_0_FMON_REPORT_LOW_THRESH_VIOL_OSCnFUSE_CK_SHIFT                        MK_SHIFT_CONST(4)
#define PMC_IMPL_FMON_CONFIG_OSCnFUSE_CK_0_FMON_REPORT_LOW_THRESH_VIOL_OSCnFUSE_CK_FIELD                        MK_FIELD_CONST(0x1, PMC_IMPL_FMON_CONFIG_OSCnFUSE_CK_0_FMON_REPORT_LOW_THRESH_VIOL_OSCnFUSE_CK_SHIFT)
#define PMC_IMPL_FMON_CONFIG_OSCnFUSE_CK_0_FMON_REPORT_LOW_THRESH_VIOL_OSCnFUSE_CK_RANGE                        4:4
#define PMC_IMPL_FMON_CONFIG_OSCnFUSE_CK_0_FMON_REPORT_LOW_THRESH_VIOL_OSCnFUSE_CK_MSB                  MK_SHIFT_CONST(4)
#define PMC_IMPL_FMON_CONFIG_OSCnFUSE_CK_0_FMON_REPORT_LOW_THRESH_VIOL_OSCnFUSE_CK_LSB                  MK_SHIFT_CONST(4)
#define PMC_IMPL_FMON_CONFIG_OSCnFUSE_CK_0_FMON_REPORT_LOW_THRESH_VIOL_OSCnFUSE_CK_WOFFSET                      0x0
#define PMC_IMPL_FMON_CONFIG_OSCnFUSE_CK_0_FMON_REPORT_LOW_THRESH_VIOL_OSCnFUSE_CK_DEFAULT                      MK_MASK_CONST(0x1)
#define PMC_IMPL_FMON_CONFIG_OSCnFUSE_CK_0_FMON_REPORT_LOW_THRESH_VIOL_OSCnFUSE_CK_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define PMC_IMPL_FMON_CONFIG_OSCnFUSE_CK_0_FMON_REPORT_LOW_THRESH_VIOL_OSCnFUSE_CK_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define PMC_IMPL_FMON_CONFIG_OSCnFUSE_CK_0_FMON_REPORT_LOW_THRESH_VIOL_OSCnFUSE_CK_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define PMC_IMPL_FMON_CONFIG_OSCnFUSE_CK_0_FMON_REPORT_LOW_THRESH_VIOL_OSCnFUSE_CK_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define PMC_IMPL_FMON_CONFIG_OSCnFUSE_CK_0_FMON_REPORT_LOW_THRESH_VIOL_OSCnFUSE_CK_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define PMC_IMPL_FMON_CONFIG_OSCnFUSE_CK_0_FMON_REPORT_LOW_THRESH_VIOL_OSCnFUSE_CK_INIT_ENUM                    ENABLE
#define PMC_IMPL_FMON_CONFIG_OSCnFUSE_CK_0_FMON_REPORT_LOW_THRESH_VIOL_OSCnFUSE_CK_DISABLE                      MK_ENUM_CONST(0)
#define PMC_IMPL_FMON_CONFIG_OSCnFUSE_CK_0_FMON_REPORT_LOW_THRESH_VIOL_OSCnFUSE_CK_ENABLE                       MK_ENUM_CONST(1)

// If set, Overflow error will be reported on fault_out_pulse
#define PMC_IMPL_FMON_CONFIG_OSCnFUSE_CK_0_FMON_REPORT_OVERFLOW_ERROR_OSCnFUSE_CK_SHIFT                 MK_SHIFT_CONST(3)
#define PMC_IMPL_FMON_CONFIG_OSCnFUSE_CK_0_FMON_REPORT_OVERFLOW_ERROR_OSCnFUSE_CK_FIELD                 MK_FIELD_CONST(0x1, PMC_IMPL_FMON_CONFIG_OSCnFUSE_CK_0_FMON_REPORT_OVERFLOW_ERROR_OSCnFUSE_CK_SHIFT)
#define PMC_IMPL_FMON_CONFIG_OSCnFUSE_CK_0_FMON_REPORT_OVERFLOW_ERROR_OSCnFUSE_CK_RANGE                 3:3
#define PMC_IMPL_FMON_CONFIG_OSCnFUSE_CK_0_FMON_REPORT_OVERFLOW_ERROR_OSCnFUSE_CK_MSB                   MK_SHIFT_CONST(3)
#define PMC_IMPL_FMON_CONFIG_OSCnFUSE_CK_0_FMON_REPORT_OVERFLOW_ERROR_OSCnFUSE_CK_LSB                   MK_SHIFT_CONST(3)
#define PMC_IMPL_FMON_CONFIG_OSCnFUSE_CK_0_FMON_REPORT_OVERFLOW_ERROR_OSCnFUSE_CK_WOFFSET                       0x0
#define PMC_IMPL_FMON_CONFIG_OSCnFUSE_CK_0_FMON_REPORT_OVERFLOW_ERROR_OSCnFUSE_CK_DEFAULT                       MK_MASK_CONST(0x1)
#define PMC_IMPL_FMON_CONFIG_OSCnFUSE_CK_0_FMON_REPORT_OVERFLOW_ERROR_OSCnFUSE_CK_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define PMC_IMPL_FMON_CONFIG_OSCnFUSE_CK_0_FMON_REPORT_OVERFLOW_ERROR_OSCnFUSE_CK_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define PMC_IMPL_FMON_CONFIG_OSCnFUSE_CK_0_FMON_REPORT_OVERFLOW_ERROR_OSCnFUSE_CK_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define PMC_IMPL_FMON_CONFIG_OSCnFUSE_CK_0_FMON_REPORT_OVERFLOW_ERROR_OSCnFUSE_CK_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define PMC_IMPL_FMON_CONFIG_OSCnFUSE_CK_0_FMON_REPORT_OVERFLOW_ERROR_OSCnFUSE_CK_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define PMC_IMPL_FMON_CONFIG_OSCnFUSE_CK_0_FMON_REPORT_OVERFLOW_ERROR_OSCnFUSE_CK_INIT_ENUM                     ENABLE
#define PMC_IMPL_FMON_CONFIG_OSCnFUSE_CK_0_FMON_REPORT_OVERFLOW_ERROR_OSCnFUSE_CK_DISABLE                       MK_ENUM_CONST(0)
#define PMC_IMPL_FMON_CONFIG_OSCnFUSE_CK_0_FMON_REPORT_OVERFLOW_ERROR_OSCnFUSE_CK_ENABLE                        MK_ENUM_CONST(1)

// Reference clock window enable
#define PMC_IMPL_FMON_CONFIG_OSCnFUSE_CK_0_FMON_REF_CLK_WINDOW_EN_OSCnFUSE_CK_SHIFT                     MK_SHIFT_CONST(2)
#define PMC_IMPL_FMON_CONFIG_OSCnFUSE_CK_0_FMON_REF_CLK_WINDOW_EN_OSCnFUSE_CK_FIELD                     MK_FIELD_CONST(0x1, PMC_IMPL_FMON_CONFIG_OSCnFUSE_CK_0_FMON_REF_CLK_WINDOW_EN_OSCnFUSE_CK_SHIFT)
#define PMC_IMPL_FMON_CONFIG_OSCnFUSE_CK_0_FMON_REF_CLK_WINDOW_EN_OSCnFUSE_CK_RANGE                     2:2
#define PMC_IMPL_FMON_CONFIG_OSCnFUSE_CK_0_FMON_REF_CLK_WINDOW_EN_OSCnFUSE_CK_MSB                       MK_SHIFT_CONST(2)
#define PMC_IMPL_FMON_CONFIG_OSCnFUSE_CK_0_FMON_REF_CLK_WINDOW_EN_OSCnFUSE_CK_LSB                       MK_SHIFT_CONST(2)
#define PMC_IMPL_FMON_CONFIG_OSCnFUSE_CK_0_FMON_REF_CLK_WINDOW_EN_OSCnFUSE_CK_WOFFSET                   0x0
#define PMC_IMPL_FMON_CONFIG_OSCnFUSE_CK_0_FMON_REF_CLK_WINDOW_EN_OSCnFUSE_CK_DEFAULT                   MK_MASK_CONST(0x1)
#define PMC_IMPL_FMON_CONFIG_OSCnFUSE_CK_0_FMON_REF_CLK_WINDOW_EN_OSCnFUSE_CK_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define PMC_IMPL_FMON_CONFIG_OSCnFUSE_CK_0_FMON_REF_CLK_WINDOW_EN_OSCnFUSE_CK_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define PMC_IMPL_FMON_CONFIG_OSCnFUSE_CK_0_FMON_REF_CLK_WINDOW_EN_OSCnFUSE_CK_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define PMC_IMPL_FMON_CONFIG_OSCnFUSE_CK_0_FMON_REF_CLK_WINDOW_EN_OSCnFUSE_CK_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define PMC_IMPL_FMON_CONFIG_OSCnFUSE_CK_0_FMON_REF_CLK_WINDOW_EN_OSCnFUSE_CK_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define PMC_IMPL_FMON_CONFIG_OSCnFUSE_CK_0_FMON_REF_CLK_WINDOW_EN_OSCnFUSE_CK_INIT_ENUM                 ENABLE
#define PMC_IMPL_FMON_CONFIG_OSCnFUSE_CK_0_FMON_REF_CLK_WINDOW_EN_OSCnFUSE_CK_DISABLE                   MK_ENUM_CONST(0)
#define PMC_IMPL_FMON_CONFIG_OSCnFUSE_CK_0_FMON_REF_CLK_WINDOW_EN_OSCnFUSE_CK_ENABLE                    MK_ENUM_CONST(1)

// FMON counter enable
#define PMC_IMPL_FMON_CONFIG_OSCnFUSE_CK_0_FMON_ENABLE_FMON_COUNTER_OSCnFUSE_CK_SHIFT                   MK_SHIFT_CONST(1)
#define PMC_IMPL_FMON_CONFIG_OSCnFUSE_CK_0_FMON_ENABLE_FMON_COUNTER_OSCnFUSE_CK_FIELD                   MK_FIELD_CONST(0x1, PMC_IMPL_FMON_CONFIG_OSCnFUSE_CK_0_FMON_ENABLE_FMON_COUNTER_OSCnFUSE_CK_SHIFT)
#define PMC_IMPL_FMON_CONFIG_OSCnFUSE_CK_0_FMON_ENABLE_FMON_COUNTER_OSCnFUSE_CK_RANGE                   1:1
#define PMC_IMPL_FMON_CONFIG_OSCnFUSE_CK_0_FMON_ENABLE_FMON_COUNTER_OSCnFUSE_CK_MSB                     MK_SHIFT_CONST(1)
#define PMC_IMPL_FMON_CONFIG_OSCnFUSE_CK_0_FMON_ENABLE_FMON_COUNTER_OSCnFUSE_CK_LSB                     MK_SHIFT_CONST(1)
#define PMC_IMPL_FMON_CONFIG_OSCnFUSE_CK_0_FMON_ENABLE_FMON_COUNTER_OSCnFUSE_CK_WOFFSET                 0x0
#define PMC_IMPL_FMON_CONFIG_OSCnFUSE_CK_0_FMON_ENABLE_FMON_COUNTER_OSCnFUSE_CK_DEFAULT                 MK_MASK_CONST(0x1)
#define PMC_IMPL_FMON_CONFIG_OSCnFUSE_CK_0_FMON_ENABLE_FMON_COUNTER_OSCnFUSE_CK_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define PMC_IMPL_FMON_CONFIG_OSCnFUSE_CK_0_FMON_ENABLE_FMON_COUNTER_OSCnFUSE_CK_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define PMC_IMPL_FMON_CONFIG_OSCnFUSE_CK_0_FMON_ENABLE_FMON_COUNTER_OSCnFUSE_CK_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define PMC_IMPL_FMON_CONFIG_OSCnFUSE_CK_0_FMON_ENABLE_FMON_COUNTER_OSCnFUSE_CK_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define PMC_IMPL_FMON_CONFIG_OSCnFUSE_CK_0_FMON_ENABLE_FMON_COUNTER_OSCnFUSE_CK_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define PMC_IMPL_FMON_CONFIG_OSCnFUSE_CK_0_FMON_ENABLE_FMON_COUNTER_OSCnFUSE_CK_INIT_ENUM                       ENABLE
#define PMC_IMPL_FMON_CONFIG_OSCnFUSE_CK_0_FMON_ENABLE_FMON_COUNTER_OSCnFUSE_CK_DISABLE                 MK_ENUM_CONST(0)
#define PMC_IMPL_FMON_CONFIG_OSCnFUSE_CK_0_FMON_ENABLE_FMON_COUNTER_OSCnFUSE_CK_ENABLE                  MK_ENUM_CONST(1)

// FMON master enable, this should be disabled (made 0) for each and every configuration change
#define PMC_IMPL_FMON_CONFIG_OSCnFUSE_CK_0_FMON_ENABLE_OSCnFUSE_CK_SHIFT                        MK_SHIFT_CONST(0)
#define PMC_IMPL_FMON_CONFIG_OSCnFUSE_CK_0_FMON_ENABLE_OSCnFUSE_CK_FIELD                        MK_FIELD_CONST(0x1, PMC_IMPL_FMON_CONFIG_OSCnFUSE_CK_0_FMON_ENABLE_OSCnFUSE_CK_SHIFT)
#define PMC_IMPL_FMON_CONFIG_OSCnFUSE_CK_0_FMON_ENABLE_OSCnFUSE_CK_RANGE                        0:0
#define PMC_IMPL_FMON_CONFIG_OSCnFUSE_CK_0_FMON_ENABLE_OSCnFUSE_CK_MSB                  MK_SHIFT_CONST(0)
#define PMC_IMPL_FMON_CONFIG_OSCnFUSE_CK_0_FMON_ENABLE_OSCnFUSE_CK_LSB                  MK_SHIFT_CONST(0)
#define PMC_IMPL_FMON_CONFIG_OSCnFUSE_CK_0_FMON_ENABLE_OSCnFUSE_CK_WOFFSET                      0x0
#define PMC_IMPL_FMON_CONFIG_OSCnFUSE_CK_0_FMON_ENABLE_OSCnFUSE_CK_DEFAULT                      MK_MASK_CONST(0x1)
#define PMC_IMPL_FMON_CONFIG_OSCnFUSE_CK_0_FMON_ENABLE_OSCnFUSE_CK_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define PMC_IMPL_FMON_CONFIG_OSCnFUSE_CK_0_FMON_ENABLE_OSCnFUSE_CK_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define PMC_IMPL_FMON_CONFIG_OSCnFUSE_CK_0_FMON_ENABLE_OSCnFUSE_CK_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define PMC_IMPL_FMON_CONFIG_OSCnFUSE_CK_0_FMON_ENABLE_OSCnFUSE_CK_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define PMC_IMPL_FMON_CONFIG_OSCnFUSE_CK_0_FMON_ENABLE_OSCnFUSE_CK_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define PMC_IMPL_FMON_CONFIG_OSCnFUSE_CK_0_FMON_ENABLE_OSCnFUSE_CK_INIT_ENUM                    ENABLE
#define PMC_IMPL_FMON_CONFIG_OSCnFUSE_CK_0_FMON_ENABLE_OSCnFUSE_CK_DISABLE                      MK_ENUM_CONST(0)
#define PMC_IMPL_FMON_CONFIG_OSCnFUSE_CK_0_FMON_ENABLE_OSCnFUSE_CK_ENABLE                       MK_ENUM_CONST(1)

//Reset level:l1acoldrst_pmc_pclk_srstn

// Register PMC_IMPL_FMON_ENABLE_STATUS_OSCnFUSE_CK_0
#define PMC_IMPL_FMON_ENABLE_STATUS_OSCnFUSE_CK_0                       MK_ADDR_CONST(0x87c)
#define PMC_IMPL_FMON_ENABLE_STATUS_OSCnFUSE_CK_0_SECURE                        0x0
#define PMC_IMPL_FMON_ENABLE_STATUS_OSCnFUSE_CK_0_DUAL                  0x0
#define PMC_IMPL_FMON_ENABLE_STATUS_OSCnFUSE_CK_0_SCR                   OSCnFUSE_CK_SCR_0
#define PMC_IMPL_FMON_ENABLE_STATUS_OSCnFUSE_CK_0_SCRREG                        PMC_IMPL_SCR_OSCnFUSE_CK_SCR_0
#define PMC_IMPL_FMON_ENABLE_STATUS_OSCnFUSE_CK_0_WORD_COUNT                    0x1
#define PMC_IMPL_FMON_ENABLE_STATUS_OSCnFUSE_CK_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define PMC_IMPL_FMON_ENABLE_STATUS_OSCnFUSE_CK_0_RESET_MASK                    MK_MASK_CONST(0x7)
#define PMC_IMPL_FMON_ENABLE_STATUS_OSCnFUSE_CK_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define PMC_IMPL_FMON_ENABLE_STATUS_OSCnFUSE_CK_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define PMC_IMPL_FMON_ENABLE_STATUS_OSCnFUSE_CK_0_READ_MASK                     MK_MASK_CONST(0x7)
#define PMC_IMPL_FMON_ENABLE_STATUS_OSCnFUSE_CK_0_WRITE_MASK                    MK_MASK_CONST(0x0)
// Fmon_clk_domain Monitor enable (status). If the read value is not matching with FMON_ENABLE_PMC_CK, then the FMON_CLK (vref_ro_clk) is not running
#define PMC_IMPL_FMON_ENABLE_STATUS_OSCnFUSE_CK_0_FMON_ENABLE_FMON_CLK_STATUS_OSCnFUSE_CK_SHIFT                 MK_SHIFT_CONST(2)
#define PMC_IMPL_FMON_ENABLE_STATUS_OSCnFUSE_CK_0_FMON_ENABLE_FMON_CLK_STATUS_OSCnFUSE_CK_FIELD                 MK_FIELD_CONST(0x1, PMC_IMPL_FMON_ENABLE_STATUS_OSCnFUSE_CK_0_FMON_ENABLE_FMON_CLK_STATUS_OSCnFUSE_CK_SHIFT)
#define PMC_IMPL_FMON_ENABLE_STATUS_OSCnFUSE_CK_0_FMON_ENABLE_FMON_CLK_STATUS_OSCnFUSE_CK_RANGE                 2:2
#define PMC_IMPL_FMON_ENABLE_STATUS_OSCnFUSE_CK_0_FMON_ENABLE_FMON_CLK_STATUS_OSCnFUSE_CK_MSB                   MK_SHIFT_CONST(2)
#define PMC_IMPL_FMON_ENABLE_STATUS_OSCnFUSE_CK_0_FMON_ENABLE_FMON_CLK_STATUS_OSCnFUSE_CK_LSB                   MK_SHIFT_CONST(2)
#define PMC_IMPL_FMON_ENABLE_STATUS_OSCnFUSE_CK_0_FMON_ENABLE_FMON_CLK_STATUS_OSCnFUSE_CK_WOFFSET                       0x0
#define PMC_IMPL_FMON_ENABLE_STATUS_OSCnFUSE_CK_0_FMON_ENABLE_FMON_CLK_STATUS_OSCnFUSE_CK_DEFAULT                       MK_MASK_CONST(0x0)
#define PMC_IMPL_FMON_ENABLE_STATUS_OSCnFUSE_CK_0_FMON_ENABLE_FMON_CLK_STATUS_OSCnFUSE_CK_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define PMC_IMPL_FMON_ENABLE_STATUS_OSCnFUSE_CK_0_FMON_ENABLE_FMON_CLK_STATUS_OSCnFUSE_CK_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define PMC_IMPL_FMON_ENABLE_STATUS_OSCnFUSE_CK_0_FMON_ENABLE_FMON_CLK_STATUS_OSCnFUSE_CK_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define PMC_IMPL_FMON_ENABLE_STATUS_OSCnFUSE_CK_0_FMON_ENABLE_FMON_CLK_STATUS_OSCnFUSE_CK_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define PMC_IMPL_FMON_ENABLE_STATUS_OSCnFUSE_CK_0_FMON_ENABLE_FMON_CLK_STATUS_OSCnFUSE_CK_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define PMC_IMPL_FMON_ENABLE_STATUS_OSCnFUSE_CK_0_FMON_ENABLE_FMON_CLK_STATUS_OSCnFUSE_CK_INIT_ENUM                     FALSE
#define PMC_IMPL_FMON_ENABLE_STATUS_OSCnFUSE_CK_0_FMON_ENABLE_FMON_CLK_STATUS_OSCnFUSE_CK_FALSE                 MK_ENUM_CONST(0)
#define PMC_IMPL_FMON_ENABLE_STATUS_OSCnFUSE_CK_0_FMON_ENABLE_FMON_CLK_STATUS_OSCnFUSE_CK_TRUE                  MK_ENUM_CONST(1)

// Fmon_err_clk_domain Monitor enable (status). If the read value is not matching with FMON_ENABLE_PMC_CK, then the FMON_ERR_CLK (vref_ro_clk) is not running
#define PMC_IMPL_FMON_ENABLE_STATUS_OSCnFUSE_CK_0_FMON_ENABLE_FMON_ERR_CLK_STATUS_OSCnFUSE_CK_SHIFT                     MK_SHIFT_CONST(1)
#define PMC_IMPL_FMON_ENABLE_STATUS_OSCnFUSE_CK_0_FMON_ENABLE_FMON_ERR_CLK_STATUS_OSCnFUSE_CK_FIELD                     MK_FIELD_CONST(0x1, PMC_IMPL_FMON_ENABLE_STATUS_OSCnFUSE_CK_0_FMON_ENABLE_FMON_ERR_CLK_STATUS_OSCnFUSE_CK_SHIFT)
#define PMC_IMPL_FMON_ENABLE_STATUS_OSCnFUSE_CK_0_FMON_ENABLE_FMON_ERR_CLK_STATUS_OSCnFUSE_CK_RANGE                     1:1
#define PMC_IMPL_FMON_ENABLE_STATUS_OSCnFUSE_CK_0_FMON_ENABLE_FMON_ERR_CLK_STATUS_OSCnFUSE_CK_MSB                       MK_SHIFT_CONST(1)
#define PMC_IMPL_FMON_ENABLE_STATUS_OSCnFUSE_CK_0_FMON_ENABLE_FMON_ERR_CLK_STATUS_OSCnFUSE_CK_LSB                       MK_SHIFT_CONST(1)
#define PMC_IMPL_FMON_ENABLE_STATUS_OSCnFUSE_CK_0_FMON_ENABLE_FMON_ERR_CLK_STATUS_OSCnFUSE_CK_WOFFSET                   0x0
#define PMC_IMPL_FMON_ENABLE_STATUS_OSCnFUSE_CK_0_FMON_ENABLE_FMON_ERR_CLK_STATUS_OSCnFUSE_CK_DEFAULT                   MK_MASK_CONST(0x0)
#define PMC_IMPL_FMON_ENABLE_STATUS_OSCnFUSE_CK_0_FMON_ENABLE_FMON_ERR_CLK_STATUS_OSCnFUSE_CK_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define PMC_IMPL_FMON_ENABLE_STATUS_OSCnFUSE_CK_0_FMON_ENABLE_FMON_ERR_CLK_STATUS_OSCnFUSE_CK_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define PMC_IMPL_FMON_ENABLE_STATUS_OSCnFUSE_CK_0_FMON_ENABLE_FMON_ERR_CLK_STATUS_OSCnFUSE_CK_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define PMC_IMPL_FMON_ENABLE_STATUS_OSCnFUSE_CK_0_FMON_ENABLE_FMON_ERR_CLK_STATUS_OSCnFUSE_CK_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define PMC_IMPL_FMON_ENABLE_STATUS_OSCnFUSE_CK_0_FMON_ENABLE_FMON_ERR_CLK_STATUS_OSCnFUSE_CK_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define PMC_IMPL_FMON_ENABLE_STATUS_OSCnFUSE_CK_0_FMON_ENABLE_FMON_ERR_CLK_STATUS_OSCnFUSE_CK_INIT_ENUM                 FALSE
#define PMC_IMPL_FMON_ENABLE_STATUS_OSCnFUSE_CK_0_FMON_ENABLE_FMON_ERR_CLK_STATUS_OSCnFUSE_CK_FALSE                     MK_ENUM_CONST(0)
#define PMC_IMPL_FMON_ENABLE_STATUS_OSCnFUSE_CK_0_FMON_ENABLE_FMON_ERR_CLK_STATUS_OSCnFUSE_CK_TRUE                      MK_ENUM_CONST(1)

// Fmon_ref_clk_domain Monitor enable (status). If the read value is not matching with FMON_ENABLE_PMC_CK, then the FMON_REF_CLK (PMC_CLK/32khz clk) is not running
#define PMC_IMPL_FMON_ENABLE_STATUS_OSCnFUSE_CK_0_FMON_ENABLE_FMON_REF_CLK_STATUS_OSCnFUSE_CK_SHIFT                     MK_SHIFT_CONST(0)
#define PMC_IMPL_FMON_ENABLE_STATUS_OSCnFUSE_CK_0_FMON_ENABLE_FMON_REF_CLK_STATUS_OSCnFUSE_CK_FIELD                     MK_FIELD_CONST(0x1, PMC_IMPL_FMON_ENABLE_STATUS_OSCnFUSE_CK_0_FMON_ENABLE_FMON_REF_CLK_STATUS_OSCnFUSE_CK_SHIFT)
#define PMC_IMPL_FMON_ENABLE_STATUS_OSCnFUSE_CK_0_FMON_ENABLE_FMON_REF_CLK_STATUS_OSCnFUSE_CK_RANGE                     0:0
#define PMC_IMPL_FMON_ENABLE_STATUS_OSCnFUSE_CK_0_FMON_ENABLE_FMON_REF_CLK_STATUS_OSCnFUSE_CK_MSB                       MK_SHIFT_CONST(0)
#define PMC_IMPL_FMON_ENABLE_STATUS_OSCnFUSE_CK_0_FMON_ENABLE_FMON_REF_CLK_STATUS_OSCnFUSE_CK_LSB                       MK_SHIFT_CONST(0)
#define PMC_IMPL_FMON_ENABLE_STATUS_OSCnFUSE_CK_0_FMON_ENABLE_FMON_REF_CLK_STATUS_OSCnFUSE_CK_WOFFSET                   0x0
#define PMC_IMPL_FMON_ENABLE_STATUS_OSCnFUSE_CK_0_FMON_ENABLE_FMON_REF_CLK_STATUS_OSCnFUSE_CK_DEFAULT                   MK_MASK_CONST(0x0)
#define PMC_IMPL_FMON_ENABLE_STATUS_OSCnFUSE_CK_0_FMON_ENABLE_FMON_REF_CLK_STATUS_OSCnFUSE_CK_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define PMC_IMPL_FMON_ENABLE_STATUS_OSCnFUSE_CK_0_FMON_ENABLE_FMON_REF_CLK_STATUS_OSCnFUSE_CK_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define PMC_IMPL_FMON_ENABLE_STATUS_OSCnFUSE_CK_0_FMON_ENABLE_FMON_REF_CLK_STATUS_OSCnFUSE_CK_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define PMC_IMPL_FMON_ENABLE_STATUS_OSCnFUSE_CK_0_FMON_ENABLE_FMON_REF_CLK_STATUS_OSCnFUSE_CK_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define PMC_IMPL_FMON_ENABLE_STATUS_OSCnFUSE_CK_0_FMON_ENABLE_FMON_REF_CLK_STATUS_OSCnFUSE_CK_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define PMC_IMPL_FMON_ENABLE_STATUS_OSCnFUSE_CK_0_FMON_ENABLE_FMON_REF_CLK_STATUS_OSCnFUSE_CK_INIT_ENUM                 FALSE
#define PMC_IMPL_FMON_ENABLE_STATUS_OSCnFUSE_CK_0_FMON_ENABLE_FMON_REF_CLK_STATUS_OSCnFUSE_CK_FALSE                     MK_ENUM_CONST(0)
#define PMC_IMPL_FMON_ENABLE_STATUS_OSCnFUSE_CK_0_FMON_ENABLE_FMON_REF_CLK_STATUS_OSCnFUSE_CK_TRUE                      MK_ENUM_CONST(1)

//Reset level:l1acoldrst_pmc_pclk_srstn

// Register PMC_IMPL_FMON_FAULT_STATUS_OSCnFUSE_CK_0
#define PMC_IMPL_FMON_FAULT_STATUS_OSCnFUSE_CK_0                        MK_ADDR_CONST(0x880)
#define PMC_IMPL_FMON_FAULT_STATUS_OSCnFUSE_CK_0_SECURE                         0x0
#define PMC_IMPL_FMON_FAULT_STATUS_OSCnFUSE_CK_0_DUAL                   0x0
#define PMC_IMPL_FMON_FAULT_STATUS_OSCnFUSE_CK_0_SCR                    OSCnFUSE_CK_SCR_0
#define PMC_IMPL_FMON_FAULT_STATUS_OSCnFUSE_CK_0_SCRREG                         PMC_IMPL_SCR_OSCnFUSE_CK_SCR_0
#define PMC_IMPL_FMON_FAULT_STATUS_OSCnFUSE_CK_0_WORD_COUNT                     0x1
#define PMC_IMPL_FMON_FAULT_STATUS_OSCnFUSE_CK_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define PMC_IMPL_FMON_FAULT_STATUS_OSCnFUSE_CK_0_RESET_MASK                     MK_MASK_CONST(0x8000001f)
#define PMC_IMPL_FMON_FAULT_STATUS_OSCnFUSE_CK_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define PMC_IMPL_FMON_FAULT_STATUS_OSCnFUSE_CK_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define PMC_IMPL_FMON_FAULT_STATUS_OSCnFUSE_CK_0_READ_MASK                      MK_MASK_CONST(0x8000001f)
#define PMC_IMPL_FMON_FAULT_STATUS_OSCnFUSE_CK_0_WRITE_MASK                     MK_MASK_CONST(0x80000000)
// Write 1 to this field to clear all fault status fields in this register.  writing 0 has no effect, writing 1 toggles the bit, toggled value reflects in the read data (not the written data).
#define PMC_IMPL_FMON_FAULT_STATUS_OSCnFUSE_CK_0_FMON_FAULT_CLEAR_OSCnFUSE_CK_SHIFT                     MK_SHIFT_CONST(31)
#define PMC_IMPL_FMON_FAULT_STATUS_OSCnFUSE_CK_0_FMON_FAULT_CLEAR_OSCnFUSE_CK_FIELD                     MK_FIELD_CONST(0x1, PMC_IMPL_FMON_FAULT_STATUS_OSCnFUSE_CK_0_FMON_FAULT_CLEAR_OSCnFUSE_CK_SHIFT)
#define PMC_IMPL_FMON_FAULT_STATUS_OSCnFUSE_CK_0_FMON_FAULT_CLEAR_OSCnFUSE_CK_RANGE                     31:31
#define PMC_IMPL_FMON_FAULT_STATUS_OSCnFUSE_CK_0_FMON_FAULT_CLEAR_OSCnFUSE_CK_MSB                       MK_SHIFT_CONST(31)
#define PMC_IMPL_FMON_FAULT_STATUS_OSCnFUSE_CK_0_FMON_FAULT_CLEAR_OSCnFUSE_CK_LSB                       MK_SHIFT_CONST(31)
#define PMC_IMPL_FMON_FAULT_STATUS_OSCnFUSE_CK_0_FMON_FAULT_CLEAR_OSCnFUSE_CK_WOFFSET                   0x0
#define PMC_IMPL_FMON_FAULT_STATUS_OSCnFUSE_CK_0_FMON_FAULT_CLEAR_OSCnFUSE_CK_DEFAULT                   MK_MASK_CONST(0x0)
#define PMC_IMPL_FMON_FAULT_STATUS_OSCnFUSE_CK_0_FMON_FAULT_CLEAR_OSCnFUSE_CK_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define PMC_IMPL_FMON_FAULT_STATUS_OSCnFUSE_CK_0_FMON_FAULT_CLEAR_OSCnFUSE_CK_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define PMC_IMPL_FMON_FAULT_STATUS_OSCnFUSE_CK_0_FMON_FAULT_CLEAR_OSCnFUSE_CK_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define PMC_IMPL_FMON_FAULT_STATUS_OSCnFUSE_CK_0_FMON_FAULT_CLEAR_OSCnFUSE_CK_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define PMC_IMPL_FMON_FAULT_STATUS_OSCnFUSE_CK_0_FMON_FAULT_CLEAR_OSCnFUSE_CK_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define PMC_IMPL_FMON_FAULT_STATUS_OSCnFUSE_CK_0_FMON_FAULT_CLEAR_OSCnFUSE_CK_INIT_ENUM                 FALSE
#define PMC_IMPL_FMON_FAULT_STATUS_OSCnFUSE_CK_0_FMON_FAULT_CLEAR_OSCnFUSE_CK_FALSE                     MK_ENUM_CONST(0)
#define PMC_IMPL_FMON_FAULT_STATUS_OSCnFUSE_CK_0_FMON_FAULT_CLEAR_OSCnFUSE_CK_TRUE                      MK_ENUM_CONST(1)

// If read 1, fault_out_pulse pin has toggled at least once. Cleared by FMON_FAULT_CLEAR_OSCnFUSE_CK
#define PMC_IMPL_FMON_FAULT_STATUS_OSCnFUSE_CK_0_FMON_FAULT_OUT_STATUS_OSCnFUSE_CK_SHIFT                        MK_SHIFT_CONST(4)
#define PMC_IMPL_FMON_FAULT_STATUS_OSCnFUSE_CK_0_FMON_FAULT_OUT_STATUS_OSCnFUSE_CK_FIELD                        MK_FIELD_CONST(0x1, PMC_IMPL_FMON_FAULT_STATUS_OSCnFUSE_CK_0_FMON_FAULT_OUT_STATUS_OSCnFUSE_CK_SHIFT)
#define PMC_IMPL_FMON_FAULT_STATUS_OSCnFUSE_CK_0_FMON_FAULT_OUT_STATUS_OSCnFUSE_CK_RANGE                        4:4
#define PMC_IMPL_FMON_FAULT_STATUS_OSCnFUSE_CK_0_FMON_FAULT_OUT_STATUS_OSCnFUSE_CK_MSB                  MK_SHIFT_CONST(4)
#define PMC_IMPL_FMON_FAULT_STATUS_OSCnFUSE_CK_0_FMON_FAULT_OUT_STATUS_OSCnFUSE_CK_LSB                  MK_SHIFT_CONST(4)
#define PMC_IMPL_FMON_FAULT_STATUS_OSCnFUSE_CK_0_FMON_FAULT_OUT_STATUS_OSCnFUSE_CK_WOFFSET                      0x0
#define PMC_IMPL_FMON_FAULT_STATUS_OSCnFUSE_CK_0_FMON_FAULT_OUT_STATUS_OSCnFUSE_CK_DEFAULT                      MK_MASK_CONST(0x0)
#define PMC_IMPL_FMON_FAULT_STATUS_OSCnFUSE_CK_0_FMON_FAULT_OUT_STATUS_OSCnFUSE_CK_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define PMC_IMPL_FMON_FAULT_STATUS_OSCnFUSE_CK_0_FMON_FAULT_OUT_STATUS_OSCnFUSE_CK_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define PMC_IMPL_FMON_FAULT_STATUS_OSCnFUSE_CK_0_FMON_FAULT_OUT_STATUS_OSCnFUSE_CK_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define PMC_IMPL_FMON_FAULT_STATUS_OSCnFUSE_CK_0_FMON_FAULT_OUT_STATUS_OSCnFUSE_CK_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define PMC_IMPL_FMON_FAULT_STATUS_OSCnFUSE_CK_0_FMON_FAULT_OUT_STATUS_OSCnFUSE_CK_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define PMC_IMPL_FMON_FAULT_STATUS_OSCnFUSE_CK_0_FMON_FAULT_OUT_STATUS_OSCnFUSE_CK_INIT_ENUM                    FALSE
#define PMC_IMPL_FMON_FAULT_STATUS_OSCnFUSE_CK_0_FMON_FAULT_OUT_STATUS_OSCnFUSE_CK_FALSE                        MK_ENUM_CONST(0)
#define PMC_IMPL_FMON_FAULT_STATUS_OSCnFUSE_CK_0_FMON_FAULT_OUT_STATUS_OSCnFUSE_CK_TRUE                 MK_ENUM_CONST(1)

// If read 1, overflow error has occured. Cleared by FMON_FAULT_CLEAR_OSCnFUSE_CK
#define PMC_IMPL_FMON_FAULT_STATUS_OSCnFUSE_CK_0_FMON_OVERFLOW_ERROR_OSCnFUSE_CK_SHIFT                  MK_SHIFT_CONST(3)
#define PMC_IMPL_FMON_FAULT_STATUS_OSCnFUSE_CK_0_FMON_OVERFLOW_ERROR_OSCnFUSE_CK_FIELD                  MK_FIELD_CONST(0x1, PMC_IMPL_FMON_FAULT_STATUS_OSCnFUSE_CK_0_FMON_OVERFLOW_ERROR_OSCnFUSE_CK_SHIFT)
#define PMC_IMPL_FMON_FAULT_STATUS_OSCnFUSE_CK_0_FMON_OVERFLOW_ERROR_OSCnFUSE_CK_RANGE                  3:3
#define PMC_IMPL_FMON_FAULT_STATUS_OSCnFUSE_CK_0_FMON_OVERFLOW_ERROR_OSCnFUSE_CK_MSB                    MK_SHIFT_CONST(3)
#define PMC_IMPL_FMON_FAULT_STATUS_OSCnFUSE_CK_0_FMON_OVERFLOW_ERROR_OSCnFUSE_CK_LSB                    MK_SHIFT_CONST(3)
#define PMC_IMPL_FMON_FAULT_STATUS_OSCnFUSE_CK_0_FMON_OVERFLOW_ERROR_OSCnFUSE_CK_WOFFSET                        0x0
#define PMC_IMPL_FMON_FAULT_STATUS_OSCnFUSE_CK_0_FMON_OVERFLOW_ERROR_OSCnFUSE_CK_DEFAULT                        MK_MASK_CONST(0x0)
#define PMC_IMPL_FMON_FAULT_STATUS_OSCnFUSE_CK_0_FMON_OVERFLOW_ERROR_OSCnFUSE_CK_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define PMC_IMPL_FMON_FAULT_STATUS_OSCnFUSE_CK_0_FMON_OVERFLOW_ERROR_OSCnFUSE_CK_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define PMC_IMPL_FMON_FAULT_STATUS_OSCnFUSE_CK_0_FMON_OVERFLOW_ERROR_OSCnFUSE_CK_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define PMC_IMPL_FMON_FAULT_STATUS_OSCnFUSE_CK_0_FMON_OVERFLOW_ERROR_OSCnFUSE_CK_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define PMC_IMPL_FMON_FAULT_STATUS_OSCnFUSE_CK_0_FMON_OVERFLOW_ERROR_OSCnFUSE_CK_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define PMC_IMPL_FMON_FAULT_STATUS_OSCnFUSE_CK_0_FMON_OVERFLOW_ERROR_OSCnFUSE_CK_INIT_ENUM                      FALSE
#define PMC_IMPL_FMON_FAULT_STATUS_OSCnFUSE_CK_0_FMON_OVERFLOW_ERROR_OSCnFUSE_CK_FALSE                  MK_ENUM_CONST(0)
#define PMC_IMPL_FMON_FAULT_STATUS_OSCnFUSE_CK_0_FMON_OVERFLOW_ERROR_OSCnFUSE_CK_TRUE                   MK_ENUM_CONST(1)

// If read 1, high threshold error has occured. Cleared by FMON_FAULT_CLEAR_OSCnFUSE_CK
#define PMC_IMPL_FMON_FAULT_STATUS_OSCnFUSE_CK_0_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_OSCnFUSE_CK_SHIFT                  MK_SHIFT_CONST(2)
#define PMC_IMPL_FMON_FAULT_STATUS_OSCnFUSE_CK_0_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_OSCnFUSE_CK_FIELD                  MK_FIELD_CONST(0x1, PMC_IMPL_FMON_FAULT_STATUS_OSCnFUSE_CK_0_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_OSCnFUSE_CK_SHIFT)
#define PMC_IMPL_FMON_FAULT_STATUS_OSCnFUSE_CK_0_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_OSCnFUSE_CK_RANGE                  2:2
#define PMC_IMPL_FMON_FAULT_STATUS_OSCnFUSE_CK_0_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_OSCnFUSE_CK_MSB                    MK_SHIFT_CONST(2)
#define PMC_IMPL_FMON_FAULT_STATUS_OSCnFUSE_CK_0_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_OSCnFUSE_CK_LSB                    MK_SHIFT_CONST(2)
#define PMC_IMPL_FMON_FAULT_STATUS_OSCnFUSE_CK_0_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_OSCnFUSE_CK_WOFFSET                        0x0
#define PMC_IMPL_FMON_FAULT_STATUS_OSCnFUSE_CK_0_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_OSCnFUSE_CK_DEFAULT                        MK_MASK_CONST(0x0)
#define PMC_IMPL_FMON_FAULT_STATUS_OSCnFUSE_CK_0_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_OSCnFUSE_CK_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define PMC_IMPL_FMON_FAULT_STATUS_OSCnFUSE_CK_0_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_OSCnFUSE_CK_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define PMC_IMPL_FMON_FAULT_STATUS_OSCnFUSE_CK_0_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_OSCnFUSE_CK_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define PMC_IMPL_FMON_FAULT_STATUS_OSCnFUSE_CK_0_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_OSCnFUSE_CK_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define PMC_IMPL_FMON_FAULT_STATUS_OSCnFUSE_CK_0_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_OSCnFUSE_CK_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define PMC_IMPL_FMON_FAULT_STATUS_OSCnFUSE_CK_0_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_OSCnFUSE_CK_INIT_ENUM                      FALSE
#define PMC_IMPL_FMON_FAULT_STATUS_OSCnFUSE_CK_0_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_OSCnFUSE_CK_FALSE                  MK_ENUM_CONST(0)
#define PMC_IMPL_FMON_FAULT_STATUS_OSCnFUSE_CK_0_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_OSCnFUSE_CK_TRUE                   MK_ENUM_CONST(1)

// If read 1, low threshold error has occurred. Cleared by FMON_FAULT_CLEAR_OSCnFUSE_CK
#define PMC_IMPL_FMON_FAULT_STATUS_OSCnFUSE_CK_0_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_OSCnFUSE_CK_SHIFT                   MK_SHIFT_CONST(1)
#define PMC_IMPL_FMON_FAULT_STATUS_OSCnFUSE_CK_0_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_OSCnFUSE_CK_FIELD                   MK_FIELD_CONST(0x1, PMC_IMPL_FMON_FAULT_STATUS_OSCnFUSE_CK_0_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_OSCnFUSE_CK_SHIFT)
#define PMC_IMPL_FMON_FAULT_STATUS_OSCnFUSE_CK_0_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_OSCnFUSE_CK_RANGE                   1:1
#define PMC_IMPL_FMON_FAULT_STATUS_OSCnFUSE_CK_0_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_OSCnFUSE_CK_MSB                     MK_SHIFT_CONST(1)
#define PMC_IMPL_FMON_FAULT_STATUS_OSCnFUSE_CK_0_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_OSCnFUSE_CK_LSB                     MK_SHIFT_CONST(1)
#define PMC_IMPL_FMON_FAULT_STATUS_OSCnFUSE_CK_0_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_OSCnFUSE_CK_WOFFSET                 0x0
#define PMC_IMPL_FMON_FAULT_STATUS_OSCnFUSE_CK_0_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_OSCnFUSE_CK_DEFAULT                 MK_MASK_CONST(0x0)
#define PMC_IMPL_FMON_FAULT_STATUS_OSCnFUSE_CK_0_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_OSCnFUSE_CK_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define PMC_IMPL_FMON_FAULT_STATUS_OSCnFUSE_CK_0_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_OSCnFUSE_CK_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define PMC_IMPL_FMON_FAULT_STATUS_OSCnFUSE_CK_0_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_OSCnFUSE_CK_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define PMC_IMPL_FMON_FAULT_STATUS_OSCnFUSE_CK_0_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_OSCnFUSE_CK_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define PMC_IMPL_FMON_FAULT_STATUS_OSCnFUSE_CK_0_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_OSCnFUSE_CK_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define PMC_IMPL_FMON_FAULT_STATUS_OSCnFUSE_CK_0_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_OSCnFUSE_CK_INIT_ENUM                       FALSE
#define PMC_IMPL_FMON_FAULT_STATUS_OSCnFUSE_CK_0_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_OSCnFUSE_CK_FALSE                   MK_ENUM_CONST(0)
#define PMC_IMPL_FMON_FAULT_STATUS_OSCnFUSE_CK_0_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_OSCnFUSE_CK_TRUE                    MK_ENUM_CONST(1)

// If read 1, DC fault has occured. DC fault can be triggered by overflow error as define USE_CNTR_OVERFLOW_DC_RSTREQ is used in RTL.
#define PMC_IMPL_FMON_FAULT_STATUS_OSCnFUSE_CK_0_FMON_DC_FAULT_OSCnFUSE_CK_SHIFT                        MK_SHIFT_CONST(0)
#define PMC_IMPL_FMON_FAULT_STATUS_OSCnFUSE_CK_0_FMON_DC_FAULT_OSCnFUSE_CK_FIELD                        MK_FIELD_CONST(0x1, PMC_IMPL_FMON_FAULT_STATUS_OSCnFUSE_CK_0_FMON_DC_FAULT_OSCnFUSE_CK_SHIFT)
#define PMC_IMPL_FMON_FAULT_STATUS_OSCnFUSE_CK_0_FMON_DC_FAULT_OSCnFUSE_CK_RANGE                        0:0
#define PMC_IMPL_FMON_FAULT_STATUS_OSCnFUSE_CK_0_FMON_DC_FAULT_OSCnFUSE_CK_MSB                  MK_SHIFT_CONST(0)
#define PMC_IMPL_FMON_FAULT_STATUS_OSCnFUSE_CK_0_FMON_DC_FAULT_OSCnFUSE_CK_LSB                  MK_SHIFT_CONST(0)
#define PMC_IMPL_FMON_FAULT_STATUS_OSCnFUSE_CK_0_FMON_DC_FAULT_OSCnFUSE_CK_WOFFSET                      0x0
#define PMC_IMPL_FMON_FAULT_STATUS_OSCnFUSE_CK_0_FMON_DC_FAULT_OSCnFUSE_CK_DEFAULT                      MK_MASK_CONST(0x0)
#define PMC_IMPL_FMON_FAULT_STATUS_OSCnFUSE_CK_0_FMON_DC_FAULT_OSCnFUSE_CK_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define PMC_IMPL_FMON_FAULT_STATUS_OSCnFUSE_CK_0_FMON_DC_FAULT_OSCnFUSE_CK_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define PMC_IMPL_FMON_FAULT_STATUS_OSCnFUSE_CK_0_FMON_DC_FAULT_OSCnFUSE_CK_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define PMC_IMPL_FMON_FAULT_STATUS_OSCnFUSE_CK_0_FMON_DC_FAULT_OSCnFUSE_CK_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define PMC_IMPL_FMON_FAULT_STATUS_OSCnFUSE_CK_0_FMON_DC_FAULT_OSCnFUSE_CK_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define PMC_IMPL_FMON_FAULT_STATUS_OSCnFUSE_CK_0_FMON_DC_FAULT_OSCnFUSE_CK_INIT_ENUM                    FALSE
#define PMC_IMPL_FMON_FAULT_STATUS_OSCnFUSE_CK_0_FMON_DC_FAULT_OSCnFUSE_CK_FALSE                        MK_ENUM_CONST(0)
#define PMC_IMPL_FMON_FAULT_STATUS_OSCnFUSE_CK_0_FMON_DC_FAULT_OSCnFUSE_CK_TRUE                 MK_ENUM_CONST(1)

//Reset level:l1acoldrst_pmc_pclk_srstn

// Register PMC_IMPL_FMON_LOAD_DATA_CTRL_OSCnFUSE_CK_0
#define PMC_IMPL_FMON_LOAD_DATA_CTRL_OSCnFUSE_CK_0                      MK_ADDR_CONST(0x884)
#define PMC_IMPL_FMON_LOAD_DATA_CTRL_OSCnFUSE_CK_0_SECURE                       0x0
#define PMC_IMPL_FMON_LOAD_DATA_CTRL_OSCnFUSE_CK_0_DUAL                         0x0
#define PMC_IMPL_FMON_LOAD_DATA_CTRL_OSCnFUSE_CK_0_SCR                  OSCnFUSE_CK_SCR_0
#define PMC_IMPL_FMON_LOAD_DATA_CTRL_OSCnFUSE_CK_0_SCRREG                       PMC_IMPL_SCR_OSCnFUSE_CK_SCR_0
#define PMC_IMPL_FMON_LOAD_DATA_CTRL_OSCnFUSE_CK_0_WORD_COUNT                   0x1
#define PMC_IMPL_FMON_LOAD_DATA_CTRL_OSCnFUSE_CK_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define PMC_IMPL_FMON_LOAD_DATA_CTRL_OSCnFUSE_CK_0_RESET_MASK                   MK_MASK_CONST(0x80000007)
#define PMC_IMPL_FMON_LOAD_DATA_CTRL_OSCnFUSE_CK_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define PMC_IMPL_FMON_LOAD_DATA_CTRL_OSCnFUSE_CK_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define PMC_IMPL_FMON_LOAD_DATA_CTRL_OSCnFUSE_CK_0_READ_MASK                    MK_MASK_CONST(0x80000007)
#define PMC_IMPL_FMON_LOAD_DATA_CTRL_OSCnFUSE_CK_0_WRITE_MASK                   MK_MASK_CONST(0x80000007)
// Load data enable signal
#define PMC_IMPL_FMON_LOAD_DATA_CTRL_OSCnFUSE_CK_0_FMON_LOAD_DATA_OSCnFUSE_CK_SHIFT                     MK_SHIFT_CONST(31)
#define PMC_IMPL_FMON_LOAD_DATA_CTRL_OSCnFUSE_CK_0_FMON_LOAD_DATA_OSCnFUSE_CK_FIELD                     MK_FIELD_CONST(0x1, PMC_IMPL_FMON_LOAD_DATA_CTRL_OSCnFUSE_CK_0_FMON_LOAD_DATA_OSCnFUSE_CK_SHIFT)
#define PMC_IMPL_FMON_LOAD_DATA_CTRL_OSCnFUSE_CK_0_FMON_LOAD_DATA_OSCnFUSE_CK_RANGE                     31:31
#define PMC_IMPL_FMON_LOAD_DATA_CTRL_OSCnFUSE_CK_0_FMON_LOAD_DATA_OSCnFUSE_CK_MSB                       MK_SHIFT_CONST(31)
#define PMC_IMPL_FMON_LOAD_DATA_CTRL_OSCnFUSE_CK_0_FMON_LOAD_DATA_OSCnFUSE_CK_LSB                       MK_SHIFT_CONST(31)
#define PMC_IMPL_FMON_LOAD_DATA_CTRL_OSCnFUSE_CK_0_FMON_LOAD_DATA_OSCnFUSE_CK_WOFFSET                   0x0
#define PMC_IMPL_FMON_LOAD_DATA_CTRL_OSCnFUSE_CK_0_FMON_LOAD_DATA_OSCnFUSE_CK_DEFAULT                   MK_MASK_CONST(0x0)
#define PMC_IMPL_FMON_LOAD_DATA_CTRL_OSCnFUSE_CK_0_FMON_LOAD_DATA_OSCnFUSE_CK_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define PMC_IMPL_FMON_LOAD_DATA_CTRL_OSCnFUSE_CK_0_FMON_LOAD_DATA_OSCnFUSE_CK_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define PMC_IMPL_FMON_LOAD_DATA_CTRL_OSCnFUSE_CK_0_FMON_LOAD_DATA_OSCnFUSE_CK_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define PMC_IMPL_FMON_LOAD_DATA_CTRL_OSCnFUSE_CK_0_FMON_LOAD_DATA_OSCnFUSE_CK_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define PMC_IMPL_FMON_LOAD_DATA_CTRL_OSCnFUSE_CK_0_FMON_LOAD_DATA_OSCnFUSE_CK_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define PMC_IMPL_FMON_LOAD_DATA_CTRL_OSCnFUSE_CK_0_FMON_LOAD_DATA_OSCnFUSE_CK_INIT_ENUM                 DISABLE
#define PMC_IMPL_FMON_LOAD_DATA_CTRL_OSCnFUSE_CK_0_FMON_LOAD_DATA_OSCnFUSE_CK_DISABLE                   MK_ENUM_CONST(0)
#define PMC_IMPL_FMON_LOAD_DATA_CTRL_OSCnFUSE_CK_0_FMON_LOAD_DATA_OSCnFUSE_CK_ENABLE                    MK_ENUM_CONST(1)

// Select value to load
// 0x1 - Min
// 0x2 - Max
// 0x3 - Count [0] (latest Count)
// 0x4 - Count [1]
// 0x5 - Count [2]
// 0x6 - Count [3]
// 0x7 - Count [4] (Earliest count)
#define PMC_IMPL_FMON_LOAD_DATA_CTRL_OSCnFUSE_CK_0_FMON_LOAD_DATA_SEL_OSCnFUSE_CK_SHIFT                 MK_SHIFT_CONST(0)
#define PMC_IMPL_FMON_LOAD_DATA_CTRL_OSCnFUSE_CK_0_FMON_LOAD_DATA_SEL_OSCnFUSE_CK_FIELD                 MK_FIELD_CONST(0x7, PMC_IMPL_FMON_LOAD_DATA_CTRL_OSCnFUSE_CK_0_FMON_LOAD_DATA_SEL_OSCnFUSE_CK_SHIFT)
#define PMC_IMPL_FMON_LOAD_DATA_CTRL_OSCnFUSE_CK_0_FMON_LOAD_DATA_SEL_OSCnFUSE_CK_RANGE                 2:0
#define PMC_IMPL_FMON_LOAD_DATA_CTRL_OSCnFUSE_CK_0_FMON_LOAD_DATA_SEL_OSCnFUSE_CK_MSB                   MK_SHIFT_CONST(2)
#define PMC_IMPL_FMON_LOAD_DATA_CTRL_OSCnFUSE_CK_0_FMON_LOAD_DATA_SEL_OSCnFUSE_CK_LSB                   MK_SHIFT_CONST(0)
#define PMC_IMPL_FMON_LOAD_DATA_CTRL_OSCnFUSE_CK_0_FMON_LOAD_DATA_SEL_OSCnFUSE_CK_WOFFSET                       0x0
#define PMC_IMPL_FMON_LOAD_DATA_CTRL_OSCnFUSE_CK_0_FMON_LOAD_DATA_SEL_OSCnFUSE_CK_DEFAULT                       MK_MASK_CONST(0x0)
#define PMC_IMPL_FMON_LOAD_DATA_CTRL_OSCnFUSE_CK_0_FMON_LOAD_DATA_SEL_OSCnFUSE_CK_DEFAULT_MASK                  MK_MASK_CONST(0x7)
#define PMC_IMPL_FMON_LOAD_DATA_CTRL_OSCnFUSE_CK_0_FMON_LOAD_DATA_SEL_OSCnFUSE_CK_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define PMC_IMPL_FMON_LOAD_DATA_CTRL_OSCnFUSE_CK_0_FMON_LOAD_DATA_SEL_OSCnFUSE_CK_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define PMC_IMPL_FMON_LOAD_DATA_CTRL_OSCnFUSE_CK_0_FMON_LOAD_DATA_SEL_OSCnFUSE_CK_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define PMC_IMPL_FMON_LOAD_DATA_CTRL_OSCnFUSE_CK_0_FMON_LOAD_DATA_SEL_OSCnFUSE_CK_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define PMC_IMPL_FMON_LOAD_DATA_CTRL_OSCnFUSE_CK_0_FMON_LOAD_DATA_SEL_OSCnFUSE_CK_INIT_ENUM                     DISABLE
#define PMC_IMPL_FMON_LOAD_DATA_CTRL_OSCnFUSE_CK_0_FMON_LOAD_DATA_SEL_OSCnFUSE_CK_DISABLE                       MK_ENUM_CONST(0)
#define PMC_IMPL_FMON_LOAD_DATA_CTRL_OSCnFUSE_CK_0_FMON_LOAD_DATA_SEL_OSCnFUSE_CK_ENABLE                        MK_ENUM_CONST(1)

//Reset level:l1acoldrst_pmc_pclk_srstn

// Register PMC_IMPL_FMON_LOAD_DATA_STATUS_0_OSCnFUSE_CK_0
#define PMC_IMPL_FMON_LOAD_DATA_STATUS_0_OSCnFUSE_CK_0                  MK_ADDR_CONST(0x888)
#define PMC_IMPL_FMON_LOAD_DATA_STATUS_0_OSCnFUSE_CK_0_SECURE                   0x0
#define PMC_IMPL_FMON_LOAD_DATA_STATUS_0_OSCnFUSE_CK_0_DUAL                     0x0
#define PMC_IMPL_FMON_LOAD_DATA_STATUS_0_OSCnFUSE_CK_0_SCR                      OSCnFUSE_CK_SCR_0
#define PMC_IMPL_FMON_LOAD_DATA_STATUS_0_OSCnFUSE_CK_0_SCRREG                   PMC_IMPL_SCR_OSCnFUSE_CK_SCR_0
#define PMC_IMPL_FMON_LOAD_DATA_STATUS_0_OSCnFUSE_CK_0_WORD_COUNT                       0x1
#define PMC_IMPL_FMON_LOAD_DATA_STATUS_0_OSCnFUSE_CK_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define PMC_IMPL_FMON_LOAD_DATA_STATUS_0_OSCnFUSE_CK_0_RESET_MASK                       MK_MASK_CONST(0x1)
#define PMC_IMPL_FMON_LOAD_DATA_STATUS_0_OSCnFUSE_CK_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define PMC_IMPL_FMON_LOAD_DATA_STATUS_0_OSCnFUSE_CK_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define PMC_IMPL_FMON_LOAD_DATA_STATUS_0_OSCnFUSE_CK_0_READ_MASK                        MK_MASK_CONST(0x1)
#define PMC_IMPL_FMON_LOAD_DATA_STATUS_0_OSCnFUSE_CK_0_WRITE_MASK                       MK_MASK_CONST(0x0)
// Status : Load data done
#define PMC_IMPL_FMON_LOAD_DATA_STATUS_0_OSCnFUSE_CK_0_FMON_LOAD_DATA_DONE_OSCnFUSE_CK_SHIFT                    MK_SHIFT_CONST(0)
#define PMC_IMPL_FMON_LOAD_DATA_STATUS_0_OSCnFUSE_CK_0_FMON_LOAD_DATA_DONE_OSCnFUSE_CK_FIELD                    MK_FIELD_CONST(0x1, PMC_IMPL_FMON_LOAD_DATA_STATUS_0_OSCnFUSE_CK_0_FMON_LOAD_DATA_DONE_OSCnFUSE_CK_SHIFT)
#define PMC_IMPL_FMON_LOAD_DATA_STATUS_0_OSCnFUSE_CK_0_FMON_LOAD_DATA_DONE_OSCnFUSE_CK_RANGE                    0:0
#define PMC_IMPL_FMON_LOAD_DATA_STATUS_0_OSCnFUSE_CK_0_FMON_LOAD_DATA_DONE_OSCnFUSE_CK_MSB                      MK_SHIFT_CONST(0)
#define PMC_IMPL_FMON_LOAD_DATA_STATUS_0_OSCnFUSE_CK_0_FMON_LOAD_DATA_DONE_OSCnFUSE_CK_LSB                      MK_SHIFT_CONST(0)
#define PMC_IMPL_FMON_LOAD_DATA_STATUS_0_OSCnFUSE_CK_0_FMON_LOAD_DATA_DONE_OSCnFUSE_CK_WOFFSET                  0x0
#define PMC_IMPL_FMON_LOAD_DATA_STATUS_0_OSCnFUSE_CK_0_FMON_LOAD_DATA_DONE_OSCnFUSE_CK_DEFAULT                  MK_MASK_CONST(0x0)
#define PMC_IMPL_FMON_LOAD_DATA_STATUS_0_OSCnFUSE_CK_0_FMON_LOAD_DATA_DONE_OSCnFUSE_CK_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define PMC_IMPL_FMON_LOAD_DATA_STATUS_0_OSCnFUSE_CK_0_FMON_LOAD_DATA_DONE_OSCnFUSE_CK_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define PMC_IMPL_FMON_LOAD_DATA_STATUS_0_OSCnFUSE_CK_0_FMON_LOAD_DATA_DONE_OSCnFUSE_CK_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define PMC_IMPL_FMON_LOAD_DATA_STATUS_0_OSCnFUSE_CK_0_FMON_LOAD_DATA_DONE_OSCnFUSE_CK_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define PMC_IMPL_FMON_LOAD_DATA_STATUS_0_OSCnFUSE_CK_0_FMON_LOAD_DATA_DONE_OSCnFUSE_CK_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define PMC_IMPL_FMON_LOAD_DATA_STATUS_0_OSCnFUSE_CK_0_FMON_LOAD_DATA_DONE_OSCnFUSE_CK_INIT_ENUM                        DISABLE
#define PMC_IMPL_FMON_LOAD_DATA_STATUS_0_OSCnFUSE_CK_0_FMON_LOAD_DATA_DONE_OSCnFUSE_CK_DISABLE                  MK_ENUM_CONST(0)
#define PMC_IMPL_FMON_LOAD_DATA_STATUS_0_OSCnFUSE_CK_0_FMON_LOAD_DATA_DONE_OSCnFUSE_CK_ENABLE                   MK_ENUM_CONST(1)

//Reset level:l1acoldrst_pmc_pclk_srstn

// Register PMC_IMPL_FMON_LOAD_DATA_STATUS_1_OSCnFUSE_CK_0
#define PMC_IMPL_FMON_LOAD_DATA_STATUS_1_OSCnFUSE_CK_0                  MK_ADDR_CONST(0x88c)
#define PMC_IMPL_FMON_LOAD_DATA_STATUS_1_OSCnFUSE_CK_0_SECURE                   0x0
#define PMC_IMPL_FMON_LOAD_DATA_STATUS_1_OSCnFUSE_CK_0_DUAL                     0x0
#define PMC_IMPL_FMON_LOAD_DATA_STATUS_1_OSCnFUSE_CK_0_SCR                      OSCnFUSE_CK_SCR_0
#define PMC_IMPL_FMON_LOAD_DATA_STATUS_1_OSCnFUSE_CK_0_SCRREG                   PMC_IMPL_SCR_OSCnFUSE_CK_SCR_0
#define PMC_IMPL_FMON_LOAD_DATA_STATUS_1_OSCnFUSE_CK_0_WORD_COUNT                       0x1
#define PMC_IMPL_FMON_LOAD_DATA_STATUS_1_OSCnFUSE_CK_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define PMC_IMPL_FMON_LOAD_DATA_STATUS_1_OSCnFUSE_CK_0_RESET_MASK                       MK_MASK_CONST(0x7)
#define PMC_IMPL_FMON_LOAD_DATA_STATUS_1_OSCnFUSE_CK_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define PMC_IMPL_FMON_LOAD_DATA_STATUS_1_OSCnFUSE_CK_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define PMC_IMPL_FMON_LOAD_DATA_STATUS_1_OSCnFUSE_CK_0_READ_MASK                        MK_MASK_CONST(0x7)
#define PMC_IMPL_FMON_LOAD_DATA_STATUS_1_OSCnFUSE_CK_0_WRITE_MASK                       MK_MASK_CONST(0x0)
// Return data selected status. Load data sel field should match this status if read.
#define PMC_IMPL_FMON_LOAD_DATA_STATUS_1_OSCnFUSE_CK_0_FMON_LOAD_DATA_SEL_STATUS_OSCnFUSE_CK_SHIFT                      MK_SHIFT_CONST(0)
#define PMC_IMPL_FMON_LOAD_DATA_STATUS_1_OSCnFUSE_CK_0_FMON_LOAD_DATA_SEL_STATUS_OSCnFUSE_CK_FIELD                      MK_FIELD_CONST(0x7, PMC_IMPL_FMON_LOAD_DATA_STATUS_1_OSCnFUSE_CK_0_FMON_LOAD_DATA_SEL_STATUS_OSCnFUSE_CK_SHIFT)
#define PMC_IMPL_FMON_LOAD_DATA_STATUS_1_OSCnFUSE_CK_0_FMON_LOAD_DATA_SEL_STATUS_OSCnFUSE_CK_RANGE                      2:0
#define PMC_IMPL_FMON_LOAD_DATA_STATUS_1_OSCnFUSE_CK_0_FMON_LOAD_DATA_SEL_STATUS_OSCnFUSE_CK_MSB                        MK_SHIFT_CONST(2)
#define PMC_IMPL_FMON_LOAD_DATA_STATUS_1_OSCnFUSE_CK_0_FMON_LOAD_DATA_SEL_STATUS_OSCnFUSE_CK_LSB                        MK_SHIFT_CONST(0)
#define PMC_IMPL_FMON_LOAD_DATA_STATUS_1_OSCnFUSE_CK_0_FMON_LOAD_DATA_SEL_STATUS_OSCnFUSE_CK_WOFFSET                    0x0
#define PMC_IMPL_FMON_LOAD_DATA_STATUS_1_OSCnFUSE_CK_0_FMON_LOAD_DATA_SEL_STATUS_OSCnFUSE_CK_DEFAULT                    MK_MASK_CONST(0x0)
#define PMC_IMPL_FMON_LOAD_DATA_STATUS_1_OSCnFUSE_CK_0_FMON_LOAD_DATA_SEL_STATUS_OSCnFUSE_CK_DEFAULT_MASK                       MK_MASK_CONST(0x7)
#define PMC_IMPL_FMON_LOAD_DATA_STATUS_1_OSCnFUSE_CK_0_FMON_LOAD_DATA_SEL_STATUS_OSCnFUSE_CK_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define PMC_IMPL_FMON_LOAD_DATA_STATUS_1_OSCnFUSE_CK_0_FMON_LOAD_DATA_SEL_STATUS_OSCnFUSE_CK_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define PMC_IMPL_FMON_LOAD_DATA_STATUS_1_OSCnFUSE_CK_0_FMON_LOAD_DATA_SEL_STATUS_OSCnFUSE_CK_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define PMC_IMPL_FMON_LOAD_DATA_STATUS_1_OSCnFUSE_CK_0_FMON_LOAD_DATA_SEL_STATUS_OSCnFUSE_CK_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

//Reset level:l1acoldrst_pmc_pclk_srstn

// Register PMC_IMPL_FMON_LOAD_DATA_STATUS_2_OSCnFUSE_CK_0
#define PMC_IMPL_FMON_LOAD_DATA_STATUS_2_OSCnFUSE_CK_0                  MK_ADDR_CONST(0x890)
#define PMC_IMPL_FMON_LOAD_DATA_STATUS_2_OSCnFUSE_CK_0_SECURE                   0x0
#define PMC_IMPL_FMON_LOAD_DATA_STATUS_2_OSCnFUSE_CK_0_DUAL                     0x0
#define PMC_IMPL_FMON_LOAD_DATA_STATUS_2_OSCnFUSE_CK_0_SCR                      OSCnFUSE_CK_SCR_0
#define PMC_IMPL_FMON_LOAD_DATA_STATUS_2_OSCnFUSE_CK_0_SCRREG                   PMC_IMPL_SCR_OSCnFUSE_CK_SCR_0
#define PMC_IMPL_FMON_LOAD_DATA_STATUS_2_OSCnFUSE_CK_0_WORD_COUNT                       0x1
#define PMC_IMPL_FMON_LOAD_DATA_STATUS_2_OSCnFUSE_CK_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define PMC_IMPL_FMON_LOAD_DATA_STATUS_2_OSCnFUSE_CK_0_RESET_MASK                       MK_MASK_CONST(0xffffffff)
#define PMC_IMPL_FMON_LOAD_DATA_STATUS_2_OSCnFUSE_CK_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define PMC_IMPL_FMON_LOAD_DATA_STATUS_2_OSCnFUSE_CK_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define PMC_IMPL_FMON_LOAD_DATA_STATUS_2_OSCnFUSE_CK_0_READ_MASK                        MK_MASK_CONST(0xffffffff)
#define PMC_IMPL_FMON_LOAD_DATA_STATUS_2_OSCnFUSE_CK_0_WRITE_MASK                       MK_MASK_CONST(0x0)
// Return data value
#define PMC_IMPL_FMON_LOAD_DATA_STATUS_2_OSCnFUSE_CK_0_FMON_LOAD_DATA_VAL_OSCnFUSE_CK_SHIFT                     MK_SHIFT_CONST(0)
#define PMC_IMPL_FMON_LOAD_DATA_STATUS_2_OSCnFUSE_CK_0_FMON_LOAD_DATA_VAL_OSCnFUSE_CK_FIELD                     MK_FIELD_CONST(0xffffffff, PMC_IMPL_FMON_LOAD_DATA_STATUS_2_OSCnFUSE_CK_0_FMON_LOAD_DATA_VAL_OSCnFUSE_CK_SHIFT)
#define PMC_IMPL_FMON_LOAD_DATA_STATUS_2_OSCnFUSE_CK_0_FMON_LOAD_DATA_VAL_OSCnFUSE_CK_RANGE                     31:0
#define PMC_IMPL_FMON_LOAD_DATA_STATUS_2_OSCnFUSE_CK_0_FMON_LOAD_DATA_VAL_OSCnFUSE_CK_MSB                       MK_SHIFT_CONST(31)
#define PMC_IMPL_FMON_LOAD_DATA_STATUS_2_OSCnFUSE_CK_0_FMON_LOAD_DATA_VAL_OSCnFUSE_CK_LSB                       MK_SHIFT_CONST(0)
#define PMC_IMPL_FMON_LOAD_DATA_STATUS_2_OSCnFUSE_CK_0_FMON_LOAD_DATA_VAL_OSCnFUSE_CK_WOFFSET                   0x0
#define PMC_IMPL_FMON_LOAD_DATA_STATUS_2_OSCnFUSE_CK_0_FMON_LOAD_DATA_VAL_OSCnFUSE_CK_DEFAULT                   MK_MASK_CONST(0x0)
#define PMC_IMPL_FMON_LOAD_DATA_STATUS_2_OSCnFUSE_CK_0_FMON_LOAD_DATA_VAL_OSCnFUSE_CK_DEFAULT_MASK                      MK_MASK_CONST(0xffffffff)
#define PMC_IMPL_FMON_LOAD_DATA_STATUS_2_OSCnFUSE_CK_0_FMON_LOAD_DATA_VAL_OSCnFUSE_CK_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define PMC_IMPL_FMON_LOAD_DATA_STATUS_2_OSCnFUSE_CK_0_FMON_LOAD_DATA_VAL_OSCnFUSE_CK_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define PMC_IMPL_FMON_LOAD_DATA_STATUS_2_OSCnFUSE_CK_0_FMON_LOAD_DATA_VAL_OSCnFUSE_CK_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define PMC_IMPL_FMON_LOAD_DATA_STATUS_2_OSCnFUSE_CK_0_FMON_LOAD_DATA_VAL_OSCnFUSE_CK_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

//Reset level:l1acoldrst_pmc_pclk_srstn

// Register PMC_IMPL_FMON_CLEAR_COUNTER_OSCnFUSE_CK_0
#define PMC_IMPL_FMON_CLEAR_COUNTER_OSCnFUSE_CK_0                       MK_ADDR_CONST(0x894)
#define PMC_IMPL_FMON_CLEAR_COUNTER_OSCnFUSE_CK_0_SECURE                        0x0
#define PMC_IMPL_FMON_CLEAR_COUNTER_OSCnFUSE_CK_0_DUAL                  0x0
#define PMC_IMPL_FMON_CLEAR_COUNTER_OSCnFUSE_CK_0_SCR                   OSCnFUSE_CK_SCR_0
#define PMC_IMPL_FMON_CLEAR_COUNTER_OSCnFUSE_CK_0_SCRREG                        PMC_IMPL_SCR_OSCnFUSE_CK_SCR_0
#define PMC_IMPL_FMON_CLEAR_COUNTER_OSCnFUSE_CK_0_WORD_COUNT                    0x1
#define PMC_IMPL_FMON_CLEAR_COUNTER_OSCnFUSE_CK_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define PMC_IMPL_FMON_CLEAR_COUNTER_OSCnFUSE_CK_0_RESET_MASK                    MK_MASK_CONST(0xf)
#define PMC_IMPL_FMON_CLEAR_COUNTER_OSCnFUSE_CK_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define PMC_IMPL_FMON_CLEAR_COUNTER_OSCnFUSE_CK_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define PMC_IMPL_FMON_CLEAR_COUNTER_OSCnFUSE_CK_0_READ_MASK                     MK_MASK_CONST(0xf)
#define PMC_IMPL_FMON_CLEAR_COUNTER_OSCnFUSE_CK_0_WRITE_MASK                    MK_MASK_CONST(0xf)
// When set, the Min, Max, Count[4:0] sampling is stopped
#define PMC_IMPL_FMON_CLEAR_COUNTER_OSCnFUSE_CK_0_FMON_HOLD_COUNT_SAMPLES_OSCnFUSE_CK_SHIFT                     MK_SHIFT_CONST(3)
#define PMC_IMPL_FMON_CLEAR_COUNTER_OSCnFUSE_CK_0_FMON_HOLD_COUNT_SAMPLES_OSCnFUSE_CK_FIELD                     MK_FIELD_CONST(0x1, PMC_IMPL_FMON_CLEAR_COUNTER_OSCnFUSE_CK_0_FMON_HOLD_COUNT_SAMPLES_OSCnFUSE_CK_SHIFT)
#define PMC_IMPL_FMON_CLEAR_COUNTER_OSCnFUSE_CK_0_FMON_HOLD_COUNT_SAMPLES_OSCnFUSE_CK_RANGE                     3:3
#define PMC_IMPL_FMON_CLEAR_COUNTER_OSCnFUSE_CK_0_FMON_HOLD_COUNT_SAMPLES_OSCnFUSE_CK_MSB                       MK_SHIFT_CONST(3)
#define PMC_IMPL_FMON_CLEAR_COUNTER_OSCnFUSE_CK_0_FMON_HOLD_COUNT_SAMPLES_OSCnFUSE_CK_LSB                       MK_SHIFT_CONST(3)
#define PMC_IMPL_FMON_CLEAR_COUNTER_OSCnFUSE_CK_0_FMON_HOLD_COUNT_SAMPLES_OSCnFUSE_CK_WOFFSET                   0x0
#define PMC_IMPL_FMON_CLEAR_COUNTER_OSCnFUSE_CK_0_FMON_HOLD_COUNT_SAMPLES_OSCnFUSE_CK_DEFAULT                   MK_MASK_CONST(0x0)
#define PMC_IMPL_FMON_CLEAR_COUNTER_OSCnFUSE_CK_0_FMON_HOLD_COUNT_SAMPLES_OSCnFUSE_CK_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define PMC_IMPL_FMON_CLEAR_COUNTER_OSCnFUSE_CK_0_FMON_HOLD_COUNT_SAMPLES_OSCnFUSE_CK_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define PMC_IMPL_FMON_CLEAR_COUNTER_OSCnFUSE_CK_0_FMON_HOLD_COUNT_SAMPLES_OSCnFUSE_CK_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define PMC_IMPL_FMON_CLEAR_COUNTER_OSCnFUSE_CK_0_FMON_HOLD_COUNT_SAMPLES_OSCnFUSE_CK_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define PMC_IMPL_FMON_CLEAR_COUNTER_OSCnFUSE_CK_0_FMON_HOLD_COUNT_SAMPLES_OSCnFUSE_CK_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

// S/W clear for FMON counter. S/W is expected to write 1 to clear counter (and then write 0).
#define PMC_IMPL_FMON_CLEAR_COUNTER_OSCnFUSE_CK_0_FMON_CLEAR_FMON_COUNTER_OSCnFUSE_CK_SHIFT                     MK_SHIFT_CONST(2)
#define PMC_IMPL_FMON_CLEAR_COUNTER_OSCnFUSE_CK_0_FMON_CLEAR_FMON_COUNTER_OSCnFUSE_CK_FIELD                     MK_FIELD_CONST(0x1, PMC_IMPL_FMON_CLEAR_COUNTER_OSCnFUSE_CK_0_FMON_CLEAR_FMON_COUNTER_OSCnFUSE_CK_SHIFT)
#define PMC_IMPL_FMON_CLEAR_COUNTER_OSCnFUSE_CK_0_FMON_CLEAR_FMON_COUNTER_OSCnFUSE_CK_RANGE                     2:2
#define PMC_IMPL_FMON_CLEAR_COUNTER_OSCnFUSE_CK_0_FMON_CLEAR_FMON_COUNTER_OSCnFUSE_CK_MSB                       MK_SHIFT_CONST(2)
#define PMC_IMPL_FMON_CLEAR_COUNTER_OSCnFUSE_CK_0_FMON_CLEAR_FMON_COUNTER_OSCnFUSE_CK_LSB                       MK_SHIFT_CONST(2)
#define PMC_IMPL_FMON_CLEAR_COUNTER_OSCnFUSE_CK_0_FMON_CLEAR_FMON_COUNTER_OSCnFUSE_CK_WOFFSET                   0x0
#define PMC_IMPL_FMON_CLEAR_COUNTER_OSCnFUSE_CK_0_FMON_CLEAR_FMON_COUNTER_OSCnFUSE_CK_DEFAULT                   MK_MASK_CONST(0x0)
#define PMC_IMPL_FMON_CLEAR_COUNTER_OSCnFUSE_CK_0_FMON_CLEAR_FMON_COUNTER_OSCnFUSE_CK_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define PMC_IMPL_FMON_CLEAR_COUNTER_OSCnFUSE_CK_0_FMON_CLEAR_FMON_COUNTER_OSCnFUSE_CK_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define PMC_IMPL_FMON_CLEAR_COUNTER_OSCnFUSE_CK_0_FMON_CLEAR_FMON_COUNTER_OSCnFUSE_CK_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define PMC_IMPL_FMON_CLEAR_COUNTER_OSCnFUSE_CK_0_FMON_CLEAR_FMON_COUNTER_OSCnFUSE_CK_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define PMC_IMPL_FMON_CLEAR_COUNTER_OSCnFUSE_CK_0_FMON_CLEAR_FMON_COUNTER_OSCnFUSE_CK_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

// When set, min max counter values are not cleared when we assert fmon_clear_fmon_counter
#define PMC_IMPL_FMON_CLEAR_COUNTER_OSCnFUSE_CK_0_FMON_MASK_MIN_MAX_COUNT_CLEAR_OSCnFUSE_CK_SHIFT                       MK_SHIFT_CONST(1)
#define PMC_IMPL_FMON_CLEAR_COUNTER_OSCnFUSE_CK_0_FMON_MASK_MIN_MAX_COUNT_CLEAR_OSCnFUSE_CK_FIELD                       MK_FIELD_CONST(0x1, PMC_IMPL_FMON_CLEAR_COUNTER_OSCnFUSE_CK_0_FMON_MASK_MIN_MAX_COUNT_CLEAR_OSCnFUSE_CK_SHIFT)
#define PMC_IMPL_FMON_CLEAR_COUNTER_OSCnFUSE_CK_0_FMON_MASK_MIN_MAX_COUNT_CLEAR_OSCnFUSE_CK_RANGE                       1:1
#define PMC_IMPL_FMON_CLEAR_COUNTER_OSCnFUSE_CK_0_FMON_MASK_MIN_MAX_COUNT_CLEAR_OSCnFUSE_CK_MSB                 MK_SHIFT_CONST(1)
#define PMC_IMPL_FMON_CLEAR_COUNTER_OSCnFUSE_CK_0_FMON_MASK_MIN_MAX_COUNT_CLEAR_OSCnFUSE_CK_LSB                 MK_SHIFT_CONST(1)
#define PMC_IMPL_FMON_CLEAR_COUNTER_OSCnFUSE_CK_0_FMON_MASK_MIN_MAX_COUNT_CLEAR_OSCnFUSE_CK_WOFFSET                     0x0
#define PMC_IMPL_FMON_CLEAR_COUNTER_OSCnFUSE_CK_0_FMON_MASK_MIN_MAX_COUNT_CLEAR_OSCnFUSE_CK_DEFAULT                     MK_MASK_CONST(0x0)
#define PMC_IMPL_FMON_CLEAR_COUNTER_OSCnFUSE_CK_0_FMON_MASK_MIN_MAX_COUNT_CLEAR_OSCnFUSE_CK_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define PMC_IMPL_FMON_CLEAR_COUNTER_OSCnFUSE_CK_0_FMON_MASK_MIN_MAX_COUNT_CLEAR_OSCnFUSE_CK_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define PMC_IMPL_FMON_CLEAR_COUNTER_OSCnFUSE_CK_0_FMON_MASK_MIN_MAX_COUNT_CLEAR_OSCnFUSE_CK_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define PMC_IMPL_FMON_CLEAR_COUNTER_OSCnFUSE_CK_0_FMON_MASK_MIN_MAX_COUNT_CLEAR_OSCnFUSE_CK_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define PMC_IMPL_FMON_CLEAR_COUNTER_OSCnFUSE_CK_0_FMON_MASK_MIN_MAX_COUNT_CLEAR_OSCnFUSE_CK_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

// Clear Min, Max, Count[4:0] samples
#define PMC_IMPL_FMON_CLEAR_COUNTER_OSCnFUSE_CK_0_FMON_MIN_MAX_LASTN_COUNT_CLEAR_OSCnFUSE_CK_SHIFT                      MK_SHIFT_CONST(0)
#define PMC_IMPL_FMON_CLEAR_COUNTER_OSCnFUSE_CK_0_FMON_MIN_MAX_LASTN_COUNT_CLEAR_OSCnFUSE_CK_FIELD                      MK_FIELD_CONST(0x1, PMC_IMPL_FMON_CLEAR_COUNTER_OSCnFUSE_CK_0_FMON_MIN_MAX_LASTN_COUNT_CLEAR_OSCnFUSE_CK_SHIFT)
#define PMC_IMPL_FMON_CLEAR_COUNTER_OSCnFUSE_CK_0_FMON_MIN_MAX_LASTN_COUNT_CLEAR_OSCnFUSE_CK_RANGE                      0:0
#define PMC_IMPL_FMON_CLEAR_COUNTER_OSCnFUSE_CK_0_FMON_MIN_MAX_LASTN_COUNT_CLEAR_OSCnFUSE_CK_MSB                        MK_SHIFT_CONST(0)
#define PMC_IMPL_FMON_CLEAR_COUNTER_OSCnFUSE_CK_0_FMON_MIN_MAX_LASTN_COUNT_CLEAR_OSCnFUSE_CK_LSB                        MK_SHIFT_CONST(0)
#define PMC_IMPL_FMON_CLEAR_COUNTER_OSCnFUSE_CK_0_FMON_MIN_MAX_LASTN_COUNT_CLEAR_OSCnFUSE_CK_WOFFSET                    0x0
#define PMC_IMPL_FMON_CLEAR_COUNTER_OSCnFUSE_CK_0_FMON_MIN_MAX_LASTN_COUNT_CLEAR_OSCnFUSE_CK_DEFAULT                    MK_MASK_CONST(0x0)
#define PMC_IMPL_FMON_CLEAR_COUNTER_OSCnFUSE_CK_0_FMON_MIN_MAX_LASTN_COUNT_CLEAR_OSCnFUSE_CK_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define PMC_IMPL_FMON_CLEAR_COUNTER_OSCnFUSE_CK_0_FMON_MIN_MAX_LASTN_COUNT_CLEAR_OSCnFUSE_CK_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define PMC_IMPL_FMON_CLEAR_COUNTER_OSCnFUSE_CK_0_FMON_MIN_MAX_LASTN_COUNT_CLEAR_OSCnFUSE_CK_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define PMC_IMPL_FMON_CLEAR_COUNTER_OSCnFUSE_CK_0_FMON_MIN_MAX_LASTN_COUNT_CLEAR_OSCnFUSE_CK_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define PMC_IMPL_FMON_CLEAR_COUNTER_OSCnFUSE_CK_0_FMON_MIN_MAX_LASTN_COUNT_CLEAR_OSCnFUSE_CK_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

//Reset level:l1acoldrst_pmc_pclk_srstn

// Register PMC_IMPL_FMON_DEBUG_CONFIG_OSCnFUSE_CK_0
#define PMC_IMPL_FMON_DEBUG_CONFIG_OSCnFUSE_CK_0                        MK_ADDR_CONST(0x898)
#define PMC_IMPL_FMON_DEBUG_CONFIG_OSCnFUSE_CK_0_SECURE                         0x0
#define PMC_IMPL_FMON_DEBUG_CONFIG_OSCnFUSE_CK_0_DUAL                   0x0
#define PMC_IMPL_FMON_DEBUG_CONFIG_OSCnFUSE_CK_0_SCR                    OSCnFUSE_CK_SCR_0
#define PMC_IMPL_FMON_DEBUG_CONFIG_OSCnFUSE_CK_0_SCRREG                         PMC_IMPL_SCR_OSCnFUSE_CK_SCR_0
#define PMC_IMPL_FMON_DEBUG_CONFIG_OSCnFUSE_CK_0_WORD_COUNT                     0x1
#define PMC_IMPL_FMON_DEBUG_CONFIG_OSCnFUSE_CK_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define PMC_IMPL_FMON_DEBUG_CONFIG_OSCnFUSE_CK_0_RESET_MASK                     MK_MASK_CONST(0x3)
#define PMC_IMPL_FMON_DEBUG_CONFIG_OSCnFUSE_CK_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define PMC_IMPL_FMON_DEBUG_CONFIG_OSCnFUSE_CK_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define PMC_IMPL_FMON_DEBUG_CONFIG_OSCnFUSE_CK_0_READ_MASK                      MK_MASK_CONST(0x3)
#define PMC_IMPL_FMON_DEBUG_CONFIG_OSCnFUSE_CK_0_WRITE_MASK                     MK_MASK_CONST(0x1)
// Status : Read reference window
#define PMC_IMPL_FMON_DEBUG_CONFIG_OSCnFUSE_CK_0_FMON_REF_WINDOW_OSCnFUSE_CK_SHIFT                      MK_SHIFT_CONST(1)
#define PMC_IMPL_FMON_DEBUG_CONFIG_OSCnFUSE_CK_0_FMON_REF_WINDOW_OSCnFUSE_CK_FIELD                      MK_FIELD_CONST(0x1, PMC_IMPL_FMON_DEBUG_CONFIG_OSCnFUSE_CK_0_FMON_REF_WINDOW_OSCnFUSE_CK_SHIFT)
#define PMC_IMPL_FMON_DEBUG_CONFIG_OSCnFUSE_CK_0_FMON_REF_WINDOW_OSCnFUSE_CK_RANGE                      1:1
#define PMC_IMPL_FMON_DEBUG_CONFIG_OSCnFUSE_CK_0_FMON_REF_WINDOW_OSCnFUSE_CK_MSB                        MK_SHIFT_CONST(1)
#define PMC_IMPL_FMON_DEBUG_CONFIG_OSCnFUSE_CK_0_FMON_REF_WINDOW_OSCnFUSE_CK_LSB                        MK_SHIFT_CONST(1)
#define PMC_IMPL_FMON_DEBUG_CONFIG_OSCnFUSE_CK_0_FMON_REF_WINDOW_OSCnFUSE_CK_WOFFSET                    0x0
#define PMC_IMPL_FMON_DEBUG_CONFIG_OSCnFUSE_CK_0_FMON_REF_WINDOW_OSCnFUSE_CK_DEFAULT                    MK_MASK_CONST(0x0)
#define PMC_IMPL_FMON_DEBUG_CONFIG_OSCnFUSE_CK_0_FMON_REF_WINDOW_OSCnFUSE_CK_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define PMC_IMPL_FMON_DEBUG_CONFIG_OSCnFUSE_CK_0_FMON_REF_WINDOW_OSCnFUSE_CK_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define PMC_IMPL_FMON_DEBUG_CONFIG_OSCnFUSE_CK_0_FMON_REF_WINDOW_OSCnFUSE_CK_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define PMC_IMPL_FMON_DEBUG_CONFIG_OSCnFUSE_CK_0_FMON_REF_WINDOW_OSCnFUSE_CK_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define PMC_IMPL_FMON_DEBUG_CONFIG_OSCnFUSE_CK_0_FMON_REF_WINDOW_OSCnFUSE_CK_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

// Enable debug. Enables clock divider and gates output to DFD logic when not enabled
#define PMC_IMPL_FMON_DEBUG_CONFIG_OSCnFUSE_CK_0_FMON_ENABLE_DEBUG_OSCnFUSE_CK_SHIFT                    MK_SHIFT_CONST(0)
#define PMC_IMPL_FMON_DEBUG_CONFIG_OSCnFUSE_CK_0_FMON_ENABLE_DEBUG_OSCnFUSE_CK_FIELD                    MK_FIELD_CONST(0x1, PMC_IMPL_FMON_DEBUG_CONFIG_OSCnFUSE_CK_0_FMON_ENABLE_DEBUG_OSCnFUSE_CK_SHIFT)
#define PMC_IMPL_FMON_DEBUG_CONFIG_OSCnFUSE_CK_0_FMON_ENABLE_DEBUG_OSCnFUSE_CK_RANGE                    0:0
#define PMC_IMPL_FMON_DEBUG_CONFIG_OSCnFUSE_CK_0_FMON_ENABLE_DEBUG_OSCnFUSE_CK_MSB                      MK_SHIFT_CONST(0)
#define PMC_IMPL_FMON_DEBUG_CONFIG_OSCnFUSE_CK_0_FMON_ENABLE_DEBUG_OSCnFUSE_CK_LSB                      MK_SHIFT_CONST(0)
#define PMC_IMPL_FMON_DEBUG_CONFIG_OSCnFUSE_CK_0_FMON_ENABLE_DEBUG_OSCnFUSE_CK_WOFFSET                  0x0
#define PMC_IMPL_FMON_DEBUG_CONFIG_OSCnFUSE_CK_0_FMON_ENABLE_DEBUG_OSCnFUSE_CK_DEFAULT                  MK_MASK_CONST(0x0)
#define PMC_IMPL_FMON_DEBUG_CONFIG_OSCnFUSE_CK_0_FMON_ENABLE_DEBUG_OSCnFUSE_CK_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define PMC_IMPL_FMON_DEBUG_CONFIG_OSCnFUSE_CK_0_FMON_ENABLE_DEBUG_OSCnFUSE_CK_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define PMC_IMPL_FMON_DEBUG_CONFIG_OSCnFUSE_CK_0_FMON_ENABLE_DEBUG_OSCnFUSE_CK_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define PMC_IMPL_FMON_DEBUG_CONFIG_OSCnFUSE_CK_0_FMON_ENABLE_DEBUG_OSCnFUSE_CK_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define PMC_IMPL_FMON_DEBUG_CONFIG_OSCnFUSE_CK_0_FMON_ENABLE_DEBUG_OSCnFUSE_CK_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define PMC_IMPL_FMON_DEBUG_CONFIG_OSCnFUSE_CK_0_FMON_ENABLE_DEBUG_OSCnFUSE_CK_INIT_ENUM                        DISABLE
#define PMC_IMPL_FMON_DEBUG_CONFIG_OSCnFUSE_CK_0_FMON_ENABLE_DEBUG_OSCnFUSE_CK_DISABLE                  MK_ENUM_CONST(0)
#define PMC_IMPL_FMON_DEBUG_CONFIG_OSCnFUSE_CK_0_FMON_ENABLE_DEBUG_OSCnFUSE_CK_ENABLE                   MK_ENUM_CONST(1)

//Optional Register based on define USE_CNTR_OVERFLOW_DC_RSTREQ
//Reset level:l1acoldrst_pmc_pclk_srstn

// Register PMC_IMPL_FMON_CNTR_OVERFLOW_CTRL_OSCnFUSE_CK_0
#define PMC_IMPL_FMON_CNTR_OVERFLOW_CTRL_OSCnFUSE_CK_0                  MK_ADDR_CONST(0x89c)
#define PMC_IMPL_FMON_CNTR_OVERFLOW_CTRL_OSCnFUSE_CK_0_SECURE                   0x0
#define PMC_IMPL_FMON_CNTR_OVERFLOW_CTRL_OSCnFUSE_CK_0_DUAL                     0x0
#define PMC_IMPL_FMON_CNTR_OVERFLOW_CTRL_OSCnFUSE_CK_0_SCR                      OSCnFUSE_CK_SCR_0
#define PMC_IMPL_FMON_CNTR_OVERFLOW_CTRL_OSCnFUSE_CK_0_SCRREG                   PMC_IMPL_SCR_OSCnFUSE_CK_SCR_0
#define PMC_IMPL_FMON_CNTR_OVERFLOW_CTRL_OSCnFUSE_CK_0_WORD_COUNT                       0x1
#define PMC_IMPL_FMON_CNTR_OVERFLOW_CTRL_OSCnFUSE_CK_0_RESET_VAL                        MK_MASK_CONST(0x8000000b)
#define PMC_IMPL_FMON_CNTR_OVERFLOW_CTRL_OSCnFUSE_CK_0_RESET_MASK                       MK_MASK_CONST(0x8000001f)
#define PMC_IMPL_FMON_CNTR_OVERFLOW_CTRL_OSCnFUSE_CK_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define PMC_IMPL_FMON_CNTR_OVERFLOW_CTRL_OSCnFUSE_CK_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define PMC_IMPL_FMON_CNTR_OVERFLOW_CTRL_OSCnFUSE_CK_0_READ_MASK                        MK_MASK_CONST(0x8000001f)
#define PMC_IMPL_FMON_CNTR_OVERFLOW_CTRL_OSCnFUSE_CK_0_WRITE_MASK                       MK_MASK_CONST(0x8000001f)
// Select HS counter bits to generate overflow error
#define PMC_IMPL_FMON_CNTR_OVERFLOW_CTRL_OSCnFUSE_CK_0_FMON_OVERFLOW_BIT_SEL_OSCnFUSE_CK_SHIFT                  MK_SHIFT_CONST(0)
#define PMC_IMPL_FMON_CNTR_OVERFLOW_CTRL_OSCnFUSE_CK_0_FMON_OVERFLOW_BIT_SEL_OSCnFUSE_CK_FIELD                  MK_FIELD_CONST(0x1f, PMC_IMPL_FMON_CNTR_OVERFLOW_CTRL_OSCnFUSE_CK_0_FMON_OVERFLOW_BIT_SEL_OSCnFUSE_CK_SHIFT)
#define PMC_IMPL_FMON_CNTR_OVERFLOW_CTRL_OSCnFUSE_CK_0_FMON_OVERFLOW_BIT_SEL_OSCnFUSE_CK_RANGE                  4:0
#define PMC_IMPL_FMON_CNTR_OVERFLOW_CTRL_OSCnFUSE_CK_0_FMON_OVERFLOW_BIT_SEL_OSCnFUSE_CK_MSB                    MK_SHIFT_CONST(4)
#define PMC_IMPL_FMON_CNTR_OVERFLOW_CTRL_OSCnFUSE_CK_0_FMON_OVERFLOW_BIT_SEL_OSCnFUSE_CK_LSB                    MK_SHIFT_CONST(0)
#define PMC_IMPL_FMON_CNTR_OVERFLOW_CTRL_OSCnFUSE_CK_0_FMON_OVERFLOW_BIT_SEL_OSCnFUSE_CK_WOFFSET                        0x0
#define PMC_IMPL_FMON_CNTR_OVERFLOW_CTRL_OSCnFUSE_CK_0_FMON_OVERFLOW_BIT_SEL_OSCnFUSE_CK_DEFAULT                        MK_MASK_CONST(0xb)
#define PMC_IMPL_FMON_CNTR_OVERFLOW_CTRL_OSCnFUSE_CK_0_FMON_OVERFLOW_BIT_SEL_OSCnFUSE_CK_DEFAULT_MASK                   MK_MASK_CONST(0x1f)
#define PMC_IMPL_FMON_CNTR_OVERFLOW_CTRL_OSCnFUSE_CK_0_FMON_OVERFLOW_BIT_SEL_OSCnFUSE_CK_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define PMC_IMPL_FMON_CNTR_OVERFLOW_CTRL_OSCnFUSE_CK_0_FMON_OVERFLOW_BIT_SEL_OSCnFUSE_CK_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define PMC_IMPL_FMON_CNTR_OVERFLOW_CTRL_OSCnFUSE_CK_0_FMON_OVERFLOW_BIT_SEL_OSCnFUSE_CK_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define PMC_IMPL_FMON_CNTR_OVERFLOW_CTRL_OSCnFUSE_CK_0_FMON_OVERFLOW_BIT_SEL_OSCnFUSE_CK_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

// Use the bit to select overflow error as DC fault for reset req generation
#define PMC_IMPL_FMON_CNTR_OVERFLOW_CTRL_OSCnFUSE_CK_0_USE_CNTR_OVERFLOW_DC_FAULT_OSCnFUSE_CK_SHIFT                     MK_SHIFT_CONST(31)
#define PMC_IMPL_FMON_CNTR_OVERFLOW_CTRL_OSCnFUSE_CK_0_USE_CNTR_OVERFLOW_DC_FAULT_OSCnFUSE_CK_FIELD                     MK_FIELD_CONST(0x1, PMC_IMPL_FMON_CNTR_OVERFLOW_CTRL_OSCnFUSE_CK_0_USE_CNTR_OVERFLOW_DC_FAULT_OSCnFUSE_CK_SHIFT)
#define PMC_IMPL_FMON_CNTR_OVERFLOW_CTRL_OSCnFUSE_CK_0_USE_CNTR_OVERFLOW_DC_FAULT_OSCnFUSE_CK_RANGE                     31:31
#define PMC_IMPL_FMON_CNTR_OVERFLOW_CTRL_OSCnFUSE_CK_0_USE_CNTR_OVERFLOW_DC_FAULT_OSCnFUSE_CK_MSB                       MK_SHIFT_CONST(31)
#define PMC_IMPL_FMON_CNTR_OVERFLOW_CTRL_OSCnFUSE_CK_0_USE_CNTR_OVERFLOW_DC_FAULT_OSCnFUSE_CK_LSB                       MK_SHIFT_CONST(31)
#define PMC_IMPL_FMON_CNTR_OVERFLOW_CTRL_OSCnFUSE_CK_0_USE_CNTR_OVERFLOW_DC_FAULT_OSCnFUSE_CK_WOFFSET                   0x0
#define PMC_IMPL_FMON_CNTR_OVERFLOW_CTRL_OSCnFUSE_CK_0_USE_CNTR_OVERFLOW_DC_FAULT_OSCnFUSE_CK_DEFAULT                   MK_MASK_CONST(0x1)
#define PMC_IMPL_FMON_CNTR_OVERFLOW_CTRL_OSCnFUSE_CK_0_USE_CNTR_OVERFLOW_DC_FAULT_OSCnFUSE_CK_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define PMC_IMPL_FMON_CNTR_OVERFLOW_CTRL_OSCnFUSE_CK_0_USE_CNTR_OVERFLOW_DC_FAULT_OSCnFUSE_CK_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define PMC_IMPL_FMON_CNTR_OVERFLOW_CTRL_OSCnFUSE_CK_0_USE_CNTR_OVERFLOW_DC_FAULT_OSCnFUSE_CK_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define PMC_IMPL_FMON_CNTR_OVERFLOW_CTRL_OSCnFUSE_CK_0_USE_CNTR_OVERFLOW_DC_FAULT_OSCnFUSE_CK_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define PMC_IMPL_FMON_CNTR_OVERFLOW_CTRL_OSCnFUSE_CK_0_USE_CNTR_OVERFLOW_DC_FAULT_OSCnFUSE_CK_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define PMC_IMPL_FMON_CNTR_OVERFLOW_CTRL_OSCnFUSE_CK_0_USE_CNTR_OVERFLOW_DC_FAULT_OSCnFUSE_CK_INIT_ENUM                 ENABLE
#define PMC_IMPL_FMON_CNTR_OVERFLOW_CTRL_OSCnFUSE_CK_0_USE_CNTR_OVERFLOW_DC_FAULT_OSCnFUSE_CK_DISABLE                   MK_ENUM_CONST(0)
#define PMC_IMPL_FMON_CNTR_OVERFLOW_CTRL_OSCnFUSE_CK_0_USE_CNTR_OVERFLOW_DC_FAULT_OSCnFUSE_CK_ENABLE                    MK_ENUM_CONST(1)


// Reserved address 0x8a0

// Reserved address 0x8a4

// Reserved address 0x8a8

// Reserved address 0x8ac

// Reserved address 0x8b0

// Reserved address 0x8b4

// Reserved address 0x8b8
//Reset level:l0coldrst_pmc_pclk_srstn

// Register PMC_IMPL_RST_REQ_TIMER_0
#define PMC_IMPL_RST_REQ_TIMER_0                        MK_ADDR_CONST(0x8bc)
#define PMC_IMPL_RST_REQ_TIMER_0_SECURE                         0x0
#define PMC_IMPL_RST_REQ_TIMER_0_DUAL                   0x0
#define PMC_IMPL_RST_REQ_TIMER_0_SCR                    CNTRL_SCR_0
#define PMC_IMPL_RST_REQ_TIMER_0_SCRREG                         PMC_IMPL_SCR_CNTRL_SCR_0
#define PMC_IMPL_RST_REQ_TIMER_0_WORD_COUNT                     0x1
#define PMC_IMPL_RST_REQ_TIMER_0_RESET_VAL                      MK_MASK_CONST(0x6)
#define PMC_IMPL_RST_REQ_TIMER_0_RESET_MASK                     MK_MASK_CONST(0xff)
#define PMC_IMPL_RST_REQ_TIMER_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define PMC_IMPL_RST_REQ_TIMER_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define PMC_IMPL_RST_REQ_TIMER_0_READ_MASK                      MK_MASK_CONST(0xff)
#define PMC_IMPL_RST_REQ_TIMER_0_WRITE_MASK                     MK_MASK_CONST(0xff)
// WAIT_CLK_STOP_VAL+1 Number of pmc_clk (32K) cycles to stay in wait CLK_STOP state
#define PMC_IMPL_RST_REQ_TIMER_0_WAIT_CLK_STOP_VAL_SHIFT                        MK_SHIFT_CONST(0)
#define PMC_IMPL_RST_REQ_TIMER_0_WAIT_CLK_STOP_VAL_FIELD                        MK_FIELD_CONST(0xff, PMC_IMPL_RST_REQ_TIMER_0_WAIT_CLK_STOP_VAL_SHIFT)
#define PMC_IMPL_RST_REQ_TIMER_0_WAIT_CLK_STOP_VAL_RANGE                        7:0
#define PMC_IMPL_RST_REQ_TIMER_0_WAIT_CLK_STOP_VAL_MSB                  MK_SHIFT_CONST(7)
#define PMC_IMPL_RST_REQ_TIMER_0_WAIT_CLK_STOP_VAL_LSB                  MK_SHIFT_CONST(0)
#define PMC_IMPL_RST_REQ_TIMER_0_WAIT_CLK_STOP_VAL_WOFFSET                      0x0
#define PMC_IMPL_RST_REQ_TIMER_0_WAIT_CLK_STOP_VAL_DEFAULT                      MK_MASK_CONST(0x6)
#define PMC_IMPL_RST_REQ_TIMER_0_WAIT_CLK_STOP_VAL_DEFAULT_MASK                 MK_MASK_CONST(0xff)
#define PMC_IMPL_RST_REQ_TIMER_0_WAIT_CLK_STOP_VAL_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define PMC_IMPL_RST_REQ_TIMER_0_WAIT_CLK_STOP_VAL_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define PMC_IMPL_RST_REQ_TIMER_0_WAIT_CLK_STOP_VAL_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define PMC_IMPL_RST_REQ_TIMER_0_WAIT_CLK_STOP_VAL_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Reserved address 0x8c0

// Register PMC_IMPL_PMC_RESET_DETECTOR_0
#define PMC_IMPL_PMC_RESET_DETECTOR_0                   MK_ADDR_CONST(0x8c4)
#define PMC_IMPL_PMC_RESET_DETECTOR_0_SECURE                    0x0
#define PMC_IMPL_PMC_RESET_DETECTOR_0_DUAL                      0x0
#define PMC_IMPL_PMC_RESET_DETECTOR_0_SCR                       0
#define PMC_IMPL_PMC_RESET_DETECTOR_0_SCRREG                    0
#define PMC_IMPL_PMC_RESET_DETECTOR_0_WORD_COUNT                        0x1
#define PMC_IMPL_PMC_RESET_DETECTOR_0_RESET_VAL                         MK_MASK_CONST(0x1)
#define PMC_IMPL_PMC_RESET_DETECTOR_0_RESET_MASK                        MK_MASK_CONST(0x1)
#define PMC_IMPL_PMC_RESET_DETECTOR_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define PMC_IMPL_PMC_RESET_DETECTOR_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define PMC_IMPL_PMC_RESET_DETECTOR_0_READ_MASK                         MK_MASK_CONST(0x1)
#define PMC_IMPL_PMC_RESET_DETECTOR_0_WRITE_MASK                        MK_MASK_CONST(0x0)
// if read 1, reset cycling happened after power cycling. if read 0, reset cycling has not happened after power cycling
#define PMC_IMPL_PMC_RESET_DETECTOR_0_pmc2dfd_reset_detector_SHIFT                      MK_SHIFT_CONST(0)
#define PMC_IMPL_PMC_RESET_DETECTOR_0_pmc2dfd_reset_detector_FIELD                      MK_FIELD_CONST(0x1, PMC_IMPL_PMC_RESET_DETECTOR_0_pmc2dfd_reset_detector_SHIFT)
#define PMC_IMPL_PMC_RESET_DETECTOR_0_pmc2dfd_reset_detector_RANGE                      0:0
#define PMC_IMPL_PMC_RESET_DETECTOR_0_pmc2dfd_reset_detector_MSB                        MK_SHIFT_CONST(0)
#define PMC_IMPL_PMC_RESET_DETECTOR_0_pmc2dfd_reset_detector_LSB                        MK_SHIFT_CONST(0)
#define PMC_IMPL_PMC_RESET_DETECTOR_0_pmc2dfd_reset_detector_WOFFSET                    0x0
#define PMC_IMPL_PMC_RESET_DETECTOR_0_pmc2dfd_reset_detector_DEFAULT                    MK_MASK_CONST(0x1)
#define PMC_IMPL_PMC_RESET_DETECTOR_0_pmc2dfd_reset_detector_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define PMC_IMPL_PMC_RESET_DETECTOR_0_pmc2dfd_reset_detector_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define PMC_IMPL_PMC_RESET_DETECTOR_0_pmc2dfd_reset_detector_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define PMC_IMPL_PMC_RESET_DETECTOR_0_pmc2dfd_reset_detector_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define PMC_IMPL_PMC_RESET_DETECTOR_0_pmc2dfd_reset_detector_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define PMC_IMPL_PMC_RESET_DETECTOR_0_pmc2dfd_reset_detector_INIT_ENUM                  DETECTED
#define PMC_IMPL_PMC_RESET_DETECTOR_0_pmc2dfd_reset_detector_DETECTED                   MK_ENUM_CONST(1)
#define PMC_IMPL_PMC_RESET_DETECTOR_0_pmc2dfd_reset_detector_NOT_DETECTED                       MK_ENUM_CONST(0)

//===========================================================
//LED Breathing
//===========================================================

// Register PMC_IMPL_LED_BREATHING_CTRL_0
#define PMC_IMPL_LED_BREATHING_CTRL_0                   MK_ADDR_CONST(0x8c8)
#define PMC_IMPL_LED_BREATHING_CTRL_0_SECURE                    0x0
#define PMC_IMPL_LED_BREATHING_CTRL_0_DUAL                      0x0
#define PMC_IMPL_LED_BREATHING_CTRL_0_SCR                       CNTRL_SCR_0
#define PMC_IMPL_LED_BREATHING_CTRL_0_SCRREG                    PMC_IMPL_SCR_CNTRL_SCR_0
#define PMC_IMPL_LED_BREATHING_CTRL_0_WORD_COUNT                        0x1
#define PMC_IMPL_LED_BREATHING_CTRL_0_RESET_VAL                         MK_MASK_CONST(0x2)
#define PMC_IMPL_LED_BREATHING_CTRL_0_RESET_MASK                        MK_MASK_CONST(0x3)
#define PMC_IMPL_LED_BREATHING_CTRL_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define PMC_IMPL_LED_BREATHING_CTRL_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define PMC_IMPL_LED_BREATHING_CTRL_0_READ_MASK                         MK_MASK_CONST(0x3)
#define PMC_IMPL_LED_BREATHING_CTRL_0_WRITE_MASK                        MK_MASK_CONST(0x3)
// Enable the LED breathing functionality
#define PMC_IMPL_LED_BREATHING_CTRL_0_BREATHING_EN_SHIFT                        MK_SHIFT_CONST(0)
#define PMC_IMPL_LED_BREATHING_CTRL_0_BREATHING_EN_FIELD                        MK_FIELD_CONST(0x1, PMC_IMPL_LED_BREATHING_CTRL_0_BREATHING_EN_SHIFT)
#define PMC_IMPL_LED_BREATHING_CTRL_0_BREATHING_EN_RANGE                        0:0
#define PMC_IMPL_LED_BREATHING_CTRL_0_BREATHING_EN_MSB                  MK_SHIFT_CONST(0)
#define PMC_IMPL_LED_BREATHING_CTRL_0_BREATHING_EN_LSB                  MK_SHIFT_CONST(0)
#define PMC_IMPL_LED_BREATHING_CTRL_0_BREATHING_EN_WOFFSET                      0x0
#define PMC_IMPL_LED_BREATHING_CTRL_0_BREATHING_EN_DEFAULT                      MK_MASK_CONST(0x0)
#define PMC_IMPL_LED_BREATHING_CTRL_0_BREATHING_EN_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define PMC_IMPL_LED_BREATHING_CTRL_0_BREATHING_EN_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define PMC_IMPL_LED_BREATHING_CTRL_0_BREATHING_EN_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define PMC_IMPL_LED_BREATHING_CTRL_0_BREATHING_EN_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define PMC_IMPL_LED_BREATHING_CTRL_0_BREATHING_EN_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

// Enable short low period between 2 cones
#define PMC_IMPL_LED_BREATHING_CTRL_0_SHORT_LOW_PERIOD_EN_SHIFT                 MK_SHIFT_CONST(1)
#define PMC_IMPL_LED_BREATHING_CTRL_0_SHORT_LOW_PERIOD_EN_FIELD                 MK_FIELD_CONST(0x1, PMC_IMPL_LED_BREATHING_CTRL_0_SHORT_LOW_PERIOD_EN_SHIFT)
#define PMC_IMPL_LED_BREATHING_CTRL_0_SHORT_LOW_PERIOD_EN_RANGE                 1:1
#define PMC_IMPL_LED_BREATHING_CTRL_0_SHORT_LOW_PERIOD_EN_MSB                   MK_SHIFT_CONST(1)
#define PMC_IMPL_LED_BREATHING_CTRL_0_SHORT_LOW_PERIOD_EN_LSB                   MK_SHIFT_CONST(1)
#define PMC_IMPL_LED_BREATHING_CTRL_0_SHORT_LOW_PERIOD_EN_WOFFSET                       0x0
#define PMC_IMPL_LED_BREATHING_CTRL_0_SHORT_LOW_PERIOD_EN_DEFAULT                       MK_MASK_CONST(0x1)
#define PMC_IMPL_LED_BREATHING_CTRL_0_SHORT_LOW_PERIOD_EN_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define PMC_IMPL_LED_BREATHING_CTRL_0_SHORT_LOW_PERIOD_EN_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define PMC_IMPL_LED_BREATHING_CTRL_0_SHORT_LOW_PERIOD_EN_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define PMC_IMPL_LED_BREATHING_CTRL_0_SHORT_LOW_PERIOD_EN_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define PMC_IMPL_LED_BREATHING_CTRL_0_SHORT_LOW_PERIOD_EN_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register PMC_IMPL_LED_BREATHING_COUNTER0_0
#define PMC_IMPL_LED_BREATHING_COUNTER0_0                       MK_ADDR_CONST(0x8cc)
#define PMC_IMPL_LED_BREATHING_COUNTER0_0_SECURE                        0x0
#define PMC_IMPL_LED_BREATHING_COUNTER0_0_DUAL                  0x0
#define PMC_IMPL_LED_BREATHING_COUNTER0_0_SCR                   CNTRL_SCR_0
#define PMC_IMPL_LED_BREATHING_COUNTER0_0_SCRREG                        PMC_IMPL_SCR_CNTRL_SCR_0
#define PMC_IMPL_LED_BREATHING_COUNTER0_0_WORD_COUNT                    0x1
#define PMC_IMPL_LED_BREATHING_COUNTER0_0_RESET_VAL                     MK_MASK_CONST(0x4)
#define PMC_IMPL_LED_BREATHING_COUNTER0_0_RESET_MASK                    MK_MASK_CONST(0xffffffff)
#define PMC_IMPL_LED_BREATHING_COUNTER0_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define PMC_IMPL_LED_BREATHING_COUNTER0_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define PMC_IMPL_LED_BREATHING_COUNTER0_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
#define PMC_IMPL_LED_BREATHING_COUNTER0_0_WRITE_MASK                    MK_MASK_CONST(0xffffffff)
// No. of step for ramp-up/down
// 0 - 1step, 1 - 2steps and so on
#define PMC_IMPL_LED_BREATHING_COUNTER0_0_NO_OF_STEPS_SHIFT                     MK_SHIFT_CONST(0)
#define PMC_IMPL_LED_BREATHING_COUNTER0_0_NO_OF_STEPS_FIELD                     MK_FIELD_CONST(0xffffffff, PMC_IMPL_LED_BREATHING_COUNTER0_0_NO_OF_STEPS_SHIFT)
#define PMC_IMPL_LED_BREATHING_COUNTER0_0_NO_OF_STEPS_RANGE                     31:0
#define PMC_IMPL_LED_BREATHING_COUNTER0_0_NO_OF_STEPS_MSB                       MK_SHIFT_CONST(31)
#define PMC_IMPL_LED_BREATHING_COUNTER0_0_NO_OF_STEPS_LSB                       MK_SHIFT_CONST(0)
#define PMC_IMPL_LED_BREATHING_COUNTER0_0_NO_OF_STEPS_WOFFSET                   0x0
#define PMC_IMPL_LED_BREATHING_COUNTER0_0_NO_OF_STEPS_DEFAULT                   MK_MASK_CONST(0x4)
#define PMC_IMPL_LED_BREATHING_COUNTER0_0_NO_OF_STEPS_DEFAULT_MASK                      MK_MASK_CONST(0xffffffff)
#define PMC_IMPL_LED_BREATHING_COUNTER0_0_NO_OF_STEPS_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define PMC_IMPL_LED_BREATHING_COUNTER0_0_NO_OF_STEPS_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define PMC_IMPL_LED_BREATHING_COUNTER0_0_NO_OF_STEPS_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define PMC_IMPL_LED_BREATHING_COUNTER0_0_NO_OF_STEPS_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register PMC_IMPL_LED_BREATHING_COUNTER1_0
#define PMC_IMPL_LED_BREATHING_COUNTER1_0                       MK_ADDR_CONST(0x8d0)
#define PMC_IMPL_LED_BREATHING_COUNTER1_0_SECURE                        0x0
#define PMC_IMPL_LED_BREATHING_COUNTER1_0_DUAL                  0x0
#define PMC_IMPL_LED_BREATHING_COUNTER1_0_SCR                   CNTRL_SCR_0
#define PMC_IMPL_LED_BREATHING_COUNTER1_0_SCRREG                        PMC_IMPL_SCR_CNTRL_SCR_0
#define PMC_IMPL_LED_BREATHING_COUNTER1_0_WORD_COUNT                    0x1
#define PMC_IMPL_LED_BREATHING_COUNTER1_0_RESET_VAL                     MK_MASK_CONST(0x1f)
#define PMC_IMPL_LED_BREATHING_COUNTER1_0_RESET_MASK                    MK_MASK_CONST(0xffffffff)
#define PMC_IMPL_LED_BREATHING_COUNTER1_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define PMC_IMPL_LED_BREATHING_COUNTER1_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define PMC_IMPL_LED_BREATHING_COUNTER1_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
#define PMC_IMPL_LED_BREATHING_COUNTER1_0_WRITE_MASK                    MK_MASK_CONST(0xffffffff)
//
#define PMC_IMPL_LED_BREATHING_COUNTER1_0_PLATEAU_COUNT_SHIFT                   MK_SHIFT_CONST(0)
#define PMC_IMPL_LED_BREATHING_COUNTER1_0_PLATEAU_COUNT_FIELD                   MK_FIELD_CONST(0xffffffff, PMC_IMPL_LED_BREATHING_COUNTER1_0_PLATEAU_COUNT_SHIFT)
#define PMC_IMPL_LED_BREATHING_COUNTER1_0_PLATEAU_COUNT_RANGE                   31:0
#define PMC_IMPL_LED_BREATHING_COUNTER1_0_PLATEAU_COUNT_MSB                     MK_SHIFT_CONST(31)
#define PMC_IMPL_LED_BREATHING_COUNTER1_0_PLATEAU_COUNT_LSB                     MK_SHIFT_CONST(0)
#define PMC_IMPL_LED_BREATHING_COUNTER1_0_PLATEAU_COUNT_WOFFSET                 0x0
#define PMC_IMPL_LED_BREATHING_COUNTER1_0_PLATEAU_COUNT_DEFAULT                 MK_MASK_CONST(0x1f)
#define PMC_IMPL_LED_BREATHING_COUNTER1_0_PLATEAU_COUNT_DEFAULT_MASK                    MK_MASK_CONST(0xffffffff)
#define PMC_IMPL_LED_BREATHING_COUNTER1_0_PLATEAU_COUNT_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define PMC_IMPL_LED_BREATHING_COUNTER1_0_PLATEAU_COUNT_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define PMC_IMPL_LED_BREATHING_COUNTER1_0_PLATEAU_COUNT_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define PMC_IMPL_LED_BREATHING_COUNTER1_0_PLATEAU_COUNT_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register PMC_IMPL_LED_BREATHING_COUNTER2_0
#define PMC_IMPL_LED_BREATHING_COUNTER2_0                       MK_ADDR_CONST(0x8d4)
#define PMC_IMPL_LED_BREATHING_COUNTER2_0_SECURE                        0x0
#define PMC_IMPL_LED_BREATHING_COUNTER2_0_DUAL                  0x0
#define PMC_IMPL_LED_BREATHING_COUNTER2_0_SCR                   CNTRL_SCR_0
#define PMC_IMPL_LED_BREATHING_COUNTER2_0_SCRREG                        PMC_IMPL_SCR_CNTRL_SCR_0
#define PMC_IMPL_LED_BREATHING_COUNTER2_0_WORD_COUNT                    0x1
#define PMC_IMPL_LED_BREATHING_COUNTER2_0_RESET_VAL                     MK_MASK_CONST(0xf)
#define PMC_IMPL_LED_BREATHING_COUNTER2_0_RESET_MASK                    MK_MASK_CONST(0xffffffff)
#define PMC_IMPL_LED_BREATHING_COUNTER2_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define PMC_IMPL_LED_BREATHING_COUNTER2_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define PMC_IMPL_LED_BREATHING_COUNTER2_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
#define PMC_IMPL_LED_BREATHING_COUNTER2_0_WRITE_MASK                    MK_MASK_CONST(0xffffffff)
//
#define PMC_IMPL_LED_BREATHING_COUNTER2_0_SHORT_LOW_PERIOD_COUNT_SHIFT                  MK_SHIFT_CONST(0)
#define PMC_IMPL_LED_BREATHING_COUNTER2_0_SHORT_LOW_PERIOD_COUNT_FIELD                  MK_FIELD_CONST(0xffffffff, PMC_IMPL_LED_BREATHING_COUNTER2_0_SHORT_LOW_PERIOD_COUNT_SHIFT)
#define PMC_IMPL_LED_BREATHING_COUNTER2_0_SHORT_LOW_PERIOD_COUNT_RANGE                  31:0
#define PMC_IMPL_LED_BREATHING_COUNTER2_0_SHORT_LOW_PERIOD_COUNT_MSB                    MK_SHIFT_CONST(31)
#define PMC_IMPL_LED_BREATHING_COUNTER2_0_SHORT_LOW_PERIOD_COUNT_LSB                    MK_SHIFT_CONST(0)
#define PMC_IMPL_LED_BREATHING_COUNTER2_0_SHORT_LOW_PERIOD_COUNT_WOFFSET                        0x0
#define PMC_IMPL_LED_BREATHING_COUNTER2_0_SHORT_LOW_PERIOD_COUNT_DEFAULT                        MK_MASK_CONST(0xf)
#define PMC_IMPL_LED_BREATHING_COUNTER2_0_SHORT_LOW_PERIOD_COUNT_DEFAULT_MASK                   MK_MASK_CONST(0xffffffff)
#define PMC_IMPL_LED_BREATHING_COUNTER2_0_SHORT_LOW_PERIOD_COUNT_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define PMC_IMPL_LED_BREATHING_COUNTER2_0_SHORT_LOW_PERIOD_COUNT_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define PMC_IMPL_LED_BREATHING_COUNTER2_0_SHORT_LOW_PERIOD_COUNT_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define PMC_IMPL_LED_BREATHING_COUNTER2_0_SHORT_LOW_PERIOD_COUNT_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)


// Register PMC_IMPL_LED_BREATHING_COUNTER3_0
#define PMC_IMPL_LED_BREATHING_COUNTER3_0                       MK_ADDR_CONST(0x8d8)
#define PMC_IMPL_LED_BREATHING_COUNTER3_0_SECURE                        0x0
#define PMC_IMPL_LED_BREATHING_COUNTER3_0_DUAL                  0x0
#define PMC_IMPL_LED_BREATHING_COUNTER3_0_SCR                   CNTRL_SCR_0
#define PMC_IMPL_LED_BREATHING_COUNTER3_0_SCRREG                        PMC_IMPL_SCR_CNTRL_SCR_0
#define PMC_IMPL_LED_BREATHING_COUNTER3_0_WORD_COUNT                    0x1
#define PMC_IMPL_LED_BREATHING_COUNTER3_0_RESET_VAL                     MK_MASK_CONST(0x1f)
#define PMC_IMPL_LED_BREATHING_COUNTER3_0_RESET_MASK                    MK_MASK_CONST(0xffffffff)
#define PMC_IMPL_LED_BREATHING_COUNTER3_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define PMC_IMPL_LED_BREATHING_COUNTER3_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define PMC_IMPL_LED_BREATHING_COUNTER3_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
#define PMC_IMPL_LED_BREATHING_COUNTER3_0_WRITE_MASK                    MK_MASK_CONST(0xffffffff)
//
#define PMC_IMPL_LED_BREATHING_COUNTER3_0_LONG_LOW_PERIOD_COUNT_SHIFT                   MK_SHIFT_CONST(0)
#define PMC_IMPL_LED_BREATHING_COUNTER3_0_LONG_LOW_PERIOD_COUNT_FIELD                   MK_FIELD_CONST(0xffffffff, PMC_IMPL_LED_BREATHING_COUNTER3_0_LONG_LOW_PERIOD_COUNT_SHIFT)
#define PMC_IMPL_LED_BREATHING_COUNTER3_0_LONG_LOW_PERIOD_COUNT_RANGE                   31:0
#define PMC_IMPL_LED_BREATHING_COUNTER3_0_LONG_LOW_PERIOD_COUNT_MSB                     MK_SHIFT_CONST(31)
#define PMC_IMPL_LED_BREATHING_COUNTER3_0_LONG_LOW_PERIOD_COUNT_LSB                     MK_SHIFT_CONST(0)
#define PMC_IMPL_LED_BREATHING_COUNTER3_0_LONG_LOW_PERIOD_COUNT_WOFFSET                 0x0
#define PMC_IMPL_LED_BREATHING_COUNTER3_0_LONG_LOW_PERIOD_COUNT_DEFAULT                 MK_MASK_CONST(0x1f)
#define PMC_IMPL_LED_BREATHING_COUNTER3_0_LONG_LOW_PERIOD_COUNT_DEFAULT_MASK                    MK_MASK_CONST(0xffffffff)
#define PMC_IMPL_LED_BREATHING_COUNTER3_0_LONG_LOW_PERIOD_COUNT_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define PMC_IMPL_LED_BREATHING_COUNTER3_0_LONG_LOW_PERIOD_COUNT_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define PMC_IMPL_LED_BREATHING_COUNTER3_0_LONG_LOW_PERIOD_COUNT_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define PMC_IMPL_LED_BREATHING_COUNTER3_0_LONG_LOW_PERIOD_COUNT_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register PMC_IMPL_LED_BREATHING_STATUS_0
#define PMC_IMPL_LED_BREATHING_STATUS_0                 MK_ADDR_CONST(0x8dc)
#define PMC_IMPL_LED_BREATHING_STATUS_0_SECURE                  0x0
#define PMC_IMPL_LED_BREATHING_STATUS_0_DUAL                    0x0
#define PMC_IMPL_LED_BREATHING_STATUS_0_SCR                     CNTRL_SCR_0
#define PMC_IMPL_LED_BREATHING_STATUS_0_SCRREG                  PMC_IMPL_SCR_CNTRL_SCR_0
#define PMC_IMPL_LED_BREATHING_STATUS_0_WORD_COUNT                      0x1
#define PMC_IMPL_LED_BREATHING_STATUS_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define PMC_IMPL_LED_BREATHING_STATUS_0_RESET_MASK                      MK_MASK_CONST(0x0)
#define PMC_IMPL_LED_BREATHING_STATUS_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define PMC_IMPL_LED_BREATHING_STATUS_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define PMC_IMPL_LED_BREATHING_STATUS_0_READ_MASK                       MK_MASK_CONST(0x7)
#define PMC_IMPL_LED_BREATHING_STATUS_0_WRITE_MASK                      MK_MASK_CONST(0x0)
// 000 - IDLE, 001 - UP_RAMP, 010 - PLATEAU, 011 - DOWN_RAMP, 100 - SHORT_LOW_PERIOD, 101 - LONG_LOW_PERIOD.
#define PMC_IMPL_LED_BREATHING_STATUS_0_CSTATE_SHIFT                    MK_SHIFT_CONST(0)
#define PMC_IMPL_LED_BREATHING_STATUS_0_CSTATE_FIELD                    MK_FIELD_CONST(0x7, PMC_IMPL_LED_BREATHING_STATUS_0_CSTATE_SHIFT)
#define PMC_IMPL_LED_BREATHING_STATUS_0_CSTATE_RANGE                    2:0
#define PMC_IMPL_LED_BREATHING_STATUS_0_CSTATE_MSB                      MK_SHIFT_CONST(2)
#define PMC_IMPL_LED_BREATHING_STATUS_0_CSTATE_LSB                      MK_SHIFT_CONST(0)
#define PMC_IMPL_LED_BREATHING_STATUS_0_CSTATE_WOFFSET                  0x0
#define PMC_IMPL_LED_BREATHING_STATUS_0_CSTATE_DEFAULT                  MK_MASK_CONST(0x0)
#define PMC_IMPL_LED_BREATHING_STATUS_0_CSTATE_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define PMC_IMPL_LED_BREATHING_STATUS_0_CSTATE_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define PMC_IMPL_LED_BREATHING_STATUS_0_CSTATE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define PMC_IMPL_LED_BREATHING_STATUS_0_CSTATE_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define PMC_IMPL_LED_BREATHING_STATUS_0_CSTATE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

// Reset level:l0coldrst_pmc_pclk_srstn

// Register PMC_IMPL_DPD_AUX_CLAMP_0
#define PMC_IMPL_DPD_AUX_CLAMP_0                        MK_ADDR_CONST(0x8e0)
#define PMC_IMPL_DPD_AUX_CLAMP_0_SECURE                         0x0
#define PMC_IMPL_DPD_AUX_CLAMP_0_DUAL                   0x0
#define PMC_IMPL_DPD_AUX_CLAMP_0_SCR                    AUX_CLAMP_SCR_0
#define PMC_IMPL_DPD_AUX_CLAMP_0_SCRREG                         PMC_IMPL_SCR_AUX_CLAMP_SCR_0
#define PMC_IMPL_DPD_AUX_CLAMP_0_WORD_COUNT                     0x1
#define PMC_IMPL_DPD_AUX_CLAMP_0_RESET_VAL                      MK_MASK_CONST(0x1)
#define PMC_IMPL_DPD_AUX_CLAMP_0_RESET_MASK                     MK_MASK_CONST(0x1)
#define PMC_IMPL_DPD_AUX_CLAMP_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define PMC_IMPL_DPD_AUX_CLAMP_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define PMC_IMPL_DPD_AUX_CLAMP_0_READ_MASK                      MK_MASK_CONST(0x1)
#define PMC_IMPL_DPD_AUX_CLAMP_0_WRITE_MASK                     MK_MASK_CONST(0x1)
// 1 - UPHY clampped
// 0 - UPHY not clampped
#define PMC_IMPL_DPD_AUX_CLAMP_0_AUX_CLAMP_SHIFT                        MK_SHIFT_CONST(0)
#define PMC_IMPL_DPD_AUX_CLAMP_0_AUX_CLAMP_FIELD                        MK_FIELD_CONST(0x1, PMC_IMPL_DPD_AUX_CLAMP_0_AUX_CLAMP_SHIFT)
#define PMC_IMPL_DPD_AUX_CLAMP_0_AUX_CLAMP_RANGE                        0:0
#define PMC_IMPL_DPD_AUX_CLAMP_0_AUX_CLAMP_MSB                  MK_SHIFT_CONST(0)
#define PMC_IMPL_DPD_AUX_CLAMP_0_AUX_CLAMP_LSB                  MK_SHIFT_CONST(0)
#define PMC_IMPL_DPD_AUX_CLAMP_0_AUX_CLAMP_WOFFSET                      0x0
#define PMC_IMPL_DPD_AUX_CLAMP_0_AUX_CLAMP_DEFAULT                      MK_MASK_CONST(0x1)
#define PMC_IMPL_DPD_AUX_CLAMP_0_AUX_CLAMP_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define PMC_IMPL_DPD_AUX_CLAMP_0_AUX_CLAMP_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define PMC_IMPL_DPD_AUX_CLAMP_0_AUX_CLAMP_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define PMC_IMPL_DPD_AUX_CLAMP_0_AUX_CLAMP_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define PMC_IMPL_DPD_AUX_CLAMP_0_AUX_CLAMP_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Reserved address 0x8e4

// Reserved address 0x8e8

// Register PMC_IMPL_IO_SYS_DPD_REQ_0
#define PMC_IMPL_IO_SYS_DPD_REQ_0                       MK_ADDR_CONST(0xe014)
#define PMC_IMPL_IO_SYS_DPD_REQ_0_SECURE                        0x0
#define PMC_IMPL_IO_SYS_DPD_REQ_0_DUAL                  0x0
#define PMC_IMPL_IO_SYS_DPD_REQ_0_SCR                   IO_SYS_SCR_0
#define PMC_IMPL_IO_SYS_DPD_REQ_0_SCRREG                        PMC_IMPL_SCR_IO_SYS_SCR_0
#define PMC_IMPL_IO_SYS_DPD_REQ_0_WORD_COUNT                    0x1
#define PMC_IMPL_IO_SYS_DPD_REQ_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_SYS_DPD_REQ_0_RESET_MASK                    MK_MASK_CONST(0xc00001ff)
#define PMC_IMPL_IO_SYS_DPD_REQ_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_SYS_DPD_REQ_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_SYS_DPD_REQ_0_READ_MASK                     MK_MASK_CONST(0xc00001ff)
#define PMC_IMPL_IO_SYS_DPD_REQ_0_WRITE_MASK                    MK_MASK_CONST(0xc00001ff)
// code of operation for all set bits
#define PMC_IMPL_IO_SYS_DPD_REQ_0_CODE_SHIFT                    MK_SHIFT_CONST(30)
#define PMC_IMPL_IO_SYS_DPD_REQ_0_CODE_FIELD                    MK_FIELD_CONST(0x3, PMC_IMPL_IO_SYS_DPD_REQ_0_CODE_SHIFT)
#define PMC_IMPL_IO_SYS_DPD_REQ_0_CODE_RANGE                    31:30
#define PMC_IMPL_IO_SYS_DPD_REQ_0_CODE_MSB                      MK_SHIFT_CONST(31)
#define PMC_IMPL_IO_SYS_DPD_REQ_0_CODE_LSB                      MK_SHIFT_CONST(30)
#define PMC_IMPL_IO_SYS_DPD_REQ_0_CODE_WOFFSET                  0x0
#define PMC_IMPL_IO_SYS_DPD_REQ_0_CODE_DEFAULT                  MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_SYS_DPD_REQ_0_CODE_DEFAULT_MASK                     MK_MASK_CONST(0x3)
#define PMC_IMPL_IO_SYS_DPD_REQ_0_CODE_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_SYS_DPD_REQ_0_CODE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_SYS_DPD_REQ_0_CODE_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_SYS_DPD_REQ_0_CODE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_SYS_DPD_REQ_0_CODE_IDLE                     MK_ENUM_CONST(0)
#define PMC_IMPL_IO_SYS_DPD_REQ_0_CODE_DPD_OFF                  MK_ENUM_CONST(1)
#define PMC_IMPL_IO_SYS_DPD_REQ_0_CODE_DPD_ON                   MK_ENUM_CONST(2)

// puts SCE_ERROR PAD(s) in/out of Depp Power Down (DPD) mode
#define PMC_IMPL_IO_SYS_DPD_REQ_0_SCE_ERROR_SHIFT                       MK_SHIFT_CONST(0)
#define PMC_IMPL_IO_SYS_DPD_REQ_0_SCE_ERROR_FIELD                       MK_FIELD_CONST(0x1, PMC_IMPL_IO_SYS_DPD_REQ_0_SCE_ERROR_SHIFT)
#define PMC_IMPL_IO_SYS_DPD_REQ_0_SCE_ERROR_RANGE                       0:0
#define PMC_IMPL_IO_SYS_DPD_REQ_0_SCE_ERROR_MSB                 MK_SHIFT_CONST(0)
#define PMC_IMPL_IO_SYS_DPD_REQ_0_SCE_ERROR_LSB                 MK_SHIFT_CONST(0)
#define PMC_IMPL_IO_SYS_DPD_REQ_0_SCE_ERROR_WOFFSET                     0x0
#define PMC_IMPL_IO_SYS_DPD_REQ_0_SCE_ERROR_DEFAULT                     MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_SYS_DPD_REQ_0_SCE_ERROR_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_SYS_DPD_REQ_0_SCE_ERROR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_SYS_DPD_REQ_0_SCE_ERROR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_SYS_DPD_REQ_0_SCE_ERROR_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_SYS_DPD_REQ_0_SCE_ERROR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_SYS_DPD_REQ_0_SCE_ERROR_OFF                 MK_ENUM_CONST(0)
#define PMC_IMPL_IO_SYS_DPD_REQ_0_SCE_ERROR_ON                  MK_ENUM_CONST(1)

// puts VCOMP_ALERT PAD(s) in/out of Depp Power Down (DPD) mode
#define PMC_IMPL_IO_SYS_DPD_REQ_0_VCOMP_ALERT_SHIFT                     MK_SHIFT_CONST(1)
#define PMC_IMPL_IO_SYS_DPD_REQ_0_VCOMP_ALERT_FIELD                     MK_FIELD_CONST(0x1, PMC_IMPL_IO_SYS_DPD_REQ_0_VCOMP_ALERT_SHIFT)
#define PMC_IMPL_IO_SYS_DPD_REQ_0_VCOMP_ALERT_RANGE                     1:1
#define PMC_IMPL_IO_SYS_DPD_REQ_0_VCOMP_ALERT_MSB                       MK_SHIFT_CONST(1)
#define PMC_IMPL_IO_SYS_DPD_REQ_0_VCOMP_ALERT_LSB                       MK_SHIFT_CONST(1)
#define PMC_IMPL_IO_SYS_DPD_REQ_0_VCOMP_ALERT_WOFFSET                   0x0
#define PMC_IMPL_IO_SYS_DPD_REQ_0_VCOMP_ALERT_DEFAULT                   MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_SYS_DPD_REQ_0_VCOMP_ALERT_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_SYS_DPD_REQ_0_VCOMP_ALERT_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_SYS_DPD_REQ_0_VCOMP_ALERT_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_SYS_DPD_REQ_0_VCOMP_ALERT_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_SYS_DPD_REQ_0_VCOMP_ALERT_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_SYS_DPD_REQ_0_VCOMP_ALERT_OFF                       MK_ENUM_CONST(0)
#define PMC_IMPL_IO_SYS_DPD_REQ_0_VCOMP_ALERT_ON                        MK_ENUM_CONST(1)

// puts SOC_GPIO26 PAD(s) in/out of Depp Power Down (DPD) mode
#define PMC_IMPL_IO_SYS_DPD_REQ_0_SOC_GPIO26_SHIFT                      MK_SHIFT_CONST(2)
#define PMC_IMPL_IO_SYS_DPD_REQ_0_SOC_GPIO26_FIELD                      MK_FIELD_CONST(0x1, PMC_IMPL_IO_SYS_DPD_REQ_0_SOC_GPIO26_SHIFT)
#define PMC_IMPL_IO_SYS_DPD_REQ_0_SOC_GPIO26_RANGE                      2:2
#define PMC_IMPL_IO_SYS_DPD_REQ_0_SOC_GPIO26_MSB                        MK_SHIFT_CONST(2)
#define PMC_IMPL_IO_SYS_DPD_REQ_0_SOC_GPIO26_LSB                        MK_SHIFT_CONST(2)
#define PMC_IMPL_IO_SYS_DPD_REQ_0_SOC_GPIO26_WOFFSET                    0x0
#define PMC_IMPL_IO_SYS_DPD_REQ_0_SOC_GPIO26_DEFAULT                    MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_SYS_DPD_REQ_0_SOC_GPIO26_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_SYS_DPD_REQ_0_SOC_GPIO26_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_SYS_DPD_REQ_0_SOC_GPIO26_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_SYS_DPD_REQ_0_SOC_GPIO26_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_SYS_DPD_REQ_0_SOC_GPIO26_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_SYS_DPD_REQ_0_SOC_GPIO26_OFF                        MK_ENUM_CONST(0)
#define PMC_IMPL_IO_SYS_DPD_REQ_0_SOC_GPIO26_ON                 MK_ENUM_CONST(1)

// puts SOC_GPIO27 PAD(s) in/out of Depp Power Down (DPD) mode
#define PMC_IMPL_IO_SYS_DPD_REQ_0_SOC_GPIO27_SHIFT                      MK_SHIFT_CONST(3)
#define PMC_IMPL_IO_SYS_DPD_REQ_0_SOC_GPIO27_FIELD                      MK_FIELD_CONST(0x1, PMC_IMPL_IO_SYS_DPD_REQ_0_SOC_GPIO27_SHIFT)
#define PMC_IMPL_IO_SYS_DPD_REQ_0_SOC_GPIO27_RANGE                      3:3
#define PMC_IMPL_IO_SYS_DPD_REQ_0_SOC_GPIO27_MSB                        MK_SHIFT_CONST(3)
#define PMC_IMPL_IO_SYS_DPD_REQ_0_SOC_GPIO27_LSB                        MK_SHIFT_CONST(3)
#define PMC_IMPL_IO_SYS_DPD_REQ_0_SOC_GPIO27_WOFFSET                    0x0
#define PMC_IMPL_IO_SYS_DPD_REQ_0_SOC_GPIO27_DEFAULT                    MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_SYS_DPD_REQ_0_SOC_GPIO27_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_SYS_DPD_REQ_0_SOC_GPIO27_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_SYS_DPD_REQ_0_SOC_GPIO27_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_SYS_DPD_REQ_0_SOC_GPIO27_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_SYS_DPD_REQ_0_SOC_GPIO27_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_SYS_DPD_REQ_0_SOC_GPIO27_OFF                        MK_ENUM_CONST(0)
#define PMC_IMPL_IO_SYS_DPD_REQ_0_SOC_GPIO27_ON                 MK_ENUM_CONST(1)

// puts AO_RETENTION_N PAD(s) in/out of Depp Power Down (DPD) mode
#define PMC_IMPL_IO_SYS_DPD_REQ_0_AO_RETENTION_N_SHIFT                  MK_SHIFT_CONST(4)
#define PMC_IMPL_IO_SYS_DPD_REQ_0_AO_RETENTION_N_FIELD                  MK_FIELD_CONST(0x1, PMC_IMPL_IO_SYS_DPD_REQ_0_AO_RETENTION_N_SHIFT)
#define PMC_IMPL_IO_SYS_DPD_REQ_0_AO_RETENTION_N_RANGE                  4:4
#define PMC_IMPL_IO_SYS_DPD_REQ_0_AO_RETENTION_N_MSB                    MK_SHIFT_CONST(4)
#define PMC_IMPL_IO_SYS_DPD_REQ_0_AO_RETENTION_N_LSB                    MK_SHIFT_CONST(4)
#define PMC_IMPL_IO_SYS_DPD_REQ_0_AO_RETENTION_N_WOFFSET                        0x0
#define PMC_IMPL_IO_SYS_DPD_REQ_0_AO_RETENTION_N_DEFAULT                        MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_SYS_DPD_REQ_0_AO_RETENTION_N_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_SYS_DPD_REQ_0_AO_RETENTION_N_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_SYS_DPD_REQ_0_AO_RETENTION_N_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_SYS_DPD_REQ_0_AO_RETENTION_N_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_SYS_DPD_REQ_0_AO_RETENTION_N_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_SYS_DPD_REQ_0_AO_RETENTION_N_OFF                    MK_ENUM_CONST(0)
#define PMC_IMPL_IO_SYS_DPD_REQ_0_AO_RETENTION_N_ON                     MK_ENUM_CONST(1)

// puts BATT_OC PAD(s) in/out of Depp Power Down (DPD) mode
#define PMC_IMPL_IO_SYS_DPD_REQ_0_BATT_OC_SHIFT                 MK_SHIFT_CONST(5)
#define PMC_IMPL_IO_SYS_DPD_REQ_0_BATT_OC_FIELD                 MK_FIELD_CONST(0x1, PMC_IMPL_IO_SYS_DPD_REQ_0_BATT_OC_SHIFT)
#define PMC_IMPL_IO_SYS_DPD_REQ_0_BATT_OC_RANGE                 5:5
#define PMC_IMPL_IO_SYS_DPD_REQ_0_BATT_OC_MSB                   MK_SHIFT_CONST(5)
#define PMC_IMPL_IO_SYS_DPD_REQ_0_BATT_OC_LSB                   MK_SHIFT_CONST(5)
#define PMC_IMPL_IO_SYS_DPD_REQ_0_BATT_OC_WOFFSET                       0x0
#define PMC_IMPL_IO_SYS_DPD_REQ_0_BATT_OC_DEFAULT                       MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_SYS_DPD_REQ_0_BATT_OC_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_SYS_DPD_REQ_0_BATT_OC_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_SYS_DPD_REQ_0_BATT_OC_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_SYS_DPD_REQ_0_BATT_OC_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_SYS_DPD_REQ_0_BATT_OC_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_SYS_DPD_REQ_0_BATT_OC_OFF                   MK_ENUM_CONST(0)
#define PMC_IMPL_IO_SYS_DPD_REQ_0_BATT_OC_ON                    MK_ENUM_CONST(1)

// puts BOOTV_CTL_N PAD(s) in/out of Depp Power Down (DPD) mode
#define PMC_IMPL_IO_SYS_DPD_REQ_0_BOOTV_CTL_N_SHIFT                     MK_SHIFT_CONST(6)
#define PMC_IMPL_IO_SYS_DPD_REQ_0_BOOTV_CTL_N_FIELD                     MK_FIELD_CONST(0x1, PMC_IMPL_IO_SYS_DPD_REQ_0_BOOTV_CTL_N_SHIFT)
#define PMC_IMPL_IO_SYS_DPD_REQ_0_BOOTV_CTL_N_RANGE                     6:6
#define PMC_IMPL_IO_SYS_DPD_REQ_0_BOOTV_CTL_N_MSB                       MK_SHIFT_CONST(6)
#define PMC_IMPL_IO_SYS_DPD_REQ_0_BOOTV_CTL_N_LSB                       MK_SHIFT_CONST(6)
#define PMC_IMPL_IO_SYS_DPD_REQ_0_BOOTV_CTL_N_WOFFSET                   0x0
#define PMC_IMPL_IO_SYS_DPD_REQ_0_BOOTV_CTL_N_DEFAULT                   MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_SYS_DPD_REQ_0_BOOTV_CTL_N_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_SYS_DPD_REQ_0_BOOTV_CTL_N_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_SYS_DPD_REQ_0_BOOTV_CTL_N_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_SYS_DPD_REQ_0_BOOTV_CTL_N_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_SYS_DPD_REQ_0_BOOTV_CTL_N_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_SYS_DPD_REQ_0_BOOTV_CTL_N_OFF                       MK_ENUM_CONST(0)
#define PMC_IMPL_IO_SYS_DPD_REQ_0_BOOTV_CTL_N_ON                        MK_ENUM_CONST(1)

// puts POWER_ON PAD(s) in/out of Depp Power Down (DPD) mode
#define PMC_IMPL_IO_SYS_DPD_REQ_0_POWER_ON_SHIFT                        MK_SHIFT_CONST(7)
#define PMC_IMPL_IO_SYS_DPD_REQ_0_POWER_ON_FIELD                        MK_FIELD_CONST(0x1, PMC_IMPL_IO_SYS_DPD_REQ_0_POWER_ON_SHIFT)
#define PMC_IMPL_IO_SYS_DPD_REQ_0_POWER_ON_RANGE                        7:7
#define PMC_IMPL_IO_SYS_DPD_REQ_0_POWER_ON_MSB                  MK_SHIFT_CONST(7)
#define PMC_IMPL_IO_SYS_DPD_REQ_0_POWER_ON_LSB                  MK_SHIFT_CONST(7)
#define PMC_IMPL_IO_SYS_DPD_REQ_0_POWER_ON_WOFFSET                      0x0
#define PMC_IMPL_IO_SYS_DPD_REQ_0_POWER_ON_DEFAULT                      MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_SYS_DPD_REQ_0_POWER_ON_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_SYS_DPD_REQ_0_POWER_ON_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_SYS_DPD_REQ_0_POWER_ON_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_SYS_DPD_REQ_0_POWER_ON_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_SYS_DPD_REQ_0_POWER_ON_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_SYS_DPD_REQ_0_POWER_ON_OFF                  MK_ENUM_CONST(0)
#define PMC_IMPL_IO_SYS_DPD_REQ_0_POWER_ON_ON                   MK_ENUM_CONST(1)

// puts HDMI_CEC PAD(s) in/out of Depp Power Down (DPD) mode
#define PMC_IMPL_IO_SYS_DPD_REQ_0_HDMI_CEC_SHIFT                        MK_SHIFT_CONST(8)
#define PMC_IMPL_IO_SYS_DPD_REQ_0_HDMI_CEC_FIELD                        MK_FIELD_CONST(0x1, PMC_IMPL_IO_SYS_DPD_REQ_0_HDMI_CEC_SHIFT)
#define PMC_IMPL_IO_SYS_DPD_REQ_0_HDMI_CEC_RANGE                        8:8
#define PMC_IMPL_IO_SYS_DPD_REQ_0_HDMI_CEC_MSB                  MK_SHIFT_CONST(8)
#define PMC_IMPL_IO_SYS_DPD_REQ_0_HDMI_CEC_LSB                  MK_SHIFT_CONST(8)
#define PMC_IMPL_IO_SYS_DPD_REQ_0_HDMI_CEC_WOFFSET                      0x0
#define PMC_IMPL_IO_SYS_DPD_REQ_0_HDMI_CEC_DEFAULT                      MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_SYS_DPD_REQ_0_HDMI_CEC_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_SYS_DPD_REQ_0_HDMI_CEC_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_SYS_DPD_REQ_0_HDMI_CEC_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_SYS_DPD_REQ_0_HDMI_CEC_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_SYS_DPD_REQ_0_HDMI_CEC_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_SYS_DPD_REQ_0_HDMI_CEC_OFF                  MK_ENUM_CONST(0)
#define PMC_IMPL_IO_SYS_DPD_REQ_0_HDMI_CEC_ON                   MK_ENUM_CONST(1)


// Register PMC_IMPL_IO_SYS_DPD_STATUS_0
#define PMC_IMPL_IO_SYS_DPD_STATUS_0                    MK_ADDR_CONST(0xe018)
#define PMC_IMPL_IO_SYS_DPD_STATUS_0_SECURE                     0x0
#define PMC_IMPL_IO_SYS_DPD_STATUS_0_DUAL                       0x0
#define PMC_IMPL_IO_SYS_DPD_STATUS_0_SCR                        IO_SYS_SCR_0
#define PMC_IMPL_IO_SYS_DPD_STATUS_0_SCRREG                     PMC_IMPL_SCR_IO_SYS_SCR_0
#define PMC_IMPL_IO_SYS_DPD_STATUS_0_WORD_COUNT                         0x1
#define PMC_IMPL_IO_SYS_DPD_STATUS_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_SYS_DPD_STATUS_0_RESET_MASK                         MK_MASK_CONST(0x1ff)
#define PMC_IMPL_IO_SYS_DPD_STATUS_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_SYS_DPD_STATUS_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_SYS_DPD_STATUS_0_READ_MASK                  MK_MASK_CONST(0x1ff)
#define PMC_IMPL_IO_SYS_DPD_STATUS_0_WRITE_MASK                         MK_MASK_CONST(0x0)
// On - SCE_ERROR PAD(s) is in Deep Power Down mode, Off - SCE_ERROR PAD(s) is out of Deep Power Down mode
#define PMC_IMPL_IO_SYS_DPD_STATUS_0_SCE_ERROR_SHIFT                    MK_SHIFT_CONST(0)
#define PMC_IMPL_IO_SYS_DPD_STATUS_0_SCE_ERROR_FIELD                    MK_FIELD_CONST(0x1, PMC_IMPL_IO_SYS_DPD_STATUS_0_SCE_ERROR_SHIFT)
#define PMC_IMPL_IO_SYS_DPD_STATUS_0_SCE_ERROR_RANGE                    0:0
#define PMC_IMPL_IO_SYS_DPD_STATUS_0_SCE_ERROR_MSB                      MK_SHIFT_CONST(0)
#define PMC_IMPL_IO_SYS_DPD_STATUS_0_SCE_ERROR_LSB                      MK_SHIFT_CONST(0)
#define PMC_IMPL_IO_SYS_DPD_STATUS_0_SCE_ERROR_WOFFSET                  0x0
#define PMC_IMPL_IO_SYS_DPD_STATUS_0_SCE_ERROR_DEFAULT                  MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_SYS_DPD_STATUS_0_SCE_ERROR_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_SYS_DPD_STATUS_0_SCE_ERROR_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_SYS_DPD_STATUS_0_SCE_ERROR_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_SYS_DPD_STATUS_0_SCE_ERROR_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_SYS_DPD_STATUS_0_SCE_ERROR_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_SYS_DPD_STATUS_0_SCE_ERROR_OFF                      MK_ENUM_CONST(0)
#define PMC_IMPL_IO_SYS_DPD_STATUS_0_SCE_ERROR_ON                       MK_ENUM_CONST(1)

// On - VCOMP_ALERT PAD(s) is in Deep Power Down mode, Off - VCOMP_ALERT PAD(s) is out of Deep Power Down mode
#define PMC_IMPL_IO_SYS_DPD_STATUS_0_VCOMP_ALERT_SHIFT                  MK_SHIFT_CONST(1)
#define PMC_IMPL_IO_SYS_DPD_STATUS_0_VCOMP_ALERT_FIELD                  MK_FIELD_CONST(0x1, PMC_IMPL_IO_SYS_DPD_STATUS_0_VCOMP_ALERT_SHIFT)
#define PMC_IMPL_IO_SYS_DPD_STATUS_0_VCOMP_ALERT_RANGE                  1:1
#define PMC_IMPL_IO_SYS_DPD_STATUS_0_VCOMP_ALERT_MSB                    MK_SHIFT_CONST(1)
#define PMC_IMPL_IO_SYS_DPD_STATUS_0_VCOMP_ALERT_LSB                    MK_SHIFT_CONST(1)
#define PMC_IMPL_IO_SYS_DPD_STATUS_0_VCOMP_ALERT_WOFFSET                        0x0
#define PMC_IMPL_IO_SYS_DPD_STATUS_0_VCOMP_ALERT_DEFAULT                        MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_SYS_DPD_STATUS_0_VCOMP_ALERT_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_SYS_DPD_STATUS_0_VCOMP_ALERT_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_SYS_DPD_STATUS_0_VCOMP_ALERT_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_SYS_DPD_STATUS_0_VCOMP_ALERT_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_SYS_DPD_STATUS_0_VCOMP_ALERT_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_SYS_DPD_STATUS_0_VCOMP_ALERT_OFF                    MK_ENUM_CONST(0)
#define PMC_IMPL_IO_SYS_DPD_STATUS_0_VCOMP_ALERT_ON                     MK_ENUM_CONST(1)

// On - SOC_GPIO26 PAD(s) is in Deep Power Down mode, Off - SOC_GPIO26 PAD(s) is out of Deep Power Down mode
#define PMC_IMPL_IO_SYS_DPD_STATUS_0_SOC_GPIO26_SHIFT                   MK_SHIFT_CONST(2)
#define PMC_IMPL_IO_SYS_DPD_STATUS_0_SOC_GPIO26_FIELD                   MK_FIELD_CONST(0x1, PMC_IMPL_IO_SYS_DPD_STATUS_0_SOC_GPIO26_SHIFT)
#define PMC_IMPL_IO_SYS_DPD_STATUS_0_SOC_GPIO26_RANGE                   2:2
#define PMC_IMPL_IO_SYS_DPD_STATUS_0_SOC_GPIO26_MSB                     MK_SHIFT_CONST(2)
#define PMC_IMPL_IO_SYS_DPD_STATUS_0_SOC_GPIO26_LSB                     MK_SHIFT_CONST(2)
#define PMC_IMPL_IO_SYS_DPD_STATUS_0_SOC_GPIO26_WOFFSET                 0x0
#define PMC_IMPL_IO_SYS_DPD_STATUS_0_SOC_GPIO26_DEFAULT                 MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_SYS_DPD_STATUS_0_SOC_GPIO26_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_SYS_DPD_STATUS_0_SOC_GPIO26_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_SYS_DPD_STATUS_0_SOC_GPIO26_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_SYS_DPD_STATUS_0_SOC_GPIO26_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_SYS_DPD_STATUS_0_SOC_GPIO26_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_SYS_DPD_STATUS_0_SOC_GPIO26_OFF                     MK_ENUM_CONST(0)
#define PMC_IMPL_IO_SYS_DPD_STATUS_0_SOC_GPIO26_ON                      MK_ENUM_CONST(1)

// On - SOC_GPIO27 PAD(s) is in Deep Power Down mode, Off - SOC_GPIO27 PAD(s) is out of Deep Power Down mode
#define PMC_IMPL_IO_SYS_DPD_STATUS_0_SOC_GPIO27_SHIFT                   MK_SHIFT_CONST(3)
#define PMC_IMPL_IO_SYS_DPD_STATUS_0_SOC_GPIO27_FIELD                   MK_FIELD_CONST(0x1, PMC_IMPL_IO_SYS_DPD_STATUS_0_SOC_GPIO27_SHIFT)
#define PMC_IMPL_IO_SYS_DPD_STATUS_0_SOC_GPIO27_RANGE                   3:3
#define PMC_IMPL_IO_SYS_DPD_STATUS_0_SOC_GPIO27_MSB                     MK_SHIFT_CONST(3)
#define PMC_IMPL_IO_SYS_DPD_STATUS_0_SOC_GPIO27_LSB                     MK_SHIFT_CONST(3)
#define PMC_IMPL_IO_SYS_DPD_STATUS_0_SOC_GPIO27_WOFFSET                 0x0
#define PMC_IMPL_IO_SYS_DPD_STATUS_0_SOC_GPIO27_DEFAULT                 MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_SYS_DPD_STATUS_0_SOC_GPIO27_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_SYS_DPD_STATUS_0_SOC_GPIO27_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_SYS_DPD_STATUS_0_SOC_GPIO27_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_SYS_DPD_STATUS_0_SOC_GPIO27_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_SYS_DPD_STATUS_0_SOC_GPIO27_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_SYS_DPD_STATUS_0_SOC_GPIO27_OFF                     MK_ENUM_CONST(0)
#define PMC_IMPL_IO_SYS_DPD_STATUS_0_SOC_GPIO27_ON                      MK_ENUM_CONST(1)

// On - AO_RETENTION_N PAD(s) is in Deep Power Down mode, Off - AO_RETENTION_N PAD(s) is out of Deep Power Down mode
#define PMC_IMPL_IO_SYS_DPD_STATUS_0_AO_RETENTION_N_SHIFT                       MK_SHIFT_CONST(4)
#define PMC_IMPL_IO_SYS_DPD_STATUS_0_AO_RETENTION_N_FIELD                       MK_FIELD_CONST(0x1, PMC_IMPL_IO_SYS_DPD_STATUS_0_AO_RETENTION_N_SHIFT)
#define PMC_IMPL_IO_SYS_DPD_STATUS_0_AO_RETENTION_N_RANGE                       4:4
#define PMC_IMPL_IO_SYS_DPD_STATUS_0_AO_RETENTION_N_MSB                 MK_SHIFT_CONST(4)
#define PMC_IMPL_IO_SYS_DPD_STATUS_0_AO_RETENTION_N_LSB                 MK_SHIFT_CONST(4)
#define PMC_IMPL_IO_SYS_DPD_STATUS_0_AO_RETENTION_N_WOFFSET                     0x0
#define PMC_IMPL_IO_SYS_DPD_STATUS_0_AO_RETENTION_N_DEFAULT                     MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_SYS_DPD_STATUS_0_AO_RETENTION_N_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_SYS_DPD_STATUS_0_AO_RETENTION_N_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_SYS_DPD_STATUS_0_AO_RETENTION_N_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_SYS_DPD_STATUS_0_AO_RETENTION_N_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_SYS_DPD_STATUS_0_AO_RETENTION_N_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_SYS_DPD_STATUS_0_AO_RETENTION_N_OFF                 MK_ENUM_CONST(0)
#define PMC_IMPL_IO_SYS_DPD_STATUS_0_AO_RETENTION_N_ON                  MK_ENUM_CONST(1)

// On - BATT_OC PAD(s) is in Deep Power Down mode, Off - BATT_OC PAD(s) is out of Deep Power Down mode
#define PMC_IMPL_IO_SYS_DPD_STATUS_0_BATT_OC_SHIFT                      MK_SHIFT_CONST(5)
#define PMC_IMPL_IO_SYS_DPD_STATUS_0_BATT_OC_FIELD                      MK_FIELD_CONST(0x1, PMC_IMPL_IO_SYS_DPD_STATUS_0_BATT_OC_SHIFT)
#define PMC_IMPL_IO_SYS_DPD_STATUS_0_BATT_OC_RANGE                      5:5
#define PMC_IMPL_IO_SYS_DPD_STATUS_0_BATT_OC_MSB                        MK_SHIFT_CONST(5)
#define PMC_IMPL_IO_SYS_DPD_STATUS_0_BATT_OC_LSB                        MK_SHIFT_CONST(5)
#define PMC_IMPL_IO_SYS_DPD_STATUS_0_BATT_OC_WOFFSET                    0x0
#define PMC_IMPL_IO_SYS_DPD_STATUS_0_BATT_OC_DEFAULT                    MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_SYS_DPD_STATUS_0_BATT_OC_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_SYS_DPD_STATUS_0_BATT_OC_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_SYS_DPD_STATUS_0_BATT_OC_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_SYS_DPD_STATUS_0_BATT_OC_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_SYS_DPD_STATUS_0_BATT_OC_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_SYS_DPD_STATUS_0_BATT_OC_OFF                        MK_ENUM_CONST(0)
#define PMC_IMPL_IO_SYS_DPD_STATUS_0_BATT_OC_ON                 MK_ENUM_CONST(1)

// On - BOOTV_CTL_N PAD(s) is in Deep Power Down mode, Off - BOOTV_CTL_N PAD(s) is out of Deep Power Down mode
#define PMC_IMPL_IO_SYS_DPD_STATUS_0_BOOTV_CTL_N_SHIFT                  MK_SHIFT_CONST(6)
#define PMC_IMPL_IO_SYS_DPD_STATUS_0_BOOTV_CTL_N_FIELD                  MK_FIELD_CONST(0x1, PMC_IMPL_IO_SYS_DPD_STATUS_0_BOOTV_CTL_N_SHIFT)
#define PMC_IMPL_IO_SYS_DPD_STATUS_0_BOOTV_CTL_N_RANGE                  6:6
#define PMC_IMPL_IO_SYS_DPD_STATUS_0_BOOTV_CTL_N_MSB                    MK_SHIFT_CONST(6)
#define PMC_IMPL_IO_SYS_DPD_STATUS_0_BOOTV_CTL_N_LSB                    MK_SHIFT_CONST(6)
#define PMC_IMPL_IO_SYS_DPD_STATUS_0_BOOTV_CTL_N_WOFFSET                        0x0
#define PMC_IMPL_IO_SYS_DPD_STATUS_0_BOOTV_CTL_N_DEFAULT                        MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_SYS_DPD_STATUS_0_BOOTV_CTL_N_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_SYS_DPD_STATUS_0_BOOTV_CTL_N_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_SYS_DPD_STATUS_0_BOOTV_CTL_N_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_SYS_DPD_STATUS_0_BOOTV_CTL_N_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_SYS_DPD_STATUS_0_BOOTV_CTL_N_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_SYS_DPD_STATUS_0_BOOTV_CTL_N_OFF                    MK_ENUM_CONST(0)
#define PMC_IMPL_IO_SYS_DPD_STATUS_0_BOOTV_CTL_N_ON                     MK_ENUM_CONST(1)

// On - POWER_ON PAD(s) is in Deep Power Down mode, Off - POWER_ON PAD(s) is out of Deep Power Down mode
#define PMC_IMPL_IO_SYS_DPD_STATUS_0_POWER_ON_SHIFT                     MK_SHIFT_CONST(7)
#define PMC_IMPL_IO_SYS_DPD_STATUS_0_POWER_ON_FIELD                     MK_FIELD_CONST(0x1, PMC_IMPL_IO_SYS_DPD_STATUS_0_POWER_ON_SHIFT)
#define PMC_IMPL_IO_SYS_DPD_STATUS_0_POWER_ON_RANGE                     7:7
#define PMC_IMPL_IO_SYS_DPD_STATUS_0_POWER_ON_MSB                       MK_SHIFT_CONST(7)
#define PMC_IMPL_IO_SYS_DPD_STATUS_0_POWER_ON_LSB                       MK_SHIFT_CONST(7)
#define PMC_IMPL_IO_SYS_DPD_STATUS_0_POWER_ON_WOFFSET                   0x0
#define PMC_IMPL_IO_SYS_DPD_STATUS_0_POWER_ON_DEFAULT                   MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_SYS_DPD_STATUS_0_POWER_ON_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_SYS_DPD_STATUS_0_POWER_ON_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_SYS_DPD_STATUS_0_POWER_ON_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_SYS_DPD_STATUS_0_POWER_ON_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_SYS_DPD_STATUS_0_POWER_ON_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_SYS_DPD_STATUS_0_POWER_ON_OFF                       MK_ENUM_CONST(0)
#define PMC_IMPL_IO_SYS_DPD_STATUS_0_POWER_ON_ON                        MK_ENUM_CONST(1)

// On - HDMI_CEC PAD(s) is in Deep Power Down mode, Off - HDMI_CEC PAD(s) is out of Deep Power Down mode
#define PMC_IMPL_IO_SYS_DPD_STATUS_0_HDMI_CEC_SHIFT                     MK_SHIFT_CONST(8)
#define PMC_IMPL_IO_SYS_DPD_STATUS_0_HDMI_CEC_FIELD                     MK_FIELD_CONST(0x1, PMC_IMPL_IO_SYS_DPD_STATUS_0_HDMI_CEC_SHIFT)
#define PMC_IMPL_IO_SYS_DPD_STATUS_0_HDMI_CEC_RANGE                     8:8
#define PMC_IMPL_IO_SYS_DPD_STATUS_0_HDMI_CEC_MSB                       MK_SHIFT_CONST(8)
#define PMC_IMPL_IO_SYS_DPD_STATUS_0_HDMI_CEC_LSB                       MK_SHIFT_CONST(8)
#define PMC_IMPL_IO_SYS_DPD_STATUS_0_HDMI_CEC_WOFFSET                   0x0
#define PMC_IMPL_IO_SYS_DPD_STATUS_0_HDMI_CEC_DEFAULT                   MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_SYS_DPD_STATUS_0_HDMI_CEC_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_SYS_DPD_STATUS_0_HDMI_CEC_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_SYS_DPD_STATUS_0_HDMI_CEC_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_SYS_DPD_STATUS_0_HDMI_CEC_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_SYS_DPD_STATUS_0_HDMI_CEC_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_SYS_DPD_STATUS_0_HDMI_CEC_OFF                       MK_ENUM_CONST(0)
#define PMC_IMPL_IO_SYS_DPD_STATUS_0_HDMI_CEC_ON                        MK_ENUM_CONST(1)


// Register PMC_IMPL_IO_SYS_DPD_OFF_MASK_0
#define PMC_IMPL_IO_SYS_DPD_OFF_MASK_0                  MK_ADDR_CONST(0xe01c)
#define PMC_IMPL_IO_SYS_DPD_OFF_MASK_0_SECURE                   0x0
#define PMC_IMPL_IO_SYS_DPD_OFF_MASK_0_DUAL                     0x0
#define PMC_IMPL_IO_SYS_DPD_OFF_MASK_0_SCR                      IO_SYS_SCR_0
#define PMC_IMPL_IO_SYS_DPD_OFF_MASK_0_SCRREG                   PMC_IMPL_SCR_IO_SYS_SCR_0
#define PMC_IMPL_IO_SYS_DPD_OFF_MASK_0_WORD_COUNT                       0x1
#define PMC_IMPL_IO_SYS_DPD_OFF_MASK_0_RESET_VAL                        MK_MASK_CONST(0x1ff)
#define PMC_IMPL_IO_SYS_DPD_OFF_MASK_0_RESET_MASK                       MK_MASK_CONST(0x1ff)
#define PMC_IMPL_IO_SYS_DPD_OFF_MASK_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_SYS_DPD_OFF_MASK_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_SYS_DPD_OFF_MASK_0_READ_MASK                        MK_MASK_CONST(0x1ff)
#define PMC_IMPL_IO_SYS_DPD_OFF_MASK_0_WRITE_MASK                       MK_MASK_CONST(0x1ff)
// On - SCE_ERROR PAD(s) are masked to enter Deep Power Down mode from SC7 controller, Off - SCE_ERROR PAD(s) are free to enter Deep Power Down mode
#define PMC_IMPL_IO_SYS_DPD_OFF_MASK_0_SCE_ERROR_SHIFT                  MK_SHIFT_CONST(0)
#define PMC_IMPL_IO_SYS_DPD_OFF_MASK_0_SCE_ERROR_FIELD                  MK_FIELD_CONST(0x1, PMC_IMPL_IO_SYS_DPD_OFF_MASK_0_SCE_ERROR_SHIFT)
#define PMC_IMPL_IO_SYS_DPD_OFF_MASK_0_SCE_ERROR_RANGE                  0:0
#define PMC_IMPL_IO_SYS_DPD_OFF_MASK_0_SCE_ERROR_MSB                    MK_SHIFT_CONST(0)
#define PMC_IMPL_IO_SYS_DPD_OFF_MASK_0_SCE_ERROR_LSB                    MK_SHIFT_CONST(0)
#define PMC_IMPL_IO_SYS_DPD_OFF_MASK_0_SCE_ERROR_WOFFSET                        0x0
#define PMC_IMPL_IO_SYS_DPD_OFF_MASK_0_SCE_ERROR_DEFAULT                        MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_SYS_DPD_OFF_MASK_0_SCE_ERROR_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_SYS_DPD_OFF_MASK_0_SCE_ERROR_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_SYS_DPD_OFF_MASK_0_SCE_ERROR_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_SYS_DPD_OFF_MASK_0_SCE_ERROR_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_SYS_DPD_OFF_MASK_0_SCE_ERROR_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_SYS_DPD_OFF_MASK_0_SCE_ERROR_OFF                    MK_ENUM_CONST(0)
#define PMC_IMPL_IO_SYS_DPD_OFF_MASK_0_SCE_ERROR_ON                     MK_ENUM_CONST(1)

// On - VCOMP_ALERT PAD(s) are masked to enter Deep Power Down mode from SC7 controller, Off - VCOMP_ALERT PAD(s) are free to enter Deep Power Down mode
#define PMC_IMPL_IO_SYS_DPD_OFF_MASK_0_VCOMP_ALERT_SHIFT                        MK_SHIFT_CONST(1)
#define PMC_IMPL_IO_SYS_DPD_OFF_MASK_0_VCOMP_ALERT_FIELD                        MK_FIELD_CONST(0x1, PMC_IMPL_IO_SYS_DPD_OFF_MASK_0_VCOMP_ALERT_SHIFT)
#define PMC_IMPL_IO_SYS_DPD_OFF_MASK_0_VCOMP_ALERT_RANGE                        1:1
#define PMC_IMPL_IO_SYS_DPD_OFF_MASK_0_VCOMP_ALERT_MSB                  MK_SHIFT_CONST(1)
#define PMC_IMPL_IO_SYS_DPD_OFF_MASK_0_VCOMP_ALERT_LSB                  MK_SHIFT_CONST(1)
#define PMC_IMPL_IO_SYS_DPD_OFF_MASK_0_VCOMP_ALERT_WOFFSET                      0x0
#define PMC_IMPL_IO_SYS_DPD_OFF_MASK_0_VCOMP_ALERT_DEFAULT                      MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_SYS_DPD_OFF_MASK_0_VCOMP_ALERT_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_SYS_DPD_OFF_MASK_0_VCOMP_ALERT_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_SYS_DPD_OFF_MASK_0_VCOMP_ALERT_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_SYS_DPD_OFF_MASK_0_VCOMP_ALERT_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_SYS_DPD_OFF_MASK_0_VCOMP_ALERT_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_SYS_DPD_OFF_MASK_0_VCOMP_ALERT_OFF                  MK_ENUM_CONST(0)
#define PMC_IMPL_IO_SYS_DPD_OFF_MASK_0_VCOMP_ALERT_ON                   MK_ENUM_CONST(1)

// On - SOC_GPIO26 PAD(s) are masked to enter Deep Power Down mode from SC7 controller, Off - SOC_GPIO26 PAD(s) are free to enter Deep Power Down mode
#define PMC_IMPL_IO_SYS_DPD_OFF_MASK_0_SOC_GPIO26_SHIFT                 MK_SHIFT_CONST(2)
#define PMC_IMPL_IO_SYS_DPD_OFF_MASK_0_SOC_GPIO26_FIELD                 MK_FIELD_CONST(0x1, PMC_IMPL_IO_SYS_DPD_OFF_MASK_0_SOC_GPIO26_SHIFT)
#define PMC_IMPL_IO_SYS_DPD_OFF_MASK_0_SOC_GPIO26_RANGE                 2:2
#define PMC_IMPL_IO_SYS_DPD_OFF_MASK_0_SOC_GPIO26_MSB                   MK_SHIFT_CONST(2)
#define PMC_IMPL_IO_SYS_DPD_OFF_MASK_0_SOC_GPIO26_LSB                   MK_SHIFT_CONST(2)
#define PMC_IMPL_IO_SYS_DPD_OFF_MASK_0_SOC_GPIO26_WOFFSET                       0x0
#define PMC_IMPL_IO_SYS_DPD_OFF_MASK_0_SOC_GPIO26_DEFAULT                       MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_SYS_DPD_OFF_MASK_0_SOC_GPIO26_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_SYS_DPD_OFF_MASK_0_SOC_GPIO26_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_SYS_DPD_OFF_MASK_0_SOC_GPIO26_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_SYS_DPD_OFF_MASK_0_SOC_GPIO26_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_SYS_DPD_OFF_MASK_0_SOC_GPIO26_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_SYS_DPD_OFF_MASK_0_SOC_GPIO26_OFF                   MK_ENUM_CONST(0)
#define PMC_IMPL_IO_SYS_DPD_OFF_MASK_0_SOC_GPIO26_ON                    MK_ENUM_CONST(1)

// On - SOC_GPIO27 PAD(s) are masked to enter Deep Power Down mode from SC7 controller, Off - SOC_GPIO27 PAD(s) are free to enter Deep Power Down mode
#define PMC_IMPL_IO_SYS_DPD_OFF_MASK_0_SOC_GPIO27_SHIFT                 MK_SHIFT_CONST(3)
#define PMC_IMPL_IO_SYS_DPD_OFF_MASK_0_SOC_GPIO27_FIELD                 MK_FIELD_CONST(0x1, PMC_IMPL_IO_SYS_DPD_OFF_MASK_0_SOC_GPIO27_SHIFT)
#define PMC_IMPL_IO_SYS_DPD_OFF_MASK_0_SOC_GPIO27_RANGE                 3:3
#define PMC_IMPL_IO_SYS_DPD_OFF_MASK_0_SOC_GPIO27_MSB                   MK_SHIFT_CONST(3)
#define PMC_IMPL_IO_SYS_DPD_OFF_MASK_0_SOC_GPIO27_LSB                   MK_SHIFT_CONST(3)
#define PMC_IMPL_IO_SYS_DPD_OFF_MASK_0_SOC_GPIO27_WOFFSET                       0x0
#define PMC_IMPL_IO_SYS_DPD_OFF_MASK_0_SOC_GPIO27_DEFAULT                       MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_SYS_DPD_OFF_MASK_0_SOC_GPIO27_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_SYS_DPD_OFF_MASK_0_SOC_GPIO27_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_SYS_DPD_OFF_MASK_0_SOC_GPIO27_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_SYS_DPD_OFF_MASK_0_SOC_GPIO27_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_SYS_DPD_OFF_MASK_0_SOC_GPIO27_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_SYS_DPD_OFF_MASK_0_SOC_GPIO27_OFF                   MK_ENUM_CONST(0)
#define PMC_IMPL_IO_SYS_DPD_OFF_MASK_0_SOC_GPIO27_ON                    MK_ENUM_CONST(1)

// On - AO_RETENTION_N PAD(s) are masked to enter Deep Power Down mode from SC7 controller, Off - AO_RETENTION_N PAD(s) are free to enter Deep Power Down mode
#define PMC_IMPL_IO_SYS_DPD_OFF_MASK_0_AO_RETENTION_N_SHIFT                     MK_SHIFT_CONST(4)
#define PMC_IMPL_IO_SYS_DPD_OFF_MASK_0_AO_RETENTION_N_FIELD                     MK_FIELD_CONST(0x1, PMC_IMPL_IO_SYS_DPD_OFF_MASK_0_AO_RETENTION_N_SHIFT)
#define PMC_IMPL_IO_SYS_DPD_OFF_MASK_0_AO_RETENTION_N_RANGE                     4:4
#define PMC_IMPL_IO_SYS_DPD_OFF_MASK_0_AO_RETENTION_N_MSB                       MK_SHIFT_CONST(4)
#define PMC_IMPL_IO_SYS_DPD_OFF_MASK_0_AO_RETENTION_N_LSB                       MK_SHIFT_CONST(4)
#define PMC_IMPL_IO_SYS_DPD_OFF_MASK_0_AO_RETENTION_N_WOFFSET                   0x0
#define PMC_IMPL_IO_SYS_DPD_OFF_MASK_0_AO_RETENTION_N_DEFAULT                   MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_SYS_DPD_OFF_MASK_0_AO_RETENTION_N_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_SYS_DPD_OFF_MASK_0_AO_RETENTION_N_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_SYS_DPD_OFF_MASK_0_AO_RETENTION_N_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_SYS_DPD_OFF_MASK_0_AO_RETENTION_N_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_SYS_DPD_OFF_MASK_0_AO_RETENTION_N_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_SYS_DPD_OFF_MASK_0_AO_RETENTION_N_OFF                       MK_ENUM_CONST(0)
#define PMC_IMPL_IO_SYS_DPD_OFF_MASK_0_AO_RETENTION_N_ON                        MK_ENUM_CONST(1)

// On - BATT_OC PAD(s) are masked to enter Deep Power Down mode from SC7 controller, Off - BATT_OC PAD(s) are free to enter Deep Power Down mode
#define PMC_IMPL_IO_SYS_DPD_OFF_MASK_0_BATT_OC_SHIFT                    MK_SHIFT_CONST(5)
#define PMC_IMPL_IO_SYS_DPD_OFF_MASK_0_BATT_OC_FIELD                    MK_FIELD_CONST(0x1, PMC_IMPL_IO_SYS_DPD_OFF_MASK_0_BATT_OC_SHIFT)
#define PMC_IMPL_IO_SYS_DPD_OFF_MASK_0_BATT_OC_RANGE                    5:5
#define PMC_IMPL_IO_SYS_DPD_OFF_MASK_0_BATT_OC_MSB                      MK_SHIFT_CONST(5)
#define PMC_IMPL_IO_SYS_DPD_OFF_MASK_0_BATT_OC_LSB                      MK_SHIFT_CONST(5)
#define PMC_IMPL_IO_SYS_DPD_OFF_MASK_0_BATT_OC_WOFFSET                  0x0
#define PMC_IMPL_IO_SYS_DPD_OFF_MASK_0_BATT_OC_DEFAULT                  MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_SYS_DPD_OFF_MASK_0_BATT_OC_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_SYS_DPD_OFF_MASK_0_BATT_OC_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_SYS_DPD_OFF_MASK_0_BATT_OC_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_SYS_DPD_OFF_MASK_0_BATT_OC_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_SYS_DPD_OFF_MASK_0_BATT_OC_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_SYS_DPD_OFF_MASK_0_BATT_OC_OFF                      MK_ENUM_CONST(0)
#define PMC_IMPL_IO_SYS_DPD_OFF_MASK_0_BATT_OC_ON                       MK_ENUM_CONST(1)

// On - BOOTV_CTL_N PAD(s) are masked to enter Deep Power Down mode from SC7 controller, Off - BOOTV_CTL_N PAD(s) are free to enter Deep Power Down mode
#define PMC_IMPL_IO_SYS_DPD_OFF_MASK_0_BOOTV_CTL_N_SHIFT                        MK_SHIFT_CONST(6)
#define PMC_IMPL_IO_SYS_DPD_OFF_MASK_0_BOOTV_CTL_N_FIELD                        MK_FIELD_CONST(0x1, PMC_IMPL_IO_SYS_DPD_OFF_MASK_0_BOOTV_CTL_N_SHIFT)
#define PMC_IMPL_IO_SYS_DPD_OFF_MASK_0_BOOTV_CTL_N_RANGE                        6:6
#define PMC_IMPL_IO_SYS_DPD_OFF_MASK_0_BOOTV_CTL_N_MSB                  MK_SHIFT_CONST(6)
#define PMC_IMPL_IO_SYS_DPD_OFF_MASK_0_BOOTV_CTL_N_LSB                  MK_SHIFT_CONST(6)
#define PMC_IMPL_IO_SYS_DPD_OFF_MASK_0_BOOTV_CTL_N_WOFFSET                      0x0
#define PMC_IMPL_IO_SYS_DPD_OFF_MASK_0_BOOTV_CTL_N_DEFAULT                      MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_SYS_DPD_OFF_MASK_0_BOOTV_CTL_N_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_SYS_DPD_OFF_MASK_0_BOOTV_CTL_N_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_SYS_DPD_OFF_MASK_0_BOOTV_CTL_N_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_SYS_DPD_OFF_MASK_0_BOOTV_CTL_N_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_SYS_DPD_OFF_MASK_0_BOOTV_CTL_N_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_SYS_DPD_OFF_MASK_0_BOOTV_CTL_N_OFF                  MK_ENUM_CONST(0)
#define PMC_IMPL_IO_SYS_DPD_OFF_MASK_0_BOOTV_CTL_N_ON                   MK_ENUM_CONST(1)

// On - POWER_ON PAD(s) are masked to enter Deep Power Down mode from SC7 controller, Off - POWER_ON PAD(s) are free to enter Deep Power Down mode
#define PMC_IMPL_IO_SYS_DPD_OFF_MASK_0_POWER_ON_SHIFT                   MK_SHIFT_CONST(7)
#define PMC_IMPL_IO_SYS_DPD_OFF_MASK_0_POWER_ON_FIELD                   MK_FIELD_CONST(0x1, PMC_IMPL_IO_SYS_DPD_OFF_MASK_0_POWER_ON_SHIFT)
#define PMC_IMPL_IO_SYS_DPD_OFF_MASK_0_POWER_ON_RANGE                   7:7
#define PMC_IMPL_IO_SYS_DPD_OFF_MASK_0_POWER_ON_MSB                     MK_SHIFT_CONST(7)
#define PMC_IMPL_IO_SYS_DPD_OFF_MASK_0_POWER_ON_LSB                     MK_SHIFT_CONST(7)
#define PMC_IMPL_IO_SYS_DPD_OFF_MASK_0_POWER_ON_WOFFSET                 0x0
#define PMC_IMPL_IO_SYS_DPD_OFF_MASK_0_POWER_ON_DEFAULT                 MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_SYS_DPD_OFF_MASK_0_POWER_ON_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_SYS_DPD_OFF_MASK_0_POWER_ON_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_SYS_DPD_OFF_MASK_0_POWER_ON_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_SYS_DPD_OFF_MASK_0_POWER_ON_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_SYS_DPD_OFF_MASK_0_POWER_ON_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_SYS_DPD_OFF_MASK_0_POWER_ON_OFF                     MK_ENUM_CONST(0)
#define PMC_IMPL_IO_SYS_DPD_OFF_MASK_0_POWER_ON_ON                      MK_ENUM_CONST(1)

// On - HDMI_CEC PAD(s) are masked to enter Deep Power Down mode from SC7 controller, Off - HDMI_CEC PAD(s) are free to enter Deep Power Down mode
#define PMC_IMPL_IO_SYS_DPD_OFF_MASK_0_HDMI_CEC_SHIFT                   MK_SHIFT_CONST(8)
#define PMC_IMPL_IO_SYS_DPD_OFF_MASK_0_HDMI_CEC_FIELD                   MK_FIELD_CONST(0x1, PMC_IMPL_IO_SYS_DPD_OFF_MASK_0_HDMI_CEC_SHIFT)
#define PMC_IMPL_IO_SYS_DPD_OFF_MASK_0_HDMI_CEC_RANGE                   8:8
#define PMC_IMPL_IO_SYS_DPD_OFF_MASK_0_HDMI_CEC_MSB                     MK_SHIFT_CONST(8)
#define PMC_IMPL_IO_SYS_DPD_OFF_MASK_0_HDMI_CEC_LSB                     MK_SHIFT_CONST(8)
#define PMC_IMPL_IO_SYS_DPD_OFF_MASK_0_HDMI_CEC_WOFFSET                 0x0
#define PMC_IMPL_IO_SYS_DPD_OFF_MASK_0_HDMI_CEC_DEFAULT                 MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_SYS_DPD_OFF_MASK_0_HDMI_CEC_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_SYS_DPD_OFF_MASK_0_HDMI_CEC_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_SYS_DPD_OFF_MASK_0_HDMI_CEC_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_SYS_DPD_OFF_MASK_0_HDMI_CEC_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_SYS_DPD_OFF_MASK_0_HDMI_CEC_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_SYS_DPD_OFF_MASK_0_HDMI_CEC_OFF                     MK_ENUM_CONST(0)
#define PMC_IMPL_IO_SYS_DPD_OFF_MASK_0_HDMI_CEC_ON                      MK_ENUM_CONST(1)


// Register PMC_IMPL_IO_AO_DPD_REQ_0
#define PMC_IMPL_IO_AO_DPD_REQ_0                        MK_ADDR_CONST(0xe020)
#define PMC_IMPL_IO_AO_DPD_REQ_0_SECURE                         0x0
#define PMC_IMPL_IO_AO_DPD_REQ_0_DUAL                   0x0
#define PMC_IMPL_IO_AO_DPD_REQ_0_SCR                    IO_AO_SCR_0
#define PMC_IMPL_IO_AO_DPD_REQ_0_SCRREG                         PMC_IMPL_SCR_IO_AO_SCR_0
#define PMC_IMPL_IO_AO_DPD_REQ_0_WORD_COUNT                     0x1
#define PMC_IMPL_IO_AO_DPD_REQ_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_AO_DPD_REQ_0_RESET_MASK                     MK_MASK_CONST(0xc00007ff)
#define PMC_IMPL_IO_AO_DPD_REQ_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_AO_DPD_REQ_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_AO_DPD_REQ_0_READ_MASK                      MK_MASK_CONST(0xc00007ff)
#define PMC_IMPL_IO_AO_DPD_REQ_0_WRITE_MASK                     MK_MASK_CONST(0xc00007ff)
// code of operation for all set bits
#define PMC_IMPL_IO_AO_DPD_REQ_0_CODE_SHIFT                     MK_SHIFT_CONST(30)
#define PMC_IMPL_IO_AO_DPD_REQ_0_CODE_FIELD                     MK_FIELD_CONST(0x3, PMC_IMPL_IO_AO_DPD_REQ_0_CODE_SHIFT)
#define PMC_IMPL_IO_AO_DPD_REQ_0_CODE_RANGE                     31:30
#define PMC_IMPL_IO_AO_DPD_REQ_0_CODE_MSB                       MK_SHIFT_CONST(31)
#define PMC_IMPL_IO_AO_DPD_REQ_0_CODE_LSB                       MK_SHIFT_CONST(30)
#define PMC_IMPL_IO_AO_DPD_REQ_0_CODE_WOFFSET                   0x0
#define PMC_IMPL_IO_AO_DPD_REQ_0_CODE_DEFAULT                   MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_AO_DPD_REQ_0_CODE_DEFAULT_MASK                      MK_MASK_CONST(0x3)
#define PMC_IMPL_IO_AO_DPD_REQ_0_CODE_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_AO_DPD_REQ_0_CODE_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_AO_DPD_REQ_0_CODE_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_AO_DPD_REQ_0_CODE_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_AO_DPD_REQ_0_CODE_IDLE                      MK_ENUM_CONST(0)
#define PMC_IMPL_IO_AO_DPD_REQ_0_CODE_DPD_OFF                   MK_ENUM_CONST(1)
#define PMC_IMPL_IO_AO_DPD_REQ_0_CODE_DPD_ON                    MK_ENUM_CONST(2)

// puts SPI2_SCK PAD(s) in/out of Depp Power Down (DPD) mode
#define PMC_IMPL_IO_AO_DPD_REQ_0_SPI2_SCK_SHIFT                 MK_SHIFT_CONST(0)
#define PMC_IMPL_IO_AO_DPD_REQ_0_SPI2_SCK_FIELD                 MK_FIELD_CONST(0x1, PMC_IMPL_IO_AO_DPD_REQ_0_SPI2_SCK_SHIFT)
#define PMC_IMPL_IO_AO_DPD_REQ_0_SPI2_SCK_RANGE                 0:0
#define PMC_IMPL_IO_AO_DPD_REQ_0_SPI2_SCK_MSB                   MK_SHIFT_CONST(0)
#define PMC_IMPL_IO_AO_DPD_REQ_0_SPI2_SCK_LSB                   MK_SHIFT_CONST(0)
#define PMC_IMPL_IO_AO_DPD_REQ_0_SPI2_SCK_WOFFSET                       0x0
#define PMC_IMPL_IO_AO_DPD_REQ_0_SPI2_SCK_DEFAULT                       MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_AO_DPD_REQ_0_SPI2_SCK_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_AO_DPD_REQ_0_SPI2_SCK_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_AO_DPD_REQ_0_SPI2_SCK_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_AO_DPD_REQ_0_SPI2_SCK_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_AO_DPD_REQ_0_SPI2_SCK_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_AO_DPD_REQ_0_SPI2_SCK_OFF                   MK_ENUM_CONST(0)
#define PMC_IMPL_IO_AO_DPD_REQ_0_SPI2_SCK_ON                    MK_ENUM_CONST(1)

// puts SPI2_MISO PAD(s) in/out of Depp Power Down (DPD) mode
#define PMC_IMPL_IO_AO_DPD_REQ_0_SPI2_MISO_SHIFT                        MK_SHIFT_CONST(1)
#define PMC_IMPL_IO_AO_DPD_REQ_0_SPI2_MISO_FIELD                        MK_FIELD_CONST(0x1, PMC_IMPL_IO_AO_DPD_REQ_0_SPI2_MISO_SHIFT)
#define PMC_IMPL_IO_AO_DPD_REQ_0_SPI2_MISO_RANGE                        1:1
#define PMC_IMPL_IO_AO_DPD_REQ_0_SPI2_MISO_MSB                  MK_SHIFT_CONST(1)
#define PMC_IMPL_IO_AO_DPD_REQ_0_SPI2_MISO_LSB                  MK_SHIFT_CONST(1)
#define PMC_IMPL_IO_AO_DPD_REQ_0_SPI2_MISO_WOFFSET                      0x0
#define PMC_IMPL_IO_AO_DPD_REQ_0_SPI2_MISO_DEFAULT                      MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_AO_DPD_REQ_0_SPI2_MISO_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_AO_DPD_REQ_0_SPI2_MISO_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_AO_DPD_REQ_0_SPI2_MISO_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_AO_DPD_REQ_0_SPI2_MISO_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_AO_DPD_REQ_0_SPI2_MISO_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_AO_DPD_REQ_0_SPI2_MISO_OFF                  MK_ENUM_CONST(0)
#define PMC_IMPL_IO_AO_DPD_REQ_0_SPI2_MISO_ON                   MK_ENUM_CONST(1)

// puts SPI2_MOSI PAD(s) in/out of Depp Power Down (DPD) mode
#define PMC_IMPL_IO_AO_DPD_REQ_0_SPI2_MOSI_SHIFT                        MK_SHIFT_CONST(2)
#define PMC_IMPL_IO_AO_DPD_REQ_0_SPI2_MOSI_FIELD                        MK_FIELD_CONST(0x1, PMC_IMPL_IO_AO_DPD_REQ_0_SPI2_MOSI_SHIFT)
#define PMC_IMPL_IO_AO_DPD_REQ_0_SPI2_MOSI_RANGE                        2:2
#define PMC_IMPL_IO_AO_DPD_REQ_0_SPI2_MOSI_MSB                  MK_SHIFT_CONST(2)
#define PMC_IMPL_IO_AO_DPD_REQ_0_SPI2_MOSI_LSB                  MK_SHIFT_CONST(2)
#define PMC_IMPL_IO_AO_DPD_REQ_0_SPI2_MOSI_WOFFSET                      0x0
#define PMC_IMPL_IO_AO_DPD_REQ_0_SPI2_MOSI_DEFAULT                      MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_AO_DPD_REQ_0_SPI2_MOSI_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_AO_DPD_REQ_0_SPI2_MOSI_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_AO_DPD_REQ_0_SPI2_MOSI_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_AO_DPD_REQ_0_SPI2_MOSI_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_AO_DPD_REQ_0_SPI2_MOSI_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_AO_DPD_REQ_0_SPI2_MOSI_OFF                  MK_ENUM_CONST(0)
#define PMC_IMPL_IO_AO_DPD_REQ_0_SPI2_MOSI_ON                   MK_ENUM_CONST(1)

// puts SPI2_CS0 PAD(s) in/out of Depp Power Down (DPD) mode
#define PMC_IMPL_IO_AO_DPD_REQ_0_SPI2_CS0_SHIFT                 MK_SHIFT_CONST(3)
#define PMC_IMPL_IO_AO_DPD_REQ_0_SPI2_CS0_FIELD                 MK_FIELD_CONST(0x1, PMC_IMPL_IO_AO_DPD_REQ_0_SPI2_CS0_SHIFT)
#define PMC_IMPL_IO_AO_DPD_REQ_0_SPI2_CS0_RANGE                 3:3
#define PMC_IMPL_IO_AO_DPD_REQ_0_SPI2_CS0_MSB                   MK_SHIFT_CONST(3)
#define PMC_IMPL_IO_AO_DPD_REQ_0_SPI2_CS0_LSB                   MK_SHIFT_CONST(3)
#define PMC_IMPL_IO_AO_DPD_REQ_0_SPI2_CS0_WOFFSET                       0x0
#define PMC_IMPL_IO_AO_DPD_REQ_0_SPI2_CS0_DEFAULT                       MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_AO_DPD_REQ_0_SPI2_CS0_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_AO_DPD_REQ_0_SPI2_CS0_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_AO_DPD_REQ_0_SPI2_CS0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_AO_DPD_REQ_0_SPI2_CS0_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_AO_DPD_REQ_0_SPI2_CS0_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_AO_DPD_REQ_0_SPI2_CS0_OFF                   MK_ENUM_CONST(0)
#define PMC_IMPL_IO_AO_DPD_REQ_0_SPI2_CS0_ON                    MK_ENUM_CONST(1)

// puts TOUCH_CLK PAD(s) in/out of Depp Power Down (DPD) mode
#define PMC_IMPL_IO_AO_DPD_REQ_0_TOUCH_CLK_SHIFT                        MK_SHIFT_CONST(4)
#define PMC_IMPL_IO_AO_DPD_REQ_0_TOUCH_CLK_FIELD                        MK_FIELD_CONST(0x1, PMC_IMPL_IO_AO_DPD_REQ_0_TOUCH_CLK_SHIFT)
#define PMC_IMPL_IO_AO_DPD_REQ_0_TOUCH_CLK_RANGE                        4:4
#define PMC_IMPL_IO_AO_DPD_REQ_0_TOUCH_CLK_MSB                  MK_SHIFT_CONST(4)
#define PMC_IMPL_IO_AO_DPD_REQ_0_TOUCH_CLK_LSB                  MK_SHIFT_CONST(4)
#define PMC_IMPL_IO_AO_DPD_REQ_0_TOUCH_CLK_WOFFSET                      0x0
#define PMC_IMPL_IO_AO_DPD_REQ_0_TOUCH_CLK_DEFAULT                      MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_AO_DPD_REQ_0_TOUCH_CLK_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_AO_DPD_REQ_0_TOUCH_CLK_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_AO_DPD_REQ_0_TOUCH_CLK_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_AO_DPD_REQ_0_TOUCH_CLK_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_AO_DPD_REQ_0_TOUCH_CLK_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_AO_DPD_REQ_0_TOUCH_CLK_OFF                  MK_ENUM_CONST(0)
#define PMC_IMPL_IO_AO_DPD_REQ_0_TOUCH_CLK_ON                   MK_ENUM_CONST(1)

// puts UART3_TX PAD(s) in/out of Depp Power Down (DPD) mode
#define PMC_IMPL_IO_AO_DPD_REQ_0_UART3_TX_SHIFT                 MK_SHIFT_CONST(5)
#define PMC_IMPL_IO_AO_DPD_REQ_0_UART3_TX_FIELD                 MK_FIELD_CONST(0x1, PMC_IMPL_IO_AO_DPD_REQ_0_UART3_TX_SHIFT)
#define PMC_IMPL_IO_AO_DPD_REQ_0_UART3_TX_RANGE                 5:5
#define PMC_IMPL_IO_AO_DPD_REQ_0_UART3_TX_MSB                   MK_SHIFT_CONST(5)
#define PMC_IMPL_IO_AO_DPD_REQ_0_UART3_TX_LSB                   MK_SHIFT_CONST(5)
#define PMC_IMPL_IO_AO_DPD_REQ_0_UART3_TX_WOFFSET                       0x0
#define PMC_IMPL_IO_AO_DPD_REQ_0_UART3_TX_DEFAULT                       MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_AO_DPD_REQ_0_UART3_TX_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_AO_DPD_REQ_0_UART3_TX_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_AO_DPD_REQ_0_UART3_TX_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_AO_DPD_REQ_0_UART3_TX_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_AO_DPD_REQ_0_UART3_TX_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_AO_DPD_REQ_0_UART3_TX_OFF                   MK_ENUM_CONST(0)
#define PMC_IMPL_IO_AO_DPD_REQ_0_UART3_TX_ON                    MK_ENUM_CONST(1)

// puts UART3_RX PAD(s) in/out of Depp Power Down (DPD) mode
#define PMC_IMPL_IO_AO_DPD_REQ_0_UART3_RX_SHIFT                 MK_SHIFT_CONST(6)
#define PMC_IMPL_IO_AO_DPD_REQ_0_UART3_RX_FIELD                 MK_FIELD_CONST(0x1, PMC_IMPL_IO_AO_DPD_REQ_0_UART3_RX_SHIFT)
#define PMC_IMPL_IO_AO_DPD_REQ_0_UART3_RX_RANGE                 6:6
#define PMC_IMPL_IO_AO_DPD_REQ_0_UART3_RX_MSB                   MK_SHIFT_CONST(6)
#define PMC_IMPL_IO_AO_DPD_REQ_0_UART3_RX_LSB                   MK_SHIFT_CONST(6)
#define PMC_IMPL_IO_AO_DPD_REQ_0_UART3_RX_WOFFSET                       0x0
#define PMC_IMPL_IO_AO_DPD_REQ_0_UART3_RX_DEFAULT                       MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_AO_DPD_REQ_0_UART3_RX_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_AO_DPD_REQ_0_UART3_RX_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_AO_DPD_REQ_0_UART3_RX_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_AO_DPD_REQ_0_UART3_RX_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_AO_DPD_REQ_0_UART3_RX_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_AO_DPD_REQ_0_UART3_RX_OFF                   MK_ENUM_CONST(0)
#define PMC_IMPL_IO_AO_DPD_REQ_0_UART3_RX_ON                    MK_ENUM_CONST(1)

// puts GEN2_I2C_SCL PAD(s) in/out of Depp Power Down (DPD) mode
#define PMC_IMPL_IO_AO_DPD_REQ_0_GEN2_I2C_SCL_SHIFT                     MK_SHIFT_CONST(7)
#define PMC_IMPL_IO_AO_DPD_REQ_0_GEN2_I2C_SCL_FIELD                     MK_FIELD_CONST(0x1, PMC_IMPL_IO_AO_DPD_REQ_0_GEN2_I2C_SCL_SHIFT)
#define PMC_IMPL_IO_AO_DPD_REQ_0_GEN2_I2C_SCL_RANGE                     7:7
#define PMC_IMPL_IO_AO_DPD_REQ_0_GEN2_I2C_SCL_MSB                       MK_SHIFT_CONST(7)
#define PMC_IMPL_IO_AO_DPD_REQ_0_GEN2_I2C_SCL_LSB                       MK_SHIFT_CONST(7)
#define PMC_IMPL_IO_AO_DPD_REQ_0_GEN2_I2C_SCL_WOFFSET                   0x0
#define PMC_IMPL_IO_AO_DPD_REQ_0_GEN2_I2C_SCL_DEFAULT                   MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_AO_DPD_REQ_0_GEN2_I2C_SCL_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_AO_DPD_REQ_0_GEN2_I2C_SCL_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_AO_DPD_REQ_0_GEN2_I2C_SCL_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_AO_DPD_REQ_0_GEN2_I2C_SCL_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_AO_DPD_REQ_0_GEN2_I2C_SCL_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_AO_DPD_REQ_0_GEN2_I2C_SCL_OFF                       MK_ENUM_CONST(0)
#define PMC_IMPL_IO_AO_DPD_REQ_0_GEN2_I2C_SCL_ON                        MK_ENUM_CONST(1)

// puts GEN2_I2C_SDA PAD(s) in/out of Depp Power Down (DPD) mode
#define PMC_IMPL_IO_AO_DPD_REQ_0_GEN2_I2C_SDA_SHIFT                     MK_SHIFT_CONST(8)
#define PMC_IMPL_IO_AO_DPD_REQ_0_GEN2_I2C_SDA_FIELD                     MK_FIELD_CONST(0x1, PMC_IMPL_IO_AO_DPD_REQ_0_GEN2_I2C_SDA_SHIFT)
#define PMC_IMPL_IO_AO_DPD_REQ_0_GEN2_I2C_SDA_RANGE                     8:8
#define PMC_IMPL_IO_AO_DPD_REQ_0_GEN2_I2C_SDA_MSB                       MK_SHIFT_CONST(8)
#define PMC_IMPL_IO_AO_DPD_REQ_0_GEN2_I2C_SDA_LSB                       MK_SHIFT_CONST(8)
#define PMC_IMPL_IO_AO_DPD_REQ_0_GEN2_I2C_SDA_WOFFSET                   0x0
#define PMC_IMPL_IO_AO_DPD_REQ_0_GEN2_I2C_SDA_DEFAULT                   MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_AO_DPD_REQ_0_GEN2_I2C_SDA_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_AO_DPD_REQ_0_GEN2_I2C_SDA_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_AO_DPD_REQ_0_GEN2_I2C_SDA_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_AO_DPD_REQ_0_GEN2_I2C_SDA_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_AO_DPD_REQ_0_GEN2_I2C_SDA_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_AO_DPD_REQ_0_GEN2_I2C_SDA_OFF                       MK_ENUM_CONST(0)
#define PMC_IMPL_IO_AO_DPD_REQ_0_GEN2_I2C_SDA_ON                        MK_ENUM_CONST(1)

// puts GEN8_I2C_SCL PAD(s) in/out of Depp Power Down (DPD) mode
#define PMC_IMPL_IO_AO_DPD_REQ_0_GEN8_I2C_SCL_SHIFT                     MK_SHIFT_CONST(9)
#define PMC_IMPL_IO_AO_DPD_REQ_0_GEN8_I2C_SCL_FIELD                     MK_FIELD_CONST(0x1, PMC_IMPL_IO_AO_DPD_REQ_0_GEN8_I2C_SCL_SHIFT)
#define PMC_IMPL_IO_AO_DPD_REQ_0_GEN8_I2C_SCL_RANGE                     9:9
#define PMC_IMPL_IO_AO_DPD_REQ_0_GEN8_I2C_SCL_MSB                       MK_SHIFT_CONST(9)
#define PMC_IMPL_IO_AO_DPD_REQ_0_GEN8_I2C_SCL_LSB                       MK_SHIFT_CONST(9)
#define PMC_IMPL_IO_AO_DPD_REQ_0_GEN8_I2C_SCL_WOFFSET                   0x0
#define PMC_IMPL_IO_AO_DPD_REQ_0_GEN8_I2C_SCL_DEFAULT                   MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_AO_DPD_REQ_0_GEN8_I2C_SCL_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_AO_DPD_REQ_0_GEN8_I2C_SCL_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_AO_DPD_REQ_0_GEN8_I2C_SCL_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_AO_DPD_REQ_0_GEN8_I2C_SCL_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_AO_DPD_REQ_0_GEN8_I2C_SCL_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_AO_DPD_REQ_0_GEN8_I2C_SCL_OFF                       MK_ENUM_CONST(0)
#define PMC_IMPL_IO_AO_DPD_REQ_0_GEN8_I2C_SCL_ON                        MK_ENUM_CONST(1)

// puts GEN8_I2C_SDA PAD(s) in/out of Depp Power Down (DPD) mode
#define PMC_IMPL_IO_AO_DPD_REQ_0_GEN8_I2C_SDA_SHIFT                     MK_SHIFT_CONST(10)
#define PMC_IMPL_IO_AO_DPD_REQ_0_GEN8_I2C_SDA_FIELD                     MK_FIELD_CONST(0x1, PMC_IMPL_IO_AO_DPD_REQ_0_GEN8_I2C_SDA_SHIFT)
#define PMC_IMPL_IO_AO_DPD_REQ_0_GEN8_I2C_SDA_RANGE                     10:10
#define PMC_IMPL_IO_AO_DPD_REQ_0_GEN8_I2C_SDA_MSB                       MK_SHIFT_CONST(10)
#define PMC_IMPL_IO_AO_DPD_REQ_0_GEN8_I2C_SDA_LSB                       MK_SHIFT_CONST(10)
#define PMC_IMPL_IO_AO_DPD_REQ_0_GEN8_I2C_SDA_WOFFSET                   0x0
#define PMC_IMPL_IO_AO_DPD_REQ_0_GEN8_I2C_SDA_DEFAULT                   MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_AO_DPD_REQ_0_GEN8_I2C_SDA_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_AO_DPD_REQ_0_GEN8_I2C_SDA_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_AO_DPD_REQ_0_GEN8_I2C_SDA_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_AO_DPD_REQ_0_GEN8_I2C_SDA_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_AO_DPD_REQ_0_GEN8_I2C_SDA_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_AO_DPD_REQ_0_GEN8_I2C_SDA_OFF                       MK_ENUM_CONST(0)
#define PMC_IMPL_IO_AO_DPD_REQ_0_GEN8_I2C_SDA_ON                        MK_ENUM_CONST(1)


// Register PMC_IMPL_IO_AO_DPD_STATUS_0
#define PMC_IMPL_IO_AO_DPD_STATUS_0                     MK_ADDR_CONST(0xe024)
#define PMC_IMPL_IO_AO_DPD_STATUS_0_SECURE                      0x0
#define PMC_IMPL_IO_AO_DPD_STATUS_0_DUAL                        0x0
#define PMC_IMPL_IO_AO_DPD_STATUS_0_SCR                         IO_AO_SCR_0
#define PMC_IMPL_IO_AO_DPD_STATUS_0_SCRREG                      PMC_IMPL_SCR_IO_AO_SCR_0
#define PMC_IMPL_IO_AO_DPD_STATUS_0_WORD_COUNT                  0x1
#define PMC_IMPL_IO_AO_DPD_STATUS_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_AO_DPD_STATUS_0_RESET_MASK                  MK_MASK_CONST(0x7ff)
#define PMC_IMPL_IO_AO_DPD_STATUS_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_AO_DPD_STATUS_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_AO_DPD_STATUS_0_READ_MASK                   MK_MASK_CONST(0x7ff)
#define PMC_IMPL_IO_AO_DPD_STATUS_0_WRITE_MASK                  MK_MASK_CONST(0x0)
// On - SPI2_SCK PAD(s) is in Deep Power Down mode, Off - SPI2_SCK PAD(s) is out of Deep Power Down mode
#define PMC_IMPL_IO_AO_DPD_STATUS_0_SPI2_SCK_SHIFT                      MK_SHIFT_CONST(0)
#define PMC_IMPL_IO_AO_DPD_STATUS_0_SPI2_SCK_FIELD                      MK_FIELD_CONST(0x1, PMC_IMPL_IO_AO_DPD_STATUS_0_SPI2_SCK_SHIFT)
#define PMC_IMPL_IO_AO_DPD_STATUS_0_SPI2_SCK_RANGE                      0:0
#define PMC_IMPL_IO_AO_DPD_STATUS_0_SPI2_SCK_MSB                        MK_SHIFT_CONST(0)
#define PMC_IMPL_IO_AO_DPD_STATUS_0_SPI2_SCK_LSB                        MK_SHIFT_CONST(0)
#define PMC_IMPL_IO_AO_DPD_STATUS_0_SPI2_SCK_WOFFSET                    0x0
#define PMC_IMPL_IO_AO_DPD_STATUS_0_SPI2_SCK_DEFAULT                    MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_AO_DPD_STATUS_0_SPI2_SCK_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_AO_DPD_STATUS_0_SPI2_SCK_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_AO_DPD_STATUS_0_SPI2_SCK_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_AO_DPD_STATUS_0_SPI2_SCK_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_AO_DPD_STATUS_0_SPI2_SCK_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_AO_DPD_STATUS_0_SPI2_SCK_OFF                        MK_ENUM_CONST(0)
#define PMC_IMPL_IO_AO_DPD_STATUS_0_SPI2_SCK_ON                 MK_ENUM_CONST(1)

// On - SPI2_MISO PAD(s) is in Deep Power Down mode, Off - SPI2_MISO PAD(s) is out of Deep Power Down mode
#define PMC_IMPL_IO_AO_DPD_STATUS_0_SPI2_MISO_SHIFT                     MK_SHIFT_CONST(1)
#define PMC_IMPL_IO_AO_DPD_STATUS_0_SPI2_MISO_FIELD                     MK_FIELD_CONST(0x1, PMC_IMPL_IO_AO_DPD_STATUS_0_SPI2_MISO_SHIFT)
#define PMC_IMPL_IO_AO_DPD_STATUS_0_SPI2_MISO_RANGE                     1:1
#define PMC_IMPL_IO_AO_DPD_STATUS_0_SPI2_MISO_MSB                       MK_SHIFT_CONST(1)
#define PMC_IMPL_IO_AO_DPD_STATUS_0_SPI2_MISO_LSB                       MK_SHIFT_CONST(1)
#define PMC_IMPL_IO_AO_DPD_STATUS_0_SPI2_MISO_WOFFSET                   0x0
#define PMC_IMPL_IO_AO_DPD_STATUS_0_SPI2_MISO_DEFAULT                   MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_AO_DPD_STATUS_0_SPI2_MISO_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_AO_DPD_STATUS_0_SPI2_MISO_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_AO_DPD_STATUS_0_SPI2_MISO_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_AO_DPD_STATUS_0_SPI2_MISO_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_AO_DPD_STATUS_0_SPI2_MISO_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_AO_DPD_STATUS_0_SPI2_MISO_OFF                       MK_ENUM_CONST(0)
#define PMC_IMPL_IO_AO_DPD_STATUS_0_SPI2_MISO_ON                        MK_ENUM_CONST(1)

// On - SPI2_MOSI PAD(s) is in Deep Power Down mode, Off - SPI2_MOSI PAD(s) is out of Deep Power Down mode
#define PMC_IMPL_IO_AO_DPD_STATUS_0_SPI2_MOSI_SHIFT                     MK_SHIFT_CONST(2)
#define PMC_IMPL_IO_AO_DPD_STATUS_0_SPI2_MOSI_FIELD                     MK_FIELD_CONST(0x1, PMC_IMPL_IO_AO_DPD_STATUS_0_SPI2_MOSI_SHIFT)
#define PMC_IMPL_IO_AO_DPD_STATUS_0_SPI2_MOSI_RANGE                     2:2
#define PMC_IMPL_IO_AO_DPD_STATUS_0_SPI2_MOSI_MSB                       MK_SHIFT_CONST(2)
#define PMC_IMPL_IO_AO_DPD_STATUS_0_SPI2_MOSI_LSB                       MK_SHIFT_CONST(2)
#define PMC_IMPL_IO_AO_DPD_STATUS_0_SPI2_MOSI_WOFFSET                   0x0
#define PMC_IMPL_IO_AO_DPD_STATUS_0_SPI2_MOSI_DEFAULT                   MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_AO_DPD_STATUS_0_SPI2_MOSI_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_AO_DPD_STATUS_0_SPI2_MOSI_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_AO_DPD_STATUS_0_SPI2_MOSI_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_AO_DPD_STATUS_0_SPI2_MOSI_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_AO_DPD_STATUS_0_SPI2_MOSI_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_AO_DPD_STATUS_0_SPI2_MOSI_OFF                       MK_ENUM_CONST(0)
#define PMC_IMPL_IO_AO_DPD_STATUS_0_SPI2_MOSI_ON                        MK_ENUM_CONST(1)

// On - SPI2_CS0 PAD(s) is in Deep Power Down mode, Off - SPI2_CS0 PAD(s) is out of Deep Power Down mode
#define PMC_IMPL_IO_AO_DPD_STATUS_0_SPI2_CS0_SHIFT                      MK_SHIFT_CONST(3)
#define PMC_IMPL_IO_AO_DPD_STATUS_0_SPI2_CS0_FIELD                      MK_FIELD_CONST(0x1, PMC_IMPL_IO_AO_DPD_STATUS_0_SPI2_CS0_SHIFT)
#define PMC_IMPL_IO_AO_DPD_STATUS_0_SPI2_CS0_RANGE                      3:3
#define PMC_IMPL_IO_AO_DPD_STATUS_0_SPI2_CS0_MSB                        MK_SHIFT_CONST(3)
#define PMC_IMPL_IO_AO_DPD_STATUS_0_SPI2_CS0_LSB                        MK_SHIFT_CONST(3)
#define PMC_IMPL_IO_AO_DPD_STATUS_0_SPI2_CS0_WOFFSET                    0x0
#define PMC_IMPL_IO_AO_DPD_STATUS_0_SPI2_CS0_DEFAULT                    MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_AO_DPD_STATUS_0_SPI2_CS0_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_AO_DPD_STATUS_0_SPI2_CS0_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_AO_DPD_STATUS_0_SPI2_CS0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_AO_DPD_STATUS_0_SPI2_CS0_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_AO_DPD_STATUS_0_SPI2_CS0_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_AO_DPD_STATUS_0_SPI2_CS0_OFF                        MK_ENUM_CONST(0)
#define PMC_IMPL_IO_AO_DPD_STATUS_0_SPI2_CS0_ON                 MK_ENUM_CONST(1)

// On - TOUCH_CLK PAD(s) is in Deep Power Down mode, Off - TOUCH_CLK PAD(s) is out of Deep Power Down mode
#define PMC_IMPL_IO_AO_DPD_STATUS_0_TOUCH_CLK_SHIFT                     MK_SHIFT_CONST(4)
#define PMC_IMPL_IO_AO_DPD_STATUS_0_TOUCH_CLK_FIELD                     MK_FIELD_CONST(0x1, PMC_IMPL_IO_AO_DPD_STATUS_0_TOUCH_CLK_SHIFT)
#define PMC_IMPL_IO_AO_DPD_STATUS_0_TOUCH_CLK_RANGE                     4:4
#define PMC_IMPL_IO_AO_DPD_STATUS_0_TOUCH_CLK_MSB                       MK_SHIFT_CONST(4)
#define PMC_IMPL_IO_AO_DPD_STATUS_0_TOUCH_CLK_LSB                       MK_SHIFT_CONST(4)
#define PMC_IMPL_IO_AO_DPD_STATUS_0_TOUCH_CLK_WOFFSET                   0x0
#define PMC_IMPL_IO_AO_DPD_STATUS_0_TOUCH_CLK_DEFAULT                   MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_AO_DPD_STATUS_0_TOUCH_CLK_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_AO_DPD_STATUS_0_TOUCH_CLK_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_AO_DPD_STATUS_0_TOUCH_CLK_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_AO_DPD_STATUS_0_TOUCH_CLK_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_AO_DPD_STATUS_0_TOUCH_CLK_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_AO_DPD_STATUS_0_TOUCH_CLK_OFF                       MK_ENUM_CONST(0)
#define PMC_IMPL_IO_AO_DPD_STATUS_0_TOUCH_CLK_ON                        MK_ENUM_CONST(1)

// On - UART3_TX PAD(s) is in Deep Power Down mode, Off - UART3_TX PAD(s) is out of Deep Power Down mode
#define PMC_IMPL_IO_AO_DPD_STATUS_0_UART3_TX_SHIFT                      MK_SHIFT_CONST(5)
#define PMC_IMPL_IO_AO_DPD_STATUS_0_UART3_TX_FIELD                      MK_FIELD_CONST(0x1, PMC_IMPL_IO_AO_DPD_STATUS_0_UART3_TX_SHIFT)
#define PMC_IMPL_IO_AO_DPD_STATUS_0_UART3_TX_RANGE                      5:5
#define PMC_IMPL_IO_AO_DPD_STATUS_0_UART3_TX_MSB                        MK_SHIFT_CONST(5)
#define PMC_IMPL_IO_AO_DPD_STATUS_0_UART3_TX_LSB                        MK_SHIFT_CONST(5)
#define PMC_IMPL_IO_AO_DPD_STATUS_0_UART3_TX_WOFFSET                    0x0
#define PMC_IMPL_IO_AO_DPD_STATUS_0_UART3_TX_DEFAULT                    MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_AO_DPD_STATUS_0_UART3_TX_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_AO_DPD_STATUS_0_UART3_TX_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_AO_DPD_STATUS_0_UART3_TX_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_AO_DPD_STATUS_0_UART3_TX_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_AO_DPD_STATUS_0_UART3_TX_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_AO_DPD_STATUS_0_UART3_TX_OFF                        MK_ENUM_CONST(0)
#define PMC_IMPL_IO_AO_DPD_STATUS_0_UART3_TX_ON                 MK_ENUM_CONST(1)

// On - UART3_RX PAD(s) is in Deep Power Down mode, Off - UART3_RX PAD(s) is out of Deep Power Down mode
#define PMC_IMPL_IO_AO_DPD_STATUS_0_UART3_RX_SHIFT                      MK_SHIFT_CONST(6)
#define PMC_IMPL_IO_AO_DPD_STATUS_0_UART3_RX_FIELD                      MK_FIELD_CONST(0x1, PMC_IMPL_IO_AO_DPD_STATUS_0_UART3_RX_SHIFT)
#define PMC_IMPL_IO_AO_DPD_STATUS_0_UART3_RX_RANGE                      6:6
#define PMC_IMPL_IO_AO_DPD_STATUS_0_UART3_RX_MSB                        MK_SHIFT_CONST(6)
#define PMC_IMPL_IO_AO_DPD_STATUS_0_UART3_RX_LSB                        MK_SHIFT_CONST(6)
#define PMC_IMPL_IO_AO_DPD_STATUS_0_UART3_RX_WOFFSET                    0x0
#define PMC_IMPL_IO_AO_DPD_STATUS_0_UART3_RX_DEFAULT                    MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_AO_DPD_STATUS_0_UART3_RX_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_AO_DPD_STATUS_0_UART3_RX_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_AO_DPD_STATUS_0_UART3_RX_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_AO_DPD_STATUS_0_UART3_RX_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_AO_DPD_STATUS_0_UART3_RX_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_AO_DPD_STATUS_0_UART3_RX_OFF                        MK_ENUM_CONST(0)
#define PMC_IMPL_IO_AO_DPD_STATUS_0_UART3_RX_ON                 MK_ENUM_CONST(1)

// On - GEN2_I2C_SCL PAD(s) is in Deep Power Down mode, Off - GEN2_I2C_SCL PAD(s) is out of Deep Power Down mode
#define PMC_IMPL_IO_AO_DPD_STATUS_0_GEN2_I2C_SCL_SHIFT                  MK_SHIFT_CONST(7)
#define PMC_IMPL_IO_AO_DPD_STATUS_0_GEN2_I2C_SCL_FIELD                  MK_FIELD_CONST(0x1, PMC_IMPL_IO_AO_DPD_STATUS_0_GEN2_I2C_SCL_SHIFT)
#define PMC_IMPL_IO_AO_DPD_STATUS_0_GEN2_I2C_SCL_RANGE                  7:7
#define PMC_IMPL_IO_AO_DPD_STATUS_0_GEN2_I2C_SCL_MSB                    MK_SHIFT_CONST(7)
#define PMC_IMPL_IO_AO_DPD_STATUS_0_GEN2_I2C_SCL_LSB                    MK_SHIFT_CONST(7)
#define PMC_IMPL_IO_AO_DPD_STATUS_0_GEN2_I2C_SCL_WOFFSET                        0x0
#define PMC_IMPL_IO_AO_DPD_STATUS_0_GEN2_I2C_SCL_DEFAULT                        MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_AO_DPD_STATUS_0_GEN2_I2C_SCL_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_AO_DPD_STATUS_0_GEN2_I2C_SCL_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_AO_DPD_STATUS_0_GEN2_I2C_SCL_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_AO_DPD_STATUS_0_GEN2_I2C_SCL_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_AO_DPD_STATUS_0_GEN2_I2C_SCL_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_AO_DPD_STATUS_0_GEN2_I2C_SCL_OFF                    MK_ENUM_CONST(0)
#define PMC_IMPL_IO_AO_DPD_STATUS_0_GEN2_I2C_SCL_ON                     MK_ENUM_CONST(1)

// On - GEN2_I2C_SDA PAD(s) is in Deep Power Down mode, Off - GEN2_I2C_SDA PAD(s) is out of Deep Power Down mode
#define PMC_IMPL_IO_AO_DPD_STATUS_0_GEN2_I2C_SDA_SHIFT                  MK_SHIFT_CONST(8)
#define PMC_IMPL_IO_AO_DPD_STATUS_0_GEN2_I2C_SDA_FIELD                  MK_FIELD_CONST(0x1, PMC_IMPL_IO_AO_DPD_STATUS_0_GEN2_I2C_SDA_SHIFT)
#define PMC_IMPL_IO_AO_DPD_STATUS_0_GEN2_I2C_SDA_RANGE                  8:8
#define PMC_IMPL_IO_AO_DPD_STATUS_0_GEN2_I2C_SDA_MSB                    MK_SHIFT_CONST(8)
#define PMC_IMPL_IO_AO_DPD_STATUS_0_GEN2_I2C_SDA_LSB                    MK_SHIFT_CONST(8)
#define PMC_IMPL_IO_AO_DPD_STATUS_0_GEN2_I2C_SDA_WOFFSET                        0x0
#define PMC_IMPL_IO_AO_DPD_STATUS_0_GEN2_I2C_SDA_DEFAULT                        MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_AO_DPD_STATUS_0_GEN2_I2C_SDA_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_AO_DPD_STATUS_0_GEN2_I2C_SDA_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_AO_DPD_STATUS_0_GEN2_I2C_SDA_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_AO_DPD_STATUS_0_GEN2_I2C_SDA_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_AO_DPD_STATUS_0_GEN2_I2C_SDA_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_AO_DPD_STATUS_0_GEN2_I2C_SDA_OFF                    MK_ENUM_CONST(0)
#define PMC_IMPL_IO_AO_DPD_STATUS_0_GEN2_I2C_SDA_ON                     MK_ENUM_CONST(1)

// On - GEN8_I2C_SCL PAD(s) is in Deep Power Down mode, Off - GEN8_I2C_SCL PAD(s) is out of Deep Power Down mode
#define PMC_IMPL_IO_AO_DPD_STATUS_0_GEN8_I2C_SCL_SHIFT                  MK_SHIFT_CONST(9)
#define PMC_IMPL_IO_AO_DPD_STATUS_0_GEN8_I2C_SCL_FIELD                  MK_FIELD_CONST(0x1, PMC_IMPL_IO_AO_DPD_STATUS_0_GEN8_I2C_SCL_SHIFT)
#define PMC_IMPL_IO_AO_DPD_STATUS_0_GEN8_I2C_SCL_RANGE                  9:9
#define PMC_IMPL_IO_AO_DPD_STATUS_0_GEN8_I2C_SCL_MSB                    MK_SHIFT_CONST(9)
#define PMC_IMPL_IO_AO_DPD_STATUS_0_GEN8_I2C_SCL_LSB                    MK_SHIFT_CONST(9)
#define PMC_IMPL_IO_AO_DPD_STATUS_0_GEN8_I2C_SCL_WOFFSET                        0x0
#define PMC_IMPL_IO_AO_DPD_STATUS_0_GEN8_I2C_SCL_DEFAULT                        MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_AO_DPD_STATUS_0_GEN8_I2C_SCL_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_AO_DPD_STATUS_0_GEN8_I2C_SCL_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_AO_DPD_STATUS_0_GEN8_I2C_SCL_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_AO_DPD_STATUS_0_GEN8_I2C_SCL_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_AO_DPD_STATUS_0_GEN8_I2C_SCL_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_AO_DPD_STATUS_0_GEN8_I2C_SCL_OFF                    MK_ENUM_CONST(0)
#define PMC_IMPL_IO_AO_DPD_STATUS_0_GEN8_I2C_SCL_ON                     MK_ENUM_CONST(1)

// On - GEN8_I2C_SDA PAD(s) is in Deep Power Down mode, Off - GEN8_I2C_SDA PAD(s) is out of Deep Power Down mode
#define PMC_IMPL_IO_AO_DPD_STATUS_0_GEN8_I2C_SDA_SHIFT                  MK_SHIFT_CONST(10)
#define PMC_IMPL_IO_AO_DPD_STATUS_0_GEN8_I2C_SDA_FIELD                  MK_FIELD_CONST(0x1, PMC_IMPL_IO_AO_DPD_STATUS_0_GEN8_I2C_SDA_SHIFT)
#define PMC_IMPL_IO_AO_DPD_STATUS_0_GEN8_I2C_SDA_RANGE                  10:10
#define PMC_IMPL_IO_AO_DPD_STATUS_0_GEN8_I2C_SDA_MSB                    MK_SHIFT_CONST(10)
#define PMC_IMPL_IO_AO_DPD_STATUS_0_GEN8_I2C_SDA_LSB                    MK_SHIFT_CONST(10)
#define PMC_IMPL_IO_AO_DPD_STATUS_0_GEN8_I2C_SDA_WOFFSET                        0x0
#define PMC_IMPL_IO_AO_DPD_STATUS_0_GEN8_I2C_SDA_DEFAULT                        MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_AO_DPD_STATUS_0_GEN8_I2C_SDA_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_AO_DPD_STATUS_0_GEN8_I2C_SDA_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_AO_DPD_STATUS_0_GEN8_I2C_SDA_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_AO_DPD_STATUS_0_GEN8_I2C_SDA_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_AO_DPD_STATUS_0_GEN8_I2C_SDA_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_AO_DPD_STATUS_0_GEN8_I2C_SDA_OFF                    MK_ENUM_CONST(0)
#define PMC_IMPL_IO_AO_DPD_STATUS_0_GEN8_I2C_SDA_ON                     MK_ENUM_CONST(1)


// Register PMC_IMPL_IO_AO_DPD_OFF_MASK_0
#define PMC_IMPL_IO_AO_DPD_OFF_MASK_0                   MK_ADDR_CONST(0xe028)
#define PMC_IMPL_IO_AO_DPD_OFF_MASK_0_SECURE                    0x0
#define PMC_IMPL_IO_AO_DPD_OFF_MASK_0_DUAL                      0x0
#define PMC_IMPL_IO_AO_DPD_OFF_MASK_0_SCR                       IO_AO_SCR_0
#define PMC_IMPL_IO_AO_DPD_OFF_MASK_0_SCRREG                    PMC_IMPL_SCR_IO_AO_SCR_0
#define PMC_IMPL_IO_AO_DPD_OFF_MASK_0_WORD_COUNT                        0x1
#define PMC_IMPL_IO_AO_DPD_OFF_MASK_0_RESET_VAL                         MK_MASK_CONST(0x7ff)
#define PMC_IMPL_IO_AO_DPD_OFF_MASK_0_RESET_MASK                        MK_MASK_CONST(0x7ff)
#define PMC_IMPL_IO_AO_DPD_OFF_MASK_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_AO_DPD_OFF_MASK_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_AO_DPD_OFF_MASK_0_READ_MASK                         MK_MASK_CONST(0x7ff)
#define PMC_IMPL_IO_AO_DPD_OFF_MASK_0_WRITE_MASK                        MK_MASK_CONST(0x7ff)
// On - SPI2_SCK PAD(s) are masked to enter Deep Power Down mode from SC7 controller, Off - SPI2_SCK PAD(s) are free to enter Deep Power Down mode
#define PMC_IMPL_IO_AO_DPD_OFF_MASK_0_SPI2_SCK_SHIFT                    MK_SHIFT_CONST(0)
#define PMC_IMPL_IO_AO_DPD_OFF_MASK_0_SPI2_SCK_FIELD                    MK_FIELD_CONST(0x1, PMC_IMPL_IO_AO_DPD_OFF_MASK_0_SPI2_SCK_SHIFT)
#define PMC_IMPL_IO_AO_DPD_OFF_MASK_0_SPI2_SCK_RANGE                    0:0
#define PMC_IMPL_IO_AO_DPD_OFF_MASK_0_SPI2_SCK_MSB                      MK_SHIFT_CONST(0)
#define PMC_IMPL_IO_AO_DPD_OFF_MASK_0_SPI2_SCK_LSB                      MK_SHIFT_CONST(0)
#define PMC_IMPL_IO_AO_DPD_OFF_MASK_0_SPI2_SCK_WOFFSET                  0x0
#define PMC_IMPL_IO_AO_DPD_OFF_MASK_0_SPI2_SCK_DEFAULT                  MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_AO_DPD_OFF_MASK_0_SPI2_SCK_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_AO_DPD_OFF_MASK_0_SPI2_SCK_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_AO_DPD_OFF_MASK_0_SPI2_SCK_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_AO_DPD_OFF_MASK_0_SPI2_SCK_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_AO_DPD_OFF_MASK_0_SPI2_SCK_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_AO_DPD_OFF_MASK_0_SPI2_SCK_OFF                      MK_ENUM_CONST(0)
#define PMC_IMPL_IO_AO_DPD_OFF_MASK_0_SPI2_SCK_ON                       MK_ENUM_CONST(1)

// On - SPI2_MISO PAD(s) are masked to enter Deep Power Down mode from SC7 controller, Off - SPI2_MISO PAD(s) are free to enter Deep Power Down mode
#define PMC_IMPL_IO_AO_DPD_OFF_MASK_0_SPI2_MISO_SHIFT                   MK_SHIFT_CONST(1)
#define PMC_IMPL_IO_AO_DPD_OFF_MASK_0_SPI2_MISO_FIELD                   MK_FIELD_CONST(0x1, PMC_IMPL_IO_AO_DPD_OFF_MASK_0_SPI2_MISO_SHIFT)
#define PMC_IMPL_IO_AO_DPD_OFF_MASK_0_SPI2_MISO_RANGE                   1:1
#define PMC_IMPL_IO_AO_DPD_OFF_MASK_0_SPI2_MISO_MSB                     MK_SHIFT_CONST(1)
#define PMC_IMPL_IO_AO_DPD_OFF_MASK_0_SPI2_MISO_LSB                     MK_SHIFT_CONST(1)
#define PMC_IMPL_IO_AO_DPD_OFF_MASK_0_SPI2_MISO_WOFFSET                 0x0
#define PMC_IMPL_IO_AO_DPD_OFF_MASK_0_SPI2_MISO_DEFAULT                 MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_AO_DPD_OFF_MASK_0_SPI2_MISO_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_AO_DPD_OFF_MASK_0_SPI2_MISO_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_AO_DPD_OFF_MASK_0_SPI2_MISO_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_AO_DPD_OFF_MASK_0_SPI2_MISO_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_AO_DPD_OFF_MASK_0_SPI2_MISO_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_AO_DPD_OFF_MASK_0_SPI2_MISO_OFF                     MK_ENUM_CONST(0)
#define PMC_IMPL_IO_AO_DPD_OFF_MASK_0_SPI2_MISO_ON                      MK_ENUM_CONST(1)

// On - SPI2_MOSI PAD(s) are masked to enter Deep Power Down mode from SC7 controller, Off - SPI2_MOSI PAD(s) are free to enter Deep Power Down mode
#define PMC_IMPL_IO_AO_DPD_OFF_MASK_0_SPI2_MOSI_SHIFT                   MK_SHIFT_CONST(2)
#define PMC_IMPL_IO_AO_DPD_OFF_MASK_0_SPI2_MOSI_FIELD                   MK_FIELD_CONST(0x1, PMC_IMPL_IO_AO_DPD_OFF_MASK_0_SPI2_MOSI_SHIFT)
#define PMC_IMPL_IO_AO_DPD_OFF_MASK_0_SPI2_MOSI_RANGE                   2:2
#define PMC_IMPL_IO_AO_DPD_OFF_MASK_0_SPI2_MOSI_MSB                     MK_SHIFT_CONST(2)
#define PMC_IMPL_IO_AO_DPD_OFF_MASK_0_SPI2_MOSI_LSB                     MK_SHIFT_CONST(2)
#define PMC_IMPL_IO_AO_DPD_OFF_MASK_0_SPI2_MOSI_WOFFSET                 0x0
#define PMC_IMPL_IO_AO_DPD_OFF_MASK_0_SPI2_MOSI_DEFAULT                 MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_AO_DPD_OFF_MASK_0_SPI2_MOSI_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_AO_DPD_OFF_MASK_0_SPI2_MOSI_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_AO_DPD_OFF_MASK_0_SPI2_MOSI_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_AO_DPD_OFF_MASK_0_SPI2_MOSI_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_AO_DPD_OFF_MASK_0_SPI2_MOSI_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_AO_DPD_OFF_MASK_0_SPI2_MOSI_OFF                     MK_ENUM_CONST(0)
#define PMC_IMPL_IO_AO_DPD_OFF_MASK_0_SPI2_MOSI_ON                      MK_ENUM_CONST(1)

// On - SPI2_CS0 PAD(s) are masked to enter Deep Power Down mode from SC7 controller, Off - SPI2_CS0 PAD(s) are free to enter Deep Power Down mode
#define PMC_IMPL_IO_AO_DPD_OFF_MASK_0_SPI2_CS0_SHIFT                    MK_SHIFT_CONST(3)
#define PMC_IMPL_IO_AO_DPD_OFF_MASK_0_SPI2_CS0_FIELD                    MK_FIELD_CONST(0x1, PMC_IMPL_IO_AO_DPD_OFF_MASK_0_SPI2_CS0_SHIFT)
#define PMC_IMPL_IO_AO_DPD_OFF_MASK_0_SPI2_CS0_RANGE                    3:3
#define PMC_IMPL_IO_AO_DPD_OFF_MASK_0_SPI2_CS0_MSB                      MK_SHIFT_CONST(3)
#define PMC_IMPL_IO_AO_DPD_OFF_MASK_0_SPI2_CS0_LSB                      MK_SHIFT_CONST(3)
#define PMC_IMPL_IO_AO_DPD_OFF_MASK_0_SPI2_CS0_WOFFSET                  0x0
#define PMC_IMPL_IO_AO_DPD_OFF_MASK_0_SPI2_CS0_DEFAULT                  MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_AO_DPD_OFF_MASK_0_SPI2_CS0_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_AO_DPD_OFF_MASK_0_SPI2_CS0_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_AO_DPD_OFF_MASK_0_SPI2_CS0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_AO_DPD_OFF_MASK_0_SPI2_CS0_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_AO_DPD_OFF_MASK_0_SPI2_CS0_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_AO_DPD_OFF_MASK_0_SPI2_CS0_OFF                      MK_ENUM_CONST(0)
#define PMC_IMPL_IO_AO_DPD_OFF_MASK_0_SPI2_CS0_ON                       MK_ENUM_CONST(1)

// On - TOUCH_CLK PAD(s) are masked to enter Deep Power Down mode from SC7 controller, Off - TOUCH_CLK PAD(s) are free to enter Deep Power Down mode
#define PMC_IMPL_IO_AO_DPD_OFF_MASK_0_TOUCH_CLK_SHIFT                   MK_SHIFT_CONST(4)
#define PMC_IMPL_IO_AO_DPD_OFF_MASK_0_TOUCH_CLK_FIELD                   MK_FIELD_CONST(0x1, PMC_IMPL_IO_AO_DPD_OFF_MASK_0_TOUCH_CLK_SHIFT)
#define PMC_IMPL_IO_AO_DPD_OFF_MASK_0_TOUCH_CLK_RANGE                   4:4
#define PMC_IMPL_IO_AO_DPD_OFF_MASK_0_TOUCH_CLK_MSB                     MK_SHIFT_CONST(4)
#define PMC_IMPL_IO_AO_DPD_OFF_MASK_0_TOUCH_CLK_LSB                     MK_SHIFT_CONST(4)
#define PMC_IMPL_IO_AO_DPD_OFF_MASK_0_TOUCH_CLK_WOFFSET                 0x0
#define PMC_IMPL_IO_AO_DPD_OFF_MASK_0_TOUCH_CLK_DEFAULT                 MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_AO_DPD_OFF_MASK_0_TOUCH_CLK_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_AO_DPD_OFF_MASK_0_TOUCH_CLK_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_AO_DPD_OFF_MASK_0_TOUCH_CLK_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_AO_DPD_OFF_MASK_0_TOUCH_CLK_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_AO_DPD_OFF_MASK_0_TOUCH_CLK_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_AO_DPD_OFF_MASK_0_TOUCH_CLK_OFF                     MK_ENUM_CONST(0)
#define PMC_IMPL_IO_AO_DPD_OFF_MASK_0_TOUCH_CLK_ON                      MK_ENUM_CONST(1)

// On - UART3_TX PAD(s) are masked to enter Deep Power Down mode from SC7 controller, Off - UART3_TX PAD(s) are free to enter Deep Power Down mode
#define PMC_IMPL_IO_AO_DPD_OFF_MASK_0_UART3_TX_SHIFT                    MK_SHIFT_CONST(5)
#define PMC_IMPL_IO_AO_DPD_OFF_MASK_0_UART3_TX_FIELD                    MK_FIELD_CONST(0x1, PMC_IMPL_IO_AO_DPD_OFF_MASK_0_UART3_TX_SHIFT)
#define PMC_IMPL_IO_AO_DPD_OFF_MASK_0_UART3_TX_RANGE                    5:5
#define PMC_IMPL_IO_AO_DPD_OFF_MASK_0_UART3_TX_MSB                      MK_SHIFT_CONST(5)
#define PMC_IMPL_IO_AO_DPD_OFF_MASK_0_UART3_TX_LSB                      MK_SHIFT_CONST(5)
#define PMC_IMPL_IO_AO_DPD_OFF_MASK_0_UART3_TX_WOFFSET                  0x0
#define PMC_IMPL_IO_AO_DPD_OFF_MASK_0_UART3_TX_DEFAULT                  MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_AO_DPD_OFF_MASK_0_UART3_TX_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_AO_DPD_OFF_MASK_0_UART3_TX_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_AO_DPD_OFF_MASK_0_UART3_TX_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_AO_DPD_OFF_MASK_0_UART3_TX_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_AO_DPD_OFF_MASK_0_UART3_TX_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_AO_DPD_OFF_MASK_0_UART3_TX_OFF                      MK_ENUM_CONST(0)
#define PMC_IMPL_IO_AO_DPD_OFF_MASK_0_UART3_TX_ON                       MK_ENUM_CONST(1)

// On - UART3_RX PAD(s) are masked to enter Deep Power Down mode from SC7 controller, Off - UART3_RX PAD(s) are free to enter Deep Power Down mode
#define PMC_IMPL_IO_AO_DPD_OFF_MASK_0_UART3_RX_SHIFT                    MK_SHIFT_CONST(6)
#define PMC_IMPL_IO_AO_DPD_OFF_MASK_0_UART3_RX_FIELD                    MK_FIELD_CONST(0x1, PMC_IMPL_IO_AO_DPD_OFF_MASK_0_UART3_RX_SHIFT)
#define PMC_IMPL_IO_AO_DPD_OFF_MASK_0_UART3_RX_RANGE                    6:6
#define PMC_IMPL_IO_AO_DPD_OFF_MASK_0_UART3_RX_MSB                      MK_SHIFT_CONST(6)
#define PMC_IMPL_IO_AO_DPD_OFF_MASK_0_UART3_RX_LSB                      MK_SHIFT_CONST(6)
#define PMC_IMPL_IO_AO_DPD_OFF_MASK_0_UART3_RX_WOFFSET                  0x0
#define PMC_IMPL_IO_AO_DPD_OFF_MASK_0_UART3_RX_DEFAULT                  MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_AO_DPD_OFF_MASK_0_UART3_RX_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_AO_DPD_OFF_MASK_0_UART3_RX_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_AO_DPD_OFF_MASK_0_UART3_RX_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_AO_DPD_OFF_MASK_0_UART3_RX_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_AO_DPD_OFF_MASK_0_UART3_RX_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_AO_DPD_OFF_MASK_0_UART3_RX_OFF                      MK_ENUM_CONST(0)
#define PMC_IMPL_IO_AO_DPD_OFF_MASK_0_UART3_RX_ON                       MK_ENUM_CONST(1)

// On - GEN2_I2C_SCL PAD(s) are masked to enter Deep Power Down mode from SC7 controller, Off - GEN2_I2C_SCL PAD(s) are free to enter Deep Power Down mode
#define PMC_IMPL_IO_AO_DPD_OFF_MASK_0_GEN2_I2C_SCL_SHIFT                        MK_SHIFT_CONST(7)
#define PMC_IMPL_IO_AO_DPD_OFF_MASK_0_GEN2_I2C_SCL_FIELD                        MK_FIELD_CONST(0x1, PMC_IMPL_IO_AO_DPD_OFF_MASK_0_GEN2_I2C_SCL_SHIFT)
#define PMC_IMPL_IO_AO_DPD_OFF_MASK_0_GEN2_I2C_SCL_RANGE                        7:7
#define PMC_IMPL_IO_AO_DPD_OFF_MASK_0_GEN2_I2C_SCL_MSB                  MK_SHIFT_CONST(7)
#define PMC_IMPL_IO_AO_DPD_OFF_MASK_0_GEN2_I2C_SCL_LSB                  MK_SHIFT_CONST(7)
#define PMC_IMPL_IO_AO_DPD_OFF_MASK_0_GEN2_I2C_SCL_WOFFSET                      0x0
#define PMC_IMPL_IO_AO_DPD_OFF_MASK_0_GEN2_I2C_SCL_DEFAULT                      MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_AO_DPD_OFF_MASK_0_GEN2_I2C_SCL_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_AO_DPD_OFF_MASK_0_GEN2_I2C_SCL_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_AO_DPD_OFF_MASK_0_GEN2_I2C_SCL_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_AO_DPD_OFF_MASK_0_GEN2_I2C_SCL_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_AO_DPD_OFF_MASK_0_GEN2_I2C_SCL_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_AO_DPD_OFF_MASK_0_GEN2_I2C_SCL_OFF                  MK_ENUM_CONST(0)
#define PMC_IMPL_IO_AO_DPD_OFF_MASK_0_GEN2_I2C_SCL_ON                   MK_ENUM_CONST(1)

// On - GEN2_I2C_SDA PAD(s) are masked to enter Deep Power Down mode from SC7 controller, Off - GEN2_I2C_SDA PAD(s) are free to enter Deep Power Down mode
#define PMC_IMPL_IO_AO_DPD_OFF_MASK_0_GEN2_I2C_SDA_SHIFT                        MK_SHIFT_CONST(8)
#define PMC_IMPL_IO_AO_DPD_OFF_MASK_0_GEN2_I2C_SDA_FIELD                        MK_FIELD_CONST(0x1, PMC_IMPL_IO_AO_DPD_OFF_MASK_0_GEN2_I2C_SDA_SHIFT)
#define PMC_IMPL_IO_AO_DPD_OFF_MASK_0_GEN2_I2C_SDA_RANGE                        8:8
#define PMC_IMPL_IO_AO_DPD_OFF_MASK_0_GEN2_I2C_SDA_MSB                  MK_SHIFT_CONST(8)
#define PMC_IMPL_IO_AO_DPD_OFF_MASK_0_GEN2_I2C_SDA_LSB                  MK_SHIFT_CONST(8)
#define PMC_IMPL_IO_AO_DPD_OFF_MASK_0_GEN2_I2C_SDA_WOFFSET                      0x0
#define PMC_IMPL_IO_AO_DPD_OFF_MASK_0_GEN2_I2C_SDA_DEFAULT                      MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_AO_DPD_OFF_MASK_0_GEN2_I2C_SDA_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_AO_DPD_OFF_MASK_0_GEN2_I2C_SDA_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_AO_DPD_OFF_MASK_0_GEN2_I2C_SDA_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_AO_DPD_OFF_MASK_0_GEN2_I2C_SDA_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_AO_DPD_OFF_MASK_0_GEN2_I2C_SDA_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_AO_DPD_OFF_MASK_0_GEN2_I2C_SDA_OFF                  MK_ENUM_CONST(0)
#define PMC_IMPL_IO_AO_DPD_OFF_MASK_0_GEN2_I2C_SDA_ON                   MK_ENUM_CONST(1)

// On - GEN8_I2C_SCL PAD(s) are masked to enter Deep Power Down mode from SC7 controller, Off - GEN8_I2C_SCL PAD(s) are free to enter Deep Power Down mode
#define PMC_IMPL_IO_AO_DPD_OFF_MASK_0_GEN8_I2C_SCL_SHIFT                        MK_SHIFT_CONST(9)
#define PMC_IMPL_IO_AO_DPD_OFF_MASK_0_GEN8_I2C_SCL_FIELD                        MK_FIELD_CONST(0x1, PMC_IMPL_IO_AO_DPD_OFF_MASK_0_GEN8_I2C_SCL_SHIFT)
#define PMC_IMPL_IO_AO_DPD_OFF_MASK_0_GEN8_I2C_SCL_RANGE                        9:9
#define PMC_IMPL_IO_AO_DPD_OFF_MASK_0_GEN8_I2C_SCL_MSB                  MK_SHIFT_CONST(9)
#define PMC_IMPL_IO_AO_DPD_OFF_MASK_0_GEN8_I2C_SCL_LSB                  MK_SHIFT_CONST(9)
#define PMC_IMPL_IO_AO_DPD_OFF_MASK_0_GEN8_I2C_SCL_WOFFSET                      0x0
#define PMC_IMPL_IO_AO_DPD_OFF_MASK_0_GEN8_I2C_SCL_DEFAULT                      MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_AO_DPD_OFF_MASK_0_GEN8_I2C_SCL_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_AO_DPD_OFF_MASK_0_GEN8_I2C_SCL_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_AO_DPD_OFF_MASK_0_GEN8_I2C_SCL_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_AO_DPD_OFF_MASK_0_GEN8_I2C_SCL_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_AO_DPD_OFF_MASK_0_GEN8_I2C_SCL_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_AO_DPD_OFF_MASK_0_GEN8_I2C_SCL_OFF                  MK_ENUM_CONST(0)
#define PMC_IMPL_IO_AO_DPD_OFF_MASK_0_GEN8_I2C_SCL_ON                   MK_ENUM_CONST(1)

// On - GEN8_I2C_SDA PAD(s) are masked to enter Deep Power Down mode from SC7 controller, Off - GEN8_I2C_SDA PAD(s) are free to enter Deep Power Down mode
#define PMC_IMPL_IO_AO_DPD_OFF_MASK_0_GEN8_I2C_SDA_SHIFT                        MK_SHIFT_CONST(10)
#define PMC_IMPL_IO_AO_DPD_OFF_MASK_0_GEN8_I2C_SDA_FIELD                        MK_FIELD_CONST(0x1, PMC_IMPL_IO_AO_DPD_OFF_MASK_0_GEN8_I2C_SDA_SHIFT)
#define PMC_IMPL_IO_AO_DPD_OFF_MASK_0_GEN8_I2C_SDA_RANGE                        10:10
#define PMC_IMPL_IO_AO_DPD_OFF_MASK_0_GEN8_I2C_SDA_MSB                  MK_SHIFT_CONST(10)
#define PMC_IMPL_IO_AO_DPD_OFF_MASK_0_GEN8_I2C_SDA_LSB                  MK_SHIFT_CONST(10)
#define PMC_IMPL_IO_AO_DPD_OFF_MASK_0_GEN8_I2C_SDA_WOFFSET                      0x0
#define PMC_IMPL_IO_AO_DPD_OFF_MASK_0_GEN8_I2C_SDA_DEFAULT                      MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_AO_DPD_OFF_MASK_0_GEN8_I2C_SDA_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_AO_DPD_OFF_MASK_0_GEN8_I2C_SDA_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_AO_DPD_OFF_MASK_0_GEN8_I2C_SDA_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_AO_DPD_OFF_MASK_0_GEN8_I2C_SDA_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_AO_DPD_OFF_MASK_0_GEN8_I2C_SDA_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_AO_DPD_OFF_MASK_0_GEN8_I2C_SDA_OFF                  MK_ENUM_CONST(0)
#define PMC_IMPL_IO_AO_DPD_OFF_MASK_0_GEN8_I2C_SDA_ON                   MK_ENUM_CONST(1)


// Register PMC_IMPL_IO_DBG_DPD_REQ_0
#define PMC_IMPL_IO_DBG_DPD_REQ_0                       MK_ADDR_CONST(0xe02c)
#define PMC_IMPL_IO_DBG_DPD_REQ_0_SECURE                        0x0
#define PMC_IMPL_IO_DBG_DPD_REQ_0_DUAL                  0x0
#define PMC_IMPL_IO_DBG_DPD_REQ_0_SCR                   IO_DBG_SCR_0
#define PMC_IMPL_IO_DBG_DPD_REQ_0_SCRREG                        PMC_IMPL_SCR_IO_DBG_SCR_0
#define PMC_IMPL_IO_DBG_DPD_REQ_0_WORD_COUNT                    0x1
#define PMC_IMPL_IO_DBG_DPD_REQ_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DBG_DPD_REQ_0_RESET_MASK                    MK_MASK_CONST(0xc0000001)
#define PMC_IMPL_IO_DBG_DPD_REQ_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DBG_DPD_REQ_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DBG_DPD_REQ_0_READ_MASK                     MK_MASK_CONST(0xc0000001)
#define PMC_IMPL_IO_DBG_DPD_REQ_0_WRITE_MASK                    MK_MASK_CONST(0xc0000001)
// code of operation for all set bits
#define PMC_IMPL_IO_DBG_DPD_REQ_0_CODE_SHIFT                    MK_SHIFT_CONST(30)
#define PMC_IMPL_IO_DBG_DPD_REQ_0_CODE_FIELD                    MK_FIELD_CONST(0x3, PMC_IMPL_IO_DBG_DPD_REQ_0_CODE_SHIFT)
#define PMC_IMPL_IO_DBG_DPD_REQ_0_CODE_RANGE                    31:30
#define PMC_IMPL_IO_DBG_DPD_REQ_0_CODE_MSB                      MK_SHIFT_CONST(31)
#define PMC_IMPL_IO_DBG_DPD_REQ_0_CODE_LSB                      MK_SHIFT_CONST(30)
#define PMC_IMPL_IO_DBG_DPD_REQ_0_CODE_WOFFSET                  0x0
#define PMC_IMPL_IO_DBG_DPD_REQ_0_CODE_DEFAULT                  MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DBG_DPD_REQ_0_CODE_DEFAULT_MASK                     MK_MASK_CONST(0x3)
#define PMC_IMPL_IO_DBG_DPD_REQ_0_CODE_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DBG_DPD_REQ_0_CODE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DBG_DPD_REQ_0_CODE_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DBG_DPD_REQ_0_CODE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DBG_DPD_REQ_0_CODE_IDLE                     MK_ENUM_CONST(0)
#define PMC_IMPL_IO_DBG_DPD_REQ_0_CODE_DPD_OFF                  MK_ENUM_CONST(1)
#define PMC_IMPL_IO_DBG_DPD_REQ_0_CODE_DPD_ON                   MK_ENUM_CONST(2)

// puts SOC_GPIO08 PAD(s) in/out of Depp Power Down (DPD) mode
#define PMC_IMPL_IO_DBG_DPD_REQ_0_SOC_GPIO08_SHIFT                      MK_SHIFT_CONST(0)
#define PMC_IMPL_IO_DBG_DPD_REQ_0_SOC_GPIO08_FIELD                      MK_FIELD_CONST(0x1, PMC_IMPL_IO_DBG_DPD_REQ_0_SOC_GPIO08_SHIFT)
#define PMC_IMPL_IO_DBG_DPD_REQ_0_SOC_GPIO08_RANGE                      0:0
#define PMC_IMPL_IO_DBG_DPD_REQ_0_SOC_GPIO08_MSB                        MK_SHIFT_CONST(0)
#define PMC_IMPL_IO_DBG_DPD_REQ_0_SOC_GPIO08_LSB                        MK_SHIFT_CONST(0)
#define PMC_IMPL_IO_DBG_DPD_REQ_0_SOC_GPIO08_WOFFSET                    0x0
#define PMC_IMPL_IO_DBG_DPD_REQ_0_SOC_GPIO08_DEFAULT                    MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DBG_DPD_REQ_0_SOC_GPIO08_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DBG_DPD_REQ_0_SOC_GPIO08_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DBG_DPD_REQ_0_SOC_GPIO08_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DBG_DPD_REQ_0_SOC_GPIO08_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DBG_DPD_REQ_0_SOC_GPIO08_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DBG_DPD_REQ_0_SOC_GPIO08_OFF                        MK_ENUM_CONST(0)
#define PMC_IMPL_IO_DBG_DPD_REQ_0_SOC_GPIO08_ON                 MK_ENUM_CONST(1)


// Register PMC_IMPL_IO_DBG_DPD_STATUS_0
#define PMC_IMPL_IO_DBG_DPD_STATUS_0                    MK_ADDR_CONST(0xe030)
#define PMC_IMPL_IO_DBG_DPD_STATUS_0_SECURE                     0x0
#define PMC_IMPL_IO_DBG_DPD_STATUS_0_DUAL                       0x0
#define PMC_IMPL_IO_DBG_DPD_STATUS_0_SCR                        IO_DBG_SCR_0
#define PMC_IMPL_IO_DBG_DPD_STATUS_0_SCRREG                     PMC_IMPL_SCR_IO_DBG_SCR_0
#define PMC_IMPL_IO_DBG_DPD_STATUS_0_WORD_COUNT                         0x1
#define PMC_IMPL_IO_DBG_DPD_STATUS_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DBG_DPD_STATUS_0_RESET_MASK                         MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DBG_DPD_STATUS_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DBG_DPD_STATUS_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DBG_DPD_STATUS_0_READ_MASK                  MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DBG_DPD_STATUS_0_WRITE_MASK                         MK_MASK_CONST(0x0)
// On - SOC_GPIO08 PAD(s) is in Deep Power Down mode, Off - SOC_GPIO08 PAD(s) is out of Deep Power Down mode
#define PMC_IMPL_IO_DBG_DPD_STATUS_0_SOC_GPIO08_SHIFT                   MK_SHIFT_CONST(0)
#define PMC_IMPL_IO_DBG_DPD_STATUS_0_SOC_GPIO08_FIELD                   MK_FIELD_CONST(0x1, PMC_IMPL_IO_DBG_DPD_STATUS_0_SOC_GPIO08_SHIFT)
#define PMC_IMPL_IO_DBG_DPD_STATUS_0_SOC_GPIO08_RANGE                   0:0
#define PMC_IMPL_IO_DBG_DPD_STATUS_0_SOC_GPIO08_MSB                     MK_SHIFT_CONST(0)
#define PMC_IMPL_IO_DBG_DPD_STATUS_0_SOC_GPIO08_LSB                     MK_SHIFT_CONST(0)
#define PMC_IMPL_IO_DBG_DPD_STATUS_0_SOC_GPIO08_WOFFSET                 0x0
#define PMC_IMPL_IO_DBG_DPD_STATUS_0_SOC_GPIO08_DEFAULT                 MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DBG_DPD_STATUS_0_SOC_GPIO08_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DBG_DPD_STATUS_0_SOC_GPIO08_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DBG_DPD_STATUS_0_SOC_GPIO08_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DBG_DPD_STATUS_0_SOC_GPIO08_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DBG_DPD_STATUS_0_SOC_GPIO08_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DBG_DPD_STATUS_0_SOC_GPIO08_OFF                     MK_ENUM_CONST(0)
#define PMC_IMPL_IO_DBG_DPD_STATUS_0_SOC_GPIO08_ON                      MK_ENUM_CONST(1)


// Register PMC_IMPL_IO_G2_DPD_REQ_0
#define PMC_IMPL_IO_G2_DPD_REQ_0                        MK_ADDR_CONST(0xe034)
#define PMC_IMPL_IO_G2_DPD_REQ_0_SECURE                         0x0
#define PMC_IMPL_IO_G2_DPD_REQ_0_DUAL                   0x0
#define PMC_IMPL_IO_G2_DPD_REQ_0_SCR                    IO_G2_SCR_0
#define PMC_IMPL_IO_G2_DPD_REQ_0_SCRREG                         PMC_IMPL_SCR_IO_G2_SCR_0
#define PMC_IMPL_IO_G2_DPD_REQ_0_WORD_COUNT                     0x1
#define PMC_IMPL_IO_G2_DPD_REQ_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_G2_DPD_REQ_0_RESET_MASK                     MK_MASK_CONST(0xc000007f)
#define PMC_IMPL_IO_G2_DPD_REQ_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_G2_DPD_REQ_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_G2_DPD_REQ_0_READ_MASK                      MK_MASK_CONST(0xc000007f)
#define PMC_IMPL_IO_G2_DPD_REQ_0_WRITE_MASK                     MK_MASK_CONST(0xc000007f)
// code of operation for all set bits
#define PMC_IMPL_IO_G2_DPD_REQ_0_CODE_SHIFT                     MK_SHIFT_CONST(30)
#define PMC_IMPL_IO_G2_DPD_REQ_0_CODE_FIELD                     MK_FIELD_CONST(0x3, PMC_IMPL_IO_G2_DPD_REQ_0_CODE_SHIFT)
#define PMC_IMPL_IO_G2_DPD_REQ_0_CODE_RANGE                     31:30
#define PMC_IMPL_IO_G2_DPD_REQ_0_CODE_MSB                       MK_SHIFT_CONST(31)
#define PMC_IMPL_IO_G2_DPD_REQ_0_CODE_LSB                       MK_SHIFT_CONST(30)
#define PMC_IMPL_IO_G2_DPD_REQ_0_CODE_WOFFSET                   0x0
#define PMC_IMPL_IO_G2_DPD_REQ_0_CODE_DEFAULT                   MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_G2_DPD_REQ_0_CODE_DEFAULT_MASK                      MK_MASK_CONST(0x3)
#define PMC_IMPL_IO_G2_DPD_REQ_0_CODE_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_G2_DPD_REQ_0_CODE_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_G2_DPD_REQ_0_CODE_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_G2_DPD_REQ_0_CODE_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_G2_DPD_REQ_0_CODE_IDLE                      MK_ENUM_CONST(0)
#define PMC_IMPL_IO_G2_DPD_REQ_0_CODE_DPD_OFF                   MK_ENUM_CONST(1)
#define PMC_IMPL_IO_G2_DPD_REQ_0_CODE_DPD_ON                    MK_ENUM_CONST(2)

// puts GPU_PWR_REQ PAD(s) in/out of Depp Power Down (DPD) mode
#define PMC_IMPL_IO_G2_DPD_REQ_0_GPU_PWR_REQ_SHIFT                      MK_SHIFT_CONST(0)
#define PMC_IMPL_IO_G2_DPD_REQ_0_GPU_PWR_REQ_FIELD                      MK_FIELD_CONST(0x1, PMC_IMPL_IO_G2_DPD_REQ_0_GPU_PWR_REQ_SHIFT)
#define PMC_IMPL_IO_G2_DPD_REQ_0_GPU_PWR_REQ_RANGE                      0:0
#define PMC_IMPL_IO_G2_DPD_REQ_0_GPU_PWR_REQ_MSB                        MK_SHIFT_CONST(0)
#define PMC_IMPL_IO_G2_DPD_REQ_0_GPU_PWR_REQ_LSB                        MK_SHIFT_CONST(0)
#define PMC_IMPL_IO_G2_DPD_REQ_0_GPU_PWR_REQ_WOFFSET                    0x0
#define PMC_IMPL_IO_G2_DPD_REQ_0_GPU_PWR_REQ_DEFAULT                    MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_G2_DPD_REQ_0_GPU_PWR_REQ_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_G2_DPD_REQ_0_GPU_PWR_REQ_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_G2_DPD_REQ_0_GPU_PWR_REQ_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_G2_DPD_REQ_0_GPU_PWR_REQ_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_G2_DPD_REQ_0_GPU_PWR_REQ_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_G2_DPD_REQ_0_GPU_PWR_REQ_OFF                        MK_ENUM_CONST(0)
#define PMC_IMPL_IO_G2_DPD_REQ_0_GPU_PWR_REQ_ON                 MK_ENUM_CONST(1)

// puts CV_PWR_REQ PAD(s) in/out of Depp Power Down (DPD) mode
#define PMC_IMPL_IO_G2_DPD_REQ_0_CV_PWR_REQ_SHIFT                       MK_SHIFT_CONST(1)
#define PMC_IMPL_IO_G2_DPD_REQ_0_CV_PWR_REQ_FIELD                       MK_FIELD_CONST(0x1, PMC_IMPL_IO_G2_DPD_REQ_0_CV_PWR_REQ_SHIFT)
#define PMC_IMPL_IO_G2_DPD_REQ_0_CV_PWR_REQ_RANGE                       1:1
#define PMC_IMPL_IO_G2_DPD_REQ_0_CV_PWR_REQ_MSB                 MK_SHIFT_CONST(1)
#define PMC_IMPL_IO_G2_DPD_REQ_0_CV_PWR_REQ_LSB                 MK_SHIFT_CONST(1)
#define PMC_IMPL_IO_G2_DPD_REQ_0_CV_PWR_REQ_WOFFSET                     0x0
#define PMC_IMPL_IO_G2_DPD_REQ_0_CV_PWR_REQ_DEFAULT                     MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_G2_DPD_REQ_0_CV_PWR_REQ_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_G2_DPD_REQ_0_CV_PWR_REQ_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_G2_DPD_REQ_0_CV_PWR_REQ_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_G2_DPD_REQ_0_CV_PWR_REQ_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_G2_DPD_REQ_0_CV_PWR_REQ_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_G2_DPD_REQ_0_CV_PWR_REQ_OFF                 MK_ENUM_CONST(0)
#define PMC_IMPL_IO_G2_DPD_REQ_0_CV_PWR_REQ_ON                  MK_ENUM_CONST(1)

// puts GP_PWM2 PAD(s) in/out of Depp Power Down (DPD) mode
#define PMC_IMPL_IO_G2_DPD_REQ_0_GP_PWM2_SHIFT                  MK_SHIFT_CONST(2)
#define PMC_IMPL_IO_G2_DPD_REQ_0_GP_PWM2_FIELD                  MK_FIELD_CONST(0x1, PMC_IMPL_IO_G2_DPD_REQ_0_GP_PWM2_SHIFT)
#define PMC_IMPL_IO_G2_DPD_REQ_0_GP_PWM2_RANGE                  2:2
#define PMC_IMPL_IO_G2_DPD_REQ_0_GP_PWM2_MSB                    MK_SHIFT_CONST(2)
#define PMC_IMPL_IO_G2_DPD_REQ_0_GP_PWM2_LSB                    MK_SHIFT_CONST(2)
#define PMC_IMPL_IO_G2_DPD_REQ_0_GP_PWM2_WOFFSET                        0x0
#define PMC_IMPL_IO_G2_DPD_REQ_0_GP_PWM2_DEFAULT                        MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_G2_DPD_REQ_0_GP_PWM2_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_G2_DPD_REQ_0_GP_PWM2_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_G2_DPD_REQ_0_GP_PWM2_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_G2_DPD_REQ_0_GP_PWM2_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_G2_DPD_REQ_0_GP_PWM2_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_G2_DPD_REQ_0_GP_PWM2_OFF                    MK_ENUM_CONST(0)
#define PMC_IMPL_IO_G2_DPD_REQ_0_GP_PWM2_ON                     MK_ENUM_CONST(1)

// puts GP_PWM3 PAD(s) in/out of Depp Power Down (DPD) mode
#define PMC_IMPL_IO_G2_DPD_REQ_0_GP_PWM3_SHIFT                  MK_SHIFT_CONST(3)
#define PMC_IMPL_IO_G2_DPD_REQ_0_GP_PWM3_FIELD                  MK_FIELD_CONST(0x1, PMC_IMPL_IO_G2_DPD_REQ_0_GP_PWM3_SHIFT)
#define PMC_IMPL_IO_G2_DPD_REQ_0_GP_PWM3_RANGE                  3:3
#define PMC_IMPL_IO_G2_DPD_REQ_0_GP_PWM3_MSB                    MK_SHIFT_CONST(3)
#define PMC_IMPL_IO_G2_DPD_REQ_0_GP_PWM3_LSB                    MK_SHIFT_CONST(3)
#define PMC_IMPL_IO_G2_DPD_REQ_0_GP_PWM3_WOFFSET                        0x0
#define PMC_IMPL_IO_G2_DPD_REQ_0_GP_PWM3_DEFAULT                        MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_G2_DPD_REQ_0_GP_PWM3_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_G2_DPD_REQ_0_GP_PWM3_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_G2_DPD_REQ_0_GP_PWM3_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_G2_DPD_REQ_0_GP_PWM3_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_G2_DPD_REQ_0_GP_PWM3_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_G2_DPD_REQ_0_GP_PWM3_OFF                    MK_ENUM_CONST(0)
#define PMC_IMPL_IO_G2_DPD_REQ_0_GP_PWM3_ON                     MK_ENUM_CONST(1)

// puts UART2 PAD(s) in/out of Depp Power Down (DPD) mode
#define PMC_IMPL_IO_G2_DPD_REQ_0_UART2_SHIFT                    MK_SHIFT_CONST(4)
#define PMC_IMPL_IO_G2_DPD_REQ_0_UART2_FIELD                    MK_FIELD_CONST(0x1, PMC_IMPL_IO_G2_DPD_REQ_0_UART2_SHIFT)
#define PMC_IMPL_IO_G2_DPD_REQ_0_UART2_RANGE                    4:4
#define PMC_IMPL_IO_G2_DPD_REQ_0_UART2_MSB                      MK_SHIFT_CONST(4)
#define PMC_IMPL_IO_G2_DPD_REQ_0_UART2_LSB                      MK_SHIFT_CONST(4)
#define PMC_IMPL_IO_G2_DPD_REQ_0_UART2_WOFFSET                  0x0
#define PMC_IMPL_IO_G2_DPD_REQ_0_UART2_DEFAULT                  MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_G2_DPD_REQ_0_UART2_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_G2_DPD_REQ_0_UART2_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_G2_DPD_REQ_0_UART2_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_G2_DPD_REQ_0_UART2_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_G2_DPD_REQ_0_UART2_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_G2_DPD_REQ_0_UART2_OFF                      MK_ENUM_CONST(0)
#define PMC_IMPL_IO_G2_DPD_REQ_0_UART2_ON                       MK_ENUM_CONST(1)

// puts UART5 PAD(s) in/out of Depp Power Down (DPD) mode
#define PMC_IMPL_IO_G2_DPD_REQ_0_UART5_SHIFT                    MK_SHIFT_CONST(5)
#define PMC_IMPL_IO_G2_DPD_REQ_0_UART5_FIELD                    MK_FIELD_CONST(0x1, PMC_IMPL_IO_G2_DPD_REQ_0_UART5_SHIFT)
#define PMC_IMPL_IO_G2_DPD_REQ_0_UART5_RANGE                    5:5
#define PMC_IMPL_IO_G2_DPD_REQ_0_UART5_MSB                      MK_SHIFT_CONST(5)
#define PMC_IMPL_IO_G2_DPD_REQ_0_UART5_LSB                      MK_SHIFT_CONST(5)
#define PMC_IMPL_IO_G2_DPD_REQ_0_UART5_WOFFSET                  0x0
#define PMC_IMPL_IO_G2_DPD_REQ_0_UART5_DEFAULT                  MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_G2_DPD_REQ_0_UART5_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_G2_DPD_REQ_0_UART5_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_G2_DPD_REQ_0_UART5_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_G2_DPD_REQ_0_UART5_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_G2_DPD_REQ_0_UART5_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_G2_DPD_REQ_0_UART5_OFF                      MK_ENUM_CONST(0)
#define PMC_IMPL_IO_G2_DPD_REQ_0_UART5_ON                       MK_ENUM_CONST(1)

// puts G2 PAD(s) in/out of Depp Power Down (DPD) mode
#define PMC_IMPL_IO_G2_DPD_REQ_0_G2_SHIFT                       MK_SHIFT_CONST(6)
#define PMC_IMPL_IO_G2_DPD_REQ_0_G2_FIELD                       MK_FIELD_CONST(0x1, PMC_IMPL_IO_G2_DPD_REQ_0_G2_SHIFT)
#define PMC_IMPL_IO_G2_DPD_REQ_0_G2_RANGE                       6:6
#define PMC_IMPL_IO_G2_DPD_REQ_0_G2_MSB                 MK_SHIFT_CONST(6)
#define PMC_IMPL_IO_G2_DPD_REQ_0_G2_LSB                 MK_SHIFT_CONST(6)
#define PMC_IMPL_IO_G2_DPD_REQ_0_G2_WOFFSET                     0x0
#define PMC_IMPL_IO_G2_DPD_REQ_0_G2_DEFAULT                     MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_G2_DPD_REQ_0_G2_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_G2_DPD_REQ_0_G2_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_G2_DPD_REQ_0_G2_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_G2_DPD_REQ_0_G2_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_G2_DPD_REQ_0_G2_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_G2_DPD_REQ_0_G2_OFF                 MK_ENUM_CONST(0)
#define PMC_IMPL_IO_G2_DPD_REQ_0_G2_ON                  MK_ENUM_CONST(1)


// Register PMC_IMPL_IO_G2_DPD_STATUS_0
#define PMC_IMPL_IO_G2_DPD_STATUS_0                     MK_ADDR_CONST(0xe038)
#define PMC_IMPL_IO_G2_DPD_STATUS_0_SECURE                      0x0
#define PMC_IMPL_IO_G2_DPD_STATUS_0_DUAL                        0x0
#define PMC_IMPL_IO_G2_DPD_STATUS_0_SCR                         IO_G2_SCR_0
#define PMC_IMPL_IO_G2_DPD_STATUS_0_SCRREG                      PMC_IMPL_SCR_IO_G2_SCR_0
#define PMC_IMPL_IO_G2_DPD_STATUS_0_WORD_COUNT                  0x1
#define PMC_IMPL_IO_G2_DPD_STATUS_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_G2_DPD_STATUS_0_RESET_MASK                  MK_MASK_CONST(0x7f)
#define PMC_IMPL_IO_G2_DPD_STATUS_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_G2_DPD_STATUS_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_G2_DPD_STATUS_0_READ_MASK                   MK_MASK_CONST(0x7f)
#define PMC_IMPL_IO_G2_DPD_STATUS_0_WRITE_MASK                  MK_MASK_CONST(0x0)
// On - GPU_PWR_REQ PAD(s) is in Deep Power Down mode, Off - GPU_PWR_REQ PAD(s) is out of Deep Power Down mode
#define PMC_IMPL_IO_G2_DPD_STATUS_0_GPU_PWR_REQ_SHIFT                   MK_SHIFT_CONST(0)
#define PMC_IMPL_IO_G2_DPD_STATUS_0_GPU_PWR_REQ_FIELD                   MK_FIELD_CONST(0x1, PMC_IMPL_IO_G2_DPD_STATUS_0_GPU_PWR_REQ_SHIFT)
#define PMC_IMPL_IO_G2_DPD_STATUS_0_GPU_PWR_REQ_RANGE                   0:0
#define PMC_IMPL_IO_G2_DPD_STATUS_0_GPU_PWR_REQ_MSB                     MK_SHIFT_CONST(0)
#define PMC_IMPL_IO_G2_DPD_STATUS_0_GPU_PWR_REQ_LSB                     MK_SHIFT_CONST(0)
#define PMC_IMPL_IO_G2_DPD_STATUS_0_GPU_PWR_REQ_WOFFSET                 0x0
#define PMC_IMPL_IO_G2_DPD_STATUS_0_GPU_PWR_REQ_DEFAULT                 MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_G2_DPD_STATUS_0_GPU_PWR_REQ_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_G2_DPD_STATUS_0_GPU_PWR_REQ_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_G2_DPD_STATUS_0_GPU_PWR_REQ_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_G2_DPD_STATUS_0_GPU_PWR_REQ_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_G2_DPD_STATUS_0_GPU_PWR_REQ_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_G2_DPD_STATUS_0_GPU_PWR_REQ_OFF                     MK_ENUM_CONST(0)
#define PMC_IMPL_IO_G2_DPD_STATUS_0_GPU_PWR_REQ_ON                      MK_ENUM_CONST(1)

// On - CV_PWR_REQ PAD(s) is in Deep Power Down mode, Off - CV_PWR_REQ PAD(s) is out of Deep Power Down mode
#define PMC_IMPL_IO_G2_DPD_STATUS_0_CV_PWR_REQ_SHIFT                    MK_SHIFT_CONST(1)
#define PMC_IMPL_IO_G2_DPD_STATUS_0_CV_PWR_REQ_FIELD                    MK_FIELD_CONST(0x1, PMC_IMPL_IO_G2_DPD_STATUS_0_CV_PWR_REQ_SHIFT)
#define PMC_IMPL_IO_G2_DPD_STATUS_0_CV_PWR_REQ_RANGE                    1:1
#define PMC_IMPL_IO_G2_DPD_STATUS_0_CV_PWR_REQ_MSB                      MK_SHIFT_CONST(1)
#define PMC_IMPL_IO_G2_DPD_STATUS_0_CV_PWR_REQ_LSB                      MK_SHIFT_CONST(1)
#define PMC_IMPL_IO_G2_DPD_STATUS_0_CV_PWR_REQ_WOFFSET                  0x0
#define PMC_IMPL_IO_G2_DPD_STATUS_0_CV_PWR_REQ_DEFAULT                  MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_G2_DPD_STATUS_0_CV_PWR_REQ_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_G2_DPD_STATUS_0_CV_PWR_REQ_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_G2_DPD_STATUS_0_CV_PWR_REQ_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_G2_DPD_STATUS_0_CV_PWR_REQ_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_G2_DPD_STATUS_0_CV_PWR_REQ_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_G2_DPD_STATUS_0_CV_PWR_REQ_OFF                      MK_ENUM_CONST(0)
#define PMC_IMPL_IO_G2_DPD_STATUS_0_CV_PWR_REQ_ON                       MK_ENUM_CONST(1)

// On - GP_PWM2 PAD(s) is in Deep Power Down mode, Off - GP_PWM2 PAD(s) is out of Deep Power Down mode
#define PMC_IMPL_IO_G2_DPD_STATUS_0_GP_PWM2_SHIFT                       MK_SHIFT_CONST(2)
#define PMC_IMPL_IO_G2_DPD_STATUS_0_GP_PWM2_FIELD                       MK_FIELD_CONST(0x1, PMC_IMPL_IO_G2_DPD_STATUS_0_GP_PWM2_SHIFT)
#define PMC_IMPL_IO_G2_DPD_STATUS_0_GP_PWM2_RANGE                       2:2
#define PMC_IMPL_IO_G2_DPD_STATUS_0_GP_PWM2_MSB                 MK_SHIFT_CONST(2)
#define PMC_IMPL_IO_G2_DPD_STATUS_0_GP_PWM2_LSB                 MK_SHIFT_CONST(2)
#define PMC_IMPL_IO_G2_DPD_STATUS_0_GP_PWM2_WOFFSET                     0x0
#define PMC_IMPL_IO_G2_DPD_STATUS_0_GP_PWM2_DEFAULT                     MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_G2_DPD_STATUS_0_GP_PWM2_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_G2_DPD_STATUS_0_GP_PWM2_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_G2_DPD_STATUS_0_GP_PWM2_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_G2_DPD_STATUS_0_GP_PWM2_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_G2_DPD_STATUS_0_GP_PWM2_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_G2_DPD_STATUS_0_GP_PWM2_OFF                 MK_ENUM_CONST(0)
#define PMC_IMPL_IO_G2_DPD_STATUS_0_GP_PWM2_ON                  MK_ENUM_CONST(1)

// On - GP_PWM3 PAD(s) is in Deep Power Down mode, Off - GP_PWM3 PAD(s) is out of Deep Power Down mode
#define PMC_IMPL_IO_G2_DPD_STATUS_0_GP_PWM3_SHIFT                       MK_SHIFT_CONST(3)
#define PMC_IMPL_IO_G2_DPD_STATUS_0_GP_PWM3_FIELD                       MK_FIELD_CONST(0x1, PMC_IMPL_IO_G2_DPD_STATUS_0_GP_PWM3_SHIFT)
#define PMC_IMPL_IO_G2_DPD_STATUS_0_GP_PWM3_RANGE                       3:3
#define PMC_IMPL_IO_G2_DPD_STATUS_0_GP_PWM3_MSB                 MK_SHIFT_CONST(3)
#define PMC_IMPL_IO_G2_DPD_STATUS_0_GP_PWM3_LSB                 MK_SHIFT_CONST(3)
#define PMC_IMPL_IO_G2_DPD_STATUS_0_GP_PWM3_WOFFSET                     0x0
#define PMC_IMPL_IO_G2_DPD_STATUS_0_GP_PWM3_DEFAULT                     MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_G2_DPD_STATUS_0_GP_PWM3_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_G2_DPD_STATUS_0_GP_PWM3_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_G2_DPD_STATUS_0_GP_PWM3_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_G2_DPD_STATUS_0_GP_PWM3_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_G2_DPD_STATUS_0_GP_PWM3_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_G2_DPD_STATUS_0_GP_PWM3_OFF                 MK_ENUM_CONST(0)
#define PMC_IMPL_IO_G2_DPD_STATUS_0_GP_PWM3_ON                  MK_ENUM_CONST(1)

// On - UART2 PAD(s) is in Deep Power Down mode, Off - UART2 PAD(s) is out of Deep Power Down mode
#define PMC_IMPL_IO_G2_DPD_STATUS_0_UART2_SHIFT                 MK_SHIFT_CONST(4)
#define PMC_IMPL_IO_G2_DPD_STATUS_0_UART2_FIELD                 MK_FIELD_CONST(0x1, PMC_IMPL_IO_G2_DPD_STATUS_0_UART2_SHIFT)
#define PMC_IMPL_IO_G2_DPD_STATUS_0_UART2_RANGE                 4:4
#define PMC_IMPL_IO_G2_DPD_STATUS_0_UART2_MSB                   MK_SHIFT_CONST(4)
#define PMC_IMPL_IO_G2_DPD_STATUS_0_UART2_LSB                   MK_SHIFT_CONST(4)
#define PMC_IMPL_IO_G2_DPD_STATUS_0_UART2_WOFFSET                       0x0
#define PMC_IMPL_IO_G2_DPD_STATUS_0_UART2_DEFAULT                       MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_G2_DPD_STATUS_0_UART2_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_G2_DPD_STATUS_0_UART2_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_G2_DPD_STATUS_0_UART2_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_G2_DPD_STATUS_0_UART2_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_G2_DPD_STATUS_0_UART2_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_G2_DPD_STATUS_0_UART2_OFF                   MK_ENUM_CONST(0)
#define PMC_IMPL_IO_G2_DPD_STATUS_0_UART2_ON                    MK_ENUM_CONST(1)

// On - UART5 PAD(s) is in Deep Power Down mode, Off - UART5 PAD(s) is out of Deep Power Down mode
#define PMC_IMPL_IO_G2_DPD_STATUS_0_UART5_SHIFT                 MK_SHIFT_CONST(5)
#define PMC_IMPL_IO_G2_DPD_STATUS_0_UART5_FIELD                 MK_FIELD_CONST(0x1, PMC_IMPL_IO_G2_DPD_STATUS_0_UART5_SHIFT)
#define PMC_IMPL_IO_G2_DPD_STATUS_0_UART5_RANGE                 5:5
#define PMC_IMPL_IO_G2_DPD_STATUS_0_UART5_MSB                   MK_SHIFT_CONST(5)
#define PMC_IMPL_IO_G2_DPD_STATUS_0_UART5_LSB                   MK_SHIFT_CONST(5)
#define PMC_IMPL_IO_G2_DPD_STATUS_0_UART5_WOFFSET                       0x0
#define PMC_IMPL_IO_G2_DPD_STATUS_0_UART5_DEFAULT                       MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_G2_DPD_STATUS_0_UART5_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_G2_DPD_STATUS_0_UART5_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_G2_DPD_STATUS_0_UART5_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_G2_DPD_STATUS_0_UART5_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_G2_DPD_STATUS_0_UART5_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_G2_DPD_STATUS_0_UART5_OFF                   MK_ENUM_CONST(0)
#define PMC_IMPL_IO_G2_DPD_STATUS_0_UART5_ON                    MK_ENUM_CONST(1)

// On - G2 PAD(s) is in Deep Power Down mode, Off - G2 PAD(s) is out of Deep Power Down mode
#define PMC_IMPL_IO_G2_DPD_STATUS_0_G2_SHIFT                    MK_SHIFT_CONST(6)
#define PMC_IMPL_IO_G2_DPD_STATUS_0_G2_FIELD                    MK_FIELD_CONST(0x1, PMC_IMPL_IO_G2_DPD_STATUS_0_G2_SHIFT)
#define PMC_IMPL_IO_G2_DPD_STATUS_0_G2_RANGE                    6:6
#define PMC_IMPL_IO_G2_DPD_STATUS_0_G2_MSB                      MK_SHIFT_CONST(6)
#define PMC_IMPL_IO_G2_DPD_STATUS_0_G2_LSB                      MK_SHIFT_CONST(6)
#define PMC_IMPL_IO_G2_DPD_STATUS_0_G2_WOFFSET                  0x0
#define PMC_IMPL_IO_G2_DPD_STATUS_0_G2_DEFAULT                  MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_G2_DPD_STATUS_0_G2_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_G2_DPD_STATUS_0_G2_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_G2_DPD_STATUS_0_G2_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_G2_DPD_STATUS_0_G2_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_G2_DPD_STATUS_0_G2_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_G2_DPD_STATUS_0_G2_OFF                      MK_ENUM_CONST(0)
#define PMC_IMPL_IO_G2_DPD_STATUS_0_G2_ON                       MK_ENUM_CONST(1)


// Register PMC_IMPL_IO_G3_DPD_REQ_0
#define PMC_IMPL_IO_G3_DPD_REQ_0                        MK_ADDR_CONST(0xe03c)
#define PMC_IMPL_IO_G3_DPD_REQ_0_SECURE                         0x0
#define PMC_IMPL_IO_G3_DPD_REQ_0_DUAL                   0x0
#define PMC_IMPL_IO_G3_DPD_REQ_0_SCR                    IO_G3_SCR_0
#define PMC_IMPL_IO_G3_DPD_REQ_0_SCRREG                         PMC_IMPL_SCR_IO_G3_SCR_0
#define PMC_IMPL_IO_G3_DPD_REQ_0_WORD_COUNT                     0x1
#define PMC_IMPL_IO_G3_DPD_REQ_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_G3_DPD_REQ_0_RESET_MASK                     MK_MASK_CONST(0xc000000f)
#define PMC_IMPL_IO_G3_DPD_REQ_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_G3_DPD_REQ_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_G3_DPD_REQ_0_READ_MASK                      MK_MASK_CONST(0xc000000f)
#define PMC_IMPL_IO_G3_DPD_REQ_0_WRITE_MASK                     MK_MASK_CONST(0xc000000f)
// code of operation for all set bits
#define PMC_IMPL_IO_G3_DPD_REQ_0_CODE_SHIFT                     MK_SHIFT_CONST(30)
#define PMC_IMPL_IO_G3_DPD_REQ_0_CODE_FIELD                     MK_FIELD_CONST(0x3, PMC_IMPL_IO_G3_DPD_REQ_0_CODE_SHIFT)
#define PMC_IMPL_IO_G3_DPD_REQ_0_CODE_RANGE                     31:30
#define PMC_IMPL_IO_G3_DPD_REQ_0_CODE_MSB                       MK_SHIFT_CONST(31)
#define PMC_IMPL_IO_G3_DPD_REQ_0_CODE_LSB                       MK_SHIFT_CONST(30)
#define PMC_IMPL_IO_G3_DPD_REQ_0_CODE_WOFFSET                   0x0
#define PMC_IMPL_IO_G3_DPD_REQ_0_CODE_DEFAULT                   MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_G3_DPD_REQ_0_CODE_DEFAULT_MASK                      MK_MASK_CONST(0x3)
#define PMC_IMPL_IO_G3_DPD_REQ_0_CODE_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_G3_DPD_REQ_0_CODE_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_G3_DPD_REQ_0_CODE_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_G3_DPD_REQ_0_CODE_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_G3_DPD_REQ_0_CODE_IDLE                      MK_ENUM_CONST(0)
#define PMC_IMPL_IO_G3_DPD_REQ_0_CODE_DPD_OFF                   MK_ENUM_CONST(1)
#define PMC_IMPL_IO_G3_DPD_REQ_0_CODE_DPD_ON                    MK_ENUM_CONST(2)

// puts CAM_I2C_SCL PAD(s) in/out of Depp Power Down (DPD) mode
#define PMC_IMPL_IO_G3_DPD_REQ_0_CAM_I2C_SCL_SHIFT                      MK_SHIFT_CONST(0)
#define PMC_IMPL_IO_G3_DPD_REQ_0_CAM_I2C_SCL_FIELD                      MK_FIELD_CONST(0x1, PMC_IMPL_IO_G3_DPD_REQ_0_CAM_I2C_SCL_SHIFT)
#define PMC_IMPL_IO_G3_DPD_REQ_0_CAM_I2C_SCL_RANGE                      0:0
#define PMC_IMPL_IO_G3_DPD_REQ_0_CAM_I2C_SCL_MSB                        MK_SHIFT_CONST(0)
#define PMC_IMPL_IO_G3_DPD_REQ_0_CAM_I2C_SCL_LSB                        MK_SHIFT_CONST(0)
#define PMC_IMPL_IO_G3_DPD_REQ_0_CAM_I2C_SCL_WOFFSET                    0x0
#define PMC_IMPL_IO_G3_DPD_REQ_0_CAM_I2C_SCL_DEFAULT                    MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_G3_DPD_REQ_0_CAM_I2C_SCL_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_G3_DPD_REQ_0_CAM_I2C_SCL_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_G3_DPD_REQ_0_CAM_I2C_SCL_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_G3_DPD_REQ_0_CAM_I2C_SCL_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_G3_DPD_REQ_0_CAM_I2C_SCL_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_G3_DPD_REQ_0_CAM_I2C_SCL_OFF                        MK_ENUM_CONST(0)
#define PMC_IMPL_IO_G3_DPD_REQ_0_CAM_I2C_SCL_ON                 MK_ENUM_CONST(1)

// puts CAM_I2C_SDA PAD(s) in/out of Depp Power Down (DPD) mode
#define PMC_IMPL_IO_G3_DPD_REQ_0_CAM_I2C_SDA_SHIFT                      MK_SHIFT_CONST(1)
#define PMC_IMPL_IO_G3_DPD_REQ_0_CAM_I2C_SDA_FIELD                      MK_FIELD_CONST(0x1, PMC_IMPL_IO_G3_DPD_REQ_0_CAM_I2C_SDA_SHIFT)
#define PMC_IMPL_IO_G3_DPD_REQ_0_CAM_I2C_SDA_RANGE                      1:1
#define PMC_IMPL_IO_G3_DPD_REQ_0_CAM_I2C_SDA_MSB                        MK_SHIFT_CONST(1)
#define PMC_IMPL_IO_G3_DPD_REQ_0_CAM_I2C_SDA_LSB                        MK_SHIFT_CONST(1)
#define PMC_IMPL_IO_G3_DPD_REQ_0_CAM_I2C_SDA_WOFFSET                    0x0
#define PMC_IMPL_IO_G3_DPD_REQ_0_CAM_I2C_SDA_DEFAULT                    MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_G3_DPD_REQ_0_CAM_I2C_SDA_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_G3_DPD_REQ_0_CAM_I2C_SDA_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_G3_DPD_REQ_0_CAM_I2C_SDA_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_G3_DPD_REQ_0_CAM_I2C_SDA_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_G3_DPD_REQ_0_CAM_I2C_SDA_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_G3_DPD_REQ_0_CAM_I2C_SDA_OFF                        MK_ENUM_CONST(0)
#define PMC_IMPL_IO_G3_DPD_REQ_0_CAM_I2C_SDA_ON                 MK_ENUM_CONST(1)

// puts SOC_GPIO23 PAD(s) in/out of Depp Power Down (DPD) mode
#define PMC_IMPL_IO_G3_DPD_REQ_0_SOC_GPIO23_SHIFT                       MK_SHIFT_CONST(2)
#define PMC_IMPL_IO_G3_DPD_REQ_0_SOC_GPIO23_FIELD                       MK_FIELD_CONST(0x1, PMC_IMPL_IO_G3_DPD_REQ_0_SOC_GPIO23_SHIFT)
#define PMC_IMPL_IO_G3_DPD_REQ_0_SOC_GPIO23_RANGE                       2:2
#define PMC_IMPL_IO_G3_DPD_REQ_0_SOC_GPIO23_MSB                 MK_SHIFT_CONST(2)
#define PMC_IMPL_IO_G3_DPD_REQ_0_SOC_GPIO23_LSB                 MK_SHIFT_CONST(2)
#define PMC_IMPL_IO_G3_DPD_REQ_0_SOC_GPIO23_WOFFSET                     0x0
#define PMC_IMPL_IO_G3_DPD_REQ_0_SOC_GPIO23_DEFAULT                     MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_G3_DPD_REQ_0_SOC_GPIO23_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_G3_DPD_REQ_0_SOC_GPIO23_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_G3_DPD_REQ_0_SOC_GPIO23_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_G3_DPD_REQ_0_SOC_GPIO23_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_G3_DPD_REQ_0_SOC_GPIO23_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_G3_DPD_REQ_0_SOC_GPIO23_OFF                 MK_ENUM_CONST(0)
#define PMC_IMPL_IO_G3_DPD_REQ_0_SOC_GPIO23_ON                  MK_ENUM_CONST(1)

// puts G3 PAD(s) in/out of Depp Power Down (DPD) mode
#define PMC_IMPL_IO_G3_DPD_REQ_0_G3_SHIFT                       MK_SHIFT_CONST(3)
#define PMC_IMPL_IO_G3_DPD_REQ_0_G3_FIELD                       MK_FIELD_CONST(0x1, PMC_IMPL_IO_G3_DPD_REQ_0_G3_SHIFT)
#define PMC_IMPL_IO_G3_DPD_REQ_0_G3_RANGE                       3:3
#define PMC_IMPL_IO_G3_DPD_REQ_0_G3_MSB                 MK_SHIFT_CONST(3)
#define PMC_IMPL_IO_G3_DPD_REQ_0_G3_LSB                 MK_SHIFT_CONST(3)
#define PMC_IMPL_IO_G3_DPD_REQ_0_G3_WOFFSET                     0x0
#define PMC_IMPL_IO_G3_DPD_REQ_0_G3_DEFAULT                     MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_G3_DPD_REQ_0_G3_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_G3_DPD_REQ_0_G3_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_G3_DPD_REQ_0_G3_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_G3_DPD_REQ_0_G3_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_G3_DPD_REQ_0_G3_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_G3_DPD_REQ_0_G3_OFF                 MK_ENUM_CONST(0)
#define PMC_IMPL_IO_G3_DPD_REQ_0_G3_ON                  MK_ENUM_CONST(1)


// Register PMC_IMPL_IO_G3_DPD_STATUS_0
#define PMC_IMPL_IO_G3_DPD_STATUS_0                     MK_ADDR_CONST(0xe040)
#define PMC_IMPL_IO_G3_DPD_STATUS_0_SECURE                      0x0
#define PMC_IMPL_IO_G3_DPD_STATUS_0_DUAL                        0x0
#define PMC_IMPL_IO_G3_DPD_STATUS_0_SCR                         IO_G3_SCR_0
#define PMC_IMPL_IO_G3_DPD_STATUS_0_SCRREG                      PMC_IMPL_SCR_IO_G3_SCR_0
#define PMC_IMPL_IO_G3_DPD_STATUS_0_WORD_COUNT                  0x1
#define PMC_IMPL_IO_G3_DPD_STATUS_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_G3_DPD_STATUS_0_RESET_MASK                  MK_MASK_CONST(0xf)
#define PMC_IMPL_IO_G3_DPD_STATUS_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_G3_DPD_STATUS_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_G3_DPD_STATUS_0_READ_MASK                   MK_MASK_CONST(0xf)
#define PMC_IMPL_IO_G3_DPD_STATUS_0_WRITE_MASK                  MK_MASK_CONST(0x0)
// On - CAM_I2C_SCL PAD(s) is in Deep Power Down mode, Off - CAM_I2C_SCL PAD(s) is out of Deep Power Down mode
#define PMC_IMPL_IO_G3_DPD_STATUS_0_CAM_I2C_SCL_SHIFT                   MK_SHIFT_CONST(0)
#define PMC_IMPL_IO_G3_DPD_STATUS_0_CAM_I2C_SCL_FIELD                   MK_FIELD_CONST(0x1, PMC_IMPL_IO_G3_DPD_STATUS_0_CAM_I2C_SCL_SHIFT)
#define PMC_IMPL_IO_G3_DPD_STATUS_0_CAM_I2C_SCL_RANGE                   0:0
#define PMC_IMPL_IO_G3_DPD_STATUS_0_CAM_I2C_SCL_MSB                     MK_SHIFT_CONST(0)
#define PMC_IMPL_IO_G3_DPD_STATUS_0_CAM_I2C_SCL_LSB                     MK_SHIFT_CONST(0)
#define PMC_IMPL_IO_G3_DPD_STATUS_0_CAM_I2C_SCL_WOFFSET                 0x0
#define PMC_IMPL_IO_G3_DPD_STATUS_0_CAM_I2C_SCL_DEFAULT                 MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_G3_DPD_STATUS_0_CAM_I2C_SCL_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_G3_DPD_STATUS_0_CAM_I2C_SCL_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_G3_DPD_STATUS_0_CAM_I2C_SCL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_G3_DPD_STATUS_0_CAM_I2C_SCL_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_G3_DPD_STATUS_0_CAM_I2C_SCL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_G3_DPD_STATUS_0_CAM_I2C_SCL_OFF                     MK_ENUM_CONST(0)
#define PMC_IMPL_IO_G3_DPD_STATUS_0_CAM_I2C_SCL_ON                      MK_ENUM_CONST(1)

// On - CAM_I2C_SDA PAD(s) is in Deep Power Down mode, Off - CAM_I2C_SDA PAD(s) is out of Deep Power Down mode
#define PMC_IMPL_IO_G3_DPD_STATUS_0_CAM_I2C_SDA_SHIFT                   MK_SHIFT_CONST(1)
#define PMC_IMPL_IO_G3_DPD_STATUS_0_CAM_I2C_SDA_FIELD                   MK_FIELD_CONST(0x1, PMC_IMPL_IO_G3_DPD_STATUS_0_CAM_I2C_SDA_SHIFT)
#define PMC_IMPL_IO_G3_DPD_STATUS_0_CAM_I2C_SDA_RANGE                   1:1
#define PMC_IMPL_IO_G3_DPD_STATUS_0_CAM_I2C_SDA_MSB                     MK_SHIFT_CONST(1)
#define PMC_IMPL_IO_G3_DPD_STATUS_0_CAM_I2C_SDA_LSB                     MK_SHIFT_CONST(1)
#define PMC_IMPL_IO_G3_DPD_STATUS_0_CAM_I2C_SDA_WOFFSET                 0x0
#define PMC_IMPL_IO_G3_DPD_STATUS_0_CAM_I2C_SDA_DEFAULT                 MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_G3_DPD_STATUS_0_CAM_I2C_SDA_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_G3_DPD_STATUS_0_CAM_I2C_SDA_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_G3_DPD_STATUS_0_CAM_I2C_SDA_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_G3_DPD_STATUS_0_CAM_I2C_SDA_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_G3_DPD_STATUS_0_CAM_I2C_SDA_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_G3_DPD_STATUS_0_CAM_I2C_SDA_OFF                     MK_ENUM_CONST(0)
#define PMC_IMPL_IO_G3_DPD_STATUS_0_CAM_I2C_SDA_ON                      MK_ENUM_CONST(1)

// On - SOC_GPIO23 PAD(s) is in Deep Power Down mode, Off - SOC_GPIO23 PAD(s) is out of Deep Power Down mode
#define PMC_IMPL_IO_G3_DPD_STATUS_0_SOC_GPIO23_SHIFT                    MK_SHIFT_CONST(2)
#define PMC_IMPL_IO_G3_DPD_STATUS_0_SOC_GPIO23_FIELD                    MK_FIELD_CONST(0x1, PMC_IMPL_IO_G3_DPD_STATUS_0_SOC_GPIO23_SHIFT)
#define PMC_IMPL_IO_G3_DPD_STATUS_0_SOC_GPIO23_RANGE                    2:2
#define PMC_IMPL_IO_G3_DPD_STATUS_0_SOC_GPIO23_MSB                      MK_SHIFT_CONST(2)
#define PMC_IMPL_IO_G3_DPD_STATUS_0_SOC_GPIO23_LSB                      MK_SHIFT_CONST(2)
#define PMC_IMPL_IO_G3_DPD_STATUS_0_SOC_GPIO23_WOFFSET                  0x0
#define PMC_IMPL_IO_G3_DPD_STATUS_0_SOC_GPIO23_DEFAULT                  MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_G3_DPD_STATUS_0_SOC_GPIO23_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_G3_DPD_STATUS_0_SOC_GPIO23_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_G3_DPD_STATUS_0_SOC_GPIO23_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_G3_DPD_STATUS_0_SOC_GPIO23_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_G3_DPD_STATUS_0_SOC_GPIO23_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_G3_DPD_STATUS_0_SOC_GPIO23_OFF                      MK_ENUM_CONST(0)
#define PMC_IMPL_IO_G3_DPD_STATUS_0_SOC_GPIO23_ON                       MK_ENUM_CONST(1)

// On - G3 PAD(s) is in Deep Power Down mode, Off - G3 PAD(s) is out of Deep Power Down mode
#define PMC_IMPL_IO_G3_DPD_STATUS_0_G3_SHIFT                    MK_SHIFT_CONST(3)
#define PMC_IMPL_IO_G3_DPD_STATUS_0_G3_FIELD                    MK_FIELD_CONST(0x1, PMC_IMPL_IO_G3_DPD_STATUS_0_G3_SHIFT)
#define PMC_IMPL_IO_G3_DPD_STATUS_0_G3_RANGE                    3:3
#define PMC_IMPL_IO_G3_DPD_STATUS_0_G3_MSB                      MK_SHIFT_CONST(3)
#define PMC_IMPL_IO_G3_DPD_STATUS_0_G3_LSB                      MK_SHIFT_CONST(3)
#define PMC_IMPL_IO_G3_DPD_STATUS_0_G3_WOFFSET                  0x0
#define PMC_IMPL_IO_G3_DPD_STATUS_0_G3_DEFAULT                  MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_G3_DPD_STATUS_0_G3_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_G3_DPD_STATUS_0_G3_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_G3_DPD_STATUS_0_G3_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_G3_DPD_STATUS_0_G3_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_G3_DPD_STATUS_0_G3_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_G3_DPD_STATUS_0_G3_OFF                      MK_ENUM_CONST(0)
#define PMC_IMPL_IO_G3_DPD_STATUS_0_G3_ON                       MK_ENUM_CONST(1)


// Register PMC_IMPL_IO_G4_DPD_REQ_0
#define PMC_IMPL_IO_G4_DPD_REQ_0                        MK_ADDR_CONST(0xe044)
#define PMC_IMPL_IO_G4_DPD_REQ_0_SECURE                         0x0
#define PMC_IMPL_IO_G4_DPD_REQ_0_DUAL                   0x0
#define PMC_IMPL_IO_G4_DPD_REQ_0_SCR                    IO_G4_SCR_0
#define PMC_IMPL_IO_G4_DPD_REQ_0_SCRREG                         PMC_IMPL_SCR_IO_G4_SCR_0
#define PMC_IMPL_IO_G4_DPD_REQ_0_WORD_COUNT                     0x1
#define PMC_IMPL_IO_G4_DPD_REQ_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_G4_DPD_REQ_0_RESET_MASK                     MK_MASK_CONST(0xc000003f)
#define PMC_IMPL_IO_G4_DPD_REQ_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_G4_DPD_REQ_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_G4_DPD_REQ_0_READ_MASK                      MK_MASK_CONST(0xc000003f)
#define PMC_IMPL_IO_G4_DPD_REQ_0_WRITE_MASK                     MK_MASK_CONST(0xc000003f)
// code of operation for all set bits
#define PMC_IMPL_IO_G4_DPD_REQ_0_CODE_SHIFT                     MK_SHIFT_CONST(30)
#define PMC_IMPL_IO_G4_DPD_REQ_0_CODE_FIELD                     MK_FIELD_CONST(0x3, PMC_IMPL_IO_G4_DPD_REQ_0_CODE_SHIFT)
#define PMC_IMPL_IO_G4_DPD_REQ_0_CODE_RANGE                     31:30
#define PMC_IMPL_IO_G4_DPD_REQ_0_CODE_MSB                       MK_SHIFT_CONST(31)
#define PMC_IMPL_IO_G4_DPD_REQ_0_CODE_LSB                       MK_SHIFT_CONST(30)
#define PMC_IMPL_IO_G4_DPD_REQ_0_CODE_WOFFSET                   0x0
#define PMC_IMPL_IO_G4_DPD_REQ_0_CODE_DEFAULT                   MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_G4_DPD_REQ_0_CODE_DEFAULT_MASK                      MK_MASK_CONST(0x3)
#define PMC_IMPL_IO_G4_DPD_REQ_0_CODE_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_G4_DPD_REQ_0_CODE_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_G4_DPD_REQ_0_CODE_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_G4_DPD_REQ_0_CODE_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_G4_DPD_REQ_0_CODE_IDLE                      MK_ENUM_CONST(0)
#define PMC_IMPL_IO_G4_DPD_REQ_0_CODE_DPD_OFF                   MK_ENUM_CONST(1)
#define PMC_IMPL_IO_G4_DPD_REQ_0_CODE_DPD_ON                    MK_ENUM_CONST(2)

// puts SOC_GPIO14 PAD(s) in/out of Depp Power Down (DPD) mode
#define PMC_IMPL_IO_G4_DPD_REQ_0_SOC_GPIO14_SHIFT                       MK_SHIFT_CONST(0)
#define PMC_IMPL_IO_G4_DPD_REQ_0_SOC_GPIO14_FIELD                       MK_FIELD_CONST(0x1, PMC_IMPL_IO_G4_DPD_REQ_0_SOC_GPIO14_SHIFT)
#define PMC_IMPL_IO_G4_DPD_REQ_0_SOC_GPIO14_RANGE                       0:0
#define PMC_IMPL_IO_G4_DPD_REQ_0_SOC_GPIO14_MSB                 MK_SHIFT_CONST(0)
#define PMC_IMPL_IO_G4_DPD_REQ_0_SOC_GPIO14_LSB                 MK_SHIFT_CONST(0)
#define PMC_IMPL_IO_G4_DPD_REQ_0_SOC_GPIO14_WOFFSET                     0x0
#define PMC_IMPL_IO_G4_DPD_REQ_0_SOC_GPIO14_DEFAULT                     MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_G4_DPD_REQ_0_SOC_GPIO14_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_G4_DPD_REQ_0_SOC_GPIO14_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_G4_DPD_REQ_0_SOC_GPIO14_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_G4_DPD_REQ_0_SOC_GPIO14_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_G4_DPD_REQ_0_SOC_GPIO14_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_G4_DPD_REQ_0_SOC_GPIO14_OFF                 MK_ENUM_CONST(0)
#define PMC_IMPL_IO_G4_DPD_REQ_0_SOC_GPIO14_ON                  MK_ENUM_CONST(1)

// puts GP_PWM7 PAD(s) in/out of Depp Power Down (DPD) mode
#define PMC_IMPL_IO_G4_DPD_REQ_0_GP_PWM7_SHIFT                  MK_SHIFT_CONST(1)
#define PMC_IMPL_IO_G4_DPD_REQ_0_GP_PWM7_FIELD                  MK_FIELD_CONST(0x1, PMC_IMPL_IO_G4_DPD_REQ_0_GP_PWM7_SHIFT)
#define PMC_IMPL_IO_G4_DPD_REQ_0_GP_PWM7_RANGE                  1:1
#define PMC_IMPL_IO_G4_DPD_REQ_0_GP_PWM7_MSB                    MK_SHIFT_CONST(1)
#define PMC_IMPL_IO_G4_DPD_REQ_0_GP_PWM7_LSB                    MK_SHIFT_CONST(1)
#define PMC_IMPL_IO_G4_DPD_REQ_0_GP_PWM7_WOFFSET                        0x0
#define PMC_IMPL_IO_G4_DPD_REQ_0_GP_PWM7_DEFAULT                        MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_G4_DPD_REQ_0_GP_PWM7_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_G4_DPD_REQ_0_GP_PWM7_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_G4_DPD_REQ_0_GP_PWM7_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_G4_DPD_REQ_0_GP_PWM7_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_G4_DPD_REQ_0_GP_PWM7_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_G4_DPD_REQ_0_GP_PWM7_OFF                    MK_ENUM_CONST(0)
#define PMC_IMPL_IO_G4_DPD_REQ_0_GP_PWM7_ON                     MK_ENUM_CONST(1)

// puts CPU_PWR_REQ PAD(s) in/out of Depp Power Down (DPD) mode
#define PMC_IMPL_IO_G4_DPD_REQ_0_CPU_PWR_REQ_SHIFT                      MK_SHIFT_CONST(2)
#define PMC_IMPL_IO_G4_DPD_REQ_0_CPU_PWR_REQ_FIELD                      MK_FIELD_CONST(0x1, PMC_IMPL_IO_G4_DPD_REQ_0_CPU_PWR_REQ_SHIFT)
#define PMC_IMPL_IO_G4_DPD_REQ_0_CPU_PWR_REQ_RANGE                      2:2
#define PMC_IMPL_IO_G4_DPD_REQ_0_CPU_PWR_REQ_MSB                        MK_SHIFT_CONST(2)
#define PMC_IMPL_IO_G4_DPD_REQ_0_CPU_PWR_REQ_LSB                        MK_SHIFT_CONST(2)
#define PMC_IMPL_IO_G4_DPD_REQ_0_CPU_PWR_REQ_WOFFSET                    0x0
#define PMC_IMPL_IO_G4_DPD_REQ_0_CPU_PWR_REQ_DEFAULT                    MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_G4_DPD_REQ_0_CPU_PWR_REQ_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_G4_DPD_REQ_0_CPU_PWR_REQ_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_G4_DPD_REQ_0_CPU_PWR_REQ_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_G4_DPD_REQ_0_CPU_PWR_REQ_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_G4_DPD_REQ_0_CPU_PWR_REQ_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_G4_DPD_REQ_0_CPU_PWR_REQ_OFF                        MK_ENUM_CONST(0)
#define PMC_IMPL_IO_G4_DPD_REQ_0_CPU_PWR_REQ_ON                 MK_ENUM_CONST(1)

// puts GP_PWM6 PAD(s) in/out of Depp Power Down (DPD) mode
#define PMC_IMPL_IO_G4_DPD_REQ_0_GP_PWM6_SHIFT                  MK_SHIFT_CONST(3)
#define PMC_IMPL_IO_G4_DPD_REQ_0_GP_PWM6_FIELD                  MK_FIELD_CONST(0x1, PMC_IMPL_IO_G4_DPD_REQ_0_GP_PWM6_SHIFT)
#define PMC_IMPL_IO_G4_DPD_REQ_0_GP_PWM6_RANGE                  3:3
#define PMC_IMPL_IO_G4_DPD_REQ_0_GP_PWM6_MSB                    MK_SHIFT_CONST(3)
#define PMC_IMPL_IO_G4_DPD_REQ_0_GP_PWM6_LSB                    MK_SHIFT_CONST(3)
#define PMC_IMPL_IO_G4_DPD_REQ_0_GP_PWM6_WOFFSET                        0x0
#define PMC_IMPL_IO_G4_DPD_REQ_0_GP_PWM6_DEFAULT                        MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_G4_DPD_REQ_0_GP_PWM6_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_G4_DPD_REQ_0_GP_PWM6_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_G4_DPD_REQ_0_GP_PWM6_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_G4_DPD_REQ_0_GP_PWM6_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_G4_DPD_REQ_0_GP_PWM6_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_G4_DPD_REQ_0_GP_PWM6_OFF                    MK_ENUM_CONST(0)
#define PMC_IMPL_IO_G4_DPD_REQ_0_GP_PWM6_ON                     MK_ENUM_CONST(1)

// puts GP_PWM5 PAD(s) in/out of Depp Power Down (DPD) mode
#define PMC_IMPL_IO_G4_DPD_REQ_0_GP_PWM5_SHIFT                  MK_SHIFT_CONST(4)
#define PMC_IMPL_IO_G4_DPD_REQ_0_GP_PWM5_FIELD                  MK_FIELD_CONST(0x1, PMC_IMPL_IO_G4_DPD_REQ_0_GP_PWM5_SHIFT)
#define PMC_IMPL_IO_G4_DPD_REQ_0_GP_PWM5_RANGE                  4:4
#define PMC_IMPL_IO_G4_DPD_REQ_0_GP_PWM5_MSB                    MK_SHIFT_CONST(4)
#define PMC_IMPL_IO_G4_DPD_REQ_0_GP_PWM5_LSB                    MK_SHIFT_CONST(4)
#define PMC_IMPL_IO_G4_DPD_REQ_0_GP_PWM5_WOFFSET                        0x0
#define PMC_IMPL_IO_G4_DPD_REQ_0_GP_PWM5_DEFAULT                        MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_G4_DPD_REQ_0_GP_PWM5_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_G4_DPD_REQ_0_GP_PWM5_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_G4_DPD_REQ_0_GP_PWM5_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_G4_DPD_REQ_0_GP_PWM5_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_G4_DPD_REQ_0_GP_PWM5_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_G4_DPD_REQ_0_GP_PWM5_OFF                    MK_ENUM_CONST(0)
#define PMC_IMPL_IO_G4_DPD_REQ_0_GP_PWM5_ON                     MK_ENUM_CONST(1)

// puts G4 PAD(s) in/out of Depp Power Down (DPD) mode
#define PMC_IMPL_IO_G4_DPD_REQ_0_G4_SHIFT                       MK_SHIFT_CONST(5)
#define PMC_IMPL_IO_G4_DPD_REQ_0_G4_FIELD                       MK_FIELD_CONST(0x1, PMC_IMPL_IO_G4_DPD_REQ_0_G4_SHIFT)
#define PMC_IMPL_IO_G4_DPD_REQ_0_G4_RANGE                       5:5
#define PMC_IMPL_IO_G4_DPD_REQ_0_G4_MSB                 MK_SHIFT_CONST(5)
#define PMC_IMPL_IO_G4_DPD_REQ_0_G4_LSB                 MK_SHIFT_CONST(5)
#define PMC_IMPL_IO_G4_DPD_REQ_0_G4_WOFFSET                     0x0
#define PMC_IMPL_IO_G4_DPD_REQ_0_G4_DEFAULT                     MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_G4_DPD_REQ_0_G4_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_G4_DPD_REQ_0_G4_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_G4_DPD_REQ_0_G4_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_G4_DPD_REQ_0_G4_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_G4_DPD_REQ_0_G4_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_G4_DPD_REQ_0_G4_OFF                 MK_ENUM_CONST(0)
#define PMC_IMPL_IO_G4_DPD_REQ_0_G4_ON                  MK_ENUM_CONST(1)


// Register PMC_IMPL_IO_G4_DPD_STATUS_0
#define PMC_IMPL_IO_G4_DPD_STATUS_0                     MK_ADDR_CONST(0xe048)
#define PMC_IMPL_IO_G4_DPD_STATUS_0_SECURE                      0x0
#define PMC_IMPL_IO_G4_DPD_STATUS_0_DUAL                        0x0
#define PMC_IMPL_IO_G4_DPD_STATUS_0_SCR                         IO_G4_SCR_0
#define PMC_IMPL_IO_G4_DPD_STATUS_0_SCRREG                      PMC_IMPL_SCR_IO_G4_SCR_0
#define PMC_IMPL_IO_G4_DPD_STATUS_0_WORD_COUNT                  0x1
#define PMC_IMPL_IO_G4_DPD_STATUS_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_G4_DPD_STATUS_0_RESET_MASK                  MK_MASK_CONST(0x3f)
#define PMC_IMPL_IO_G4_DPD_STATUS_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_G4_DPD_STATUS_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_G4_DPD_STATUS_0_READ_MASK                   MK_MASK_CONST(0x3f)
#define PMC_IMPL_IO_G4_DPD_STATUS_0_WRITE_MASK                  MK_MASK_CONST(0x0)
// On - SOC_GPIO14 PAD(s) is in Deep Power Down mode, Off - SOC_GPIO14 PAD(s) is out of Deep Power Down mode
#define PMC_IMPL_IO_G4_DPD_STATUS_0_SOC_GPIO14_SHIFT                    MK_SHIFT_CONST(0)
#define PMC_IMPL_IO_G4_DPD_STATUS_0_SOC_GPIO14_FIELD                    MK_FIELD_CONST(0x1, PMC_IMPL_IO_G4_DPD_STATUS_0_SOC_GPIO14_SHIFT)
#define PMC_IMPL_IO_G4_DPD_STATUS_0_SOC_GPIO14_RANGE                    0:0
#define PMC_IMPL_IO_G4_DPD_STATUS_0_SOC_GPIO14_MSB                      MK_SHIFT_CONST(0)
#define PMC_IMPL_IO_G4_DPD_STATUS_0_SOC_GPIO14_LSB                      MK_SHIFT_CONST(0)
#define PMC_IMPL_IO_G4_DPD_STATUS_0_SOC_GPIO14_WOFFSET                  0x0
#define PMC_IMPL_IO_G4_DPD_STATUS_0_SOC_GPIO14_DEFAULT                  MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_G4_DPD_STATUS_0_SOC_GPIO14_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_G4_DPD_STATUS_0_SOC_GPIO14_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_G4_DPD_STATUS_0_SOC_GPIO14_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_G4_DPD_STATUS_0_SOC_GPIO14_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_G4_DPD_STATUS_0_SOC_GPIO14_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_G4_DPD_STATUS_0_SOC_GPIO14_OFF                      MK_ENUM_CONST(0)
#define PMC_IMPL_IO_G4_DPD_STATUS_0_SOC_GPIO14_ON                       MK_ENUM_CONST(1)

// On - GP_PWM7 PAD(s) is in Deep Power Down mode, Off - GP_PWM7 PAD(s) is out of Deep Power Down mode
#define PMC_IMPL_IO_G4_DPD_STATUS_0_GP_PWM7_SHIFT                       MK_SHIFT_CONST(1)
#define PMC_IMPL_IO_G4_DPD_STATUS_0_GP_PWM7_FIELD                       MK_FIELD_CONST(0x1, PMC_IMPL_IO_G4_DPD_STATUS_0_GP_PWM7_SHIFT)
#define PMC_IMPL_IO_G4_DPD_STATUS_0_GP_PWM7_RANGE                       1:1
#define PMC_IMPL_IO_G4_DPD_STATUS_0_GP_PWM7_MSB                 MK_SHIFT_CONST(1)
#define PMC_IMPL_IO_G4_DPD_STATUS_0_GP_PWM7_LSB                 MK_SHIFT_CONST(1)
#define PMC_IMPL_IO_G4_DPD_STATUS_0_GP_PWM7_WOFFSET                     0x0
#define PMC_IMPL_IO_G4_DPD_STATUS_0_GP_PWM7_DEFAULT                     MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_G4_DPD_STATUS_0_GP_PWM7_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_G4_DPD_STATUS_0_GP_PWM7_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_G4_DPD_STATUS_0_GP_PWM7_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_G4_DPD_STATUS_0_GP_PWM7_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_G4_DPD_STATUS_0_GP_PWM7_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_G4_DPD_STATUS_0_GP_PWM7_OFF                 MK_ENUM_CONST(0)
#define PMC_IMPL_IO_G4_DPD_STATUS_0_GP_PWM7_ON                  MK_ENUM_CONST(1)

// On - CPU_PWR_REQ PAD(s) is in Deep Power Down mode, Off - CPU_PWR_REQ PAD(s) is out of Deep Power Down mode
#define PMC_IMPL_IO_G4_DPD_STATUS_0_CPU_PWR_REQ_SHIFT                   MK_SHIFT_CONST(2)
#define PMC_IMPL_IO_G4_DPD_STATUS_0_CPU_PWR_REQ_FIELD                   MK_FIELD_CONST(0x1, PMC_IMPL_IO_G4_DPD_STATUS_0_CPU_PWR_REQ_SHIFT)
#define PMC_IMPL_IO_G4_DPD_STATUS_0_CPU_PWR_REQ_RANGE                   2:2
#define PMC_IMPL_IO_G4_DPD_STATUS_0_CPU_PWR_REQ_MSB                     MK_SHIFT_CONST(2)
#define PMC_IMPL_IO_G4_DPD_STATUS_0_CPU_PWR_REQ_LSB                     MK_SHIFT_CONST(2)
#define PMC_IMPL_IO_G4_DPD_STATUS_0_CPU_PWR_REQ_WOFFSET                 0x0
#define PMC_IMPL_IO_G4_DPD_STATUS_0_CPU_PWR_REQ_DEFAULT                 MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_G4_DPD_STATUS_0_CPU_PWR_REQ_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_G4_DPD_STATUS_0_CPU_PWR_REQ_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_G4_DPD_STATUS_0_CPU_PWR_REQ_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_G4_DPD_STATUS_0_CPU_PWR_REQ_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_G4_DPD_STATUS_0_CPU_PWR_REQ_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_G4_DPD_STATUS_0_CPU_PWR_REQ_OFF                     MK_ENUM_CONST(0)
#define PMC_IMPL_IO_G4_DPD_STATUS_0_CPU_PWR_REQ_ON                      MK_ENUM_CONST(1)

// On - GP_PWM6 PAD(s) is in Deep Power Down mode, Off - GP_PWM6 PAD(s) is out of Deep Power Down mode
#define PMC_IMPL_IO_G4_DPD_STATUS_0_GP_PWM6_SHIFT                       MK_SHIFT_CONST(3)
#define PMC_IMPL_IO_G4_DPD_STATUS_0_GP_PWM6_FIELD                       MK_FIELD_CONST(0x1, PMC_IMPL_IO_G4_DPD_STATUS_0_GP_PWM6_SHIFT)
#define PMC_IMPL_IO_G4_DPD_STATUS_0_GP_PWM6_RANGE                       3:3
#define PMC_IMPL_IO_G4_DPD_STATUS_0_GP_PWM6_MSB                 MK_SHIFT_CONST(3)
#define PMC_IMPL_IO_G4_DPD_STATUS_0_GP_PWM6_LSB                 MK_SHIFT_CONST(3)
#define PMC_IMPL_IO_G4_DPD_STATUS_0_GP_PWM6_WOFFSET                     0x0
#define PMC_IMPL_IO_G4_DPD_STATUS_0_GP_PWM6_DEFAULT                     MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_G4_DPD_STATUS_0_GP_PWM6_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_G4_DPD_STATUS_0_GP_PWM6_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_G4_DPD_STATUS_0_GP_PWM6_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_G4_DPD_STATUS_0_GP_PWM6_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_G4_DPD_STATUS_0_GP_PWM6_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_G4_DPD_STATUS_0_GP_PWM6_OFF                 MK_ENUM_CONST(0)
#define PMC_IMPL_IO_G4_DPD_STATUS_0_GP_PWM6_ON                  MK_ENUM_CONST(1)

// On - GP_PWM5 PAD(s) is in Deep Power Down mode, Off - GP_PWM5 PAD(s) is out of Deep Power Down mode
#define PMC_IMPL_IO_G4_DPD_STATUS_0_GP_PWM5_SHIFT                       MK_SHIFT_CONST(4)
#define PMC_IMPL_IO_G4_DPD_STATUS_0_GP_PWM5_FIELD                       MK_FIELD_CONST(0x1, PMC_IMPL_IO_G4_DPD_STATUS_0_GP_PWM5_SHIFT)
#define PMC_IMPL_IO_G4_DPD_STATUS_0_GP_PWM5_RANGE                       4:4
#define PMC_IMPL_IO_G4_DPD_STATUS_0_GP_PWM5_MSB                 MK_SHIFT_CONST(4)
#define PMC_IMPL_IO_G4_DPD_STATUS_0_GP_PWM5_LSB                 MK_SHIFT_CONST(4)
#define PMC_IMPL_IO_G4_DPD_STATUS_0_GP_PWM5_WOFFSET                     0x0
#define PMC_IMPL_IO_G4_DPD_STATUS_0_GP_PWM5_DEFAULT                     MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_G4_DPD_STATUS_0_GP_PWM5_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_G4_DPD_STATUS_0_GP_PWM5_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_G4_DPD_STATUS_0_GP_PWM5_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_G4_DPD_STATUS_0_GP_PWM5_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_G4_DPD_STATUS_0_GP_PWM5_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_G4_DPD_STATUS_0_GP_PWM5_OFF                 MK_ENUM_CONST(0)
#define PMC_IMPL_IO_G4_DPD_STATUS_0_GP_PWM5_ON                  MK_ENUM_CONST(1)

// On - G4 PAD(s) is in Deep Power Down mode, Off - G4 PAD(s) is out of Deep Power Down mode
#define PMC_IMPL_IO_G4_DPD_STATUS_0_G4_SHIFT                    MK_SHIFT_CONST(5)
#define PMC_IMPL_IO_G4_DPD_STATUS_0_G4_FIELD                    MK_FIELD_CONST(0x1, PMC_IMPL_IO_G4_DPD_STATUS_0_G4_SHIFT)
#define PMC_IMPL_IO_G4_DPD_STATUS_0_G4_RANGE                    5:5
#define PMC_IMPL_IO_G4_DPD_STATUS_0_G4_MSB                      MK_SHIFT_CONST(5)
#define PMC_IMPL_IO_G4_DPD_STATUS_0_G4_LSB                      MK_SHIFT_CONST(5)
#define PMC_IMPL_IO_G4_DPD_STATUS_0_G4_WOFFSET                  0x0
#define PMC_IMPL_IO_G4_DPD_STATUS_0_G4_DEFAULT                  MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_G4_DPD_STATUS_0_G4_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_G4_DPD_STATUS_0_G4_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_G4_DPD_STATUS_0_G4_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_G4_DPD_STATUS_0_G4_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_G4_DPD_STATUS_0_G4_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_G4_DPD_STATUS_0_G4_OFF                      MK_ENUM_CONST(0)
#define PMC_IMPL_IO_G4_DPD_STATUS_0_G4_ON                       MK_ENUM_CONST(1)


// Register PMC_IMPL_IO_G5_DPD_REQ_0
#define PMC_IMPL_IO_G5_DPD_REQ_0                        MK_ADDR_CONST(0xe04c)
#define PMC_IMPL_IO_G5_DPD_REQ_0_SECURE                         0x0
#define PMC_IMPL_IO_G5_DPD_REQ_0_DUAL                   0x0
#define PMC_IMPL_IO_G5_DPD_REQ_0_SCR                    IO_G5_SCR_0
#define PMC_IMPL_IO_G5_DPD_REQ_0_SCRREG                         PMC_IMPL_SCR_IO_G5_SCR_0
#define PMC_IMPL_IO_G5_DPD_REQ_0_WORD_COUNT                     0x1
#define PMC_IMPL_IO_G5_DPD_REQ_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_G5_DPD_REQ_0_RESET_MASK                     MK_MASK_CONST(0xc0000003)
#define PMC_IMPL_IO_G5_DPD_REQ_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_G5_DPD_REQ_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_G5_DPD_REQ_0_READ_MASK                      MK_MASK_CONST(0xc0000003)
#define PMC_IMPL_IO_G5_DPD_REQ_0_WRITE_MASK                     MK_MASK_CONST(0xc0000003)
// code of operation for all set bits
#define PMC_IMPL_IO_G5_DPD_REQ_0_CODE_SHIFT                     MK_SHIFT_CONST(30)
#define PMC_IMPL_IO_G5_DPD_REQ_0_CODE_FIELD                     MK_FIELD_CONST(0x3, PMC_IMPL_IO_G5_DPD_REQ_0_CODE_SHIFT)
#define PMC_IMPL_IO_G5_DPD_REQ_0_CODE_RANGE                     31:30
#define PMC_IMPL_IO_G5_DPD_REQ_0_CODE_MSB                       MK_SHIFT_CONST(31)
#define PMC_IMPL_IO_G5_DPD_REQ_0_CODE_LSB                       MK_SHIFT_CONST(30)
#define PMC_IMPL_IO_G5_DPD_REQ_0_CODE_WOFFSET                   0x0
#define PMC_IMPL_IO_G5_DPD_REQ_0_CODE_DEFAULT                   MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_G5_DPD_REQ_0_CODE_DEFAULT_MASK                      MK_MASK_CONST(0x3)
#define PMC_IMPL_IO_G5_DPD_REQ_0_CODE_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_G5_DPD_REQ_0_CODE_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_G5_DPD_REQ_0_CODE_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_G5_DPD_REQ_0_CODE_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_G5_DPD_REQ_0_CODE_IDLE                      MK_ENUM_CONST(0)
#define PMC_IMPL_IO_G5_DPD_REQ_0_CODE_DPD_OFF                   MK_ENUM_CONST(1)
#define PMC_IMPL_IO_G5_DPD_REQ_0_CODE_DPD_ON                    MK_ENUM_CONST(2)

// puts DAP4 PAD(s) in/out of Depp Power Down (DPD) mode
#define PMC_IMPL_IO_G5_DPD_REQ_0_DAP4_SHIFT                     MK_SHIFT_CONST(0)
#define PMC_IMPL_IO_G5_DPD_REQ_0_DAP4_FIELD                     MK_FIELD_CONST(0x1, PMC_IMPL_IO_G5_DPD_REQ_0_DAP4_SHIFT)
#define PMC_IMPL_IO_G5_DPD_REQ_0_DAP4_RANGE                     0:0
#define PMC_IMPL_IO_G5_DPD_REQ_0_DAP4_MSB                       MK_SHIFT_CONST(0)
#define PMC_IMPL_IO_G5_DPD_REQ_0_DAP4_LSB                       MK_SHIFT_CONST(0)
#define PMC_IMPL_IO_G5_DPD_REQ_0_DAP4_WOFFSET                   0x0
#define PMC_IMPL_IO_G5_DPD_REQ_0_DAP4_DEFAULT                   MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_G5_DPD_REQ_0_DAP4_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_G5_DPD_REQ_0_DAP4_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_G5_DPD_REQ_0_DAP4_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_G5_DPD_REQ_0_DAP4_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_G5_DPD_REQ_0_DAP4_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_G5_DPD_REQ_0_DAP4_OFF                       MK_ENUM_CONST(0)
#define PMC_IMPL_IO_G5_DPD_REQ_0_DAP4_ON                        MK_ENUM_CONST(1)

// puts DAP6 PAD(s) in/out of Depp Power Down (DPD) mode
#define PMC_IMPL_IO_G5_DPD_REQ_0_DAP6_SHIFT                     MK_SHIFT_CONST(1)
#define PMC_IMPL_IO_G5_DPD_REQ_0_DAP6_FIELD                     MK_FIELD_CONST(0x1, PMC_IMPL_IO_G5_DPD_REQ_0_DAP6_SHIFT)
#define PMC_IMPL_IO_G5_DPD_REQ_0_DAP6_RANGE                     1:1
#define PMC_IMPL_IO_G5_DPD_REQ_0_DAP6_MSB                       MK_SHIFT_CONST(1)
#define PMC_IMPL_IO_G5_DPD_REQ_0_DAP6_LSB                       MK_SHIFT_CONST(1)
#define PMC_IMPL_IO_G5_DPD_REQ_0_DAP6_WOFFSET                   0x0
#define PMC_IMPL_IO_G5_DPD_REQ_0_DAP6_DEFAULT                   MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_G5_DPD_REQ_0_DAP6_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_G5_DPD_REQ_0_DAP6_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_G5_DPD_REQ_0_DAP6_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_G5_DPD_REQ_0_DAP6_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_G5_DPD_REQ_0_DAP6_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_G5_DPD_REQ_0_DAP6_OFF                       MK_ENUM_CONST(0)
#define PMC_IMPL_IO_G5_DPD_REQ_0_DAP6_ON                        MK_ENUM_CONST(1)


// Register PMC_IMPL_IO_G5_DPD_STATUS_0
#define PMC_IMPL_IO_G5_DPD_STATUS_0                     MK_ADDR_CONST(0xe050)
#define PMC_IMPL_IO_G5_DPD_STATUS_0_SECURE                      0x0
#define PMC_IMPL_IO_G5_DPD_STATUS_0_DUAL                        0x0
#define PMC_IMPL_IO_G5_DPD_STATUS_0_SCR                         IO_G5_SCR_0
#define PMC_IMPL_IO_G5_DPD_STATUS_0_SCRREG                      PMC_IMPL_SCR_IO_G5_SCR_0
#define PMC_IMPL_IO_G5_DPD_STATUS_0_WORD_COUNT                  0x1
#define PMC_IMPL_IO_G5_DPD_STATUS_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_G5_DPD_STATUS_0_RESET_MASK                  MK_MASK_CONST(0x3)
#define PMC_IMPL_IO_G5_DPD_STATUS_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_G5_DPD_STATUS_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_G5_DPD_STATUS_0_READ_MASK                   MK_MASK_CONST(0x3)
#define PMC_IMPL_IO_G5_DPD_STATUS_0_WRITE_MASK                  MK_MASK_CONST(0x0)
// On - DAP4 PAD(s) is in Deep Power Down mode, Off - DAP4 PAD(s) is out of Deep Power Down mode
#define PMC_IMPL_IO_G5_DPD_STATUS_0_DAP4_SHIFT                  MK_SHIFT_CONST(0)
#define PMC_IMPL_IO_G5_DPD_STATUS_0_DAP4_FIELD                  MK_FIELD_CONST(0x1, PMC_IMPL_IO_G5_DPD_STATUS_0_DAP4_SHIFT)
#define PMC_IMPL_IO_G5_DPD_STATUS_0_DAP4_RANGE                  0:0
#define PMC_IMPL_IO_G5_DPD_STATUS_0_DAP4_MSB                    MK_SHIFT_CONST(0)
#define PMC_IMPL_IO_G5_DPD_STATUS_0_DAP4_LSB                    MK_SHIFT_CONST(0)
#define PMC_IMPL_IO_G5_DPD_STATUS_0_DAP4_WOFFSET                        0x0
#define PMC_IMPL_IO_G5_DPD_STATUS_0_DAP4_DEFAULT                        MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_G5_DPD_STATUS_0_DAP4_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_G5_DPD_STATUS_0_DAP4_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_G5_DPD_STATUS_0_DAP4_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_G5_DPD_STATUS_0_DAP4_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_G5_DPD_STATUS_0_DAP4_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_G5_DPD_STATUS_0_DAP4_OFF                    MK_ENUM_CONST(0)
#define PMC_IMPL_IO_G5_DPD_STATUS_0_DAP4_ON                     MK_ENUM_CONST(1)

// On - DAP6 PAD(s) is in Deep Power Down mode, Off - DAP6 PAD(s) is out of Deep Power Down mode
#define PMC_IMPL_IO_G5_DPD_STATUS_0_DAP6_SHIFT                  MK_SHIFT_CONST(1)
#define PMC_IMPL_IO_G5_DPD_STATUS_0_DAP6_FIELD                  MK_FIELD_CONST(0x1, PMC_IMPL_IO_G5_DPD_STATUS_0_DAP6_SHIFT)
#define PMC_IMPL_IO_G5_DPD_STATUS_0_DAP6_RANGE                  1:1
#define PMC_IMPL_IO_G5_DPD_STATUS_0_DAP6_MSB                    MK_SHIFT_CONST(1)
#define PMC_IMPL_IO_G5_DPD_STATUS_0_DAP6_LSB                    MK_SHIFT_CONST(1)
#define PMC_IMPL_IO_G5_DPD_STATUS_0_DAP6_WOFFSET                        0x0
#define PMC_IMPL_IO_G5_DPD_STATUS_0_DAP6_DEFAULT                        MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_G5_DPD_STATUS_0_DAP6_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_G5_DPD_STATUS_0_DAP6_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_G5_DPD_STATUS_0_DAP6_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_G5_DPD_STATUS_0_DAP6_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_G5_DPD_STATUS_0_DAP6_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_G5_DPD_STATUS_0_DAP6_OFF                    MK_ENUM_CONST(0)
#define PMC_IMPL_IO_G5_DPD_STATUS_0_DAP6_ON                     MK_ENUM_CONST(1)


// Register PMC_IMPL_IO_SDMMC1_HV_DPD_REQ_0
#define PMC_IMPL_IO_SDMMC1_HV_DPD_REQ_0                 MK_ADDR_CONST(0xe054)
#define PMC_IMPL_IO_SDMMC1_HV_DPD_REQ_0_SECURE                  0x0
#define PMC_IMPL_IO_SDMMC1_HV_DPD_REQ_0_DUAL                    0x0
#define PMC_IMPL_IO_SDMMC1_HV_DPD_REQ_0_SCR                     IO_SDMMC1_HV_SCR_0
#define PMC_IMPL_IO_SDMMC1_HV_DPD_REQ_0_SCRREG                  PMC_IMPL_SCR_IO_SDMMC1_HV_SCR_0
#define PMC_IMPL_IO_SDMMC1_HV_DPD_REQ_0_WORD_COUNT                      0x1
#define PMC_IMPL_IO_SDMMC1_HV_DPD_REQ_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_SDMMC1_HV_DPD_REQ_0_RESET_MASK                      MK_MASK_CONST(0xc0000001)
#define PMC_IMPL_IO_SDMMC1_HV_DPD_REQ_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_SDMMC1_HV_DPD_REQ_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_SDMMC1_HV_DPD_REQ_0_READ_MASK                       MK_MASK_CONST(0xc0000001)
#define PMC_IMPL_IO_SDMMC1_HV_DPD_REQ_0_WRITE_MASK                      MK_MASK_CONST(0xc0000001)
// code of operation for all set bits
#define PMC_IMPL_IO_SDMMC1_HV_DPD_REQ_0_CODE_SHIFT                      MK_SHIFT_CONST(30)
#define PMC_IMPL_IO_SDMMC1_HV_DPD_REQ_0_CODE_FIELD                      MK_FIELD_CONST(0x3, PMC_IMPL_IO_SDMMC1_HV_DPD_REQ_0_CODE_SHIFT)
#define PMC_IMPL_IO_SDMMC1_HV_DPD_REQ_0_CODE_RANGE                      31:30
#define PMC_IMPL_IO_SDMMC1_HV_DPD_REQ_0_CODE_MSB                        MK_SHIFT_CONST(31)
#define PMC_IMPL_IO_SDMMC1_HV_DPD_REQ_0_CODE_LSB                        MK_SHIFT_CONST(30)
#define PMC_IMPL_IO_SDMMC1_HV_DPD_REQ_0_CODE_WOFFSET                    0x0
#define PMC_IMPL_IO_SDMMC1_HV_DPD_REQ_0_CODE_DEFAULT                    MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_SDMMC1_HV_DPD_REQ_0_CODE_DEFAULT_MASK                       MK_MASK_CONST(0x3)
#define PMC_IMPL_IO_SDMMC1_HV_DPD_REQ_0_CODE_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_SDMMC1_HV_DPD_REQ_0_CODE_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_SDMMC1_HV_DPD_REQ_0_CODE_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_SDMMC1_HV_DPD_REQ_0_CODE_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_SDMMC1_HV_DPD_REQ_0_CODE_IDLE                       MK_ENUM_CONST(0)
#define PMC_IMPL_IO_SDMMC1_HV_DPD_REQ_0_CODE_DPD_OFF                    MK_ENUM_CONST(1)
#define PMC_IMPL_IO_SDMMC1_HV_DPD_REQ_0_CODE_DPD_ON                     MK_ENUM_CONST(2)

// puts SDMMC1 PAD(s) in/out of Depp Power Down (DPD) mode
#define PMC_IMPL_IO_SDMMC1_HV_DPD_REQ_0_SDMMC1_SHIFT                    MK_SHIFT_CONST(0)
#define PMC_IMPL_IO_SDMMC1_HV_DPD_REQ_0_SDMMC1_FIELD                    MK_FIELD_CONST(0x1, PMC_IMPL_IO_SDMMC1_HV_DPD_REQ_0_SDMMC1_SHIFT)
#define PMC_IMPL_IO_SDMMC1_HV_DPD_REQ_0_SDMMC1_RANGE                    0:0
#define PMC_IMPL_IO_SDMMC1_HV_DPD_REQ_0_SDMMC1_MSB                      MK_SHIFT_CONST(0)
#define PMC_IMPL_IO_SDMMC1_HV_DPD_REQ_0_SDMMC1_LSB                      MK_SHIFT_CONST(0)
#define PMC_IMPL_IO_SDMMC1_HV_DPD_REQ_0_SDMMC1_WOFFSET                  0x0
#define PMC_IMPL_IO_SDMMC1_HV_DPD_REQ_0_SDMMC1_DEFAULT                  MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_SDMMC1_HV_DPD_REQ_0_SDMMC1_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_SDMMC1_HV_DPD_REQ_0_SDMMC1_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_SDMMC1_HV_DPD_REQ_0_SDMMC1_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_SDMMC1_HV_DPD_REQ_0_SDMMC1_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_SDMMC1_HV_DPD_REQ_0_SDMMC1_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_SDMMC1_HV_DPD_REQ_0_SDMMC1_OFF                      MK_ENUM_CONST(0)
#define PMC_IMPL_IO_SDMMC1_HV_DPD_REQ_0_SDMMC1_ON                       MK_ENUM_CONST(1)


// Register PMC_IMPL_IO_SDMMC1_HV_DPD_STATUS_0
#define PMC_IMPL_IO_SDMMC1_HV_DPD_STATUS_0                      MK_ADDR_CONST(0xe058)
#define PMC_IMPL_IO_SDMMC1_HV_DPD_STATUS_0_SECURE                       0x0
#define PMC_IMPL_IO_SDMMC1_HV_DPD_STATUS_0_DUAL                         0x0
#define PMC_IMPL_IO_SDMMC1_HV_DPD_STATUS_0_SCR                  IO_SDMMC1_HV_SCR_0
#define PMC_IMPL_IO_SDMMC1_HV_DPD_STATUS_0_SCRREG                       PMC_IMPL_SCR_IO_SDMMC1_HV_SCR_0
#define PMC_IMPL_IO_SDMMC1_HV_DPD_STATUS_0_WORD_COUNT                   0x1
#define PMC_IMPL_IO_SDMMC1_HV_DPD_STATUS_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_SDMMC1_HV_DPD_STATUS_0_RESET_MASK                   MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_SDMMC1_HV_DPD_STATUS_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_SDMMC1_HV_DPD_STATUS_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_SDMMC1_HV_DPD_STATUS_0_READ_MASK                    MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_SDMMC1_HV_DPD_STATUS_0_WRITE_MASK                   MK_MASK_CONST(0x0)
// On - SDMMC1 PAD(s) is in Deep Power Down mode, Off - SDMMC1 PAD(s) is out of Deep Power Down mode
#define PMC_IMPL_IO_SDMMC1_HV_DPD_STATUS_0_SDMMC1_SHIFT                 MK_SHIFT_CONST(0)
#define PMC_IMPL_IO_SDMMC1_HV_DPD_STATUS_0_SDMMC1_FIELD                 MK_FIELD_CONST(0x1, PMC_IMPL_IO_SDMMC1_HV_DPD_STATUS_0_SDMMC1_SHIFT)
#define PMC_IMPL_IO_SDMMC1_HV_DPD_STATUS_0_SDMMC1_RANGE                 0:0
#define PMC_IMPL_IO_SDMMC1_HV_DPD_STATUS_0_SDMMC1_MSB                   MK_SHIFT_CONST(0)
#define PMC_IMPL_IO_SDMMC1_HV_DPD_STATUS_0_SDMMC1_LSB                   MK_SHIFT_CONST(0)
#define PMC_IMPL_IO_SDMMC1_HV_DPD_STATUS_0_SDMMC1_WOFFSET                       0x0
#define PMC_IMPL_IO_SDMMC1_HV_DPD_STATUS_0_SDMMC1_DEFAULT                       MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_SDMMC1_HV_DPD_STATUS_0_SDMMC1_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_SDMMC1_HV_DPD_STATUS_0_SDMMC1_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_SDMMC1_HV_DPD_STATUS_0_SDMMC1_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_SDMMC1_HV_DPD_STATUS_0_SDMMC1_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_SDMMC1_HV_DPD_STATUS_0_SDMMC1_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_SDMMC1_HV_DPD_STATUS_0_SDMMC1_OFF                   MK_ENUM_CONST(0)
#define PMC_IMPL_IO_SDMMC1_HV_DPD_STATUS_0_SDMMC1_ON                    MK_ENUM_CONST(1)


// Register PMC_IMPL_IO_EDP_DPD_REQ_0
#define PMC_IMPL_IO_EDP_DPD_REQ_0                       MK_ADDR_CONST(0xe05c)
#define PMC_IMPL_IO_EDP_DPD_REQ_0_SECURE                        0x0
#define PMC_IMPL_IO_EDP_DPD_REQ_0_DUAL                  0x0
#define PMC_IMPL_IO_EDP_DPD_REQ_0_SCR                   IO_EDP_SCR_0
#define PMC_IMPL_IO_EDP_DPD_REQ_0_SCRREG                        PMC_IMPL_SCR_IO_EDP_SCR_0
#define PMC_IMPL_IO_EDP_DPD_REQ_0_WORD_COUNT                    0x1
#define PMC_IMPL_IO_EDP_DPD_REQ_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_EDP_DPD_REQ_0_RESET_MASK                    MK_MASK_CONST(0xc0000003)
#define PMC_IMPL_IO_EDP_DPD_REQ_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_EDP_DPD_REQ_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_EDP_DPD_REQ_0_READ_MASK                     MK_MASK_CONST(0xc0000003)
#define PMC_IMPL_IO_EDP_DPD_REQ_0_WRITE_MASK                    MK_MASK_CONST(0xc0000003)
// code of operation for all set bits
#define PMC_IMPL_IO_EDP_DPD_REQ_0_CODE_SHIFT                    MK_SHIFT_CONST(30)
#define PMC_IMPL_IO_EDP_DPD_REQ_0_CODE_FIELD                    MK_FIELD_CONST(0x3, PMC_IMPL_IO_EDP_DPD_REQ_0_CODE_SHIFT)
#define PMC_IMPL_IO_EDP_DPD_REQ_0_CODE_RANGE                    31:30
#define PMC_IMPL_IO_EDP_DPD_REQ_0_CODE_MSB                      MK_SHIFT_CONST(31)
#define PMC_IMPL_IO_EDP_DPD_REQ_0_CODE_LSB                      MK_SHIFT_CONST(30)
#define PMC_IMPL_IO_EDP_DPD_REQ_0_CODE_WOFFSET                  0x0
#define PMC_IMPL_IO_EDP_DPD_REQ_0_CODE_DEFAULT                  MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_EDP_DPD_REQ_0_CODE_DEFAULT_MASK                     MK_MASK_CONST(0x3)
#define PMC_IMPL_IO_EDP_DPD_REQ_0_CODE_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_EDP_DPD_REQ_0_CODE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_EDP_DPD_REQ_0_CODE_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_EDP_DPD_REQ_0_CODE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_EDP_DPD_REQ_0_CODE_IDLE                     MK_ENUM_CONST(0)
#define PMC_IMPL_IO_EDP_DPD_REQ_0_CODE_DPD_OFF                  MK_ENUM_CONST(1)
#define PMC_IMPL_IO_EDP_DPD_REQ_0_CODE_DPD_ON                   MK_ENUM_CONST(2)

// puts GP_PWM1 PAD(s) in/out of Depp Power Down (DPD) mode
#define PMC_IMPL_IO_EDP_DPD_REQ_0_GP_PWM1_SHIFT                 MK_SHIFT_CONST(0)
#define PMC_IMPL_IO_EDP_DPD_REQ_0_GP_PWM1_FIELD                 MK_FIELD_CONST(0x1, PMC_IMPL_IO_EDP_DPD_REQ_0_GP_PWM1_SHIFT)
#define PMC_IMPL_IO_EDP_DPD_REQ_0_GP_PWM1_RANGE                 0:0
#define PMC_IMPL_IO_EDP_DPD_REQ_0_GP_PWM1_MSB                   MK_SHIFT_CONST(0)
#define PMC_IMPL_IO_EDP_DPD_REQ_0_GP_PWM1_LSB                   MK_SHIFT_CONST(0)
#define PMC_IMPL_IO_EDP_DPD_REQ_0_GP_PWM1_WOFFSET                       0x0
#define PMC_IMPL_IO_EDP_DPD_REQ_0_GP_PWM1_DEFAULT                       MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_EDP_DPD_REQ_0_GP_PWM1_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_EDP_DPD_REQ_0_GP_PWM1_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_EDP_DPD_REQ_0_GP_PWM1_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_EDP_DPD_REQ_0_GP_PWM1_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_EDP_DPD_REQ_0_GP_PWM1_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_EDP_DPD_REQ_0_GP_PWM1_OFF                   MK_ENUM_CONST(0)
#define PMC_IMPL_IO_EDP_DPD_REQ_0_GP_PWM1_ON                    MK_ENUM_CONST(1)

// puts EDP PAD(s) in/out of Depp Power Down (DPD) mode
#define PMC_IMPL_IO_EDP_DPD_REQ_0_EDP_SHIFT                     MK_SHIFT_CONST(1)
#define PMC_IMPL_IO_EDP_DPD_REQ_0_EDP_FIELD                     MK_FIELD_CONST(0x1, PMC_IMPL_IO_EDP_DPD_REQ_0_EDP_SHIFT)
#define PMC_IMPL_IO_EDP_DPD_REQ_0_EDP_RANGE                     1:1
#define PMC_IMPL_IO_EDP_DPD_REQ_0_EDP_MSB                       MK_SHIFT_CONST(1)
#define PMC_IMPL_IO_EDP_DPD_REQ_0_EDP_LSB                       MK_SHIFT_CONST(1)
#define PMC_IMPL_IO_EDP_DPD_REQ_0_EDP_WOFFSET                   0x0
#define PMC_IMPL_IO_EDP_DPD_REQ_0_EDP_DEFAULT                   MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_EDP_DPD_REQ_0_EDP_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_EDP_DPD_REQ_0_EDP_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_EDP_DPD_REQ_0_EDP_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_EDP_DPD_REQ_0_EDP_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_EDP_DPD_REQ_0_EDP_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_EDP_DPD_REQ_0_EDP_OFF                       MK_ENUM_CONST(0)
#define PMC_IMPL_IO_EDP_DPD_REQ_0_EDP_ON                        MK_ENUM_CONST(1)


// Register PMC_IMPL_IO_EDP_DPD_STATUS_0
#define PMC_IMPL_IO_EDP_DPD_STATUS_0                    MK_ADDR_CONST(0xe060)
#define PMC_IMPL_IO_EDP_DPD_STATUS_0_SECURE                     0x0
#define PMC_IMPL_IO_EDP_DPD_STATUS_0_DUAL                       0x0
#define PMC_IMPL_IO_EDP_DPD_STATUS_0_SCR                        IO_EDP_SCR_0
#define PMC_IMPL_IO_EDP_DPD_STATUS_0_SCRREG                     PMC_IMPL_SCR_IO_EDP_SCR_0
#define PMC_IMPL_IO_EDP_DPD_STATUS_0_WORD_COUNT                         0x1
#define PMC_IMPL_IO_EDP_DPD_STATUS_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_EDP_DPD_STATUS_0_RESET_MASK                         MK_MASK_CONST(0x3)
#define PMC_IMPL_IO_EDP_DPD_STATUS_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_EDP_DPD_STATUS_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_EDP_DPD_STATUS_0_READ_MASK                  MK_MASK_CONST(0x3)
#define PMC_IMPL_IO_EDP_DPD_STATUS_0_WRITE_MASK                         MK_MASK_CONST(0x0)
// On - GP_PWM1 PAD(s) is in Deep Power Down mode, Off - GP_PWM1 PAD(s) is out of Deep Power Down mode
#define PMC_IMPL_IO_EDP_DPD_STATUS_0_GP_PWM1_SHIFT                      MK_SHIFT_CONST(0)
#define PMC_IMPL_IO_EDP_DPD_STATUS_0_GP_PWM1_FIELD                      MK_FIELD_CONST(0x1, PMC_IMPL_IO_EDP_DPD_STATUS_0_GP_PWM1_SHIFT)
#define PMC_IMPL_IO_EDP_DPD_STATUS_0_GP_PWM1_RANGE                      0:0
#define PMC_IMPL_IO_EDP_DPD_STATUS_0_GP_PWM1_MSB                        MK_SHIFT_CONST(0)
#define PMC_IMPL_IO_EDP_DPD_STATUS_0_GP_PWM1_LSB                        MK_SHIFT_CONST(0)
#define PMC_IMPL_IO_EDP_DPD_STATUS_0_GP_PWM1_WOFFSET                    0x0
#define PMC_IMPL_IO_EDP_DPD_STATUS_0_GP_PWM1_DEFAULT                    MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_EDP_DPD_STATUS_0_GP_PWM1_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_EDP_DPD_STATUS_0_GP_PWM1_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_EDP_DPD_STATUS_0_GP_PWM1_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_EDP_DPD_STATUS_0_GP_PWM1_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_EDP_DPD_STATUS_0_GP_PWM1_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_EDP_DPD_STATUS_0_GP_PWM1_OFF                        MK_ENUM_CONST(0)
#define PMC_IMPL_IO_EDP_DPD_STATUS_0_GP_PWM1_ON                 MK_ENUM_CONST(1)

// On - EDP PAD(s) is in Deep Power Down mode, Off - EDP PAD(s) is out of Deep Power Down mode
#define PMC_IMPL_IO_EDP_DPD_STATUS_0_EDP_SHIFT                  MK_SHIFT_CONST(1)
#define PMC_IMPL_IO_EDP_DPD_STATUS_0_EDP_FIELD                  MK_FIELD_CONST(0x1, PMC_IMPL_IO_EDP_DPD_STATUS_0_EDP_SHIFT)
#define PMC_IMPL_IO_EDP_DPD_STATUS_0_EDP_RANGE                  1:1
#define PMC_IMPL_IO_EDP_DPD_STATUS_0_EDP_MSB                    MK_SHIFT_CONST(1)
#define PMC_IMPL_IO_EDP_DPD_STATUS_0_EDP_LSB                    MK_SHIFT_CONST(1)
#define PMC_IMPL_IO_EDP_DPD_STATUS_0_EDP_WOFFSET                        0x0
#define PMC_IMPL_IO_EDP_DPD_STATUS_0_EDP_DEFAULT                        MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_EDP_DPD_STATUS_0_EDP_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_EDP_DPD_STATUS_0_EDP_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_EDP_DPD_STATUS_0_EDP_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_EDP_DPD_STATUS_0_EDP_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_EDP_DPD_STATUS_0_EDP_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_EDP_DPD_STATUS_0_EDP_OFF                    MK_ENUM_CONST(0)
#define PMC_IMPL_IO_EDP_DPD_STATUS_0_EDP_ON                     MK_ENUM_CONST(1)


// Register PMC_IMPL_IO_UFS_DPD_REQ_0
#define PMC_IMPL_IO_UFS_DPD_REQ_0                       MK_ADDR_CONST(0xe064)
#define PMC_IMPL_IO_UFS_DPD_REQ_0_SECURE                        0x0
#define PMC_IMPL_IO_UFS_DPD_REQ_0_DUAL                  0x0
#define PMC_IMPL_IO_UFS_DPD_REQ_0_SCR                   IO_UFS_SCR_0
#define PMC_IMPL_IO_UFS_DPD_REQ_0_SCRREG                        PMC_IMPL_SCR_IO_UFS_SCR_0
#define PMC_IMPL_IO_UFS_DPD_REQ_0_WORD_COUNT                    0x1
#define PMC_IMPL_IO_UFS_DPD_REQ_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_UFS_DPD_REQ_0_RESET_MASK                    MK_MASK_CONST(0xc0000001)
#define PMC_IMPL_IO_UFS_DPD_REQ_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_UFS_DPD_REQ_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_UFS_DPD_REQ_0_READ_MASK                     MK_MASK_CONST(0xc0000001)
#define PMC_IMPL_IO_UFS_DPD_REQ_0_WRITE_MASK                    MK_MASK_CONST(0xc0000001)
// code of operation for all set bits
#define PMC_IMPL_IO_UFS_DPD_REQ_0_CODE_SHIFT                    MK_SHIFT_CONST(30)
#define PMC_IMPL_IO_UFS_DPD_REQ_0_CODE_FIELD                    MK_FIELD_CONST(0x3, PMC_IMPL_IO_UFS_DPD_REQ_0_CODE_SHIFT)
#define PMC_IMPL_IO_UFS_DPD_REQ_0_CODE_RANGE                    31:30
#define PMC_IMPL_IO_UFS_DPD_REQ_0_CODE_MSB                      MK_SHIFT_CONST(31)
#define PMC_IMPL_IO_UFS_DPD_REQ_0_CODE_LSB                      MK_SHIFT_CONST(30)
#define PMC_IMPL_IO_UFS_DPD_REQ_0_CODE_WOFFSET                  0x0
#define PMC_IMPL_IO_UFS_DPD_REQ_0_CODE_DEFAULT                  MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_UFS_DPD_REQ_0_CODE_DEFAULT_MASK                     MK_MASK_CONST(0x3)
#define PMC_IMPL_IO_UFS_DPD_REQ_0_CODE_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_UFS_DPD_REQ_0_CODE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_UFS_DPD_REQ_0_CODE_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_UFS_DPD_REQ_0_CODE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_UFS_DPD_REQ_0_CODE_IDLE                     MK_ENUM_CONST(0)
#define PMC_IMPL_IO_UFS_DPD_REQ_0_CODE_DPD_OFF                  MK_ENUM_CONST(1)
#define PMC_IMPL_IO_UFS_DPD_REQ_0_CODE_DPD_ON                   MK_ENUM_CONST(2)

// puts UFS PAD(s) in/out of Depp Power Down (DPD) mode
#define PMC_IMPL_IO_UFS_DPD_REQ_0_UFS_SHIFT                     MK_SHIFT_CONST(0)
#define PMC_IMPL_IO_UFS_DPD_REQ_0_UFS_FIELD                     MK_FIELD_CONST(0x1, PMC_IMPL_IO_UFS_DPD_REQ_0_UFS_SHIFT)
#define PMC_IMPL_IO_UFS_DPD_REQ_0_UFS_RANGE                     0:0
#define PMC_IMPL_IO_UFS_DPD_REQ_0_UFS_MSB                       MK_SHIFT_CONST(0)
#define PMC_IMPL_IO_UFS_DPD_REQ_0_UFS_LSB                       MK_SHIFT_CONST(0)
#define PMC_IMPL_IO_UFS_DPD_REQ_0_UFS_WOFFSET                   0x0
#define PMC_IMPL_IO_UFS_DPD_REQ_0_UFS_DEFAULT                   MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_UFS_DPD_REQ_0_UFS_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_UFS_DPD_REQ_0_UFS_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_UFS_DPD_REQ_0_UFS_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_UFS_DPD_REQ_0_UFS_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_UFS_DPD_REQ_0_UFS_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_UFS_DPD_REQ_0_UFS_OFF                       MK_ENUM_CONST(0)
#define PMC_IMPL_IO_UFS_DPD_REQ_0_UFS_ON                        MK_ENUM_CONST(1)


// Register PMC_IMPL_IO_UFS_DPD_STATUS_0
#define PMC_IMPL_IO_UFS_DPD_STATUS_0                    MK_ADDR_CONST(0xe068)
#define PMC_IMPL_IO_UFS_DPD_STATUS_0_SECURE                     0x0
#define PMC_IMPL_IO_UFS_DPD_STATUS_0_DUAL                       0x0
#define PMC_IMPL_IO_UFS_DPD_STATUS_0_SCR                        IO_UFS_SCR_0
#define PMC_IMPL_IO_UFS_DPD_STATUS_0_SCRREG                     PMC_IMPL_SCR_IO_UFS_SCR_0
#define PMC_IMPL_IO_UFS_DPD_STATUS_0_WORD_COUNT                         0x1
#define PMC_IMPL_IO_UFS_DPD_STATUS_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_UFS_DPD_STATUS_0_RESET_MASK                         MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_UFS_DPD_STATUS_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_UFS_DPD_STATUS_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_UFS_DPD_STATUS_0_READ_MASK                  MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_UFS_DPD_STATUS_0_WRITE_MASK                         MK_MASK_CONST(0x0)
// On - UFS PAD(s) is in Deep Power Down mode, Off - UFS PAD(s) is out of Deep Power Down mode
#define PMC_IMPL_IO_UFS_DPD_STATUS_0_UFS_SHIFT                  MK_SHIFT_CONST(0)
#define PMC_IMPL_IO_UFS_DPD_STATUS_0_UFS_FIELD                  MK_FIELD_CONST(0x1, PMC_IMPL_IO_UFS_DPD_STATUS_0_UFS_SHIFT)
#define PMC_IMPL_IO_UFS_DPD_STATUS_0_UFS_RANGE                  0:0
#define PMC_IMPL_IO_UFS_DPD_STATUS_0_UFS_MSB                    MK_SHIFT_CONST(0)
#define PMC_IMPL_IO_UFS_DPD_STATUS_0_UFS_LSB                    MK_SHIFT_CONST(0)
#define PMC_IMPL_IO_UFS_DPD_STATUS_0_UFS_WOFFSET                        0x0
#define PMC_IMPL_IO_UFS_DPD_STATUS_0_UFS_DEFAULT                        MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_UFS_DPD_STATUS_0_UFS_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_UFS_DPD_STATUS_0_UFS_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_UFS_DPD_STATUS_0_UFS_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_UFS_DPD_STATUS_0_UFS_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_UFS_DPD_STATUS_0_UFS_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_UFS_DPD_STATUS_0_UFS_OFF                    MK_ENUM_CONST(0)
#define PMC_IMPL_IO_UFS_DPD_STATUS_0_UFS_ON                     MK_ENUM_CONST(1)


// Register PMC_IMPL_IO_PEX_CTL_A_DPD_REQ_0
#define PMC_IMPL_IO_PEX_CTL_A_DPD_REQ_0                 MK_ADDR_CONST(0xe06c)
#define PMC_IMPL_IO_PEX_CTL_A_DPD_REQ_0_SECURE                  0x0
#define PMC_IMPL_IO_PEX_CTL_A_DPD_REQ_0_DUAL                    0x0
#define PMC_IMPL_IO_PEX_CTL_A_DPD_REQ_0_SCR                     IO_PEX_CTL_A_SCR_0
#define PMC_IMPL_IO_PEX_CTL_A_DPD_REQ_0_SCRREG                  PMC_IMPL_SCR_IO_PEX_CTL_A_SCR_0
#define PMC_IMPL_IO_PEX_CTL_A_DPD_REQ_0_WORD_COUNT                      0x1
#define PMC_IMPL_IO_PEX_CTL_A_DPD_REQ_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_PEX_CTL_A_DPD_REQ_0_RESET_MASK                      MK_MASK_CONST(0xc0000001)
#define PMC_IMPL_IO_PEX_CTL_A_DPD_REQ_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_PEX_CTL_A_DPD_REQ_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_PEX_CTL_A_DPD_REQ_0_READ_MASK                       MK_MASK_CONST(0xc0000001)
#define PMC_IMPL_IO_PEX_CTL_A_DPD_REQ_0_WRITE_MASK                      MK_MASK_CONST(0xc0000001)
// code of operation for all set bits
#define PMC_IMPL_IO_PEX_CTL_A_DPD_REQ_0_CODE_SHIFT                      MK_SHIFT_CONST(30)
#define PMC_IMPL_IO_PEX_CTL_A_DPD_REQ_0_CODE_FIELD                      MK_FIELD_CONST(0x3, PMC_IMPL_IO_PEX_CTL_A_DPD_REQ_0_CODE_SHIFT)
#define PMC_IMPL_IO_PEX_CTL_A_DPD_REQ_0_CODE_RANGE                      31:30
#define PMC_IMPL_IO_PEX_CTL_A_DPD_REQ_0_CODE_MSB                        MK_SHIFT_CONST(31)
#define PMC_IMPL_IO_PEX_CTL_A_DPD_REQ_0_CODE_LSB                        MK_SHIFT_CONST(30)
#define PMC_IMPL_IO_PEX_CTL_A_DPD_REQ_0_CODE_WOFFSET                    0x0
#define PMC_IMPL_IO_PEX_CTL_A_DPD_REQ_0_CODE_DEFAULT                    MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_PEX_CTL_A_DPD_REQ_0_CODE_DEFAULT_MASK                       MK_MASK_CONST(0x3)
#define PMC_IMPL_IO_PEX_CTL_A_DPD_REQ_0_CODE_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_PEX_CTL_A_DPD_REQ_0_CODE_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_PEX_CTL_A_DPD_REQ_0_CODE_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_PEX_CTL_A_DPD_REQ_0_CODE_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_PEX_CTL_A_DPD_REQ_0_CODE_IDLE                       MK_ENUM_CONST(0)
#define PMC_IMPL_IO_PEX_CTL_A_DPD_REQ_0_CODE_DPD_OFF                    MK_ENUM_CONST(1)
#define PMC_IMPL_IO_PEX_CTL_A_DPD_REQ_0_CODE_DPD_ON                     MK_ENUM_CONST(2)

// puts PEX_CTL PAD(s) in/out of Depp Power Down (DPD) mode
#define PMC_IMPL_IO_PEX_CTL_A_DPD_REQ_0_PEX_CTL_SHIFT                   MK_SHIFT_CONST(0)
#define PMC_IMPL_IO_PEX_CTL_A_DPD_REQ_0_PEX_CTL_FIELD                   MK_FIELD_CONST(0x1, PMC_IMPL_IO_PEX_CTL_A_DPD_REQ_0_PEX_CTL_SHIFT)
#define PMC_IMPL_IO_PEX_CTL_A_DPD_REQ_0_PEX_CTL_RANGE                   0:0
#define PMC_IMPL_IO_PEX_CTL_A_DPD_REQ_0_PEX_CTL_MSB                     MK_SHIFT_CONST(0)
#define PMC_IMPL_IO_PEX_CTL_A_DPD_REQ_0_PEX_CTL_LSB                     MK_SHIFT_CONST(0)
#define PMC_IMPL_IO_PEX_CTL_A_DPD_REQ_0_PEX_CTL_WOFFSET                 0x0
#define PMC_IMPL_IO_PEX_CTL_A_DPD_REQ_0_PEX_CTL_DEFAULT                 MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_PEX_CTL_A_DPD_REQ_0_PEX_CTL_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_PEX_CTL_A_DPD_REQ_0_PEX_CTL_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_PEX_CTL_A_DPD_REQ_0_PEX_CTL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_PEX_CTL_A_DPD_REQ_0_PEX_CTL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_PEX_CTL_A_DPD_REQ_0_PEX_CTL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_PEX_CTL_A_DPD_REQ_0_PEX_CTL_OFF                     MK_ENUM_CONST(0)
#define PMC_IMPL_IO_PEX_CTL_A_DPD_REQ_0_PEX_CTL_ON                      MK_ENUM_CONST(1)


// Register PMC_IMPL_IO_PEX_CTL_A_DPD_STATUS_0
#define PMC_IMPL_IO_PEX_CTL_A_DPD_STATUS_0                      MK_ADDR_CONST(0xe070)
#define PMC_IMPL_IO_PEX_CTL_A_DPD_STATUS_0_SECURE                       0x0
#define PMC_IMPL_IO_PEX_CTL_A_DPD_STATUS_0_DUAL                         0x0
#define PMC_IMPL_IO_PEX_CTL_A_DPD_STATUS_0_SCR                  IO_PEX_CTL_A_SCR_0
#define PMC_IMPL_IO_PEX_CTL_A_DPD_STATUS_0_SCRREG                       PMC_IMPL_SCR_IO_PEX_CTL_A_SCR_0
#define PMC_IMPL_IO_PEX_CTL_A_DPD_STATUS_0_WORD_COUNT                   0x1
#define PMC_IMPL_IO_PEX_CTL_A_DPD_STATUS_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_PEX_CTL_A_DPD_STATUS_0_RESET_MASK                   MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_PEX_CTL_A_DPD_STATUS_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_PEX_CTL_A_DPD_STATUS_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_PEX_CTL_A_DPD_STATUS_0_READ_MASK                    MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_PEX_CTL_A_DPD_STATUS_0_WRITE_MASK                   MK_MASK_CONST(0x0)
// On - PEX_CTL PAD(s) is in Deep Power Down mode, Off - PEX_CTL PAD(s) is out of Deep Power Down mode
#define PMC_IMPL_IO_PEX_CTL_A_DPD_STATUS_0_PEX_CTL_SHIFT                        MK_SHIFT_CONST(0)
#define PMC_IMPL_IO_PEX_CTL_A_DPD_STATUS_0_PEX_CTL_FIELD                        MK_FIELD_CONST(0x1, PMC_IMPL_IO_PEX_CTL_A_DPD_STATUS_0_PEX_CTL_SHIFT)
#define PMC_IMPL_IO_PEX_CTL_A_DPD_STATUS_0_PEX_CTL_RANGE                        0:0
#define PMC_IMPL_IO_PEX_CTL_A_DPD_STATUS_0_PEX_CTL_MSB                  MK_SHIFT_CONST(0)
#define PMC_IMPL_IO_PEX_CTL_A_DPD_STATUS_0_PEX_CTL_LSB                  MK_SHIFT_CONST(0)
#define PMC_IMPL_IO_PEX_CTL_A_DPD_STATUS_0_PEX_CTL_WOFFSET                      0x0
#define PMC_IMPL_IO_PEX_CTL_A_DPD_STATUS_0_PEX_CTL_DEFAULT                      MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_PEX_CTL_A_DPD_STATUS_0_PEX_CTL_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_PEX_CTL_A_DPD_STATUS_0_PEX_CTL_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_PEX_CTL_A_DPD_STATUS_0_PEX_CTL_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_PEX_CTL_A_DPD_STATUS_0_PEX_CTL_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_PEX_CTL_A_DPD_STATUS_0_PEX_CTL_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_PEX_CTL_A_DPD_STATUS_0_PEX_CTL_OFF                  MK_ENUM_CONST(0)
#define PMC_IMPL_IO_PEX_CTL_A_DPD_STATUS_0_PEX_CTL_ON                   MK_ENUM_CONST(1)


// Register PMC_IMPL_IO_QSPI_DPD_REQ_0
#define PMC_IMPL_IO_QSPI_DPD_REQ_0                      MK_ADDR_CONST(0xe074)
#define PMC_IMPL_IO_QSPI_DPD_REQ_0_SECURE                       0x0
#define PMC_IMPL_IO_QSPI_DPD_REQ_0_DUAL                         0x0
#define PMC_IMPL_IO_QSPI_DPD_REQ_0_SCR                  IO_QSPI_SCR_0
#define PMC_IMPL_IO_QSPI_DPD_REQ_0_SCRREG                       PMC_IMPL_SCR_IO_QSPI_SCR_0
#define PMC_IMPL_IO_QSPI_DPD_REQ_0_WORD_COUNT                   0x1
#define PMC_IMPL_IO_QSPI_DPD_REQ_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_QSPI_DPD_REQ_0_RESET_MASK                   MK_MASK_CONST(0xc0000001)
#define PMC_IMPL_IO_QSPI_DPD_REQ_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_QSPI_DPD_REQ_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_QSPI_DPD_REQ_0_READ_MASK                    MK_MASK_CONST(0xc0000001)
#define PMC_IMPL_IO_QSPI_DPD_REQ_0_WRITE_MASK                   MK_MASK_CONST(0xc0000001)
// code of operation for all set bits
#define PMC_IMPL_IO_QSPI_DPD_REQ_0_CODE_SHIFT                   MK_SHIFT_CONST(30)
#define PMC_IMPL_IO_QSPI_DPD_REQ_0_CODE_FIELD                   MK_FIELD_CONST(0x3, PMC_IMPL_IO_QSPI_DPD_REQ_0_CODE_SHIFT)
#define PMC_IMPL_IO_QSPI_DPD_REQ_0_CODE_RANGE                   31:30
#define PMC_IMPL_IO_QSPI_DPD_REQ_0_CODE_MSB                     MK_SHIFT_CONST(31)
#define PMC_IMPL_IO_QSPI_DPD_REQ_0_CODE_LSB                     MK_SHIFT_CONST(30)
#define PMC_IMPL_IO_QSPI_DPD_REQ_0_CODE_WOFFSET                 0x0
#define PMC_IMPL_IO_QSPI_DPD_REQ_0_CODE_DEFAULT                 MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_QSPI_DPD_REQ_0_CODE_DEFAULT_MASK                    MK_MASK_CONST(0x3)
#define PMC_IMPL_IO_QSPI_DPD_REQ_0_CODE_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_QSPI_DPD_REQ_0_CODE_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_QSPI_DPD_REQ_0_CODE_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_QSPI_DPD_REQ_0_CODE_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_QSPI_DPD_REQ_0_CODE_IDLE                    MK_ENUM_CONST(0)
#define PMC_IMPL_IO_QSPI_DPD_REQ_0_CODE_DPD_OFF                 MK_ENUM_CONST(1)
#define PMC_IMPL_IO_QSPI_DPD_REQ_0_CODE_DPD_ON                  MK_ENUM_CONST(2)

// puts QSPI PAD(s) in/out of Depp Power Down (DPD) mode
#define PMC_IMPL_IO_QSPI_DPD_REQ_0_QSPI_SHIFT                   MK_SHIFT_CONST(0)
#define PMC_IMPL_IO_QSPI_DPD_REQ_0_QSPI_FIELD                   MK_FIELD_CONST(0x1, PMC_IMPL_IO_QSPI_DPD_REQ_0_QSPI_SHIFT)
#define PMC_IMPL_IO_QSPI_DPD_REQ_0_QSPI_RANGE                   0:0
#define PMC_IMPL_IO_QSPI_DPD_REQ_0_QSPI_MSB                     MK_SHIFT_CONST(0)
#define PMC_IMPL_IO_QSPI_DPD_REQ_0_QSPI_LSB                     MK_SHIFT_CONST(0)
#define PMC_IMPL_IO_QSPI_DPD_REQ_0_QSPI_WOFFSET                 0x0
#define PMC_IMPL_IO_QSPI_DPD_REQ_0_QSPI_DEFAULT                 MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_QSPI_DPD_REQ_0_QSPI_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_QSPI_DPD_REQ_0_QSPI_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_QSPI_DPD_REQ_0_QSPI_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_QSPI_DPD_REQ_0_QSPI_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_QSPI_DPD_REQ_0_QSPI_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_QSPI_DPD_REQ_0_QSPI_OFF                     MK_ENUM_CONST(0)
#define PMC_IMPL_IO_QSPI_DPD_REQ_0_QSPI_ON                      MK_ENUM_CONST(1)


// Register PMC_IMPL_IO_QSPI_DPD_STATUS_0
#define PMC_IMPL_IO_QSPI_DPD_STATUS_0                   MK_ADDR_CONST(0xe078)
#define PMC_IMPL_IO_QSPI_DPD_STATUS_0_SECURE                    0x0
#define PMC_IMPL_IO_QSPI_DPD_STATUS_0_DUAL                      0x0
#define PMC_IMPL_IO_QSPI_DPD_STATUS_0_SCR                       IO_QSPI_SCR_0
#define PMC_IMPL_IO_QSPI_DPD_STATUS_0_SCRREG                    PMC_IMPL_SCR_IO_QSPI_SCR_0
#define PMC_IMPL_IO_QSPI_DPD_STATUS_0_WORD_COUNT                        0x1
#define PMC_IMPL_IO_QSPI_DPD_STATUS_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_QSPI_DPD_STATUS_0_RESET_MASK                        MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_QSPI_DPD_STATUS_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_QSPI_DPD_STATUS_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_QSPI_DPD_STATUS_0_READ_MASK                         MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_QSPI_DPD_STATUS_0_WRITE_MASK                        MK_MASK_CONST(0x0)
// On - QSPI PAD(s) is in Deep Power Down mode, Off - QSPI PAD(s) is out of Deep Power Down mode
#define PMC_IMPL_IO_QSPI_DPD_STATUS_0_QSPI_SHIFT                        MK_SHIFT_CONST(0)
#define PMC_IMPL_IO_QSPI_DPD_STATUS_0_QSPI_FIELD                        MK_FIELD_CONST(0x1, PMC_IMPL_IO_QSPI_DPD_STATUS_0_QSPI_SHIFT)
#define PMC_IMPL_IO_QSPI_DPD_STATUS_0_QSPI_RANGE                        0:0
#define PMC_IMPL_IO_QSPI_DPD_STATUS_0_QSPI_MSB                  MK_SHIFT_CONST(0)
#define PMC_IMPL_IO_QSPI_DPD_STATUS_0_QSPI_LSB                  MK_SHIFT_CONST(0)
#define PMC_IMPL_IO_QSPI_DPD_STATUS_0_QSPI_WOFFSET                      0x0
#define PMC_IMPL_IO_QSPI_DPD_STATUS_0_QSPI_DEFAULT                      MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_QSPI_DPD_STATUS_0_QSPI_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_QSPI_DPD_STATUS_0_QSPI_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_QSPI_DPD_STATUS_0_QSPI_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_QSPI_DPD_STATUS_0_QSPI_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_QSPI_DPD_STATUS_0_QSPI_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_QSPI_DPD_STATUS_0_QSPI_OFF                  MK_ENUM_CONST(0)
#define PMC_IMPL_IO_QSPI_DPD_STATUS_0_QSPI_ON                   MK_ENUM_CONST(1)


// Register PMC_IMPL_IO_G7_DPD_REQ_0
#define PMC_IMPL_IO_G7_DPD_REQ_0                        MK_ADDR_CONST(0xe07c)
#define PMC_IMPL_IO_G7_DPD_REQ_0_SECURE                         0x0
#define PMC_IMPL_IO_G7_DPD_REQ_0_DUAL                   0x0
#define PMC_IMPL_IO_G7_DPD_REQ_0_SCR                    IO_G7_SCR_0
#define PMC_IMPL_IO_G7_DPD_REQ_0_SCRREG                         PMC_IMPL_SCR_IO_G7_SCR_0
#define PMC_IMPL_IO_G7_DPD_REQ_0_WORD_COUNT                     0x1
#define PMC_IMPL_IO_G7_DPD_REQ_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_G7_DPD_REQ_0_RESET_MASK                     MK_MASK_CONST(0xc000000f)
#define PMC_IMPL_IO_G7_DPD_REQ_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_G7_DPD_REQ_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_G7_DPD_REQ_0_READ_MASK                      MK_MASK_CONST(0xc000000f)
#define PMC_IMPL_IO_G7_DPD_REQ_0_WRITE_MASK                     MK_MASK_CONST(0xc000000f)
// code of operation for all set bits
#define PMC_IMPL_IO_G7_DPD_REQ_0_CODE_SHIFT                     MK_SHIFT_CONST(30)
#define PMC_IMPL_IO_G7_DPD_REQ_0_CODE_FIELD                     MK_FIELD_CONST(0x3, PMC_IMPL_IO_G7_DPD_REQ_0_CODE_SHIFT)
#define PMC_IMPL_IO_G7_DPD_REQ_0_CODE_RANGE                     31:30
#define PMC_IMPL_IO_G7_DPD_REQ_0_CODE_MSB                       MK_SHIFT_CONST(31)
#define PMC_IMPL_IO_G7_DPD_REQ_0_CODE_LSB                       MK_SHIFT_CONST(30)
#define PMC_IMPL_IO_G7_DPD_REQ_0_CODE_WOFFSET                   0x0
#define PMC_IMPL_IO_G7_DPD_REQ_0_CODE_DEFAULT                   MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_G7_DPD_REQ_0_CODE_DEFAULT_MASK                      MK_MASK_CONST(0x3)
#define PMC_IMPL_IO_G7_DPD_REQ_0_CODE_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_G7_DPD_REQ_0_CODE_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_G7_DPD_REQ_0_CODE_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_G7_DPD_REQ_0_CODE_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_G7_DPD_REQ_0_CODE_IDLE                      MK_ENUM_CONST(0)
#define PMC_IMPL_IO_G7_DPD_REQ_0_CODE_DPD_OFF                   MK_ENUM_CONST(1)
#define PMC_IMPL_IO_G7_DPD_REQ_0_CODE_DPD_ON                    MK_ENUM_CONST(2)

// puts SOC_GPIO57 PAD(s) in/out of Depp Power Down (DPD) mode
#define PMC_IMPL_IO_G7_DPD_REQ_0_SOC_GPIO57_SHIFT                       MK_SHIFT_CONST(0)
#define PMC_IMPL_IO_G7_DPD_REQ_0_SOC_GPIO57_FIELD                       MK_FIELD_CONST(0x1, PMC_IMPL_IO_G7_DPD_REQ_0_SOC_GPIO57_SHIFT)
#define PMC_IMPL_IO_G7_DPD_REQ_0_SOC_GPIO57_RANGE                       0:0
#define PMC_IMPL_IO_G7_DPD_REQ_0_SOC_GPIO57_MSB                 MK_SHIFT_CONST(0)
#define PMC_IMPL_IO_G7_DPD_REQ_0_SOC_GPIO57_LSB                 MK_SHIFT_CONST(0)
#define PMC_IMPL_IO_G7_DPD_REQ_0_SOC_GPIO57_WOFFSET                     0x0
#define PMC_IMPL_IO_G7_DPD_REQ_0_SOC_GPIO57_DEFAULT                     MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_G7_DPD_REQ_0_SOC_GPIO57_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_G7_DPD_REQ_0_SOC_GPIO57_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_G7_DPD_REQ_0_SOC_GPIO57_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_G7_DPD_REQ_0_SOC_GPIO57_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_G7_DPD_REQ_0_SOC_GPIO57_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_G7_DPD_REQ_0_SOC_GPIO57_OFF                 MK_ENUM_CONST(0)
#define PMC_IMPL_IO_G7_DPD_REQ_0_SOC_GPIO57_ON                  MK_ENUM_CONST(1)

// puts DAP1 PAD(s) in/out of Depp Power Down (DPD) mode
#define PMC_IMPL_IO_G7_DPD_REQ_0_DAP1_SHIFT                     MK_SHIFT_CONST(1)
#define PMC_IMPL_IO_G7_DPD_REQ_0_DAP1_FIELD                     MK_FIELD_CONST(0x1, PMC_IMPL_IO_G7_DPD_REQ_0_DAP1_SHIFT)
#define PMC_IMPL_IO_G7_DPD_REQ_0_DAP1_RANGE                     1:1
#define PMC_IMPL_IO_G7_DPD_REQ_0_DAP1_MSB                       MK_SHIFT_CONST(1)
#define PMC_IMPL_IO_G7_DPD_REQ_0_DAP1_LSB                       MK_SHIFT_CONST(1)
#define PMC_IMPL_IO_G7_DPD_REQ_0_DAP1_WOFFSET                   0x0
#define PMC_IMPL_IO_G7_DPD_REQ_0_DAP1_DEFAULT                   MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_G7_DPD_REQ_0_DAP1_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_G7_DPD_REQ_0_DAP1_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_G7_DPD_REQ_0_DAP1_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_G7_DPD_REQ_0_DAP1_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_G7_DPD_REQ_0_DAP1_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_G7_DPD_REQ_0_DAP1_OFF                       MK_ENUM_CONST(0)
#define PMC_IMPL_IO_G7_DPD_REQ_0_DAP1_ON                        MK_ENUM_CONST(1)

// puts SPI5 PAD(s) in/out of Depp Power Down (DPD) mode
#define PMC_IMPL_IO_G7_DPD_REQ_0_SPI5_SHIFT                     MK_SHIFT_CONST(2)
#define PMC_IMPL_IO_G7_DPD_REQ_0_SPI5_FIELD                     MK_FIELD_CONST(0x1, PMC_IMPL_IO_G7_DPD_REQ_0_SPI5_SHIFT)
#define PMC_IMPL_IO_G7_DPD_REQ_0_SPI5_RANGE                     2:2
#define PMC_IMPL_IO_G7_DPD_REQ_0_SPI5_MSB                       MK_SHIFT_CONST(2)
#define PMC_IMPL_IO_G7_DPD_REQ_0_SPI5_LSB                       MK_SHIFT_CONST(2)
#define PMC_IMPL_IO_G7_DPD_REQ_0_SPI5_WOFFSET                   0x0
#define PMC_IMPL_IO_G7_DPD_REQ_0_SPI5_DEFAULT                   MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_G7_DPD_REQ_0_SPI5_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_G7_DPD_REQ_0_SPI5_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_G7_DPD_REQ_0_SPI5_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_G7_DPD_REQ_0_SPI5_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_G7_DPD_REQ_0_SPI5_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_G7_DPD_REQ_0_SPI5_OFF                       MK_ENUM_CONST(0)
#define PMC_IMPL_IO_G7_DPD_REQ_0_SPI5_ON                        MK_ENUM_CONST(1)

// puts G7 PAD(s) in/out of Depp Power Down (DPD) mode
#define PMC_IMPL_IO_G7_DPD_REQ_0_G7_SHIFT                       MK_SHIFT_CONST(3)
#define PMC_IMPL_IO_G7_DPD_REQ_0_G7_FIELD                       MK_FIELD_CONST(0x1, PMC_IMPL_IO_G7_DPD_REQ_0_G7_SHIFT)
#define PMC_IMPL_IO_G7_DPD_REQ_0_G7_RANGE                       3:3
#define PMC_IMPL_IO_G7_DPD_REQ_0_G7_MSB                 MK_SHIFT_CONST(3)
#define PMC_IMPL_IO_G7_DPD_REQ_0_G7_LSB                 MK_SHIFT_CONST(3)
#define PMC_IMPL_IO_G7_DPD_REQ_0_G7_WOFFSET                     0x0
#define PMC_IMPL_IO_G7_DPD_REQ_0_G7_DEFAULT                     MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_G7_DPD_REQ_0_G7_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_G7_DPD_REQ_0_G7_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_G7_DPD_REQ_0_G7_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_G7_DPD_REQ_0_G7_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_G7_DPD_REQ_0_G7_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_G7_DPD_REQ_0_G7_OFF                 MK_ENUM_CONST(0)
#define PMC_IMPL_IO_G7_DPD_REQ_0_G7_ON                  MK_ENUM_CONST(1)


// Register PMC_IMPL_IO_G7_DPD_STATUS_0
#define PMC_IMPL_IO_G7_DPD_STATUS_0                     MK_ADDR_CONST(0xe080)
#define PMC_IMPL_IO_G7_DPD_STATUS_0_SECURE                      0x0
#define PMC_IMPL_IO_G7_DPD_STATUS_0_DUAL                        0x0
#define PMC_IMPL_IO_G7_DPD_STATUS_0_SCR                         IO_G7_SCR_0
#define PMC_IMPL_IO_G7_DPD_STATUS_0_SCRREG                      PMC_IMPL_SCR_IO_G7_SCR_0
#define PMC_IMPL_IO_G7_DPD_STATUS_0_WORD_COUNT                  0x1
#define PMC_IMPL_IO_G7_DPD_STATUS_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_G7_DPD_STATUS_0_RESET_MASK                  MK_MASK_CONST(0xf)
#define PMC_IMPL_IO_G7_DPD_STATUS_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_G7_DPD_STATUS_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_G7_DPD_STATUS_0_READ_MASK                   MK_MASK_CONST(0xf)
#define PMC_IMPL_IO_G7_DPD_STATUS_0_WRITE_MASK                  MK_MASK_CONST(0x0)
// On - SOC_GPIO57 PAD(s) is in Deep Power Down mode, Off - SOC_GPIO57 PAD(s) is out of Deep Power Down mode
#define PMC_IMPL_IO_G7_DPD_STATUS_0_SOC_GPIO57_SHIFT                    MK_SHIFT_CONST(0)
#define PMC_IMPL_IO_G7_DPD_STATUS_0_SOC_GPIO57_FIELD                    MK_FIELD_CONST(0x1, PMC_IMPL_IO_G7_DPD_STATUS_0_SOC_GPIO57_SHIFT)
#define PMC_IMPL_IO_G7_DPD_STATUS_0_SOC_GPIO57_RANGE                    0:0
#define PMC_IMPL_IO_G7_DPD_STATUS_0_SOC_GPIO57_MSB                      MK_SHIFT_CONST(0)
#define PMC_IMPL_IO_G7_DPD_STATUS_0_SOC_GPIO57_LSB                      MK_SHIFT_CONST(0)
#define PMC_IMPL_IO_G7_DPD_STATUS_0_SOC_GPIO57_WOFFSET                  0x0
#define PMC_IMPL_IO_G7_DPD_STATUS_0_SOC_GPIO57_DEFAULT                  MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_G7_DPD_STATUS_0_SOC_GPIO57_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_G7_DPD_STATUS_0_SOC_GPIO57_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_G7_DPD_STATUS_0_SOC_GPIO57_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_G7_DPD_STATUS_0_SOC_GPIO57_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_G7_DPD_STATUS_0_SOC_GPIO57_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_G7_DPD_STATUS_0_SOC_GPIO57_OFF                      MK_ENUM_CONST(0)
#define PMC_IMPL_IO_G7_DPD_STATUS_0_SOC_GPIO57_ON                       MK_ENUM_CONST(1)

// On - DAP1 PAD(s) is in Deep Power Down mode, Off - DAP1 PAD(s) is out of Deep Power Down mode
#define PMC_IMPL_IO_G7_DPD_STATUS_0_DAP1_SHIFT                  MK_SHIFT_CONST(1)
#define PMC_IMPL_IO_G7_DPD_STATUS_0_DAP1_FIELD                  MK_FIELD_CONST(0x1, PMC_IMPL_IO_G7_DPD_STATUS_0_DAP1_SHIFT)
#define PMC_IMPL_IO_G7_DPD_STATUS_0_DAP1_RANGE                  1:1
#define PMC_IMPL_IO_G7_DPD_STATUS_0_DAP1_MSB                    MK_SHIFT_CONST(1)
#define PMC_IMPL_IO_G7_DPD_STATUS_0_DAP1_LSB                    MK_SHIFT_CONST(1)
#define PMC_IMPL_IO_G7_DPD_STATUS_0_DAP1_WOFFSET                        0x0
#define PMC_IMPL_IO_G7_DPD_STATUS_0_DAP1_DEFAULT                        MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_G7_DPD_STATUS_0_DAP1_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_G7_DPD_STATUS_0_DAP1_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_G7_DPD_STATUS_0_DAP1_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_G7_DPD_STATUS_0_DAP1_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_G7_DPD_STATUS_0_DAP1_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_G7_DPD_STATUS_0_DAP1_OFF                    MK_ENUM_CONST(0)
#define PMC_IMPL_IO_G7_DPD_STATUS_0_DAP1_ON                     MK_ENUM_CONST(1)

// On - SPI5 PAD(s) is in Deep Power Down mode, Off - SPI5 PAD(s) is out of Deep Power Down mode
#define PMC_IMPL_IO_G7_DPD_STATUS_0_SPI5_SHIFT                  MK_SHIFT_CONST(2)
#define PMC_IMPL_IO_G7_DPD_STATUS_0_SPI5_FIELD                  MK_FIELD_CONST(0x1, PMC_IMPL_IO_G7_DPD_STATUS_0_SPI5_SHIFT)
#define PMC_IMPL_IO_G7_DPD_STATUS_0_SPI5_RANGE                  2:2
#define PMC_IMPL_IO_G7_DPD_STATUS_0_SPI5_MSB                    MK_SHIFT_CONST(2)
#define PMC_IMPL_IO_G7_DPD_STATUS_0_SPI5_LSB                    MK_SHIFT_CONST(2)
#define PMC_IMPL_IO_G7_DPD_STATUS_0_SPI5_WOFFSET                        0x0
#define PMC_IMPL_IO_G7_DPD_STATUS_0_SPI5_DEFAULT                        MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_G7_DPD_STATUS_0_SPI5_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_G7_DPD_STATUS_0_SPI5_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_G7_DPD_STATUS_0_SPI5_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_G7_DPD_STATUS_0_SPI5_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_G7_DPD_STATUS_0_SPI5_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_G7_DPD_STATUS_0_SPI5_OFF                    MK_ENUM_CONST(0)
#define PMC_IMPL_IO_G7_DPD_STATUS_0_SPI5_ON                     MK_ENUM_CONST(1)

// On - G7 PAD(s) is in Deep Power Down mode, Off - G7 PAD(s) is out of Deep Power Down mode
#define PMC_IMPL_IO_G7_DPD_STATUS_0_G7_SHIFT                    MK_SHIFT_CONST(3)
#define PMC_IMPL_IO_G7_DPD_STATUS_0_G7_FIELD                    MK_FIELD_CONST(0x1, PMC_IMPL_IO_G7_DPD_STATUS_0_G7_SHIFT)
#define PMC_IMPL_IO_G7_DPD_STATUS_0_G7_RANGE                    3:3
#define PMC_IMPL_IO_G7_DPD_STATUS_0_G7_MSB                      MK_SHIFT_CONST(3)
#define PMC_IMPL_IO_G7_DPD_STATUS_0_G7_LSB                      MK_SHIFT_CONST(3)
#define PMC_IMPL_IO_G7_DPD_STATUS_0_G7_WOFFSET                  0x0
#define PMC_IMPL_IO_G7_DPD_STATUS_0_G7_DEFAULT                  MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_G7_DPD_STATUS_0_G7_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_G7_DPD_STATUS_0_G7_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_G7_DPD_STATUS_0_G7_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_G7_DPD_STATUS_0_G7_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_G7_DPD_STATUS_0_G7_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_G7_DPD_STATUS_0_G7_OFF                      MK_ENUM_CONST(0)
#define PMC_IMPL_IO_G7_DPD_STATUS_0_G7_ON                       MK_ENUM_CONST(1)


// Register PMC_IMPL_IO_AO_HV_DPD_REQ_0
#define PMC_IMPL_IO_AO_HV_DPD_REQ_0                     MK_ADDR_CONST(0xe084)
#define PMC_IMPL_IO_AO_HV_DPD_REQ_0_SECURE                      0x0
#define PMC_IMPL_IO_AO_HV_DPD_REQ_0_DUAL                        0x0
#define PMC_IMPL_IO_AO_HV_DPD_REQ_0_SCR                         IO_AO_HV_SCR_0
#define PMC_IMPL_IO_AO_HV_DPD_REQ_0_SCRREG                      PMC_IMPL_SCR_IO_AO_HV_SCR_0
#define PMC_IMPL_IO_AO_HV_DPD_REQ_0_WORD_COUNT                  0x1
#define PMC_IMPL_IO_AO_HV_DPD_REQ_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_AO_HV_DPD_REQ_0_RESET_MASK                  MK_MASK_CONST(0xc0000fff)
#define PMC_IMPL_IO_AO_HV_DPD_REQ_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_AO_HV_DPD_REQ_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_AO_HV_DPD_REQ_0_READ_MASK                   MK_MASK_CONST(0xc0000fff)
#define PMC_IMPL_IO_AO_HV_DPD_REQ_0_WRITE_MASK                  MK_MASK_CONST(0xc0000fff)
// code of operation for all set bits
#define PMC_IMPL_IO_AO_HV_DPD_REQ_0_CODE_SHIFT                  MK_SHIFT_CONST(30)
#define PMC_IMPL_IO_AO_HV_DPD_REQ_0_CODE_FIELD                  MK_FIELD_CONST(0x3, PMC_IMPL_IO_AO_HV_DPD_REQ_0_CODE_SHIFT)
#define PMC_IMPL_IO_AO_HV_DPD_REQ_0_CODE_RANGE                  31:30
#define PMC_IMPL_IO_AO_HV_DPD_REQ_0_CODE_MSB                    MK_SHIFT_CONST(31)
#define PMC_IMPL_IO_AO_HV_DPD_REQ_0_CODE_LSB                    MK_SHIFT_CONST(30)
#define PMC_IMPL_IO_AO_HV_DPD_REQ_0_CODE_WOFFSET                        0x0
#define PMC_IMPL_IO_AO_HV_DPD_REQ_0_CODE_DEFAULT                        MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_AO_HV_DPD_REQ_0_CODE_DEFAULT_MASK                   MK_MASK_CONST(0x3)
#define PMC_IMPL_IO_AO_HV_DPD_REQ_0_CODE_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_AO_HV_DPD_REQ_0_CODE_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_AO_HV_DPD_REQ_0_CODE_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_AO_HV_DPD_REQ_0_CODE_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_AO_HV_DPD_REQ_0_CODE_IDLE                   MK_ENUM_CONST(0)
#define PMC_IMPL_IO_AO_HV_DPD_REQ_0_CODE_DPD_OFF                        MK_ENUM_CONST(1)
#define PMC_IMPL_IO_AO_HV_DPD_REQ_0_CODE_DPD_ON                 MK_ENUM_CONST(2)

// puts CAN0_DOUT PAD(s) in/out of Depp Power Down (DPD) mode
#define PMC_IMPL_IO_AO_HV_DPD_REQ_0_CAN0_DOUT_SHIFT                     MK_SHIFT_CONST(0)
#define PMC_IMPL_IO_AO_HV_DPD_REQ_0_CAN0_DOUT_FIELD                     MK_FIELD_CONST(0x1, PMC_IMPL_IO_AO_HV_DPD_REQ_0_CAN0_DOUT_SHIFT)
#define PMC_IMPL_IO_AO_HV_DPD_REQ_0_CAN0_DOUT_RANGE                     0:0
#define PMC_IMPL_IO_AO_HV_DPD_REQ_0_CAN0_DOUT_MSB                       MK_SHIFT_CONST(0)
#define PMC_IMPL_IO_AO_HV_DPD_REQ_0_CAN0_DOUT_LSB                       MK_SHIFT_CONST(0)
#define PMC_IMPL_IO_AO_HV_DPD_REQ_0_CAN0_DOUT_WOFFSET                   0x0
#define PMC_IMPL_IO_AO_HV_DPD_REQ_0_CAN0_DOUT_DEFAULT                   MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_AO_HV_DPD_REQ_0_CAN0_DOUT_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_AO_HV_DPD_REQ_0_CAN0_DOUT_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_AO_HV_DPD_REQ_0_CAN0_DOUT_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_AO_HV_DPD_REQ_0_CAN0_DOUT_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_AO_HV_DPD_REQ_0_CAN0_DOUT_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_AO_HV_DPD_REQ_0_CAN0_DOUT_OFF                       MK_ENUM_CONST(0)
#define PMC_IMPL_IO_AO_HV_DPD_REQ_0_CAN0_DOUT_ON                        MK_ENUM_CONST(1)

// puts CAN0_DIN PAD(s) in/out of Depp Power Down (DPD) mode
#define PMC_IMPL_IO_AO_HV_DPD_REQ_0_CAN0_DIN_SHIFT                      MK_SHIFT_CONST(1)
#define PMC_IMPL_IO_AO_HV_DPD_REQ_0_CAN0_DIN_FIELD                      MK_FIELD_CONST(0x1, PMC_IMPL_IO_AO_HV_DPD_REQ_0_CAN0_DIN_SHIFT)
#define PMC_IMPL_IO_AO_HV_DPD_REQ_0_CAN0_DIN_RANGE                      1:1
#define PMC_IMPL_IO_AO_HV_DPD_REQ_0_CAN0_DIN_MSB                        MK_SHIFT_CONST(1)
#define PMC_IMPL_IO_AO_HV_DPD_REQ_0_CAN0_DIN_LSB                        MK_SHIFT_CONST(1)
#define PMC_IMPL_IO_AO_HV_DPD_REQ_0_CAN0_DIN_WOFFSET                    0x0
#define PMC_IMPL_IO_AO_HV_DPD_REQ_0_CAN0_DIN_DEFAULT                    MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_AO_HV_DPD_REQ_0_CAN0_DIN_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_AO_HV_DPD_REQ_0_CAN0_DIN_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_AO_HV_DPD_REQ_0_CAN0_DIN_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_AO_HV_DPD_REQ_0_CAN0_DIN_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_AO_HV_DPD_REQ_0_CAN0_DIN_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_AO_HV_DPD_REQ_0_CAN0_DIN_OFF                        MK_ENUM_CONST(0)
#define PMC_IMPL_IO_AO_HV_DPD_REQ_0_CAN0_DIN_ON                 MK_ENUM_CONST(1)

// puts CAN1_DOUT PAD(s) in/out of Depp Power Down (DPD) mode
#define PMC_IMPL_IO_AO_HV_DPD_REQ_0_CAN1_DOUT_SHIFT                     MK_SHIFT_CONST(2)
#define PMC_IMPL_IO_AO_HV_DPD_REQ_0_CAN1_DOUT_FIELD                     MK_FIELD_CONST(0x1, PMC_IMPL_IO_AO_HV_DPD_REQ_0_CAN1_DOUT_SHIFT)
#define PMC_IMPL_IO_AO_HV_DPD_REQ_0_CAN1_DOUT_RANGE                     2:2
#define PMC_IMPL_IO_AO_HV_DPD_REQ_0_CAN1_DOUT_MSB                       MK_SHIFT_CONST(2)
#define PMC_IMPL_IO_AO_HV_DPD_REQ_0_CAN1_DOUT_LSB                       MK_SHIFT_CONST(2)
#define PMC_IMPL_IO_AO_HV_DPD_REQ_0_CAN1_DOUT_WOFFSET                   0x0
#define PMC_IMPL_IO_AO_HV_DPD_REQ_0_CAN1_DOUT_DEFAULT                   MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_AO_HV_DPD_REQ_0_CAN1_DOUT_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_AO_HV_DPD_REQ_0_CAN1_DOUT_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_AO_HV_DPD_REQ_0_CAN1_DOUT_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_AO_HV_DPD_REQ_0_CAN1_DOUT_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_AO_HV_DPD_REQ_0_CAN1_DOUT_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_AO_HV_DPD_REQ_0_CAN1_DOUT_OFF                       MK_ENUM_CONST(0)
#define PMC_IMPL_IO_AO_HV_DPD_REQ_0_CAN1_DOUT_ON                        MK_ENUM_CONST(1)

// puts CAN1_DIN PAD(s) in/out of Depp Power Down (DPD) mode
#define PMC_IMPL_IO_AO_HV_DPD_REQ_0_CAN1_DIN_SHIFT                      MK_SHIFT_CONST(3)
#define PMC_IMPL_IO_AO_HV_DPD_REQ_0_CAN1_DIN_FIELD                      MK_FIELD_CONST(0x1, PMC_IMPL_IO_AO_HV_DPD_REQ_0_CAN1_DIN_SHIFT)
#define PMC_IMPL_IO_AO_HV_DPD_REQ_0_CAN1_DIN_RANGE                      3:3
#define PMC_IMPL_IO_AO_HV_DPD_REQ_0_CAN1_DIN_MSB                        MK_SHIFT_CONST(3)
#define PMC_IMPL_IO_AO_HV_DPD_REQ_0_CAN1_DIN_LSB                        MK_SHIFT_CONST(3)
#define PMC_IMPL_IO_AO_HV_DPD_REQ_0_CAN1_DIN_WOFFSET                    0x0
#define PMC_IMPL_IO_AO_HV_DPD_REQ_0_CAN1_DIN_DEFAULT                    MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_AO_HV_DPD_REQ_0_CAN1_DIN_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_AO_HV_DPD_REQ_0_CAN1_DIN_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_AO_HV_DPD_REQ_0_CAN1_DIN_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_AO_HV_DPD_REQ_0_CAN1_DIN_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_AO_HV_DPD_REQ_0_CAN1_DIN_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_AO_HV_DPD_REQ_0_CAN1_DIN_OFF                        MK_ENUM_CONST(0)
#define PMC_IMPL_IO_AO_HV_DPD_REQ_0_CAN1_DIN_ON                 MK_ENUM_CONST(1)

// puts CAN0_STB PAD(s) in/out of Depp Power Down (DPD) mode
#define PMC_IMPL_IO_AO_HV_DPD_REQ_0_CAN0_STB_SHIFT                      MK_SHIFT_CONST(4)
#define PMC_IMPL_IO_AO_HV_DPD_REQ_0_CAN0_STB_FIELD                      MK_FIELD_CONST(0x1, PMC_IMPL_IO_AO_HV_DPD_REQ_0_CAN0_STB_SHIFT)
#define PMC_IMPL_IO_AO_HV_DPD_REQ_0_CAN0_STB_RANGE                      4:4
#define PMC_IMPL_IO_AO_HV_DPD_REQ_0_CAN0_STB_MSB                        MK_SHIFT_CONST(4)
#define PMC_IMPL_IO_AO_HV_DPD_REQ_0_CAN0_STB_LSB                        MK_SHIFT_CONST(4)
#define PMC_IMPL_IO_AO_HV_DPD_REQ_0_CAN0_STB_WOFFSET                    0x0
#define PMC_IMPL_IO_AO_HV_DPD_REQ_0_CAN0_STB_DEFAULT                    MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_AO_HV_DPD_REQ_0_CAN0_STB_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_AO_HV_DPD_REQ_0_CAN0_STB_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_AO_HV_DPD_REQ_0_CAN0_STB_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_AO_HV_DPD_REQ_0_CAN0_STB_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_AO_HV_DPD_REQ_0_CAN0_STB_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_AO_HV_DPD_REQ_0_CAN0_STB_OFF                        MK_ENUM_CONST(0)
#define PMC_IMPL_IO_AO_HV_DPD_REQ_0_CAN0_STB_ON                 MK_ENUM_CONST(1)

// puts CAN0_EN PAD(s) in/out of Depp Power Down (DPD) mode
#define PMC_IMPL_IO_AO_HV_DPD_REQ_0_CAN0_EN_SHIFT                       MK_SHIFT_CONST(5)
#define PMC_IMPL_IO_AO_HV_DPD_REQ_0_CAN0_EN_FIELD                       MK_FIELD_CONST(0x1, PMC_IMPL_IO_AO_HV_DPD_REQ_0_CAN0_EN_SHIFT)
#define PMC_IMPL_IO_AO_HV_DPD_REQ_0_CAN0_EN_RANGE                       5:5
#define PMC_IMPL_IO_AO_HV_DPD_REQ_0_CAN0_EN_MSB                 MK_SHIFT_CONST(5)
#define PMC_IMPL_IO_AO_HV_DPD_REQ_0_CAN0_EN_LSB                 MK_SHIFT_CONST(5)
#define PMC_IMPL_IO_AO_HV_DPD_REQ_0_CAN0_EN_WOFFSET                     0x0
#define PMC_IMPL_IO_AO_HV_DPD_REQ_0_CAN0_EN_DEFAULT                     MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_AO_HV_DPD_REQ_0_CAN0_EN_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_AO_HV_DPD_REQ_0_CAN0_EN_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_AO_HV_DPD_REQ_0_CAN0_EN_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_AO_HV_DPD_REQ_0_CAN0_EN_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_AO_HV_DPD_REQ_0_CAN0_EN_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_AO_HV_DPD_REQ_0_CAN0_EN_OFF                 MK_ENUM_CONST(0)
#define PMC_IMPL_IO_AO_HV_DPD_REQ_0_CAN0_EN_ON                  MK_ENUM_CONST(1)

// puts SOC_GPIO49 PAD(s) in/out of Depp Power Down (DPD) mode
#define PMC_IMPL_IO_AO_HV_DPD_REQ_0_SOC_GPIO49_SHIFT                    MK_SHIFT_CONST(6)
#define PMC_IMPL_IO_AO_HV_DPD_REQ_0_SOC_GPIO49_FIELD                    MK_FIELD_CONST(0x1, PMC_IMPL_IO_AO_HV_DPD_REQ_0_SOC_GPIO49_SHIFT)
#define PMC_IMPL_IO_AO_HV_DPD_REQ_0_SOC_GPIO49_RANGE                    6:6
#define PMC_IMPL_IO_AO_HV_DPD_REQ_0_SOC_GPIO49_MSB                      MK_SHIFT_CONST(6)
#define PMC_IMPL_IO_AO_HV_DPD_REQ_0_SOC_GPIO49_LSB                      MK_SHIFT_CONST(6)
#define PMC_IMPL_IO_AO_HV_DPD_REQ_0_SOC_GPIO49_WOFFSET                  0x0
#define PMC_IMPL_IO_AO_HV_DPD_REQ_0_SOC_GPIO49_DEFAULT                  MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_AO_HV_DPD_REQ_0_SOC_GPIO49_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_AO_HV_DPD_REQ_0_SOC_GPIO49_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_AO_HV_DPD_REQ_0_SOC_GPIO49_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_AO_HV_DPD_REQ_0_SOC_GPIO49_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_AO_HV_DPD_REQ_0_SOC_GPIO49_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_AO_HV_DPD_REQ_0_SOC_GPIO49_OFF                      MK_ENUM_CONST(0)
#define PMC_IMPL_IO_AO_HV_DPD_REQ_0_SOC_GPIO49_ON                       MK_ENUM_CONST(1)

// puts CAN0_ERR PAD(s) in/out of Depp Power Down (DPD) mode
#define PMC_IMPL_IO_AO_HV_DPD_REQ_0_CAN0_ERR_SHIFT                      MK_SHIFT_CONST(7)
#define PMC_IMPL_IO_AO_HV_DPD_REQ_0_CAN0_ERR_FIELD                      MK_FIELD_CONST(0x1, PMC_IMPL_IO_AO_HV_DPD_REQ_0_CAN0_ERR_SHIFT)
#define PMC_IMPL_IO_AO_HV_DPD_REQ_0_CAN0_ERR_RANGE                      7:7
#define PMC_IMPL_IO_AO_HV_DPD_REQ_0_CAN0_ERR_MSB                        MK_SHIFT_CONST(7)
#define PMC_IMPL_IO_AO_HV_DPD_REQ_0_CAN0_ERR_LSB                        MK_SHIFT_CONST(7)
#define PMC_IMPL_IO_AO_HV_DPD_REQ_0_CAN0_ERR_WOFFSET                    0x0
#define PMC_IMPL_IO_AO_HV_DPD_REQ_0_CAN0_ERR_DEFAULT                    MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_AO_HV_DPD_REQ_0_CAN0_ERR_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_AO_HV_DPD_REQ_0_CAN0_ERR_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_AO_HV_DPD_REQ_0_CAN0_ERR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_AO_HV_DPD_REQ_0_CAN0_ERR_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_AO_HV_DPD_REQ_0_CAN0_ERR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_AO_HV_DPD_REQ_0_CAN0_ERR_OFF                        MK_ENUM_CONST(0)
#define PMC_IMPL_IO_AO_HV_DPD_REQ_0_CAN0_ERR_ON                 MK_ENUM_CONST(1)

// puts CAN1_STB PAD(s) in/out of Depp Power Down (DPD) mode
#define PMC_IMPL_IO_AO_HV_DPD_REQ_0_CAN1_STB_SHIFT                      MK_SHIFT_CONST(8)
#define PMC_IMPL_IO_AO_HV_DPD_REQ_0_CAN1_STB_FIELD                      MK_FIELD_CONST(0x1, PMC_IMPL_IO_AO_HV_DPD_REQ_0_CAN1_STB_SHIFT)
#define PMC_IMPL_IO_AO_HV_DPD_REQ_0_CAN1_STB_RANGE                      8:8
#define PMC_IMPL_IO_AO_HV_DPD_REQ_0_CAN1_STB_MSB                        MK_SHIFT_CONST(8)
#define PMC_IMPL_IO_AO_HV_DPD_REQ_0_CAN1_STB_LSB                        MK_SHIFT_CONST(8)
#define PMC_IMPL_IO_AO_HV_DPD_REQ_0_CAN1_STB_WOFFSET                    0x0
#define PMC_IMPL_IO_AO_HV_DPD_REQ_0_CAN1_STB_DEFAULT                    MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_AO_HV_DPD_REQ_0_CAN1_STB_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_AO_HV_DPD_REQ_0_CAN1_STB_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_AO_HV_DPD_REQ_0_CAN1_STB_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_AO_HV_DPD_REQ_0_CAN1_STB_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_AO_HV_DPD_REQ_0_CAN1_STB_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_AO_HV_DPD_REQ_0_CAN1_STB_OFF                        MK_ENUM_CONST(0)
#define PMC_IMPL_IO_AO_HV_DPD_REQ_0_CAN1_STB_ON                 MK_ENUM_CONST(1)

// puts CAN1_EN PAD(s) in/out of Depp Power Down (DPD) mode
#define PMC_IMPL_IO_AO_HV_DPD_REQ_0_CAN1_EN_SHIFT                       MK_SHIFT_CONST(9)
#define PMC_IMPL_IO_AO_HV_DPD_REQ_0_CAN1_EN_FIELD                       MK_FIELD_CONST(0x1, PMC_IMPL_IO_AO_HV_DPD_REQ_0_CAN1_EN_SHIFT)
#define PMC_IMPL_IO_AO_HV_DPD_REQ_0_CAN1_EN_RANGE                       9:9
#define PMC_IMPL_IO_AO_HV_DPD_REQ_0_CAN1_EN_MSB                 MK_SHIFT_CONST(9)
#define PMC_IMPL_IO_AO_HV_DPD_REQ_0_CAN1_EN_LSB                 MK_SHIFT_CONST(9)
#define PMC_IMPL_IO_AO_HV_DPD_REQ_0_CAN1_EN_WOFFSET                     0x0
#define PMC_IMPL_IO_AO_HV_DPD_REQ_0_CAN1_EN_DEFAULT                     MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_AO_HV_DPD_REQ_0_CAN1_EN_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_AO_HV_DPD_REQ_0_CAN1_EN_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_AO_HV_DPD_REQ_0_CAN1_EN_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_AO_HV_DPD_REQ_0_CAN1_EN_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_AO_HV_DPD_REQ_0_CAN1_EN_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_AO_HV_DPD_REQ_0_CAN1_EN_OFF                 MK_ENUM_CONST(0)
#define PMC_IMPL_IO_AO_HV_DPD_REQ_0_CAN1_EN_ON                  MK_ENUM_CONST(1)

// puts SOC_GPIO50 PAD(s) in/out of Depp Power Down (DPD) mode
#define PMC_IMPL_IO_AO_HV_DPD_REQ_0_SOC_GPIO50_SHIFT                    MK_SHIFT_CONST(10)
#define PMC_IMPL_IO_AO_HV_DPD_REQ_0_SOC_GPIO50_FIELD                    MK_FIELD_CONST(0x1, PMC_IMPL_IO_AO_HV_DPD_REQ_0_SOC_GPIO50_SHIFT)
#define PMC_IMPL_IO_AO_HV_DPD_REQ_0_SOC_GPIO50_RANGE                    10:10
#define PMC_IMPL_IO_AO_HV_DPD_REQ_0_SOC_GPIO50_MSB                      MK_SHIFT_CONST(10)
#define PMC_IMPL_IO_AO_HV_DPD_REQ_0_SOC_GPIO50_LSB                      MK_SHIFT_CONST(10)
#define PMC_IMPL_IO_AO_HV_DPD_REQ_0_SOC_GPIO50_WOFFSET                  0x0
#define PMC_IMPL_IO_AO_HV_DPD_REQ_0_SOC_GPIO50_DEFAULT                  MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_AO_HV_DPD_REQ_0_SOC_GPIO50_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_AO_HV_DPD_REQ_0_SOC_GPIO50_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_AO_HV_DPD_REQ_0_SOC_GPIO50_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_AO_HV_DPD_REQ_0_SOC_GPIO50_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_AO_HV_DPD_REQ_0_SOC_GPIO50_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_AO_HV_DPD_REQ_0_SOC_GPIO50_OFF                      MK_ENUM_CONST(0)
#define PMC_IMPL_IO_AO_HV_DPD_REQ_0_SOC_GPIO50_ON                       MK_ENUM_CONST(1)

// puts CAN1_ERR PAD(s) in/out of Depp Power Down (DPD) mode
#define PMC_IMPL_IO_AO_HV_DPD_REQ_0_CAN1_ERR_SHIFT                      MK_SHIFT_CONST(11)
#define PMC_IMPL_IO_AO_HV_DPD_REQ_0_CAN1_ERR_FIELD                      MK_FIELD_CONST(0x1, PMC_IMPL_IO_AO_HV_DPD_REQ_0_CAN1_ERR_SHIFT)
#define PMC_IMPL_IO_AO_HV_DPD_REQ_0_CAN1_ERR_RANGE                      11:11
#define PMC_IMPL_IO_AO_HV_DPD_REQ_0_CAN1_ERR_MSB                        MK_SHIFT_CONST(11)
#define PMC_IMPL_IO_AO_HV_DPD_REQ_0_CAN1_ERR_LSB                        MK_SHIFT_CONST(11)
#define PMC_IMPL_IO_AO_HV_DPD_REQ_0_CAN1_ERR_WOFFSET                    0x0
#define PMC_IMPL_IO_AO_HV_DPD_REQ_0_CAN1_ERR_DEFAULT                    MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_AO_HV_DPD_REQ_0_CAN1_ERR_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_AO_HV_DPD_REQ_0_CAN1_ERR_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_AO_HV_DPD_REQ_0_CAN1_ERR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_AO_HV_DPD_REQ_0_CAN1_ERR_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_AO_HV_DPD_REQ_0_CAN1_ERR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_AO_HV_DPD_REQ_0_CAN1_ERR_OFF                        MK_ENUM_CONST(0)
#define PMC_IMPL_IO_AO_HV_DPD_REQ_0_CAN1_ERR_ON                 MK_ENUM_CONST(1)


// Register PMC_IMPL_IO_AO_HV_DPD_STATUS_0
#define PMC_IMPL_IO_AO_HV_DPD_STATUS_0                  MK_ADDR_CONST(0xe088)
#define PMC_IMPL_IO_AO_HV_DPD_STATUS_0_SECURE                   0x0
#define PMC_IMPL_IO_AO_HV_DPD_STATUS_0_DUAL                     0x0
#define PMC_IMPL_IO_AO_HV_DPD_STATUS_0_SCR                      IO_AO_HV_SCR_0
#define PMC_IMPL_IO_AO_HV_DPD_STATUS_0_SCRREG                   PMC_IMPL_SCR_IO_AO_HV_SCR_0
#define PMC_IMPL_IO_AO_HV_DPD_STATUS_0_WORD_COUNT                       0x1
#define PMC_IMPL_IO_AO_HV_DPD_STATUS_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_AO_HV_DPD_STATUS_0_RESET_MASK                       MK_MASK_CONST(0xfff)
#define PMC_IMPL_IO_AO_HV_DPD_STATUS_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_AO_HV_DPD_STATUS_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_AO_HV_DPD_STATUS_0_READ_MASK                        MK_MASK_CONST(0xfff)
#define PMC_IMPL_IO_AO_HV_DPD_STATUS_0_WRITE_MASK                       MK_MASK_CONST(0x0)
// On - CAN0_DOUT PAD(s) is in Deep Power Down mode, Off - CAN0_DOUT PAD(s) is out of Deep Power Down mode
#define PMC_IMPL_IO_AO_HV_DPD_STATUS_0_CAN0_DOUT_SHIFT                  MK_SHIFT_CONST(0)
#define PMC_IMPL_IO_AO_HV_DPD_STATUS_0_CAN0_DOUT_FIELD                  MK_FIELD_CONST(0x1, PMC_IMPL_IO_AO_HV_DPD_STATUS_0_CAN0_DOUT_SHIFT)
#define PMC_IMPL_IO_AO_HV_DPD_STATUS_0_CAN0_DOUT_RANGE                  0:0
#define PMC_IMPL_IO_AO_HV_DPD_STATUS_0_CAN0_DOUT_MSB                    MK_SHIFT_CONST(0)
#define PMC_IMPL_IO_AO_HV_DPD_STATUS_0_CAN0_DOUT_LSB                    MK_SHIFT_CONST(0)
#define PMC_IMPL_IO_AO_HV_DPD_STATUS_0_CAN0_DOUT_WOFFSET                        0x0
#define PMC_IMPL_IO_AO_HV_DPD_STATUS_0_CAN0_DOUT_DEFAULT                        MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_AO_HV_DPD_STATUS_0_CAN0_DOUT_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_AO_HV_DPD_STATUS_0_CAN0_DOUT_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_AO_HV_DPD_STATUS_0_CAN0_DOUT_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_AO_HV_DPD_STATUS_0_CAN0_DOUT_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_AO_HV_DPD_STATUS_0_CAN0_DOUT_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_AO_HV_DPD_STATUS_0_CAN0_DOUT_OFF                    MK_ENUM_CONST(0)
#define PMC_IMPL_IO_AO_HV_DPD_STATUS_0_CAN0_DOUT_ON                     MK_ENUM_CONST(1)

// On - CAN0_DIN PAD(s) is in Deep Power Down mode, Off - CAN0_DIN PAD(s) is out of Deep Power Down mode
#define PMC_IMPL_IO_AO_HV_DPD_STATUS_0_CAN0_DIN_SHIFT                   MK_SHIFT_CONST(1)
#define PMC_IMPL_IO_AO_HV_DPD_STATUS_0_CAN0_DIN_FIELD                   MK_FIELD_CONST(0x1, PMC_IMPL_IO_AO_HV_DPD_STATUS_0_CAN0_DIN_SHIFT)
#define PMC_IMPL_IO_AO_HV_DPD_STATUS_0_CAN0_DIN_RANGE                   1:1
#define PMC_IMPL_IO_AO_HV_DPD_STATUS_0_CAN0_DIN_MSB                     MK_SHIFT_CONST(1)
#define PMC_IMPL_IO_AO_HV_DPD_STATUS_0_CAN0_DIN_LSB                     MK_SHIFT_CONST(1)
#define PMC_IMPL_IO_AO_HV_DPD_STATUS_0_CAN0_DIN_WOFFSET                 0x0
#define PMC_IMPL_IO_AO_HV_DPD_STATUS_0_CAN0_DIN_DEFAULT                 MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_AO_HV_DPD_STATUS_0_CAN0_DIN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_AO_HV_DPD_STATUS_0_CAN0_DIN_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_AO_HV_DPD_STATUS_0_CAN0_DIN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_AO_HV_DPD_STATUS_0_CAN0_DIN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_AO_HV_DPD_STATUS_0_CAN0_DIN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_AO_HV_DPD_STATUS_0_CAN0_DIN_OFF                     MK_ENUM_CONST(0)
#define PMC_IMPL_IO_AO_HV_DPD_STATUS_0_CAN0_DIN_ON                      MK_ENUM_CONST(1)

// On - CAN1_DOUT PAD(s) is in Deep Power Down mode, Off - CAN1_DOUT PAD(s) is out of Deep Power Down mode
#define PMC_IMPL_IO_AO_HV_DPD_STATUS_0_CAN1_DOUT_SHIFT                  MK_SHIFT_CONST(2)
#define PMC_IMPL_IO_AO_HV_DPD_STATUS_0_CAN1_DOUT_FIELD                  MK_FIELD_CONST(0x1, PMC_IMPL_IO_AO_HV_DPD_STATUS_0_CAN1_DOUT_SHIFT)
#define PMC_IMPL_IO_AO_HV_DPD_STATUS_0_CAN1_DOUT_RANGE                  2:2
#define PMC_IMPL_IO_AO_HV_DPD_STATUS_0_CAN1_DOUT_MSB                    MK_SHIFT_CONST(2)
#define PMC_IMPL_IO_AO_HV_DPD_STATUS_0_CAN1_DOUT_LSB                    MK_SHIFT_CONST(2)
#define PMC_IMPL_IO_AO_HV_DPD_STATUS_0_CAN1_DOUT_WOFFSET                        0x0
#define PMC_IMPL_IO_AO_HV_DPD_STATUS_0_CAN1_DOUT_DEFAULT                        MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_AO_HV_DPD_STATUS_0_CAN1_DOUT_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_AO_HV_DPD_STATUS_0_CAN1_DOUT_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_AO_HV_DPD_STATUS_0_CAN1_DOUT_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_AO_HV_DPD_STATUS_0_CAN1_DOUT_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_AO_HV_DPD_STATUS_0_CAN1_DOUT_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_AO_HV_DPD_STATUS_0_CAN1_DOUT_OFF                    MK_ENUM_CONST(0)
#define PMC_IMPL_IO_AO_HV_DPD_STATUS_0_CAN1_DOUT_ON                     MK_ENUM_CONST(1)

// On - CAN1_DIN PAD(s) is in Deep Power Down mode, Off - CAN1_DIN PAD(s) is out of Deep Power Down mode
#define PMC_IMPL_IO_AO_HV_DPD_STATUS_0_CAN1_DIN_SHIFT                   MK_SHIFT_CONST(3)
#define PMC_IMPL_IO_AO_HV_DPD_STATUS_0_CAN1_DIN_FIELD                   MK_FIELD_CONST(0x1, PMC_IMPL_IO_AO_HV_DPD_STATUS_0_CAN1_DIN_SHIFT)
#define PMC_IMPL_IO_AO_HV_DPD_STATUS_0_CAN1_DIN_RANGE                   3:3
#define PMC_IMPL_IO_AO_HV_DPD_STATUS_0_CAN1_DIN_MSB                     MK_SHIFT_CONST(3)
#define PMC_IMPL_IO_AO_HV_DPD_STATUS_0_CAN1_DIN_LSB                     MK_SHIFT_CONST(3)
#define PMC_IMPL_IO_AO_HV_DPD_STATUS_0_CAN1_DIN_WOFFSET                 0x0
#define PMC_IMPL_IO_AO_HV_DPD_STATUS_0_CAN1_DIN_DEFAULT                 MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_AO_HV_DPD_STATUS_0_CAN1_DIN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_AO_HV_DPD_STATUS_0_CAN1_DIN_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_AO_HV_DPD_STATUS_0_CAN1_DIN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_AO_HV_DPD_STATUS_0_CAN1_DIN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_AO_HV_DPD_STATUS_0_CAN1_DIN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_AO_HV_DPD_STATUS_0_CAN1_DIN_OFF                     MK_ENUM_CONST(0)
#define PMC_IMPL_IO_AO_HV_DPD_STATUS_0_CAN1_DIN_ON                      MK_ENUM_CONST(1)

// On - CAN0_STB PAD(s) is in Deep Power Down mode, Off - CAN0_STB PAD(s) is out of Deep Power Down mode
#define PMC_IMPL_IO_AO_HV_DPD_STATUS_0_CAN0_STB_SHIFT                   MK_SHIFT_CONST(4)
#define PMC_IMPL_IO_AO_HV_DPD_STATUS_0_CAN0_STB_FIELD                   MK_FIELD_CONST(0x1, PMC_IMPL_IO_AO_HV_DPD_STATUS_0_CAN0_STB_SHIFT)
#define PMC_IMPL_IO_AO_HV_DPD_STATUS_0_CAN0_STB_RANGE                   4:4
#define PMC_IMPL_IO_AO_HV_DPD_STATUS_0_CAN0_STB_MSB                     MK_SHIFT_CONST(4)
#define PMC_IMPL_IO_AO_HV_DPD_STATUS_0_CAN0_STB_LSB                     MK_SHIFT_CONST(4)
#define PMC_IMPL_IO_AO_HV_DPD_STATUS_0_CAN0_STB_WOFFSET                 0x0
#define PMC_IMPL_IO_AO_HV_DPD_STATUS_0_CAN0_STB_DEFAULT                 MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_AO_HV_DPD_STATUS_0_CAN0_STB_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_AO_HV_DPD_STATUS_0_CAN0_STB_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_AO_HV_DPD_STATUS_0_CAN0_STB_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_AO_HV_DPD_STATUS_0_CAN0_STB_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_AO_HV_DPD_STATUS_0_CAN0_STB_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_AO_HV_DPD_STATUS_0_CAN0_STB_OFF                     MK_ENUM_CONST(0)
#define PMC_IMPL_IO_AO_HV_DPD_STATUS_0_CAN0_STB_ON                      MK_ENUM_CONST(1)

// On - CAN0_EN PAD(s) is in Deep Power Down mode, Off - CAN0_EN PAD(s) is out of Deep Power Down mode
#define PMC_IMPL_IO_AO_HV_DPD_STATUS_0_CAN0_EN_SHIFT                    MK_SHIFT_CONST(5)
#define PMC_IMPL_IO_AO_HV_DPD_STATUS_0_CAN0_EN_FIELD                    MK_FIELD_CONST(0x1, PMC_IMPL_IO_AO_HV_DPD_STATUS_0_CAN0_EN_SHIFT)
#define PMC_IMPL_IO_AO_HV_DPD_STATUS_0_CAN0_EN_RANGE                    5:5
#define PMC_IMPL_IO_AO_HV_DPD_STATUS_0_CAN0_EN_MSB                      MK_SHIFT_CONST(5)
#define PMC_IMPL_IO_AO_HV_DPD_STATUS_0_CAN0_EN_LSB                      MK_SHIFT_CONST(5)
#define PMC_IMPL_IO_AO_HV_DPD_STATUS_0_CAN0_EN_WOFFSET                  0x0
#define PMC_IMPL_IO_AO_HV_DPD_STATUS_0_CAN0_EN_DEFAULT                  MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_AO_HV_DPD_STATUS_0_CAN0_EN_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_AO_HV_DPD_STATUS_0_CAN0_EN_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_AO_HV_DPD_STATUS_0_CAN0_EN_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_AO_HV_DPD_STATUS_0_CAN0_EN_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_AO_HV_DPD_STATUS_0_CAN0_EN_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_AO_HV_DPD_STATUS_0_CAN0_EN_OFF                      MK_ENUM_CONST(0)
#define PMC_IMPL_IO_AO_HV_DPD_STATUS_0_CAN0_EN_ON                       MK_ENUM_CONST(1)

// On - SOC_GPIO49 PAD(s) is in Deep Power Down mode, Off - SOC_GPIO49 PAD(s) is out of Deep Power Down mode
#define PMC_IMPL_IO_AO_HV_DPD_STATUS_0_SOC_GPIO49_SHIFT                 MK_SHIFT_CONST(6)
#define PMC_IMPL_IO_AO_HV_DPD_STATUS_0_SOC_GPIO49_FIELD                 MK_FIELD_CONST(0x1, PMC_IMPL_IO_AO_HV_DPD_STATUS_0_SOC_GPIO49_SHIFT)
#define PMC_IMPL_IO_AO_HV_DPD_STATUS_0_SOC_GPIO49_RANGE                 6:6
#define PMC_IMPL_IO_AO_HV_DPD_STATUS_0_SOC_GPIO49_MSB                   MK_SHIFT_CONST(6)
#define PMC_IMPL_IO_AO_HV_DPD_STATUS_0_SOC_GPIO49_LSB                   MK_SHIFT_CONST(6)
#define PMC_IMPL_IO_AO_HV_DPD_STATUS_0_SOC_GPIO49_WOFFSET                       0x0
#define PMC_IMPL_IO_AO_HV_DPD_STATUS_0_SOC_GPIO49_DEFAULT                       MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_AO_HV_DPD_STATUS_0_SOC_GPIO49_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_AO_HV_DPD_STATUS_0_SOC_GPIO49_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_AO_HV_DPD_STATUS_0_SOC_GPIO49_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_AO_HV_DPD_STATUS_0_SOC_GPIO49_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_AO_HV_DPD_STATUS_0_SOC_GPIO49_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_AO_HV_DPD_STATUS_0_SOC_GPIO49_OFF                   MK_ENUM_CONST(0)
#define PMC_IMPL_IO_AO_HV_DPD_STATUS_0_SOC_GPIO49_ON                    MK_ENUM_CONST(1)

// On - CAN0_ERR PAD(s) is in Deep Power Down mode, Off - CAN0_ERR PAD(s) is out of Deep Power Down mode
#define PMC_IMPL_IO_AO_HV_DPD_STATUS_0_CAN0_ERR_SHIFT                   MK_SHIFT_CONST(7)
#define PMC_IMPL_IO_AO_HV_DPD_STATUS_0_CAN0_ERR_FIELD                   MK_FIELD_CONST(0x1, PMC_IMPL_IO_AO_HV_DPD_STATUS_0_CAN0_ERR_SHIFT)
#define PMC_IMPL_IO_AO_HV_DPD_STATUS_0_CAN0_ERR_RANGE                   7:7
#define PMC_IMPL_IO_AO_HV_DPD_STATUS_0_CAN0_ERR_MSB                     MK_SHIFT_CONST(7)
#define PMC_IMPL_IO_AO_HV_DPD_STATUS_0_CAN0_ERR_LSB                     MK_SHIFT_CONST(7)
#define PMC_IMPL_IO_AO_HV_DPD_STATUS_0_CAN0_ERR_WOFFSET                 0x0
#define PMC_IMPL_IO_AO_HV_DPD_STATUS_0_CAN0_ERR_DEFAULT                 MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_AO_HV_DPD_STATUS_0_CAN0_ERR_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_AO_HV_DPD_STATUS_0_CAN0_ERR_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_AO_HV_DPD_STATUS_0_CAN0_ERR_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_AO_HV_DPD_STATUS_0_CAN0_ERR_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_AO_HV_DPD_STATUS_0_CAN0_ERR_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_AO_HV_DPD_STATUS_0_CAN0_ERR_OFF                     MK_ENUM_CONST(0)
#define PMC_IMPL_IO_AO_HV_DPD_STATUS_0_CAN0_ERR_ON                      MK_ENUM_CONST(1)

// On - CAN1_STB PAD(s) is in Deep Power Down mode, Off - CAN1_STB PAD(s) is out of Deep Power Down mode
#define PMC_IMPL_IO_AO_HV_DPD_STATUS_0_CAN1_STB_SHIFT                   MK_SHIFT_CONST(8)
#define PMC_IMPL_IO_AO_HV_DPD_STATUS_0_CAN1_STB_FIELD                   MK_FIELD_CONST(0x1, PMC_IMPL_IO_AO_HV_DPD_STATUS_0_CAN1_STB_SHIFT)
#define PMC_IMPL_IO_AO_HV_DPD_STATUS_0_CAN1_STB_RANGE                   8:8
#define PMC_IMPL_IO_AO_HV_DPD_STATUS_0_CAN1_STB_MSB                     MK_SHIFT_CONST(8)
#define PMC_IMPL_IO_AO_HV_DPD_STATUS_0_CAN1_STB_LSB                     MK_SHIFT_CONST(8)
#define PMC_IMPL_IO_AO_HV_DPD_STATUS_0_CAN1_STB_WOFFSET                 0x0
#define PMC_IMPL_IO_AO_HV_DPD_STATUS_0_CAN1_STB_DEFAULT                 MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_AO_HV_DPD_STATUS_0_CAN1_STB_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_AO_HV_DPD_STATUS_0_CAN1_STB_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_AO_HV_DPD_STATUS_0_CAN1_STB_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_AO_HV_DPD_STATUS_0_CAN1_STB_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_AO_HV_DPD_STATUS_0_CAN1_STB_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_AO_HV_DPD_STATUS_0_CAN1_STB_OFF                     MK_ENUM_CONST(0)
#define PMC_IMPL_IO_AO_HV_DPD_STATUS_0_CAN1_STB_ON                      MK_ENUM_CONST(1)

// On - CAN1_EN PAD(s) is in Deep Power Down mode, Off - CAN1_EN PAD(s) is out of Deep Power Down mode
#define PMC_IMPL_IO_AO_HV_DPD_STATUS_0_CAN1_EN_SHIFT                    MK_SHIFT_CONST(9)
#define PMC_IMPL_IO_AO_HV_DPD_STATUS_0_CAN1_EN_FIELD                    MK_FIELD_CONST(0x1, PMC_IMPL_IO_AO_HV_DPD_STATUS_0_CAN1_EN_SHIFT)
#define PMC_IMPL_IO_AO_HV_DPD_STATUS_0_CAN1_EN_RANGE                    9:9
#define PMC_IMPL_IO_AO_HV_DPD_STATUS_0_CAN1_EN_MSB                      MK_SHIFT_CONST(9)
#define PMC_IMPL_IO_AO_HV_DPD_STATUS_0_CAN1_EN_LSB                      MK_SHIFT_CONST(9)
#define PMC_IMPL_IO_AO_HV_DPD_STATUS_0_CAN1_EN_WOFFSET                  0x0
#define PMC_IMPL_IO_AO_HV_DPD_STATUS_0_CAN1_EN_DEFAULT                  MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_AO_HV_DPD_STATUS_0_CAN1_EN_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_AO_HV_DPD_STATUS_0_CAN1_EN_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_AO_HV_DPD_STATUS_0_CAN1_EN_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_AO_HV_DPD_STATUS_0_CAN1_EN_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_AO_HV_DPD_STATUS_0_CAN1_EN_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_AO_HV_DPD_STATUS_0_CAN1_EN_OFF                      MK_ENUM_CONST(0)
#define PMC_IMPL_IO_AO_HV_DPD_STATUS_0_CAN1_EN_ON                       MK_ENUM_CONST(1)

// On - SOC_GPIO50 PAD(s) is in Deep Power Down mode, Off - SOC_GPIO50 PAD(s) is out of Deep Power Down mode
#define PMC_IMPL_IO_AO_HV_DPD_STATUS_0_SOC_GPIO50_SHIFT                 MK_SHIFT_CONST(10)
#define PMC_IMPL_IO_AO_HV_DPD_STATUS_0_SOC_GPIO50_FIELD                 MK_FIELD_CONST(0x1, PMC_IMPL_IO_AO_HV_DPD_STATUS_0_SOC_GPIO50_SHIFT)
#define PMC_IMPL_IO_AO_HV_DPD_STATUS_0_SOC_GPIO50_RANGE                 10:10
#define PMC_IMPL_IO_AO_HV_DPD_STATUS_0_SOC_GPIO50_MSB                   MK_SHIFT_CONST(10)
#define PMC_IMPL_IO_AO_HV_DPD_STATUS_0_SOC_GPIO50_LSB                   MK_SHIFT_CONST(10)
#define PMC_IMPL_IO_AO_HV_DPD_STATUS_0_SOC_GPIO50_WOFFSET                       0x0
#define PMC_IMPL_IO_AO_HV_DPD_STATUS_0_SOC_GPIO50_DEFAULT                       MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_AO_HV_DPD_STATUS_0_SOC_GPIO50_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_AO_HV_DPD_STATUS_0_SOC_GPIO50_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_AO_HV_DPD_STATUS_0_SOC_GPIO50_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_AO_HV_DPD_STATUS_0_SOC_GPIO50_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_AO_HV_DPD_STATUS_0_SOC_GPIO50_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_AO_HV_DPD_STATUS_0_SOC_GPIO50_OFF                   MK_ENUM_CONST(0)
#define PMC_IMPL_IO_AO_HV_DPD_STATUS_0_SOC_GPIO50_ON                    MK_ENUM_CONST(1)

// On - CAN1_ERR PAD(s) is in Deep Power Down mode, Off - CAN1_ERR PAD(s) is out of Deep Power Down mode
#define PMC_IMPL_IO_AO_HV_DPD_STATUS_0_CAN1_ERR_SHIFT                   MK_SHIFT_CONST(11)
#define PMC_IMPL_IO_AO_HV_DPD_STATUS_0_CAN1_ERR_FIELD                   MK_FIELD_CONST(0x1, PMC_IMPL_IO_AO_HV_DPD_STATUS_0_CAN1_ERR_SHIFT)
#define PMC_IMPL_IO_AO_HV_DPD_STATUS_0_CAN1_ERR_RANGE                   11:11
#define PMC_IMPL_IO_AO_HV_DPD_STATUS_0_CAN1_ERR_MSB                     MK_SHIFT_CONST(11)
#define PMC_IMPL_IO_AO_HV_DPD_STATUS_0_CAN1_ERR_LSB                     MK_SHIFT_CONST(11)
#define PMC_IMPL_IO_AO_HV_DPD_STATUS_0_CAN1_ERR_WOFFSET                 0x0
#define PMC_IMPL_IO_AO_HV_DPD_STATUS_0_CAN1_ERR_DEFAULT                 MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_AO_HV_DPD_STATUS_0_CAN1_ERR_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_AO_HV_DPD_STATUS_0_CAN1_ERR_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_AO_HV_DPD_STATUS_0_CAN1_ERR_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_AO_HV_DPD_STATUS_0_CAN1_ERR_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_AO_HV_DPD_STATUS_0_CAN1_ERR_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_AO_HV_DPD_STATUS_0_CAN1_ERR_OFF                     MK_ENUM_CONST(0)
#define PMC_IMPL_IO_AO_HV_DPD_STATUS_0_CAN1_ERR_ON                      MK_ENUM_CONST(1)


// Register PMC_IMPL_IO_AO_HV_DPD_OFF_MASK_0
#define PMC_IMPL_IO_AO_HV_DPD_OFF_MASK_0                        MK_ADDR_CONST(0xe08c)
#define PMC_IMPL_IO_AO_HV_DPD_OFF_MASK_0_SECURE                         0x0
#define PMC_IMPL_IO_AO_HV_DPD_OFF_MASK_0_DUAL                   0x0
#define PMC_IMPL_IO_AO_HV_DPD_OFF_MASK_0_SCR                    IO_AO_HV_SCR_0
#define PMC_IMPL_IO_AO_HV_DPD_OFF_MASK_0_SCRREG                         PMC_IMPL_SCR_IO_AO_HV_SCR_0
#define PMC_IMPL_IO_AO_HV_DPD_OFF_MASK_0_WORD_COUNT                     0x1
#define PMC_IMPL_IO_AO_HV_DPD_OFF_MASK_0_RESET_VAL                      MK_MASK_CONST(0xfff)
#define PMC_IMPL_IO_AO_HV_DPD_OFF_MASK_0_RESET_MASK                     MK_MASK_CONST(0xfff)
#define PMC_IMPL_IO_AO_HV_DPD_OFF_MASK_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_AO_HV_DPD_OFF_MASK_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_AO_HV_DPD_OFF_MASK_0_READ_MASK                      MK_MASK_CONST(0xfff)
#define PMC_IMPL_IO_AO_HV_DPD_OFF_MASK_0_WRITE_MASK                     MK_MASK_CONST(0xfff)
// On - CAN0_DOUT PAD(s) are masked to enter Deep Power Down mode from SC7 controller, Off - CAN0_DOUT PAD(s) are free to enter Deep Power Down mode
#define PMC_IMPL_IO_AO_HV_DPD_OFF_MASK_0_CAN0_DOUT_SHIFT                        MK_SHIFT_CONST(0)
#define PMC_IMPL_IO_AO_HV_DPD_OFF_MASK_0_CAN0_DOUT_FIELD                        MK_FIELD_CONST(0x1, PMC_IMPL_IO_AO_HV_DPD_OFF_MASK_0_CAN0_DOUT_SHIFT)
#define PMC_IMPL_IO_AO_HV_DPD_OFF_MASK_0_CAN0_DOUT_RANGE                        0:0
#define PMC_IMPL_IO_AO_HV_DPD_OFF_MASK_0_CAN0_DOUT_MSB                  MK_SHIFT_CONST(0)
#define PMC_IMPL_IO_AO_HV_DPD_OFF_MASK_0_CAN0_DOUT_LSB                  MK_SHIFT_CONST(0)
#define PMC_IMPL_IO_AO_HV_DPD_OFF_MASK_0_CAN0_DOUT_WOFFSET                      0x0
#define PMC_IMPL_IO_AO_HV_DPD_OFF_MASK_0_CAN0_DOUT_DEFAULT                      MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_AO_HV_DPD_OFF_MASK_0_CAN0_DOUT_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_AO_HV_DPD_OFF_MASK_0_CAN0_DOUT_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_AO_HV_DPD_OFF_MASK_0_CAN0_DOUT_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_AO_HV_DPD_OFF_MASK_0_CAN0_DOUT_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_AO_HV_DPD_OFF_MASK_0_CAN0_DOUT_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_AO_HV_DPD_OFF_MASK_0_CAN0_DOUT_OFF                  MK_ENUM_CONST(0)
#define PMC_IMPL_IO_AO_HV_DPD_OFF_MASK_0_CAN0_DOUT_ON                   MK_ENUM_CONST(1)

// On - CAN0_DIN PAD(s) are masked to enter Deep Power Down mode from SC7 controller, Off - CAN0_DIN PAD(s) are free to enter Deep Power Down mode
#define PMC_IMPL_IO_AO_HV_DPD_OFF_MASK_0_CAN0_DIN_SHIFT                 MK_SHIFT_CONST(1)
#define PMC_IMPL_IO_AO_HV_DPD_OFF_MASK_0_CAN0_DIN_FIELD                 MK_FIELD_CONST(0x1, PMC_IMPL_IO_AO_HV_DPD_OFF_MASK_0_CAN0_DIN_SHIFT)
#define PMC_IMPL_IO_AO_HV_DPD_OFF_MASK_0_CAN0_DIN_RANGE                 1:1
#define PMC_IMPL_IO_AO_HV_DPD_OFF_MASK_0_CAN0_DIN_MSB                   MK_SHIFT_CONST(1)
#define PMC_IMPL_IO_AO_HV_DPD_OFF_MASK_0_CAN0_DIN_LSB                   MK_SHIFT_CONST(1)
#define PMC_IMPL_IO_AO_HV_DPD_OFF_MASK_0_CAN0_DIN_WOFFSET                       0x0
#define PMC_IMPL_IO_AO_HV_DPD_OFF_MASK_0_CAN0_DIN_DEFAULT                       MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_AO_HV_DPD_OFF_MASK_0_CAN0_DIN_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_AO_HV_DPD_OFF_MASK_0_CAN0_DIN_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_AO_HV_DPD_OFF_MASK_0_CAN0_DIN_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_AO_HV_DPD_OFF_MASK_0_CAN0_DIN_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_AO_HV_DPD_OFF_MASK_0_CAN0_DIN_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_AO_HV_DPD_OFF_MASK_0_CAN0_DIN_OFF                   MK_ENUM_CONST(0)
#define PMC_IMPL_IO_AO_HV_DPD_OFF_MASK_0_CAN0_DIN_ON                    MK_ENUM_CONST(1)

// On - CAN1_DOUT PAD(s) are masked to enter Deep Power Down mode from SC7 controller, Off - CAN1_DOUT PAD(s) are free to enter Deep Power Down mode
#define PMC_IMPL_IO_AO_HV_DPD_OFF_MASK_0_CAN1_DOUT_SHIFT                        MK_SHIFT_CONST(2)
#define PMC_IMPL_IO_AO_HV_DPD_OFF_MASK_0_CAN1_DOUT_FIELD                        MK_FIELD_CONST(0x1, PMC_IMPL_IO_AO_HV_DPD_OFF_MASK_0_CAN1_DOUT_SHIFT)
#define PMC_IMPL_IO_AO_HV_DPD_OFF_MASK_0_CAN1_DOUT_RANGE                        2:2
#define PMC_IMPL_IO_AO_HV_DPD_OFF_MASK_0_CAN1_DOUT_MSB                  MK_SHIFT_CONST(2)
#define PMC_IMPL_IO_AO_HV_DPD_OFF_MASK_0_CAN1_DOUT_LSB                  MK_SHIFT_CONST(2)
#define PMC_IMPL_IO_AO_HV_DPD_OFF_MASK_0_CAN1_DOUT_WOFFSET                      0x0
#define PMC_IMPL_IO_AO_HV_DPD_OFF_MASK_0_CAN1_DOUT_DEFAULT                      MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_AO_HV_DPD_OFF_MASK_0_CAN1_DOUT_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_AO_HV_DPD_OFF_MASK_0_CAN1_DOUT_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_AO_HV_DPD_OFF_MASK_0_CAN1_DOUT_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_AO_HV_DPD_OFF_MASK_0_CAN1_DOUT_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_AO_HV_DPD_OFF_MASK_0_CAN1_DOUT_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_AO_HV_DPD_OFF_MASK_0_CAN1_DOUT_OFF                  MK_ENUM_CONST(0)
#define PMC_IMPL_IO_AO_HV_DPD_OFF_MASK_0_CAN1_DOUT_ON                   MK_ENUM_CONST(1)

// On - CAN1_DIN PAD(s) are masked to enter Deep Power Down mode from SC7 controller, Off - CAN1_DIN PAD(s) are free to enter Deep Power Down mode
#define PMC_IMPL_IO_AO_HV_DPD_OFF_MASK_0_CAN1_DIN_SHIFT                 MK_SHIFT_CONST(3)
#define PMC_IMPL_IO_AO_HV_DPD_OFF_MASK_0_CAN1_DIN_FIELD                 MK_FIELD_CONST(0x1, PMC_IMPL_IO_AO_HV_DPD_OFF_MASK_0_CAN1_DIN_SHIFT)
#define PMC_IMPL_IO_AO_HV_DPD_OFF_MASK_0_CAN1_DIN_RANGE                 3:3
#define PMC_IMPL_IO_AO_HV_DPD_OFF_MASK_0_CAN1_DIN_MSB                   MK_SHIFT_CONST(3)
#define PMC_IMPL_IO_AO_HV_DPD_OFF_MASK_0_CAN1_DIN_LSB                   MK_SHIFT_CONST(3)
#define PMC_IMPL_IO_AO_HV_DPD_OFF_MASK_0_CAN1_DIN_WOFFSET                       0x0
#define PMC_IMPL_IO_AO_HV_DPD_OFF_MASK_0_CAN1_DIN_DEFAULT                       MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_AO_HV_DPD_OFF_MASK_0_CAN1_DIN_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_AO_HV_DPD_OFF_MASK_0_CAN1_DIN_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_AO_HV_DPD_OFF_MASK_0_CAN1_DIN_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_AO_HV_DPD_OFF_MASK_0_CAN1_DIN_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_AO_HV_DPD_OFF_MASK_0_CAN1_DIN_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_AO_HV_DPD_OFF_MASK_0_CAN1_DIN_OFF                   MK_ENUM_CONST(0)
#define PMC_IMPL_IO_AO_HV_DPD_OFF_MASK_0_CAN1_DIN_ON                    MK_ENUM_CONST(1)

// On - CAN0_STB PAD(s) are masked to enter Deep Power Down mode from SC7 controller, Off - CAN0_STB PAD(s) are free to enter Deep Power Down mode
#define PMC_IMPL_IO_AO_HV_DPD_OFF_MASK_0_CAN0_STB_SHIFT                 MK_SHIFT_CONST(4)
#define PMC_IMPL_IO_AO_HV_DPD_OFF_MASK_0_CAN0_STB_FIELD                 MK_FIELD_CONST(0x1, PMC_IMPL_IO_AO_HV_DPD_OFF_MASK_0_CAN0_STB_SHIFT)
#define PMC_IMPL_IO_AO_HV_DPD_OFF_MASK_0_CAN0_STB_RANGE                 4:4
#define PMC_IMPL_IO_AO_HV_DPD_OFF_MASK_0_CAN0_STB_MSB                   MK_SHIFT_CONST(4)
#define PMC_IMPL_IO_AO_HV_DPD_OFF_MASK_0_CAN0_STB_LSB                   MK_SHIFT_CONST(4)
#define PMC_IMPL_IO_AO_HV_DPD_OFF_MASK_0_CAN0_STB_WOFFSET                       0x0
#define PMC_IMPL_IO_AO_HV_DPD_OFF_MASK_0_CAN0_STB_DEFAULT                       MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_AO_HV_DPD_OFF_MASK_0_CAN0_STB_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_AO_HV_DPD_OFF_MASK_0_CAN0_STB_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_AO_HV_DPD_OFF_MASK_0_CAN0_STB_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_AO_HV_DPD_OFF_MASK_0_CAN0_STB_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_AO_HV_DPD_OFF_MASK_0_CAN0_STB_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_AO_HV_DPD_OFF_MASK_0_CAN0_STB_OFF                   MK_ENUM_CONST(0)
#define PMC_IMPL_IO_AO_HV_DPD_OFF_MASK_0_CAN0_STB_ON                    MK_ENUM_CONST(1)

// On - CAN0_EN PAD(s) are masked to enter Deep Power Down mode from SC7 controller, Off - CAN0_EN PAD(s) are free to enter Deep Power Down mode
#define PMC_IMPL_IO_AO_HV_DPD_OFF_MASK_0_CAN0_EN_SHIFT                  MK_SHIFT_CONST(5)
#define PMC_IMPL_IO_AO_HV_DPD_OFF_MASK_0_CAN0_EN_FIELD                  MK_FIELD_CONST(0x1, PMC_IMPL_IO_AO_HV_DPD_OFF_MASK_0_CAN0_EN_SHIFT)
#define PMC_IMPL_IO_AO_HV_DPD_OFF_MASK_0_CAN0_EN_RANGE                  5:5
#define PMC_IMPL_IO_AO_HV_DPD_OFF_MASK_0_CAN0_EN_MSB                    MK_SHIFT_CONST(5)
#define PMC_IMPL_IO_AO_HV_DPD_OFF_MASK_0_CAN0_EN_LSB                    MK_SHIFT_CONST(5)
#define PMC_IMPL_IO_AO_HV_DPD_OFF_MASK_0_CAN0_EN_WOFFSET                        0x0
#define PMC_IMPL_IO_AO_HV_DPD_OFF_MASK_0_CAN0_EN_DEFAULT                        MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_AO_HV_DPD_OFF_MASK_0_CAN0_EN_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_AO_HV_DPD_OFF_MASK_0_CAN0_EN_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_AO_HV_DPD_OFF_MASK_0_CAN0_EN_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_AO_HV_DPD_OFF_MASK_0_CAN0_EN_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_AO_HV_DPD_OFF_MASK_0_CAN0_EN_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_AO_HV_DPD_OFF_MASK_0_CAN0_EN_OFF                    MK_ENUM_CONST(0)
#define PMC_IMPL_IO_AO_HV_DPD_OFF_MASK_0_CAN0_EN_ON                     MK_ENUM_CONST(1)

// On - SOC_GPIO49 PAD(s) are masked to enter Deep Power Down mode from SC7 controller, Off - SOC_GPIO49 PAD(s) are free to enter Deep Power Down mode
#define PMC_IMPL_IO_AO_HV_DPD_OFF_MASK_0_SOC_GPIO49_SHIFT                       MK_SHIFT_CONST(6)
#define PMC_IMPL_IO_AO_HV_DPD_OFF_MASK_0_SOC_GPIO49_FIELD                       MK_FIELD_CONST(0x1, PMC_IMPL_IO_AO_HV_DPD_OFF_MASK_0_SOC_GPIO49_SHIFT)
#define PMC_IMPL_IO_AO_HV_DPD_OFF_MASK_0_SOC_GPIO49_RANGE                       6:6
#define PMC_IMPL_IO_AO_HV_DPD_OFF_MASK_0_SOC_GPIO49_MSB                 MK_SHIFT_CONST(6)
#define PMC_IMPL_IO_AO_HV_DPD_OFF_MASK_0_SOC_GPIO49_LSB                 MK_SHIFT_CONST(6)
#define PMC_IMPL_IO_AO_HV_DPD_OFF_MASK_0_SOC_GPIO49_WOFFSET                     0x0
#define PMC_IMPL_IO_AO_HV_DPD_OFF_MASK_0_SOC_GPIO49_DEFAULT                     MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_AO_HV_DPD_OFF_MASK_0_SOC_GPIO49_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_AO_HV_DPD_OFF_MASK_0_SOC_GPIO49_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_AO_HV_DPD_OFF_MASK_0_SOC_GPIO49_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_AO_HV_DPD_OFF_MASK_0_SOC_GPIO49_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_AO_HV_DPD_OFF_MASK_0_SOC_GPIO49_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_AO_HV_DPD_OFF_MASK_0_SOC_GPIO49_OFF                 MK_ENUM_CONST(0)
#define PMC_IMPL_IO_AO_HV_DPD_OFF_MASK_0_SOC_GPIO49_ON                  MK_ENUM_CONST(1)

// On - CAN0_ERR PAD(s) are masked to enter Deep Power Down mode from SC7 controller, Off - CAN0_ERR PAD(s) are free to enter Deep Power Down mode
#define PMC_IMPL_IO_AO_HV_DPD_OFF_MASK_0_CAN0_ERR_SHIFT                 MK_SHIFT_CONST(7)
#define PMC_IMPL_IO_AO_HV_DPD_OFF_MASK_0_CAN0_ERR_FIELD                 MK_FIELD_CONST(0x1, PMC_IMPL_IO_AO_HV_DPD_OFF_MASK_0_CAN0_ERR_SHIFT)
#define PMC_IMPL_IO_AO_HV_DPD_OFF_MASK_0_CAN0_ERR_RANGE                 7:7
#define PMC_IMPL_IO_AO_HV_DPD_OFF_MASK_0_CAN0_ERR_MSB                   MK_SHIFT_CONST(7)
#define PMC_IMPL_IO_AO_HV_DPD_OFF_MASK_0_CAN0_ERR_LSB                   MK_SHIFT_CONST(7)
#define PMC_IMPL_IO_AO_HV_DPD_OFF_MASK_0_CAN0_ERR_WOFFSET                       0x0
#define PMC_IMPL_IO_AO_HV_DPD_OFF_MASK_0_CAN0_ERR_DEFAULT                       MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_AO_HV_DPD_OFF_MASK_0_CAN0_ERR_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_AO_HV_DPD_OFF_MASK_0_CAN0_ERR_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_AO_HV_DPD_OFF_MASK_0_CAN0_ERR_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_AO_HV_DPD_OFF_MASK_0_CAN0_ERR_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_AO_HV_DPD_OFF_MASK_0_CAN0_ERR_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_AO_HV_DPD_OFF_MASK_0_CAN0_ERR_OFF                   MK_ENUM_CONST(0)
#define PMC_IMPL_IO_AO_HV_DPD_OFF_MASK_0_CAN0_ERR_ON                    MK_ENUM_CONST(1)

// On - CAN1_STB PAD(s) are masked to enter Deep Power Down mode from SC7 controller, Off - CAN1_STB PAD(s) are free to enter Deep Power Down mode
#define PMC_IMPL_IO_AO_HV_DPD_OFF_MASK_0_CAN1_STB_SHIFT                 MK_SHIFT_CONST(8)
#define PMC_IMPL_IO_AO_HV_DPD_OFF_MASK_0_CAN1_STB_FIELD                 MK_FIELD_CONST(0x1, PMC_IMPL_IO_AO_HV_DPD_OFF_MASK_0_CAN1_STB_SHIFT)
#define PMC_IMPL_IO_AO_HV_DPD_OFF_MASK_0_CAN1_STB_RANGE                 8:8
#define PMC_IMPL_IO_AO_HV_DPD_OFF_MASK_0_CAN1_STB_MSB                   MK_SHIFT_CONST(8)
#define PMC_IMPL_IO_AO_HV_DPD_OFF_MASK_0_CAN1_STB_LSB                   MK_SHIFT_CONST(8)
#define PMC_IMPL_IO_AO_HV_DPD_OFF_MASK_0_CAN1_STB_WOFFSET                       0x0
#define PMC_IMPL_IO_AO_HV_DPD_OFF_MASK_0_CAN1_STB_DEFAULT                       MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_AO_HV_DPD_OFF_MASK_0_CAN1_STB_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_AO_HV_DPD_OFF_MASK_0_CAN1_STB_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_AO_HV_DPD_OFF_MASK_0_CAN1_STB_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_AO_HV_DPD_OFF_MASK_0_CAN1_STB_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_AO_HV_DPD_OFF_MASK_0_CAN1_STB_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_AO_HV_DPD_OFF_MASK_0_CAN1_STB_OFF                   MK_ENUM_CONST(0)
#define PMC_IMPL_IO_AO_HV_DPD_OFF_MASK_0_CAN1_STB_ON                    MK_ENUM_CONST(1)

// On - CAN1_EN PAD(s) are masked to enter Deep Power Down mode from SC7 controller, Off - CAN1_EN PAD(s) are free to enter Deep Power Down mode
#define PMC_IMPL_IO_AO_HV_DPD_OFF_MASK_0_CAN1_EN_SHIFT                  MK_SHIFT_CONST(9)
#define PMC_IMPL_IO_AO_HV_DPD_OFF_MASK_0_CAN1_EN_FIELD                  MK_FIELD_CONST(0x1, PMC_IMPL_IO_AO_HV_DPD_OFF_MASK_0_CAN1_EN_SHIFT)
#define PMC_IMPL_IO_AO_HV_DPD_OFF_MASK_0_CAN1_EN_RANGE                  9:9
#define PMC_IMPL_IO_AO_HV_DPD_OFF_MASK_0_CAN1_EN_MSB                    MK_SHIFT_CONST(9)
#define PMC_IMPL_IO_AO_HV_DPD_OFF_MASK_0_CAN1_EN_LSB                    MK_SHIFT_CONST(9)
#define PMC_IMPL_IO_AO_HV_DPD_OFF_MASK_0_CAN1_EN_WOFFSET                        0x0
#define PMC_IMPL_IO_AO_HV_DPD_OFF_MASK_0_CAN1_EN_DEFAULT                        MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_AO_HV_DPD_OFF_MASK_0_CAN1_EN_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_AO_HV_DPD_OFF_MASK_0_CAN1_EN_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_AO_HV_DPD_OFF_MASK_0_CAN1_EN_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_AO_HV_DPD_OFF_MASK_0_CAN1_EN_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_AO_HV_DPD_OFF_MASK_0_CAN1_EN_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_AO_HV_DPD_OFF_MASK_0_CAN1_EN_OFF                    MK_ENUM_CONST(0)
#define PMC_IMPL_IO_AO_HV_DPD_OFF_MASK_0_CAN1_EN_ON                     MK_ENUM_CONST(1)

// On - SOC_GPIO50 PAD(s) are masked to enter Deep Power Down mode from SC7 controller, Off - SOC_GPIO50 PAD(s) are free to enter Deep Power Down mode
#define PMC_IMPL_IO_AO_HV_DPD_OFF_MASK_0_SOC_GPIO50_SHIFT                       MK_SHIFT_CONST(10)
#define PMC_IMPL_IO_AO_HV_DPD_OFF_MASK_0_SOC_GPIO50_FIELD                       MK_FIELD_CONST(0x1, PMC_IMPL_IO_AO_HV_DPD_OFF_MASK_0_SOC_GPIO50_SHIFT)
#define PMC_IMPL_IO_AO_HV_DPD_OFF_MASK_0_SOC_GPIO50_RANGE                       10:10
#define PMC_IMPL_IO_AO_HV_DPD_OFF_MASK_0_SOC_GPIO50_MSB                 MK_SHIFT_CONST(10)
#define PMC_IMPL_IO_AO_HV_DPD_OFF_MASK_0_SOC_GPIO50_LSB                 MK_SHIFT_CONST(10)
#define PMC_IMPL_IO_AO_HV_DPD_OFF_MASK_0_SOC_GPIO50_WOFFSET                     0x0
#define PMC_IMPL_IO_AO_HV_DPD_OFF_MASK_0_SOC_GPIO50_DEFAULT                     MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_AO_HV_DPD_OFF_MASK_0_SOC_GPIO50_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_AO_HV_DPD_OFF_MASK_0_SOC_GPIO50_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_AO_HV_DPD_OFF_MASK_0_SOC_GPIO50_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_AO_HV_DPD_OFF_MASK_0_SOC_GPIO50_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_AO_HV_DPD_OFF_MASK_0_SOC_GPIO50_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_AO_HV_DPD_OFF_MASK_0_SOC_GPIO50_OFF                 MK_ENUM_CONST(0)
#define PMC_IMPL_IO_AO_HV_DPD_OFF_MASK_0_SOC_GPIO50_ON                  MK_ENUM_CONST(1)

// On - CAN1_ERR PAD(s) are masked to enter Deep Power Down mode from SC7 controller, Off - CAN1_ERR PAD(s) are free to enter Deep Power Down mode
#define PMC_IMPL_IO_AO_HV_DPD_OFF_MASK_0_CAN1_ERR_SHIFT                 MK_SHIFT_CONST(11)
#define PMC_IMPL_IO_AO_HV_DPD_OFF_MASK_0_CAN1_ERR_FIELD                 MK_FIELD_CONST(0x1, PMC_IMPL_IO_AO_HV_DPD_OFF_MASK_0_CAN1_ERR_SHIFT)
#define PMC_IMPL_IO_AO_HV_DPD_OFF_MASK_0_CAN1_ERR_RANGE                 11:11
#define PMC_IMPL_IO_AO_HV_DPD_OFF_MASK_0_CAN1_ERR_MSB                   MK_SHIFT_CONST(11)
#define PMC_IMPL_IO_AO_HV_DPD_OFF_MASK_0_CAN1_ERR_LSB                   MK_SHIFT_CONST(11)
#define PMC_IMPL_IO_AO_HV_DPD_OFF_MASK_0_CAN1_ERR_WOFFSET                       0x0
#define PMC_IMPL_IO_AO_HV_DPD_OFF_MASK_0_CAN1_ERR_DEFAULT                       MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_AO_HV_DPD_OFF_MASK_0_CAN1_ERR_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_AO_HV_DPD_OFF_MASK_0_CAN1_ERR_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_AO_HV_DPD_OFF_MASK_0_CAN1_ERR_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_AO_HV_DPD_OFF_MASK_0_CAN1_ERR_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_AO_HV_DPD_OFF_MASK_0_CAN1_ERR_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_AO_HV_DPD_OFF_MASK_0_CAN1_ERR_OFF                   MK_ENUM_CONST(0)
#define PMC_IMPL_IO_AO_HV_DPD_OFF_MASK_0_CAN1_ERR_ON                    MK_ENUM_CONST(1)


// Register PMC_IMPL_IO_EQOS_DPD_REQ_0
#define PMC_IMPL_IO_EQOS_DPD_REQ_0                      MK_ADDR_CONST(0xe090)
#define PMC_IMPL_IO_EQOS_DPD_REQ_0_SECURE                       0x0
#define PMC_IMPL_IO_EQOS_DPD_REQ_0_DUAL                         0x0
#define PMC_IMPL_IO_EQOS_DPD_REQ_0_SCR                  IO_EQOS_SCR_0
#define PMC_IMPL_IO_EQOS_DPD_REQ_0_SCRREG                       PMC_IMPL_SCR_IO_EQOS_SCR_0
#define PMC_IMPL_IO_EQOS_DPD_REQ_0_WORD_COUNT                   0x1
#define PMC_IMPL_IO_EQOS_DPD_REQ_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_EQOS_DPD_REQ_0_RESET_MASK                   MK_MASK_CONST(0xc0000001)
#define PMC_IMPL_IO_EQOS_DPD_REQ_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_EQOS_DPD_REQ_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_EQOS_DPD_REQ_0_READ_MASK                    MK_MASK_CONST(0xc0000001)
#define PMC_IMPL_IO_EQOS_DPD_REQ_0_WRITE_MASK                   MK_MASK_CONST(0xc0000001)
// code of operation for all set bits
#define PMC_IMPL_IO_EQOS_DPD_REQ_0_CODE_SHIFT                   MK_SHIFT_CONST(30)
#define PMC_IMPL_IO_EQOS_DPD_REQ_0_CODE_FIELD                   MK_FIELD_CONST(0x3, PMC_IMPL_IO_EQOS_DPD_REQ_0_CODE_SHIFT)
#define PMC_IMPL_IO_EQOS_DPD_REQ_0_CODE_RANGE                   31:30
#define PMC_IMPL_IO_EQOS_DPD_REQ_0_CODE_MSB                     MK_SHIFT_CONST(31)
#define PMC_IMPL_IO_EQOS_DPD_REQ_0_CODE_LSB                     MK_SHIFT_CONST(30)
#define PMC_IMPL_IO_EQOS_DPD_REQ_0_CODE_WOFFSET                 0x0
#define PMC_IMPL_IO_EQOS_DPD_REQ_0_CODE_DEFAULT                 MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_EQOS_DPD_REQ_0_CODE_DEFAULT_MASK                    MK_MASK_CONST(0x3)
#define PMC_IMPL_IO_EQOS_DPD_REQ_0_CODE_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_EQOS_DPD_REQ_0_CODE_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_EQOS_DPD_REQ_0_CODE_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_EQOS_DPD_REQ_0_CODE_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_EQOS_DPD_REQ_0_CODE_IDLE                    MK_ENUM_CONST(0)
#define PMC_IMPL_IO_EQOS_DPD_REQ_0_CODE_DPD_OFF                 MK_ENUM_CONST(1)
#define PMC_IMPL_IO_EQOS_DPD_REQ_0_CODE_DPD_ON                  MK_ENUM_CONST(2)

// puts EQOS PAD(s) in/out of Depp Power Down (DPD) mode
#define PMC_IMPL_IO_EQOS_DPD_REQ_0_EQOS_SHIFT                   MK_SHIFT_CONST(0)
#define PMC_IMPL_IO_EQOS_DPD_REQ_0_EQOS_FIELD                   MK_FIELD_CONST(0x1, PMC_IMPL_IO_EQOS_DPD_REQ_0_EQOS_SHIFT)
#define PMC_IMPL_IO_EQOS_DPD_REQ_0_EQOS_RANGE                   0:0
#define PMC_IMPL_IO_EQOS_DPD_REQ_0_EQOS_MSB                     MK_SHIFT_CONST(0)
#define PMC_IMPL_IO_EQOS_DPD_REQ_0_EQOS_LSB                     MK_SHIFT_CONST(0)
#define PMC_IMPL_IO_EQOS_DPD_REQ_0_EQOS_WOFFSET                 0x0
#define PMC_IMPL_IO_EQOS_DPD_REQ_0_EQOS_DEFAULT                 MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_EQOS_DPD_REQ_0_EQOS_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_EQOS_DPD_REQ_0_EQOS_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_EQOS_DPD_REQ_0_EQOS_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_EQOS_DPD_REQ_0_EQOS_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_EQOS_DPD_REQ_0_EQOS_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_EQOS_DPD_REQ_0_EQOS_OFF                     MK_ENUM_CONST(0)
#define PMC_IMPL_IO_EQOS_DPD_REQ_0_EQOS_ON                      MK_ENUM_CONST(1)


// Register PMC_IMPL_IO_EQOS_DPD_STATUS_0
#define PMC_IMPL_IO_EQOS_DPD_STATUS_0                   MK_ADDR_CONST(0xe094)
#define PMC_IMPL_IO_EQOS_DPD_STATUS_0_SECURE                    0x0
#define PMC_IMPL_IO_EQOS_DPD_STATUS_0_DUAL                      0x0
#define PMC_IMPL_IO_EQOS_DPD_STATUS_0_SCR                       IO_EQOS_SCR_0
#define PMC_IMPL_IO_EQOS_DPD_STATUS_0_SCRREG                    PMC_IMPL_SCR_IO_EQOS_SCR_0
#define PMC_IMPL_IO_EQOS_DPD_STATUS_0_WORD_COUNT                        0x1
#define PMC_IMPL_IO_EQOS_DPD_STATUS_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_EQOS_DPD_STATUS_0_RESET_MASK                        MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_EQOS_DPD_STATUS_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_EQOS_DPD_STATUS_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_EQOS_DPD_STATUS_0_READ_MASK                         MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_EQOS_DPD_STATUS_0_WRITE_MASK                        MK_MASK_CONST(0x0)
// On - EQOS PAD(s) is in Deep Power Down mode, Off - EQOS PAD(s) is out of Deep Power Down mode
#define PMC_IMPL_IO_EQOS_DPD_STATUS_0_EQOS_SHIFT                        MK_SHIFT_CONST(0)
#define PMC_IMPL_IO_EQOS_DPD_STATUS_0_EQOS_FIELD                        MK_FIELD_CONST(0x1, PMC_IMPL_IO_EQOS_DPD_STATUS_0_EQOS_SHIFT)
#define PMC_IMPL_IO_EQOS_DPD_STATUS_0_EQOS_RANGE                        0:0
#define PMC_IMPL_IO_EQOS_DPD_STATUS_0_EQOS_MSB                  MK_SHIFT_CONST(0)
#define PMC_IMPL_IO_EQOS_DPD_STATUS_0_EQOS_LSB                  MK_SHIFT_CONST(0)
#define PMC_IMPL_IO_EQOS_DPD_STATUS_0_EQOS_WOFFSET                      0x0
#define PMC_IMPL_IO_EQOS_DPD_STATUS_0_EQOS_DEFAULT                      MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_EQOS_DPD_STATUS_0_EQOS_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_EQOS_DPD_STATUS_0_EQOS_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_EQOS_DPD_STATUS_0_EQOS_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_EQOS_DPD_STATUS_0_EQOS_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_EQOS_DPD_STATUS_0_EQOS_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_EQOS_DPD_STATUS_0_EQOS_OFF                  MK_ENUM_CONST(0)
#define PMC_IMPL_IO_EQOS_DPD_STATUS_0_EQOS_ON                   MK_ENUM_CONST(1)


// Register PMC_IMPL_IO_PEX_CTL_B_DPD_REQ_0
#define PMC_IMPL_IO_PEX_CTL_B_DPD_REQ_0                 MK_ADDR_CONST(0xe098)
#define PMC_IMPL_IO_PEX_CTL_B_DPD_REQ_0_SECURE                  0x0
#define PMC_IMPL_IO_PEX_CTL_B_DPD_REQ_0_DUAL                    0x0
#define PMC_IMPL_IO_PEX_CTL_B_DPD_REQ_0_SCR                     IO_PEX_CTL_B_SCR_0
#define PMC_IMPL_IO_PEX_CTL_B_DPD_REQ_0_SCRREG                  PMC_IMPL_SCR_IO_PEX_CTL_B_SCR_0
#define PMC_IMPL_IO_PEX_CTL_B_DPD_REQ_0_WORD_COUNT                      0x1
#define PMC_IMPL_IO_PEX_CTL_B_DPD_REQ_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_PEX_CTL_B_DPD_REQ_0_RESET_MASK                      MK_MASK_CONST(0xc0000001)
#define PMC_IMPL_IO_PEX_CTL_B_DPD_REQ_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_PEX_CTL_B_DPD_REQ_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_PEX_CTL_B_DPD_REQ_0_READ_MASK                       MK_MASK_CONST(0xc0000001)
#define PMC_IMPL_IO_PEX_CTL_B_DPD_REQ_0_WRITE_MASK                      MK_MASK_CONST(0xc0000001)
// code of operation for all set bits
#define PMC_IMPL_IO_PEX_CTL_B_DPD_REQ_0_CODE_SHIFT                      MK_SHIFT_CONST(30)
#define PMC_IMPL_IO_PEX_CTL_B_DPD_REQ_0_CODE_FIELD                      MK_FIELD_CONST(0x3, PMC_IMPL_IO_PEX_CTL_B_DPD_REQ_0_CODE_SHIFT)
#define PMC_IMPL_IO_PEX_CTL_B_DPD_REQ_0_CODE_RANGE                      31:30
#define PMC_IMPL_IO_PEX_CTL_B_DPD_REQ_0_CODE_MSB                        MK_SHIFT_CONST(31)
#define PMC_IMPL_IO_PEX_CTL_B_DPD_REQ_0_CODE_LSB                        MK_SHIFT_CONST(30)
#define PMC_IMPL_IO_PEX_CTL_B_DPD_REQ_0_CODE_WOFFSET                    0x0
#define PMC_IMPL_IO_PEX_CTL_B_DPD_REQ_0_CODE_DEFAULT                    MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_PEX_CTL_B_DPD_REQ_0_CODE_DEFAULT_MASK                       MK_MASK_CONST(0x3)
#define PMC_IMPL_IO_PEX_CTL_B_DPD_REQ_0_CODE_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_PEX_CTL_B_DPD_REQ_0_CODE_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_PEX_CTL_B_DPD_REQ_0_CODE_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_PEX_CTL_B_DPD_REQ_0_CODE_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_PEX_CTL_B_DPD_REQ_0_CODE_IDLE                       MK_ENUM_CONST(0)
#define PMC_IMPL_IO_PEX_CTL_B_DPD_REQ_0_CODE_DPD_OFF                    MK_ENUM_CONST(1)
#define PMC_IMPL_IO_PEX_CTL_B_DPD_REQ_0_CODE_DPD_ON                     MK_ENUM_CONST(2)

// puts PEX_CTL_2 PAD(s) in/out of Depp Power Down (DPD) mode
#define PMC_IMPL_IO_PEX_CTL_B_DPD_REQ_0_PEX_CTL_2_SHIFT                 MK_SHIFT_CONST(0)
#define PMC_IMPL_IO_PEX_CTL_B_DPD_REQ_0_PEX_CTL_2_FIELD                 MK_FIELD_CONST(0x1, PMC_IMPL_IO_PEX_CTL_B_DPD_REQ_0_PEX_CTL_2_SHIFT)
#define PMC_IMPL_IO_PEX_CTL_B_DPD_REQ_0_PEX_CTL_2_RANGE                 0:0
#define PMC_IMPL_IO_PEX_CTL_B_DPD_REQ_0_PEX_CTL_2_MSB                   MK_SHIFT_CONST(0)
#define PMC_IMPL_IO_PEX_CTL_B_DPD_REQ_0_PEX_CTL_2_LSB                   MK_SHIFT_CONST(0)
#define PMC_IMPL_IO_PEX_CTL_B_DPD_REQ_0_PEX_CTL_2_WOFFSET                       0x0
#define PMC_IMPL_IO_PEX_CTL_B_DPD_REQ_0_PEX_CTL_2_DEFAULT                       MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_PEX_CTL_B_DPD_REQ_0_PEX_CTL_2_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_PEX_CTL_B_DPD_REQ_0_PEX_CTL_2_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_PEX_CTL_B_DPD_REQ_0_PEX_CTL_2_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_PEX_CTL_B_DPD_REQ_0_PEX_CTL_2_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_PEX_CTL_B_DPD_REQ_0_PEX_CTL_2_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_PEX_CTL_B_DPD_REQ_0_PEX_CTL_2_OFF                   MK_ENUM_CONST(0)
#define PMC_IMPL_IO_PEX_CTL_B_DPD_REQ_0_PEX_CTL_2_ON                    MK_ENUM_CONST(1)


// Register PMC_IMPL_IO_PEX_CTL_B_DPD_STATUS_0
#define PMC_IMPL_IO_PEX_CTL_B_DPD_STATUS_0                      MK_ADDR_CONST(0xe09c)
#define PMC_IMPL_IO_PEX_CTL_B_DPD_STATUS_0_SECURE                       0x0
#define PMC_IMPL_IO_PEX_CTL_B_DPD_STATUS_0_DUAL                         0x0
#define PMC_IMPL_IO_PEX_CTL_B_DPD_STATUS_0_SCR                  IO_PEX_CTL_B_SCR_0
#define PMC_IMPL_IO_PEX_CTL_B_DPD_STATUS_0_SCRREG                       PMC_IMPL_SCR_IO_PEX_CTL_B_SCR_0
#define PMC_IMPL_IO_PEX_CTL_B_DPD_STATUS_0_WORD_COUNT                   0x1
#define PMC_IMPL_IO_PEX_CTL_B_DPD_STATUS_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_PEX_CTL_B_DPD_STATUS_0_RESET_MASK                   MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_PEX_CTL_B_DPD_STATUS_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_PEX_CTL_B_DPD_STATUS_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_PEX_CTL_B_DPD_STATUS_0_READ_MASK                    MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_PEX_CTL_B_DPD_STATUS_0_WRITE_MASK                   MK_MASK_CONST(0x0)
// On - PEX_CTL_2 PAD(s) is in Deep Power Down mode, Off - PEX_CTL_2 PAD(s) is out of Deep Power Down mode
#define PMC_IMPL_IO_PEX_CTL_B_DPD_STATUS_0_PEX_CTL_2_SHIFT                      MK_SHIFT_CONST(0)
#define PMC_IMPL_IO_PEX_CTL_B_DPD_STATUS_0_PEX_CTL_2_FIELD                      MK_FIELD_CONST(0x1, PMC_IMPL_IO_PEX_CTL_B_DPD_STATUS_0_PEX_CTL_2_SHIFT)
#define PMC_IMPL_IO_PEX_CTL_B_DPD_STATUS_0_PEX_CTL_2_RANGE                      0:0
#define PMC_IMPL_IO_PEX_CTL_B_DPD_STATUS_0_PEX_CTL_2_MSB                        MK_SHIFT_CONST(0)
#define PMC_IMPL_IO_PEX_CTL_B_DPD_STATUS_0_PEX_CTL_2_LSB                        MK_SHIFT_CONST(0)
#define PMC_IMPL_IO_PEX_CTL_B_DPD_STATUS_0_PEX_CTL_2_WOFFSET                    0x0
#define PMC_IMPL_IO_PEX_CTL_B_DPD_STATUS_0_PEX_CTL_2_DEFAULT                    MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_PEX_CTL_B_DPD_STATUS_0_PEX_CTL_2_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_PEX_CTL_B_DPD_STATUS_0_PEX_CTL_2_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_PEX_CTL_B_DPD_STATUS_0_PEX_CTL_2_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_PEX_CTL_B_DPD_STATUS_0_PEX_CTL_2_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_PEX_CTL_B_DPD_STATUS_0_PEX_CTL_2_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_PEX_CTL_B_DPD_STATUS_0_PEX_CTL_2_OFF                        MK_ENUM_CONST(0)
#define PMC_IMPL_IO_PEX_CTL_B_DPD_STATUS_0_PEX_CTL_2_ON                 MK_ENUM_CONST(1)


// Register PMC_IMPL_IO_PEX_CTL_C_DPD_REQ_0
#define PMC_IMPL_IO_PEX_CTL_C_DPD_REQ_0                 MK_ADDR_CONST(0xe0a0)
#define PMC_IMPL_IO_PEX_CTL_C_DPD_REQ_0_SECURE                  0x0
#define PMC_IMPL_IO_PEX_CTL_C_DPD_REQ_0_DUAL                    0x0
#define PMC_IMPL_IO_PEX_CTL_C_DPD_REQ_0_SCR                     IO_PEX_CTL_C_SCR_0
#define PMC_IMPL_IO_PEX_CTL_C_DPD_REQ_0_SCRREG                  PMC_IMPL_SCR_IO_PEX_CTL_C_SCR_0
#define PMC_IMPL_IO_PEX_CTL_C_DPD_REQ_0_WORD_COUNT                      0x1
#define PMC_IMPL_IO_PEX_CTL_C_DPD_REQ_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_PEX_CTL_C_DPD_REQ_0_RESET_MASK                      MK_MASK_CONST(0xc0000001)
#define PMC_IMPL_IO_PEX_CTL_C_DPD_REQ_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_PEX_CTL_C_DPD_REQ_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_PEX_CTL_C_DPD_REQ_0_READ_MASK                       MK_MASK_CONST(0xc0000001)
#define PMC_IMPL_IO_PEX_CTL_C_DPD_REQ_0_WRITE_MASK                      MK_MASK_CONST(0xc0000001)
// code of operation for all set bits
#define PMC_IMPL_IO_PEX_CTL_C_DPD_REQ_0_CODE_SHIFT                      MK_SHIFT_CONST(30)
#define PMC_IMPL_IO_PEX_CTL_C_DPD_REQ_0_CODE_FIELD                      MK_FIELD_CONST(0x3, PMC_IMPL_IO_PEX_CTL_C_DPD_REQ_0_CODE_SHIFT)
#define PMC_IMPL_IO_PEX_CTL_C_DPD_REQ_0_CODE_RANGE                      31:30
#define PMC_IMPL_IO_PEX_CTL_C_DPD_REQ_0_CODE_MSB                        MK_SHIFT_CONST(31)
#define PMC_IMPL_IO_PEX_CTL_C_DPD_REQ_0_CODE_LSB                        MK_SHIFT_CONST(30)
#define PMC_IMPL_IO_PEX_CTL_C_DPD_REQ_0_CODE_WOFFSET                    0x0
#define PMC_IMPL_IO_PEX_CTL_C_DPD_REQ_0_CODE_DEFAULT                    MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_PEX_CTL_C_DPD_REQ_0_CODE_DEFAULT_MASK                       MK_MASK_CONST(0x3)
#define PMC_IMPL_IO_PEX_CTL_C_DPD_REQ_0_CODE_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_PEX_CTL_C_DPD_REQ_0_CODE_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_PEX_CTL_C_DPD_REQ_0_CODE_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_PEX_CTL_C_DPD_REQ_0_CODE_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_PEX_CTL_C_DPD_REQ_0_CODE_IDLE                       MK_ENUM_CONST(0)
#define PMC_IMPL_IO_PEX_CTL_C_DPD_REQ_0_CODE_DPD_OFF                    MK_ENUM_CONST(1)
#define PMC_IMPL_IO_PEX_CTL_C_DPD_REQ_0_CODE_DPD_ON                     MK_ENUM_CONST(2)

// puts PEX_CTL_3 PAD(s) in/out of Depp Power Down (DPD) mode
#define PMC_IMPL_IO_PEX_CTL_C_DPD_REQ_0_PEX_CTL_3_SHIFT                 MK_SHIFT_CONST(0)
#define PMC_IMPL_IO_PEX_CTL_C_DPD_REQ_0_PEX_CTL_3_FIELD                 MK_FIELD_CONST(0x1, PMC_IMPL_IO_PEX_CTL_C_DPD_REQ_0_PEX_CTL_3_SHIFT)
#define PMC_IMPL_IO_PEX_CTL_C_DPD_REQ_0_PEX_CTL_3_RANGE                 0:0
#define PMC_IMPL_IO_PEX_CTL_C_DPD_REQ_0_PEX_CTL_3_MSB                   MK_SHIFT_CONST(0)
#define PMC_IMPL_IO_PEX_CTL_C_DPD_REQ_0_PEX_CTL_3_LSB                   MK_SHIFT_CONST(0)
#define PMC_IMPL_IO_PEX_CTL_C_DPD_REQ_0_PEX_CTL_3_WOFFSET                       0x0
#define PMC_IMPL_IO_PEX_CTL_C_DPD_REQ_0_PEX_CTL_3_DEFAULT                       MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_PEX_CTL_C_DPD_REQ_0_PEX_CTL_3_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_PEX_CTL_C_DPD_REQ_0_PEX_CTL_3_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_PEX_CTL_C_DPD_REQ_0_PEX_CTL_3_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_PEX_CTL_C_DPD_REQ_0_PEX_CTL_3_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_PEX_CTL_C_DPD_REQ_0_PEX_CTL_3_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_PEX_CTL_C_DPD_REQ_0_PEX_CTL_3_OFF                   MK_ENUM_CONST(0)
#define PMC_IMPL_IO_PEX_CTL_C_DPD_REQ_0_PEX_CTL_3_ON                    MK_ENUM_CONST(1)


// Register PMC_IMPL_IO_PEX_CTL_C_DPD_STATUS_0
#define PMC_IMPL_IO_PEX_CTL_C_DPD_STATUS_0                      MK_ADDR_CONST(0xe0a4)
#define PMC_IMPL_IO_PEX_CTL_C_DPD_STATUS_0_SECURE                       0x0
#define PMC_IMPL_IO_PEX_CTL_C_DPD_STATUS_0_DUAL                         0x0
#define PMC_IMPL_IO_PEX_CTL_C_DPD_STATUS_0_SCR                  IO_PEX_CTL_C_SCR_0
#define PMC_IMPL_IO_PEX_CTL_C_DPD_STATUS_0_SCRREG                       PMC_IMPL_SCR_IO_PEX_CTL_C_SCR_0
#define PMC_IMPL_IO_PEX_CTL_C_DPD_STATUS_0_WORD_COUNT                   0x1
#define PMC_IMPL_IO_PEX_CTL_C_DPD_STATUS_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_PEX_CTL_C_DPD_STATUS_0_RESET_MASK                   MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_PEX_CTL_C_DPD_STATUS_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_PEX_CTL_C_DPD_STATUS_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_PEX_CTL_C_DPD_STATUS_0_READ_MASK                    MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_PEX_CTL_C_DPD_STATUS_0_WRITE_MASK                   MK_MASK_CONST(0x0)
// On - PEX_CTL_3 PAD(s) is in Deep Power Down mode, Off - PEX_CTL_3 PAD(s) is out of Deep Power Down mode
#define PMC_IMPL_IO_PEX_CTL_C_DPD_STATUS_0_PEX_CTL_3_SHIFT                      MK_SHIFT_CONST(0)
#define PMC_IMPL_IO_PEX_CTL_C_DPD_STATUS_0_PEX_CTL_3_FIELD                      MK_FIELD_CONST(0x1, PMC_IMPL_IO_PEX_CTL_C_DPD_STATUS_0_PEX_CTL_3_SHIFT)
#define PMC_IMPL_IO_PEX_CTL_C_DPD_STATUS_0_PEX_CTL_3_RANGE                      0:0
#define PMC_IMPL_IO_PEX_CTL_C_DPD_STATUS_0_PEX_CTL_3_MSB                        MK_SHIFT_CONST(0)
#define PMC_IMPL_IO_PEX_CTL_C_DPD_STATUS_0_PEX_CTL_3_LSB                        MK_SHIFT_CONST(0)
#define PMC_IMPL_IO_PEX_CTL_C_DPD_STATUS_0_PEX_CTL_3_WOFFSET                    0x0
#define PMC_IMPL_IO_PEX_CTL_C_DPD_STATUS_0_PEX_CTL_3_DEFAULT                    MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_PEX_CTL_C_DPD_STATUS_0_PEX_CTL_3_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_PEX_CTL_C_DPD_STATUS_0_PEX_CTL_3_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_PEX_CTL_C_DPD_STATUS_0_PEX_CTL_3_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_PEX_CTL_C_DPD_STATUS_0_PEX_CTL_3_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_PEX_CTL_C_DPD_STATUS_0_PEX_CTL_3_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_PEX_CTL_C_DPD_STATUS_0_PEX_CTL_3_OFF                        MK_ENUM_CONST(0)
#define PMC_IMPL_IO_PEX_CTL_C_DPD_STATUS_0_PEX_CTL_3_ON                 MK_ENUM_CONST(1)


// Register PMC_IMPL_IO_PEX_CLK_C_DPD_REQ_0
#define PMC_IMPL_IO_PEX_CLK_C_DPD_REQ_0                 MK_ADDR_CONST(0xe0a8)
#define PMC_IMPL_IO_PEX_CLK_C_DPD_REQ_0_SECURE                  0x0
#define PMC_IMPL_IO_PEX_CLK_C_DPD_REQ_0_DUAL                    0x0
#define PMC_IMPL_IO_PEX_CLK_C_DPD_REQ_0_SCR                     IO_PEX_CLK_C_SCR_0
#define PMC_IMPL_IO_PEX_CLK_C_DPD_REQ_0_SCRREG                  PMC_IMPL_SCR_IO_PEX_CLK_C_SCR_0
#define PMC_IMPL_IO_PEX_CLK_C_DPD_REQ_0_WORD_COUNT                      0x1
#define PMC_IMPL_IO_PEX_CLK_C_DPD_REQ_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_PEX_CLK_C_DPD_REQ_0_RESET_MASK                      MK_MASK_CONST(0xc000000f)
#define PMC_IMPL_IO_PEX_CLK_C_DPD_REQ_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_PEX_CLK_C_DPD_REQ_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_PEX_CLK_C_DPD_REQ_0_READ_MASK                       MK_MASK_CONST(0xc000000f)
#define PMC_IMPL_IO_PEX_CLK_C_DPD_REQ_0_WRITE_MASK                      MK_MASK_CONST(0xc000000f)
// code of operation for all set bits
#define PMC_IMPL_IO_PEX_CLK_C_DPD_REQ_0_CODE_SHIFT                      MK_SHIFT_CONST(30)
#define PMC_IMPL_IO_PEX_CLK_C_DPD_REQ_0_CODE_FIELD                      MK_FIELD_CONST(0x3, PMC_IMPL_IO_PEX_CLK_C_DPD_REQ_0_CODE_SHIFT)
#define PMC_IMPL_IO_PEX_CLK_C_DPD_REQ_0_CODE_RANGE                      31:30
#define PMC_IMPL_IO_PEX_CLK_C_DPD_REQ_0_CODE_MSB                        MK_SHIFT_CONST(31)
#define PMC_IMPL_IO_PEX_CLK_C_DPD_REQ_0_CODE_LSB                        MK_SHIFT_CONST(30)
#define PMC_IMPL_IO_PEX_CLK_C_DPD_REQ_0_CODE_WOFFSET                    0x0
#define PMC_IMPL_IO_PEX_CLK_C_DPD_REQ_0_CODE_DEFAULT                    MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_PEX_CLK_C_DPD_REQ_0_CODE_DEFAULT_MASK                       MK_MASK_CONST(0x3)
#define PMC_IMPL_IO_PEX_CLK_C_DPD_REQ_0_CODE_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_PEX_CLK_C_DPD_REQ_0_CODE_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_PEX_CLK_C_DPD_REQ_0_CODE_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_PEX_CLK_C_DPD_REQ_0_CODE_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_PEX_CLK_C_DPD_REQ_0_CODE_IDLE                       MK_ENUM_CONST(0)
#define PMC_IMPL_IO_PEX_CLK_C_DPD_REQ_0_CODE_DPD_OFF                    MK_ENUM_CONST(1)
#define PMC_IMPL_IO_PEX_CLK_C_DPD_REQ_0_CODE_DPD_ON                     MK_ENUM_CONST(2)

// puts PEX_CLK2 PAD(s) in/out of Depp Power Down (DPD) mode
#define PMC_IMPL_IO_PEX_CLK_C_DPD_REQ_0_PEX_CLK2_SHIFT                  MK_SHIFT_CONST(0)
#define PMC_IMPL_IO_PEX_CLK_C_DPD_REQ_0_PEX_CLK2_FIELD                  MK_FIELD_CONST(0x1, PMC_IMPL_IO_PEX_CLK_C_DPD_REQ_0_PEX_CLK2_SHIFT)
#define PMC_IMPL_IO_PEX_CLK_C_DPD_REQ_0_PEX_CLK2_RANGE                  0:0
#define PMC_IMPL_IO_PEX_CLK_C_DPD_REQ_0_PEX_CLK2_MSB                    MK_SHIFT_CONST(0)
#define PMC_IMPL_IO_PEX_CLK_C_DPD_REQ_0_PEX_CLK2_LSB                    MK_SHIFT_CONST(0)
#define PMC_IMPL_IO_PEX_CLK_C_DPD_REQ_0_PEX_CLK2_WOFFSET                        0x0
#define PMC_IMPL_IO_PEX_CLK_C_DPD_REQ_0_PEX_CLK2_DEFAULT                        MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_PEX_CLK_C_DPD_REQ_0_PEX_CLK2_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_PEX_CLK_C_DPD_REQ_0_PEX_CLK2_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_PEX_CLK_C_DPD_REQ_0_PEX_CLK2_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_PEX_CLK_C_DPD_REQ_0_PEX_CLK2_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_PEX_CLK_C_DPD_REQ_0_PEX_CLK2_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_PEX_CLK_C_DPD_REQ_0_PEX_CLK2_OFF                    MK_ENUM_CONST(0)
#define PMC_IMPL_IO_PEX_CLK_C_DPD_REQ_0_PEX_CLK2_ON                     MK_ENUM_CONST(1)

// puts PEX_CLK2_BIAS0 PAD(s) in/out of Depp Power Down (DPD) mode
#define PMC_IMPL_IO_PEX_CLK_C_DPD_REQ_0_PEX_CLK2_BIAS0_SHIFT                    MK_SHIFT_CONST(1)
#define PMC_IMPL_IO_PEX_CLK_C_DPD_REQ_0_PEX_CLK2_BIAS0_FIELD                    MK_FIELD_CONST(0x1, PMC_IMPL_IO_PEX_CLK_C_DPD_REQ_0_PEX_CLK2_BIAS0_SHIFT)
#define PMC_IMPL_IO_PEX_CLK_C_DPD_REQ_0_PEX_CLK2_BIAS0_RANGE                    1:1
#define PMC_IMPL_IO_PEX_CLK_C_DPD_REQ_0_PEX_CLK2_BIAS0_MSB                      MK_SHIFT_CONST(1)
#define PMC_IMPL_IO_PEX_CLK_C_DPD_REQ_0_PEX_CLK2_BIAS0_LSB                      MK_SHIFT_CONST(1)
#define PMC_IMPL_IO_PEX_CLK_C_DPD_REQ_0_PEX_CLK2_BIAS0_WOFFSET                  0x0
#define PMC_IMPL_IO_PEX_CLK_C_DPD_REQ_0_PEX_CLK2_BIAS0_DEFAULT                  MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_PEX_CLK_C_DPD_REQ_0_PEX_CLK2_BIAS0_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_PEX_CLK_C_DPD_REQ_0_PEX_CLK2_BIAS0_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_PEX_CLK_C_DPD_REQ_0_PEX_CLK2_BIAS0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_PEX_CLK_C_DPD_REQ_0_PEX_CLK2_BIAS0_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_PEX_CLK_C_DPD_REQ_0_PEX_CLK2_BIAS0_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_PEX_CLK_C_DPD_REQ_0_PEX_CLK2_BIAS0_OFF                      MK_ENUM_CONST(0)
#define PMC_IMPL_IO_PEX_CLK_C_DPD_REQ_0_PEX_CLK2_BIAS0_ON                       MK_ENUM_CONST(1)

// puts PEX_CLK3 PAD(s) in/out of Depp Power Down (DPD) mode
#define PMC_IMPL_IO_PEX_CLK_C_DPD_REQ_0_PEX_CLK3_SHIFT                  MK_SHIFT_CONST(2)
#define PMC_IMPL_IO_PEX_CLK_C_DPD_REQ_0_PEX_CLK3_FIELD                  MK_FIELD_CONST(0x1, PMC_IMPL_IO_PEX_CLK_C_DPD_REQ_0_PEX_CLK3_SHIFT)
#define PMC_IMPL_IO_PEX_CLK_C_DPD_REQ_0_PEX_CLK3_RANGE                  2:2
#define PMC_IMPL_IO_PEX_CLK_C_DPD_REQ_0_PEX_CLK3_MSB                    MK_SHIFT_CONST(2)
#define PMC_IMPL_IO_PEX_CLK_C_DPD_REQ_0_PEX_CLK3_LSB                    MK_SHIFT_CONST(2)
#define PMC_IMPL_IO_PEX_CLK_C_DPD_REQ_0_PEX_CLK3_WOFFSET                        0x0
#define PMC_IMPL_IO_PEX_CLK_C_DPD_REQ_0_PEX_CLK3_DEFAULT                        MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_PEX_CLK_C_DPD_REQ_0_PEX_CLK3_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_PEX_CLK_C_DPD_REQ_0_PEX_CLK3_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_PEX_CLK_C_DPD_REQ_0_PEX_CLK3_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_PEX_CLK_C_DPD_REQ_0_PEX_CLK3_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_PEX_CLK_C_DPD_REQ_0_PEX_CLK3_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_PEX_CLK_C_DPD_REQ_0_PEX_CLK3_OFF                    MK_ENUM_CONST(0)
#define PMC_IMPL_IO_PEX_CLK_C_DPD_REQ_0_PEX_CLK3_ON                     MK_ENUM_CONST(1)

// puts PEX_CLK3_BIAS1 PAD(s) in/out of Depp Power Down (DPD) mode
#define PMC_IMPL_IO_PEX_CLK_C_DPD_REQ_0_PEX_CLK3_BIAS1_SHIFT                    MK_SHIFT_CONST(3)
#define PMC_IMPL_IO_PEX_CLK_C_DPD_REQ_0_PEX_CLK3_BIAS1_FIELD                    MK_FIELD_CONST(0x1, PMC_IMPL_IO_PEX_CLK_C_DPD_REQ_0_PEX_CLK3_BIAS1_SHIFT)
#define PMC_IMPL_IO_PEX_CLK_C_DPD_REQ_0_PEX_CLK3_BIAS1_RANGE                    3:3
#define PMC_IMPL_IO_PEX_CLK_C_DPD_REQ_0_PEX_CLK3_BIAS1_MSB                      MK_SHIFT_CONST(3)
#define PMC_IMPL_IO_PEX_CLK_C_DPD_REQ_0_PEX_CLK3_BIAS1_LSB                      MK_SHIFT_CONST(3)
#define PMC_IMPL_IO_PEX_CLK_C_DPD_REQ_0_PEX_CLK3_BIAS1_WOFFSET                  0x0
#define PMC_IMPL_IO_PEX_CLK_C_DPD_REQ_0_PEX_CLK3_BIAS1_DEFAULT                  MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_PEX_CLK_C_DPD_REQ_0_PEX_CLK3_BIAS1_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_PEX_CLK_C_DPD_REQ_0_PEX_CLK3_BIAS1_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_PEX_CLK_C_DPD_REQ_0_PEX_CLK3_BIAS1_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_PEX_CLK_C_DPD_REQ_0_PEX_CLK3_BIAS1_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_PEX_CLK_C_DPD_REQ_0_PEX_CLK3_BIAS1_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_PEX_CLK_C_DPD_REQ_0_PEX_CLK3_BIAS1_OFF                      MK_ENUM_CONST(0)
#define PMC_IMPL_IO_PEX_CLK_C_DPD_REQ_0_PEX_CLK3_BIAS1_ON                       MK_ENUM_CONST(1)


// Register PMC_IMPL_IO_PEX_CLK_C_DPD_STATUS_0
#define PMC_IMPL_IO_PEX_CLK_C_DPD_STATUS_0                      MK_ADDR_CONST(0xe0ac)
#define PMC_IMPL_IO_PEX_CLK_C_DPD_STATUS_0_SECURE                       0x0
#define PMC_IMPL_IO_PEX_CLK_C_DPD_STATUS_0_DUAL                         0x0
#define PMC_IMPL_IO_PEX_CLK_C_DPD_STATUS_0_SCR                  IO_PEX_CLK_C_SCR_0
#define PMC_IMPL_IO_PEX_CLK_C_DPD_STATUS_0_SCRREG                       PMC_IMPL_SCR_IO_PEX_CLK_C_SCR_0
#define PMC_IMPL_IO_PEX_CLK_C_DPD_STATUS_0_WORD_COUNT                   0x1
#define PMC_IMPL_IO_PEX_CLK_C_DPD_STATUS_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_PEX_CLK_C_DPD_STATUS_0_RESET_MASK                   MK_MASK_CONST(0xf)
#define PMC_IMPL_IO_PEX_CLK_C_DPD_STATUS_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_PEX_CLK_C_DPD_STATUS_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_PEX_CLK_C_DPD_STATUS_0_READ_MASK                    MK_MASK_CONST(0xf)
#define PMC_IMPL_IO_PEX_CLK_C_DPD_STATUS_0_WRITE_MASK                   MK_MASK_CONST(0x0)
// On - PEX_CLK2 PAD(s) is in Deep Power Down mode, Off - PEX_CLK2 PAD(s) is out of Deep Power Down mode
#define PMC_IMPL_IO_PEX_CLK_C_DPD_STATUS_0_PEX_CLK2_SHIFT                       MK_SHIFT_CONST(0)
#define PMC_IMPL_IO_PEX_CLK_C_DPD_STATUS_0_PEX_CLK2_FIELD                       MK_FIELD_CONST(0x1, PMC_IMPL_IO_PEX_CLK_C_DPD_STATUS_0_PEX_CLK2_SHIFT)
#define PMC_IMPL_IO_PEX_CLK_C_DPD_STATUS_0_PEX_CLK2_RANGE                       0:0
#define PMC_IMPL_IO_PEX_CLK_C_DPD_STATUS_0_PEX_CLK2_MSB                 MK_SHIFT_CONST(0)
#define PMC_IMPL_IO_PEX_CLK_C_DPD_STATUS_0_PEX_CLK2_LSB                 MK_SHIFT_CONST(0)
#define PMC_IMPL_IO_PEX_CLK_C_DPD_STATUS_0_PEX_CLK2_WOFFSET                     0x0
#define PMC_IMPL_IO_PEX_CLK_C_DPD_STATUS_0_PEX_CLK2_DEFAULT                     MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_PEX_CLK_C_DPD_STATUS_0_PEX_CLK2_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_PEX_CLK_C_DPD_STATUS_0_PEX_CLK2_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_PEX_CLK_C_DPD_STATUS_0_PEX_CLK2_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_PEX_CLK_C_DPD_STATUS_0_PEX_CLK2_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_PEX_CLK_C_DPD_STATUS_0_PEX_CLK2_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_PEX_CLK_C_DPD_STATUS_0_PEX_CLK2_OFF                 MK_ENUM_CONST(0)
#define PMC_IMPL_IO_PEX_CLK_C_DPD_STATUS_0_PEX_CLK2_ON                  MK_ENUM_CONST(1)

// On - PEX_CLK2_BIAS0 PAD(s) is in Deep Power Down mode, Off - PEX_CLK2_BIAS0 PAD(s) is out of Deep Power Down mode
#define PMC_IMPL_IO_PEX_CLK_C_DPD_STATUS_0_PEX_CLK2_BIAS0_SHIFT                 MK_SHIFT_CONST(1)
#define PMC_IMPL_IO_PEX_CLK_C_DPD_STATUS_0_PEX_CLK2_BIAS0_FIELD                 MK_FIELD_CONST(0x1, PMC_IMPL_IO_PEX_CLK_C_DPD_STATUS_0_PEX_CLK2_BIAS0_SHIFT)
#define PMC_IMPL_IO_PEX_CLK_C_DPD_STATUS_0_PEX_CLK2_BIAS0_RANGE                 1:1
#define PMC_IMPL_IO_PEX_CLK_C_DPD_STATUS_0_PEX_CLK2_BIAS0_MSB                   MK_SHIFT_CONST(1)
#define PMC_IMPL_IO_PEX_CLK_C_DPD_STATUS_0_PEX_CLK2_BIAS0_LSB                   MK_SHIFT_CONST(1)
#define PMC_IMPL_IO_PEX_CLK_C_DPD_STATUS_0_PEX_CLK2_BIAS0_WOFFSET                       0x0
#define PMC_IMPL_IO_PEX_CLK_C_DPD_STATUS_0_PEX_CLK2_BIAS0_DEFAULT                       MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_PEX_CLK_C_DPD_STATUS_0_PEX_CLK2_BIAS0_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_PEX_CLK_C_DPD_STATUS_0_PEX_CLK2_BIAS0_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_PEX_CLK_C_DPD_STATUS_0_PEX_CLK2_BIAS0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_PEX_CLK_C_DPD_STATUS_0_PEX_CLK2_BIAS0_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_PEX_CLK_C_DPD_STATUS_0_PEX_CLK2_BIAS0_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_PEX_CLK_C_DPD_STATUS_0_PEX_CLK2_BIAS0_OFF                   MK_ENUM_CONST(0)
#define PMC_IMPL_IO_PEX_CLK_C_DPD_STATUS_0_PEX_CLK2_BIAS0_ON                    MK_ENUM_CONST(1)

// On - PEX_CLK3 PAD(s) is in Deep Power Down mode, Off - PEX_CLK3 PAD(s) is out of Deep Power Down mode
#define PMC_IMPL_IO_PEX_CLK_C_DPD_STATUS_0_PEX_CLK3_SHIFT                       MK_SHIFT_CONST(2)
#define PMC_IMPL_IO_PEX_CLK_C_DPD_STATUS_0_PEX_CLK3_FIELD                       MK_FIELD_CONST(0x1, PMC_IMPL_IO_PEX_CLK_C_DPD_STATUS_0_PEX_CLK3_SHIFT)
#define PMC_IMPL_IO_PEX_CLK_C_DPD_STATUS_0_PEX_CLK3_RANGE                       2:2
#define PMC_IMPL_IO_PEX_CLK_C_DPD_STATUS_0_PEX_CLK3_MSB                 MK_SHIFT_CONST(2)
#define PMC_IMPL_IO_PEX_CLK_C_DPD_STATUS_0_PEX_CLK3_LSB                 MK_SHIFT_CONST(2)
#define PMC_IMPL_IO_PEX_CLK_C_DPD_STATUS_0_PEX_CLK3_WOFFSET                     0x0
#define PMC_IMPL_IO_PEX_CLK_C_DPD_STATUS_0_PEX_CLK3_DEFAULT                     MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_PEX_CLK_C_DPD_STATUS_0_PEX_CLK3_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_PEX_CLK_C_DPD_STATUS_0_PEX_CLK3_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_PEX_CLK_C_DPD_STATUS_0_PEX_CLK3_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_PEX_CLK_C_DPD_STATUS_0_PEX_CLK3_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_PEX_CLK_C_DPD_STATUS_0_PEX_CLK3_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_PEX_CLK_C_DPD_STATUS_0_PEX_CLK3_OFF                 MK_ENUM_CONST(0)
#define PMC_IMPL_IO_PEX_CLK_C_DPD_STATUS_0_PEX_CLK3_ON                  MK_ENUM_CONST(1)

// On - PEX_CLK3_BIAS1 PAD(s) is in Deep Power Down mode, Off - PEX_CLK3_BIAS1 PAD(s) is out of Deep Power Down mode
#define PMC_IMPL_IO_PEX_CLK_C_DPD_STATUS_0_PEX_CLK3_BIAS1_SHIFT                 MK_SHIFT_CONST(3)
#define PMC_IMPL_IO_PEX_CLK_C_DPD_STATUS_0_PEX_CLK3_BIAS1_FIELD                 MK_FIELD_CONST(0x1, PMC_IMPL_IO_PEX_CLK_C_DPD_STATUS_0_PEX_CLK3_BIAS1_SHIFT)
#define PMC_IMPL_IO_PEX_CLK_C_DPD_STATUS_0_PEX_CLK3_BIAS1_RANGE                 3:3
#define PMC_IMPL_IO_PEX_CLK_C_DPD_STATUS_0_PEX_CLK3_BIAS1_MSB                   MK_SHIFT_CONST(3)
#define PMC_IMPL_IO_PEX_CLK_C_DPD_STATUS_0_PEX_CLK3_BIAS1_LSB                   MK_SHIFT_CONST(3)
#define PMC_IMPL_IO_PEX_CLK_C_DPD_STATUS_0_PEX_CLK3_BIAS1_WOFFSET                       0x0
#define PMC_IMPL_IO_PEX_CLK_C_DPD_STATUS_0_PEX_CLK3_BIAS1_DEFAULT                       MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_PEX_CLK_C_DPD_STATUS_0_PEX_CLK3_BIAS1_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_PEX_CLK_C_DPD_STATUS_0_PEX_CLK3_BIAS1_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_PEX_CLK_C_DPD_STATUS_0_PEX_CLK3_BIAS1_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_PEX_CLK_C_DPD_STATUS_0_PEX_CLK3_BIAS1_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_PEX_CLK_C_DPD_STATUS_0_PEX_CLK3_BIAS1_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_PEX_CLK_C_DPD_STATUS_0_PEX_CLK3_BIAS1_OFF                   MK_ENUM_CONST(0)
#define PMC_IMPL_IO_PEX_CLK_C_DPD_STATUS_0_PEX_CLK3_BIAS1_ON                    MK_ENUM_CONST(1)


// Register PMC_IMPL_IO_PEX_CLK_A_DPD_REQ_0
#define PMC_IMPL_IO_PEX_CLK_A_DPD_REQ_0                 MK_ADDR_CONST(0xe0b0)
#define PMC_IMPL_IO_PEX_CLK_A_DPD_REQ_0_SECURE                  0x0
#define PMC_IMPL_IO_PEX_CLK_A_DPD_REQ_0_DUAL                    0x0
#define PMC_IMPL_IO_PEX_CLK_A_DPD_REQ_0_SCR                     IO_PEX_CLK_A_SCR_0
#define PMC_IMPL_IO_PEX_CLK_A_DPD_REQ_0_SCRREG                  PMC_IMPL_SCR_IO_PEX_CLK_A_SCR_0
#define PMC_IMPL_IO_PEX_CLK_A_DPD_REQ_0_WORD_COUNT                      0x1
#define PMC_IMPL_IO_PEX_CLK_A_DPD_REQ_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_PEX_CLK_A_DPD_REQ_0_RESET_MASK                      MK_MASK_CONST(0xc000000f)
#define PMC_IMPL_IO_PEX_CLK_A_DPD_REQ_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_PEX_CLK_A_DPD_REQ_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_PEX_CLK_A_DPD_REQ_0_READ_MASK                       MK_MASK_CONST(0xc000000f)
#define PMC_IMPL_IO_PEX_CLK_A_DPD_REQ_0_WRITE_MASK                      MK_MASK_CONST(0xc000000f)
// code of operation for all set bits
#define PMC_IMPL_IO_PEX_CLK_A_DPD_REQ_0_CODE_SHIFT                      MK_SHIFT_CONST(30)
#define PMC_IMPL_IO_PEX_CLK_A_DPD_REQ_0_CODE_FIELD                      MK_FIELD_CONST(0x3, PMC_IMPL_IO_PEX_CLK_A_DPD_REQ_0_CODE_SHIFT)
#define PMC_IMPL_IO_PEX_CLK_A_DPD_REQ_0_CODE_RANGE                      31:30
#define PMC_IMPL_IO_PEX_CLK_A_DPD_REQ_0_CODE_MSB                        MK_SHIFT_CONST(31)
#define PMC_IMPL_IO_PEX_CLK_A_DPD_REQ_0_CODE_LSB                        MK_SHIFT_CONST(30)
#define PMC_IMPL_IO_PEX_CLK_A_DPD_REQ_0_CODE_WOFFSET                    0x0
#define PMC_IMPL_IO_PEX_CLK_A_DPD_REQ_0_CODE_DEFAULT                    MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_PEX_CLK_A_DPD_REQ_0_CODE_DEFAULT_MASK                       MK_MASK_CONST(0x3)
#define PMC_IMPL_IO_PEX_CLK_A_DPD_REQ_0_CODE_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_PEX_CLK_A_DPD_REQ_0_CODE_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_PEX_CLK_A_DPD_REQ_0_CODE_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_PEX_CLK_A_DPD_REQ_0_CODE_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_PEX_CLK_A_DPD_REQ_0_CODE_IDLE                       MK_ENUM_CONST(0)
#define PMC_IMPL_IO_PEX_CLK_A_DPD_REQ_0_CODE_DPD_OFF                    MK_ENUM_CONST(1)
#define PMC_IMPL_IO_PEX_CLK_A_DPD_REQ_0_CODE_DPD_ON                     MK_ENUM_CONST(2)

// puts PEX_CLK0 PAD(s) in/out of Depp Power Down (DPD) mode
#define PMC_IMPL_IO_PEX_CLK_A_DPD_REQ_0_PEX_CLK0_SHIFT                  MK_SHIFT_CONST(0)
#define PMC_IMPL_IO_PEX_CLK_A_DPD_REQ_0_PEX_CLK0_FIELD                  MK_FIELD_CONST(0x1, PMC_IMPL_IO_PEX_CLK_A_DPD_REQ_0_PEX_CLK0_SHIFT)
#define PMC_IMPL_IO_PEX_CLK_A_DPD_REQ_0_PEX_CLK0_RANGE                  0:0
#define PMC_IMPL_IO_PEX_CLK_A_DPD_REQ_0_PEX_CLK0_MSB                    MK_SHIFT_CONST(0)
#define PMC_IMPL_IO_PEX_CLK_A_DPD_REQ_0_PEX_CLK0_LSB                    MK_SHIFT_CONST(0)
#define PMC_IMPL_IO_PEX_CLK_A_DPD_REQ_0_PEX_CLK0_WOFFSET                        0x0
#define PMC_IMPL_IO_PEX_CLK_A_DPD_REQ_0_PEX_CLK0_DEFAULT                        MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_PEX_CLK_A_DPD_REQ_0_PEX_CLK0_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_PEX_CLK_A_DPD_REQ_0_PEX_CLK0_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_PEX_CLK_A_DPD_REQ_0_PEX_CLK0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_PEX_CLK_A_DPD_REQ_0_PEX_CLK0_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_PEX_CLK_A_DPD_REQ_0_PEX_CLK0_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_PEX_CLK_A_DPD_REQ_0_PEX_CLK0_OFF                    MK_ENUM_CONST(0)
#define PMC_IMPL_IO_PEX_CLK_A_DPD_REQ_0_PEX_CLK0_ON                     MK_ENUM_CONST(1)

// puts PEX_CLK0_BIAS0 PAD(s) in/out of Depp Power Down (DPD) mode
#define PMC_IMPL_IO_PEX_CLK_A_DPD_REQ_0_PEX_CLK0_BIAS0_SHIFT                    MK_SHIFT_CONST(1)
#define PMC_IMPL_IO_PEX_CLK_A_DPD_REQ_0_PEX_CLK0_BIAS0_FIELD                    MK_FIELD_CONST(0x1, PMC_IMPL_IO_PEX_CLK_A_DPD_REQ_0_PEX_CLK0_BIAS0_SHIFT)
#define PMC_IMPL_IO_PEX_CLK_A_DPD_REQ_0_PEX_CLK0_BIAS0_RANGE                    1:1
#define PMC_IMPL_IO_PEX_CLK_A_DPD_REQ_0_PEX_CLK0_BIAS0_MSB                      MK_SHIFT_CONST(1)
#define PMC_IMPL_IO_PEX_CLK_A_DPD_REQ_0_PEX_CLK0_BIAS0_LSB                      MK_SHIFT_CONST(1)
#define PMC_IMPL_IO_PEX_CLK_A_DPD_REQ_0_PEX_CLK0_BIAS0_WOFFSET                  0x0
#define PMC_IMPL_IO_PEX_CLK_A_DPD_REQ_0_PEX_CLK0_BIAS0_DEFAULT                  MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_PEX_CLK_A_DPD_REQ_0_PEX_CLK0_BIAS0_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_PEX_CLK_A_DPD_REQ_0_PEX_CLK0_BIAS0_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_PEX_CLK_A_DPD_REQ_0_PEX_CLK0_BIAS0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_PEX_CLK_A_DPD_REQ_0_PEX_CLK0_BIAS0_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_PEX_CLK_A_DPD_REQ_0_PEX_CLK0_BIAS0_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_PEX_CLK_A_DPD_REQ_0_PEX_CLK0_BIAS0_OFF                      MK_ENUM_CONST(0)
#define PMC_IMPL_IO_PEX_CLK_A_DPD_REQ_0_PEX_CLK0_BIAS0_ON                       MK_ENUM_CONST(1)

// puts PEX_CLK1 PAD(s) in/out of Depp Power Down (DPD) mode
#define PMC_IMPL_IO_PEX_CLK_A_DPD_REQ_0_PEX_CLK1_SHIFT                  MK_SHIFT_CONST(2)
#define PMC_IMPL_IO_PEX_CLK_A_DPD_REQ_0_PEX_CLK1_FIELD                  MK_FIELD_CONST(0x1, PMC_IMPL_IO_PEX_CLK_A_DPD_REQ_0_PEX_CLK1_SHIFT)
#define PMC_IMPL_IO_PEX_CLK_A_DPD_REQ_0_PEX_CLK1_RANGE                  2:2
#define PMC_IMPL_IO_PEX_CLK_A_DPD_REQ_0_PEX_CLK1_MSB                    MK_SHIFT_CONST(2)
#define PMC_IMPL_IO_PEX_CLK_A_DPD_REQ_0_PEX_CLK1_LSB                    MK_SHIFT_CONST(2)
#define PMC_IMPL_IO_PEX_CLK_A_DPD_REQ_0_PEX_CLK1_WOFFSET                        0x0
#define PMC_IMPL_IO_PEX_CLK_A_DPD_REQ_0_PEX_CLK1_DEFAULT                        MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_PEX_CLK_A_DPD_REQ_0_PEX_CLK1_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_PEX_CLK_A_DPD_REQ_0_PEX_CLK1_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_PEX_CLK_A_DPD_REQ_0_PEX_CLK1_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_PEX_CLK_A_DPD_REQ_0_PEX_CLK1_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_PEX_CLK_A_DPD_REQ_0_PEX_CLK1_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_PEX_CLK_A_DPD_REQ_0_PEX_CLK1_OFF                    MK_ENUM_CONST(0)
#define PMC_IMPL_IO_PEX_CLK_A_DPD_REQ_0_PEX_CLK1_ON                     MK_ENUM_CONST(1)

// puts PEX_CLK1_BIAS1 PAD(s) in/out of Depp Power Down (DPD) mode
#define PMC_IMPL_IO_PEX_CLK_A_DPD_REQ_0_PEX_CLK1_BIAS1_SHIFT                    MK_SHIFT_CONST(3)
#define PMC_IMPL_IO_PEX_CLK_A_DPD_REQ_0_PEX_CLK1_BIAS1_FIELD                    MK_FIELD_CONST(0x1, PMC_IMPL_IO_PEX_CLK_A_DPD_REQ_0_PEX_CLK1_BIAS1_SHIFT)
#define PMC_IMPL_IO_PEX_CLK_A_DPD_REQ_0_PEX_CLK1_BIAS1_RANGE                    3:3
#define PMC_IMPL_IO_PEX_CLK_A_DPD_REQ_0_PEX_CLK1_BIAS1_MSB                      MK_SHIFT_CONST(3)
#define PMC_IMPL_IO_PEX_CLK_A_DPD_REQ_0_PEX_CLK1_BIAS1_LSB                      MK_SHIFT_CONST(3)
#define PMC_IMPL_IO_PEX_CLK_A_DPD_REQ_0_PEX_CLK1_BIAS1_WOFFSET                  0x0
#define PMC_IMPL_IO_PEX_CLK_A_DPD_REQ_0_PEX_CLK1_BIAS1_DEFAULT                  MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_PEX_CLK_A_DPD_REQ_0_PEX_CLK1_BIAS1_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_PEX_CLK_A_DPD_REQ_0_PEX_CLK1_BIAS1_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_PEX_CLK_A_DPD_REQ_0_PEX_CLK1_BIAS1_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_PEX_CLK_A_DPD_REQ_0_PEX_CLK1_BIAS1_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_PEX_CLK_A_DPD_REQ_0_PEX_CLK1_BIAS1_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_PEX_CLK_A_DPD_REQ_0_PEX_CLK1_BIAS1_OFF                      MK_ENUM_CONST(0)
#define PMC_IMPL_IO_PEX_CLK_A_DPD_REQ_0_PEX_CLK1_BIAS1_ON                       MK_ENUM_CONST(1)


// Register PMC_IMPL_IO_PEX_CLK_A_DPD_STATUS_0
#define PMC_IMPL_IO_PEX_CLK_A_DPD_STATUS_0                      MK_ADDR_CONST(0xe0b4)
#define PMC_IMPL_IO_PEX_CLK_A_DPD_STATUS_0_SECURE                       0x0
#define PMC_IMPL_IO_PEX_CLK_A_DPD_STATUS_0_DUAL                         0x0
#define PMC_IMPL_IO_PEX_CLK_A_DPD_STATUS_0_SCR                  IO_PEX_CLK_A_SCR_0
#define PMC_IMPL_IO_PEX_CLK_A_DPD_STATUS_0_SCRREG                       PMC_IMPL_SCR_IO_PEX_CLK_A_SCR_0
#define PMC_IMPL_IO_PEX_CLK_A_DPD_STATUS_0_WORD_COUNT                   0x1
#define PMC_IMPL_IO_PEX_CLK_A_DPD_STATUS_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_PEX_CLK_A_DPD_STATUS_0_RESET_MASK                   MK_MASK_CONST(0xf)
#define PMC_IMPL_IO_PEX_CLK_A_DPD_STATUS_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_PEX_CLK_A_DPD_STATUS_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_PEX_CLK_A_DPD_STATUS_0_READ_MASK                    MK_MASK_CONST(0xf)
#define PMC_IMPL_IO_PEX_CLK_A_DPD_STATUS_0_WRITE_MASK                   MK_MASK_CONST(0x0)
// On - PEX_CLK0 PAD(s) is in Deep Power Down mode, Off - PEX_CLK0 PAD(s) is out of Deep Power Down mode
#define PMC_IMPL_IO_PEX_CLK_A_DPD_STATUS_0_PEX_CLK0_SHIFT                       MK_SHIFT_CONST(0)
#define PMC_IMPL_IO_PEX_CLK_A_DPD_STATUS_0_PEX_CLK0_FIELD                       MK_FIELD_CONST(0x1, PMC_IMPL_IO_PEX_CLK_A_DPD_STATUS_0_PEX_CLK0_SHIFT)
#define PMC_IMPL_IO_PEX_CLK_A_DPD_STATUS_0_PEX_CLK0_RANGE                       0:0
#define PMC_IMPL_IO_PEX_CLK_A_DPD_STATUS_0_PEX_CLK0_MSB                 MK_SHIFT_CONST(0)
#define PMC_IMPL_IO_PEX_CLK_A_DPD_STATUS_0_PEX_CLK0_LSB                 MK_SHIFT_CONST(0)
#define PMC_IMPL_IO_PEX_CLK_A_DPD_STATUS_0_PEX_CLK0_WOFFSET                     0x0
#define PMC_IMPL_IO_PEX_CLK_A_DPD_STATUS_0_PEX_CLK0_DEFAULT                     MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_PEX_CLK_A_DPD_STATUS_0_PEX_CLK0_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_PEX_CLK_A_DPD_STATUS_0_PEX_CLK0_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_PEX_CLK_A_DPD_STATUS_0_PEX_CLK0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_PEX_CLK_A_DPD_STATUS_0_PEX_CLK0_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_PEX_CLK_A_DPD_STATUS_0_PEX_CLK0_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_PEX_CLK_A_DPD_STATUS_0_PEX_CLK0_OFF                 MK_ENUM_CONST(0)
#define PMC_IMPL_IO_PEX_CLK_A_DPD_STATUS_0_PEX_CLK0_ON                  MK_ENUM_CONST(1)

// On - PEX_CLK0_BIAS0 PAD(s) is in Deep Power Down mode, Off - PEX_CLK0_BIAS0 PAD(s) is out of Deep Power Down mode
#define PMC_IMPL_IO_PEX_CLK_A_DPD_STATUS_0_PEX_CLK0_BIAS0_SHIFT                 MK_SHIFT_CONST(1)
#define PMC_IMPL_IO_PEX_CLK_A_DPD_STATUS_0_PEX_CLK0_BIAS0_FIELD                 MK_FIELD_CONST(0x1, PMC_IMPL_IO_PEX_CLK_A_DPD_STATUS_0_PEX_CLK0_BIAS0_SHIFT)
#define PMC_IMPL_IO_PEX_CLK_A_DPD_STATUS_0_PEX_CLK0_BIAS0_RANGE                 1:1
#define PMC_IMPL_IO_PEX_CLK_A_DPD_STATUS_0_PEX_CLK0_BIAS0_MSB                   MK_SHIFT_CONST(1)
#define PMC_IMPL_IO_PEX_CLK_A_DPD_STATUS_0_PEX_CLK0_BIAS0_LSB                   MK_SHIFT_CONST(1)
#define PMC_IMPL_IO_PEX_CLK_A_DPD_STATUS_0_PEX_CLK0_BIAS0_WOFFSET                       0x0
#define PMC_IMPL_IO_PEX_CLK_A_DPD_STATUS_0_PEX_CLK0_BIAS0_DEFAULT                       MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_PEX_CLK_A_DPD_STATUS_0_PEX_CLK0_BIAS0_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_PEX_CLK_A_DPD_STATUS_0_PEX_CLK0_BIAS0_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_PEX_CLK_A_DPD_STATUS_0_PEX_CLK0_BIAS0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_PEX_CLK_A_DPD_STATUS_0_PEX_CLK0_BIAS0_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_PEX_CLK_A_DPD_STATUS_0_PEX_CLK0_BIAS0_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_PEX_CLK_A_DPD_STATUS_0_PEX_CLK0_BIAS0_OFF                   MK_ENUM_CONST(0)
#define PMC_IMPL_IO_PEX_CLK_A_DPD_STATUS_0_PEX_CLK0_BIAS0_ON                    MK_ENUM_CONST(1)

// On - PEX_CLK1 PAD(s) is in Deep Power Down mode, Off - PEX_CLK1 PAD(s) is out of Deep Power Down mode
#define PMC_IMPL_IO_PEX_CLK_A_DPD_STATUS_0_PEX_CLK1_SHIFT                       MK_SHIFT_CONST(2)
#define PMC_IMPL_IO_PEX_CLK_A_DPD_STATUS_0_PEX_CLK1_FIELD                       MK_FIELD_CONST(0x1, PMC_IMPL_IO_PEX_CLK_A_DPD_STATUS_0_PEX_CLK1_SHIFT)
#define PMC_IMPL_IO_PEX_CLK_A_DPD_STATUS_0_PEX_CLK1_RANGE                       2:2
#define PMC_IMPL_IO_PEX_CLK_A_DPD_STATUS_0_PEX_CLK1_MSB                 MK_SHIFT_CONST(2)
#define PMC_IMPL_IO_PEX_CLK_A_DPD_STATUS_0_PEX_CLK1_LSB                 MK_SHIFT_CONST(2)
#define PMC_IMPL_IO_PEX_CLK_A_DPD_STATUS_0_PEX_CLK1_WOFFSET                     0x0
#define PMC_IMPL_IO_PEX_CLK_A_DPD_STATUS_0_PEX_CLK1_DEFAULT                     MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_PEX_CLK_A_DPD_STATUS_0_PEX_CLK1_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_PEX_CLK_A_DPD_STATUS_0_PEX_CLK1_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_PEX_CLK_A_DPD_STATUS_0_PEX_CLK1_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_PEX_CLK_A_DPD_STATUS_0_PEX_CLK1_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_PEX_CLK_A_DPD_STATUS_0_PEX_CLK1_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_PEX_CLK_A_DPD_STATUS_0_PEX_CLK1_OFF                 MK_ENUM_CONST(0)
#define PMC_IMPL_IO_PEX_CLK_A_DPD_STATUS_0_PEX_CLK1_ON                  MK_ENUM_CONST(1)

// On - PEX_CLK1_BIAS1 PAD(s) is in Deep Power Down mode, Off - PEX_CLK1_BIAS1 PAD(s) is out of Deep Power Down mode
#define PMC_IMPL_IO_PEX_CLK_A_DPD_STATUS_0_PEX_CLK1_BIAS1_SHIFT                 MK_SHIFT_CONST(3)
#define PMC_IMPL_IO_PEX_CLK_A_DPD_STATUS_0_PEX_CLK1_BIAS1_FIELD                 MK_FIELD_CONST(0x1, PMC_IMPL_IO_PEX_CLK_A_DPD_STATUS_0_PEX_CLK1_BIAS1_SHIFT)
#define PMC_IMPL_IO_PEX_CLK_A_DPD_STATUS_0_PEX_CLK1_BIAS1_RANGE                 3:3
#define PMC_IMPL_IO_PEX_CLK_A_DPD_STATUS_0_PEX_CLK1_BIAS1_MSB                   MK_SHIFT_CONST(3)
#define PMC_IMPL_IO_PEX_CLK_A_DPD_STATUS_0_PEX_CLK1_BIAS1_LSB                   MK_SHIFT_CONST(3)
#define PMC_IMPL_IO_PEX_CLK_A_DPD_STATUS_0_PEX_CLK1_BIAS1_WOFFSET                       0x0
#define PMC_IMPL_IO_PEX_CLK_A_DPD_STATUS_0_PEX_CLK1_BIAS1_DEFAULT                       MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_PEX_CLK_A_DPD_STATUS_0_PEX_CLK1_BIAS1_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_PEX_CLK_A_DPD_STATUS_0_PEX_CLK1_BIAS1_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_PEX_CLK_A_DPD_STATUS_0_PEX_CLK1_BIAS1_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_PEX_CLK_A_DPD_STATUS_0_PEX_CLK1_BIAS1_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_PEX_CLK_A_DPD_STATUS_0_PEX_CLK1_BIAS1_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_PEX_CLK_A_DPD_STATUS_0_PEX_CLK1_BIAS1_OFF                   MK_ENUM_CONST(0)
#define PMC_IMPL_IO_PEX_CLK_A_DPD_STATUS_0_PEX_CLK1_BIAS1_ON                    MK_ENUM_CONST(1)


// Register PMC_IMPL_IO_PEX_CLK_B_DPD_REQ_0
#define PMC_IMPL_IO_PEX_CLK_B_DPD_REQ_0                 MK_ADDR_CONST(0xe0b8)
#define PMC_IMPL_IO_PEX_CLK_B_DPD_REQ_0_SECURE                  0x0
#define PMC_IMPL_IO_PEX_CLK_B_DPD_REQ_0_DUAL                    0x0
#define PMC_IMPL_IO_PEX_CLK_B_DPD_REQ_0_SCR                     IO_PEX_CLK_B_SCR_0
#define PMC_IMPL_IO_PEX_CLK_B_DPD_REQ_0_SCRREG                  PMC_IMPL_SCR_IO_PEX_CLK_B_SCR_0
#define PMC_IMPL_IO_PEX_CLK_B_DPD_REQ_0_WORD_COUNT                      0x1
#define PMC_IMPL_IO_PEX_CLK_B_DPD_REQ_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_PEX_CLK_B_DPD_REQ_0_RESET_MASK                      MK_MASK_CONST(0xc0000003)
#define PMC_IMPL_IO_PEX_CLK_B_DPD_REQ_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_PEX_CLK_B_DPD_REQ_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_PEX_CLK_B_DPD_REQ_0_READ_MASK                       MK_MASK_CONST(0xc0000003)
#define PMC_IMPL_IO_PEX_CLK_B_DPD_REQ_0_WRITE_MASK                      MK_MASK_CONST(0xc0000003)
// code of operation for all set bits
#define PMC_IMPL_IO_PEX_CLK_B_DPD_REQ_0_CODE_SHIFT                      MK_SHIFT_CONST(30)
#define PMC_IMPL_IO_PEX_CLK_B_DPD_REQ_0_CODE_FIELD                      MK_FIELD_CONST(0x3, PMC_IMPL_IO_PEX_CLK_B_DPD_REQ_0_CODE_SHIFT)
#define PMC_IMPL_IO_PEX_CLK_B_DPD_REQ_0_CODE_RANGE                      31:30
#define PMC_IMPL_IO_PEX_CLK_B_DPD_REQ_0_CODE_MSB                        MK_SHIFT_CONST(31)
#define PMC_IMPL_IO_PEX_CLK_B_DPD_REQ_0_CODE_LSB                        MK_SHIFT_CONST(30)
#define PMC_IMPL_IO_PEX_CLK_B_DPD_REQ_0_CODE_WOFFSET                    0x0
#define PMC_IMPL_IO_PEX_CLK_B_DPD_REQ_0_CODE_DEFAULT                    MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_PEX_CLK_B_DPD_REQ_0_CODE_DEFAULT_MASK                       MK_MASK_CONST(0x3)
#define PMC_IMPL_IO_PEX_CLK_B_DPD_REQ_0_CODE_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_PEX_CLK_B_DPD_REQ_0_CODE_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_PEX_CLK_B_DPD_REQ_0_CODE_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_PEX_CLK_B_DPD_REQ_0_CODE_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_PEX_CLK_B_DPD_REQ_0_CODE_IDLE                       MK_ENUM_CONST(0)
#define PMC_IMPL_IO_PEX_CLK_B_DPD_REQ_0_CODE_DPD_OFF                    MK_ENUM_CONST(1)
#define PMC_IMPL_IO_PEX_CLK_B_DPD_REQ_0_CODE_DPD_ON                     MK_ENUM_CONST(2)

// puts PEX_CLK4 PAD(s) in/out of Depp Power Down (DPD) mode
#define PMC_IMPL_IO_PEX_CLK_B_DPD_REQ_0_PEX_CLK4_SHIFT                  MK_SHIFT_CONST(0)
#define PMC_IMPL_IO_PEX_CLK_B_DPD_REQ_0_PEX_CLK4_FIELD                  MK_FIELD_CONST(0x1, PMC_IMPL_IO_PEX_CLK_B_DPD_REQ_0_PEX_CLK4_SHIFT)
#define PMC_IMPL_IO_PEX_CLK_B_DPD_REQ_0_PEX_CLK4_RANGE                  0:0
#define PMC_IMPL_IO_PEX_CLK_B_DPD_REQ_0_PEX_CLK4_MSB                    MK_SHIFT_CONST(0)
#define PMC_IMPL_IO_PEX_CLK_B_DPD_REQ_0_PEX_CLK4_LSB                    MK_SHIFT_CONST(0)
#define PMC_IMPL_IO_PEX_CLK_B_DPD_REQ_0_PEX_CLK4_WOFFSET                        0x0
#define PMC_IMPL_IO_PEX_CLK_B_DPD_REQ_0_PEX_CLK4_DEFAULT                        MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_PEX_CLK_B_DPD_REQ_0_PEX_CLK4_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_PEX_CLK_B_DPD_REQ_0_PEX_CLK4_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_PEX_CLK_B_DPD_REQ_0_PEX_CLK4_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_PEX_CLK_B_DPD_REQ_0_PEX_CLK4_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_PEX_CLK_B_DPD_REQ_0_PEX_CLK4_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_PEX_CLK_B_DPD_REQ_0_PEX_CLK4_OFF                    MK_ENUM_CONST(0)
#define PMC_IMPL_IO_PEX_CLK_B_DPD_REQ_0_PEX_CLK4_ON                     MK_ENUM_CONST(1)

// puts PEX_CLK4_BIAS PAD(s) in/out of Depp Power Down (DPD) mode
#define PMC_IMPL_IO_PEX_CLK_B_DPD_REQ_0_PEX_CLK4_BIAS_SHIFT                     MK_SHIFT_CONST(1)
#define PMC_IMPL_IO_PEX_CLK_B_DPD_REQ_0_PEX_CLK4_BIAS_FIELD                     MK_FIELD_CONST(0x1, PMC_IMPL_IO_PEX_CLK_B_DPD_REQ_0_PEX_CLK4_BIAS_SHIFT)
#define PMC_IMPL_IO_PEX_CLK_B_DPD_REQ_0_PEX_CLK4_BIAS_RANGE                     1:1
#define PMC_IMPL_IO_PEX_CLK_B_DPD_REQ_0_PEX_CLK4_BIAS_MSB                       MK_SHIFT_CONST(1)
#define PMC_IMPL_IO_PEX_CLK_B_DPD_REQ_0_PEX_CLK4_BIAS_LSB                       MK_SHIFT_CONST(1)
#define PMC_IMPL_IO_PEX_CLK_B_DPD_REQ_0_PEX_CLK4_BIAS_WOFFSET                   0x0
#define PMC_IMPL_IO_PEX_CLK_B_DPD_REQ_0_PEX_CLK4_BIAS_DEFAULT                   MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_PEX_CLK_B_DPD_REQ_0_PEX_CLK4_BIAS_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_PEX_CLK_B_DPD_REQ_0_PEX_CLK4_BIAS_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_PEX_CLK_B_DPD_REQ_0_PEX_CLK4_BIAS_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_PEX_CLK_B_DPD_REQ_0_PEX_CLK4_BIAS_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_PEX_CLK_B_DPD_REQ_0_PEX_CLK4_BIAS_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_PEX_CLK_B_DPD_REQ_0_PEX_CLK4_BIAS_OFF                       MK_ENUM_CONST(0)
#define PMC_IMPL_IO_PEX_CLK_B_DPD_REQ_0_PEX_CLK4_BIAS_ON                        MK_ENUM_CONST(1)


// Register PMC_IMPL_IO_PEX_CLK_B_DPD_STATUS_0
#define PMC_IMPL_IO_PEX_CLK_B_DPD_STATUS_0                      MK_ADDR_CONST(0xe0bc)
#define PMC_IMPL_IO_PEX_CLK_B_DPD_STATUS_0_SECURE                       0x0
#define PMC_IMPL_IO_PEX_CLK_B_DPD_STATUS_0_DUAL                         0x0
#define PMC_IMPL_IO_PEX_CLK_B_DPD_STATUS_0_SCR                  IO_PEX_CLK_B_SCR_0
#define PMC_IMPL_IO_PEX_CLK_B_DPD_STATUS_0_SCRREG                       PMC_IMPL_SCR_IO_PEX_CLK_B_SCR_0
#define PMC_IMPL_IO_PEX_CLK_B_DPD_STATUS_0_WORD_COUNT                   0x1
#define PMC_IMPL_IO_PEX_CLK_B_DPD_STATUS_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_PEX_CLK_B_DPD_STATUS_0_RESET_MASK                   MK_MASK_CONST(0x3)
#define PMC_IMPL_IO_PEX_CLK_B_DPD_STATUS_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_PEX_CLK_B_DPD_STATUS_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_PEX_CLK_B_DPD_STATUS_0_READ_MASK                    MK_MASK_CONST(0x3)
#define PMC_IMPL_IO_PEX_CLK_B_DPD_STATUS_0_WRITE_MASK                   MK_MASK_CONST(0x0)
// On - PEX_CLK4 PAD(s) is in Deep Power Down mode, Off - PEX_CLK4 PAD(s) is out of Deep Power Down mode
#define PMC_IMPL_IO_PEX_CLK_B_DPD_STATUS_0_PEX_CLK4_SHIFT                       MK_SHIFT_CONST(0)
#define PMC_IMPL_IO_PEX_CLK_B_DPD_STATUS_0_PEX_CLK4_FIELD                       MK_FIELD_CONST(0x1, PMC_IMPL_IO_PEX_CLK_B_DPD_STATUS_0_PEX_CLK4_SHIFT)
#define PMC_IMPL_IO_PEX_CLK_B_DPD_STATUS_0_PEX_CLK4_RANGE                       0:0
#define PMC_IMPL_IO_PEX_CLK_B_DPD_STATUS_0_PEX_CLK4_MSB                 MK_SHIFT_CONST(0)
#define PMC_IMPL_IO_PEX_CLK_B_DPD_STATUS_0_PEX_CLK4_LSB                 MK_SHIFT_CONST(0)
#define PMC_IMPL_IO_PEX_CLK_B_DPD_STATUS_0_PEX_CLK4_WOFFSET                     0x0
#define PMC_IMPL_IO_PEX_CLK_B_DPD_STATUS_0_PEX_CLK4_DEFAULT                     MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_PEX_CLK_B_DPD_STATUS_0_PEX_CLK4_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_PEX_CLK_B_DPD_STATUS_0_PEX_CLK4_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_PEX_CLK_B_DPD_STATUS_0_PEX_CLK4_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_PEX_CLK_B_DPD_STATUS_0_PEX_CLK4_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_PEX_CLK_B_DPD_STATUS_0_PEX_CLK4_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_PEX_CLK_B_DPD_STATUS_0_PEX_CLK4_OFF                 MK_ENUM_CONST(0)
#define PMC_IMPL_IO_PEX_CLK_B_DPD_STATUS_0_PEX_CLK4_ON                  MK_ENUM_CONST(1)

// On - PEX_CLK4_BIAS PAD(s) is in Deep Power Down mode, Off - PEX_CLK4_BIAS PAD(s) is out of Deep Power Down mode
#define PMC_IMPL_IO_PEX_CLK_B_DPD_STATUS_0_PEX_CLK4_BIAS_SHIFT                  MK_SHIFT_CONST(1)
#define PMC_IMPL_IO_PEX_CLK_B_DPD_STATUS_0_PEX_CLK4_BIAS_FIELD                  MK_FIELD_CONST(0x1, PMC_IMPL_IO_PEX_CLK_B_DPD_STATUS_0_PEX_CLK4_BIAS_SHIFT)
#define PMC_IMPL_IO_PEX_CLK_B_DPD_STATUS_0_PEX_CLK4_BIAS_RANGE                  1:1
#define PMC_IMPL_IO_PEX_CLK_B_DPD_STATUS_0_PEX_CLK4_BIAS_MSB                    MK_SHIFT_CONST(1)
#define PMC_IMPL_IO_PEX_CLK_B_DPD_STATUS_0_PEX_CLK4_BIAS_LSB                    MK_SHIFT_CONST(1)
#define PMC_IMPL_IO_PEX_CLK_B_DPD_STATUS_0_PEX_CLK4_BIAS_WOFFSET                        0x0
#define PMC_IMPL_IO_PEX_CLK_B_DPD_STATUS_0_PEX_CLK4_BIAS_DEFAULT                        MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_PEX_CLK_B_DPD_STATUS_0_PEX_CLK4_BIAS_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_PEX_CLK_B_DPD_STATUS_0_PEX_CLK4_BIAS_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_PEX_CLK_B_DPD_STATUS_0_PEX_CLK4_BIAS_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_PEX_CLK_B_DPD_STATUS_0_PEX_CLK4_BIAS_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_PEX_CLK_B_DPD_STATUS_0_PEX_CLK4_BIAS_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_PEX_CLK_B_DPD_STATUS_0_PEX_CLK4_BIAS_OFF                    MK_ENUM_CONST(0)
#define PMC_IMPL_IO_PEX_CLK_B_DPD_STATUS_0_PEX_CLK4_BIAS_ON                     MK_ENUM_CONST(1)


// Register PMC_IMPL_IO_CSI_DPD_REQ_0
#define PMC_IMPL_IO_CSI_DPD_REQ_0                       MK_ADDR_CONST(0xe0c0)
#define PMC_IMPL_IO_CSI_DPD_REQ_0_SECURE                        0x0
#define PMC_IMPL_IO_CSI_DPD_REQ_0_DUAL                  0x0
#define PMC_IMPL_IO_CSI_DPD_REQ_0_SCR                   IO_CSI_SCR_0
#define PMC_IMPL_IO_CSI_DPD_REQ_0_SCRREG                        PMC_IMPL_SCR_IO_CSI_SCR_0
#define PMC_IMPL_IO_CSI_DPD_REQ_0_WORD_COUNT                    0x1
#define PMC_IMPL_IO_CSI_DPD_REQ_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_CSI_DPD_REQ_0_RESET_MASK                    MK_MASK_CONST(0xc00003ff)
#define PMC_IMPL_IO_CSI_DPD_REQ_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_CSI_DPD_REQ_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_CSI_DPD_REQ_0_READ_MASK                     MK_MASK_CONST(0xc00003ff)
#define PMC_IMPL_IO_CSI_DPD_REQ_0_WRITE_MASK                    MK_MASK_CONST(0xc00003ff)
// code of operation for all set bits
#define PMC_IMPL_IO_CSI_DPD_REQ_0_CODE_SHIFT                    MK_SHIFT_CONST(30)
#define PMC_IMPL_IO_CSI_DPD_REQ_0_CODE_FIELD                    MK_FIELD_CONST(0x3, PMC_IMPL_IO_CSI_DPD_REQ_0_CODE_SHIFT)
#define PMC_IMPL_IO_CSI_DPD_REQ_0_CODE_RANGE                    31:30
#define PMC_IMPL_IO_CSI_DPD_REQ_0_CODE_MSB                      MK_SHIFT_CONST(31)
#define PMC_IMPL_IO_CSI_DPD_REQ_0_CODE_LSB                      MK_SHIFT_CONST(30)
#define PMC_IMPL_IO_CSI_DPD_REQ_0_CODE_WOFFSET                  0x0
#define PMC_IMPL_IO_CSI_DPD_REQ_0_CODE_DEFAULT                  MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_CSI_DPD_REQ_0_CODE_DEFAULT_MASK                     MK_MASK_CONST(0x3)
#define PMC_IMPL_IO_CSI_DPD_REQ_0_CODE_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_CSI_DPD_REQ_0_CODE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_CSI_DPD_REQ_0_CODE_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_CSI_DPD_REQ_0_CODE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_CSI_DPD_REQ_0_CODE_IDLE                     MK_ENUM_CONST(0)
#define PMC_IMPL_IO_CSI_DPD_REQ_0_CODE_DPD_OFF                  MK_ENUM_CONST(1)
#define PMC_IMPL_IO_CSI_DPD_REQ_0_CODE_DPD_ON                   MK_ENUM_CONST(2)

// puts CSI_A PAD(s) in/out of Depp Power Down (DPD) mode
#define PMC_IMPL_IO_CSI_DPD_REQ_0_CSI_A_SHIFT                   MK_SHIFT_CONST(0)
#define PMC_IMPL_IO_CSI_DPD_REQ_0_CSI_A_FIELD                   MK_FIELD_CONST(0x1, PMC_IMPL_IO_CSI_DPD_REQ_0_CSI_A_SHIFT)
#define PMC_IMPL_IO_CSI_DPD_REQ_0_CSI_A_RANGE                   0:0
#define PMC_IMPL_IO_CSI_DPD_REQ_0_CSI_A_MSB                     MK_SHIFT_CONST(0)
#define PMC_IMPL_IO_CSI_DPD_REQ_0_CSI_A_LSB                     MK_SHIFT_CONST(0)
#define PMC_IMPL_IO_CSI_DPD_REQ_0_CSI_A_WOFFSET                 0x0
#define PMC_IMPL_IO_CSI_DPD_REQ_0_CSI_A_DEFAULT                 MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_CSI_DPD_REQ_0_CSI_A_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_CSI_DPD_REQ_0_CSI_A_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_CSI_DPD_REQ_0_CSI_A_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_CSI_DPD_REQ_0_CSI_A_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_CSI_DPD_REQ_0_CSI_A_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_CSI_DPD_REQ_0_CSI_A_OFF                     MK_ENUM_CONST(0)
#define PMC_IMPL_IO_CSI_DPD_REQ_0_CSI_A_ON                      MK_ENUM_CONST(1)

// puts CSI_B PAD(s) in/out of Depp Power Down (DPD) mode
#define PMC_IMPL_IO_CSI_DPD_REQ_0_CSI_B_SHIFT                   MK_SHIFT_CONST(1)
#define PMC_IMPL_IO_CSI_DPD_REQ_0_CSI_B_FIELD                   MK_FIELD_CONST(0x1, PMC_IMPL_IO_CSI_DPD_REQ_0_CSI_B_SHIFT)
#define PMC_IMPL_IO_CSI_DPD_REQ_0_CSI_B_RANGE                   1:1
#define PMC_IMPL_IO_CSI_DPD_REQ_0_CSI_B_MSB                     MK_SHIFT_CONST(1)
#define PMC_IMPL_IO_CSI_DPD_REQ_0_CSI_B_LSB                     MK_SHIFT_CONST(1)
#define PMC_IMPL_IO_CSI_DPD_REQ_0_CSI_B_WOFFSET                 0x0
#define PMC_IMPL_IO_CSI_DPD_REQ_0_CSI_B_DEFAULT                 MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_CSI_DPD_REQ_0_CSI_B_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_CSI_DPD_REQ_0_CSI_B_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_CSI_DPD_REQ_0_CSI_B_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_CSI_DPD_REQ_0_CSI_B_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_CSI_DPD_REQ_0_CSI_B_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_CSI_DPD_REQ_0_CSI_B_OFF                     MK_ENUM_CONST(0)
#define PMC_IMPL_IO_CSI_DPD_REQ_0_CSI_B_ON                      MK_ENUM_CONST(1)

// puts CSI_C PAD(s) in/out of Depp Power Down (DPD) mode
#define PMC_IMPL_IO_CSI_DPD_REQ_0_CSI_C_SHIFT                   MK_SHIFT_CONST(2)
#define PMC_IMPL_IO_CSI_DPD_REQ_0_CSI_C_FIELD                   MK_FIELD_CONST(0x1, PMC_IMPL_IO_CSI_DPD_REQ_0_CSI_C_SHIFT)
#define PMC_IMPL_IO_CSI_DPD_REQ_0_CSI_C_RANGE                   2:2
#define PMC_IMPL_IO_CSI_DPD_REQ_0_CSI_C_MSB                     MK_SHIFT_CONST(2)
#define PMC_IMPL_IO_CSI_DPD_REQ_0_CSI_C_LSB                     MK_SHIFT_CONST(2)
#define PMC_IMPL_IO_CSI_DPD_REQ_0_CSI_C_WOFFSET                 0x0
#define PMC_IMPL_IO_CSI_DPD_REQ_0_CSI_C_DEFAULT                 MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_CSI_DPD_REQ_0_CSI_C_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_CSI_DPD_REQ_0_CSI_C_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_CSI_DPD_REQ_0_CSI_C_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_CSI_DPD_REQ_0_CSI_C_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_CSI_DPD_REQ_0_CSI_C_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_CSI_DPD_REQ_0_CSI_C_OFF                     MK_ENUM_CONST(0)
#define PMC_IMPL_IO_CSI_DPD_REQ_0_CSI_C_ON                      MK_ENUM_CONST(1)

// puts CSI_D PAD(s) in/out of Depp Power Down (DPD) mode
#define PMC_IMPL_IO_CSI_DPD_REQ_0_CSI_D_SHIFT                   MK_SHIFT_CONST(3)
#define PMC_IMPL_IO_CSI_DPD_REQ_0_CSI_D_FIELD                   MK_FIELD_CONST(0x1, PMC_IMPL_IO_CSI_DPD_REQ_0_CSI_D_SHIFT)
#define PMC_IMPL_IO_CSI_DPD_REQ_0_CSI_D_RANGE                   3:3
#define PMC_IMPL_IO_CSI_DPD_REQ_0_CSI_D_MSB                     MK_SHIFT_CONST(3)
#define PMC_IMPL_IO_CSI_DPD_REQ_0_CSI_D_LSB                     MK_SHIFT_CONST(3)
#define PMC_IMPL_IO_CSI_DPD_REQ_0_CSI_D_WOFFSET                 0x0
#define PMC_IMPL_IO_CSI_DPD_REQ_0_CSI_D_DEFAULT                 MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_CSI_DPD_REQ_0_CSI_D_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_CSI_DPD_REQ_0_CSI_D_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_CSI_DPD_REQ_0_CSI_D_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_CSI_DPD_REQ_0_CSI_D_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_CSI_DPD_REQ_0_CSI_D_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_CSI_DPD_REQ_0_CSI_D_OFF                     MK_ENUM_CONST(0)
#define PMC_IMPL_IO_CSI_DPD_REQ_0_CSI_D_ON                      MK_ENUM_CONST(1)

// puts CSI_E PAD(s) in/out of Depp Power Down (DPD) mode
#define PMC_IMPL_IO_CSI_DPD_REQ_0_CSI_E_SHIFT                   MK_SHIFT_CONST(4)
#define PMC_IMPL_IO_CSI_DPD_REQ_0_CSI_E_FIELD                   MK_FIELD_CONST(0x1, PMC_IMPL_IO_CSI_DPD_REQ_0_CSI_E_SHIFT)
#define PMC_IMPL_IO_CSI_DPD_REQ_0_CSI_E_RANGE                   4:4
#define PMC_IMPL_IO_CSI_DPD_REQ_0_CSI_E_MSB                     MK_SHIFT_CONST(4)
#define PMC_IMPL_IO_CSI_DPD_REQ_0_CSI_E_LSB                     MK_SHIFT_CONST(4)
#define PMC_IMPL_IO_CSI_DPD_REQ_0_CSI_E_WOFFSET                 0x0
#define PMC_IMPL_IO_CSI_DPD_REQ_0_CSI_E_DEFAULT                 MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_CSI_DPD_REQ_0_CSI_E_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_CSI_DPD_REQ_0_CSI_E_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_CSI_DPD_REQ_0_CSI_E_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_CSI_DPD_REQ_0_CSI_E_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_CSI_DPD_REQ_0_CSI_E_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_CSI_DPD_REQ_0_CSI_E_OFF                     MK_ENUM_CONST(0)
#define PMC_IMPL_IO_CSI_DPD_REQ_0_CSI_E_ON                      MK_ENUM_CONST(1)

// puts CSI_F PAD(s) in/out of Depp Power Down (DPD) mode
#define PMC_IMPL_IO_CSI_DPD_REQ_0_CSI_F_SHIFT                   MK_SHIFT_CONST(5)
#define PMC_IMPL_IO_CSI_DPD_REQ_0_CSI_F_FIELD                   MK_FIELD_CONST(0x1, PMC_IMPL_IO_CSI_DPD_REQ_0_CSI_F_SHIFT)
#define PMC_IMPL_IO_CSI_DPD_REQ_0_CSI_F_RANGE                   5:5
#define PMC_IMPL_IO_CSI_DPD_REQ_0_CSI_F_MSB                     MK_SHIFT_CONST(5)
#define PMC_IMPL_IO_CSI_DPD_REQ_0_CSI_F_LSB                     MK_SHIFT_CONST(5)
#define PMC_IMPL_IO_CSI_DPD_REQ_0_CSI_F_WOFFSET                 0x0
#define PMC_IMPL_IO_CSI_DPD_REQ_0_CSI_F_DEFAULT                 MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_CSI_DPD_REQ_0_CSI_F_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_CSI_DPD_REQ_0_CSI_F_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_CSI_DPD_REQ_0_CSI_F_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_CSI_DPD_REQ_0_CSI_F_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_CSI_DPD_REQ_0_CSI_F_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_CSI_DPD_REQ_0_CSI_F_OFF                     MK_ENUM_CONST(0)
#define PMC_IMPL_IO_CSI_DPD_REQ_0_CSI_F_ON                      MK_ENUM_CONST(1)

// puts CSI_G PAD(s) in/out of Depp Power Down (DPD) mode
#define PMC_IMPL_IO_CSI_DPD_REQ_0_CSI_G_SHIFT                   MK_SHIFT_CONST(6)
#define PMC_IMPL_IO_CSI_DPD_REQ_0_CSI_G_FIELD                   MK_FIELD_CONST(0x1, PMC_IMPL_IO_CSI_DPD_REQ_0_CSI_G_SHIFT)
#define PMC_IMPL_IO_CSI_DPD_REQ_0_CSI_G_RANGE                   6:6
#define PMC_IMPL_IO_CSI_DPD_REQ_0_CSI_G_MSB                     MK_SHIFT_CONST(6)
#define PMC_IMPL_IO_CSI_DPD_REQ_0_CSI_G_LSB                     MK_SHIFT_CONST(6)
#define PMC_IMPL_IO_CSI_DPD_REQ_0_CSI_G_WOFFSET                 0x0
#define PMC_IMPL_IO_CSI_DPD_REQ_0_CSI_G_DEFAULT                 MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_CSI_DPD_REQ_0_CSI_G_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_CSI_DPD_REQ_0_CSI_G_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_CSI_DPD_REQ_0_CSI_G_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_CSI_DPD_REQ_0_CSI_G_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_CSI_DPD_REQ_0_CSI_G_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_CSI_DPD_REQ_0_CSI_G_OFF                     MK_ENUM_CONST(0)
#define PMC_IMPL_IO_CSI_DPD_REQ_0_CSI_G_ON                      MK_ENUM_CONST(1)

// puts CSI_H PAD(s) in/out of Depp Power Down (DPD) mode
#define PMC_IMPL_IO_CSI_DPD_REQ_0_CSI_H_SHIFT                   MK_SHIFT_CONST(7)
#define PMC_IMPL_IO_CSI_DPD_REQ_0_CSI_H_FIELD                   MK_FIELD_CONST(0x1, PMC_IMPL_IO_CSI_DPD_REQ_0_CSI_H_SHIFT)
#define PMC_IMPL_IO_CSI_DPD_REQ_0_CSI_H_RANGE                   7:7
#define PMC_IMPL_IO_CSI_DPD_REQ_0_CSI_H_MSB                     MK_SHIFT_CONST(7)
#define PMC_IMPL_IO_CSI_DPD_REQ_0_CSI_H_LSB                     MK_SHIFT_CONST(7)
#define PMC_IMPL_IO_CSI_DPD_REQ_0_CSI_H_WOFFSET                 0x0
#define PMC_IMPL_IO_CSI_DPD_REQ_0_CSI_H_DEFAULT                 MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_CSI_DPD_REQ_0_CSI_H_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_CSI_DPD_REQ_0_CSI_H_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_CSI_DPD_REQ_0_CSI_H_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_CSI_DPD_REQ_0_CSI_H_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_CSI_DPD_REQ_0_CSI_H_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_CSI_DPD_REQ_0_CSI_H_OFF                     MK_ENUM_CONST(0)
#define PMC_IMPL_IO_CSI_DPD_REQ_0_CSI_H_ON                      MK_ENUM_CONST(1)

// puts PHY_BIAS PAD(s) in/out of Depp Power Down (DPD) mode
#define PMC_IMPL_IO_CSI_DPD_REQ_0_PHY_BIAS_SHIFT                        MK_SHIFT_CONST(8)
#define PMC_IMPL_IO_CSI_DPD_REQ_0_PHY_BIAS_FIELD                        MK_FIELD_CONST(0x1, PMC_IMPL_IO_CSI_DPD_REQ_0_PHY_BIAS_SHIFT)
#define PMC_IMPL_IO_CSI_DPD_REQ_0_PHY_BIAS_RANGE                        8:8
#define PMC_IMPL_IO_CSI_DPD_REQ_0_PHY_BIAS_MSB                  MK_SHIFT_CONST(8)
#define PMC_IMPL_IO_CSI_DPD_REQ_0_PHY_BIAS_LSB                  MK_SHIFT_CONST(8)
#define PMC_IMPL_IO_CSI_DPD_REQ_0_PHY_BIAS_WOFFSET                      0x0
#define PMC_IMPL_IO_CSI_DPD_REQ_0_PHY_BIAS_DEFAULT                      MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_CSI_DPD_REQ_0_PHY_BIAS_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_CSI_DPD_REQ_0_PHY_BIAS_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_CSI_DPD_REQ_0_PHY_BIAS_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_CSI_DPD_REQ_0_PHY_BIAS_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_CSI_DPD_REQ_0_PHY_BIAS_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_CSI_DPD_REQ_0_PHY_BIAS_OFF                  MK_ENUM_CONST(0)
#define PMC_IMPL_IO_CSI_DPD_REQ_0_PHY_BIAS_ON                   MK_ENUM_CONST(1)

// puts PHY_PLL PAD(s) in/out of Depp Power Down (DPD) mode
#define PMC_IMPL_IO_CSI_DPD_REQ_0_PHY_PLL_SHIFT                 MK_SHIFT_CONST(9)
#define PMC_IMPL_IO_CSI_DPD_REQ_0_PHY_PLL_FIELD                 MK_FIELD_CONST(0x1, PMC_IMPL_IO_CSI_DPD_REQ_0_PHY_PLL_SHIFT)
#define PMC_IMPL_IO_CSI_DPD_REQ_0_PHY_PLL_RANGE                 9:9
#define PMC_IMPL_IO_CSI_DPD_REQ_0_PHY_PLL_MSB                   MK_SHIFT_CONST(9)
#define PMC_IMPL_IO_CSI_DPD_REQ_0_PHY_PLL_LSB                   MK_SHIFT_CONST(9)
#define PMC_IMPL_IO_CSI_DPD_REQ_0_PHY_PLL_WOFFSET                       0x0
#define PMC_IMPL_IO_CSI_DPD_REQ_0_PHY_PLL_DEFAULT                       MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_CSI_DPD_REQ_0_PHY_PLL_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_CSI_DPD_REQ_0_PHY_PLL_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_CSI_DPD_REQ_0_PHY_PLL_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_CSI_DPD_REQ_0_PHY_PLL_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_CSI_DPD_REQ_0_PHY_PLL_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_CSI_DPD_REQ_0_PHY_PLL_OFF                   MK_ENUM_CONST(0)
#define PMC_IMPL_IO_CSI_DPD_REQ_0_PHY_PLL_ON                    MK_ENUM_CONST(1)


// Register PMC_IMPL_IO_CSI_DPD_STATUS_0
#define PMC_IMPL_IO_CSI_DPD_STATUS_0                    MK_ADDR_CONST(0xe0c4)
#define PMC_IMPL_IO_CSI_DPD_STATUS_0_SECURE                     0x0
#define PMC_IMPL_IO_CSI_DPD_STATUS_0_DUAL                       0x0
#define PMC_IMPL_IO_CSI_DPD_STATUS_0_SCR                        IO_CSI_SCR_0
#define PMC_IMPL_IO_CSI_DPD_STATUS_0_SCRREG                     PMC_IMPL_SCR_IO_CSI_SCR_0
#define PMC_IMPL_IO_CSI_DPD_STATUS_0_WORD_COUNT                         0x1
#define PMC_IMPL_IO_CSI_DPD_STATUS_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_CSI_DPD_STATUS_0_RESET_MASK                         MK_MASK_CONST(0x3ff)
#define PMC_IMPL_IO_CSI_DPD_STATUS_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_CSI_DPD_STATUS_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_CSI_DPD_STATUS_0_READ_MASK                  MK_MASK_CONST(0x3ff)
#define PMC_IMPL_IO_CSI_DPD_STATUS_0_WRITE_MASK                         MK_MASK_CONST(0x0)
// On - CSI_A PAD(s) is in Deep Power Down mode, Off - CSI_A PAD(s) is out of Deep Power Down mode
#define PMC_IMPL_IO_CSI_DPD_STATUS_0_CSI_A_SHIFT                        MK_SHIFT_CONST(0)
#define PMC_IMPL_IO_CSI_DPD_STATUS_0_CSI_A_FIELD                        MK_FIELD_CONST(0x1, PMC_IMPL_IO_CSI_DPD_STATUS_0_CSI_A_SHIFT)
#define PMC_IMPL_IO_CSI_DPD_STATUS_0_CSI_A_RANGE                        0:0
#define PMC_IMPL_IO_CSI_DPD_STATUS_0_CSI_A_MSB                  MK_SHIFT_CONST(0)
#define PMC_IMPL_IO_CSI_DPD_STATUS_0_CSI_A_LSB                  MK_SHIFT_CONST(0)
#define PMC_IMPL_IO_CSI_DPD_STATUS_0_CSI_A_WOFFSET                      0x0
#define PMC_IMPL_IO_CSI_DPD_STATUS_0_CSI_A_DEFAULT                      MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_CSI_DPD_STATUS_0_CSI_A_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_CSI_DPD_STATUS_0_CSI_A_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_CSI_DPD_STATUS_0_CSI_A_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_CSI_DPD_STATUS_0_CSI_A_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_CSI_DPD_STATUS_0_CSI_A_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_CSI_DPD_STATUS_0_CSI_A_OFF                  MK_ENUM_CONST(0)
#define PMC_IMPL_IO_CSI_DPD_STATUS_0_CSI_A_ON                   MK_ENUM_CONST(1)

// On - CSI_B PAD(s) is in Deep Power Down mode, Off - CSI_B PAD(s) is out of Deep Power Down mode
#define PMC_IMPL_IO_CSI_DPD_STATUS_0_CSI_B_SHIFT                        MK_SHIFT_CONST(1)
#define PMC_IMPL_IO_CSI_DPD_STATUS_0_CSI_B_FIELD                        MK_FIELD_CONST(0x1, PMC_IMPL_IO_CSI_DPD_STATUS_0_CSI_B_SHIFT)
#define PMC_IMPL_IO_CSI_DPD_STATUS_0_CSI_B_RANGE                        1:1
#define PMC_IMPL_IO_CSI_DPD_STATUS_0_CSI_B_MSB                  MK_SHIFT_CONST(1)
#define PMC_IMPL_IO_CSI_DPD_STATUS_0_CSI_B_LSB                  MK_SHIFT_CONST(1)
#define PMC_IMPL_IO_CSI_DPD_STATUS_0_CSI_B_WOFFSET                      0x0
#define PMC_IMPL_IO_CSI_DPD_STATUS_0_CSI_B_DEFAULT                      MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_CSI_DPD_STATUS_0_CSI_B_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_CSI_DPD_STATUS_0_CSI_B_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_CSI_DPD_STATUS_0_CSI_B_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_CSI_DPD_STATUS_0_CSI_B_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_CSI_DPD_STATUS_0_CSI_B_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_CSI_DPD_STATUS_0_CSI_B_OFF                  MK_ENUM_CONST(0)
#define PMC_IMPL_IO_CSI_DPD_STATUS_0_CSI_B_ON                   MK_ENUM_CONST(1)

// On - CSI_C PAD(s) is in Deep Power Down mode, Off - CSI_C PAD(s) is out of Deep Power Down mode
#define PMC_IMPL_IO_CSI_DPD_STATUS_0_CSI_C_SHIFT                        MK_SHIFT_CONST(2)
#define PMC_IMPL_IO_CSI_DPD_STATUS_0_CSI_C_FIELD                        MK_FIELD_CONST(0x1, PMC_IMPL_IO_CSI_DPD_STATUS_0_CSI_C_SHIFT)
#define PMC_IMPL_IO_CSI_DPD_STATUS_0_CSI_C_RANGE                        2:2
#define PMC_IMPL_IO_CSI_DPD_STATUS_0_CSI_C_MSB                  MK_SHIFT_CONST(2)
#define PMC_IMPL_IO_CSI_DPD_STATUS_0_CSI_C_LSB                  MK_SHIFT_CONST(2)
#define PMC_IMPL_IO_CSI_DPD_STATUS_0_CSI_C_WOFFSET                      0x0
#define PMC_IMPL_IO_CSI_DPD_STATUS_0_CSI_C_DEFAULT                      MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_CSI_DPD_STATUS_0_CSI_C_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_CSI_DPD_STATUS_0_CSI_C_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_CSI_DPD_STATUS_0_CSI_C_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_CSI_DPD_STATUS_0_CSI_C_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_CSI_DPD_STATUS_0_CSI_C_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_CSI_DPD_STATUS_0_CSI_C_OFF                  MK_ENUM_CONST(0)
#define PMC_IMPL_IO_CSI_DPD_STATUS_0_CSI_C_ON                   MK_ENUM_CONST(1)

// On - CSI_D PAD(s) is in Deep Power Down mode, Off - CSI_D PAD(s) is out of Deep Power Down mode
#define PMC_IMPL_IO_CSI_DPD_STATUS_0_CSI_D_SHIFT                        MK_SHIFT_CONST(3)
#define PMC_IMPL_IO_CSI_DPD_STATUS_0_CSI_D_FIELD                        MK_FIELD_CONST(0x1, PMC_IMPL_IO_CSI_DPD_STATUS_0_CSI_D_SHIFT)
#define PMC_IMPL_IO_CSI_DPD_STATUS_0_CSI_D_RANGE                        3:3
#define PMC_IMPL_IO_CSI_DPD_STATUS_0_CSI_D_MSB                  MK_SHIFT_CONST(3)
#define PMC_IMPL_IO_CSI_DPD_STATUS_0_CSI_D_LSB                  MK_SHIFT_CONST(3)
#define PMC_IMPL_IO_CSI_DPD_STATUS_0_CSI_D_WOFFSET                      0x0
#define PMC_IMPL_IO_CSI_DPD_STATUS_0_CSI_D_DEFAULT                      MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_CSI_DPD_STATUS_0_CSI_D_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_CSI_DPD_STATUS_0_CSI_D_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_CSI_DPD_STATUS_0_CSI_D_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_CSI_DPD_STATUS_0_CSI_D_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_CSI_DPD_STATUS_0_CSI_D_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_CSI_DPD_STATUS_0_CSI_D_OFF                  MK_ENUM_CONST(0)
#define PMC_IMPL_IO_CSI_DPD_STATUS_0_CSI_D_ON                   MK_ENUM_CONST(1)

// On - CSI_E PAD(s) is in Deep Power Down mode, Off - CSI_E PAD(s) is out of Deep Power Down mode
#define PMC_IMPL_IO_CSI_DPD_STATUS_0_CSI_E_SHIFT                        MK_SHIFT_CONST(4)
#define PMC_IMPL_IO_CSI_DPD_STATUS_0_CSI_E_FIELD                        MK_FIELD_CONST(0x1, PMC_IMPL_IO_CSI_DPD_STATUS_0_CSI_E_SHIFT)
#define PMC_IMPL_IO_CSI_DPD_STATUS_0_CSI_E_RANGE                        4:4
#define PMC_IMPL_IO_CSI_DPD_STATUS_0_CSI_E_MSB                  MK_SHIFT_CONST(4)
#define PMC_IMPL_IO_CSI_DPD_STATUS_0_CSI_E_LSB                  MK_SHIFT_CONST(4)
#define PMC_IMPL_IO_CSI_DPD_STATUS_0_CSI_E_WOFFSET                      0x0
#define PMC_IMPL_IO_CSI_DPD_STATUS_0_CSI_E_DEFAULT                      MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_CSI_DPD_STATUS_0_CSI_E_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_CSI_DPD_STATUS_0_CSI_E_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_CSI_DPD_STATUS_0_CSI_E_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_CSI_DPD_STATUS_0_CSI_E_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_CSI_DPD_STATUS_0_CSI_E_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_CSI_DPD_STATUS_0_CSI_E_OFF                  MK_ENUM_CONST(0)
#define PMC_IMPL_IO_CSI_DPD_STATUS_0_CSI_E_ON                   MK_ENUM_CONST(1)

// On - CSI_F PAD(s) is in Deep Power Down mode, Off - CSI_F PAD(s) is out of Deep Power Down mode
#define PMC_IMPL_IO_CSI_DPD_STATUS_0_CSI_F_SHIFT                        MK_SHIFT_CONST(5)
#define PMC_IMPL_IO_CSI_DPD_STATUS_0_CSI_F_FIELD                        MK_FIELD_CONST(0x1, PMC_IMPL_IO_CSI_DPD_STATUS_0_CSI_F_SHIFT)
#define PMC_IMPL_IO_CSI_DPD_STATUS_0_CSI_F_RANGE                        5:5
#define PMC_IMPL_IO_CSI_DPD_STATUS_0_CSI_F_MSB                  MK_SHIFT_CONST(5)
#define PMC_IMPL_IO_CSI_DPD_STATUS_0_CSI_F_LSB                  MK_SHIFT_CONST(5)
#define PMC_IMPL_IO_CSI_DPD_STATUS_0_CSI_F_WOFFSET                      0x0
#define PMC_IMPL_IO_CSI_DPD_STATUS_0_CSI_F_DEFAULT                      MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_CSI_DPD_STATUS_0_CSI_F_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_CSI_DPD_STATUS_0_CSI_F_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_CSI_DPD_STATUS_0_CSI_F_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_CSI_DPD_STATUS_0_CSI_F_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_CSI_DPD_STATUS_0_CSI_F_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_CSI_DPD_STATUS_0_CSI_F_OFF                  MK_ENUM_CONST(0)
#define PMC_IMPL_IO_CSI_DPD_STATUS_0_CSI_F_ON                   MK_ENUM_CONST(1)

// On - CSI_G PAD(s) is in Deep Power Down mode, Off - CSI_G PAD(s) is out of Deep Power Down mode
#define PMC_IMPL_IO_CSI_DPD_STATUS_0_CSI_G_SHIFT                        MK_SHIFT_CONST(6)
#define PMC_IMPL_IO_CSI_DPD_STATUS_0_CSI_G_FIELD                        MK_FIELD_CONST(0x1, PMC_IMPL_IO_CSI_DPD_STATUS_0_CSI_G_SHIFT)
#define PMC_IMPL_IO_CSI_DPD_STATUS_0_CSI_G_RANGE                        6:6
#define PMC_IMPL_IO_CSI_DPD_STATUS_0_CSI_G_MSB                  MK_SHIFT_CONST(6)
#define PMC_IMPL_IO_CSI_DPD_STATUS_0_CSI_G_LSB                  MK_SHIFT_CONST(6)
#define PMC_IMPL_IO_CSI_DPD_STATUS_0_CSI_G_WOFFSET                      0x0
#define PMC_IMPL_IO_CSI_DPD_STATUS_0_CSI_G_DEFAULT                      MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_CSI_DPD_STATUS_0_CSI_G_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_CSI_DPD_STATUS_0_CSI_G_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_CSI_DPD_STATUS_0_CSI_G_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_CSI_DPD_STATUS_0_CSI_G_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_CSI_DPD_STATUS_0_CSI_G_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_CSI_DPD_STATUS_0_CSI_G_OFF                  MK_ENUM_CONST(0)
#define PMC_IMPL_IO_CSI_DPD_STATUS_0_CSI_G_ON                   MK_ENUM_CONST(1)

// On - CSI_H PAD(s) is in Deep Power Down mode, Off - CSI_H PAD(s) is out of Deep Power Down mode
#define PMC_IMPL_IO_CSI_DPD_STATUS_0_CSI_H_SHIFT                        MK_SHIFT_CONST(7)
#define PMC_IMPL_IO_CSI_DPD_STATUS_0_CSI_H_FIELD                        MK_FIELD_CONST(0x1, PMC_IMPL_IO_CSI_DPD_STATUS_0_CSI_H_SHIFT)
#define PMC_IMPL_IO_CSI_DPD_STATUS_0_CSI_H_RANGE                        7:7
#define PMC_IMPL_IO_CSI_DPD_STATUS_0_CSI_H_MSB                  MK_SHIFT_CONST(7)
#define PMC_IMPL_IO_CSI_DPD_STATUS_0_CSI_H_LSB                  MK_SHIFT_CONST(7)
#define PMC_IMPL_IO_CSI_DPD_STATUS_0_CSI_H_WOFFSET                      0x0
#define PMC_IMPL_IO_CSI_DPD_STATUS_0_CSI_H_DEFAULT                      MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_CSI_DPD_STATUS_0_CSI_H_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_CSI_DPD_STATUS_0_CSI_H_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_CSI_DPD_STATUS_0_CSI_H_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_CSI_DPD_STATUS_0_CSI_H_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_CSI_DPD_STATUS_0_CSI_H_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_CSI_DPD_STATUS_0_CSI_H_OFF                  MK_ENUM_CONST(0)
#define PMC_IMPL_IO_CSI_DPD_STATUS_0_CSI_H_ON                   MK_ENUM_CONST(1)

// On - PHY_BIAS PAD(s) is in Deep Power Down mode, Off - PHY_BIAS PAD(s) is out of Deep Power Down mode
#define PMC_IMPL_IO_CSI_DPD_STATUS_0_PHY_BIAS_SHIFT                     MK_SHIFT_CONST(8)
#define PMC_IMPL_IO_CSI_DPD_STATUS_0_PHY_BIAS_FIELD                     MK_FIELD_CONST(0x1, PMC_IMPL_IO_CSI_DPD_STATUS_0_PHY_BIAS_SHIFT)
#define PMC_IMPL_IO_CSI_DPD_STATUS_0_PHY_BIAS_RANGE                     8:8
#define PMC_IMPL_IO_CSI_DPD_STATUS_0_PHY_BIAS_MSB                       MK_SHIFT_CONST(8)
#define PMC_IMPL_IO_CSI_DPD_STATUS_0_PHY_BIAS_LSB                       MK_SHIFT_CONST(8)
#define PMC_IMPL_IO_CSI_DPD_STATUS_0_PHY_BIAS_WOFFSET                   0x0
#define PMC_IMPL_IO_CSI_DPD_STATUS_0_PHY_BIAS_DEFAULT                   MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_CSI_DPD_STATUS_0_PHY_BIAS_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_CSI_DPD_STATUS_0_PHY_BIAS_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_CSI_DPD_STATUS_0_PHY_BIAS_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_CSI_DPD_STATUS_0_PHY_BIAS_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_CSI_DPD_STATUS_0_PHY_BIAS_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_CSI_DPD_STATUS_0_PHY_BIAS_OFF                       MK_ENUM_CONST(0)
#define PMC_IMPL_IO_CSI_DPD_STATUS_0_PHY_BIAS_ON                        MK_ENUM_CONST(1)

// On - PHY_PLL PAD(s) is in Deep Power Down mode, Off - PHY_PLL PAD(s) is out of Deep Power Down mode
#define PMC_IMPL_IO_CSI_DPD_STATUS_0_PHY_PLL_SHIFT                      MK_SHIFT_CONST(9)
#define PMC_IMPL_IO_CSI_DPD_STATUS_0_PHY_PLL_FIELD                      MK_FIELD_CONST(0x1, PMC_IMPL_IO_CSI_DPD_STATUS_0_PHY_PLL_SHIFT)
#define PMC_IMPL_IO_CSI_DPD_STATUS_0_PHY_PLL_RANGE                      9:9
#define PMC_IMPL_IO_CSI_DPD_STATUS_0_PHY_PLL_MSB                        MK_SHIFT_CONST(9)
#define PMC_IMPL_IO_CSI_DPD_STATUS_0_PHY_PLL_LSB                        MK_SHIFT_CONST(9)
#define PMC_IMPL_IO_CSI_DPD_STATUS_0_PHY_PLL_WOFFSET                    0x0
#define PMC_IMPL_IO_CSI_DPD_STATUS_0_PHY_PLL_DEFAULT                    MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_CSI_DPD_STATUS_0_PHY_PLL_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_CSI_DPD_STATUS_0_PHY_PLL_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_CSI_DPD_STATUS_0_PHY_PLL_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_CSI_DPD_STATUS_0_PHY_PLL_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_CSI_DPD_STATUS_0_PHY_PLL_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_CSI_DPD_STATUS_0_PHY_PLL_OFF                        MK_ENUM_CONST(0)
#define PMC_IMPL_IO_CSI_DPD_STATUS_0_PHY_PLL_ON                 MK_ENUM_CONST(1)


// Register PMC_IMPL_IO_EMMC_DPD_REQ_0
#define PMC_IMPL_IO_EMMC_DPD_REQ_0                      MK_ADDR_CONST(0xe0c8)
#define PMC_IMPL_IO_EMMC_DPD_REQ_0_SECURE                       0x0
#define PMC_IMPL_IO_EMMC_DPD_REQ_0_DUAL                         0x0
#define PMC_IMPL_IO_EMMC_DPD_REQ_0_SCR                  IO_EMMC_SCR_0
#define PMC_IMPL_IO_EMMC_DPD_REQ_0_SCRREG                       PMC_IMPL_SCR_IO_EMMC_SCR_0
#define PMC_IMPL_IO_EMMC_DPD_REQ_0_WORD_COUNT                   0x1
#define PMC_IMPL_IO_EMMC_DPD_REQ_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_EMMC_DPD_REQ_0_RESET_MASK                   MK_MASK_CONST(0xc0000001)
#define PMC_IMPL_IO_EMMC_DPD_REQ_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_EMMC_DPD_REQ_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_EMMC_DPD_REQ_0_READ_MASK                    MK_MASK_CONST(0xc0000001)
#define PMC_IMPL_IO_EMMC_DPD_REQ_0_WRITE_MASK                   MK_MASK_CONST(0xc0000001)
// code of operation for all set bits
#define PMC_IMPL_IO_EMMC_DPD_REQ_0_CODE_SHIFT                   MK_SHIFT_CONST(30)
#define PMC_IMPL_IO_EMMC_DPD_REQ_0_CODE_FIELD                   MK_FIELD_CONST(0x3, PMC_IMPL_IO_EMMC_DPD_REQ_0_CODE_SHIFT)
#define PMC_IMPL_IO_EMMC_DPD_REQ_0_CODE_RANGE                   31:30
#define PMC_IMPL_IO_EMMC_DPD_REQ_0_CODE_MSB                     MK_SHIFT_CONST(31)
#define PMC_IMPL_IO_EMMC_DPD_REQ_0_CODE_LSB                     MK_SHIFT_CONST(30)
#define PMC_IMPL_IO_EMMC_DPD_REQ_0_CODE_WOFFSET                 0x0
#define PMC_IMPL_IO_EMMC_DPD_REQ_0_CODE_DEFAULT                 MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_EMMC_DPD_REQ_0_CODE_DEFAULT_MASK                    MK_MASK_CONST(0x3)
#define PMC_IMPL_IO_EMMC_DPD_REQ_0_CODE_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_EMMC_DPD_REQ_0_CODE_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_EMMC_DPD_REQ_0_CODE_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_EMMC_DPD_REQ_0_CODE_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_EMMC_DPD_REQ_0_CODE_IDLE                    MK_ENUM_CONST(0)
#define PMC_IMPL_IO_EMMC_DPD_REQ_0_CODE_DPD_OFF                 MK_ENUM_CONST(1)
#define PMC_IMPL_IO_EMMC_DPD_REQ_0_CODE_DPD_ON                  MK_ENUM_CONST(2)

// puts EMMC PAD(s) in/out of Depp Power Down (DPD) mode
#define PMC_IMPL_IO_EMMC_DPD_REQ_0_EMMC_SHIFT                   MK_SHIFT_CONST(0)
#define PMC_IMPL_IO_EMMC_DPD_REQ_0_EMMC_FIELD                   MK_FIELD_CONST(0x1, PMC_IMPL_IO_EMMC_DPD_REQ_0_EMMC_SHIFT)
#define PMC_IMPL_IO_EMMC_DPD_REQ_0_EMMC_RANGE                   0:0
#define PMC_IMPL_IO_EMMC_DPD_REQ_0_EMMC_MSB                     MK_SHIFT_CONST(0)
#define PMC_IMPL_IO_EMMC_DPD_REQ_0_EMMC_LSB                     MK_SHIFT_CONST(0)
#define PMC_IMPL_IO_EMMC_DPD_REQ_0_EMMC_WOFFSET                 0x0
#define PMC_IMPL_IO_EMMC_DPD_REQ_0_EMMC_DEFAULT                 MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_EMMC_DPD_REQ_0_EMMC_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_EMMC_DPD_REQ_0_EMMC_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_EMMC_DPD_REQ_0_EMMC_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_EMMC_DPD_REQ_0_EMMC_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_EMMC_DPD_REQ_0_EMMC_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_EMMC_DPD_REQ_0_EMMC_OFF                     MK_ENUM_CONST(0)
#define PMC_IMPL_IO_EMMC_DPD_REQ_0_EMMC_ON                      MK_ENUM_CONST(1)


// Register PMC_IMPL_IO_EMMC_DPD_STATUS_0
#define PMC_IMPL_IO_EMMC_DPD_STATUS_0                   MK_ADDR_CONST(0xe0cc)
#define PMC_IMPL_IO_EMMC_DPD_STATUS_0_SECURE                    0x0
#define PMC_IMPL_IO_EMMC_DPD_STATUS_0_DUAL                      0x0
#define PMC_IMPL_IO_EMMC_DPD_STATUS_0_SCR                       IO_EMMC_SCR_0
#define PMC_IMPL_IO_EMMC_DPD_STATUS_0_SCRREG                    PMC_IMPL_SCR_IO_EMMC_SCR_0
#define PMC_IMPL_IO_EMMC_DPD_STATUS_0_WORD_COUNT                        0x1
#define PMC_IMPL_IO_EMMC_DPD_STATUS_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_EMMC_DPD_STATUS_0_RESET_MASK                        MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_EMMC_DPD_STATUS_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_EMMC_DPD_STATUS_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_EMMC_DPD_STATUS_0_READ_MASK                         MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_EMMC_DPD_STATUS_0_WRITE_MASK                        MK_MASK_CONST(0x0)
// On - EMMC PAD(s) is in Deep Power Down mode, Off - EMMC PAD(s) is out of Deep Power Down mode
#define PMC_IMPL_IO_EMMC_DPD_STATUS_0_EMMC_SHIFT                        MK_SHIFT_CONST(0)
#define PMC_IMPL_IO_EMMC_DPD_STATUS_0_EMMC_FIELD                        MK_FIELD_CONST(0x1, PMC_IMPL_IO_EMMC_DPD_STATUS_0_EMMC_SHIFT)
#define PMC_IMPL_IO_EMMC_DPD_STATUS_0_EMMC_RANGE                        0:0
#define PMC_IMPL_IO_EMMC_DPD_STATUS_0_EMMC_MSB                  MK_SHIFT_CONST(0)
#define PMC_IMPL_IO_EMMC_DPD_STATUS_0_EMMC_LSB                  MK_SHIFT_CONST(0)
#define PMC_IMPL_IO_EMMC_DPD_STATUS_0_EMMC_WOFFSET                      0x0
#define PMC_IMPL_IO_EMMC_DPD_STATUS_0_EMMC_DEFAULT                      MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_EMMC_DPD_STATUS_0_EMMC_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_EMMC_DPD_STATUS_0_EMMC_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_EMMC_DPD_STATUS_0_EMMC_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_EMMC_DPD_STATUS_0_EMMC_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_EMMC_DPD_STATUS_0_EMMC_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_EMMC_DPD_STATUS_0_EMMC_OFF                  MK_ENUM_CONST(0)
#define PMC_IMPL_IO_EMMC_DPD_STATUS_0_EMMC_ON                   MK_ENUM_CONST(1)


// Register PMC_IMPL_IO_DISP_DPD_REQ_0
#define PMC_IMPL_IO_DISP_DPD_REQ_0                      MK_ADDR_CONST(0xe0d0)
#define PMC_IMPL_IO_DISP_DPD_REQ_0_SECURE                       0x0
#define PMC_IMPL_IO_DISP_DPD_REQ_0_DUAL                         0x0
#define PMC_IMPL_IO_DISP_DPD_REQ_0_SCR                  IO_DISP_SCR_0
#define PMC_IMPL_IO_DISP_DPD_REQ_0_SCRREG                       PMC_IMPL_SCR_IO_DISP_SCR_0
#define PMC_IMPL_IO_DISP_DPD_REQ_0_WORD_COUNT                   0x1
#define PMC_IMPL_IO_DISP_DPD_REQ_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DISP_DPD_REQ_0_RESET_MASK                   MK_MASK_CONST(0xc0000001)
#define PMC_IMPL_IO_DISP_DPD_REQ_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DISP_DPD_REQ_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DISP_DPD_REQ_0_READ_MASK                    MK_MASK_CONST(0xc0000001)
#define PMC_IMPL_IO_DISP_DPD_REQ_0_WRITE_MASK                   MK_MASK_CONST(0xc0000001)
// code of operation for all set bits
#define PMC_IMPL_IO_DISP_DPD_REQ_0_CODE_SHIFT                   MK_SHIFT_CONST(30)
#define PMC_IMPL_IO_DISP_DPD_REQ_0_CODE_FIELD                   MK_FIELD_CONST(0x3, PMC_IMPL_IO_DISP_DPD_REQ_0_CODE_SHIFT)
#define PMC_IMPL_IO_DISP_DPD_REQ_0_CODE_RANGE                   31:30
#define PMC_IMPL_IO_DISP_DPD_REQ_0_CODE_MSB                     MK_SHIFT_CONST(31)
#define PMC_IMPL_IO_DISP_DPD_REQ_0_CODE_LSB                     MK_SHIFT_CONST(30)
#define PMC_IMPL_IO_DISP_DPD_REQ_0_CODE_WOFFSET                 0x0
#define PMC_IMPL_IO_DISP_DPD_REQ_0_CODE_DEFAULT                 MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DISP_DPD_REQ_0_CODE_DEFAULT_MASK                    MK_MASK_CONST(0x3)
#define PMC_IMPL_IO_DISP_DPD_REQ_0_CODE_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DISP_DPD_REQ_0_CODE_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DISP_DPD_REQ_0_CODE_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DISP_DPD_REQ_0_CODE_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DISP_DPD_REQ_0_CODE_IDLE                    MK_ENUM_CONST(0)
#define PMC_IMPL_IO_DISP_DPD_REQ_0_CODE_DPD_OFF                 MK_ENUM_CONST(1)
#define PMC_IMPL_IO_DISP_DPD_REQ_0_CODE_DPD_ON                  MK_ENUM_CONST(2)

// puts HDMI_DP0 PAD(s) in/out of Depp Power Down (DPD) mode
#define PMC_IMPL_IO_DISP_DPD_REQ_0_HDMI_DP0_SHIFT                       MK_SHIFT_CONST(0)
#define PMC_IMPL_IO_DISP_DPD_REQ_0_HDMI_DP0_FIELD                       MK_FIELD_CONST(0x1, PMC_IMPL_IO_DISP_DPD_REQ_0_HDMI_DP0_SHIFT)
#define PMC_IMPL_IO_DISP_DPD_REQ_0_HDMI_DP0_RANGE                       0:0
#define PMC_IMPL_IO_DISP_DPD_REQ_0_HDMI_DP0_MSB                 MK_SHIFT_CONST(0)
#define PMC_IMPL_IO_DISP_DPD_REQ_0_HDMI_DP0_LSB                 MK_SHIFT_CONST(0)
#define PMC_IMPL_IO_DISP_DPD_REQ_0_HDMI_DP0_WOFFSET                     0x0
#define PMC_IMPL_IO_DISP_DPD_REQ_0_HDMI_DP0_DEFAULT                     MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DISP_DPD_REQ_0_HDMI_DP0_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DISP_DPD_REQ_0_HDMI_DP0_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DISP_DPD_REQ_0_HDMI_DP0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DISP_DPD_REQ_0_HDMI_DP0_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DISP_DPD_REQ_0_HDMI_DP0_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DISP_DPD_REQ_0_HDMI_DP0_OFF                 MK_ENUM_CONST(0)
#define PMC_IMPL_IO_DISP_DPD_REQ_0_HDMI_DP0_ON                  MK_ENUM_CONST(1)


// Register PMC_IMPL_IO_DISP_DPD_STATUS_0
#define PMC_IMPL_IO_DISP_DPD_STATUS_0                   MK_ADDR_CONST(0xe0d4)
#define PMC_IMPL_IO_DISP_DPD_STATUS_0_SECURE                    0x0
#define PMC_IMPL_IO_DISP_DPD_STATUS_0_DUAL                      0x0
#define PMC_IMPL_IO_DISP_DPD_STATUS_0_SCR                       IO_DISP_SCR_0
#define PMC_IMPL_IO_DISP_DPD_STATUS_0_SCRREG                    PMC_IMPL_SCR_IO_DISP_SCR_0
#define PMC_IMPL_IO_DISP_DPD_STATUS_0_WORD_COUNT                        0x1
#define PMC_IMPL_IO_DISP_DPD_STATUS_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DISP_DPD_STATUS_0_RESET_MASK                        MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DISP_DPD_STATUS_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DISP_DPD_STATUS_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DISP_DPD_STATUS_0_READ_MASK                         MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DISP_DPD_STATUS_0_WRITE_MASK                        MK_MASK_CONST(0x0)
// On - HDMI_DP0 PAD(s) is in Deep Power Down mode, Off - HDMI_DP0 PAD(s) is out of Deep Power Down mode
#define PMC_IMPL_IO_DISP_DPD_STATUS_0_HDMI_DP0_SHIFT                    MK_SHIFT_CONST(0)
#define PMC_IMPL_IO_DISP_DPD_STATUS_0_HDMI_DP0_FIELD                    MK_FIELD_CONST(0x1, PMC_IMPL_IO_DISP_DPD_STATUS_0_HDMI_DP0_SHIFT)
#define PMC_IMPL_IO_DISP_DPD_STATUS_0_HDMI_DP0_RANGE                    0:0
#define PMC_IMPL_IO_DISP_DPD_STATUS_0_HDMI_DP0_MSB                      MK_SHIFT_CONST(0)
#define PMC_IMPL_IO_DISP_DPD_STATUS_0_HDMI_DP0_LSB                      MK_SHIFT_CONST(0)
#define PMC_IMPL_IO_DISP_DPD_STATUS_0_HDMI_DP0_WOFFSET                  0x0
#define PMC_IMPL_IO_DISP_DPD_STATUS_0_HDMI_DP0_DEFAULT                  MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DISP_DPD_STATUS_0_HDMI_DP0_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DISP_DPD_STATUS_0_HDMI_DP0_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DISP_DPD_STATUS_0_HDMI_DP0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DISP_DPD_STATUS_0_HDMI_DP0_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DISP_DPD_STATUS_0_HDMI_DP0_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DISP_DPD_STATUS_0_HDMI_DP0_OFF                      MK_ENUM_CONST(0)
#define PMC_IMPL_IO_DISP_DPD_STATUS_0_HDMI_DP0_ON                       MK_ENUM_CONST(1)


// Reserved address 0xf000

// Reserved address 0xf004

// Reserved address 0xf008

// Reserved address 0xf00c

// Reserved address 0xf010
//Reset level:No reset, these are RO status bits of POD FE/BE indications
// For FSI and CVx, the RTL connections are swapped, please read BE for FE and read FE for BE

// Reserved address 0xf800

// Reserved address 0xf900

// Reserved address 0xf904

// Reserved address 0xf908

// Reserved address 0xf90c

// Reserved address 0xf910

// Reserved address 0xf914

// Reserved address 0xfa00

// Reserved address 0xfa04

// Reserved address 0xfa08

// Reserved address 0xfa0c

// Reserved address 0xfa10

// Reserved address 0xfa14

//
// REGISTER LIST
//
#define LIST_ARPMC_IMPL_PUBLIC_REGS(_op_) \
_op_(PMC_IMPL_CNTRL_0) \
_op_(PMC_IMPL_SLCG_CTRL_0) \
_op_(PMC_IMPL_BLINK_TIMER_0) \
_op_(PMC_IMPL_E_18V_PWR_0) \
_op_(PMC_IMPL_E_33V_PWR_0) \
_op_(PMC_IMPL_OSC_EDPD_OVER_0) \
_op_(PMC_IMPL_CLK_OUT_CNTRL_0) \
_op_(PMC_IMPL_SENSOR_CTRL_0) \
_op_(PMC_IMPL_RST_STATUS_0) \
_op_(PMC_IMPL_IO_DPD_REQ_0) \
_op_(PMC_IMPL_SEL_DPD_TIM_0) \
_op_(PMC_IMPL_TSC_MULT_0) \
_op_(PMC_IMPL_CNTRL2_0) \
_op_(PMC_IMPL_RAMDUMP_CTL_STATUS_0) \
_op_(PMC_IMPL_RST_REQ_CONFIG_0) \
_op_(PMC_IMPL_RST_REQ_CNTVAL_0) \
_op_(PMC_IMPL_PART_AUD_POWER_GATE_CONTROL_0) \
_op_(PMC_IMPL_PART_AUD_POWER_GATE_STATUS_0) \
_op_(PMC_IMPL_PART_AUD_CLAMP_CONTROL_0) \
_op_(PMC_IMPL_PART_DISP_POWER_GATE_CONTROL_0) \
_op_(PMC_IMPL_PART_DISP_POWER_GATE_STATUS_0) \
_op_(PMC_IMPL_PART_DISP_CLAMP_CONTROL_0) \
_op_(PMC_IMPL_PART_VIC_POWER_GATE_CONTROL_0) \
_op_(PMC_IMPL_PART_VIC_POWER_GATE_STATUS_0) \
_op_(PMC_IMPL_PART_VIC_CLAMP_CONTROL_0) \
_op_(PMC_IMPL_PART_XUSBA_POWER_GATE_CONTROL_0) \
_op_(PMC_IMPL_PART_XUSBA_POWER_GATE_STATUS_0) \
_op_(PMC_IMPL_PART_XUSBA_CLAMP_CONTROL_0) \
_op_(PMC_IMPL_PART_XUSBB_POWER_GATE_CONTROL_0) \
_op_(PMC_IMPL_PART_XUSBB_POWER_GATE_STATUS_0) \
_op_(PMC_IMPL_PART_XUSBB_CLAMP_CONTROL_0) \
_op_(PMC_IMPL_PART_XUSBC_POWER_GATE_CONTROL_0) \
_op_(PMC_IMPL_PART_XUSBC_POWER_GATE_STATUS_0) \
_op_(PMC_IMPL_PART_XUSBC_CLAMP_CONTROL_0) \
_op_(PMC_IMPL_PART_AOPG_TCM0_POWER_GATE_CONTROL_0) \
_op_(PMC_IMPL_PART_AOPG_TCM0_POWER_GATE_STATUS_0) \
_op_(PMC_IMPL_PART_AOPG_TCM0_CLAMP_CONTROL_0) \
_op_(PMC_IMPL_PART_AOPG_TCM1_POWER_GATE_CONTROL_0) \
_op_(PMC_IMPL_PART_AOPG_TCM1_POWER_GATE_STATUS_0) \
_op_(PMC_IMPL_PART_AOPG_TCM1_CLAMP_CONTROL_0) \
_op_(PMC_IMPL_PART_AOPG_TCM2_POWER_GATE_CONTROL_0) \
_op_(PMC_IMPL_PART_AOPG_TCM2_POWER_GATE_STATUS_0) \
_op_(PMC_IMPL_PART_AOPG_TCM2_CLAMP_CONTROL_0) \
_op_(PMC_IMPL_PART_AOPG_TCM3_POWER_GATE_CONTROL_0) \
_op_(PMC_IMPL_PART_AOPG_TCM3_POWER_GATE_STATUS_0) \
_op_(PMC_IMPL_PART_AOPG_TCM3_CLAMP_CONTROL_0) \
_op_(PMC_IMPL_PART_AOPG_TCM4_POWER_GATE_CONTROL_0) \
_op_(PMC_IMPL_PART_AOPG_TCM4_POWER_GATE_STATUS_0) \
_op_(PMC_IMPL_PART_AOPG_TCM4_CLAMP_CONTROL_0) \
_op_(PMC_IMPL_PART_AOPG_TCM5_POWER_GATE_CONTROL_0) \
_op_(PMC_IMPL_PART_AOPG_TCM5_POWER_GATE_STATUS_0) \
_op_(PMC_IMPL_PART_AOPG_TCM5_CLAMP_CONTROL_0) \
_op_(PMC_IMPL_PART_AOPG_TCM6_POWER_GATE_CONTROL_0) \
_op_(PMC_IMPL_PART_AOPG_TCM6_POWER_GATE_STATUS_0) \
_op_(PMC_IMPL_PART_AOPG_TCM6_CLAMP_CONTROL_0) \
_op_(PMC_IMPL_PART_AOPG_TCM7_POWER_GATE_CONTROL_0) \
_op_(PMC_IMPL_PART_AOPG_TCM7_POWER_GATE_STATUS_0) \
_op_(PMC_IMPL_PART_AOPG_TCM7_CLAMP_CONTROL_0) \
_op_(PMC_IMPL_PART_AOPG_CACHE_POWER_GATE_CONTROL_0) \
_op_(PMC_IMPL_PART_AOPG_CACHE_POWER_GATE_STATUS_0) \
_op_(PMC_IMPL_PART_AOPG_CACHE_CLAMP_CONTROL_0) \
_op_(PMC_IMPL_PART_AOPG_CAN0_POWER_GATE_CONTROL_0) \
_op_(PMC_IMPL_PART_AOPG_CAN0_POWER_GATE_STATUS_0) \
_op_(PMC_IMPL_PART_AOPG_CAN0_CLAMP_CONTROL_0) \
_op_(PMC_IMPL_PART_AOPG_CAN1_POWER_GATE_CONTROL_0) \
_op_(PMC_IMPL_PART_AOPG_CAN1_POWER_GATE_STATUS_0) \
_op_(PMC_IMPL_PART_AOPG_CAN1_CLAMP_CONTROL_0) \
_op_(PMC_IMPL_PART_PCIEX8A_POWER_GATE_CONTROL_0) \
_op_(PMC_IMPL_PART_PCIEX8A_POWER_GATE_STATUS_0) \
_op_(PMC_IMPL_PART_PCIEX8A_CLAMP_CONTROL_0) \
_op_(PMC_IMPL_PART_PCIEX4A_POWER_GATE_CONTROL_0) \
_op_(PMC_IMPL_PART_PCIEX4A_POWER_GATE_STATUS_0) \
_op_(PMC_IMPL_PART_PCIEX4A_CLAMP_CONTROL_0) \
_op_(PMC_IMPL_PART_PCIEX1A_POWER_GATE_CONTROL_0) \
_op_(PMC_IMPL_PART_PCIEX1A_POWER_GATE_STATUS_0) \
_op_(PMC_IMPL_PART_PCIEX1A_CLAMP_CONTROL_0) \
_op_(PMC_IMPL_PART_PCIEX8B_POWER_GATE_CONTROL_0) \
_op_(PMC_IMPL_PART_PCIEX8B_POWER_GATE_STATUS_0) \
_op_(PMC_IMPL_PART_PCIEX8B_CLAMP_CONTROL_0) \
_op_(PMC_IMPL_PART_DLAA_POWER_GATE_CONTROL_0) \
_op_(PMC_IMPL_PART_DLAA_POWER_GATE_STATUS_0) \
_op_(PMC_IMPL_PART_DLAA_CLAMP_CONTROL_0) \
_op_(PMC_IMPL_PART_DLAB_POWER_GATE_CONTROL_0) \
_op_(PMC_IMPL_PART_DLAB_POWER_GATE_STATUS_0) \
_op_(PMC_IMPL_PART_DLAB_CLAMP_CONTROL_0) \
_op_(PMC_IMPL_PART_ISP_POWER_GATE_CONTROL_0) \
_op_(PMC_IMPL_PART_ISP_POWER_GATE_STATUS_0) \
_op_(PMC_IMPL_PART_ISP_CLAMP_CONTROL_0) \
_op_(PMC_IMPL_PART_NVDEC_POWER_GATE_CONTROL_0) \
_op_(PMC_IMPL_PART_NVDEC_POWER_GATE_STATUS_0) \
_op_(PMC_IMPL_PART_NVDEC_CLAMP_CONTROL_0) \
_op_(PMC_IMPL_PART_NVJPGA_POWER_GATE_CONTROL_0) \
_op_(PMC_IMPL_PART_NVJPGA_POWER_GATE_STATUS_0) \
_op_(PMC_IMPL_PART_NVJPGA_CLAMP_CONTROL_0) \
_op_(PMC_IMPL_PART_NVJPGB_POWER_GATE_CONTROL_0) \
_op_(PMC_IMPL_PART_NVJPGB_POWER_GATE_STATUS_0) \
_op_(PMC_IMPL_PART_NVJPGB_CLAMP_CONTROL_0) \
_op_(PMC_IMPL_PART_NVENC_POWER_GATE_CONTROL_0) \
_op_(PMC_IMPL_PART_NVENC_POWER_GATE_STATUS_0) \
_op_(PMC_IMPL_PART_NVENC_CLAMP_CONTROL_0) \
_op_(PMC_IMPL_PART_VI_POWER_GATE_CONTROL_0) \
_op_(PMC_IMPL_PART_VI_POWER_GATE_STATUS_0) \
_op_(PMC_IMPL_PART_VI_CLAMP_CONTROL_0) \
_op_(PMC_IMPL_PART_PCIEX4BA_POWER_GATE_CONTROL_0) \
_op_(PMC_IMPL_PART_PCIEX4BA_POWER_GATE_STATUS_0) \
_op_(PMC_IMPL_PART_PCIEX4BA_CLAMP_CONTROL_0) \
_op_(PMC_IMPL_PART_PCIEX4BB_POWER_GATE_CONTROL_0) \
_op_(PMC_IMPL_PART_PCIEX4BB_POWER_GATE_STATUS_0) \
_op_(PMC_IMPL_PART_PCIEX4BB_CLAMP_CONTROL_0) \
_op_(PMC_IMPL_PART_PCIEX4CA_POWER_GATE_CONTROL_0) \
_op_(PMC_IMPL_PART_PCIEX4CA_POWER_GATE_STATUS_0) \
_op_(PMC_IMPL_PART_PCIEX4CA_CLAMP_CONTROL_0) \
_op_(PMC_IMPL_PART_PCIEX4CB_POWER_GATE_CONTROL_0) \
_op_(PMC_IMPL_PART_PCIEX4CB_POWER_GATE_STATUS_0) \
_op_(PMC_IMPL_PART_PCIEX4CB_CLAMP_CONTROL_0) \
_op_(PMC_IMPL_PART_PCIEX4CC_POWER_GATE_CONTROL_0) \
_op_(PMC_IMPL_PART_PCIEX4CC_POWER_GATE_STATUS_0) \
_op_(PMC_IMPL_PART_PCIEX4CC_CLAMP_CONTROL_0) \
_op_(PMC_IMPL_PART_PVA_POWER_GATE_CONTROL_0) \
_op_(PMC_IMPL_PART_PVA_POWER_GATE_STATUS_0) \
_op_(PMC_IMPL_PART_PVA_CLAMP_CONTROL_0) \
_op_(PMC_IMPL_PART_OFA_POWER_GATE_CONTROL_0) \
_op_(PMC_IMPL_PART_OFA_POWER_GATE_STATUS_0) \
_op_(PMC_IMPL_PART_OFA_CLAMP_CONTROL_0) \
_op_(PMC_IMPL_PART_MGBEA_POWER_GATE_CONTROL_0) \
_op_(PMC_IMPL_PART_MGBEA_POWER_GATE_STATUS_0) \
_op_(PMC_IMPL_PART_MGBEA_CLAMP_CONTROL_0) \
_op_(PMC_IMPL_PART_MGBEBA_POWER_GATE_CONTROL_0) \
_op_(PMC_IMPL_PART_MGBEBA_POWER_GATE_STATUS_0) \
_op_(PMC_IMPL_PART_MGBEBA_CLAMP_CONTROL_0) \
_op_(PMC_IMPL_PART_MGBEBB_POWER_GATE_CONTROL_0) \
_op_(PMC_IMPL_PART_MGBEBB_POWER_GATE_STATUS_0) \
_op_(PMC_IMPL_PART_MGBEBB_CLAMP_CONTROL_0) \
_op_(PMC_IMPL_PART_MGBEBC_POWER_GATE_CONTROL_0) \
_op_(PMC_IMPL_PART_MGBEBC_POWER_GATE_STATUS_0) \
_op_(PMC_IMPL_PART_MGBEBC_CLAMP_CONTROL_0) \
_op_(PMC_IMPL_PART_DBBRAM_POWER_GATE_CONTROL_0) \
_op_(PMC_IMPL_PART_DBBRAM_POWER_GATE_STATUS_0) \
_op_(PMC_IMPL_PART_DBBRAM_CLAMP_CONTROL_0) \
_op_(PMC_IMPL_PART_AUD_PWRDWN_REQ_CONTROL_0) \
_op_(PMC_IMPL_PART_AUD_PWRDWN_ACK_STATUS_0) \
_op_(PMC_IMPL_PART_DISP_PWRDWN_REQ_CONTROL_0) \
_op_(PMC_IMPL_PART_DISP_PWRDWN_ACK_STATUS_0) \
_op_(PMC_IMPL_PART_ISP_PWRDWN_REQ_CONTROL_0) \
_op_(PMC_IMPL_PART_ISP_PWRDWN_ACK_STATUS_0) \
_op_(PMC_IMPL_PART_NVDEC_PWRDWN_REQ_CONTROL_0) \
_op_(PMC_IMPL_PART_NVDEC_PWRDWN_ACK_STATUS_0) \
_op_(PMC_IMPL_PART_NVJPGA_PWRDWN_REQ_CONTROL_0) \
_op_(PMC_IMPL_PART_NVJPGA_PWRDWN_ACK_STATUS_0) \
_op_(PMC_IMPL_PART_NVJPGB_PWRDWN_REQ_CONTROL_0) \
_op_(PMC_IMPL_PART_NVJPGB_PWRDWN_ACK_STATUS_0) \
_op_(PMC_IMPL_PART_NVENC_PWRDWN_REQ_CONTROL_0) \
_op_(PMC_IMPL_PART_NVENC_PWRDWN_ACK_STATUS_0) \
_op_(PMC_IMPL_PART_VI_PWRDWN_REQ_CONTROL_0) \
_op_(PMC_IMPL_PART_VI_PWRDWN_ACK_STATUS_0) \
_op_(PMC_IMPL_PART_VIC_PWRDWN_REQ_CONTROL_0) \
_op_(PMC_IMPL_PART_VIC_PWRDWN_ACK_STATUS_0) \
_op_(PMC_IMPL_PART_XUSBA_PWRDWN_REQ_CONTROL_0) \
_op_(PMC_IMPL_PART_XUSBA_PWRDWN_ACK_STATUS_0) \
_op_(PMC_IMPL_PART_XUSBB_PWRDWN_REQ_CONTROL_0) \
_op_(PMC_IMPL_PART_XUSBB_PWRDWN_ACK_STATUS_0) \
_op_(PMC_IMPL_PART_XUSBC_PWRDWN_REQ_CONTROL_0) \
_op_(PMC_IMPL_PART_XUSBC_PWRDWN_ACK_STATUS_0) \
_op_(PMC_IMPL_PART_PCIEX8A_PWRDWN_REQ_CONTROL_0) \
_op_(PMC_IMPL_PART_PCIEX8A_PWRDWN_ACK_STATUS_0) \
_op_(PMC_IMPL_PART_PCIEX4A_PWRDWN_REQ_CONTROL_0) \
_op_(PMC_IMPL_PART_PCIEX4A_PWRDWN_ACK_STATUS_0) \
_op_(PMC_IMPL_PART_PCIEX4BA_PWRDWN_REQ_CONTROL_0) \
_op_(PMC_IMPL_PART_PCIEX4BA_PWRDWN_ACK_STATUS_0) \
_op_(PMC_IMPL_PART_PCIEX4BB_PWRDWN_REQ_CONTROL_0) \
_op_(PMC_IMPL_PART_PCIEX4BB_PWRDWN_ACK_STATUS_0) \
_op_(PMC_IMPL_PART_PCIEX4CA_PWRDWN_REQ_CONTROL_0) \
_op_(PMC_IMPL_PART_PCIEX4CA_PWRDWN_ACK_STATUS_0) \
_op_(PMC_IMPL_PART_PCIEX4CB_PWRDWN_REQ_CONTROL_0) \
_op_(PMC_IMPL_PART_PCIEX4CB_PWRDWN_ACK_STATUS_0) \
_op_(PMC_IMPL_PART_PCIEX4CC_PWRDWN_REQ_CONTROL_0) \
_op_(PMC_IMPL_PART_PCIEX4CC_PWRDWN_ACK_STATUS_0) \
_op_(PMC_IMPL_PART_PCIEX1A_PWRDWN_REQ_CONTROL_0) \
_op_(PMC_IMPL_PART_PCIEX1A_PWRDWN_ACK_STATUS_0) \
_op_(PMC_IMPL_PART_PCIEX8B_PWRDWN_REQ_CONTROL_0) \
_op_(PMC_IMPL_PART_PCIEX8B_PWRDWN_ACK_STATUS_0) \
_op_(PMC_IMPL_PART_PVA_PWRDWN_REQ_CONTROL_0) \
_op_(PMC_IMPL_PART_PVA_PWRDWN_ACK_STATUS_0) \
_op_(PMC_IMPL_PART_DLAA_PWRDWN_REQ_CONTROL_0) \
_op_(PMC_IMPL_PART_DLAA_PWRDWN_ACK_STATUS_0) \
_op_(PMC_IMPL_PART_DLAB_PWRDWN_REQ_CONTROL_0) \
_op_(PMC_IMPL_PART_DLAB_PWRDWN_ACK_STATUS_0) \
_op_(PMC_IMPL_PART_OFA_PWRDWN_REQ_CONTROL_0) \
_op_(PMC_IMPL_PART_OFA_PWRDWN_ACK_STATUS_0) \
_op_(PMC_IMPL_PART_MGBEA_PWRDWN_REQ_CONTROL_0) \
_op_(PMC_IMPL_PART_MGBEA_PWRDWN_ACK_STATUS_0) \
_op_(PMC_IMPL_PART_MGBEBA_PWRDWN_REQ_CONTROL_0) \
_op_(PMC_IMPL_PART_MGBEBA_PWRDWN_ACK_STATUS_0) \
_op_(PMC_IMPL_PART_MGBEBB_PWRDWN_REQ_CONTROL_0) \
_op_(PMC_IMPL_PART_MGBEBB_PWRDWN_ACK_STATUS_0) \
_op_(PMC_IMPL_PART_MGBEBC_PWRDWN_REQ_CONTROL_0) \
_op_(PMC_IMPL_PART_MGBEBC_PWRDWN_ACK_STATUS_0) \
_op_(PMC_IMPL_PART_EMCAA_PWRDWN_REQ_CONTROL_0) \
_op_(PMC_IMPL_PART_EMCAA_PWRDWN_ACK_STATUS_0) \
_op_(PMC_IMPL_SW_OVERRIDE_CTRL_1_0) \
_op_(PMC_IMPL_SW_OVERRIDE_CTRL_2_0) \
_op_(PMC_IMPL_MISC_CTRL_0) \
_op_(PMC_IMPL_PMC2LIC_INTR_STATUS_0) \
_op_(PMC_IMPL_PMC2LIC_INTR_ENABLE_0) \
_op_(PMC_IMPL_RAMDUMP_FIQ_EXIT_0) \
_op_(PMC_IMPL_SET_RAMDUMP_FIQ_EXIT_0) \
_op_(PMC_IMPL_CLR_RAMDUMP_FIQ_EXIT_0) \
_op_(PMC_IMPL_FMON_THRESHOLD_HIGH_OSCnFUSE_CK_0) \
_op_(PMC_IMPL_FMON_THRESHOLD_LOW_OSCnFUSE_CK_0) \
_op_(PMC_IMPL_FMON_REF_WINDOW_COUNT_OSCnFUSE_CK_0) \
_op_(PMC_IMPL_FMON_REF_WINDOW_DC_CHECK_COUNT_OSCnFUSE_CK_0) \
_op_(PMC_IMPL_FMON_FAULT_ACTION_OSCnFUSE_CK_0) \
_op_(PMC_IMPL_FMON_CONFIG_OSCnFUSE_CK_0) \
_op_(PMC_IMPL_FMON_ENABLE_STATUS_OSCnFUSE_CK_0) \
_op_(PMC_IMPL_FMON_FAULT_STATUS_OSCnFUSE_CK_0) \
_op_(PMC_IMPL_FMON_LOAD_DATA_CTRL_OSCnFUSE_CK_0) \
_op_(PMC_IMPL_FMON_LOAD_DATA_STATUS_0_OSCnFUSE_CK_0) \
_op_(PMC_IMPL_FMON_LOAD_DATA_STATUS_1_OSCnFUSE_CK_0) \
_op_(PMC_IMPL_FMON_LOAD_DATA_STATUS_2_OSCnFUSE_CK_0) \
_op_(PMC_IMPL_FMON_CLEAR_COUNTER_OSCnFUSE_CK_0) \
_op_(PMC_IMPL_FMON_DEBUG_CONFIG_OSCnFUSE_CK_0) \
_op_(PMC_IMPL_FMON_CNTR_OVERFLOW_CTRL_OSCnFUSE_CK_0) \
_op_(PMC_IMPL_RST_REQ_TIMER_0) \
_op_(PMC_IMPL_PMC_RESET_DETECTOR_0) \
_op_(PMC_IMPL_LED_BREATHING_CTRL_0) \
_op_(PMC_IMPL_LED_BREATHING_COUNTER0_0) \
_op_(PMC_IMPL_LED_BREATHING_COUNTER1_0) \
_op_(PMC_IMPL_LED_BREATHING_COUNTER2_0) \
_op_(PMC_IMPL_LED_BREATHING_COUNTER3_0) \
_op_(PMC_IMPL_LED_BREATHING_STATUS_0) \
_op_(PMC_IMPL_DPD_AUX_CLAMP_0) \
_op_(PMC_IMPL_IO_SYS_DPD_REQ_0) \
_op_(PMC_IMPL_IO_SYS_DPD_STATUS_0) \
_op_(PMC_IMPL_IO_SYS_DPD_OFF_MASK_0) \
_op_(PMC_IMPL_IO_AO_DPD_REQ_0) \
_op_(PMC_IMPL_IO_AO_DPD_STATUS_0) \
_op_(PMC_IMPL_IO_AO_DPD_OFF_MASK_0) \
_op_(PMC_IMPL_IO_DBG_DPD_REQ_0) \
_op_(PMC_IMPL_IO_DBG_DPD_STATUS_0) \
_op_(PMC_IMPL_IO_G2_DPD_REQ_0) \
_op_(PMC_IMPL_IO_G2_DPD_STATUS_0) \
_op_(PMC_IMPL_IO_G3_DPD_REQ_0) \
_op_(PMC_IMPL_IO_G3_DPD_STATUS_0) \
_op_(PMC_IMPL_IO_G4_DPD_REQ_0) \
_op_(PMC_IMPL_IO_G4_DPD_STATUS_0) \
_op_(PMC_IMPL_IO_G5_DPD_REQ_0) \
_op_(PMC_IMPL_IO_G5_DPD_STATUS_0) \
_op_(PMC_IMPL_IO_SDMMC1_HV_DPD_REQ_0) \
_op_(PMC_IMPL_IO_SDMMC1_HV_DPD_STATUS_0) \
_op_(PMC_IMPL_IO_EDP_DPD_REQ_0) \
_op_(PMC_IMPL_IO_EDP_DPD_STATUS_0) \
_op_(PMC_IMPL_IO_UFS_DPD_REQ_0) \
_op_(PMC_IMPL_IO_UFS_DPD_STATUS_0) \
_op_(PMC_IMPL_IO_PEX_CTL_A_DPD_REQ_0) \
_op_(PMC_IMPL_IO_PEX_CTL_A_DPD_STATUS_0) \
_op_(PMC_IMPL_IO_QSPI_DPD_REQ_0) \
_op_(PMC_IMPL_IO_QSPI_DPD_STATUS_0) \
_op_(PMC_IMPL_IO_G7_DPD_REQ_0) \
_op_(PMC_IMPL_IO_G7_DPD_STATUS_0) \
_op_(PMC_IMPL_IO_AO_HV_DPD_REQ_0) \
_op_(PMC_IMPL_IO_AO_HV_DPD_STATUS_0) \
_op_(PMC_IMPL_IO_AO_HV_DPD_OFF_MASK_0) \
_op_(PMC_IMPL_IO_EQOS_DPD_REQ_0) \
_op_(PMC_IMPL_IO_EQOS_DPD_STATUS_0) \
_op_(PMC_IMPL_IO_PEX_CTL_B_DPD_REQ_0) \
_op_(PMC_IMPL_IO_PEX_CTL_B_DPD_STATUS_0) \
_op_(PMC_IMPL_IO_PEX_CTL_C_DPD_REQ_0) \
_op_(PMC_IMPL_IO_PEX_CTL_C_DPD_STATUS_0) \
_op_(PMC_IMPL_IO_PEX_CLK_C_DPD_REQ_0) \
_op_(PMC_IMPL_IO_PEX_CLK_C_DPD_STATUS_0) \
_op_(PMC_IMPL_IO_PEX_CLK_A_DPD_REQ_0) \
_op_(PMC_IMPL_IO_PEX_CLK_A_DPD_STATUS_0) \
_op_(PMC_IMPL_IO_PEX_CLK_B_DPD_REQ_0) \
_op_(PMC_IMPL_IO_PEX_CLK_B_DPD_STATUS_0) \
_op_(PMC_IMPL_IO_CSI_DPD_REQ_0) \
_op_(PMC_IMPL_IO_CSI_DPD_STATUS_0) \
_op_(PMC_IMPL_IO_EMMC_DPD_REQ_0) \
_op_(PMC_IMPL_IO_EMMC_DPD_STATUS_0) \
_op_(PMC_IMPL_IO_DISP_DPD_REQ_0) \
_op_(PMC_IMPL_IO_DISP_DPD_STATUS_0) \


//
// ADDRESS SPACES
//

#define BASE_ADDRESS_PMC_IMPL   0x00000000

//
// ARPMC_IMPL_PUBLIC REGISTER BANKS
//

#define PMC_IMPL0_FIRST_REG 0x0000 // PMC_IMPL_CNTRL_0
#define PMC_IMPL0_LAST_REG 0x0004 // PMC_IMPL_SLCG_CTRL_0
#define PMC_IMPL1_FIRST_REG 0x0030 // PMC_IMPL_BLINK_TIMER_0
#define PMC_IMPL1_LAST_REG 0x0030 // PMC_IMPL_BLINK_TIMER_0
#define PMC_IMPL2_FIRST_REG 0x003c // PMC_IMPL_E_18V_PWR_0
#define PMC_IMPL2_LAST_REG 0x0040 // PMC_IMPL_E_33V_PWR_0
#define PMC_IMPL3_FIRST_REG 0x0060 // PMC_IMPL_OSC_EDPD_OVER_0
#define PMC_IMPL3_LAST_REG 0x0064 // PMC_IMPL_CLK_OUT_CNTRL_0
#define PMC_IMPL4_FIRST_REG 0x006c // PMC_IMPL_SENSOR_CTRL_0
#define PMC_IMPL4_LAST_REG 0x0074 // PMC_IMPL_IO_DPD_REQ_0
#define PMC_IMPL5_FIRST_REG 0x00bc // PMC_IMPL_SEL_DPD_TIM_0
#define PMC_IMPL5_LAST_REG 0x00bc // PMC_IMPL_SEL_DPD_TIM_0
#define PMC_IMPL6_FIRST_REG 0x00d4 // PMC_IMPL_TSC_MULT_0
#define PMC_IMPL6_LAST_REG 0x00d4 // PMC_IMPL_TSC_MULT_0
#define PMC_IMPL7_FIRST_REG 0x00f8 // PMC_IMPL_CNTRL2_0
#define PMC_IMPL7_LAST_REG 0x00f8 // PMC_IMPL_CNTRL2_0
#define PMC_IMPL8_FIRST_REG 0x010c // PMC_IMPL_RAMDUMP_CTL_STATUS_0
#define PMC_IMPL8_LAST_REG 0x010c // PMC_IMPL_RAMDUMP_CTL_STATUS_0
#define PMC_IMPL9_FIRST_REG 0x0114 // PMC_IMPL_RST_REQ_CONFIG_0
#define PMC_IMPL9_LAST_REG 0x0118 // PMC_IMPL_RST_REQ_CNTVAL_0
#define PMC_IMPL10_FIRST_REG 0x0208 // PMC_IMPL_PART_AUD_POWER_GATE_CONTROL_0
#define PMC_IMPL10_LAST_REG 0x0210 // PMC_IMPL_PART_AUD_CLAMP_CONTROL_0
#define PMC_IMPL11_FIRST_REG 0x0220 // PMC_IMPL_PART_DISP_POWER_GATE_CONTROL_0
#define PMC_IMPL11_LAST_REG 0x0228 // PMC_IMPL_PART_DISP_CLAMP_CONTROL_0
#define PMC_IMPL12_FIRST_REG 0x0298 // PMC_IMPL_PART_VIC_POWER_GATE_CONTROL_0
#define PMC_IMPL12_LAST_REG 0x02c4 // PMC_IMPL_PART_XUSBC_CLAMP_CONTROL_0
#define PMC_IMPL13_FIRST_REG 0x0388 // PMC_IMPL_PART_AOPG_TCM0_POWER_GATE_CONTROL_0
#define PMC_IMPL13_LAST_REG 0x0408 // PMC_IMPL_PART_AOPG_CAN1_CLAMP_CONTROL_0
#define PMC_IMPL14_FIRST_REG 0x0424 // PMC_IMPL_PART_PCIEX8A_POWER_GATE_CONTROL_0
#define PMC_IMPL14_LAST_REG 0x0444 // PMC_IMPL_PART_PCIEX1A_CLAMP_CONTROL_0
#define PMC_IMPL15_FIRST_REG 0x0454 // PMC_IMPL_PART_PCIEX8B_POWER_GATE_CONTROL_0
#define PMC_IMPL15_LAST_REG 0x045c // PMC_IMPL_PART_PCIEX8B_CLAMP_CONTROL_0
#define PMC_IMPL16_FIRST_REG 0x0478 // PMC_IMPL_PART_DLAA_POWER_GATE_CONTROL_0
#define PMC_IMPL16_LAST_REG 0x048c // PMC_IMPL_PART_DLAB_CLAMP_CONTROL_0
#define PMC_IMPL17_FIRST_REG 0x04c0 // PMC_IMPL_PART_ISP_POWER_GATE_CONTROL_0
#define PMC_IMPL17_LAST_REG 0x0588 // PMC_IMPL_PART_MGBEBC_CLAMP_CONTROL_0
#define PMC_IMPL18_FIRST_REG 0x05c8 // PMC_IMPL_PART_DBBRAM_POWER_GATE_CONTROL_0
#define PMC_IMPL18_LAST_REG 0x06c0 // PMC_IMPL_PART_EMCAA_PWRDWN_ACK_STATUS_0
#define PMC_IMPL19_FIRST_REG 0x06dc // PMC_IMPL_SW_OVERRIDE_CTRL_1_0
#define PMC_IMPL19_LAST_REG 0x06e4 // PMC_IMPL_MISC_CTRL_0
#define PMC_IMPL20_FIRST_REG 0x0800 // PMC_IMPL_PMC2LIC_INTR_STATUS_0
#define PMC_IMPL20_LAST_REG 0x0804 // PMC_IMPL_PMC2LIC_INTR_ENABLE_0
#define PMC_IMPL21_FIRST_REG 0x081c // PMC_IMPL_RAMDUMP_FIQ_EXIT_0
#define PMC_IMPL21_LAST_REG 0x0824 // PMC_IMPL_CLR_RAMDUMP_FIQ_EXIT_0
#define PMC_IMPL22_FIRST_REG 0x0864 // PMC_IMPL_FMON_THRESHOLD_HIGH_OSCnFUSE_CK_0
#define PMC_IMPL22_LAST_REG 0x089c // PMC_IMPL_FMON_CNTR_OVERFLOW_CTRL_OSCnFUSE_CK_0
#define PMC_IMPL23_FIRST_REG 0x08bc // PMC_IMPL_RST_REQ_TIMER_0
#define PMC_IMPL23_LAST_REG 0x08bc // PMC_IMPL_RST_REQ_TIMER_0
#define PMC_IMPL24_FIRST_REG 0x08c4 // PMC_IMPL_PMC_RESET_DETECTOR_0
#define PMC_IMPL24_LAST_REG 0x08e0 // PMC_IMPL_DPD_AUX_CLAMP_0
#define PMC_IMPL25_FIRST_REG 0xe014 // PMC_IMPL_IO_SYS_DPD_REQ_0
#define PMC_IMPL25_LAST_REG 0xe0d4 // PMC_IMPL_IO_DISP_DPD_STATUS_0
#define PMC_IMPL26_FIRST_REG 0xf014 // PMC_IMPL_POD_GLOBAL_MONITOR_0
#define PMC_IMPL26_LAST_REG 0xf01c // PMC_IMPL_POD_BE_MONITOR_0

// To satisfy various compilers and platforms,
// we let users control the types and syntax of certain constants, using macros.
#ifndef MK_SHIFT_CONST
  #define MK_SHIFT_CONST(_constant_) (_constant_ ## U)
#endif
#ifndef MK_MASK_CONST
  #define MK_MASK_CONST(_constant_) (_constant_ ## U)
#endif
#ifndef MK_ENUM_CONST
  #define MK_ENUM_CONST(_constant_) (_constant_ ## U)
#endif
#ifndef MK_ADDR_CONST
  #define MK_ADDR_CONST(_constant_) (_constant_ ## U)
#endif
#ifndef MK_FIELD_CONST
  #define MK_FIELD_CONST(_mask_, _shift_) (MK_MASK_CONST(_mask_) <<  _shift_)
#endif
#ifndef MK_SHIFT_CONST_64
  #define MK_SHIFT_CONST_64(_constant_) (_constant_ ## U)
#endif
#ifndef MK_MASK_CONST_64
  #define MK_MASK_CONST_64(_constant_) (_constant_ ## UL)
#endif
#ifndef MK_ENUM_CONST_64
  #define MK_ENUM_CONST_64(_constant_) (_constant_ ## UL)
#endif
#ifndef MK_ADDR_CONST_64
  #define MK_ADDR_CONST_64(_constant_) (_constant_ ## U)
#endif
#ifndef MK_FIELD_CONST_64
  #define MK_FIELD_CONST_64(_mask_, _shift_) (MK_MASK_CONST_64(_mask_) <<  _shift_)
#endif

#endif // ifndef ARPMC_IMPL_PUBLIC_H_INC
