/* _NVRM_COPYRIGHT_BEGIN_
 *
 * Copyright 2018-2021 by NVIDIA Corporation.  All rights reserved.  All
 * information contained herein is proprietary and confidential to NVIDIA
 * Corporation.  Any use, reproduction, or disclosure without the written
 * permission of NVIDIA Corporation is prohibited.
 *
 * _NVRM_COPYRIGHT_END_
 */

/* Compiler headers */
#include <stdint.h>                        // for uint32_t
#include <stddef.h>                        // for size_t

/* Early FSP headers */
#include <misc/ct-assert.h>                // for CT_ASSERT

/* Hardware headers */

/* Late FSP headers */
#include <misc/attributes.h>               // for UNUSED_NONCONST_PTR
#include <misc/bitops.h>                   // for BIT, EXTRACT, FSP__MISC__B...
#include <misc/macros.h>                   // for START_RFD_BLOCK, END_RFD_BLOCK, INLINE_RFD
#include <misc/nvmisc_drf.h>               // for DRF macros
#include <cpu/type-conversion.h>           // for fsp_c_v_ptr_to_uptr, FSP...

/* Module-specific FSP headers */
#include <cpu/csr.h>                       // for CSR macros
#include <cpu/cache.h>                     // for FSP__CPU__CACHE_H

/*
 * Compile-time check for FSP header files
 *   Each FSP header file contains a signature unique to that file, and the
 *   FSP project.  The CT_ASSERT macro (contained in misc/ct-assert.h) can
 *   check for this signature.  If it does not exist, then the build will
 *   abort.
 *
 *   This is a trap for projects which have their own include files of the
 *   same names, but different contents.  This trap ensures that only the
 *   files from the FSP project, are built into the FSP source code.
 */
START_RFD_BLOCK(MISRA, DEVIATE, Rule_1_2, "Approval: Bug 200531996, DR: SWE-FSP-009-SWSADR.docx",
                MISRA, DEVIATE, Directive_4_9, "Approval: Bug 200531995, DR: SWE-FSP-012-SWSADR.docx")
CT_ASSERT(FSP__MISC__ATTRIBUTES_H, "Header file missing or invalid.")
CT_ASSERT(FSP__MISC__BITOPS_H, "Header file missing or invalid.")
CT_ASSERT(FSP__MISC__MACROS_H, "Header file missing or invalid.")
CT_ASSERT(FSP__MISC__NVMISC_DRF_H, "Header file missing or invalid.")
CT_ASSERT(FSP__CPU__TYPE_CONVERSION_H, "Header file missing or invalid.")
CT_ASSERT(FSP__CPU__CSR_H, "Header file missing or invalid.")
CT_ASSERT(FSP__CPU__CACHE_H, "Header file missing or invalid.")
END_RFD_BLOCK(MISRA, DEVIATE, Rule_1_2, "Approval: Bug 200531996, DR: SWE-FSP-009-SWSADR.docx",
              MISRA, DEVIATE, Directive_4_9, "Approval: Bug 200531995, DR: SWE-FSP-012-SWSADR.docx")


/**
 * @copydoc icache_invalicate_all
 */
void icache_invalidate_all(void)
{
    __asm__ volatile("fence.i");
}

/**
 * @copydoc dcache_invalidate
 */
void dcache_invalidate(void * const base, const size_t length)
{
    uintptr_t start;
    uintptr_t end;

    start = fsp_v_ptr_to_uptr(base);
    end = start + ((uintptr_t)length);

    start = (start & DRF_SHIFTMASK64(NV_RISCV_CSR_XDCACHEOP_ADDR)) |
                DRF_DEF64(_RISCV_CSR, _XDCACHEOP, _ADDR_MODE, _VA) |
                DRF_DEF64(_RISCV_CSR, _XDCACHEOP, _MODE, _INV_LINE);

    for (;start < end; start += RISCV_CACHE_LINE_SIZE)
    {
        __asm__ volatile("csrrw x0, %0, %1" : :"i"(NV_RISCV_CSR_XDCACHEOP), "r"(start));
    }
}

/**
 * @copydoc dcache_invalidate_address_type
 */
void dcache_invalidate_address_type(void * const base, const size_t length, ADDRESS_TYPE address_type)
{
    uintptr_t start;
    uintptr_t end;

    start = fsp_v_ptr_to_uptr(base);
    end = start + ((uintptr_t)length);

    start = (start & DRF_SHIFTMASK64(NV_RISCV_CSR_XDCACHEOP_ADDR)) |
                DRF_DEF64(_RISCV_CSR, _XDCACHEOP, _MODE, _INV_LINE);

    // Set address mode depending address_type
    if ( address_type == RISCV_ADDRESS_TYPE_VA)
    {
        start |= DRF_DEF64(_RISCV_CSR, _XDCACHEOP, _ADDR_MODE, _VA);
    }
    else if ( address_type == RISCV_ADDRESS_TYPE_PA )
    {
        start |= DRF_DEF64(_RISCV_CSR, _XDCACHEOP, _ADDR_MODE, _PA);
    }
    else
    {
        // Do nothing.
    }

    for (;start < end; start += RISCV_CACHE_LINE_SIZE)
    {
        __asm__ volatile("csrrw x0, %0, %1" : :"i"(NV_RISCV_CSR_XDCACHEOP), "r"(start));
    }
}

/**
 * @copydoc dcache_invalidate_all
 */
void dcache_invalidate_all(void)
{
    __asm__ volatile("csrrw x0, %0, %1" : :"i"(NV_RISCV_CSR_XDCACHEOP), "r"(0));
}

/**
 * @copydoc cache_invalidate
 */
void cache_invalidate(void * const base, const size_t length)
{
    uintptr_t start;
    uintptr_t end;

    start = fsp_v_ptr_to_uptr(base);
    end = start + ((uintptr_t)length);

    start = (start & DRF_SHIFTMASK64(NV_RISCV_CSR_XDCACHEOP_ADDR)) |
                DRF_DEF64(_RISCV_CSR, _XDCACHEOP, _ADDR_MODE, _VA) |
                DRF_DEF64(_RISCV_CSR, _XDCACHEOP, _MODE, _INV_LINE);

    for (;start < end; start += RISCV_CACHE_LINE_SIZE)
    {
        __asm__ volatile("csrrw x0, %0, %1" : :"i"(NV_RISCV_CSR_XDCACHEOP), "r"(start));
    }
}
