#ifndef ARDEV_T_AHCI_H_
#define ARDEV_T_AHCI_H_

// generated by manual_ref_to_h.py from dev_t_ahci.ref - do not edit

//
// Copyright (c) 2011 NVIDIA Corporation.
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are met:
//
// Redistributions of source code must retain the above copyright notice,
// this list of conditions and the following disclaimer.
//
// Redistributions in binary form must reproduce the above copyright notice,
// this list of conditions and the following disclaimer in the documentation
// and/or other materials provided with the distribution.
//
// Neither the name of the NVIDIA Corporation nor the names of its contributors
// may be used to endorse or promote products derived from this software
// without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS AS IS
// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
// POSSIBILITY OF SUCH DAMAGE.
// 
// 
// 
// 
// 
// 
// 
// 
// 
//                            MCP65 AHCI Reference Manual
// 
//                       Amit Rao (arao@nvidia.com)
// 
//                                NVidia Corporation
// 
//                               2701 San Tomas Expwy
// 
//                              Santa Clara, CA  95050
// 
// 
// 
// 
//                    $Id: //hw/mcp65/manuals/dev_t_ahci.ref#1 $
//                               $Date: 2005/09/30 $
// 
// 
// 
// 
// 
// 
// 
// 
// 
// 
// 
// 
// 
// 
// 
// 
// 
// 
// 
// This Document contains unpublished, proprietary information and describes
// subject matter proprietary to NVidia Corporation.  This document may not be
// disclosed to third parties or copied or duplicated in any form without the
// prior written consent of NVidia Corporation.
// 
// 
// 
// 
// CONTENTS
// 
// Chapter  1  -  Introduction
// 
// Chapter  2  -  Boot Registers
// 
// Chapter  3  -  Delay Registers
// 
// Chapter  4  -  Debug Registers
// 
// Chapter  5  -  Green Registers
// 
// Chapter  6  -  Interrupt Registers
// 
// Chapter  7  -  Context Switching Registers
// 
// Chapter  8  -  Configuration Registers
// 
// Chapter  9  -  Real Mode Control Registers
// 
// 
// 
// Appendix A  -  SATA Register Memory Map
// 
// Appendix B  -  Address Filtering
// 
// Appendix C  -  MDIO Read/Write Sequences
// 
// Appendix D  -  Issues
// 
// Appendix E  -  Key
// 
// 
// 
// 
// 
// 1  -  INTRODUCTION
// 
// The SATA is a PCI device that complies with Ultra ATA-100 specification
// standard.
// 
// 
// 
// 2  -  BOOT REGISTERS
// The BOOT registers are used to configure each of the devices in NV at
// reset.  These register are not normally changed after reset.  Only the BIOS
// should access these registers.
// 
// Only one boot register is defined: Device_Enable. This register bit will
// reside in another block of the device. This register bit will control whether
// the FPCI (and interfaced device) is "seen" by the system.
// 
// There currently are no boot registers (0x0000).
// 
// 
// 
// 
// 3  -  DELAY REGISTERS
// 
// The DELAY registers allow the output signals to be shifted in time with
// respect to the clock.  Only the BIOS should access these registers.
// 
// There currently are no delay registers (0x0040).
// 
// 
// 
// 
// 4  -  DEBUG REGISTERS
// 
// The DEBUG registers are used to reconfigure NV during debug or chip
// testing.  These registers may contain function disable bits and hidden
// context.  Only the BIOS should access these registers.
// 
// 
// There currently are no DEBUG registers (0x0080).
// 
// 5  -  GREEN REGISTERS
// 
// The GREEN registers control power down levels for each of the devices in
// MCP1.  Only the BIOS should access these registers.
// 
// There currently are no green registers (0x00c0).
// 
// 
// 6  -  INTERRUPT REGISTERS
// 
// The interrupt registers control the interrupts for the local devices.
// 
// There currently are no interrupt registers (0x00c0).
// 
// 
// 
// 7  -  CONTEXT SWITCHING REGISTERS
// 
// The context switching registers control the context switching of the
// local user devices.
// 
// There currently are no context switching registers (0x0180).
// 
// 
// 
// 
// 8  -  CONFIGURATION REGISTERS
// 
// The CONFIG registers are used to configure each of the devices in MCP1
// after reset.
// 
// 
//      There currently are no config registers (0x0180).
// 
// 9  -  REAL MODE CONTROL REGISTERS
// 
// The Real Mode Control Registers provide device control after initial
// configuration.
// 
// .PUBLIC
// 
// .SECTION mem_bar AHCI Controller Registers
// 
// 
#define BASE_ADDRESS_AHCI                                  0x00000000                                                                       // 0x000010FF:0x00000000 RW--D
// 
// This manual describes SATA BAR5 registers. These registers are memory mapped.
// 
// .SUBSECTION Generic Host Control Registers
// 
// .TITLE HBA_CAP (Host Bus Adaptor) Capabilities
//        This register indicates basic capabilities to Software.
// 
// .FIELD NP
// Number of ports. This is zero based value indicating maximum number of ports that is supported by the Host Bus Adapter. 1 port is the minimum requirement and a max of 32 (if not supporting command completion coalescing feature).
// .FIELD SXS
// Supports External Sata. This field indicates presence of 1 or many ports with the controller which support signal only connector for Serial ATA ports. The software should check the T_AHCI_PORT_PXCMD_ESP bit to find which port actually supports signal only connector.
// .FIELD EMS
// Enclosure Management Support. If set to 1 it indicates the capability of the controller to support enclosure management. If it is not set then T_AHCI_HBA_EM_LOC and T_AHCI_HBA_EM_CTL are not implemented by the device.
// .FIELD CCCS
// Command Completion Coalescing Support. If set to 1 it indicates that the controller supports command completion coalescing feature. If it is not set then T_AHCI_HBA_CCC_CTL and T_AHCI_HBA_CCC_PORTS are not implemented by the device.
// .FIELD NCS
// Number of Command Slots. This is a zero based value indicating the number of commands that can be cached in each of the ports implemented. Minimum number of command slots is 1 and maximum being 32.
// .FIELD PSC
// Supports Partial State. This field indicates HBA supports transitions to the partial state to manage power. WHen set to 1 HBA and device initiated Partial requests can be supported.
// .FIELD SSC
// Supports Slumber State. This field indicates HBA supports transitions to the slumber state to manage power. WHen set to 1 HBA and device initiated Slumber requests can be supported.
// .FIELD PMD
// PIO Multiple DRQ Block. If set to '1' the HBA supports multiple DRQ block data transfers for the PIO command protocol.
// .FIELD FBSS
// FIS Based Switching Supported. When set to '1' indicates that the HBA supports Port Multiplier FIS-Based switiching.
// .FIELD SPM
// Supports Port Multiplier. When set to '1' indicates that a port multiplier with command based switching is supported.
// .FIELD SAM
// Supports AHCI mode only. When set to '1' indicates that the SATA controller doesnot implement a legacy, task-file based register interface. When cleared indicates that controller supports legacy mechanism in addition to AHCI mode.
// .FIELD SNZO
// Supports Non-Zero DMA Offsets. When set to '1' indicates that the HBA can support non-zero DMA offsets for DMA setup FISes.
// .FIELD ISS
// Interface Speed Supported. Indicates the maximum interface speed supported by the ports.
// .FIELD SCLO
// Supports Command List Override. When set to '1' HBA supports the T_AHCI_PORT_PXCMD_CLO nit and its associated functionality. When cleared to '0' the HBA is not capable of clearing the BSY and DRQ bits in the status register in order to issue a software reset if these bits are still set from a previous operation.
// .FIELD SAL
// Supports Activity LED. When set to '1' the HBA supports a single activity indication output pin.
// .FIELD SALP
// Supports Aggressive Link Power Management. When set to '1' the HBA can support auto-generating link requests to the Partial or Slumber states when there are no commands to process.
// .FIELD SSS
// Supports Staggered Spin-up. When set to '1' the HBA supports staggered spin-up on its ports, for use in balancing power spikes. This needs to be set by BIOS.
// .FIELD SMPS
// Supports Mechanical Presence Switch.
// .FIELD SSNTF
// .FIELD SNCQ
// .FIELD S64A
// 31           24 23           16 15            8 7             0
// .-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-.
// |0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0| HBA_CAP
// `-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-'
// 
#define AHCI_HBA_CAP_0                                     0x00000000                                                                       // R-I4R
#define AHCI_HBA_CAP_0_SECURE                              0
#define AHCI_HBA_CAP_0_WORD_COUNT                          1
#define AHCI_HBA_CAP_0_RESET_VAL                           0x0
#define AHCI_HBA_CAP_0_RESET_MASK                          0x0
#define AHCI_HBA_CAP_0_SW_DEFAULT_VAL                      0x0
#define AHCI_HBA_CAP_0_SW_DEFAULT_MASK                     0x0
#define AHCI_HBA_CAP_0_READ_MASK                           0xffffffff
#define AHCI_HBA_CAP_0_WRITE_MASK                          0x0
#define AHCI_HBA_CAP_0_NP_SHIFT                             _MK_SHIFT_CONST(0)                                                              // R-CVF
#define AHCI_HBA_CAP_0_NP_FIELD                            (_MK_SHIFT_CONST(0x1f) << AHCI_HBA_CAP_0_NP_SHIFT)
#define AHCI_HBA_CAP_0_NP_RANGE                            4:0
#define AHCI_HBA_CAP_0_NP_WOFFSET                          0
#define AHCI_HBA_CAP_0_NP_1                                _MK_ENUM_CONST(0x00000000)                                                       // R---V
#define AHCI_HBA_CAP_0_NP_2                                _MK_ENUM_CONST(0x00000001)                                                       // R---V
#define AHCI_HBA_CAP_0_NP_3                                _MK_ENUM_CONST(0x00000002)                                                       // R---V
#define AHCI_HBA_CAP_0_NP_4                                _MK_ENUM_CONST(0x00000003)                                                       // R---V
#define AHCI_HBA_CAP_0_SXS_SHIFT                            _MK_SHIFT_CONST(5)                                                              // R-CVF
#define AHCI_HBA_CAP_0_SXS_FIELD                           (_MK_SHIFT_CONST(0x1) << AHCI_HBA_CAP_0_SXS_SHIFT)
#define AHCI_HBA_CAP_0_SXS_RANGE                           5:5
#define AHCI_HBA_CAP_0_SXS_WOFFSET                         0
#define AHCI_HBA_CAP_0_SXS_TRUE                            _MK_ENUM_CONST(0x00000001)                                                       // R---V
#define AHCI_HBA_CAP_0_SXS_FALSE                           _MK_ENUM_CONST(0x00000000)                                                       // R-C-V
#define AHCI_HBA_CAP_0_EMS_SHIFT                            _MK_SHIFT_CONST(6)                                                              // R-CVF
#define AHCI_HBA_CAP_0_EMS_FIELD                           (_MK_SHIFT_CONST(0x1) << AHCI_HBA_CAP_0_EMS_SHIFT)
#define AHCI_HBA_CAP_0_EMS_RANGE                           6:6
#define AHCI_HBA_CAP_0_EMS_WOFFSET                         0
#define AHCI_HBA_CAP_0_EMS_TRUE                            _MK_ENUM_CONST(0x00000001)                                                       // R---V
#define AHCI_HBA_CAP_0_EMS_FALSE                           _MK_ENUM_CONST(0x00000000)                                                       // R-C-V
#define AHCI_HBA_CAP_0_CCCS_SHIFT                           _MK_SHIFT_CONST(7)                                                              // R-CVF
#define AHCI_HBA_CAP_0_CCCS_FIELD                          (_MK_SHIFT_CONST(0x1) << AHCI_HBA_CAP_0_CCCS_SHIFT)
#define AHCI_HBA_CAP_0_CCCS_RANGE                          7:7
#define AHCI_HBA_CAP_0_CCCS_WOFFSET                        0
#define AHCI_HBA_CAP_0_CCCS_TRUE                           _MK_ENUM_CONST(0x00000001)                                                       // R---V
#define AHCI_HBA_CAP_0_CCCS_FALSE                          _MK_ENUM_CONST(0x00000000)                                                       // R-C-V
#define AHCI_HBA_CAP_0_NCS_SHIFT                            _MK_SHIFT_CONST(8)                                                              // R-CVF
#define AHCI_HBA_CAP_0_NCS_FIELD                           (_MK_SHIFT_CONST(0x1f) << AHCI_HBA_CAP_0_NCS_SHIFT)
#define AHCI_HBA_CAP_0_NCS_RANGE                           12:8
#define AHCI_HBA_CAP_0_NCS_WOFFSET                         0
#define AHCI_HBA_CAP_0_NCS_1                               _MK_ENUM_CONST(0x00000000)                                                       // R---V
#define AHCI_HBA_CAP_0_NCS_8                               _MK_ENUM_CONST(0x00000007)                                                       // R---V
#define AHCI_HBA_CAP_0_NCS_16                              _MK_ENUM_CONST(0x0000000F)                                                       // R---V
#define AHCI_HBA_CAP_0_NCS_32                              _MK_ENUM_CONST(0x0000001F)                                                       // R-C-V
#define AHCI_HBA_CAP_0_PSC_SHIFT                            _MK_SHIFT_CONST(13)                                                             // R-CVF
#define AHCI_HBA_CAP_0_PSC_FIELD                           (_MK_SHIFT_CONST(0x1) << AHCI_HBA_CAP_0_PSC_SHIFT)
#define AHCI_HBA_CAP_0_PSC_RANGE                           13:13
#define AHCI_HBA_CAP_0_PSC_WOFFSET                         0
#define AHCI_HBA_CAP_0_PSC_TRUE                            _MK_ENUM_CONST(0x00000001)                                                       // R-C-V
#define AHCI_HBA_CAP_0_PSC_FALSE                           _MK_ENUM_CONST(0x00000000)                                                       // R---V
#define AHCI_HBA_CAP_0_SSC_SHIFT                            _MK_SHIFT_CONST(14)                                                             // R-CVF
#define AHCI_HBA_CAP_0_SSC_FIELD                           (_MK_SHIFT_CONST(0x1) << AHCI_HBA_CAP_0_SSC_SHIFT)
#define AHCI_HBA_CAP_0_SSC_RANGE                           14:14
#define AHCI_HBA_CAP_0_SSC_WOFFSET                         0
#define AHCI_HBA_CAP_0_SSC_TRUE                            _MK_ENUM_CONST(0x00000001)                                                       // R-C-V
#define AHCI_HBA_CAP_0_SSC_FALSE                           _MK_ENUM_CONST(0x00000000)                                                       // R---V
#define AHCI_HBA_CAP_0_PMD_SHIFT                            _MK_SHIFT_CONST(15)                                                             // R-CVF
#define AHCI_HBA_CAP_0_PMD_FIELD                           (_MK_SHIFT_CONST(0x1) << AHCI_HBA_CAP_0_PMD_SHIFT)
#define AHCI_HBA_CAP_0_PMD_RANGE                           15:15
#define AHCI_HBA_CAP_0_PMD_WOFFSET                         0
#define AHCI_HBA_CAP_0_PMD_SUPPORTED                       _MK_ENUM_CONST(0x00000001)                                                       // R-C-V
#define AHCI_HBA_CAP_0_PMD_NOT_SUPPORTED                   _MK_ENUM_CONST(0x00000000)                                                       // R---V
#define AHCI_HBA_CAP_0_FBSS_SHIFT                           _MK_SHIFT_CONST(16)                                                             // R-CVF
#define AHCI_HBA_CAP_0_FBSS_FIELD                          (_MK_SHIFT_CONST(0x1) << AHCI_HBA_CAP_0_FBSS_SHIFT)
#define AHCI_HBA_CAP_0_FBSS_RANGE                          16:16
#define AHCI_HBA_CAP_0_FBSS_WOFFSET                        0
#define AHCI_HBA_CAP_0_FBSS_TRUE                           _MK_ENUM_CONST(0x00000001)                                                       // R---V
#define AHCI_HBA_CAP_0_FBSS_FALSE                          _MK_ENUM_CONST(0x00000000)                                                       // R-C-V
#define AHCI_HBA_CAP_0_SPM_SHIFT                            _MK_SHIFT_CONST(17)                                                             // R-CVF
#define AHCI_HBA_CAP_0_SPM_FIELD                           (_MK_SHIFT_CONST(0x1) << AHCI_HBA_CAP_0_SPM_SHIFT)
#define AHCI_HBA_CAP_0_SPM_RANGE                           17:17
#define AHCI_HBA_CAP_0_SPM_WOFFSET                         0
#define AHCI_HBA_CAP_0_SPM_TRUE                            _MK_ENUM_CONST(0x00000001)                                                       // R---V
#define AHCI_HBA_CAP_0_SPM_FALSE                           _MK_ENUM_CONST(0x00000000)                                                       // R-C-V
#define AHCI_HBA_CAP_0_SAM_SHIFT                            _MK_SHIFT_CONST(18)                                                             // R-CVF
#define AHCI_HBA_CAP_0_SAM_FIELD                           (_MK_SHIFT_CONST(0x1) << AHCI_HBA_CAP_0_SAM_SHIFT)
#define AHCI_HBA_CAP_0_SAM_RANGE                           18:18
#define AHCI_HBA_CAP_0_SAM_WOFFSET                         0
#define AHCI_HBA_CAP_0_SAM_TRUE                            _MK_ENUM_CONST(0x00000001)                                                       // R---V
#define AHCI_HBA_CAP_0_SAM_FALSE                           _MK_ENUM_CONST(0x00000000)                                                       // R-C-V
#define AHCI_HBA_CAP_0_SNZO_SHIFT                           _MK_SHIFT_CONST(19)                                                             // R-CVF
#define AHCI_HBA_CAP_0_SNZO_FIELD                          (_MK_SHIFT_CONST(0x1) << AHCI_HBA_CAP_0_SNZO_SHIFT)
#define AHCI_HBA_CAP_0_SNZO_RANGE                          19:19
#define AHCI_HBA_CAP_0_SNZO_WOFFSET                        0
#define AHCI_HBA_CAP_0_SNZO_TRUE                           _MK_ENUM_CONST(0x00000001)                                                       // R---V
#define AHCI_HBA_CAP_0_SNZO_FALSE                          _MK_ENUM_CONST(0x00000000)                                                       // R-C-V
#define AHCI_HBA_CAP_0_ISS_SHIFT                            _MK_SHIFT_CONST(20)                                                             // R-CVF
#define AHCI_HBA_CAP_0_ISS_FIELD                           (_MK_SHIFT_CONST(0xf) << AHCI_HBA_CAP_0_ISS_SHIFT)
#define AHCI_HBA_CAP_0_ISS_RANGE                           23:20
#define AHCI_HBA_CAP_0_ISS_WOFFSET                         0
#define AHCI_HBA_CAP_0_ISS_RSVD                            _MK_ENUM_CONST(0x00000000)                                                       // R---V
#define AHCI_HBA_CAP_0_ISS_GEN1                            _MK_ENUM_CONST(0x00000001)                                                       // R---V
#define AHCI_HBA_CAP_0_ISS_GEN1_2                          _MK_ENUM_CONST(0x00000002)                                                       // R-C-V
#define AHCI_HBA_CAP_0_ISS_GEN3                            _MK_ENUM_CONST(0x00000003)                                                       // R---V
#define AHCI_HBA_CAP_0_SCLO_SHIFT                           _MK_SHIFT_CONST(24)                                                             // R-CVF
#define AHCI_HBA_CAP_0_SCLO_FIELD                          (_MK_SHIFT_CONST(0x1) << AHCI_HBA_CAP_0_SCLO_SHIFT)
#define AHCI_HBA_CAP_0_SCLO_RANGE                          24:24
#define AHCI_HBA_CAP_0_SCLO_WOFFSET                        0
#define AHCI_HBA_CAP_0_SCLO_TRUE                           _MK_ENUM_CONST(0x00000001)                                                       // R---V
#define AHCI_HBA_CAP_0_SCLO_FALSE                          _MK_ENUM_CONST(0x00000000)                                                       // R-C-V
#define AHCI_HBA_CAP_0_SAL_SHIFT                            _MK_SHIFT_CONST(25)                                                             // R-CVF
#define AHCI_HBA_CAP_0_SAL_FIELD                           (_MK_SHIFT_CONST(0x1) << AHCI_HBA_CAP_0_SAL_SHIFT)
#define AHCI_HBA_CAP_0_SAL_RANGE                           25:25
#define AHCI_HBA_CAP_0_SAL_WOFFSET                         0
#define AHCI_HBA_CAP_0_SAL_TRUE                            _MK_ENUM_CONST(0x00000001)                                                       // R-C-V
#define AHCI_HBA_CAP_0_SAL_FALSE                           _MK_ENUM_CONST(0x00000000)                                                       // R---V
#define AHCI_HBA_CAP_0_SALP_SHIFT                           _MK_SHIFT_CONST(26)                                                             // R-CVF
#define AHCI_HBA_CAP_0_SALP_FIELD                          (_MK_SHIFT_CONST(0x1) << AHCI_HBA_CAP_0_SALP_SHIFT)
#define AHCI_HBA_CAP_0_SALP_RANGE                          26:26
#define AHCI_HBA_CAP_0_SALP_WOFFSET                        0
#define AHCI_HBA_CAP_0_SALP_TRUE                           _MK_ENUM_CONST(0x00000001)                                                       // R-C-V
#define AHCI_HBA_CAP_0_SALP_FALSE                          _MK_ENUM_CONST(0x00000000)                                                       // R---V
#define AHCI_HBA_CAP_0_SSS_SHIFT                            _MK_SHIFT_CONST(27)                                                             // R-CVF
#define AHCI_HBA_CAP_0_SSS_FIELD                           (_MK_SHIFT_CONST(0x1) << AHCI_HBA_CAP_0_SSS_SHIFT)
#define AHCI_HBA_CAP_0_SSS_RANGE                           27:27
#define AHCI_HBA_CAP_0_SSS_WOFFSET                         0
#define AHCI_HBA_CAP_0_SSS_TRUE                            _MK_ENUM_CONST(0x00000001)                                                       // R---V
#define AHCI_HBA_CAP_0_SSS_FALSE                           _MK_ENUM_CONST(0x00000000)                                                       // R-C-V
#define AHCI_HBA_CAP_0_SMPS_SHIFT                           _MK_SHIFT_CONST(28)                                                             // R-CVF
#define AHCI_HBA_CAP_0_SMPS_FIELD                          (_MK_SHIFT_CONST(0x1) << AHCI_HBA_CAP_0_SMPS_SHIFT)
#define AHCI_HBA_CAP_0_SMPS_RANGE                          28:28
#define AHCI_HBA_CAP_0_SMPS_WOFFSET                        0
#define AHCI_HBA_CAP_0_SMPS_TRUE                           _MK_ENUM_CONST(0x00000001)                                                       // R---V
#define AHCI_HBA_CAP_0_SMPS_FALSE                          _MK_ENUM_CONST(0x00000000)                                                       // R-C-V
#define AHCI_HBA_CAP_0_SSNTF_SHIFT                          _MK_SHIFT_CONST(29)                                                             // R-CVF
#define AHCI_HBA_CAP_0_SSNTF_FIELD                         (_MK_SHIFT_CONST(0x1) << AHCI_HBA_CAP_0_SSNTF_SHIFT)
#define AHCI_HBA_CAP_0_SSNTF_RANGE                         29:29
#define AHCI_HBA_CAP_0_SSNTF_WOFFSET                       0
#define AHCI_HBA_CAP_0_SSNTF_TRUE                          _MK_ENUM_CONST(0x00000001)                                                       // R-C-V
#define AHCI_HBA_CAP_0_SSNTF_FALSE                         _MK_ENUM_CONST(0x00000000)                                                       // R---V
#define AHCI_HBA_CAP_0_SNCQ_SHIFT                           _MK_SHIFT_CONST(30)                                                             // R-CVF
#define AHCI_HBA_CAP_0_SNCQ_FIELD                          (_MK_SHIFT_CONST(0x1) << AHCI_HBA_CAP_0_SNCQ_SHIFT)
#define AHCI_HBA_CAP_0_SNCQ_RANGE                          30:30
#define AHCI_HBA_CAP_0_SNCQ_WOFFSET                        0
#define AHCI_HBA_CAP_0_SNCQ_TRUE                           _MK_ENUM_CONST(0x00000001)                                                       // R-C-V
#define AHCI_HBA_CAP_0_SNCQ_FALSE                          _MK_ENUM_CONST(0x00000000)                                                       // R---V
#define AHCI_HBA_CAP_0_S64A_SHIFT                           _MK_SHIFT_CONST(31)                                                             // R-CVF
#define AHCI_HBA_CAP_0_S64A_FIELD                          (_MK_SHIFT_CONST(0x1) << AHCI_HBA_CAP_0_S64A_SHIFT)
#define AHCI_HBA_CAP_0_S64A_RANGE                          31:31
#define AHCI_HBA_CAP_0_S64A_WOFFSET                        0
#define AHCI_HBA_CAP_0_S64A_TRUE                           _MK_ENUM_CONST(0x00000001)                                                       // R-C-V
#define AHCI_HBA_CAP_0_S64A_FALSE                          _MK_ENUM_CONST(0x00000000)                                                       // R---V
// 
// 
// .LABEL PRIVATE
// .LABEL PUBLIC
// 
//         Figure 9-1 HBA Capabilities Register
// 
// 
// 
// .TITLE HBA_GHC (Host Bus Adaptor) Global Host Control
//        This register indicates basic capabilities to Software.
// 
// .FIELD HR
// When set by SW, this bit causes an internal reset of the HBA. All
// state machines that relate to data transfers and queuing shall return to an idle
// condition, and all ports shall be re-initialized via COMRESET (if staggered spin-up is
// not supported). If staggered spin-up is supported, then it is the responsibility of
// software to spin-up each port after the reset has completed.
// When the HBA has performed the reset action, it shall reset this bit to 0. A software
// write of 0 shall have no effect.
// 
// .FIELD IE
// This global bit enables interrupts from the HBA. When cleared
// (reset default), all interrupt sources from all ports are disabled. When set, interrupts are
// enabled.
// 
// .FIELD MRSM
// When set to 1 by hardware, indicates that
// the HBA requested more than one MSI vector but has reverted to using the first vector
// only. When this bit is cleared to 0, the HBA has not reverted to single MSI mode (i.e.
// hardware is already in single MSI mode, software has allocated the number of
// messages requested, or hardware is sharing interrupt vectors if MC.MME < MC.MMC).
// The HBA may revert to single MSI mode when the number of vectors allocated by the
// host is less than the number requested. This bit shall only be set to 1 when the
// following conditions hold:
//  MC.MSIE = 1 (MSI is enabled)
//  MC.MMC > 0 (multiple messages requested)
//  MC.MME > 0 (more than one message allocated)
//  MC.MME != MC.MMC (messages allocated not equal to number requested)
// When this bit is set to 1, single MSI mode operation is in use and software is
// responsible for clearing bits in the IS register to clear interrupts.
// This bit shall be cleared to 0 by hardware when any of the four conditions stated is
// false. This bit is also cleared to 0 when MC.MSIE = 1 and MC.MME = 0h. In this
// case, the hardware has been programmed to use single MSI mode, and is not
// reverting to that mode.
// 
// .FIELD AE
// When set, indicates that communication to the HBA shall be via
// AHCI mechanisms. This can be used by an HBA that supports both legacy
// mechanisms (such as SFF-8038i) and AHCI to know when the HBA is running under an
// AHCI driver.
// When set, software shall only communicate with the HBA using AHCI. When cleared,
// software shall only communicate with the HBA using legacy mechanisms. When
// cleared FISes are not posted to memory and no commands are sent via AHCI
// mechanisms.
// Software shall set this bit to 1 before accessing other AHCI registers.
// The implementation of this bit is dependent upon the value of the CAP.SAM bit. If
// CAP.SAM is '0', then GHC.AE shall be read-write and shall have a reset value of '0'. If
// CAP.SAM is '1', then AE shall be read-only and shall have a reset value of '1'.
// 
// .LABEL PRIVATE
// Bug 609406: MCP89M-ENG: SATA HDD not being detected under linux.
// Issue: The bug is that when Linux AHCI driver sets GHC.HR and then sets GHC.AE
// without any delay, then it is seen that GHC.AE is not set at all.
// WAR: Add a 10ms delay after setting HR. The WAR is available from 2.6.31 or later
// Linux Kernel versions. The Kernel version from 2.6.27 - 2.6.30 does not have this delay and
// will repro the issue with MCP89.
// .LABEL PUBLIC
// 
// 31           24 23           16 15            8 7             0
// .-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-.
// |0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0| HBA_GHC
// `-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-'
// 
#define AHCI_HBA_GHC_0                                     0x00000004                                                                       // RWI4R
#define AHCI_HBA_GHC_0_SECURE                              0
#define AHCI_HBA_GHC_0_WORD_COUNT                          1
#define AHCI_HBA_GHC_0_RESET_VAL                           0x0
#define AHCI_HBA_GHC_0_RESET_MASK                          0x80000002
#define AHCI_HBA_GHC_0_SW_DEFAULT_VAL                      0x0
#define AHCI_HBA_GHC_0_SW_DEFAULT_MASK                     0x80000002
#define AHCI_HBA_GHC_0_READ_MASK                           0xffffffff
#define AHCI_HBA_GHC_0_WRITE_MASK                          0x80000003
#define AHCI_HBA_GHC_0_HR_SHIFT                             _MK_SHIFT_CONST(0)                                                              // RWWVF
#define AHCI_HBA_GHC_0_HR_FIELD                            (_MK_SHIFT_CONST(0x1) << AHCI_HBA_GHC_0_HR_SHIFT)
#define AHCI_HBA_GHC_0_HR_RANGE                            0:0
#define AHCI_HBA_GHC_0_HR_WOFFSET                          0
#define AHCI_HBA_GHC_0_HR_DEFAULT                          (_MK_MASK_CONST(0x00000000)
#define AHCI_HBA_GHC_0_HR_DEFAULT_MASK                     (_MK_MASK_CONST(0x1)
#define AHCI_HBA_GHC_0_HR_SW_DEFAULT                       (_MK_MASK_CONST(0x00000000)
#define AHCI_HBA_GHC_0_HR_SW_DEFAULT_MASK                  (_MK_MASK_CONST(0x1)
#define AHCI_HBA_GHC_0_HR_NOT                              _MK_ENUM_CONST(0x00000000)                                                       // R-W-V
#define AHCI_HBA_GHC_0_HR_TRUE                             _MK_ENUM_CONST(0x00000001)                                                       // R---V
#define AHCI_HBA_GHC_0_HR_SET                              _MK_ENUM_CONST(0x00000001)                                                       // -W--T
#define AHCI_HBA_GHC_0_IE_SHIFT                             _MK_SHIFT_CONST(1)                                                              // RWIVF
#define AHCI_HBA_GHC_0_IE_FIELD                            (_MK_SHIFT_CONST(0x1) << AHCI_HBA_GHC_0_IE_SHIFT)
#define AHCI_HBA_GHC_0_IE_RANGE                            1:1
#define AHCI_HBA_GHC_0_IE_WOFFSET                          0
#define AHCI_HBA_GHC_0_IE_DEFAULT                          (_MK_MASK_CONST(0x00000000)
#define AHCI_HBA_GHC_0_IE_DEFAULT_MASK                     (_MK_MASK_CONST(0x1)
#define AHCI_HBA_GHC_0_IE_SW_DEFAULT                       (_MK_MASK_CONST(0x00000000)
#define AHCI_HBA_GHC_0_IE_SW_DEFAULT_MASK                  (_MK_MASK_CONST(0x1)
#define AHCI_HBA_GHC_0_IE__NOPRDCHK                        _MK_ENUM_CONST(0x00000001)                                                       // ----V
#define AHCI_HBA_GHC_0_IE_TRUE                             _MK_ENUM_CONST(0x00000001)                                                       // RW--V
#define AHCI_HBA_GHC_0_IE_FALSE                            _MK_ENUM_CONST(0x00000000)                                                       // RWI-V
#define AHCI_HBA_GHC_0_MRSM_SHIFT                           _MK_SHIFT_CONST(2)                                                              // R-WVF
#define AHCI_HBA_GHC_0_MRSM_FIELD                          (_MK_SHIFT_CONST(0x1) << AHCI_HBA_GHC_0_MRSM_SHIFT)
#define AHCI_HBA_GHC_0_MRSM_RANGE                          2:2
#define AHCI_HBA_GHC_0_MRSM_WOFFSET                        0
#define AHCI_HBA_GHC_0_MRSM_DEFAULT                        (_MK_MASK_CONST(0x00000000)
#define AHCI_HBA_GHC_0_MRSM_DEFAULT_MASK                   (_MK_MASK_CONST(0x1)
#define AHCI_HBA_GHC_0_MRSM_SW_DEFAULT                     (_MK_MASK_CONST(0x00000000)
#define AHCI_HBA_GHC_0_MRSM_SW_DEFAULT_MASK                (_MK_MASK_CONST(0x1)
#define AHCI_HBA_GHC_0_MRSM_YES                            _MK_ENUM_CONST(0x00000001)                                                       // R---V
#define AHCI_HBA_GHC_0_MRSM_NO                             _MK_ENUM_CONST(0x00000000)                                                       // R-W-V
#define AHCI_HBA_GHC_0_RSVD_SHIFT                           _MK_SHIFT_CONST(3)                                                              // C--VF
#define AHCI_HBA_GHC_0_RSVD_FIELD                          (_MK_SHIFT_CONST(0xfffffff) << AHCI_HBA_GHC_0_RSVD_SHIFT)
#define AHCI_HBA_GHC_0_RSVD_RANGE                          30:3
#define AHCI_HBA_GHC_0_RSVD_WOFFSET                        0
#define AHCI_HBA_GHC_0_RSVD_VAL                            _MK_ENUM_CONST(0x00000000)                                                       // C---V
#define AHCI_HBA_GHC_0_AE_SHIFT                             _MK_SHIFT_CONST(31)                                                             // RWIVF
#define AHCI_HBA_GHC_0_AE_FIELD                            (_MK_SHIFT_CONST(0x1) << AHCI_HBA_GHC_0_AE_SHIFT)
#define AHCI_HBA_GHC_0_AE_RANGE                            31:31
#define AHCI_HBA_GHC_0_AE_WOFFSET                          0
#define AHCI_HBA_GHC_0_AE_DEFAULT                          (_MK_MASK_CONST(0x00000000)
#define AHCI_HBA_GHC_0_AE_DEFAULT_MASK                     (_MK_MASK_CONST(0x1)
#define AHCI_HBA_GHC_0_AE_SW_DEFAULT                       (_MK_MASK_CONST(0x00000000)
#define AHCI_HBA_GHC_0_AE_SW_DEFAULT_MASK                  (_MK_MASK_CONST(0x1)
#define AHCI_HBA_GHC_0_AE__NOPRDCHK                        _MK_ENUM_CONST(0x00000001)                                                       // ----V
#define AHCI_HBA_GHC_0_AE_YES                              _MK_ENUM_CONST(0x00000001)                                                       // RW--V
#define AHCI_HBA_GHC_0_AE_NO                               _MK_ENUM_CONST(0x00000000)                                                       // RWI-V
// 
// 
//              Figure 9-2 HBA Global Host Control Register
// 
// 
// 
// .TITLE HBA_IS (Host Bus Adaptor) Interrupt Status
//        This register indicates basic capabilities to Software.
// .FIELD PORTX_INTR
// If set, indicates that the corresponding port has an
// interrupt pending. Software can use this information to determine which ports require
// service after an interrupt.
// The IPS[x] bit is only defined for ports that are implemented or for the command
// completion coalescing interrupt defined by CCC_CTL.INT. All other bits are reserved.
// 
// 
// 31           24 23           16 15            8 7             0
// .-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-.
// |0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0| HBA_IS
// `-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-'
// 
#define AHCI_HBA_IS_0                                      0x00000008                                                                       // RWI4R
#define AHCI_HBA_IS_0_SECURE                               0
#define AHCI_HBA_IS_0_WORD_COUNT                           1
#define AHCI_HBA_IS_0_RESET_VAL                            0x0
#define AHCI_HBA_IS_0_RESET_MASK                           0xffffffff
#define AHCI_HBA_IS_0_SW_DEFAULT_VAL                       0x0
#define AHCI_HBA_IS_0_SW_DEFAULT_MASK                      0xffffffff
#define AHCI_HBA_IS_0_READ_MASK                            0xffffffff
#define AHCI_HBA_IS_0_WRITE_MASK                           0xffffffff
#define AHCI_HBA_IS_0_PORT0_INTR_SHIFT                      _MK_SHIFT_CONST(0)                                                              // RWIVF
#define AHCI_HBA_IS_0_PORT0_INTR_FIELD                     (_MK_SHIFT_CONST(0x1) << AHCI_HBA_IS_0_PORT0_INTR_SHIFT)
#define AHCI_HBA_IS_0_PORT0_INTR_RANGE                     0:0
#define AHCI_HBA_IS_0_PORT0_INTR_WOFFSET                   0
#define AHCI_HBA_IS_0_PORT0_INTR_DEFAULT                   (_MK_MASK_CONST(0x00000000)
#define AHCI_HBA_IS_0_PORT0_INTR_DEFAULT_MASK              (_MK_MASK_CONST(0x1)
#define AHCI_HBA_IS_0_PORT0_INTR_SW_DEFAULT                (_MK_MASK_CONST(0x00000000)
#define AHCI_HBA_IS_0_PORT0_INTR_SW_DEFAULT_MASK           (_MK_MASK_CONST(0x1)
#define AHCI_HBA_IS_0_PORT0_INTR__NOPRDCHK                 _MK_ENUM_CONST(0x00000001)                                                       // ----V
#define AHCI_HBA_IS_0_PORT0_INTR_ZERO                      _MK_ENUM_CONST(0x00000000)                                                       // R-I-V
#define AHCI_HBA_IS_0_PORT0_INTR_SET                       _MK_ENUM_CONST(0x00000001)                                                       // R---V
#define AHCI_HBA_IS_0_PORT0_INTR_CLEAR                     _MK_ENUM_CONST(0x00000001)                                                       // -W--C
#define AHCI_HBA_IS_0_PORT1_INTR_SHIFT                      _MK_SHIFT_CONST(1)                                                              // RWIVF
#define AHCI_HBA_IS_0_PORT1_INTR_FIELD                     (_MK_SHIFT_CONST(0x1) << AHCI_HBA_IS_0_PORT1_INTR_SHIFT)
#define AHCI_HBA_IS_0_PORT1_INTR_RANGE                     1:1
#define AHCI_HBA_IS_0_PORT1_INTR_WOFFSET                   0
#define AHCI_HBA_IS_0_PORT1_INTR_DEFAULT                   (_MK_MASK_CONST(0x00000000)
#define AHCI_HBA_IS_0_PORT1_INTR_DEFAULT_MASK              (_MK_MASK_CONST(0x1)
#define AHCI_HBA_IS_0_PORT1_INTR_SW_DEFAULT                (_MK_MASK_CONST(0x00000000)
#define AHCI_HBA_IS_0_PORT1_INTR_SW_DEFAULT_MASK           (_MK_MASK_CONST(0x1)
#define AHCI_HBA_IS_0_PORT1_INTR__NOPRDCHK                 _MK_ENUM_CONST(0x00000001)                                                       // ----V
#define AHCI_HBA_IS_0_PORT1_INTR_ZERO                      _MK_ENUM_CONST(0x00000000)                                                       // R-I-V
#define AHCI_HBA_IS_0_PORT1_INTR_SET                       _MK_ENUM_CONST(0x00000001)                                                       // R---V
#define AHCI_HBA_IS_0_PORT1_INTR_CLEAR                     _MK_ENUM_CONST(0x00000001)                                                       // -W--C
#define AHCI_HBA_IS_0_PORT2_INTR_SHIFT                      _MK_SHIFT_CONST(2)                                                              // RWIVF
#define AHCI_HBA_IS_0_PORT2_INTR_FIELD                     (_MK_SHIFT_CONST(0x1) << AHCI_HBA_IS_0_PORT2_INTR_SHIFT)
#define AHCI_HBA_IS_0_PORT2_INTR_RANGE                     2:2
#define AHCI_HBA_IS_0_PORT2_INTR_WOFFSET                   0
#define AHCI_HBA_IS_0_PORT2_INTR_DEFAULT                   (_MK_MASK_CONST(0x00000000)
#define AHCI_HBA_IS_0_PORT2_INTR_DEFAULT_MASK              (_MK_MASK_CONST(0x1)
#define AHCI_HBA_IS_0_PORT2_INTR_SW_DEFAULT                (_MK_MASK_CONST(0x00000000)
#define AHCI_HBA_IS_0_PORT2_INTR_SW_DEFAULT_MASK           (_MK_MASK_CONST(0x1)
#define AHCI_HBA_IS_0_PORT2_INTR__NOPRDCHK                 _MK_ENUM_CONST(0x00000001)                                                       // ----V
#define AHCI_HBA_IS_0_PORT2_INTR_ZERO                      _MK_ENUM_CONST(0x00000000)                                                       // R-I-V
#define AHCI_HBA_IS_0_PORT2_INTR_SET                       _MK_ENUM_CONST(0x00000001)                                                       // R---V
#define AHCI_HBA_IS_0_PORT2_INTR_CLEAR                     _MK_ENUM_CONST(0x00000001)                                                       // -W--C
#define AHCI_HBA_IS_0_PORT3_INTR_SHIFT                      _MK_SHIFT_CONST(3)                                                              // RWIVF
#define AHCI_HBA_IS_0_PORT3_INTR_FIELD                     (_MK_SHIFT_CONST(0x1) << AHCI_HBA_IS_0_PORT3_INTR_SHIFT)
#define AHCI_HBA_IS_0_PORT3_INTR_RANGE                     3:3
#define AHCI_HBA_IS_0_PORT3_INTR_WOFFSET                   0
#define AHCI_HBA_IS_0_PORT3_INTR_DEFAULT                   (_MK_MASK_CONST(0x00000000)
#define AHCI_HBA_IS_0_PORT3_INTR_DEFAULT_MASK              (_MK_MASK_CONST(0x1)
#define AHCI_HBA_IS_0_PORT3_INTR_SW_DEFAULT                (_MK_MASK_CONST(0x00000000)
#define AHCI_HBA_IS_0_PORT3_INTR_SW_DEFAULT_MASK           (_MK_MASK_CONST(0x1)
#define AHCI_HBA_IS_0_PORT3_INTR__NOPRDCHK                 _MK_ENUM_CONST(0x00000001)                                                       // ----V
#define AHCI_HBA_IS_0_PORT3_INTR_ZERO                      _MK_ENUM_CONST(0x00000000)                                                       // R-I-V
#define AHCI_HBA_IS_0_PORT3_INTR_SET                       _MK_ENUM_CONST(0x00000001)                                                       // R---V
#define AHCI_HBA_IS_0_PORT3_INTR_CLEAR                     _MK_ENUM_CONST(0x00000001)                                                       // -W--C
#define AHCI_HBA_IS_0_PORT4_INTR_SHIFT                      _MK_SHIFT_CONST(4)                                                              // RWIVF
#define AHCI_HBA_IS_0_PORT4_INTR_FIELD                     (_MK_SHIFT_CONST(0x1) << AHCI_HBA_IS_0_PORT4_INTR_SHIFT)
#define AHCI_HBA_IS_0_PORT4_INTR_RANGE                     4:4
#define AHCI_HBA_IS_0_PORT4_INTR_WOFFSET                   0
#define AHCI_HBA_IS_0_PORT4_INTR_DEFAULT                   (_MK_MASK_CONST(0x00000000)
#define AHCI_HBA_IS_0_PORT4_INTR_DEFAULT_MASK              (_MK_MASK_CONST(0x1)
#define AHCI_HBA_IS_0_PORT4_INTR_SW_DEFAULT                (_MK_MASK_CONST(0x00000000)
#define AHCI_HBA_IS_0_PORT4_INTR_SW_DEFAULT_MASK           (_MK_MASK_CONST(0x1)
#define AHCI_HBA_IS_0_PORT4_INTR__NOPRDCHK                 _MK_ENUM_CONST(0x00000001)                                                       // ----V
#define AHCI_HBA_IS_0_PORT4_INTR_ZERO                      _MK_ENUM_CONST(0x00000000)                                                       // R-I-V
#define AHCI_HBA_IS_0_PORT4_INTR_SET                       _MK_ENUM_CONST(0x00000001)                                                       // R---V
#define AHCI_HBA_IS_0_PORT4_INTR_CLEAR                     _MK_ENUM_CONST(0x00000001)                                                       // -W--C
#define AHCI_HBA_IS_0_PORT5_INTR_SHIFT                      _MK_SHIFT_CONST(5)                                                              // RWIVF
#define AHCI_HBA_IS_0_PORT5_INTR_FIELD                     (_MK_SHIFT_CONST(0x1) << AHCI_HBA_IS_0_PORT5_INTR_SHIFT)
#define AHCI_HBA_IS_0_PORT5_INTR_RANGE                     5:5
#define AHCI_HBA_IS_0_PORT5_INTR_WOFFSET                   0
#define AHCI_HBA_IS_0_PORT5_INTR_DEFAULT                   (_MK_MASK_CONST(0x00000000)
#define AHCI_HBA_IS_0_PORT5_INTR_DEFAULT_MASK              (_MK_MASK_CONST(0x1)
#define AHCI_HBA_IS_0_PORT5_INTR_SW_DEFAULT                (_MK_MASK_CONST(0x00000000)
#define AHCI_HBA_IS_0_PORT5_INTR_SW_DEFAULT_MASK           (_MK_MASK_CONST(0x1)
#define AHCI_HBA_IS_0_PORT5_INTR__NOPRDCHK                 _MK_ENUM_CONST(0x00000001)                                                       // ----V
#define AHCI_HBA_IS_0_PORT5_INTR_ZERO                      _MK_ENUM_CONST(0x00000000)                                                       // R-I-V
#define AHCI_HBA_IS_0_PORT5_INTR_SET                       _MK_ENUM_CONST(0x00000001)                                                       // R---V
#define AHCI_HBA_IS_0_PORT5_INTR_CLEAR                     _MK_ENUM_CONST(0x00000001)                                                       // -W--C
#define AHCI_HBA_IS_0_PORT6_INTR_SHIFT                      _MK_SHIFT_CONST(6)                                                              // RWIVF
#define AHCI_HBA_IS_0_PORT6_INTR_FIELD                     (_MK_SHIFT_CONST(0x1) << AHCI_HBA_IS_0_PORT6_INTR_SHIFT)
#define AHCI_HBA_IS_0_PORT6_INTR_RANGE                     6:6
#define AHCI_HBA_IS_0_PORT6_INTR_WOFFSET                   0
#define AHCI_HBA_IS_0_PORT6_INTR_DEFAULT                   (_MK_MASK_CONST(0x00000000)
#define AHCI_HBA_IS_0_PORT6_INTR_DEFAULT_MASK              (_MK_MASK_CONST(0x1)
#define AHCI_HBA_IS_0_PORT6_INTR_SW_DEFAULT                (_MK_MASK_CONST(0x00000000)
#define AHCI_HBA_IS_0_PORT6_INTR_SW_DEFAULT_MASK           (_MK_MASK_CONST(0x1)
#define AHCI_HBA_IS_0_PORT6_INTR__NOPRDCHK                 _MK_ENUM_CONST(0x00000001)                                                       // ----V
#define AHCI_HBA_IS_0_PORT6_INTR_ZERO                      _MK_ENUM_CONST(0x00000000)                                                       // R-I-V
#define AHCI_HBA_IS_0_PORT6_INTR_SET                       _MK_ENUM_CONST(0x00000001)                                                       // R---V
#define AHCI_HBA_IS_0_PORT6_INTR_CLEAR                     _MK_ENUM_CONST(0x00000001)                                                       // -W--C
#define AHCI_HBA_IS_0_PORT7_INTR_SHIFT                      _MK_SHIFT_CONST(7)                                                              // RWIVF
#define AHCI_HBA_IS_0_PORT7_INTR_FIELD                     (_MK_SHIFT_CONST(0x1) << AHCI_HBA_IS_0_PORT7_INTR_SHIFT)
#define AHCI_HBA_IS_0_PORT7_INTR_RANGE                     7:7
#define AHCI_HBA_IS_0_PORT7_INTR_WOFFSET                   0
#define AHCI_HBA_IS_0_PORT7_INTR_DEFAULT                   (_MK_MASK_CONST(0x00000000)
#define AHCI_HBA_IS_0_PORT7_INTR_DEFAULT_MASK              (_MK_MASK_CONST(0x1)
#define AHCI_HBA_IS_0_PORT7_INTR_SW_DEFAULT                (_MK_MASK_CONST(0x00000000)
#define AHCI_HBA_IS_0_PORT7_INTR_SW_DEFAULT_MASK           (_MK_MASK_CONST(0x1)
#define AHCI_HBA_IS_0_PORT7_INTR__NOPRDCHK                 _MK_ENUM_CONST(0x00000001)                                                       // ----V
#define AHCI_HBA_IS_0_PORT7_INTR_ZERO                      _MK_ENUM_CONST(0x00000000)                                                       // R-I-V
#define AHCI_HBA_IS_0_PORT7_INTR_SET                       _MK_ENUM_CONST(0x00000001)                                                       // R---V
#define AHCI_HBA_IS_0_PORT7_INTR_CLEAR                     _MK_ENUM_CONST(0x00000001)                                                       // -W--C
#define AHCI_HBA_IS_0_PORT8_INTR_SHIFT                      _MK_SHIFT_CONST(8)                                                              // RWIVF
#define AHCI_HBA_IS_0_PORT8_INTR_FIELD                     (_MK_SHIFT_CONST(0x1) << AHCI_HBA_IS_0_PORT8_INTR_SHIFT)
#define AHCI_HBA_IS_0_PORT8_INTR_RANGE                     8:8
#define AHCI_HBA_IS_0_PORT8_INTR_WOFFSET                   0
#define AHCI_HBA_IS_0_PORT8_INTR_DEFAULT                   (_MK_MASK_CONST(0x00000000)
#define AHCI_HBA_IS_0_PORT8_INTR_DEFAULT_MASK              (_MK_MASK_CONST(0x1)
#define AHCI_HBA_IS_0_PORT8_INTR_SW_DEFAULT                (_MK_MASK_CONST(0x00000000)
#define AHCI_HBA_IS_0_PORT8_INTR_SW_DEFAULT_MASK           (_MK_MASK_CONST(0x1)
#define AHCI_HBA_IS_0_PORT8_INTR__NOPRDCHK                 _MK_ENUM_CONST(0x00000001)                                                       // ----V
#define AHCI_HBA_IS_0_PORT8_INTR_ZERO                      _MK_ENUM_CONST(0x00000000)                                                       // R-I-V
#define AHCI_HBA_IS_0_PORT8_INTR_SET                       _MK_ENUM_CONST(0x00000001)                                                       // R---V
#define AHCI_HBA_IS_0_PORT8_INTR_CLEAR                     _MK_ENUM_CONST(0x00000001)                                                       // -W--C
#define AHCI_HBA_IS_0_PORT9_INTR_SHIFT                      _MK_SHIFT_CONST(9)                                                              // RWIVF
#define AHCI_HBA_IS_0_PORT9_INTR_FIELD                     (_MK_SHIFT_CONST(0x1) << AHCI_HBA_IS_0_PORT9_INTR_SHIFT)
#define AHCI_HBA_IS_0_PORT9_INTR_RANGE                     9:9
#define AHCI_HBA_IS_0_PORT9_INTR_WOFFSET                   0
#define AHCI_HBA_IS_0_PORT9_INTR_DEFAULT                   (_MK_MASK_CONST(0x00000000)
#define AHCI_HBA_IS_0_PORT9_INTR_DEFAULT_MASK              (_MK_MASK_CONST(0x1)
#define AHCI_HBA_IS_0_PORT9_INTR_SW_DEFAULT                (_MK_MASK_CONST(0x00000000)
#define AHCI_HBA_IS_0_PORT9_INTR_SW_DEFAULT_MASK           (_MK_MASK_CONST(0x1)
#define AHCI_HBA_IS_0_PORT9_INTR__NOPRDCHK                 _MK_ENUM_CONST(0x00000001)                                                       // ----V
#define AHCI_HBA_IS_0_PORT9_INTR_ZERO                      _MK_ENUM_CONST(0x00000000)                                                       // R-I-V
#define AHCI_HBA_IS_0_PORT9_INTR_SET                       _MK_ENUM_CONST(0x00000001)                                                       // R---V
#define AHCI_HBA_IS_0_PORT9_INTR_CLEAR                     _MK_ENUM_CONST(0x00000001)                                                       // -W--C
#define AHCI_HBA_IS_0_PORT10_INTR_SHIFT                     _MK_SHIFT_CONST(10)                                                             // RWIVF
#define AHCI_HBA_IS_0_PORT10_INTR_FIELD                    (_MK_SHIFT_CONST(0x1) << AHCI_HBA_IS_0_PORT10_INTR_SHIFT)
#define AHCI_HBA_IS_0_PORT10_INTR_RANGE                    10:10
#define AHCI_HBA_IS_0_PORT10_INTR_WOFFSET                  0
#define AHCI_HBA_IS_0_PORT10_INTR_DEFAULT                  (_MK_MASK_CONST(0x00000000)
#define AHCI_HBA_IS_0_PORT10_INTR_DEFAULT_MASK             (_MK_MASK_CONST(0x1)
#define AHCI_HBA_IS_0_PORT10_INTR_SW_DEFAULT               (_MK_MASK_CONST(0x00000000)
#define AHCI_HBA_IS_0_PORT10_INTR_SW_DEFAULT_MASK          (_MK_MASK_CONST(0x1)
#define AHCI_HBA_IS_0_PORT10_INTR__NOPRDCHK                _MK_ENUM_CONST(0x00000001)                                                       // ----V
#define AHCI_HBA_IS_0_PORT10_INTR_ZERO                     _MK_ENUM_CONST(0x00000000)                                                       // R-I-V
#define AHCI_HBA_IS_0_PORT10_INTR_SET                      _MK_ENUM_CONST(0x00000001)                                                       // R---V
#define AHCI_HBA_IS_0_PORT10_INTR_CLEAR                    _MK_ENUM_CONST(0x00000001)                                                       // -W--C
#define AHCI_HBA_IS_0_PORT11_INTR_SHIFT                     _MK_SHIFT_CONST(11)                                                             // RWIVF
#define AHCI_HBA_IS_0_PORT11_INTR_FIELD                    (_MK_SHIFT_CONST(0x1) << AHCI_HBA_IS_0_PORT11_INTR_SHIFT)
#define AHCI_HBA_IS_0_PORT11_INTR_RANGE                    11:11
#define AHCI_HBA_IS_0_PORT11_INTR_WOFFSET                  0
#define AHCI_HBA_IS_0_PORT11_INTR_DEFAULT                  (_MK_MASK_CONST(0x00000000)
#define AHCI_HBA_IS_0_PORT11_INTR_DEFAULT_MASK             (_MK_MASK_CONST(0x1)
#define AHCI_HBA_IS_0_PORT11_INTR_SW_DEFAULT               (_MK_MASK_CONST(0x00000000)
#define AHCI_HBA_IS_0_PORT11_INTR_SW_DEFAULT_MASK          (_MK_MASK_CONST(0x1)
#define AHCI_HBA_IS_0_PORT11_INTR__NOPRDCHK                _MK_ENUM_CONST(0x00000001)                                                       // ----V
#define AHCI_HBA_IS_0_PORT11_INTR_ZERO                     _MK_ENUM_CONST(0x00000000)                                                       // R-I-V
#define AHCI_HBA_IS_0_PORT11_INTR_SET                      _MK_ENUM_CONST(0x00000001)                                                       // R---V
#define AHCI_HBA_IS_0_PORT11_INTR_CLEAR                    _MK_ENUM_CONST(0x00000001)                                                       // -W--C
#define AHCI_HBA_IS_0_PORT12_INTR_SHIFT                     _MK_SHIFT_CONST(12)                                                             // RWIVF
#define AHCI_HBA_IS_0_PORT12_INTR_FIELD                    (_MK_SHIFT_CONST(0x1) << AHCI_HBA_IS_0_PORT12_INTR_SHIFT)
#define AHCI_HBA_IS_0_PORT12_INTR_RANGE                    12:12
#define AHCI_HBA_IS_0_PORT12_INTR_WOFFSET                  0
#define AHCI_HBA_IS_0_PORT12_INTR_DEFAULT                  (_MK_MASK_CONST(0x00000000)
#define AHCI_HBA_IS_0_PORT12_INTR_DEFAULT_MASK             (_MK_MASK_CONST(0x1)
#define AHCI_HBA_IS_0_PORT12_INTR_SW_DEFAULT               (_MK_MASK_CONST(0x00000000)
#define AHCI_HBA_IS_0_PORT12_INTR_SW_DEFAULT_MASK          (_MK_MASK_CONST(0x1)
#define AHCI_HBA_IS_0_PORT12_INTR__NOPRDCHK                _MK_ENUM_CONST(0x00000001)                                                       // ----V
#define AHCI_HBA_IS_0_PORT12_INTR_ZERO                     _MK_ENUM_CONST(0x00000000)                                                       // R-I-V
#define AHCI_HBA_IS_0_PORT12_INTR_SET                      _MK_ENUM_CONST(0x00000001)                                                       // R---V
#define AHCI_HBA_IS_0_PORT12_INTR_CLEAR                    _MK_ENUM_CONST(0x00000001)                                                       // -W--C
#define AHCI_HBA_IS_0_PORT13_INTR_SHIFT                     _MK_SHIFT_CONST(13)                                                             // RWIVF
#define AHCI_HBA_IS_0_PORT13_INTR_FIELD                    (_MK_SHIFT_CONST(0x1) << AHCI_HBA_IS_0_PORT13_INTR_SHIFT)
#define AHCI_HBA_IS_0_PORT13_INTR_RANGE                    13:13
#define AHCI_HBA_IS_0_PORT13_INTR_WOFFSET                  0
#define AHCI_HBA_IS_0_PORT13_INTR_DEFAULT                  (_MK_MASK_CONST(0x00000000)
#define AHCI_HBA_IS_0_PORT13_INTR_DEFAULT_MASK             (_MK_MASK_CONST(0x1)
#define AHCI_HBA_IS_0_PORT13_INTR_SW_DEFAULT               (_MK_MASK_CONST(0x00000000)
#define AHCI_HBA_IS_0_PORT13_INTR_SW_DEFAULT_MASK          (_MK_MASK_CONST(0x1)
#define AHCI_HBA_IS_0_PORT13_INTR__NOPRDCHK                _MK_ENUM_CONST(0x00000001)                                                       // ----V
#define AHCI_HBA_IS_0_PORT13_INTR_ZERO                     _MK_ENUM_CONST(0x00000000)                                                       // R-I-V
#define AHCI_HBA_IS_0_PORT13_INTR_SET                      _MK_ENUM_CONST(0x00000001)                                                       // R---V
#define AHCI_HBA_IS_0_PORT13_INTR_CLEAR                    _MK_ENUM_CONST(0x00000001)                                                       // -W--C
#define AHCI_HBA_IS_0_PORT14_INTR_SHIFT                     _MK_SHIFT_CONST(14)                                                             // RWIVF
#define AHCI_HBA_IS_0_PORT14_INTR_FIELD                    (_MK_SHIFT_CONST(0x1) << AHCI_HBA_IS_0_PORT14_INTR_SHIFT)
#define AHCI_HBA_IS_0_PORT14_INTR_RANGE                    14:14
#define AHCI_HBA_IS_0_PORT14_INTR_WOFFSET                  0
#define AHCI_HBA_IS_0_PORT14_INTR_DEFAULT                  (_MK_MASK_CONST(0x00000000)
#define AHCI_HBA_IS_0_PORT14_INTR_DEFAULT_MASK             (_MK_MASK_CONST(0x1)
#define AHCI_HBA_IS_0_PORT14_INTR_SW_DEFAULT               (_MK_MASK_CONST(0x00000000)
#define AHCI_HBA_IS_0_PORT14_INTR_SW_DEFAULT_MASK          (_MK_MASK_CONST(0x1)
#define AHCI_HBA_IS_0_PORT14_INTR__NOPRDCHK                _MK_ENUM_CONST(0x00000001)                                                       // ----V
#define AHCI_HBA_IS_0_PORT14_INTR_ZERO                     _MK_ENUM_CONST(0x00000000)                                                       // R-I-V
#define AHCI_HBA_IS_0_PORT14_INTR_SET                      _MK_ENUM_CONST(0x00000001)                                                       // R---V
#define AHCI_HBA_IS_0_PORT14_INTR_CLEAR                    _MK_ENUM_CONST(0x00000001)                                                       // -W--C
#define AHCI_HBA_IS_0_PORT15_INTR_SHIFT                     _MK_SHIFT_CONST(15)                                                             // RWIVF
#define AHCI_HBA_IS_0_PORT15_INTR_FIELD                    (_MK_SHIFT_CONST(0x1) << AHCI_HBA_IS_0_PORT15_INTR_SHIFT)
#define AHCI_HBA_IS_0_PORT15_INTR_RANGE                    15:15
#define AHCI_HBA_IS_0_PORT15_INTR_WOFFSET                  0
#define AHCI_HBA_IS_0_PORT15_INTR_DEFAULT                  (_MK_MASK_CONST(0x00000000)
#define AHCI_HBA_IS_0_PORT15_INTR_DEFAULT_MASK             (_MK_MASK_CONST(0x1)
#define AHCI_HBA_IS_0_PORT15_INTR_SW_DEFAULT               (_MK_MASK_CONST(0x00000000)
#define AHCI_HBA_IS_0_PORT15_INTR_SW_DEFAULT_MASK          (_MK_MASK_CONST(0x1)
#define AHCI_HBA_IS_0_PORT15_INTR__NOPRDCHK                _MK_ENUM_CONST(0x00000001)                                                       // ----V
#define AHCI_HBA_IS_0_PORT15_INTR_ZERO                     _MK_ENUM_CONST(0x00000000)                                                       // R-I-V
#define AHCI_HBA_IS_0_PORT15_INTR_SET                      _MK_ENUM_CONST(0x00000001)                                                       // R---V
#define AHCI_HBA_IS_0_PORT15_INTR_CLEAR                    _MK_ENUM_CONST(0x00000001)                                                       // -W--C
#define AHCI_HBA_IS_0_PORT16_INTR_SHIFT                     _MK_SHIFT_CONST(16)                                                             // RWIVF
#define AHCI_HBA_IS_0_PORT16_INTR_FIELD                    (_MK_SHIFT_CONST(0x1) << AHCI_HBA_IS_0_PORT16_INTR_SHIFT)
#define AHCI_HBA_IS_0_PORT16_INTR_RANGE                    16:16
#define AHCI_HBA_IS_0_PORT16_INTR_WOFFSET                  0
#define AHCI_HBA_IS_0_PORT16_INTR_DEFAULT                  (_MK_MASK_CONST(0x00000000)
#define AHCI_HBA_IS_0_PORT16_INTR_DEFAULT_MASK             (_MK_MASK_CONST(0x1)
#define AHCI_HBA_IS_0_PORT16_INTR_SW_DEFAULT               (_MK_MASK_CONST(0x00000000)
#define AHCI_HBA_IS_0_PORT16_INTR_SW_DEFAULT_MASK          (_MK_MASK_CONST(0x1)
#define AHCI_HBA_IS_0_PORT16_INTR__NOPRDCHK                _MK_ENUM_CONST(0x00000001)                                                       // ----V
#define AHCI_HBA_IS_0_PORT16_INTR_ZERO                     _MK_ENUM_CONST(0x00000000)                                                       // R-I-V
#define AHCI_HBA_IS_0_PORT16_INTR_SET                      _MK_ENUM_CONST(0x00000001)                                                       // R---V
#define AHCI_HBA_IS_0_PORT16_INTR_CLEAR                    _MK_ENUM_CONST(0x00000001)                                                       // -W--C
#define AHCI_HBA_IS_0_PORT17_INTR_SHIFT                     _MK_SHIFT_CONST(17)                                                             // RWIVF
#define AHCI_HBA_IS_0_PORT17_INTR_FIELD                    (_MK_SHIFT_CONST(0x1) << AHCI_HBA_IS_0_PORT17_INTR_SHIFT)
#define AHCI_HBA_IS_0_PORT17_INTR_RANGE                    17:17
#define AHCI_HBA_IS_0_PORT17_INTR_WOFFSET                  0
#define AHCI_HBA_IS_0_PORT17_INTR_DEFAULT                  (_MK_MASK_CONST(0x00000000)
#define AHCI_HBA_IS_0_PORT17_INTR_DEFAULT_MASK             (_MK_MASK_CONST(0x1)
#define AHCI_HBA_IS_0_PORT17_INTR_SW_DEFAULT               (_MK_MASK_CONST(0x00000000)
#define AHCI_HBA_IS_0_PORT17_INTR_SW_DEFAULT_MASK          (_MK_MASK_CONST(0x1)
#define AHCI_HBA_IS_0_PORT17_INTR__NOPRDCHK                _MK_ENUM_CONST(0x00000001)                                                       // ----V
#define AHCI_HBA_IS_0_PORT17_INTR_ZERO                     _MK_ENUM_CONST(0x00000000)                                                       // R-I-V
#define AHCI_HBA_IS_0_PORT17_INTR_SET                      _MK_ENUM_CONST(0x00000001)                                                       // R---V
#define AHCI_HBA_IS_0_PORT17_INTR_CLEAR                    _MK_ENUM_CONST(0x00000001)                                                       // -W--C
#define AHCI_HBA_IS_0_PORT18_INTR_SHIFT                     _MK_SHIFT_CONST(18)                                                             // RWIVF
#define AHCI_HBA_IS_0_PORT18_INTR_FIELD                    (_MK_SHIFT_CONST(0x1) << AHCI_HBA_IS_0_PORT18_INTR_SHIFT)
#define AHCI_HBA_IS_0_PORT18_INTR_RANGE                    18:18
#define AHCI_HBA_IS_0_PORT18_INTR_WOFFSET                  0
#define AHCI_HBA_IS_0_PORT18_INTR_DEFAULT                  (_MK_MASK_CONST(0x00000000)
#define AHCI_HBA_IS_0_PORT18_INTR_DEFAULT_MASK             (_MK_MASK_CONST(0x1)
#define AHCI_HBA_IS_0_PORT18_INTR_SW_DEFAULT               (_MK_MASK_CONST(0x00000000)
#define AHCI_HBA_IS_0_PORT18_INTR_SW_DEFAULT_MASK          (_MK_MASK_CONST(0x1)
#define AHCI_HBA_IS_0_PORT18_INTR__NOPRDCHK                _MK_ENUM_CONST(0x00000001)                                                       // ----V
#define AHCI_HBA_IS_0_PORT18_INTR_ZERO                     _MK_ENUM_CONST(0x00000000)                                                       // R-I-V
#define AHCI_HBA_IS_0_PORT18_INTR_SET                      _MK_ENUM_CONST(0x00000001)                                                       // R---V
#define AHCI_HBA_IS_0_PORT18_INTR_CLEAR                    _MK_ENUM_CONST(0x00000001)                                                       // -W--C
#define AHCI_HBA_IS_0_PORT19_INTR_SHIFT                     _MK_SHIFT_CONST(19)                                                             // RWIVF
#define AHCI_HBA_IS_0_PORT19_INTR_FIELD                    (_MK_SHIFT_CONST(0x1) << AHCI_HBA_IS_0_PORT19_INTR_SHIFT)
#define AHCI_HBA_IS_0_PORT19_INTR_RANGE                    19:19
#define AHCI_HBA_IS_0_PORT19_INTR_WOFFSET                  0
#define AHCI_HBA_IS_0_PORT19_INTR_DEFAULT                  (_MK_MASK_CONST(0x00000000)
#define AHCI_HBA_IS_0_PORT19_INTR_DEFAULT_MASK             (_MK_MASK_CONST(0x1)
#define AHCI_HBA_IS_0_PORT19_INTR_SW_DEFAULT               (_MK_MASK_CONST(0x00000000)
#define AHCI_HBA_IS_0_PORT19_INTR_SW_DEFAULT_MASK          (_MK_MASK_CONST(0x1)
#define AHCI_HBA_IS_0_PORT19_INTR__NOPRDCHK                _MK_ENUM_CONST(0x00000001)                                                       // ----V
#define AHCI_HBA_IS_0_PORT19_INTR_ZERO                     _MK_ENUM_CONST(0x00000000)                                                       // R-I-V
#define AHCI_HBA_IS_0_PORT19_INTR_SET                      _MK_ENUM_CONST(0x00000001)                                                       // R---V
#define AHCI_HBA_IS_0_PORT19_INTR_CLEAR                    _MK_ENUM_CONST(0x00000001)                                                       // -W--C
#define AHCI_HBA_IS_0_PORT20_INTR_SHIFT                     _MK_SHIFT_CONST(20)                                                             // RWIVF
#define AHCI_HBA_IS_0_PORT20_INTR_FIELD                    (_MK_SHIFT_CONST(0x1) << AHCI_HBA_IS_0_PORT20_INTR_SHIFT)
#define AHCI_HBA_IS_0_PORT20_INTR_RANGE                    20:20
#define AHCI_HBA_IS_0_PORT20_INTR_WOFFSET                  0
#define AHCI_HBA_IS_0_PORT20_INTR_DEFAULT                  (_MK_MASK_CONST(0x00000000)
#define AHCI_HBA_IS_0_PORT20_INTR_DEFAULT_MASK             (_MK_MASK_CONST(0x1)
#define AHCI_HBA_IS_0_PORT20_INTR_SW_DEFAULT               (_MK_MASK_CONST(0x00000000)
#define AHCI_HBA_IS_0_PORT20_INTR_SW_DEFAULT_MASK          (_MK_MASK_CONST(0x1)
#define AHCI_HBA_IS_0_PORT20_INTR__NOPRDCHK                _MK_ENUM_CONST(0x00000001)                                                       // ----V
#define AHCI_HBA_IS_0_PORT20_INTR_ZERO                     _MK_ENUM_CONST(0x00000000)                                                       // R-I-V
#define AHCI_HBA_IS_0_PORT20_INTR_SET                      _MK_ENUM_CONST(0x00000001)                                                       // R---V
#define AHCI_HBA_IS_0_PORT20_INTR_CLEAR                    _MK_ENUM_CONST(0x00000001)                                                       // -W--C
#define AHCI_HBA_IS_0_PORT21_INTR_SHIFT                     _MK_SHIFT_CONST(21)                                                             // RWIVF
#define AHCI_HBA_IS_0_PORT21_INTR_FIELD                    (_MK_SHIFT_CONST(0x1) << AHCI_HBA_IS_0_PORT21_INTR_SHIFT)
#define AHCI_HBA_IS_0_PORT21_INTR_RANGE                    21:21
#define AHCI_HBA_IS_0_PORT21_INTR_WOFFSET                  0
#define AHCI_HBA_IS_0_PORT21_INTR_DEFAULT                  (_MK_MASK_CONST(0x00000000)
#define AHCI_HBA_IS_0_PORT21_INTR_DEFAULT_MASK             (_MK_MASK_CONST(0x1)
#define AHCI_HBA_IS_0_PORT21_INTR_SW_DEFAULT               (_MK_MASK_CONST(0x00000000)
#define AHCI_HBA_IS_0_PORT21_INTR_SW_DEFAULT_MASK          (_MK_MASK_CONST(0x1)
#define AHCI_HBA_IS_0_PORT21_INTR__NOPRDCHK                _MK_ENUM_CONST(0x00000001)                                                       // ----V
#define AHCI_HBA_IS_0_PORT21_INTR_ZERO                     _MK_ENUM_CONST(0x00000000)                                                       // R-I-V
#define AHCI_HBA_IS_0_PORT21_INTR_SET                      _MK_ENUM_CONST(0x00000001)                                                       // R---V
#define AHCI_HBA_IS_0_PORT21_INTR_CLEAR                    _MK_ENUM_CONST(0x00000001)                                                       // -W--C
#define AHCI_HBA_IS_0_PORT22_INTR_SHIFT                     _MK_SHIFT_CONST(22)                                                             // RWIVF
#define AHCI_HBA_IS_0_PORT22_INTR_FIELD                    (_MK_SHIFT_CONST(0x1) << AHCI_HBA_IS_0_PORT22_INTR_SHIFT)
#define AHCI_HBA_IS_0_PORT22_INTR_RANGE                    22:22
#define AHCI_HBA_IS_0_PORT22_INTR_WOFFSET                  0
#define AHCI_HBA_IS_0_PORT22_INTR_DEFAULT                  (_MK_MASK_CONST(0x00000000)
#define AHCI_HBA_IS_0_PORT22_INTR_DEFAULT_MASK             (_MK_MASK_CONST(0x1)
#define AHCI_HBA_IS_0_PORT22_INTR_SW_DEFAULT               (_MK_MASK_CONST(0x00000000)
#define AHCI_HBA_IS_0_PORT22_INTR_SW_DEFAULT_MASK          (_MK_MASK_CONST(0x1)
#define AHCI_HBA_IS_0_PORT22_INTR__NOPRDCHK                _MK_ENUM_CONST(0x00000001)                                                       // ----V
#define AHCI_HBA_IS_0_PORT22_INTR_ZERO                     _MK_ENUM_CONST(0x00000000)                                                       // R-I-V
#define AHCI_HBA_IS_0_PORT22_INTR_SET                      _MK_ENUM_CONST(0x00000001)                                                       // R---V
#define AHCI_HBA_IS_0_PORT22_INTR_CLEAR                    _MK_ENUM_CONST(0x00000001)                                                       // -W--C
#define AHCI_HBA_IS_0_PORT23_INTR_SHIFT                     _MK_SHIFT_CONST(23)                                                             // RWIVF
#define AHCI_HBA_IS_0_PORT23_INTR_FIELD                    (_MK_SHIFT_CONST(0x1) << AHCI_HBA_IS_0_PORT23_INTR_SHIFT)
#define AHCI_HBA_IS_0_PORT23_INTR_RANGE                    23:23
#define AHCI_HBA_IS_0_PORT23_INTR_WOFFSET                  0
#define AHCI_HBA_IS_0_PORT23_INTR_DEFAULT                  (_MK_MASK_CONST(0x00000000)
#define AHCI_HBA_IS_0_PORT23_INTR_DEFAULT_MASK             (_MK_MASK_CONST(0x1)
#define AHCI_HBA_IS_0_PORT23_INTR_SW_DEFAULT               (_MK_MASK_CONST(0x00000000)
#define AHCI_HBA_IS_0_PORT23_INTR_SW_DEFAULT_MASK          (_MK_MASK_CONST(0x1)
#define AHCI_HBA_IS_0_PORT23_INTR__NOPRDCHK                _MK_ENUM_CONST(0x00000001)                                                       // ----V
#define AHCI_HBA_IS_0_PORT23_INTR_ZERO                     _MK_ENUM_CONST(0x00000000)                                                       // R-I-V
#define AHCI_HBA_IS_0_PORT23_INTR_SET                      _MK_ENUM_CONST(0x00000001)                                                       // R---V
#define AHCI_HBA_IS_0_PORT23_INTR_CLEAR                    _MK_ENUM_CONST(0x00000001)                                                       // -W--C
#define AHCI_HBA_IS_0_PORT24_INTR_SHIFT                     _MK_SHIFT_CONST(24)                                                             // RWIVF
#define AHCI_HBA_IS_0_PORT24_INTR_FIELD                    (_MK_SHIFT_CONST(0x1) << AHCI_HBA_IS_0_PORT24_INTR_SHIFT)
#define AHCI_HBA_IS_0_PORT24_INTR_RANGE                    24:24
#define AHCI_HBA_IS_0_PORT24_INTR_WOFFSET                  0
#define AHCI_HBA_IS_0_PORT24_INTR_DEFAULT                  (_MK_MASK_CONST(0x00000000)
#define AHCI_HBA_IS_0_PORT24_INTR_DEFAULT_MASK             (_MK_MASK_CONST(0x1)
#define AHCI_HBA_IS_0_PORT24_INTR_SW_DEFAULT               (_MK_MASK_CONST(0x00000000)
#define AHCI_HBA_IS_0_PORT24_INTR_SW_DEFAULT_MASK          (_MK_MASK_CONST(0x1)
#define AHCI_HBA_IS_0_PORT24_INTR__NOPRDCHK                _MK_ENUM_CONST(0x00000001)                                                       // ----V
#define AHCI_HBA_IS_0_PORT24_INTR_ZERO                     _MK_ENUM_CONST(0x00000000)                                                       // R-I-V
#define AHCI_HBA_IS_0_PORT24_INTR_SET                      _MK_ENUM_CONST(0x00000001)                                                       // R---V
#define AHCI_HBA_IS_0_PORT24_INTR_CLEAR                    _MK_ENUM_CONST(0x00000001)                                                       // -W--C
#define AHCI_HBA_IS_0_PORT25_INTR_SHIFT                     _MK_SHIFT_CONST(25)                                                             // RWIVF
#define AHCI_HBA_IS_0_PORT25_INTR_FIELD                    (_MK_SHIFT_CONST(0x1) << AHCI_HBA_IS_0_PORT25_INTR_SHIFT)
#define AHCI_HBA_IS_0_PORT25_INTR_RANGE                    25:25
#define AHCI_HBA_IS_0_PORT25_INTR_WOFFSET                  0
#define AHCI_HBA_IS_0_PORT25_INTR_DEFAULT                  (_MK_MASK_CONST(0x00000000)
#define AHCI_HBA_IS_0_PORT25_INTR_DEFAULT_MASK             (_MK_MASK_CONST(0x1)
#define AHCI_HBA_IS_0_PORT25_INTR_SW_DEFAULT               (_MK_MASK_CONST(0x00000000)
#define AHCI_HBA_IS_0_PORT25_INTR_SW_DEFAULT_MASK          (_MK_MASK_CONST(0x1)
#define AHCI_HBA_IS_0_PORT25_INTR__NOPRDCHK                _MK_ENUM_CONST(0x00000001)                                                       // ----V
#define AHCI_HBA_IS_0_PORT25_INTR_ZERO                     _MK_ENUM_CONST(0x00000000)                                                       // R-I-V
#define AHCI_HBA_IS_0_PORT25_INTR_SET                      _MK_ENUM_CONST(0x00000001)                                                       // R---V
#define AHCI_HBA_IS_0_PORT25_INTR_CLEAR                    _MK_ENUM_CONST(0x00000001)                                                       // -W--C
#define AHCI_HBA_IS_0_PORT26_INTR_SHIFT                     _MK_SHIFT_CONST(26)                                                             // RWIVF
#define AHCI_HBA_IS_0_PORT26_INTR_FIELD                    (_MK_SHIFT_CONST(0x1) << AHCI_HBA_IS_0_PORT26_INTR_SHIFT)
#define AHCI_HBA_IS_0_PORT26_INTR_RANGE                    26:26
#define AHCI_HBA_IS_0_PORT26_INTR_WOFFSET                  0
#define AHCI_HBA_IS_0_PORT26_INTR_DEFAULT                  (_MK_MASK_CONST(0x00000000)
#define AHCI_HBA_IS_0_PORT26_INTR_DEFAULT_MASK             (_MK_MASK_CONST(0x1)
#define AHCI_HBA_IS_0_PORT26_INTR_SW_DEFAULT               (_MK_MASK_CONST(0x00000000)
#define AHCI_HBA_IS_0_PORT26_INTR_SW_DEFAULT_MASK          (_MK_MASK_CONST(0x1)
#define AHCI_HBA_IS_0_PORT26_INTR__NOPRDCHK                _MK_ENUM_CONST(0x00000001)                                                       // ----V
#define AHCI_HBA_IS_0_PORT26_INTR_ZERO                     _MK_ENUM_CONST(0x00000000)                                                       // R-I-V
#define AHCI_HBA_IS_0_PORT26_INTR_SET                      _MK_ENUM_CONST(0x00000001)                                                       // R---V
#define AHCI_HBA_IS_0_PORT26_INTR_CLEAR                    _MK_ENUM_CONST(0x00000001)                                                       // -W--C
#define AHCI_HBA_IS_0_PORT27_INTR_SHIFT                     _MK_SHIFT_CONST(27)                                                             // RWIVF
#define AHCI_HBA_IS_0_PORT27_INTR_FIELD                    (_MK_SHIFT_CONST(0x1) << AHCI_HBA_IS_0_PORT27_INTR_SHIFT)
#define AHCI_HBA_IS_0_PORT27_INTR_RANGE                    27:27
#define AHCI_HBA_IS_0_PORT27_INTR_WOFFSET                  0
#define AHCI_HBA_IS_0_PORT27_INTR_DEFAULT                  (_MK_MASK_CONST(0x00000000)
#define AHCI_HBA_IS_0_PORT27_INTR_DEFAULT_MASK             (_MK_MASK_CONST(0x1)
#define AHCI_HBA_IS_0_PORT27_INTR_SW_DEFAULT               (_MK_MASK_CONST(0x00000000)
#define AHCI_HBA_IS_0_PORT27_INTR_SW_DEFAULT_MASK          (_MK_MASK_CONST(0x1)
#define AHCI_HBA_IS_0_PORT27_INTR__NOPRDCHK                _MK_ENUM_CONST(0x00000001)                                                       // ----V
#define AHCI_HBA_IS_0_PORT27_INTR_ZERO                     _MK_ENUM_CONST(0x00000000)                                                       // R-I-V
#define AHCI_HBA_IS_0_PORT27_INTR_SET                      _MK_ENUM_CONST(0x00000001)                                                       // R---V
#define AHCI_HBA_IS_0_PORT27_INTR_CLEAR                    _MK_ENUM_CONST(0x00000001)                                                       // -W--C
#define AHCI_HBA_IS_0_PORT28_INTR_SHIFT                     _MK_SHIFT_CONST(28)                                                             // RWIVF
#define AHCI_HBA_IS_0_PORT28_INTR_FIELD                    (_MK_SHIFT_CONST(0x1) << AHCI_HBA_IS_0_PORT28_INTR_SHIFT)
#define AHCI_HBA_IS_0_PORT28_INTR_RANGE                    28:28
#define AHCI_HBA_IS_0_PORT28_INTR_WOFFSET                  0
#define AHCI_HBA_IS_0_PORT28_INTR_DEFAULT                  (_MK_MASK_CONST(0x00000000)
#define AHCI_HBA_IS_0_PORT28_INTR_DEFAULT_MASK             (_MK_MASK_CONST(0x1)
#define AHCI_HBA_IS_0_PORT28_INTR_SW_DEFAULT               (_MK_MASK_CONST(0x00000000)
#define AHCI_HBA_IS_0_PORT28_INTR_SW_DEFAULT_MASK          (_MK_MASK_CONST(0x1)
#define AHCI_HBA_IS_0_PORT28_INTR__NOPRDCHK                _MK_ENUM_CONST(0x00000001)                                                       // ----V
#define AHCI_HBA_IS_0_PORT28_INTR_ZERO                     _MK_ENUM_CONST(0x00000000)                                                       // R-I-V
#define AHCI_HBA_IS_0_PORT28_INTR_SET                      _MK_ENUM_CONST(0x00000001)                                                       // R---V
#define AHCI_HBA_IS_0_PORT28_INTR_CLEAR                    _MK_ENUM_CONST(0x00000001)                                                       // -W--C
#define AHCI_HBA_IS_0_PORT29_INTR_SHIFT                     _MK_SHIFT_CONST(29)                                                             // RWIVF
#define AHCI_HBA_IS_0_PORT29_INTR_FIELD                    (_MK_SHIFT_CONST(0x1) << AHCI_HBA_IS_0_PORT29_INTR_SHIFT)
#define AHCI_HBA_IS_0_PORT29_INTR_RANGE                    29:29
#define AHCI_HBA_IS_0_PORT29_INTR_WOFFSET                  0
#define AHCI_HBA_IS_0_PORT29_INTR_DEFAULT                  (_MK_MASK_CONST(0x00000000)
#define AHCI_HBA_IS_0_PORT29_INTR_DEFAULT_MASK             (_MK_MASK_CONST(0x1)
#define AHCI_HBA_IS_0_PORT29_INTR_SW_DEFAULT               (_MK_MASK_CONST(0x00000000)
#define AHCI_HBA_IS_0_PORT29_INTR_SW_DEFAULT_MASK          (_MK_MASK_CONST(0x1)
#define AHCI_HBA_IS_0_PORT29_INTR__NOPRDCHK                _MK_ENUM_CONST(0x00000001)                                                       // ----V
#define AHCI_HBA_IS_0_PORT29_INTR_ZERO                     _MK_ENUM_CONST(0x00000000)                                                       // R-I-V
#define AHCI_HBA_IS_0_PORT29_INTR_SET                      _MK_ENUM_CONST(0x00000001)                                                       // R---V
#define AHCI_HBA_IS_0_PORT29_INTR_CLEAR                    _MK_ENUM_CONST(0x00000001)                                                       // -W--C
#define AHCI_HBA_IS_0_PORT30_INTR_SHIFT                     _MK_SHIFT_CONST(30)                                                             // RWIVF
#define AHCI_HBA_IS_0_PORT30_INTR_FIELD                    (_MK_SHIFT_CONST(0x1) << AHCI_HBA_IS_0_PORT30_INTR_SHIFT)
#define AHCI_HBA_IS_0_PORT30_INTR_RANGE                    30:30
#define AHCI_HBA_IS_0_PORT30_INTR_WOFFSET                  0
#define AHCI_HBA_IS_0_PORT30_INTR_DEFAULT                  (_MK_MASK_CONST(0x00000000)
#define AHCI_HBA_IS_0_PORT30_INTR_DEFAULT_MASK             (_MK_MASK_CONST(0x1)
#define AHCI_HBA_IS_0_PORT30_INTR_SW_DEFAULT               (_MK_MASK_CONST(0x00000000)
#define AHCI_HBA_IS_0_PORT30_INTR_SW_DEFAULT_MASK          (_MK_MASK_CONST(0x1)
#define AHCI_HBA_IS_0_PORT30_INTR__NOPRDCHK                _MK_ENUM_CONST(0x00000001)                                                       // ----V
#define AHCI_HBA_IS_0_PORT30_INTR_ZERO                     _MK_ENUM_CONST(0x00000000)                                                       // R-I-V
#define AHCI_HBA_IS_0_PORT30_INTR_SET                      _MK_ENUM_CONST(0x00000001)                                                       // R---V
#define AHCI_HBA_IS_0_PORT30_INTR_CLEAR                    _MK_ENUM_CONST(0x00000001)                                                       // -W--C
#define AHCI_HBA_IS_0_PORT31_INTR_SHIFT                     _MK_SHIFT_CONST(31)                                                             // RWIVF
#define AHCI_HBA_IS_0_PORT31_INTR_FIELD                    (_MK_SHIFT_CONST(0x1) << AHCI_HBA_IS_0_PORT31_INTR_SHIFT)
#define AHCI_HBA_IS_0_PORT31_INTR_RANGE                    31:31
#define AHCI_HBA_IS_0_PORT31_INTR_WOFFSET                  0
#define AHCI_HBA_IS_0_PORT31_INTR_DEFAULT                  (_MK_MASK_CONST(0x00000000)
#define AHCI_HBA_IS_0_PORT31_INTR_DEFAULT_MASK             (_MK_MASK_CONST(0x1)
#define AHCI_HBA_IS_0_PORT31_INTR_SW_DEFAULT               (_MK_MASK_CONST(0x00000000)
#define AHCI_HBA_IS_0_PORT31_INTR_SW_DEFAULT_MASK          (_MK_MASK_CONST(0x1)
#define AHCI_HBA_IS_0_PORT31_INTR__NOPRDCHK                _MK_ENUM_CONST(0x00000001)                                                       // ----V
#define AHCI_HBA_IS_0_PORT31_INTR_ZERO                     _MK_ENUM_CONST(0x00000000)                                                       // R-I-V
#define AHCI_HBA_IS_0_PORT31_INTR_SET                      _MK_ENUM_CONST(0x00000001)                                                       // R---V
#define AHCI_HBA_IS_0_PORT31_INTR_CLEAR                    _MK_ENUM_CONST(0x00000001)                                                       // -W--C
// 
// .LABEL RESERVED
// 
// 
//              Figure 9-3 HBA Interrupt Status Register
// .LABEL PUBLIC
// .TITLE HBA_PI (Host Bus Adaptor) Ports Implemented
// This register indicates the ports exposed by the HBA. It is loaded by the BIOS.
// 
// 
// .FIELD PI
// This register is bit significant. If a bit is set to 1, the
// corresponding port is available for software to use. If a bit is cleared to 0, the port is
// not available for software to use. The maximum number of bits set to 1 shall not
// exceed CAP.NP + 1, although the number of bits set in this register may be fewer than
// CAP.NP + 1. At least one bit shall be set to 1.
// 
// 
// 31           24 23           16 15            8 7             0
// .-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-.
// |0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0| HBA_PI
// `-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-'
// 
#define AHCI_HBA_PI_0                                      0x0000000C                                                                       // R--4R
#define AHCI_HBA_PI_0_SECURE                               0
#define AHCI_HBA_PI_0_WORD_COUNT                           1
#define AHCI_HBA_PI_0_RESET_VAL                            0x0
#define AHCI_HBA_PI_0_RESET_MASK                           0x0
#define AHCI_HBA_PI_0_SW_DEFAULT_VAL                       0x0
#define AHCI_HBA_PI_0_SW_DEFAULT_MASK                      0x0
#define AHCI_HBA_PI_0_READ_MASK                            0xffffffff
#define AHCI_HBA_PI_0_WRITE_MASK                           0x0
#define AHCI_HBA_PI_0_PI_SHIFT                              _MK_SHIFT_CONST(0)                                                              // R-CVF
#define AHCI_HBA_PI_0_PI_FIELD                             (_MK_SHIFT_CONST(0xffffffff) << AHCI_HBA_PI_0_PI_SHIFT)
#define AHCI_HBA_PI_0_PI_RANGE                             31:0
#define AHCI_HBA_PI_0_PI_WOFFSET                           0
#define AHCI_HBA_PI_0_PI_ZERO                              _MK_ENUM_CONST(0x00000000)                                                       // ----V
#define AHCI_HBA_PI_0_PI_FIRST                             _MK_ENUM_CONST(0x00000001)                                                       // ----V
#define AHCI_HBA_PI_0_PI_SECOND                            _MK_ENUM_CONST(0x00000002)                                                       // ----V
#define AHCI_HBA_PI_0_PI_THIRD                             _MK_ENUM_CONST(0x00000004)                                                       // ----V
#define AHCI_HBA_PI_0_PI_FOURTH                            _MK_ENUM_CONST(0x00000008)                                                       // ----V
#define AHCI_HBA_PI_0_PI_2PORTS_DIS                        _MK_ENUM_CONST(0x0000003F)                                                       // ----V
#define AHCI_HBA_PI_0_PI_4PORTS_DIS                        _MK_ENUM_CONST(0x0000000F)                                                       // ----V
#define AHCI_HBA_PI_0_PI_INIT                              _MK_ENUM_CONST(0x00000001)                                                       // R-C-V
// 
// 
//              Figure 9-4 HBA Ports Implemented Register
// 
// 
// 
// 
// .TITLE HBA_VS AHCI Revision
//        This register indicates basic capabilities to Software.
// 
// .FIELD MINOR_REV
// Indicates the minor version
// .FIELD MAJOR_REV
// Indicates the major version
// 
// 
// 31           24 23           16 15            8 7             0
// .-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-.
// |0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0| HBA_VS
// `-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-'
// 
#define AHCI_HBA_VS_0                                      0x00000010                                                                       // R--4R
#define AHCI_HBA_VS_0_SECURE                               0
#define AHCI_HBA_VS_0_WORD_COUNT                           1
#define AHCI_HBA_VS_0_RESET_VAL                            0x0
#define AHCI_HBA_VS_0_RESET_MASK                           0x0
#define AHCI_HBA_VS_0_SW_DEFAULT_VAL                       0x0
#define AHCI_HBA_VS_0_SW_DEFAULT_MASK                      0x0
#define AHCI_HBA_VS_0_READ_MASK                            0xffffffff
#define AHCI_HBA_VS_0_WRITE_MASK                           0x0
#define AHCI_HBA_VS_0_MINOR_REV_SHIFT                       _MK_SHIFT_CONST(0)                                                              // R-CVF
#define AHCI_HBA_VS_0_MINOR_REV_FIELD                      (_MK_SHIFT_CONST(0xffff) << AHCI_HBA_VS_0_MINOR_REV_SHIFT)
#define AHCI_HBA_VS_0_MINOR_REV_RANGE                      15:0
#define AHCI_HBA_VS_0_MINOR_REV_WOFFSET                    0
#define AHCI_HBA_VS_0_MINOR_REV_1_3_1                      _MK_ENUM_CONST(0x00000301)                                                       // R-C-V
#define AHCI_HBA_VS_0_MINOR_REV_1_3                        _MK_ENUM_CONST(0x00000300)                                                       // R---V
#define AHCI_HBA_VS_0_MINOR_REV_1_2                        _MK_ENUM_CONST(0x00000200)                                                       // R---V
#define AHCI_HBA_VS_0_MINOR_REV_1_0                        _MK_ENUM_CONST(0x00000000)                                                       // ----V
#define AHCI_HBA_VS_0_MINOR_REV_0_95                       _MK_ENUM_CONST(0x00000905)                                                       // ----V
#define AHCI_HBA_VS_0_MAJOR_REV_SHIFT                       _MK_SHIFT_CONST(16)                                                             // C--VF
#define AHCI_HBA_VS_0_MAJOR_REV_FIELD                      (_MK_SHIFT_CONST(0xffff) << AHCI_HBA_VS_0_MAJOR_REV_SHIFT)
#define AHCI_HBA_VS_0_MAJOR_REV_RANGE                      31:16
#define AHCI_HBA_VS_0_MAJOR_REV_WOFFSET                    0
#define AHCI_HBA_VS_0_MAJOR_REV_1_3_1                      _MK_ENUM_CONST(0x00000001)                                                       // C---V
#define AHCI_HBA_VS_0_MAJOR_REV_1_3                        _MK_ENUM_CONST(0x00000001)                                                       // ----V
#define AHCI_HBA_VS_0_MAJOR_REV_1_2                        _MK_ENUM_CONST(0x00000001)                                                       // ----V
#define AHCI_HBA_VS_0_MAJOR_REV_1_0                        _MK_ENUM_CONST(0x00000001)                                                       // ----V
#define AHCI_HBA_VS_0_MAJOR_REV_0_95                       _MK_ENUM_CONST(0x00000000)                                                       // ----V
// 
// 
// 
//              Figure 9-5 HBA AHCI Version Register
// 
// 
// 
// .TITLE HBA_CCC_CTL Command Completion Coalescing Control
//        This register indicates basic capabilities to Software.
// 
// .FIELD EN
// When cleared to 0, the command completion coalescing feature is
// disabled and no CCC interrupts are generated. When set to 1, the command
// completion coalescing feature is enabled and CCC interrupts may be generated based
// on timeout or command completion conditions. Software shall only change the contents
// of the TV and CC fields when EN is cleared to 0. On transition of this bit from 0 to 1,
// any updated values for the TV and CC fields shall take effect.
// 
// .FIELD INT
// Specifies the interrupt used by the CCC feature. This interrupt must be
// marked as unused in the Ports Implemented (PI) register by the corresponding bit being
// set to 0. Thus, the CCC interrupt corresponds to the interrupt for an unimplemented
// port on the controller. When a CCC interrupt occurs, the IS.IPS[INT] bit shall be
// asserted to 1. This field also specifies the interrupt vector used for MSI.
// 
// .FIELD CC
// Specifies the number of command completions that are
// necessary to cause a CCC interrupt. The HBA has an internal command completion
// counter, hCccComplete. hCccComplete is incremented by one each time a selected
// port has a command completion. When hCccComplete is equal to the command
// completions value, a CCC interrupt is signaled. The internal command completion
// counter is reset to 0 on the assertion of each CCC interrupt. A value of 0 for this field
// shall disable CCC interrupts being generated based on the number of commands
// completed, i.e. CCC interrupts are only generated based on the timer in this case.
// 
// .FIELD TIMEOUT_VAL
// The timeout value is specified in 1 millisecond intervals. The timer
// accuracy shall be within 5%. hCccTimer is loaded with this timeout value. hCccTimer is
// only decremented when commands are outstanding on selected ports, as defined in
// section 11.2. The HBA will signal a CCC interrupt when hCccTimer has decremented to
// 0. hCccTimer is reset to the timeout value on the assertion of each CCC interrupt. A
// timeout value of 0 is reserved.
// 
// .PRIVATE
// TODO: Do we need to have a backdoor write mechanism for writing the interrupt value?
// .PUBLIC
// 
// 31           24 23           16 15            8 7             0
// .-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-.
// |0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0| HBA_CCC_CTL
// `-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-'
// 
#define AHCI_HBA_CCC_CTL_0                                 0x00000014                                                                       // RWI4R
#define AHCI_HBA_CCC_CTL_0_SECURE                          0
#define AHCI_HBA_CCC_CTL_0_WORD_COUNT                      1
#define AHCI_HBA_CCC_CTL_0_RESET_VAL                       0x0
#define AHCI_HBA_CCC_CTL_0_RESET_MASK                      0x0
#define AHCI_HBA_CCC_CTL_0_SW_DEFAULT_VAL                  0x0
#define AHCI_HBA_CCC_CTL_0_SW_DEFAULT_MASK                 0x0
#define AHCI_HBA_CCC_CTL_0_READ_MASK                       0xffffffff
#define AHCI_HBA_CCC_CTL_0_WRITE_MASK                      0xffffff01
#define AHCI_HBA_CCC_CTL_0_EN_SHIFT                         _MK_SHIFT_CONST(0)                                                              // RWWVF
#define AHCI_HBA_CCC_CTL_0_EN_FIELD                        (_MK_SHIFT_CONST(0x1) << AHCI_HBA_CCC_CTL_0_EN_SHIFT)
#define AHCI_HBA_CCC_CTL_0_EN_RANGE                        0:0
#define AHCI_HBA_CCC_CTL_0_EN_WOFFSET                      0
#define AHCI_HBA_CCC_CTL_0_EN_DEFAULT                      (_MK_MASK_CONST(0x00000000)
#define AHCI_HBA_CCC_CTL_0_EN_DEFAULT_MASK                 (_MK_MASK_CONST(0x1)
#define AHCI_HBA_CCC_CTL_0_EN_SW_DEFAULT                   (_MK_MASK_CONST(0x00000000)
#define AHCI_HBA_CCC_CTL_0_EN_SW_DEFAULT_MASK              (_MK_MASK_CONST(0x1)
#define AHCI_HBA_CCC_CTL_0_EN__NOPRDCHK                    _MK_ENUM_CONST(0x00000001)                                                       // ----V
#define AHCI_HBA_CCC_CTL_0_EN_SET                          _MK_ENUM_CONST(0x00000001)                                                       // RW--V
#define AHCI_HBA_CCC_CTL_0_EN_CLEAR                        _MK_ENUM_CONST(0x00000000)                                                       // RWW-V
#define AHCI_HBA_CCC_CTL_0_RSVD_SHIFT                       _MK_SHIFT_CONST(1)                                                              // C--VF
#define AHCI_HBA_CCC_CTL_0_RSVD_FIELD                      (_MK_SHIFT_CONST(0x3) << AHCI_HBA_CCC_CTL_0_RSVD_SHIFT)
#define AHCI_HBA_CCC_CTL_0_RSVD_RANGE                      2:1
#define AHCI_HBA_CCC_CTL_0_RSVD_WOFFSET                    0
#define AHCI_HBA_CCC_CTL_0_RSVD_ZEROS                      _MK_ENUM_CONST(0x00000000)                                                       // C---V
#define AHCI_HBA_CCC_CTL_0_INT_SHIFT                        _MK_SHIFT_CONST(3)                                                              // R-WVF
#define AHCI_HBA_CCC_CTL_0_INT_FIELD                       (_MK_SHIFT_CONST(0x1f) << AHCI_HBA_CCC_CTL_0_INT_SHIFT)
#define AHCI_HBA_CCC_CTL_0_INT_RANGE                       7:3
#define AHCI_HBA_CCC_CTL_0_INT_WOFFSET                     0
#define AHCI_HBA_CCC_CTL_0_INT_DEFAULT                     (_MK_MASK_CONST(0x0000001F)
#define AHCI_HBA_CCC_CTL_0_INT_DEFAULT_MASK                (_MK_MASK_CONST(0x1f)
#define AHCI_HBA_CCC_CTL_0_INT_SW_DEFAULT                  (_MK_MASK_CONST(0x0000001F)
#define AHCI_HBA_CCC_CTL_0_INT_SW_DEFAULT_MASK             (_MK_MASK_CONST(0x1f)
#define AHCI_HBA_CCC_CTL_0_INT__NOPRDCHK                   _MK_ENUM_CONST(0x00000001)                                                       // ----V
#define AHCI_HBA_CCC_CTL_0_INT_ZERO                        _MK_ENUM_CONST(0x00000000)                                                       // R---V
#define AHCI_HBA_CCC_CTL_0_INT_FIVE                        _MK_ENUM_CONST(0x00000004)                                                       // R---V
#define AHCI_HBA_CCC_CTL_0_INT_SEVEN                       _MK_ENUM_CONST(0x00000006)                                                       // R---V
#define AHCI_HBA_CCC_CTL_0_INT_INIT                        _MK_ENUM_CONST(0x0000001F)                                                       // R-W-V
#define AHCI_HBA_CCC_CTL_0_CC_SHIFT                         _MK_SHIFT_CONST(8)                                                              // RWWVF
#define AHCI_HBA_CCC_CTL_0_CC_FIELD                        (_MK_SHIFT_CONST(0xff) << AHCI_HBA_CCC_CTL_0_CC_SHIFT)
#define AHCI_HBA_CCC_CTL_0_CC_RANGE                        15:8
#define AHCI_HBA_CCC_CTL_0_CC_WOFFSET                      0
#define AHCI_HBA_CCC_CTL_0_CC_DEFAULT                      (_MK_MASK_CONST(0x000000FF)
#define AHCI_HBA_CCC_CTL_0_CC_DEFAULT_MASK                 (_MK_MASK_CONST(0xff)
#define AHCI_HBA_CCC_CTL_0_CC_SW_DEFAULT                   (_MK_MASK_CONST(0x000000FF)
#define AHCI_HBA_CCC_CTL_0_CC_SW_DEFAULT_MASK              (_MK_MASK_CONST(0xff)
#define AHCI_HBA_CCC_CTL_0_CC__NOPRDCHK                    _MK_ENUM_CONST(0x00000001)                                                       // ----V
#define AHCI_HBA_CCC_CTL_0_CC_INIT_VAL                     _MK_ENUM_CONST(0x000000FF)                                                       // RWW-V
#define AHCI_HBA_CCC_CTL_0_TIMEOUT_VAL_SHIFT                _MK_SHIFT_CONST(16)                                                             // RWWVF
#define AHCI_HBA_CCC_CTL_0_TIMEOUT_VAL_FIELD               (_MK_SHIFT_CONST(0xffff) << AHCI_HBA_CCC_CTL_0_TIMEOUT_VAL_SHIFT)
#define AHCI_HBA_CCC_CTL_0_TIMEOUT_VAL_RANGE               31:16
#define AHCI_HBA_CCC_CTL_0_TIMEOUT_VAL_WOFFSET             0
#define AHCI_HBA_CCC_CTL_0_TIMEOUT_VAL_DEFAULT             (_MK_MASK_CONST(0x0000FFFF)
#define AHCI_HBA_CCC_CTL_0_TIMEOUT_VAL_DEFAULT_MASK        (_MK_MASK_CONST(0xffff)
#define AHCI_HBA_CCC_CTL_0_TIMEOUT_VAL_SW_DEFAULT          (_MK_MASK_CONST(0x0000FFFF)
#define AHCI_HBA_CCC_CTL_0_TIMEOUT_VAL_SW_DEFAULT_MASK     (_MK_MASK_CONST(0xffff)
#define AHCI_HBA_CCC_CTL_0_TIMEOUT_VAL__NOPRDCHK           _MK_ENUM_CONST(0x00000001)                                                       // ----V
#define AHCI_HBA_CCC_CTL_0_TIMEOUT_VAL_INIT                _MK_ENUM_CONST(0x0000FFFF)                                                       // RWW-V
// 
// 
//              Figure 9-6 HBA Command Completion Coalescing Control Register
// 
// 
// .TITLE HBA_CCC_PORTS Command Completion Coalescing Ports
//        This register indicates basic capabilities to Software.
// 
// .FIELD PRT
// When cleared to 0, the command completion coalescing feature is
// disabled and no CCC interrupts are generated. When set to 1, the command
// completion coalescing feature is enabled and CCC interrupts may be generated based
// on timeout or command completion conditions. Software shall only change the contents
// of the TV and CC fields when EN is cleared to 0. On transition of this bit from 0 to 1,
// any updated values for the TV and CC fields shall take effect.
// 
// 31           24 23           16 15            8 7             0
// .-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-.
// |0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0| HBA_CCC_PORTS
// `-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-'
// 
#define AHCI_HBA_CCC_PORTS_0                               0x00000018                                                                       // RWI4R
#define AHCI_HBA_CCC_PORTS_0_SECURE                        0
#define AHCI_HBA_CCC_PORTS_0_WORD_COUNT                    1
#define AHCI_HBA_CCC_PORTS_0_RESET_VAL                     0x0
#define AHCI_HBA_CCC_PORTS_0_RESET_MASK                    0x0
#define AHCI_HBA_CCC_PORTS_0_SW_DEFAULT_VAL                0x0
#define AHCI_HBA_CCC_PORTS_0_SW_DEFAULT_MASK               0x0
#define AHCI_HBA_CCC_PORTS_0_READ_MASK                     0xffffffff
#define AHCI_HBA_CCC_PORTS_0_WRITE_MASK                    0xffffffff
#define AHCI_HBA_CCC_PORTS_0_PRT_SHIFT                      _MK_SHIFT_CONST(0)                                                              // RWWVF
#define AHCI_HBA_CCC_PORTS_0_PRT_FIELD                     (_MK_SHIFT_CONST(0xffffffff) << AHCI_HBA_CCC_PORTS_0_PRT_SHIFT)
#define AHCI_HBA_CCC_PORTS_0_PRT_RANGE                     31:0
#define AHCI_HBA_CCC_PORTS_0_PRT_WOFFSET                   0
#define AHCI_HBA_CCC_PORTS_0_PRT_DEFAULT                   (_MK_MASK_CONST(0x00000000)
#define AHCI_HBA_CCC_PORTS_0_PRT_DEFAULT_MASK              (_MK_MASK_CONST(0xffffffff)
#define AHCI_HBA_CCC_PORTS_0_PRT_SW_DEFAULT                (_MK_MASK_CONST(0x00000000)
#define AHCI_HBA_CCC_PORTS_0_PRT_SW_DEFAULT_MASK           (_MK_MASK_CONST(0xffffffff)
#define AHCI_HBA_CCC_PORTS_0_PRT__NOPRDCHK                 _MK_ENUM_CONST(0x00000001)                                                       // ----V
#define AHCI_HBA_CCC_PORTS_0_PRT_RESET_VAL                 _MK_ENUM_CONST(0x00000000)                                                       // RWW-V
// 
// 
//              Figure 9-7 HBA Command Completion Coalescing Ports Register.
// 
// 
// .TITLE HBA_EM_LOC Enclosure Management Location
//        This register indicates basic capabilities to Software.
// 
// .FIELD SZ
// Specifies the size of the transmit message buffer area in Dwords. If
// both transmit and receive buffers are supported, then the transmit buffer begins at
// ABAR[EM_LOC.OFST*4] and the receive buffer directly follows it. If both transmit and
// receive buffers are supported, both buffers are of the size indicated in the Buffer Size
// field. A value of 0 is invalid.
// 
// .FIELD OFST
// The offset of the message buffer in Dwords from the beginning of the
// ABAR.
// 
// 31           24 23           16 15            8 7             0
// .-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-.
// |0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0| HBA_EM_LOC
// `-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-'
// 
#define AHCI_HBA_EM_LOC_0                                  0x0000001C                                                                       // C-I4R
#define AHCI_HBA_EM_LOC_0_SECURE                           0
#define AHCI_HBA_EM_LOC_0_WORD_COUNT                       1
#define AHCI_HBA_EM_LOC_0_RESET_VAL                        0x0
#define AHCI_HBA_EM_LOC_0_RESET_MASK                       0x0
#define AHCI_HBA_EM_LOC_0_SW_DEFAULT_VAL                   0x0
#define AHCI_HBA_EM_LOC_0_SW_DEFAULT_MASK                  0x0
#define AHCI_HBA_EM_LOC_0_READ_MASK                        0xffffffff
#define AHCI_HBA_EM_LOC_0_WRITE_MASK                       0x0
#define AHCI_HBA_EM_LOC_0_SZ_SHIFT                          _MK_SHIFT_CONST(0)                                                              // C--VF
#define AHCI_HBA_EM_LOC_0_SZ_FIELD                         (_MK_SHIFT_CONST(0xffff) << AHCI_HBA_EM_LOC_0_SZ_SHIFT)
#define AHCI_HBA_EM_LOC_0_SZ_RANGE                         15:0
#define AHCI_HBA_EM_LOC_0_SZ_WOFFSET                       0
#define AHCI_HBA_EM_LOC_0_SZ__NOPRDCHK                     _MK_ENUM_CONST(0x00000001)                                                       // ----V
#define AHCI_HBA_EM_LOC_0_SZ_VAL                           _MK_ENUM_CONST(0x00000000)                                                       // C---V
#define AHCI_HBA_EM_LOC_0_OFST_SHIFT                        _MK_SHIFT_CONST(16)                                                             // C--VF
#define AHCI_HBA_EM_LOC_0_OFST_FIELD                       (_MK_SHIFT_CONST(0xffff) << AHCI_HBA_EM_LOC_0_OFST_SHIFT)
#define AHCI_HBA_EM_LOC_0_OFST_RANGE                       31:16
#define AHCI_HBA_EM_LOC_0_OFST_WOFFSET                     0
#define AHCI_HBA_EM_LOC_0_OFST__NOPRDCHK                   _MK_ENUM_CONST(0x00000001)                                                       // ----V
#define AHCI_HBA_EM_LOC_0_OFST_VAL                         _MK_ENUM_CONST(0x00000000)                                                       // C---V
// 
// 
//              Figure 9-8 HBA Enclosure Management Location Register.
// 
// 
// .TITLE HBA_EM_CTL Enclosure Management Control
//        This register indicates basic capabilities to Software.
// 
// .FIELD STS_MR
// The HBA sets this bit to a 1 when a message is
// completely received into the message buffer. When software detects this bit is a 1,
// software should read the message and perform any actions necessary. When software
// is finished reading the message in the buffer, software writes a 1 to this bit in order to
// clear it. A write of 0 to this bit by software shall have no effect.
// 
// .FIELD TM
// When set to 1 by software, the HBA shall transmit the
// message contained in the message buffer. When the message is completely sent, the
// HBA shall clear this bit to 0. A write of 0 to this bit by software shall have no effect.
// Software shall not change the contents of the message buffer while CTL.TM is set to
// 1.
// 
// .FIELD RST
// When set to 1 by software, the HBA shall reset all enclosure
// management message logic and the attached enclosure processor (if applicable) and
// take all appropriate reset actions to ensure messages can be transmitted/received after
// the reset. After the HBA completes the reset operation, the HBA shall set the value to
// 0. A write of 0 by software to this field shall have no effect.
// 
// .FIELD SUPP_LED
// If set to 1, the HBA supports the LED message
// 
// .FIELD SUPP_SAFTE
// If set to 1, the HBA
// supports the SAF-TE message type.
// 
// .FIELD SUPP_SES2
// If set to 1, the HBA
// supports the SES-2 message type.
// 
// .FIELD SUPP_SGPIO
// If set to 1, the HBA
// supports the SGPIO register interface message type.
// 
// .FIELD ATTR_SMB
// If set to 1, the HBA has one message buffer
// that is shared for messages to transmit and messages received. In this case,
// unsolicited receive messages are not supported and it is softwares responsibility to
// manage access to this buffer. If cleared to 0, there are separate receive and transmit
// buffers such that unsolicited messages could be supported.
// 
// .FIELD ATTR_XMT
// If set to 1, the HBA only supports transmitting
// messages and does not support receiving messages. If cleared to 0, the HBA
// supports transmitting and receiving messages.
// 
// .FIELD ATTR_ALHD
// If set to 1, the HBA drives the activity
// LED for the LED message type in hardware and does not utilize software settings for
// this LED. The HBA does not begin transmitting the hardware based activity signal until
// after software has written CTL.TM=1 after a reset condition.
// 
// .FIELD ATTR_PM
// If set to 1, the HBA supports enclosure
// management messages for devices attached via a Port Multiplier. If cleared to 0, the
// HBA does not support enclosure management messages for devices attached via a
// Port Multiplier. When cleared to 0, software should use the Serial ATA enclosure
// management bridge that is built into many Port Multipliers for enclosure services with
// these devices. For more information on Serial ATA enclosure management bridges,
// refer to the Serial ATA Revision 2.6 specification.
// 
// 
// 31           24 23           16 15            8 7             0
// .-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-.
// |0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0| HBA_EM_CTL
// `-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-'
// 
#define AHCI_HBA_EM_CTL_0                                  0x00000020                                                                       // RW-4R
#define AHCI_HBA_EM_CTL_0_SECURE                           0
#define AHCI_HBA_EM_CTL_0_WORD_COUNT                       1
#define AHCI_HBA_EM_CTL_0_RESET_VAL                        0x0
#define AHCI_HBA_EM_CTL_0_RESET_MASK                       0x0
#define AHCI_HBA_EM_CTL_0_SW_DEFAULT_VAL                   0x0
#define AHCI_HBA_EM_CTL_0_SW_DEFAULT_MASK                  0x0
#define AHCI_HBA_EM_CTL_0_READ_MASK                        0xffffffff
#define AHCI_HBA_EM_CTL_0_WRITE_MASK                       0x301
#define AHCI_HBA_EM_CTL_0_STS_MR_SHIFT                      _MK_SHIFT_CONST(0)                                                              // RWWVF
#define AHCI_HBA_EM_CTL_0_STS_MR_FIELD                     (_MK_SHIFT_CONST(0x1) << AHCI_HBA_EM_CTL_0_STS_MR_SHIFT)
#define AHCI_HBA_EM_CTL_0_STS_MR_RANGE                     0:0
#define AHCI_HBA_EM_CTL_0_STS_MR_WOFFSET                   0
#define AHCI_HBA_EM_CTL_0_STS_MR_DEFAULT                   (_MK_MASK_CONST(0x00000000)
#define AHCI_HBA_EM_CTL_0_STS_MR_DEFAULT_MASK              (_MK_MASK_CONST(0x1)
#define AHCI_HBA_EM_CTL_0_STS_MR_SW_DEFAULT                (_MK_MASK_CONST(0x00000000)
#define AHCI_HBA_EM_CTL_0_STS_MR_SW_DEFAULT_MASK           (_MK_MASK_CONST(0x1)
#define AHCI_HBA_EM_CTL_0_STS_MR_TRUE                      _MK_ENUM_CONST(0x00000001)                                                       // R---V
#define AHCI_HBA_EM_CTL_0_STS_MR_FALSE                     _MK_ENUM_CONST(0x00000000)                                                       // R-W-V
#define AHCI_HBA_EM_CTL_0_STS_MR_CLEAR                     _MK_ENUM_CONST(0x00000001)                                                       // -W--C
#define AHCI_HBA_EM_CTL_0_RSVD0_SHIFT                       _MK_SHIFT_CONST(1)                                                              // C--VF
#define AHCI_HBA_EM_CTL_0_RSVD0_FIELD                      (_MK_SHIFT_CONST(0x7f) << AHCI_HBA_EM_CTL_0_RSVD0_SHIFT)
#define AHCI_HBA_EM_CTL_0_RSVD0_RANGE                      7:1
#define AHCI_HBA_EM_CTL_0_RSVD0_WOFFSET                    0
#define AHCI_HBA_EM_CTL_0_RSVD0_VAL                        _MK_ENUM_CONST(0x00000000)                                                       // C---V
#define AHCI_HBA_EM_CTL_0_TM_SHIFT                          _MK_SHIFT_CONST(8)                                                              // RWWVF
#define AHCI_HBA_EM_CTL_0_TM_FIELD                         (_MK_SHIFT_CONST(0x1) << AHCI_HBA_EM_CTL_0_TM_SHIFT)
#define AHCI_HBA_EM_CTL_0_TM_RANGE                         8:8
#define AHCI_HBA_EM_CTL_0_TM_WOFFSET                       0
#define AHCI_HBA_EM_CTL_0_TM_DEFAULT                       (_MK_MASK_CONST(0x00000000)
#define AHCI_HBA_EM_CTL_0_TM_DEFAULT_MASK                  (_MK_MASK_CONST(0x1)
#define AHCI_HBA_EM_CTL_0_TM_SW_DEFAULT                    (_MK_MASK_CONST(0x00000000)
#define AHCI_HBA_EM_CTL_0_TM_SW_DEFAULT_MASK               (_MK_MASK_CONST(0x1)
#define AHCI_HBA_EM_CTL_0_TM_CLEAR                         _MK_ENUM_CONST(0x00000000)                                                       // R-W-V
#define AHCI_HBA_EM_CTL_0_TM_SET                           _MK_ENUM_CONST(0x00000001)                                                       // -W--V
#define AHCI_HBA_EM_CTL_0_RST_SHIFT                         _MK_SHIFT_CONST(9)                                                              // RWWVF
#define AHCI_HBA_EM_CTL_0_RST_FIELD                        (_MK_SHIFT_CONST(0x1) << AHCI_HBA_EM_CTL_0_RST_SHIFT)
#define AHCI_HBA_EM_CTL_0_RST_RANGE                        9:9
#define AHCI_HBA_EM_CTL_0_RST_WOFFSET                      0
#define AHCI_HBA_EM_CTL_0_RST_DEFAULT                      (_MK_MASK_CONST(0x00000000)
#define AHCI_HBA_EM_CTL_0_RST_DEFAULT_MASK                 (_MK_MASK_CONST(0x1)
#define AHCI_HBA_EM_CTL_0_RST_SW_DEFAULT                   (_MK_MASK_CONST(0x00000000)
#define AHCI_HBA_EM_CTL_0_RST_SW_DEFAULT_MASK              (_MK_MASK_CONST(0x1)
#define AHCI_HBA_EM_CTL_0_RST_SET                          _MK_ENUM_CONST(0x00000001)                                                       // -W--V
#define AHCI_HBA_EM_CTL_0_RST_CLEAR                        _MK_ENUM_CONST(0x00000000)                                                       // R-W-V
#define AHCI_HBA_EM_CTL_0_RSVD1_SHIFT                       _MK_SHIFT_CONST(10)                                                             // C--VF
#define AHCI_HBA_EM_CTL_0_RSVD1_FIELD                      (_MK_SHIFT_CONST(0x3f) << AHCI_HBA_EM_CTL_0_RSVD1_SHIFT)
#define AHCI_HBA_EM_CTL_0_RSVD1_RANGE                      15:10
#define AHCI_HBA_EM_CTL_0_RSVD1_WOFFSET                    0
#define AHCI_HBA_EM_CTL_0_RSVD1_VAL                        _MK_ENUM_CONST(0x00000000)                                                       // C---V
#define AHCI_HBA_EM_CTL_0_SUPP_LED_SHIFT                    _MK_SHIFT_CONST(16)                                                             // C--VF
#define AHCI_HBA_EM_CTL_0_SUPP_LED_FIELD                   (_MK_SHIFT_CONST(0x1) << AHCI_HBA_EM_CTL_0_SUPP_LED_SHIFT)
#define AHCI_HBA_EM_CTL_0_SUPP_LED_RANGE                   16:16
#define AHCI_HBA_EM_CTL_0_SUPP_LED_WOFFSET                 0
#define AHCI_HBA_EM_CTL_0_SUPP_LED__NOPRDCHK               _MK_ENUM_CONST(0x00000001)                                                       // ----V
#define AHCI_HBA_EM_CTL_0_SUPP_LED_FALSE                   _MK_ENUM_CONST(0x00000000)                                                       // C---V
#define AHCI_HBA_EM_CTL_0_SUPP_LED_TRUE                    _MK_ENUM_CONST(0x00000001)                                                       // ----V
#define AHCI_HBA_EM_CTL_0_SUPP_SAFTE_SHIFT                  _MK_SHIFT_CONST(17)                                                             // C--VF
#define AHCI_HBA_EM_CTL_0_SUPP_SAFTE_FIELD                 (_MK_SHIFT_CONST(0x1) << AHCI_HBA_EM_CTL_0_SUPP_SAFTE_SHIFT)
#define AHCI_HBA_EM_CTL_0_SUPP_SAFTE_RANGE                 17:17
#define AHCI_HBA_EM_CTL_0_SUPP_SAFTE_WOFFSET               0
#define AHCI_HBA_EM_CTL_0_SUPP_SAFTE__NOPRDCHK             _MK_ENUM_CONST(0x00000001)                                                       // ----V
#define AHCI_HBA_EM_CTL_0_SUPP_SAFTE_FALSE                 _MK_ENUM_CONST(0x00000000)                                                       // C---V
#define AHCI_HBA_EM_CTL_0_SUPP_SAFTE_TRUE                  _MK_ENUM_CONST(0x00000001)                                                       // ----V
#define AHCI_HBA_EM_CTL_0_SUPP_SES2_SHIFT                   _MK_SHIFT_CONST(18)                                                             // C--VF
#define AHCI_HBA_EM_CTL_0_SUPP_SES2_FIELD                  (_MK_SHIFT_CONST(0x1) << AHCI_HBA_EM_CTL_0_SUPP_SES2_SHIFT)
#define AHCI_HBA_EM_CTL_0_SUPP_SES2_RANGE                  18:18
#define AHCI_HBA_EM_CTL_0_SUPP_SES2_WOFFSET                0
#define AHCI_HBA_EM_CTL_0_SUPP_SES2__NOPRDCHK              _MK_ENUM_CONST(0x00000001)                                                       // ----V
#define AHCI_HBA_EM_CTL_0_SUPP_SES2_FALSE                  _MK_ENUM_CONST(0x00000000)                                                       // C---V
#define AHCI_HBA_EM_CTL_0_SUPP_SES2_TRUE                   _MK_ENUM_CONST(0x00000001)                                                       // ----V
#define AHCI_HBA_EM_CTL_0_SUPP_SGPIO_SHIFT                  _MK_SHIFT_CONST(19)                                                             // C--VF
#define AHCI_HBA_EM_CTL_0_SUPP_SGPIO_FIELD                 (_MK_SHIFT_CONST(0x1) << AHCI_HBA_EM_CTL_0_SUPP_SGPIO_SHIFT)
#define AHCI_HBA_EM_CTL_0_SUPP_SGPIO_RANGE                 19:19
#define AHCI_HBA_EM_CTL_0_SUPP_SGPIO_WOFFSET               0
#define AHCI_HBA_EM_CTL_0_SUPP_SGPIO__NOPRDCHK             _MK_ENUM_CONST(0x00000001)                                                       // ----V
#define AHCI_HBA_EM_CTL_0_SUPP_SGPIO_FALSE                 _MK_ENUM_CONST(0x00000000)                                                       // C---V
#define AHCI_HBA_EM_CTL_0_SUPP_SGPIO_TRUE                  _MK_ENUM_CONST(0x00000001)                                                       // ----V
#define AHCI_HBA_EM_CTL_0_RSVD2_SHIFT                       _MK_SHIFT_CONST(20)                                                             // C--VF
#define AHCI_HBA_EM_CTL_0_RSVD2_FIELD                      (_MK_SHIFT_CONST(0xf) << AHCI_HBA_EM_CTL_0_RSVD2_SHIFT)
#define AHCI_HBA_EM_CTL_0_RSVD2_RANGE                      23:20
#define AHCI_HBA_EM_CTL_0_RSVD2_WOFFSET                    0
#define AHCI_HBA_EM_CTL_0_RSVD2_VAL                        _MK_ENUM_CONST(0x00000000)                                                       // C---V
#define AHCI_HBA_EM_CTL_0_ATTR_SMB_SHIFT                    _MK_SHIFT_CONST(24)                                                             // C--VF
#define AHCI_HBA_EM_CTL_0_ATTR_SMB_FIELD                   (_MK_SHIFT_CONST(0x1) << AHCI_HBA_EM_CTL_0_ATTR_SMB_SHIFT)
#define AHCI_HBA_EM_CTL_0_ATTR_SMB_RANGE                   24:24
#define AHCI_HBA_EM_CTL_0_ATTR_SMB_WOFFSET                 0
#define AHCI_HBA_EM_CTL_0_ATTR_SMB__NOPRDCHK               _MK_ENUM_CONST(0x00000001)                                                       // ----V
#define AHCI_HBA_EM_CTL_0_ATTR_SMB_FALSE                   _MK_ENUM_CONST(0x00000000)                                                       // C---V
#define AHCI_HBA_EM_CTL_0_ATTR_SMB_TRUE                    _MK_ENUM_CONST(0x00000001)                                                       // ----V
#define AHCI_HBA_EM_CTL_0_ATTR_XMT_SHIFT                    _MK_SHIFT_CONST(25)                                                             // C--VF
#define AHCI_HBA_EM_CTL_0_ATTR_XMT_FIELD                   (_MK_SHIFT_CONST(0x1) << AHCI_HBA_EM_CTL_0_ATTR_XMT_SHIFT)
#define AHCI_HBA_EM_CTL_0_ATTR_XMT_RANGE                   25:25
#define AHCI_HBA_EM_CTL_0_ATTR_XMT_WOFFSET                 0
#define AHCI_HBA_EM_CTL_0_ATTR_XMT__NOPRDCHK               _MK_ENUM_CONST(0x00000001)                                                       // ----V
#define AHCI_HBA_EM_CTL_0_ATTR_XMT_FALSE                   _MK_ENUM_CONST(0x00000000)                                                       // C---V
#define AHCI_HBA_EM_CTL_0_ATTR_XMT_TRUE                    _MK_ENUM_CONST(0x00000001)                                                       // ----V
#define AHCI_HBA_EM_CTL_0_ATTR_ALHD_SHIFT                   _MK_SHIFT_CONST(26)                                                             // C--VF
#define AHCI_HBA_EM_CTL_0_ATTR_ALHD_FIELD                  (_MK_SHIFT_CONST(0x1) << AHCI_HBA_EM_CTL_0_ATTR_ALHD_SHIFT)
#define AHCI_HBA_EM_CTL_0_ATTR_ALHD_RANGE                  26:26
#define AHCI_HBA_EM_CTL_0_ATTR_ALHD_WOFFSET                0
#define AHCI_HBA_EM_CTL_0_ATTR_ALHD__NOPRDCHK              _MK_ENUM_CONST(0x00000001)                                                       // ----V
#define AHCI_HBA_EM_CTL_0_ATTR_ALHD_FALSE                  _MK_ENUM_CONST(0x00000000)                                                       // C---V
#define AHCI_HBA_EM_CTL_0_ATTR_ALHD_TRUE                   _MK_ENUM_CONST(0x00000001)                                                       // ----V
#define AHCI_HBA_EM_CTL_0_ATTR_PM_SHIFT                     _MK_SHIFT_CONST(27)                                                             // C--VF
#define AHCI_HBA_EM_CTL_0_ATTR_PM_FIELD                    (_MK_SHIFT_CONST(0x1) << AHCI_HBA_EM_CTL_0_ATTR_PM_SHIFT)
#define AHCI_HBA_EM_CTL_0_ATTR_PM_RANGE                    27:27
#define AHCI_HBA_EM_CTL_0_ATTR_PM_WOFFSET                  0
#define AHCI_HBA_EM_CTL_0_ATTR_PM__NOPRDCHK                _MK_ENUM_CONST(0x00000001)                                                       // ----V
#define AHCI_HBA_EM_CTL_0_ATTR_PM_FALSE                    _MK_ENUM_CONST(0x00000000)                                                       // C---V
#define AHCI_HBA_EM_CTL_0_ATTR_PM_TRUE                     _MK_ENUM_CONST(0x00000001)                                                       // ----V
#define AHCI_HBA_EM_CTL_0_RSVD3_SHIFT                       _MK_SHIFT_CONST(28)                                                             // C--VF
#define AHCI_HBA_EM_CTL_0_RSVD3_FIELD                      (_MK_SHIFT_CONST(0xf) << AHCI_HBA_EM_CTL_0_RSVD3_SHIFT)
#define AHCI_HBA_EM_CTL_0_RSVD3_RANGE                      31:28
#define AHCI_HBA_EM_CTL_0_RSVD3_WOFFSET                    0
#define AHCI_HBA_EM_CTL_0_RSVD3_VAL                        _MK_ENUM_CONST(0x00000000)                                                       // C---V
// 
// 
//              Figure 9-9 HBA Enclosure Management Control Register.
// .TITLE CAP2 - HBA Capabilities Extended
//        This register indicates basic capabilities to Software.
// 
// .FIELD BOH
// When set to 1, the HBA supports the BIOS/OS handoff
// mechanism defined in section 10.6. When cleared to 0, the HBA does not support the
// BIOS/OS handoff mechanism. When BIOS/OS handoff is supported, the HBA has
// implemented the BOHC global HBA register. When cleared to 0, it indicates that the
// HBA does not support BIOS/OS handoff and the BOHC global HBA register is not
// implemented.
// 
// .FIELD APST
// When set to 1, the HBA supports
// Automatic Partial to Slumber Transitions. When cleared to 0, Automatic Partial to
// Slumber Transitions are not supported. Please refer to section 10.16 for more
// information regarding Automatic Partial to Slumber transitions.
// 
// .FIELD SDS
// When set to 1, the HBA supports the Device Sleep feature. When cleared to 0,
// DEVSLP is not supported and software shall not set PxCMD.ICC to '8h'
// 
// .FIELD SADM
// When set to 1, the HBA supports hardware assertion of the DEVSLP signal after
// the idle timeout expires. When cleared to 0, this function is not supported and
// software shall treat the PxDEVSLP.ADSE field as reserved. Refer to section 8.5.1.
// 
// .FIELD DESO
// This field specifies that the HBA shall only assert the DEVSLP signal if the interface is
// in Slumber.  When this bit is set to 1, the HBA shall ignore software directed entrance
// to DevSleep via PxCMD.ICC unless PxSSTS.IPM = 6h.
// When this bit is cleared to 0, the HBA may enter DevSleep from any link state
// (active, Partial, or Slumber).
// 
// 31           24 23           16 15            8 7             0
// .-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-.
// |0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0| HBA_CAP2
// `-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-'
// 
#define AHCI_HBA_CAP2_0                                    0x00000024                                                                       // R-I4R
#define AHCI_HBA_CAP2_0_SECURE                             0
#define AHCI_HBA_CAP2_0_WORD_COUNT                         1
#define AHCI_HBA_CAP2_0_RESET_VAL                          0x0
#define AHCI_HBA_CAP2_0_RESET_MASK                         0x0
#define AHCI_HBA_CAP2_0_SW_DEFAULT_VAL                     0x0
#define AHCI_HBA_CAP2_0_SW_DEFAULT_MASK                    0x0
#define AHCI_HBA_CAP2_0_READ_MASK                          0xffffffff
#define AHCI_HBA_CAP2_0_WRITE_MASK                         0x0
#define AHCI_HBA_CAP2_0_BOH_SHIFT                           _MK_SHIFT_CONST(0)                                                              // R-CVF
#define AHCI_HBA_CAP2_0_BOH_FIELD                          (_MK_SHIFT_CONST(0x1) << AHCI_HBA_CAP2_0_BOH_SHIFT)
#define AHCI_HBA_CAP2_0_BOH_RANGE                          0:0
#define AHCI_HBA_CAP2_0_BOH_WOFFSET                        0
#define AHCI_HBA_CAP2_0_BOH_TRUE                           _MK_ENUM_CONST(0x00000001)                                                       // R---V
#define AHCI_HBA_CAP2_0_BOH_FALSE                          _MK_ENUM_CONST(0x00000000)                                                       // R-C-V
#define AHCI_HBA_CAP2_0_RSVD_0_SHIFT                        _MK_SHIFT_CONST(1)                                                              // C--VF
#define AHCI_HBA_CAP2_0_RSVD_0_FIELD                       (_MK_SHIFT_CONST(0x1) << AHCI_HBA_CAP2_0_RSVD_0_SHIFT)
#define AHCI_HBA_CAP2_0_RSVD_0_RANGE                       1:1
#define AHCI_HBA_CAP2_0_RSVD_0_WOFFSET                     0
#define AHCI_HBA_CAP2_0_RSVD_0_VAL                         _MK_ENUM_CONST(0x00000000)                                                       // C---V
#define AHCI_HBA_CAP2_0_APST_SHIFT                          _MK_SHIFT_CONST(2)                                                              // R-CVF
#define AHCI_HBA_CAP2_0_APST_FIELD                         (_MK_SHIFT_CONST(0x1) << AHCI_HBA_CAP2_0_APST_SHIFT)
#define AHCI_HBA_CAP2_0_APST_RANGE                         2:2
#define AHCI_HBA_CAP2_0_APST_WOFFSET                       0
#define AHCI_HBA_CAP2_0_APST_TRUE                          _MK_ENUM_CONST(0x00000001)                                                       // R-C-V
#define AHCI_HBA_CAP2_0_APST_FALSE                         _MK_ENUM_CONST(0x00000000)                                                       // R---V
#define AHCI_HBA_CAP2_0_SDS_SHIFT                           _MK_SHIFT_CONST(3)                                                              // R-CVF
#define AHCI_HBA_CAP2_0_SDS_FIELD                          (_MK_SHIFT_CONST(0x1) << AHCI_HBA_CAP2_0_SDS_SHIFT)
#define AHCI_HBA_CAP2_0_SDS_RANGE                          3:3
#define AHCI_HBA_CAP2_0_SDS_WOFFSET                        0
#define AHCI_HBA_CAP2_0_SDS_TRUE                           _MK_ENUM_CONST(0x00000001)                                                       // R-C-V
#define AHCI_HBA_CAP2_0_SDS_FALSE                          _MK_ENUM_CONST(0x00000000)                                                       // R---V
#define AHCI_HBA_CAP2_0_SADM_SHIFT                          _MK_SHIFT_CONST(4)                                                              // R-CVF
#define AHCI_HBA_CAP2_0_SADM_FIELD                         (_MK_SHIFT_CONST(0x1) << AHCI_HBA_CAP2_0_SADM_SHIFT)
#define AHCI_HBA_CAP2_0_SADM_RANGE                         4:4
#define AHCI_HBA_CAP2_0_SADM_WOFFSET                       0
#define AHCI_HBA_CAP2_0_SADM_TRUE                          _MK_ENUM_CONST(0x00000001)                                                       // R-C-V
#define AHCI_HBA_CAP2_0_SADM_FALSE                         _MK_ENUM_CONST(0x00000000)                                                       // R---V
#define AHCI_HBA_CAP2_0_DESO_SHIFT                          _MK_SHIFT_CONST(5)                                                              // R-CVF
#define AHCI_HBA_CAP2_0_DESO_FIELD                         (_MK_SHIFT_CONST(0x1) << AHCI_HBA_CAP2_0_DESO_SHIFT)
#define AHCI_HBA_CAP2_0_DESO_RANGE                         5:5
#define AHCI_HBA_CAP2_0_DESO_WOFFSET                       0
#define AHCI_HBA_CAP2_0_DESO_TRUE                          _MK_ENUM_CONST(0x00000001)                                                       // R-C-V
#define AHCI_HBA_CAP2_0_DESO_FALSE                         _MK_ENUM_CONST(0x00000000)                                                       // R---V
#define AHCI_HBA_CAP2_0_RSVD_1_SHIFT                        _MK_SHIFT_CONST(6)                                                              // C--VF
#define AHCI_HBA_CAP2_0_RSVD_1_FIELD                       (_MK_SHIFT_CONST(0x3ffffff) << AHCI_HBA_CAP2_0_RSVD_1_SHIFT)
#define AHCI_HBA_CAP2_0_RSVD_1_RANGE                       31:6
#define AHCI_HBA_CAP2_0_RSVD_1_WOFFSET                     0
#define AHCI_HBA_CAP2_0_RSVD_1_VAL                         _MK_ENUM_CONST(0x00000000)                                                       // C---V
// 
//              Figure 9-10 HBA Capabilities Extended
// 
// .TITLE BOHC - BIOS/OS Handoff Control and Status
//        This register controls various global actions of the HBA
// 
// .FIELD BOS
// BIOS Owned Semaphore (BOS)
// .FIELD OOS
// OS Owned Semaphore   (OOS)
// .FIELD SOOE
// SMI on OS Ownership Change Enable (SOOE)
// .FIELD OOC
// OS Ownership Change (OOC)
// .FIELD BB
// BIOS Busy (BB)
// 
// 
// 31           24 23           16 15            8 7             0
// .-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-.
// |0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0| HBA_BOHC
// `-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-'
#define AHCI_HBA_BOHC_0                                    0x00000028                                                                       // R-I4R
#define AHCI_HBA_BOHC_0_SECURE                             0
#define AHCI_HBA_BOHC_0_WORD_COUNT                         1
#define AHCI_HBA_BOHC_0_RESET_VAL                          0x0
#define AHCI_HBA_BOHC_0_RESET_MASK                         0x0
#define AHCI_HBA_BOHC_0_SW_DEFAULT_VAL                     0x0
#define AHCI_HBA_BOHC_0_SW_DEFAULT_MASK                    0x0
#define AHCI_HBA_BOHC_0_READ_MASK                          0xffffffff
#define AHCI_HBA_BOHC_0_WRITE_MASK                         0x1f
#define AHCI_HBA_BOHC_0_BOS_SHIFT                           _MK_SHIFT_CONST(0)                                                              // RWWVF
#define AHCI_HBA_BOHC_0_BOS_FIELD                          (_MK_SHIFT_CONST(0x1) << AHCI_HBA_BOHC_0_BOS_SHIFT)
#define AHCI_HBA_BOHC_0_BOS_RANGE                          0:0
#define AHCI_HBA_BOHC_0_BOS_WOFFSET                        0
#define AHCI_HBA_BOHC_0_BOS_DEFAULT                        (_MK_MASK_CONST(0x00000000)
#define AHCI_HBA_BOHC_0_BOS_DEFAULT_MASK                   (_MK_MASK_CONST(0x1)
#define AHCI_HBA_BOHC_0_BOS_SW_DEFAULT                     (_MK_MASK_CONST(0x00000000)
#define AHCI_HBA_BOHC_0_BOS_SW_DEFAULT_MASK                (_MK_MASK_CONST(0x1)
#define AHCI_HBA_BOHC_0_BOS_TRUE                           _MK_ENUM_CONST(0x00000001)                                                       // RW--V
#define AHCI_HBA_BOHC_0_BOS_FALSE                          _MK_ENUM_CONST(0x00000000)                                                       // RWW-V
#define AHCI_HBA_BOHC_0_OOS_SHIFT                           _MK_SHIFT_CONST(1)                                                              // RWWVF
#define AHCI_HBA_BOHC_0_OOS_FIELD                          (_MK_SHIFT_CONST(0x1) << AHCI_HBA_BOHC_0_OOS_SHIFT)
#define AHCI_HBA_BOHC_0_OOS_RANGE                          1:1
#define AHCI_HBA_BOHC_0_OOS_WOFFSET                        0
#define AHCI_HBA_BOHC_0_OOS_DEFAULT                        (_MK_MASK_CONST(0x00000000)
#define AHCI_HBA_BOHC_0_OOS_DEFAULT_MASK                   (_MK_MASK_CONST(0x1)
#define AHCI_HBA_BOHC_0_OOS_SW_DEFAULT                     (_MK_MASK_CONST(0x00000000)
#define AHCI_HBA_BOHC_0_OOS_SW_DEFAULT_MASK                (_MK_MASK_CONST(0x1)
#define AHCI_HBA_BOHC_0_OOS_TRUE                           _MK_ENUM_CONST(0x00000001)                                                       // RW--V
#define AHCI_HBA_BOHC_0_OOS_FALSE                          _MK_ENUM_CONST(0x00000000)                                                       // RWW-V
#define AHCI_HBA_BOHC_0_SOOE_SHIFT                          _MK_SHIFT_CONST(2)                                                              // RWWVF
#define AHCI_HBA_BOHC_0_SOOE_FIELD                         (_MK_SHIFT_CONST(0x1) << AHCI_HBA_BOHC_0_SOOE_SHIFT)
#define AHCI_HBA_BOHC_0_SOOE_RANGE                         2:2
#define AHCI_HBA_BOHC_0_SOOE_WOFFSET                       0
#define AHCI_HBA_BOHC_0_SOOE_DEFAULT                       (_MK_MASK_CONST(0x00000000)
#define AHCI_HBA_BOHC_0_SOOE_DEFAULT_MASK                  (_MK_MASK_CONST(0x1)
#define AHCI_HBA_BOHC_0_SOOE_SW_DEFAULT                    (_MK_MASK_CONST(0x00000000)
#define AHCI_HBA_BOHC_0_SOOE_SW_DEFAULT_MASK               (_MK_MASK_CONST(0x1)
#define AHCI_HBA_BOHC_0_SOOE_TRUE                          _MK_ENUM_CONST(0x00000001)                                                       // RW--V
#define AHCI_HBA_BOHC_0_SOOE_FALSE                         _MK_ENUM_CONST(0x00000000)                                                       // RWW-V
#define AHCI_HBA_BOHC_0_OOC_SHIFT                           _MK_SHIFT_CONST(3)                                                              // RWWVF
#define AHCI_HBA_BOHC_0_OOC_FIELD                          (_MK_SHIFT_CONST(0x1) << AHCI_HBA_BOHC_0_OOC_SHIFT)
#define AHCI_HBA_BOHC_0_OOC_RANGE                          3:3
#define AHCI_HBA_BOHC_0_OOC_WOFFSET                        0
#define AHCI_HBA_BOHC_0_OOC_DEFAULT                        (_MK_MASK_CONST(0x00000000)
#define AHCI_HBA_BOHC_0_OOC_DEFAULT_MASK                   (_MK_MASK_CONST(0x1)
#define AHCI_HBA_BOHC_0_OOC_SW_DEFAULT                     (_MK_MASK_CONST(0x00000000)
#define AHCI_HBA_BOHC_0_OOC_SW_DEFAULT_MASK                (_MK_MASK_CONST(0x1)
#define AHCI_HBA_BOHC_0_OOC_TRUE                           _MK_ENUM_CONST(0x00000001)                                                       // R---V
#define AHCI_HBA_BOHC_0_OOC_FALSE                          _MK_ENUM_CONST(0x00000000)                                                       // R-W-V
#define AHCI_HBA_BOHC_0_OOC_CLEAR                          _MK_ENUM_CONST(0x00000001)                                                       // -W--C
#define AHCI_HBA_BOHC_0_BB_SHIFT                            _MK_SHIFT_CONST(4)                                                              // RWWVF
#define AHCI_HBA_BOHC_0_BB_FIELD                           (_MK_SHIFT_CONST(0x1) << AHCI_HBA_BOHC_0_BB_SHIFT)
#define AHCI_HBA_BOHC_0_BB_RANGE                           4:4
#define AHCI_HBA_BOHC_0_BB_WOFFSET                         0
#define AHCI_HBA_BOHC_0_BB_DEFAULT                         (_MK_MASK_CONST(0x00000000)
#define AHCI_HBA_BOHC_0_BB_DEFAULT_MASK                    (_MK_MASK_CONST(0x1)
#define AHCI_HBA_BOHC_0_BB_SW_DEFAULT                      (_MK_MASK_CONST(0x00000000)
#define AHCI_HBA_BOHC_0_BB_SW_DEFAULT_MASK                 (_MK_MASK_CONST(0x1)
#define AHCI_HBA_BOHC_0_BB_TRUE                            _MK_ENUM_CONST(0x00000001)                                                       // RW--V
#define AHCI_HBA_BOHC_0_BB_FALSE                           _MK_ENUM_CONST(0x00000000)                                                       // RWW-V
#define AHCI_HBA_BOHC_0_RSVD_SHIFT                          _MK_SHIFT_CONST(5)                                                              // C--VF
#define AHCI_HBA_BOHC_0_RSVD_FIELD                         (_MK_SHIFT_CONST(0x7ffffff) << AHCI_HBA_BOHC_0_RSVD_SHIFT)
#define AHCI_HBA_BOHC_0_RSVD_RANGE                         31:5
#define AHCI_HBA_BOHC_0_RSVD_WOFFSET                       0
#define AHCI_HBA_BOHC_0_RSVD_VAL                           _MK_ENUM_CONST(0x00000000)                                                       // C---V
// 
//              Figure 9-11 BOHC - BIOS/OS Handoff Control and Status
// 
// 
// 
// .LABEL PUBLIC
// .TITLE HBA_CAP_BKDR
// .LABEL PRIVATE
// SW_INIT required for this register to enable SALP, SSC, PSC
// .LABEL PUBLIC
// 
// .FIELD NUM_PORTS
// CAP.NP can be written using this
// 
// .FIELD INTF_SPD_SUPP
// CAP.ISS can be written using this
// 
// .LABEL PRIVATE INT_REL
// .FIELD EXT_SATA
// This is a backdoor access for enabling external sata.
// 
// .FIELD SUPP_STG_SPUP
// Backdoor field to advertise staggered spin up. BIOS has to write this we are going to support staggered spin up.
// 
// 31           24 23           16 15            8 7             0
// .-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-.
// |0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0| HBA_CAP_BKDR
// `-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-'
// 
// .LABEL PUBLIC
#define AHCI_HBA_CAP_BKDR_0                                0x000000A0                                                                       // RW-4R
#define AHCI_HBA_CAP_BKDR_0_SECURE                         0
#define AHCI_HBA_CAP_BKDR_0_WORD_COUNT                     1
#define AHCI_HBA_CAP_BKDR_0_RESET_VAL                      0x0
#define AHCI_HBA_CAP_BKDR_0_RESET_MASK                     0x0
#define AHCI_HBA_CAP_BKDR_0_SW_DEFAULT_VAL                 0x0
#define AHCI_HBA_CAP_BKDR_0_SW_DEFAULT_MASK                0x0
#define AHCI_HBA_CAP_BKDR_0_READ_MASK                      0xffffffff
#define AHCI_HBA_CAP_BKDR_0_WRITE_MASK                     0xffffffff
#define AHCI_HBA_CAP_BKDR_0_NUM_PORTS_SHIFT                 _MK_SHIFT_CONST(0)                                                              // RWCVF
#define AHCI_HBA_CAP_BKDR_0_NUM_PORTS_FIELD                (_MK_SHIFT_CONST(0x1f) << AHCI_HBA_CAP_BKDR_0_NUM_PORTS_SHIFT)
#define AHCI_HBA_CAP_BKDR_0_NUM_PORTS_RANGE                4:0
#define AHCI_HBA_CAP_BKDR_0_NUM_PORTS_WOFFSET              0
#define AHCI_HBA_CAP_BKDR_0_NUM_PORTS_1                    _MK_ENUM_CONST(0x00000000)                                                       // RW--V
#define AHCI_HBA_CAP_BKDR_0_NUM_PORTS_2                    _MK_ENUM_CONST(0x00000001)                                                       // RW--V
#define AHCI_HBA_CAP_BKDR_0_NUM_PORTS_3                    _MK_ENUM_CONST(0x00000002)                                                       // RW--V
#define AHCI_HBA_CAP_BKDR_0_NUM_PORTS_4                    _MK_ENUM_CONST(0x00000003)                                                       // RW--V
#define AHCI_HBA_CAP_BKDR_0_NUM_PORTS_DEFUALT              _MK_ENUM_CONST(0x00000001)                                                       // R-C-V
#define AHCI_HBA_CAP_BKDR_0_EXT_SATA_SHIFT                  _MK_SHIFT_CONST(5)                                                              // RWCVF
#define AHCI_HBA_CAP_BKDR_0_EXT_SATA_FIELD                 (_MK_SHIFT_CONST(0x1) << AHCI_HBA_CAP_BKDR_0_EXT_SATA_SHIFT)
#define AHCI_HBA_CAP_BKDR_0_EXT_SATA_RANGE                 5:5
#define AHCI_HBA_CAP_BKDR_0_EXT_SATA_WOFFSET               0
#define AHCI_HBA_CAP_BKDR_0_EXT_SATA_SUPPORTED             _MK_ENUM_CONST(0x00000001)                                                       // RW--V
#define AHCI_HBA_CAP_BKDR_0_EXT_SATA_NOT_SUPPORTED         _MK_ENUM_CONST(0x00000000)                                                       // RWC-V
#define AHCI_HBA_CAP_BKDR_0_ENCL_MGMT_SUPP_SHIFT            _MK_SHIFT_CONST(6)                                                              // RWCVF
#define AHCI_HBA_CAP_BKDR_0_ENCL_MGMT_SUPP_FIELD           (_MK_SHIFT_CONST(0x1) << AHCI_HBA_CAP_BKDR_0_ENCL_MGMT_SUPP_SHIFT)
#define AHCI_HBA_CAP_BKDR_0_ENCL_MGMT_SUPP_RANGE           6:6
#define AHCI_HBA_CAP_BKDR_0_ENCL_MGMT_SUPP_WOFFSET         0
#define AHCI_HBA_CAP_BKDR_0_ENCL_MGMT_SUPP_TRUE            _MK_ENUM_CONST(0x00000001)                                                       // RW--V
#define AHCI_HBA_CAP_BKDR_0_ENCL_MGMT_SUPP_FALSE           _MK_ENUM_CONST(0x00000000)                                                       // RWC-V
#define AHCI_HBA_CAP_BKDR_0_CMD_CMPL_COALESING_SHIFT        _MK_SHIFT_CONST(7)                                                              // RWCVF
#define AHCI_HBA_CAP_BKDR_0_CMD_CMPL_COALESING_FIELD       (_MK_SHIFT_CONST(0x1) << AHCI_HBA_CAP_BKDR_0_CMD_CMPL_COALESING_SHIFT)
#define AHCI_HBA_CAP_BKDR_0_CMD_CMPL_COALESING_RANGE       7:7
#define AHCI_HBA_CAP_BKDR_0_CMD_CMPL_COALESING_WOFFSET     0
#define AHCI_HBA_CAP_BKDR_0_CMD_CMPL_COALESING_TRUE        _MK_ENUM_CONST(0x00000001)                                                       // RW--V
#define AHCI_HBA_CAP_BKDR_0_CMD_CMPL_COALESING_FALSE       _MK_ENUM_CONST(0x00000000)                                                       // RWC-V
#define AHCI_HBA_CAP_BKDR_0_NUM_CMD_SLOTS_SHIFT             _MK_SHIFT_CONST(8)                                                              // RWCVF
#define AHCI_HBA_CAP_BKDR_0_NUM_CMD_SLOTS_FIELD            (_MK_SHIFT_CONST(0x1f) << AHCI_HBA_CAP_BKDR_0_NUM_CMD_SLOTS_SHIFT)
#define AHCI_HBA_CAP_BKDR_0_NUM_CMD_SLOTS_RANGE            12:8
#define AHCI_HBA_CAP_BKDR_0_NUM_CMD_SLOTS_WOFFSET          0
#define AHCI_HBA_CAP_BKDR_0_NUM_CMD_SLOTS_1                _MK_ENUM_CONST(0x00000000)                                                       // RW--V
#define AHCI_HBA_CAP_BKDR_0_NUM_CMD_SLOTS_8                _MK_ENUM_CONST(0x00000007)                                                       // RW--V
#define AHCI_HBA_CAP_BKDR_0_NUM_CMD_SLOTS_16               _MK_ENUM_CONST(0x0000000F)                                                       // RW--V
#define AHCI_HBA_CAP_BKDR_0_NUM_CMD_SLOTS_32               _MK_ENUM_CONST(0x0000001F)                                                       // RWC-V
#define AHCI_HBA_CAP_BKDR_0_PARTIAL_ST_CAP_SHIFT            _MK_SHIFT_CONST(13)                                                             // RWCVF
#define AHCI_HBA_CAP_BKDR_0_PARTIAL_ST_CAP_FIELD           (_MK_SHIFT_CONST(0x1) << AHCI_HBA_CAP_BKDR_0_PARTIAL_ST_CAP_SHIFT)
#define AHCI_HBA_CAP_BKDR_0_PARTIAL_ST_CAP_RANGE           13:13
#define AHCI_HBA_CAP_BKDR_0_PARTIAL_ST_CAP_WOFFSET         0
#define AHCI_HBA_CAP_BKDR_0_PARTIAL_ST_CAP__WRNPRDCHK      _MK_ENUM_CONST(0x00000001)                                                       // ----V
#define AHCI_HBA_CAP_BKDR_0_PARTIAL_ST_CAP_TRUE            _MK_ENUM_CONST(0x00000001)                                                       // RWC-V
#define AHCI_HBA_CAP_BKDR_0_PARTIAL_ST_CAP_FALSE           _MK_ENUM_CONST(0x00000000)                                                       // RW--V
#define AHCI_HBA_CAP_BKDR_0_SLUMBER_ST_CAP_SHIFT            _MK_SHIFT_CONST(14)                                                             // RWCVF
#define AHCI_HBA_CAP_BKDR_0_SLUMBER_ST_CAP_FIELD           (_MK_SHIFT_CONST(0x1) << AHCI_HBA_CAP_BKDR_0_SLUMBER_ST_CAP_SHIFT)
#define AHCI_HBA_CAP_BKDR_0_SLUMBER_ST_CAP_RANGE           14:14
#define AHCI_HBA_CAP_BKDR_0_SLUMBER_ST_CAP_WOFFSET         0
#define AHCI_HBA_CAP_BKDR_0_SLUMBER_ST_CAP__WRNPRDCHK      _MK_ENUM_CONST(0x00000001)                                                       // ----V
#define AHCI_HBA_CAP_BKDR_0_SLUMBER_ST_CAP_TRUE            _MK_ENUM_CONST(0x00000001)                                                       // RWC-V
#define AHCI_HBA_CAP_BKDR_0_SLUMBER_ST_CAP_FALSE           _MK_ENUM_CONST(0x00000000)                                                       // RW--V
#define AHCI_HBA_CAP_BKDR_0_PIO_MULT_DRQ_BLK_SHIFT          _MK_SHIFT_CONST(15)                                                             // RWCVF
#define AHCI_HBA_CAP_BKDR_0_PIO_MULT_DRQ_BLK_FIELD         (_MK_SHIFT_CONST(0x1) << AHCI_HBA_CAP_BKDR_0_PIO_MULT_DRQ_BLK_SHIFT)
#define AHCI_HBA_CAP_BKDR_0_PIO_MULT_DRQ_BLK_RANGE         15:15
#define AHCI_HBA_CAP_BKDR_0_PIO_MULT_DRQ_BLK_WOFFSET       0
#define AHCI_HBA_CAP_BKDR_0_PIO_MULT_DRQ_BLK_SUPP          _MK_ENUM_CONST(0x00000001)                                                       // RWC-V
#define AHCI_HBA_CAP_BKDR_0_PIO_MULT_DRQ_BLK_NOT_SUPP      _MK_ENUM_CONST(0x00000000)                                                       // RW--V
#define AHCI_HBA_CAP_BKDR_0_FIS_SWITCHING_SHIFT             _MK_SHIFT_CONST(16)                                                             // RWCVF
#define AHCI_HBA_CAP_BKDR_0_FIS_SWITCHING_FIELD            (_MK_SHIFT_CONST(0x1) << AHCI_HBA_CAP_BKDR_0_FIS_SWITCHING_SHIFT)
#define AHCI_HBA_CAP_BKDR_0_FIS_SWITCHING_RANGE            16:16
#define AHCI_HBA_CAP_BKDR_0_FIS_SWITCHING_WOFFSET          0
#define AHCI_HBA_CAP_BKDR_0_FIS_SWITCHING_TRUE             _MK_ENUM_CONST(0x00000001)                                                       // RW--V
#define AHCI_HBA_CAP_BKDR_0_FIS_SWITCHING_FALSE            _MK_ENUM_CONST(0x00000000)                                                       // RWC-V
#define AHCI_HBA_CAP_BKDR_0_SUPP_PM_SHIFT                   _MK_SHIFT_CONST(17)                                                             // RWCVF
#define AHCI_HBA_CAP_BKDR_0_SUPP_PM_FIELD                  (_MK_SHIFT_CONST(0x1) << AHCI_HBA_CAP_BKDR_0_SUPP_PM_SHIFT)
#define AHCI_HBA_CAP_BKDR_0_SUPP_PM_RANGE                  17:17
#define AHCI_HBA_CAP_BKDR_0_SUPP_PM_WOFFSET                0
#define AHCI_HBA_CAP_BKDR_0_SUPP_PM_TRUE                   _MK_ENUM_CONST(0x00000001)                                                       // RW--V
#define AHCI_HBA_CAP_BKDR_0_SUPP_PM_FALSE                  _MK_ENUM_CONST(0x00000000)                                                       // RWC-V
#define AHCI_HBA_CAP_BKDR_0_SUPP_AHCI_ONLY_SHIFT            _MK_SHIFT_CONST(18)                                                             // RWCVF
#define AHCI_HBA_CAP_BKDR_0_SUPP_AHCI_ONLY_FIELD           (_MK_SHIFT_CONST(0x1) << AHCI_HBA_CAP_BKDR_0_SUPP_AHCI_ONLY_SHIFT)
#define AHCI_HBA_CAP_BKDR_0_SUPP_AHCI_ONLY_RANGE           18:18
#define AHCI_HBA_CAP_BKDR_0_SUPP_AHCI_ONLY_WOFFSET         0
#define AHCI_HBA_CAP_BKDR_0_SUPP_AHCI_ONLY_TRUE            _MK_ENUM_CONST(0x00000001)                                                       // RW--V
#define AHCI_HBA_CAP_BKDR_0_SUPP_AHCI_ONLY_FALSE           _MK_ENUM_CONST(0x00000000)                                                       // RWC-V
#define AHCI_HBA_CAP_BKDR_0_SUPP_NONZERO_OFFSET_SHIFT       _MK_SHIFT_CONST(19)                                                             // RWCVF
#define AHCI_HBA_CAP_BKDR_0_SUPP_NONZERO_OFFSET_FIELD      (_MK_SHIFT_CONST(0x1) << AHCI_HBA_CAP_BKDR_0_SUPP_NONZERO_OFFSET_SHIFT)
#define AHCI_HBA_CAP_BKDR_0_SUPP_NONZERO_OFFSET_RANGE      19:19
#define AHCI_HBA_CAP_BKDR_0_SUPP_NONZERO_OFFSET_WOFFSET    0
#define AHCI_HBA_CAP_BKDR_0_SUPP_NONZERO_OFFSET_TRUE       _MK_ENUM_CONST(0x00000001)                                                       // RW--V
#define AHCI_HBA_CAP_BKDR_0_SUPP_NONZERO_OFFSET_FALSE      _MK_ENUM_CONST(0x00000000)                                                       // RWC-V
#define AHCI_HBA_CAP_BKDR_0_INTF_SPD_SUPP_SHIFT             _MK_SHIFT_CONST(20)                                                             // RWCVF
#define AHCI_HBA_CAP_BKDR_0_INTF_SPD_SUPP_FIELD            (_MK_SHIFT_CONST(0xf) << AHCI_HBA_CAP_BKDR_0_INTF_SPD_SUPP_SHIFT)
#define AHCI_HBA_CAP_BKDR_0_INTF_SPD_SUPP_RANGE            23:20
#define AHCI_HBA_CAP_BKDR_0_INTF_SPD_SUPP_WOFFSET          0
#define AHCI_HBA_CAP_BKDR_0_INTF_SPD_SUPP_RSVD             _MK_ENUM_CONST(0x00000000)                                                       // RW--V
#define AHCI_HBA_CAP_BKDR_0_INTF_SPD_SUPP_GEN1             _MK_ENUM_CONST(0x00000001)                                                       // RW--V
#define AHCI_HBA_CAP_BKDR_0_INTF_SPD_SUPP_GEN1_2           _MK_ENUM_CONST(0x00000002)                                                       // RWC-V
#define AHCI_HBA_CAP_BKDR_0_INTF_SPD_SUPP_GEN1_3           _MK_ENUM_CONST(0x00000003)                                                       // RW--V
#define AHCI_HBA_CAP_BKDR_0_SUPP_CLO_SHIFT                  _MK_SHIFT_CONST(24)                                                             // RWCVF
#define AHCI_HBA_CAP_BKDR_0_SUPP_CLO_FIELD                 (_MK_SHIFT_CONST(0x1) << AHCI_HBA_CAP_BKDR_0_SUPP_CLO_SHIFT)
#define AHCI_HBA_CAP_BKDR_0_SUPP_CLO_RANGE                 24:24
#define AHCI_HBA_CAP_BKDR_0_SUPP_CLO_WOFFSET               0
#define AHCI_HBA_CAP_BKDR_0_SUPP_CLO_TRUE                  _MK_ENUM_CONST(0x00000001)                                                       // RW--V
#define AHCI_HBA_CAP_BKDR_0_SUPP_CLO_FALSE                 _MK_ENUM_CONST(0x00000000)                                                       // RWC-V
#define AHCI_HBA_CAP_BKDR_0_SAL_SHIFT                       _MK_SHIFT_CONST(25)                                                             // RWCVF
#define AHCI_HBA_CAP_BKDR_0_SAL_FIELD                      (_MK_SHIFT_CONST(0x1) << AHCI_HBA_CAP_BKDR_0_SAL_SHIFT)
#define AHCI_HBA_CAP_BKDR_0_SAL_RANGE                      25:25
#define AHCI_HBA_CAP_BKDR_0_SAL_WOFFSET                    0
#define AHCI_HBA_CAP_BKDR_0_SAL_TRUE                       _MK_ENUM_CONST(0x00000001)                                                       // RWC-V
#define AHCI_HBA_CAP_BKDR_0_SAL_FALSE                      _MK_ENUM_CONST(0x00000000)                                                       // RW--V
#define AHCI_HBA_CAP_BKDR_0_SALP_SHIFT                      _MK_SHIFT_CONST(26)                                                             // RWCVF
#define AHCI_HBA_CAP_BKDR_0_SALP_FIELD                     (_MK_SHIFT_CONST(0x1) << AHCI_HBA_CAP_BKDR_0_SALP_SHIFT)
#define AHCI_HBA_CAP_BKDR_0_SALP_RANGE                     26:26
#define AHCI_HBA_CAP_BKDR_0_SALP_WOFFSET                   0
#define AHCI_HBA_CAP_BKDR_0_SALP_TRUE                      _MK_ENUM_CONST(0x00000001)                                                       // RWC-V
#define AHCI_HBA_CAP_BKDR_0_SALP_FALSE                     _MK_ENUM_CONST(0x00000000)                                                       // RW--V
#define AHCI_HBA_CAP_BKDR_0_SUPP_STG_SPUP_SHIFT             _MK_SHIFT_CONST(27)                                                             // RWCVF
#define AHCI_HBA_CAP_BKDR_0_SUPP_STG_SPUP_FIELD            (_MK_SHIFT_CONST(0x1) << AHCI_HBA_CAP_BKDR_0_SUPP_STG_SPUP_SHIFT)
#define AHCI_HBA_CAP_BKDR_0_SUPP_STG_SPUP_RANGE            27:27
#define AHCI_HBA_CAP_BKDR_0_SUPP_STG_SPUP_WOFFSET          0
#define AHCI_HBA_CAP_BKDR_0_SUPP_STG_SPUP_SET              _MK_ENUM_CONST(0x00000001)                                                       // RW--V
#define AHCI_HBA_CAP_BKDR_0_SUPP_STG_SPUP_CLEAR            _MK_ENUM_CONST(0x00000000)                                                       // RWC-V
#define AHCI_HBA_CAP_BKDR_0_SMPS_SHIFT                      _MK_SHIFT_CONST(28)                                                             // RWCVF
#define AHCI_HBA_CAP_BKDR_0_SMPS_FIELD                     (_MK_SHIFT_CONST(0x1) << AHCI_HBA_CAP_BKDR_0_SMPS_SHIFT)
#define AHCI_HBA_CAP_BKDR_0_SMPS_RANGE                     28:28
#define AHCI_HBA_CAP_BKDR_0_SMPS_WOFFSET                   0
#define AHCI_HBA_CAP_BKDR_0_SMPS_TRUE                      _MK_ENUM_CONST(0x00000001)                                                       // RW--V
#define AHCI_HBA_CAP_BKDR_0_SMPS_FALSE                     _MK_ENUM_CONST(0x00000000)                                                       // RWC-V
#define AHCI_HBA_CAP_BKDR_0_SSNTF_SHIFT                     _MK_SHIFT_CONST(29)                                                             // RWCVF
#define AHCI_HBA_CAP_BKDR_0_SSNTF_FIELD                    (_MK_SHIFT_CONST(0x1) << AHCI_HBA_CAP_BKDR_0_SSNTF_SHIFT)
#define AHCI_HBA_CAP_BKDR_0_SSNTF_RANGE                    29:29
#define AHCI_HBA_CAP_BKDR_0_SSNTF_WOFFSET                  0
#define AHCI_HBA_CAP_BKDR_0_SSNTF_TRUE                     _MK_ENUM_CONST(0x00000001)                                                       // RWC-V
#define AHCI_HBA_CAP_BKDR_0_SSNTF_FALSE                    _MK_ENUM_CONST(0x00000000)                                                       // RW--V
#define AHCI_HBA_CAP_BKDR_0_SNCQ_SHIFT                      _MK_SHIFT_CONST(30)                                                             // RWCVF
#define AHCI_HBA_CAP_BKDR_0_SNCQ_FIELD                     (_MK_SHIFT_CONST(0x1) << AHCI_HBA_CAP_BKDR_0_SNCQ_SHIFT)
#define AHCI_HBA_CAP_BKDR_0_SNCQ_RANGE                     30:30
#define AHCI_HBA_CAP_BKDR_0_SNCQ_WOFFSET                   0
#define AHCI_HBA_CAP_BKDR_0_SNCQ_TRUE                      _MK_ENUM_CONST(0x00000001)                                                       // RWC-V
#define AHCI_HBA_CAP_BKDR_0_SNCQ_FALSE                     _MK_ENUM_CONST(0x00000000)                                                       // RW--V
#define AHCI_HBA_CAP_BKDR_0_S64A_SHIFT                      _MK_SHIFT_CONST(31)                                                             // RWCVF
#define AHCI_HBA_CAP_BKDR_0_S64A_FIELD                     (_MK_SHIFT_CONST(0x1) << AHCI_HBA_CAP_BKDR_0_S64A_SHIFT)
#define AHCI_HBA_CAP_BKDR_0_S64A_RANGE                     31:31
#define AHCI_HBA_CAP_BKDR_0_S64A_WOFFSET                   0
#define AHCI_HBA_CAP_BKDR_0_S64A_TRUE                      _MK_ENUM_CONST(0x00000001)                                                       // RWC-V
#define AHCI_HBA_CAP_BKDR_0_S64A_FALSE                     _MK_ENUM_CONST(0x00000000)                                                       // RW--V
// .LABEL PRIVATE
// 
// .LABEL PUBLIC
// .LABEL PRIVATE INT_REL
// .LABEL PUBLIC
// .LABEL PRIVATE
// .LABEL PRIVATE INT_REL
// 
// .LABEL PUBLIC
// 
// .LABEL PRIVATE
// // else of ifdef SATA_FPCI_ONLY
// .LABEL PRIVATE INT_REL
// .TITLE HBA_SPARE_0
// spare register with cold reset
// 
// 31           24 23           16 15            8 7             0
// .-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-.
// |0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0| SPARE Reg 0
// `-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-'
// 
#define AHCI_HBA_SPARE_0_0                                 0x000000A4                                                                       // RW-4R
#define AHCI_HBA_SPARE_0_0_SECURE                          0
#define AHCI_HBA_SPARE_0_0_WORD_COUNT                      1
#define AHCI_HBA_SPARE_0_0_RESET_VAL                       0x0
#define AHCI_HBA_SPARE_0_0_RESET_MASK                      0x0
#define AHCI_HBA_SPARE_0_0_SW_DEFAULT_VAL                  0x0
#define AHCI_HBA_SPARE_0_0_SW_DEFAULT_MASK                 0x0
#define AHCI_HBA_SPARE_0_0_READ_MASK                       0xffffffff
#define AHCI_HBA_SPARE_0_0_WRITE_MASK                      0xffffffff
#define AHCI_HBA_SPARE_0_0_RSVD_SHIFT                       _MK_SHIFT_CONST(0)                                                              // RWC-F
#define AHCI_HBA_SPARE_0_0_RSVD_FIELD                      (_MK_SHIFT_CONST(0xffffffff) << AHCI_HBA_SPARE_0_0_RSVD_SHIFT)
#define AHCI_HBA_SPARE_0_0_RSVD_RANGE                      31:0
#define AHCI_HBA_SPARE_0_0_RSVD_WOFFSET                    0
#define AHCI_HBA_SPARE_0_0_RSVD_INIT                       _MK_ENUM_CONST(0xF0F0F0F0)                                                       // RWC-V
// 
// .LABEL PRIVATE
// //} end of else of SATA_FPCI_WRAPPER
// .LABEL PUBLIC
// 
// .LABEL PRIVATE INT_REL
// .TITLE AHCI_HBA_PLL_CTRL
// .LABEL PRIVATE
// SW_INIT needed for this register to enable PLL shutdown/ clock clamping
// .LABEL PRIVATE INT_REL
// .FIELD HBA_PLL_CTRL_DEVCLK_SHUTDOWN
// sets a signal to clocks block to shutdown the DEVCLK PLL
// 
// .FIELD HBA_PLL_CTRL_TXRXCLK_SHUTDOWN
// sets a signal to clocks block to shutdown the TXRXCLK PLL
// 
// .FIELD HBA_PLL_CTRL_TXRXCLK_WAKEUP
// deasserts the above signal to wakeup the TXRXCLK PLL
// 
// .FIELD NO_CLAMP_SHUTDOWN
//     when this bit is set the clamping of clocks(all clocks) and shutdown of PLL is disabled
// It should be written to zero if CLAMP/SHUTDOWN needs to be enabled
// 
// .FIELD CLAMP_TXCLK_ON_PARTIAL
//     this bit set indicates that txclk and rxclk clamping is enabled when PHY is in PARTIAL
// 
// .FIELD CLAMP_TXCLK_ON_SLUMBER
//     this bit set indicates that txclk and rxclk clamping is enabled when PHY is in SLUMBER
// and the SHUTDOWN signal would not be asserted
// 
// .FIELD SHUTDOWN_TXCLK_ON_SLUMBER
//     When the above bit is zero and this bit is one the SHUTDOWN signal would be asserted
// when all the ports are in SLUMBER
// 
// .FIELD CLAMP_TXCLK_ON_PHYRDY_LOW
//     this bit set indicates txclk and rxclk clamping is enabled when PHY_RDY goes low
// 
// .FIELD SHUTDOWN_TXCLK_ON_PHYRDY_LOW
//     when this bit is one and all ports PHY_RDY goes low, shutdown signal will be asserted
// 
// Similar is the case for the DEVCLK clamp and shutdown bits
// 
// 31           24 23           16 15            8 7             0
// .-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-.
// |0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0| AHCI_HBA_PLL_CTRL
// `-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-'
// 
#define AHCI_HBA_PLL_CTRL_0                                0x000000A8                                                                       // RW-4R
#define AHCI_HBA_PLL_CTRL_0_SECURE                         0
#define AHCI_HBA_PLL_CTRL_0_WORD_COUNT                     1
#define AHCI_HBA_PLL_CTRL_0_RESET_VAL                      0x0
#define AHCI_HBA_PLL_CTRL_0_RESET_MASK                     0x7
#define AHCI_HBA_PLL_CTRL_0_SW_DEFAULT_VAL                 0x0
#define AHCI_HBA_PLL_CTRL_0_SW_DEFAULT_MASK                0x7
#define AHCI_HBA_PLL_CTRL_0_READ_MASK                      0x1ffffff
#define AHCI_HBA_PLL_CTRL_0_WRITE_MASK                     0x1ffffff
#define AHCI_HBA_PLL_CTRL_0_DEVCLK_SHUTDOWN_SHIFT           _MK_SHIFT_CONST(0)                                                              // RWI-F
#define AHCI_HBA_PLL_CTRL_0_DEVCLK_SHUTDOWN_FIELD          (_MK_SHIFT_CONST(0x1) << AHCI_HBA_PLL_CTRL_0_DEVCLK_SHUTDOWN_SHIFT)
#define AHCI_HBA_PLL_CTRL_0_DEVCLK_SHUTDOWN_RANGE          0:0
#define AHCI_HBA_PLL_CTRL_0_DEVCLK_SHUTDOWN_WOFFSET        0
#define AHCI_HBA_PLL_CTRL_0_DEVCLK_SHUTDOWN_DEFAULT        (_MK_MASK_CONST(0x00000000)
#define AHCI_HBA_PLL_CTRL_0_DEVCLK_SHUTDOWN_DEFAULT_MASK   (_MK_MASK_CONST(0x1)
#define AHCI_HBA_PLL_CTRL_0_DEVCLK_SHUTDOWN_SW_DEFAULT     (_MK_MASK_CONST(0x00000000)
#define AHCI_HBA_PLL_CTRL_0_DEVCLK_SHUTDOWN_SW_DEFAULT_MASK (_MK_MASK_CONST(0x1)
#define AHCI_HBA_PLL_CTRL_0_DEVCLK_SHUTDOWN_NO             _MK_ENUM_CONST(0x00000000)                                                       // RWI-V
#define AHCI_HBA_PLL_CTRL_0_DEVCLK_SHUTDOWN_YES            _MK_ENUM_CONST(0x00000001)                                                       // RW--V
#define AHCI_HBA_PLL_CTRL_0_DEVCLK_SHUTDOWN_SET            _MK_ENUM_CONST(0x00000001)                                                       // -W--T
#define AHCI_HBA_PLL_CTRL_0_TXRXCLK_SHUTDOWN_SHIFT          _MK_SHIFT_CONST(1)                                                              // RWI-F
#define AHCI_HBA_PLL_CTRL_0_TXRXCLK_SHUTDOWN_FIELD         (_MK_SHIFT_CONST(0x1) << AHCI_HBA_PLL_CTRL_0_TXRXCLK_SHUTDOWN_SHIFT)
#define AHCI_HBA_PLL_CTRL_0_TXRXCLK_SHUTDOWN_RANGE         1:1
#define AHCI_HBA_PLL_CTRL_0_TXRXCLK_SHUTDOWN_WOFFSET       0
#define AHCI_HBA_PLL_CTRL_0_TXRXCLK_SHUTDOWN_DEFAULT       (_MK_MASK_CONST(0x00000000)
#define AHCI_HBA_PLL_CTRL_0_TXRXCLK_SHUTDOWN_DEFAULT_MASK  (_MK_MASK_CONST(0x1)
#define AHCI_HBA_PLL_CTRL_0_TXRXCLK_SHUTDOWN_SW_DEFAULT    (_MK_MASK_CONST(0x00000000)
#define AHCI_HBA_PLL_CTRL_0_TXRXCLK_SHUTDOWN_SW_DEFAULT_MASK (_MK_MASK_CONST(0x1)
#define AHCI_HBA_PLL_CTRL_0_TXRXCLK_SHUTDOWN_NO            _MK_ENUM_CONST(0x00000000)                                                       // RWI-V
#define AHCI_HBA_PLL_CTRL_0_TXRXCLK_SHUTDOWN_YES           _MK_ENUM_CONST(0x00000001)                                                       // RW--V
#define AHCI_HBA_PLL_CTRL_0_TXRXCLK_SHUTDOWN_SET           _MK_ENUM_CONST(0x00000001)                                                       // -W--T
#define AHCI_HBA_PLL_CTRL_0_TXRXCLK_WAKEUP_SHIFT            _MK_SHIFT_CONST(2)                                                              // RWI-F
#define AHCI_HBA_PLL_CTRL_0_TXRXCLK_WAKEUP_FIELD           (_MK_SHIFT_CONST(0x1) << AHCI_HBA_PLL_CTRL_0_TXRXCLK_WAKEUP_SHIFT)
#define AHCI_HBA_PLL_CTRL_0_TXRXCLK_WAKEUP_RANGE           2:2
#define AHCI_HBA_PLL_CTRL_0_TXRXCLK_WAKEUP_WOFFSET         0
#define AHCI_HBA_PLL_CTRL_0_TXRXCLK_WAKEUP_DEFAULT         (_MK_MASK_CONST(0x00000000)
#define AHCI_HBA_PLL_CTRL_0_TXRXCLK_WAKEUP_DEFAULT_MASK    (_MK_MASK_CONST(0x1)
#define AHCI_HBA_PLL_CTRL_0_TXRXCLK_WAKEUP_SW_DEFAULT      (_MK_MASK_CONST(0x00000000)
#define AHCI_HBA_PLL_CTRL_0_TXRXCLK_WAKEUP_SW_DEFAULT_MASK (_MK_MASK_CONST(0x1)
#define AHCI_HBA_PLL_CTRL_0_TXRXCLK_WAKEUP_NO              _MK_ENUM_CONST(0x00000000)                                                       // RWI-V
#define AHCI_HBA_PLL_CTRL_0_TXRXCLK_WAKEUP_YES             _MK_ENUM_CONST(0x00000001)                                                       // RW--V
#define AHCI_HBA_PLL_CTRL_0_TXRXCLK_WAKEUP_SET             _MK_ENUM_CONST(0x00000001)                                                       // -W--T
#define AHCI_HBA_PLL_CTRL_0_NO_CLAMP_SHUTDOWN_SHIFT         _MK_SHIFT_CONST(3)                                                              // RWC-F
#define AHCI_HBA_PLL_CTRL_0_NO_CLAMP_SHUTDOWN_FIELD        (_MK_SHIFT_CONST(0x1) << AHCI_HBA_PLL_CTRL_0_NO_CLAMP_SHUTDOWN_SHIFT)
#define AHCI_HBA_PLL_CTRL_0_NO_CLAMP_SHUTDOWN_RANGE        3:3
#define AHCI_HBA_PLL_CTRL_0_NO_CLAMP_SHUTDOWN_WOFFSET      0
#define AHCI_HBA_PLL_CTRL_0_NO_CLAMP_SHUTDOWN_YES          _MK_ENUM_CONST(0x00000001)                                                       // RWC-V
#define AHCI_HBA_PLL_CTRL_0_NO_CLAMP_SHUTDOWN_NO           _MK_ENUM_CONST(0x00000000)                                                       // RW--V
#define AHCI_HBA_PLL_CTRL_0_SHUTDOWN_DEVCLK_ON_SLUMBER_SHIFT  _MK_SHIFT_CONST(4)                                                              // RWC-F
#define AHCI_HBA_PLL_CTRL_0_SHUTDOWN_DEVCLK_ON_SLUMBER_FIELD (_MK_SHIFT_CONST(0x1) << AHCI_HBA_PLL_CTRL_0_SHUTDOWN_DEVCLK_ON_SLUMBER_SHIFT)
#define AHCI_HBA_PLL_CTRL_0_SHUTDOWN_DEVCLK_ON_SLUMBER_RANGE 4:4
#define AHCI_HBA_PLL_CTRL_0_SHUTDOWN_DEVCLK_ON_SLUMBER_WOFFSET 0
#define AHCI_HBA_PLL_CTRL_0_SHUTDOWN_DEVCLK_ON_SLUMBER_YES _MK_ENUM_CONST(0x00000001)                                                       // RW--V
#define AHCI_HBA_PLL_CTRL_0_SHUTDOWN_DEVCLK_ON_SLUMBER_NO  _MK_ENUM_CONST(0x00000000)                                                       // RWC-V
#define AHCI_HBA_PLL_CTRL_0_SHUTDOWN_DEVCLK_ON_PHYRDY_LOW_SHIFT  _MK_SHIFT_CONST(5)                                                              // RWC-F
#define AHCI_HBA_PLL_CTRL_0_SHUTDOWN_DEVCLK_ON_PHYRDY_LOW_FIELD (_MK_SHIFT_CONST(0x1) << AHCI_HBA_PLL_CTRL_0_SHUTDOWN_DEVCLK_ON_PHYRDY_LOW_SHIFT)
#define AHCI_HBA_PLL_CTRL_0_SHUTDOWN_DEVCLK_ON_PHYRDY_LOW_RANGE 5:5
#define AHCI_HBA_PLL_CTRL_0_SHUTDOWN_DEVCLK_ON_PHYRDY_LOW_WOFFSET 0
#define AHCI_HBA_PLL_CTRL_0_SHUTDOWN_DEVCLK_ON_PHYRDY_LOW_YES _MK_ENUM_CONST(0x00000001)                                                       // RW--V
#define AHCI_HBA_PLL_CTRL_0_SHUTDOWN_DEVCLK_ON_PHYRDY_LOW_NO _MK_ENUM_CONST(0x00000000)                                                       // RWC-V
#define AHCI_HBA_PLL_CTRL_0_SHUTDOWN_TXCLK_ON_SLUMBER_SHIFT  _MK_SHIFT_CONST(6)                                                              // RWC-F
#define AHCI_HBA_PLL_CTRL_0_SHUTDOWN_TXCLK_ON_SLUMBER_FIELD (_MK_SHIFT_CONST(0x1) << AHCI_HBA_PLL_CTRL_0_SHUTDOWN_TXCLK_ON_SLUMBER_SHIFT)
#define AHCI_HBA_PLL_CTRL_0_SHUTDOWN_TXCLK_ON_SLUMBER_RANGE 6:6
#define AHCI_HBA_PLL_CTRL_0_SHUTDOWN_TXCLK_ON_SLUMBER_WOFFSET 0
#define AHCI_HBA_PLL_CTRL_0_SHUTDOWN_TXCLK_ON_SLUMBER_YES  _MK_ENUM_CONST(0x00000001)                                                       // RW--V
#define AHCI_HBA_PLL_CTRL_0_SHUTDOWN_TXCLK_ON_SLUMBER_NO   _MK_ENUM_CONST(0x00000000)                                                       // RWC-V
#define AHCI_HBA_PLL_CTRL_0_SHUTDOWN_TXCLK_ON_PHYRDY_LOW_SHIFT  _MK_SHIFT_CONST(7)                                                              // RWC-F
#define AHCI_HBA_PLL_CTRL_0_SHUTDOWN_TXCLK_ON_PHYRDY_LOW_FIELD (_MK_SHIFT_CONST(0x1) << AHCI_HBA_PLL_CTRL_0_SHUTDOWN_TXCLK_ON_PHYRDY_LOW_SHIFT)
#define AHCI_HBA_PLL_CTRL_0_SHUTDOWN_TXCLK_ON_PHYRDY_LOW_RANGE 7:7
#define AHCI_HBA_PLL_CTRL_0_SHUTDOWN_TXCLK_ON_PHYRDY_LOW_WOFFSET 0
#define AHCI_HBA_PLL_CTRL_0_SHUTDOWN_TXCLK_ON_PHYRDY_LOW_YES _MK_ENUM_CONST(0x00000001)                                                       // RW--V
#define AHCI_HBA_PLL_CTRL_0_SHUTDOWN_TXCLK_ON_PHYRDY_LOW_NO _MK_ENUM_CONST(0x00000000)                                                       // RWC-V
#define AHCI_HBA_PLL_CTRL_0_CLAMP_DEVCLK_ON_PARTIAL_SHIFT   _MK_SHIFT_CONST(8)                                                              // RWC-F
#define AHCI_HBA_PLL_CTRL_0_CLAMP_DEVCLK_ON_PARTIAL_FIELD  (_MK_SHIFT_CONST(0x1) << AHCI_HBA_PLL_CTRL_0_CLAMP_DEVCLK_ON_PARTIAL_SHIFT)
#define AHCI_HBA_PLL_CTRL_0_CLAMP_DEVCLK_ON_PARTIAL_RANGE  8:8
#define AHCI_HBA_PLL_CTRL_0_CLAMP_DEVCLK_ON_PARTIAL_WOFFSET 0
#define AHCI_HBA_PLL_CTRL_0_CLAMP_DEVCLK_ON_PARTIAL_YES    _MK_ENUM_CONST(0x00000001)                                                       // RW--V
#define AHCI_HBA_PLL_CTRL_0_CLAMP_DEVCLK_ON_PARTIAL_NO     _MK_ENUM_CONST(0x00000000)                                                       // RWC-V
#define AHCI_HBA_PLL_CTRL_0_CLAMP_DEVCLK_ON_PHYRDY_LOW_SHIFT  _MK_SHIFT_CONST(9)                                                              // RWC-F
#define AHCI_HBA_PLL_CTRL_0_CLAMP_DEVCLK_ON_PHYRDY_LOW_FIELD (_MK_SHIFT_CONST(0x1) << AHCI_HBA_PLL_CTRL_0_CLAMP_DEVCLK_ON_PHYRDY_LOW_SHIFT)
#define AHCI_HBA_PLL_CTRL_0_CLAMP_DEVCLK_ON_PHYRDY_LOW_RANGE 9:9
#define AHCI_HBA_PLL_CTRL_0_CLAMP_DEVCLK_ON_PHYRDY_LOW_WOFFSET 0
#define AHCI_HBA_PLL_CTRL_0_CLAMP_DEVCLK_ON_PHYRDY_LOW_YES _MK_ENUM_CONST(0x00000001)                                                       // RW--V
#define AHCI_HBA_PLL_CTRL_0_CLAMP_DEVCLK_ON_PHYRDY_LOW_NO  _MK_ENUM_CONST(0x00000000)                                                       // RWC-V
#define AHCI_HBA_PLL_CTRL_0_CLAMP_DEVCLK_ON_SLUMBER_SHIFT   _MK_SHIFT_CONST(10)                                                             // RWC-F
#define AHCI_HBA_PLL_CTRL_0_CLAMP_DEVCLK_ON_SLUMBER_FIELD  (_MK_SHIFT_CONST(0x1) << AHCI_HBA_PLL_CTRL_0_CLAMP_DEVCLK_ON_SLUMBER_SHIFT)
#define AHCI_HBA_PLL_CTRL_0_CLAMP_DEVCLK_ON_SLUMBER_RANGE  10:10
#define AHCI_HBA_PLL_CTRL_0_CLAMP_DEVCLK_ON_SLUMBER_WOFFSET 0
#define AHCI_HBA_PLL_CTRL_0_CLAMP_DEVCLK_ON_SLUMBER_YES    _MK_ENUM_CONST(0x00000001)                                                       // RW--V
#define AHCI_HBA_PLL_CTRL_0_CLAMP_DEVCLK_ON_SLUMBER_NO     _MK_ENUM_CONST(0x00000000)                                                       // RWC-V
#define AHCI_HBA_PLL_CTRL_0_CLAMP_TXCLK_ON_PARTIAL_SHIFT    _MK_SHIFT_CONST(11)                                                             // RWC-F
#define AHCI_HBA_PLL_CTRL_0_CLAMP_TXCLK_ON_PARTIAL_FIELD   (_MK_SHIFT_CONST(0x1) << AHCI_HBA_PLL_CTRL_0_CLAMP_TXCLK_ON_PARTIAL_SHIFT)
#define AHCI_HBA_PLL_CTRL_0_CLAMP_TXCLK_ON_PARTIAL_RANGE   11:11
#define AHCI_HBA_PLL_CTRL_0_CLAMP_TXCLK_ON_PARTIAL_WOFFSET 0
#define AHCI_HBA_PLL_CTRL_0_CLAMP_TXCLK_ON_PARTIAL_YES     _MK_ENUM_CONST(0x00000001)                                                       // RW--V
#define AHCI_HBA_PLL_CTRL_0_CLAMP_TXCLK_ON_PARTIAL_NO      _MK_ENUM_CONST(0x00000000)                                                       // RWC-V
#define AHCI_HBA_PLL_CTRL_0_CLAMP_TXCLK_ON_PHYRDY_LOW_SHIFT  _MK_SHIFT_CONST(12)                                                             // RWC-F
#define AHCI_HBA_PLL_CTRL_0_CLAMP_TXCLK_ON_PHYRDY_LOW_FIELD (_MK_SHIFT_CONST(0x1) << AHCI_HBA_PLL_CTRL_0_CLAMP_TXCLK_ON_PHYRDY_LOW_SHIFT)
#define AHCI_HBA_PLL_CTRL_0_CLAMP_TXCLK_ON_PHYRDY_LOW_RANGE 12:12
#define AHCI_HBA_PLL_CTRL_0_CLAMP_TXCLK_ON_PHYRDY_LOW_WOFFSET 0
#define AHCI_HBA_PLL_CTRL_0_CLAMP_TXCLK_ON_PHYRDY_LOW_YES  _MK_ENUM_CONST(0x00000001)                                                       // RW--V
#define AHCI_HBA_PLL_CTRL_0_CLAMP_TXCLK_ON_PHYRDY_LOW_NO   _MK_ENUM_CONST(0x00000000)                                                       // RWC-V
#define AHCI_HBA_PLL_CTRL_0_CLAMP_TXCLK_ON_SLUMBER_SHIFT    _MK_SHIFT_CONST(13)                                                             // RWC-F
#define AHCI_HBA_PLL_CTRL_0_CLAMP_TXCLK_ON_SLUMBER_FIELD   (_MK_SHIFT_CONST(0x1) << AHCI_HBA_PLL_CTRL_0_CLAMP_TXCLK_ON_SLUMBER_SHIFT)
#define AHCI_HBA_PLL_CTRL_0_CLAMP_TXCLK_ON_SLUMBER_RANGE   13:13
#define AHCI_HBA_PLL_CTRL_0_CLAMP_TXCLK_ON_SLUMBER_WOFFSET 0
#define AHCI_HBA_PLL_CTRL_0_CLAMP_TXCLK_ON_SLUMBER_YES     _MK_ENUM_CONST(0x00000001)                                                       // RW--V
#define AHCI_HBA_PLL_CTRL_0_CLAMP_TXCLK_ON_SLUMBER_NO      _MK_ENUM_CONST(0x00000000)                                                       // RWC-V
#define AHCI_HBA_PLL_CTRL_0_WAKEUP_ONLY_THRU_SW_SHIFT       _MK_SHIFT_CONST(14)                                                             // RWC-F
#define AHCI_HBA_PLL_CTRL_0_WAKEUP_ONLY_THRU_SW_FIELD      (_MK_SHIFT_CONST(0x1) << AHCI_HBA_PLL_CTRL_0_WAKEUP_ONLY_THRU_SW_SHIFT)
#define AHCI_HBA_PLL_CTRL_0_WAKEUP_ONLY_THRU_SW_RANGE      14:14
#define AHCI_HBA_PLL_CTRL_0_WAKEUP_ONLY_THRU_SW_WOFFSET    0
#define AHCI_HBA_PLL_CTRL_0_WAKEUP_ONLY_THRU_SW_YES        _MK_ENUM_CONST(0x00000001)                                                       // RW--V
#define AHCI_HBA_PLL_CTRL_0_WAKEUP_ONLY_THRU_SW_NO         _MK_ENUM_CONST(0x00000000)                                                       // RWC-V
#define AHCI_HBA_PLL_CTRL_0_UNCLAMP_TXRXCLK_ONLY_THRU_SW_SHIFT  _MK_SHIFT_CONST(15)                                                             // RWC-F
#define AHCI_HBA_PLL_CTRL_0_UNCLAMP_TXRXCLK_ONLY_THRU_SW_FIELD (_MK_SHIFT_CONST(0x1) << AHCI_HBA_PLL_CTRL_0_UNCLAMP_TXRXCLK_ONLY_THRU_SW_SHIFT)
#define AHCI_HBA_PLL_CTRL_0_UNCLAMP_TXRXCLK_ONLY_THRU_SW_RANGE 15:15
#define AHCI_HBA_PLL_CTRL_0_UNCLAMP_TXRXCLK_ONLY_THRU_SW_WOFFSET 0
#define AHCI_HBA_PLL_CTRL_0_UNCLAMP_TXRXCLK_ONLY_THRU_SW_YES _MK_ENUM_CONST(0x00000001)                                                       // RW--V
#define AHCI_HBA_PLL_CTRL_0_UNCLAMP_TXRXCLK_ONLY_THRU_SW_NO _MK_ENUM_CONST(0x00000000)                                                       // RWC-V
#define AHCI_HBA_PLL_CTRL_0_UNCLAMP_DEVCLK_ONLY_THRU_SW_SHIFT  _MK_SHIFT_CONST(16)                                                             // RWC-F
#define AHCI_HBA_PLL_CTRL_0_UNCLAMP_DEVCLK_ONLY_THRU_SW_FIELD (_MK_SHIFT_CONST(0x1) << AHCI_HBA_PLL_CTRL_0_UNCLAMP_DEVCLK_ONLY_THRU_SW_SHIFT)
#define AHCI_HBA_PLL_CTRL_0_UNCLAMP_DEVCLK_ONLY_THRU_SW_RANGE 16:16
#define AHCI_HBA_PLL_CTRL_0_UNCLAMP_DEVCLK_ONLY_THRU_SW_WOFFSET 0
#define AHCI_HBA_PLL_CTRL_0_UNCLAMP_DEVCLK_ONLY_THRU_SW_YES _MK_ENUM_CONST(0x00000001)                                                       // RW--V
#define AHCI_HBA_PLL_CTRL_0_UNCLAMP_DEVCLK_ONLY_THRU_SW_NO _MK_ENUM_CONST(0x00000000)                                                       // RWC-V
#define AHCI_HBA_PLL_CTRL_0_CLAMP_TXRXCLK_IN_AWAIT_COMINIT_SHIFT  _MK_SHIFT_CONST(17)                                                             // RWC-F
#define AHCI_HBA_PLL_CTRL_0_CLAMP_TXRXCLK_IN_AWAIT_COMINIT_FIELD (_MK_SHIFT_CONST(0x1) << AHCI_HBA_PLL_CTRL_0_CLAMP_TXRXCLK_IN_AWAIT_COMINIT_SHIFT)
#define AHCI_HBA_PLL_CTRL_0_CLAMP_TXRXCLK_IN_AWAIT_COMINIT_RANGE 17:17
#define AHCI_HBA_PLL_CTRL_0_CLAMP_TXRXCLK_IN_AWAIT_COMINIT_WOFFSET 0
#define AHCI_HBA_PLL_CTRL_0_CLAMP_TXRXCLK_IN_AWAIT_COMINIT_YES _MK_ENUM_CONST(0x00000001)                                                       // RW--V
#define AHCI_HBA_PLL_CTRL_0_CLAMP_TXRXCLK_IN_AWAIT_COMINIT_NO _MK_ENUM_CONST(0x00000000)                                                       // RWC-V
#define AHCI_HBA_PLL_CTRL_0_CLAMP_DEVCLK_IN_AWAIT_COMINIT_SHIFT  _MK_SHIFT_CONST(18)                                                             // RWC-F
#define AHCI_HBA_PLL_CTRL_0_CLAMP_DEVCLK_IN_AWAIT_COMINIT_FIELD (_MK_SHIFT_CONST(0x1) << AHCI_HBA_PLL_CTRL_0_CLAMP_DEVCLK_IN_AWAIT_COMINIT_SHIFT)
#define AHCI_HBA_PLL_CTRL_0_CLAMP_DEVCLK_IN_AWAIT_COMINIT_RANGE 18:18
#define AHCI_HBA_PLL_CTRL_0_CLAMP_DEVCLK_IN_AWAIT_COMINIT_WOFFSET 0
#define AHCI_HBA_PLL_CTRL_0_CLAMP_DEVCLK_IN_AWAIT_COMINIT_YES _MK_ENUM_CONST(0x00000001)                                                       // RW--V
#define AHCI_HBA_PLL_CTRL_0_CLAMP_DEVCLK_IN_AWAIT_COMINIT_NO _MK_ENUM_CONST(0x00000000)                                                       // RWC-V
#define AHCI_HBA_PLL_CTRL_0_DIS_DEVCLK_CLAMPING_SHIFT       _MK_SHIFT_CONST(19)                                                             // RWC-F
#define AHCI_HBA_PLL_CTRL_0_DIS_DEVCLK_CLAMPING_FIELD      (_MK_SHIFT_CONST(0x1) << AHCI_HBA_PLL_CTRL_0_DIS_DEVCLK_CLAMPING_SHIFT)
#define AHCI_HBA_PLL_CTRL_0_DIS_DEVCLK_CLAMPING_RANGE      19:19
#define AHCI_HBA_PLL_CTRL_0_DIS_DEVCLK_CLAMPING_WOFFSET    0
#define AHCI_HBA_PLL_CTRL_0_DIS_DEVCLK_CLAMPING_YES        _MK_ENUM_CONST(0x00000001)                                                       // RW--V
#define AHCI_HBA_PLL_CTRL_0_DIS_DEVCLK_CLAMPING_NO         _MK_ENUM_CONST(0x00000000)                                                       // RWC-V
#define AHCI_HBA_PLL_CTRL_0_DIS_TXRXCLK_CLAMPING_SHIFT      _MK_SHIFT_CONST(20)                                                             // RWC-F
#define AHCI_HBA_PLL_CTRL_0_DIS_TXRXCLK_CLAMPING_FIELD     (_MK_SHIFT_CONST(0x1) << AHCI_HBA_PLL_CTRL_0_DIS_TXRXCLK_CLAMPING_SHIFT)
#define AHCI_HBA_PLL_CTRL_0_DIS_TXRXCLK_CLAMPING_RANGE     20:20
#define AHCI_HBA_PLL_CTRL_0_DIS_TXRXCLK_CLAMPING_WOFFSET   0
#define AHCI_HBA_PLL_CTRL_0_DIS_TXRXCLK_CLAMPING_YES       _MK_ENUM_CONST(0x00000001)                                                       // RW--V
#define AHCI_HBA_PLL_CTRL_0_DIS_TXRXCLK_CLAMPING_NO        _MK_ENUM_CONST(0x00000000)                                                       // RWC-V
#define AHCI_HBA_PLL_CTRL_0_DIS_TXRXCLK_SHUTDOWN_SHIFT      _MK_SHIFT_CONST(21)                                                             // RWC-F
#define AHCI_HBA_PLL_CTRL_0_DIS_TXRXCLK_SHUTDOWN_FIELD     (_MK_SHIFT_CONST(0x1) << AHCI_HBA_PLL_CTRL_0_DIS_TXRXCLK_SHUTDOWN_SHIFT)
#define AHCI_HBA_PLL_CTRL_0_DIS_TXRXCLK_SHUTDOWN_RANGE     21:21
#define AHCI_HBA_PLL_CTRL_0_DIS_TXRXCLK_SHUTDOWN_WOFFSET   0
#define AHCI_HBA_PLL_CTRL_0_DIS_TXRXCLK_SHUTDOWN_YES       _MK_ENUM_CONST(0x00000001)                                                       // RW--V
#define AHCI_HBA_PLL_CTRL_0_DIS_TXRXCLK_SHUTDOWN_NO        _MK_ENUM_CONST(0x00000000)                                                       // RWC-V
#define AHCI_HBA_PLL_CTRL_0_SHUTDOWN_TXCLK_ON_DEVSLP_SHIFT  _MK_SHIFT_CONST(22)                                                             // RWC-F
#define AHCI_HBA_PLL_CTRL_0_SHUTDOWN_TXCLK_ON_DEVSLP_FIELD (_MK_SHIFT_CONST(0x1) << AHCI_HBA_PLL_CTRL_0_SHUTDOWN_TXCLK_ON_DEVSLP_SHIFT)
#define AHCI_HBA_PLL_CTRL_0_SHUTDOWN_TXCLK_ON_DEVSLP_RANGE 22:22
#define AHCI_HBA_PLL_CTRL_0_SHUTDOWN_TXCLK_ON_DEVSLP_WOFFSET 0
#define AHCI_HBA_PLL_CTRL_0_SHUTDOWN_TXCLK_ON_DEVSLP_YES   _MK_ENUM_CONST(0x00000001)                                                       // RW--V
#define AHCI_HBA_PLL_CTRL_0_SHUTDOWN_TXCLK_ON_DEVSLP_NO    _MK_ENUM_CONST(0x00000000)                                                       // RWC-V
#define AHCI_HBA_PLL_CTRL_0_CLAMP_DEVCLK_ON_DEVSLP_SHIFT    _MK_SHIFT_CONST(23)                                                             // RWC-F
#define AHCI_HBA_PLL_CTRL_0_CLAMP_DEVCLK_ON_DEVSLP_FIELD   (_MK_SHIFT_CONST(0x1) << AHCI_HBA_PLL_CTRL_0_CLAMP_DEVCLK_ON_DEVSLP_SHIFT)
#define AHCI_HBA_PLL_CTRL_0_CLAMP_DEVCLK_ON_DEVSLP_RANGE   23:23
#define AHCI_HBA_PLL_CTRL_0_CLAMP_DEVCLK_ON_DEVSLP_WOFFSET 0
#define AHCI_HBA_PLL_CTRL_0_CLAMP_DEVCLK_ON_DEVSLP_YES     _MK_ENUM_CONST(0x00000001)                                                       // RW--V
#define AHCI_HBA_PLL_CTRL_0_CLAMP_DEVCLK_ON_DEVSLP_NO      _MK_ENUM_CONST(0x00000000)                                                       // RWC-V
#define AHCI_HBA_PLL_CTRL_0_CLAMP_TXCLK_ON_DEVSLP_SHIFT     _MK_SHIFT_CONST(24)                                                             // RWC-F
#define AHCI_HBA_PLL_CTRL_0_CLAMP_TXCLK_ON_DEVSLP_FIELD    (_MK_SHIFT_CONST(0x1) << AHCI_HBA_PLL_CTRL_0_CLAMP_TXCLK_ON_DEVSLP_SHIFT)
#define AHCI_HBA_PLL_CTRL_0_CLAMP_TXCLK_ON_DEVSLP_RANGE    24:24
#define AHCI_HBA_PLL_CTRL_0_CLAMP_TXCLK_ON_DEVSLP_WOFFSET  0
#define AHCI_HBA_PLL_CTRL_0_CLAMP_TXCLK_ON_DEVSLP_YES      _MK_ENUM_CONST(0x00000001)                                                       // RW--V
#define AHCI_HBA_PLL_CTRL_0_CLAMP_TXCLK_ON_DEVSLP_NO       _MK_ENUM_CONST(0x00000000)                                                       // RWC-V
// 
// 
// 
// 
// 
// 
// 
// 
// 
// 
// 
// 
// 
// 
// 
// 
// 
// 
// 
// 
// 
// 
// 
// 
// 
//  .LABEL PUBLIC
// 
// .LABEL PRIVATE INT_REL
// .TITLE AHCI_HBA_SHUTDOWN_TIMER
// 
// .FIELD TXRX_CLK
// specifies how many 100us we wait before shutting down the PLL
// 31           24 23           16 15            8 7             0
// .-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-.
// |0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0| AHCI_HBA_SHUTDOWN_TIMER
// `-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-'
// 
#define AHCI_HBA_SHUTDOWN_TIMER_0                          0x000000AC                                                                       // RW-4R
#define AHCI_HBA_SHUTDOWN_TIMER_0_SECURE                   0
#define AHCI_HBA_SHUTDOWN_TIMER_0_WORD_COUNT               1
#define AHCI_HBA_SHUTDOWN_TIMER_0_RESET_VAL                0x0
#define AHCI_HBA_SHUTDOWN_TIMER_0_RESET_MASK               0x0
#define AHCI_HBA_SHUTDOWN_TIMER_0_SW_DEFAULT_VAL           0x0
#define AHCI_HBA_SHUTDOWN_TIMER_0_SW_DEFAULT_MASK          0x0
#define AHCI_HBA_SHUTDOWN_TIMER_0_READ_MASK                0xfffffff
#define AHCI_HBA_SHUTDOWN_TIMER_0_WRITE_MASK               0xfffffff
#define AHCI_HBA_SHUTDOWN_TIMER_0_TXRX_CLK_SHIFT            _MK_SHIFT_CONST(0)                                                              // RWC-F
#define AHCI_HBA_SHUTDOWN_TIMER_0_TXRX_CLK_FIELD           (_MK_SHIFT_CONST(0x3fff) << AHCI_HBA_SHUTDOWN_TIMER_0_TXRX_CLK_SHIFT)
#define AHCI_HBA_SHUTDOWN_TIMER_0_TXRX_CLK_RANGE           13:0
#define AHCI_HBA_SHUTDOWN_TIMER_0_TXRX_CLK_WOFFSET         0
#define AHCI_HBA_SHUTDOWN_TIMER_0_TXRX_CLK_INIT            _MK_ENUM_CONST(0x00000004)                                                       // RWC-V
#define AHCI_HBA_SHUTDOWN_TIMER_0_DEV_CLK_SHIFT             _MK_SHIFT_CONST(14)                                                             // RWC-F
#define AHCI_HBA_SHUTDOWN_TIMER_0_DEV_CLK_FIELD            (_MK_SHIFT_CONST(0x3fff) << AHCI_HBA_SHUTDOWN_TIMER_0_DEV_CLK_SHIFT)
#define AHCI_HBA_SHUTDOWN_TIMER_0_DEV_CLK_RANGE            27:14
#define AHCI_HBA_SHUTDOWN_TIMER_0_DEV_CLK_WOFFSET          0
#define AHCI_HBA_SHUTDOWN_TIMER_0_DEV_CLK_INIT             _MK_ENUM_CONST(0x00000004)                                                       // RWC-V
// 
// 
// 
// 
// 
// 
// .LABEL PRIVATE
// .TITLE HBA_DEBUG_BUS_REG0
// 
// 31           24 23           16 15            8 7             0
// .-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-.
// |0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0| Debug Bus Reg0
// `-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-'
// 
#define AHCI_HBA_DEBUG_BUS_REG0_0                          0x000000B0                                                                       // R--4R
#define AHCI_HBA_DEBUG_BUS_REG0_0_SECURE                   0
#define AHCI_HBA_DEBUG_BUS_REG0_0_WORD_COUNT               1
#define AHCI_HBA_DEBUG_BUS_REG0_0_RESET_VAL                0x0
#define AHCI_HBA_DEBUG_BUS_REG0_0_RESET_MASK               0x0
#define AHCI_HBA_DEBUG_BUS_REG0_0_SW_DEFAULT_VAL           0x0
#define AHCI_HBA_DEBUG_BUS_REG0_0_SW_DEFAULT_MASK          0x0
#define AHCI_HBA_DEBUG_BUS_REG0_0_READ_MASK                0xffffffff
#define AHCI_HBA_DEBUG_BUS_REG0_0_WRITE_MASK               0x0
#define AHCI_HBA_DEBUG_BUS_REG0_0_DATA_SHIFT                _MK_SHIFT_CONST(0)                                                              // R---F
#define AHCI_HBA_DEBUG_BUS_REG0_0_DATA_FIELD               (_MK_SHIFT_CONST(0xffffffff) << AHCI_HBA_DEBUG_BUS_REG0_0_DATA_SHIFT)
#define AHCI_HBA_DEBUG_BUS_REG0_0_DATA_RANGE               31:0
#define AHCI_HBA_DEBUG_BUS_REG0_0_DATA_WOFFSET             0
#define AHCI_HBA_DEBUG_BUS_REG0_0_DATA_CLEAR               _MK_ENUM_CONST(0x00000000)                                                       // R---V
// 
// .LABEL PUBLIC
// 
// .LABEL PRIVATE
// .TITLE HBA_DEBUG_BUS_REG1
// 
// 1           24 23           16 15            8 7             0
// .-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-.
// |0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0| Debug Bus Reg1
// `-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-'
// 
#define AHCI_HBA_DEBUG_BUS_REG1_0                          0x000000B4                                                                       // R--4R
#define AHCI_HBA_DEBUG_BUS_REG1_0_SECURE                   0
#define AHCI_HBA_DEBUG_BUS_REG1_0_WORD_COUNT               1
#define AHCI_HBA_DEBUG_BUS_REG1_0_RESET_VAL                0x0
#define AHCI_HBA_DEBUG_BUS_REG1_0_RESET_MASK               0x0
#define AHCI_HBA_DEBUG_BUS_REG1_0_SW_DEFAULT_VAL           0x0
#define AHCI_HBA_DEBUG_BUS_REG1_0_SW_DEFAULT_MASK          0x0
#define AHCI_HBA_DEBUG_BUS_REG1_0_READ_MASK                0xffffffff
#define AHCI_HBA_DEBUG_BUS_REG1_0_WRITE_MASK               0x0
#define AHCI_HBA_DEBUG_BUS_REG1_0_DATA_SHIFT                _MK_SHIFT_CONST(0)                                                              // R---F
#define AHCI_HBA_DEBUG_BUS_REG1_0_DATA_FIELD               (_MK_SHIFT_CONST(0xffffffff) << AHCI_HBA_DEBUG_BUS_REG1_0_DATA_SHIFT)
#define AHCI_HBA_DEBUG_BUS_REG1_0_DATA_RANGE               31:0
#define AHCI_HBA_DEBUG_BUS_REG1_0_DATA_WOFFSET             0
#define AHCI_HBA_DEBUG_BUS_REG1_0_DATA_CLEAR               _MK_ENUM_CONST(0x00000000)                                                       // R---V
// 
// .LABEL PUBLIC
// 
// 
// 
// .LABEL PRIVATE INT_REL
// .TITLE HBA_SPARE_3
// 31           24 23           16 15            8 7             0
// .-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-.
// |0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0| SPARE Reg 3
// `-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-'
// 
#define AHCI_HBA_SPARE_3_0                                 0x000000F4                                                                       // RW-4R
#define AHCI_HBA_SPARE_3_0_SECURE                          0
#define AHCI_HBA_SPARE_3_0_WORD_COUNT                      1
#define AHCI_HBA_SPARE_3_0_RESET_VAL                       0xf0f0
#define AHCI_HBA_SPARE_3_0_RESET_MASK                      0xffff
#define AHCI_HBA_SPARE_3_0_SW_DEFAULT_VAL                  0xf0f0
#define AHCI_HBA_SPARE_3_0_SW_DEFAULT_MASK                 0xffff
#define AHCI_HBA_SPARE_3_0_READ_MASK                       0xffffffff
#define AHCI_HBA_SPARE_3_0_WRITE_MASK                      0xffffffff
#define AHCI_HBA_SPARE_3_0_RSVD_31_16_SHIFT                 _MK_SHIFT_CONST(16)                                                             // RWC-F
#define AHCI_HBA_SPARE_3_0_RSVD_31_16_FIELD                (_MK_SHIFT_CONST(0xffff) << AHCI_HBA_SPARE_3_0_RSVD_31_16_SHIFT)
#define AHCI_HBA_SPARE_3_0_RSVD_31_16_RANGE                31:16
#define AHCI_HBA_SPARE_3_0_RSVD_31_16_WOFFSET              0
#define AHCI_HBA_SPARE_3_0_RSVD_31_16_ZERO                 _MK_ENUM_CONST(0x0000F0F0)                                                       // RWC-V
#define AHCI_HBA_SPARE_3_0_RSVD_15_00_SHIFT                 _MK_SHIFT_CONST(0)                                                              // RWI-F
#define AHCI_HBA_SPARE_3_0_RSVD_15_00_FIELD                (_MK_SHIFT_CONST(0xffff) << AHCI_HBA_SPARE_3_0_RSVD_15_00_SHIFT)
#define AHCI_HBA_SPARE_3_0_RSVD_15_00_RANGE                15:0
#define AHCI_HBA_SPARE_3_0_RSVD_15_00_WOFFSET              0
#define AHCI_HBA_SPARE_3_0_RSVD_15_00_DEFAULT              (_MK_MASK_CONST(0x0000F0F0)
#define AHCI_HBA_SPARE_3_0_RSVD_15_00_DEFAULT_MASK         (_MK_MASK_CONST(0xffff)
#define AHCI_HBA_SPARE_3_0_RSVD_15_00_SW_DEFAULT           (_MK_MASK_CONST(0x0000F0F0)
#define AHCI_HBA_SPARE_3_0_RSVD_15_00_SW_DEFAULT_MASK      (_MK_MASK_CONST(0xffff)
#define AHCI_HBA_SPARE_3_0_RSVD_15_00_ZERO                 _MK_ENUM_CONST(0x0000F0F0)                                                       // RWI-V
// 
// .LABEL PUBLIC
// 
// 
// 
// .PUBLIC
// .LABEL PUBLIC
// .SUBSECTION Port Registers
// 
// .TITLE Port Command List Base Address
// .FIELD CLB
// Indicates the 32-bit base physical address for
// the command list for this port. This base is used when fetching commands to execute.
// The structure pointed to by this address range is 1K-bytes in length. This address must
// be 1K-byte aligned as indicated by bits 09:00 being read only.
// 
// 31           24 23           16 15            8 7             0
// .-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-.
// |0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0| PORT_PXCLB
// `-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-'
// 
#define AHCI_PORT_PXCLB_0                                  0x00000100                                                                       // RW-4R
#define AHCI_PORT_PXCLB_0_SECURE                           0
#define AHCI_PORT_PXCLB_0_WORD_COUNT                       1
#define AHCI_PORT_PXCLB_0_RESET_VAL                        0x0
#define AHCI_PORT_PXCLB_0_RESET_MASK                       0x0
#define AHCI_PORT_PXCLB_0_SW_DEFAULT_VAL                   0x0
#define AHCI_PORT_PXCLB_0_SW_DEFAULT_MASK                  0x0
#define AHCI_PORT_PXCLB_0_READ_MASK                        0xffffffff
#define AHCI_PORT_PXCLB_0_WRITE_MASK                       0xfffffc00
#define AHCI_PORT_PXCLB_0_RSVD_SHIFT                        _MK_SHIFT_CONST(0)                                                              // C--VF
#define AHCI_PORT_PXCLB_0_RSVD_FIELD                       (_MK_SHIFT_CONST(0x3ff) << AHCI_PORT_PXCLB_0_RSVD_SHIFT)
#define AHCI_PORT_PXCLB_0_RSVD_RANGE                       9:0
#define AHCI_PORT_PXCLB_0_RSVD_WOFFSET                     0
#define AHCI_PORT_PXCLB_0_RSVD_00                          _MK_ENUM_CONST(0x00000000)                                                       // C---V
#define AHCI_PORT_PXCLB_0_CLB_SHIFT                         _MK_SHIFT_CONST(10)                                                             // RWWUF
#define AHCI_PORT_PXCLB_0_CLB_FIELD                        (_MK_SHIFT_CONST(0x3fffff) << AHCI_PORT_PXCLB_0_CLB_SHIFT)
#define AHCI_PORT_PXCLB_0_CLB_RANGE                        31:10
#define AHCI_PORT_PXCLB_0_CLB_WOFFSET                      0
#define AHCI_PORT_PXCLB_0_CLB_DEFAULT                      (_MK_MASK_CONST(0x00000000)
#define AHCI_PORT_PXCLB_0_CLB_DEFAULT_MASK                 (_MK_MASK_CONST(0x3fffff)
#define AHCI_PORT_PXCLB_0_CLB_SW_DEFAULT                   (_MK_MASK_CONST(0x00000000)
#define AHCI_PORT_PXCLB_0_CLB_SW_DEFAULT_MASK              (_MK_MASK_CONST(0x3fffff)
#define AHCI_PORT_PXCLB_0_CLB__NOPRDCHK                    _MK_ENUM_CONST(0x00000001)                                                       // ----V
#define AHCI_PORT_PXCLB_0_CLB_00                           _MK_ENUM_CONST(0x00000000)                                                       // RWWUV
// 
// 
//              Figure 9-XXX Port Command List Base Address Register.
// 
// 
// .TITLE Port Command List Base Address Upper
// .FIELD CLB
// Indicates the upper 32-bits for the
// command list base physical address for this port. This base is used when fetching
// commands to execute.
// This register shall be read only 0 for HBAs that do not support 64-bit addressing
// 
// 
// 31           24 23           16 15            8 7             0
// .-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-.
// |0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0| PORT_PXCLBU
// `-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-'
// 
#define AHCI_PORT_PXCLBU_0                                 0x00000104                                                                       // RW-4R
#define AHCI_PORT_PXCLBU_0_SECURE                          0
#define AHCI_PORT_PXCLBU_0_WORD_COUNT                      1
#define AHCI_PORT_PXCLBU_0_RESET_VAL                       0x0
#define AHCI_PORT_PXCLBU_0_RESET_MASK                      0x0
#define AHCI_PORT_PXCLBU_0_SW_DEFAULT_VAL                  0x0
#define AHCI_PORT_PXCLBU_0_SW_DEFAULT_MASK                 0x0
#define AHCI_PORT_PXCLBU_0_READ_MASK                       0xffffffff
#define AHCI_PORT_PXCLBU_0_WRITE_MASK                      0xffffffff
#define AHCI_PORT_PXCLBU_0_CLB_SHIFT                        _MK_SHIFT_CONST(0)                                                              // RWWVF
#define AHCI_PORT_PXCLBU_0_CLB_FIELD                       (_MK_SHIFT_CONST(0xffffffff) << AHCI_PORT_PXCLBU_0_CLB_SHIFT)
#define AHCI_PORT_PXCLBU_0_CLB_RANGE                       31:0
#define AHCI_PORT_PXCLBU_0_CLB_WOFFSET                     0
#define AHCI_PORT_PXCLBU_0_CLB_DEFAULT                     (_MK_MASK_CONST(0x00000000)
#define AHCI_PORT_PXCLBU_0_CLB_DEFAULT_MASK                (_MK_MASK_CONST(0xffffffff)
#define AHCI_PORT_PXCLBU_0_CLB_SW_DEFAULT                  (_MK_MASK_CONST(0x00000000)
#define AHCI_PORT_PXCLBU_0_CLB_SW_DEFAULT_MASK             (_MK_MASK_CONST(0xffffffff)
#define AHCI_PORT_PXCLBU_0_CLB__NOPRDCHK                   _MK_ENUM_CONST(0x00000001)                                                       // ----V
#define AHCI_PORT_PXCLBU_0_CLB_00                          _MK_ENUM_CONST(0x00000000)                                                       // RWW-V
// 
// 
//              Figure 9-XXX Port Command List Base Address Upper Register.
// 
// 
// .TITLE Port FIS Base Address
// .FIELD FB
// Indicates the 32-bit base physical address for received
// FISes. The structure pointed to by this address range is 256 bytes in length. This
// address must be 256-byte aligned as indicated by bits 07:00 being read only. When
// FIS-based switching is in use, this structure is 4KB in length and the address shall be
// 4KB aligned
// 
// 31           24 23           16 15            8 7             0
// .-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-.
// |0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0| PORT_PXFB
// `-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-'
// 
#define AHCI_PORT_PXFB_0                                   0x00000108                                                                       // RW-4R
#define AHCI_PORT_PXFB_0_SECURE                            0
#define AHCI_PORT_PXFB_0_WORD_COUNT                        1
#define AHCI_PORT_PXFB_0_RESET_VAL                         0x0
#define AHCI_PORT_PXFB_0_RESET_MASK                        0x0
#define AHCI_PORT_PXFB_0_SW_DEFAULT_VAL                    0x0
#define AHCI_PORT_PXFB_0_SW_DEFAULT_MASK                   0x0
#define AHCI_PORT_PXFB_0_READ_MASK                         0xffffffff
#define AHCI_PORT_PXFB_0_WRITE_MASK                        0xffffff00
#define AHCI_PORT_PXFB_0_RSVD_SHIFT                         _MK_SHIFT_CONST(0)                                                              // C--VF
#define AHCI_PORT_PXFB_0_RSVD_FIELD                        (_MK_SHIFT_CONST(0xff) << AHCI_PORT_PXFB_0_RSVD_SHIFT)
#define AHCI_PORT_PXFB_0_RSVD_RANGE                        7:0
#define AHCI_PORT_PXFB_0_RSVD_WOFFSET                      0
#define AHCI_PORT_PXFB_0_RSVD__NOPRDCHK                    _MK_ENUM_CONST(0x00000001)                                                       // ----V
#define AHCI_PORT_PXFB_0_RSVD_00                           _MK_ENUM_CONST(0x00000000)                                                       // C---V
#define AHCI_PORT_PXFB_0_FB_SHIFT                           _MK_SHIFT_CONST(8)                                                              // RWWVF
#define AHCI_PORT_PXFB_0_FB_FIELD                          (_MK_SHIFT_CONST(0xffffff) << AHCI_PORT_PXFB_0_FB_SHIFT)
#define AHCI_PORT_PXFB_0_FB_RANGE                          31:8
#define AHCI_PORT_PXFB_0_FB_WOFFSET                        0
#define AHCI_PORT_PXFB_0_FB_DEFAULT                        (_MK_MASK_CONST(0x00000000)
#define AHCI_PORT_PXFB_0_FB_DEFAULT_MASK                   (_MK_MASK_CONST(0xffffff)
#define AHCI_PORT_PXFB_0_FB_SW_DEFAULT                     (_MK_MASK_CONST(0x00000000)
#define AHCI_PORT_PXFB_0_FB_SW_DEFAULT_MASK                (_MK_MASK_CONST(0xffffff)
#define AHCI_PORT_PXFB_0_FB__NOPRDCHK                      _MK_ENUM_CONST(0x00000001)                                                       // ----V
#define AHCI_PORT_PXFB_0_FB_00                             _MK_ENUM_CONST(0x00000000)                                                       // RWW-V
// 
// 
//              Figure 9-XXX Port FIS Base Address Register.
// 
// 
// 
// .TITLE Port FIS Base Address Upper
// .FIELD FB
// Indicates the upper 32-bits for the received FIS base
// physical address for this port.
// This register shall be read only 0 for HBAs that do not support 64-bit addressing.
// 
// 31           24 23           16 15            8 7             0
// .-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-.
// |0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0| PORT_PXFBU
// `-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-'
// 
#define AHCI_PORT_PXFBU_0                                  0x0000010C                                                                       // RW-4R
#define AHCI_PORT_PXFBU_0_SECURE                           0
#define AHCI_PORT_PXFBU_0_WORD_COUNT                       1
#define AHCI_PORT_PXFBU_0_RESET_VAL                        0x0
#define AHCI_PORT_PXFBU_0_RESET_MASK                       0x0
#define AHCI_PORT_PXFBU_0_SW_DEFAULT_VAL                   0x0
#define AHCI_PORT_PXFBU_0_SW_DEFAULT_MASK                  0x0
#define AHCI_PORT_PXFBU_0_READ_MASK                        0xffffffff
#define AHCI_PORT_PXFBU_0_WRITE_MASK                       0xffffffff
#define AHCI_PORT_PXFBU_0_FB_SHIFT                          _MK_SHIFT_CONST(0)                                                              // RWWVF
#define AHCI_PORT_PXFBU_0_FB_FIELD                         (_MK_SHIFT_CONST(0xffffffff) << AHCI_PORT_PXFBU_0_FB_SHIFT)
#define AHCI_PORT_PXFBU_0_FB_RANGE                         31:0
#define AHCI_PORT_PXFBU_0_FB_WOFFSET                       0
#define AHCI_PORT_PXFBU_0_FB_DEFAULT                       (_MK_MASK_CONST(0x00000000)
#define AHCI_PORT_PXFBU_0_FB_DEFAULT_MASK                  (_MK_MASK_CONST(0xffffffff)
#define AHCI_PORT_PXFBU_0_FB_SW_DEFAULT                    (_MK_MASK_CONST(0x00000000)
#define AHCI_PORT_PXFBU_0_FB_SW_DEFAULT_MASK               (_MK_MASK_CONST(0xffffffff)
#define AHCI_PORT_PXFBU_0_FB__NOPRDCHK                     _MK_ENUM_CONST(0x00000001)                                                       // ----V
#define AHCI_PORT_PXFBU_0_FB_00                            _MK_ENUM_CONST(0x00000000)                                                       // RWW-V
// 
// 
//              Figure 9-XXX Port FIS Base Address Register Upper.
// 
// 
// 
// 
// .TITLE Port Interrupt Status
// .FIELD
// 
// 
// 31           24 23           16 15            8 7             0
// .-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-.
// |0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0| PORT_PXIS
// `-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-'
// 
#define AHCI_PORT_PXIS_0                                   0x00000110                                                                       // RW-4R
#define AHCI_PORT_PXIS_0_SECURE                            0
#define AHCI_PORT_PXIS_0_WORD_COUNT                        1
#define AHCI_PORT_PXIS_0_RESET_VAL                         0x0
#define AHCI_PORT_PXIS_0_RESET_MASK                        0xfdc0007f
#define AHCI_PORT_PXIS_0_SW_DEFAULT_VAL                    0x0
#define AHCI_PORT_PXIS_0_SW_DEFAULT_MASK                   0xfdc0007f
#define AHCI_PORT_PXIS_0_READ_MASK                         0xfdffffff
#define AHCI_PORT_PXIS_0_WRITE_MASK                        0xfd80002f
#define AHCI_PORT_PXIS_0_DHRS_SHIFT                         _MK_SHIFT_CONST(0)                                                              // RWIVF
#define AHCI_PORT_PXIS_0_DHRS_FIELD                        (_MK_SHIFT_CONST(0x1) << AHCI_PORT_PXIS_0_DHRS_SHIFT)
#define AHCI_PORT_PXIS_0_DHRS_RANGE                        0:0
#define AHCI_PORT_PXIS_0_DHRS_WOFFSET                      0
#define AHCI_PORT_PXIS_0_DHRS_DEFAULT                      (_MK_MASK_CONST(0x00000000)
#define AHCI_PORT_PXIS_0_DHRS_DEFAULT_MASK                 (_MK_MASK_CONST(0x1)
#define AHCI_PORT_PXIS_0_DHRS_SW_DEFAULT                   (_MK_MASK_CONST(0x00000000)
#define AHCI_PORT_PXIS_0_DHRS_SW_DEFAULT_MASK              (_MK_MASK_CONST(0x1)
#define AHCI_PORT_PXIS_0_DHRS__NOPRDCHK                    _MK_ENUM_CONST(0x00000001)                                                       // ----V
#define AHCI_PORT_PXIS_0_DHRS_NOTPRSNT                     _MK_ENUM_CONST(0x00000000)                                                       // R-I-V
#define AHCI_PORT_PXIS_0_DHRS_PRSNT                        _MK_ENUM_CONST(0x00000001)                                                       // R---V
#define AHCI_PORT_PXIS_0_DHRS_CLEAR                        _MK_ENUM_CONST(0x00000001)                                                       // -W--C
#define AHCI_PORT_PXIS_0_PSS_SHIFT                          _MK_SHIFT_CONST(1)                                                              // RWIVF
#define AHCI_PORT_PXIS_0_PSS_FIELD                         (_MK_SHIFT_CONST(0x1) << AHCI_PORT_PXIS_0_PSS_SHIFT)
#define AHCI_PORT_PXIS_0_PSS_RANGE                         1:1
#define AHCI_PORT_PXIS_0_PSS_WOFFSET                       0
#define AHCI_PORT_PXIS_0_PSS_DEFAULT                       (_MK_MASK_CONST(0x00000000)
#define AHCI_PORT_PXIS_0_PSS_DEFAULT_MASK                  (_MK_MASK_CONST(0x1)
#define AHCI_PORT_PXIS_0_PSS_SW_DEFAULT                    (_MK_MASK_CONST(0x00000000)
#define AHCI_PORT_PXIS_0_PSS_SW_DEFAULT_MASK               (_MK_MASK_CONST(0x1)
#define AHCI_PORT_PXIS_0_PSS__NOPRDCHK                     _MK_ENUM_CONST(0x00000001)                                                       // ----V
#define AHCI_PORT_PXIS_0_PSS_NOTPRSNT                      _MK_ENUM_CONST(0x00000000)                                                       // R-I-V
#define AHCI_PORT_PXIS_0_PSS_PRSNT                         _MK_ENUM_CONST(0x00000001)                                                       // R---V
#define AHCI_PORT_PXIS_0_PSS_CLEAR                         _MK_ENUM_CONST(0x00000001)                                                       // -W--C
#define AHCI_PORT_PXIS_0_DSS_SHIFT                          _MK_SHIFT_CONST(2)                                                              // RWIVF
#define AHCI_PORT_PXIS_0_DSS_FIELD                         (_MK_SHIFT_CONST(0x1) << AHCI_PORT_PXIS_0_DSS_SHIFT)
#define AHCI_PORT_PXIS_0_DSS_RANGE                         2:2
#define AHCI_PORT_PXIS_0_DSS_WOFFSET                       0
#define AHCI_PORT_PXIS_0_DSS_DEFAULT                       (_MK_MASK_CONST(0x00000000)
#define AHCI_PORT_PXIS_0_DSS_DEFAULT_MASK                  (_MK_MASK_CONST(0x1)
#define AHCI_PORT_PXIS_0_DSS_SW_DEFAULT                    (_MK_MASK_CONST(0x00000000)
#define AHCI_PORT_PXIS_0_DSS_SW_DEFAULT_MASK               (_MK_MASK_CONST(0x1)
#define AHCI_PORT_PXIS_0_DSS__NOPRDCHK                     _MK_ENUM_CONST(0x00000001)                                                       // ----V
#define AHCI_PORT_PXIS_0_DSS_NOTPRSNT                      _MK_ENUM_CONST(0x00000000)                                                       // R-I-V
#define AHCI_PORT_PXIS_0_DSS_PRSNT                         _MK_ENUM_CONST(0x00000001)                                                       // R---V
#define AHCI_PORT_PXIS_0_DSS_CLEAR                         _MK_ENUM_CONST(0x00000001)                                                       // -W--C
#define AHCI_PORT_PXIS_0_SDBS_SHIFT                         _MK_SHIFT_CONST(3)                                                              // RWIVF
#define AHCI_PORT_PXIS_0_SDBS_FIELD                        (_MK_SHIFT_CONST(0x1) << AHCI_PORT_PXIS_0_SDBS_SHIFT)
#define AHCI_PORT_PXIS_0_SDBS_RANGE                        3:3
#define AHCI_PORT_PXIS_0_SDBS_WOFFSET                      0
#define AHCI_PORT_PXIS_0_SDBS_DEFAULT                      (_MK_MASK_CONST(0x00000000)
#define AHCI_PORT_PXIS_0_SDBS_DEFAULT_MASK                 (_MK_MASK_CONST(0x1)
#define AHCI_PORT_PXIS_0_SDBS_SW_DEFAULT                   (_MK_MASK_CONST(0x00000000)
#define AHCI_PORT_PXIS_0_SDBS_SW_DEFAULT_MASK              (_MK_MASK_CONST(0x1)
#define AHCI_PORT_PXIS_0_SDBS__NOPRDCHK                    _MK_ENUM_CONST(0x00000001)                                                       // ----V
#define AHCI_PORT_PXIS_0_SDBS_NOTPRSNT                     _MK_ENUM_CONST(0x00000000)                                                       // R-I-V
#define AHCI_PORT_PXIS_0_SDBS_PRSNT                        _MK_ENUM_CONST(0x00000001)                                                       // R---V
#define AHCI_PORT_PXIS_0_SDBS_CLEAR                        _MK_ENUM_CONST(0x00000001)                                                       // -W--C
#define AHCI_PORT_PXIS_0_UFS_SHIFT                          _MK_SHIFT_CONST(4)                                                              // R-IVF
#define AHCI_PORT_PXIS_0_UFS_FIELD                         (_MK_SHIFT_CONST(0x1) << AHCI_PORT_PXIS_0_UFS_SHIFT)
#define AHCI_PORT_PXIS_0_UFS_RANGE                         4:4
#define AHCI_PORT_PXIS_0_UFS_WOFFSET                       0
#define AHCI_PORT_PXIS_0_UFS_DEFAULT                       (_MK_MASK_CONST(0x00000000)
#define AHCI_PORT_PXIS_0_UFS_DEFAULT_MASK                  (_MK_MASK_CONST(0x1)
#define AHCI_PORT_PXIS_0_UFS_SW_DEFAULT                    (_MK_MASK_CONST(0x00000000)
#define AHCI_PORT_PXIS_0_UFS_SW_DEFAULT_MASK               (_MK_MASK_CONST(0x1)
#define AHCI_PORT_PXIS_0_UFS__NOPRDCHK                     _MK_ENUM_CONST(0x00000001)                                                       // ----V
#define AHCI_PORT_PXIS_0_UFS_NOTPRSNT                      _MK_ENUM_CONST(0x00000000)                                                       // R-I-V
#define AHCI_PORT_PXIS_0_UFS_PRSNT                         _MK_ENUM_CONST(0x00000001)                                                       // R---V
#define AHCI_PORT_PXIS_0_DPS_SHIFT                          _MK_SHIFT_CONST(5)                                                              // RWIVF
#define AHCI_PORT_PXIS_0_DPS_FIELD                         (_MK_SHIFT_CONST(0x1) << AHCI_PORT_PXIS_0_DPS_SHIFT)
#define AHCI_PORT_PXIS_0_DPS_RANGE                         5:5
#define AHCI_PORT_PXIS_0_DPS_WOFFSET                       0
#define AHCI_PORT_PXIS_0_DPS_DEFAULT                       (_MK_MASK_CONST(0x00000000)
#define AHCI_PORT_PXIS_0_DPS_DEFAULT_MASK                  (_MK_MASK_CONST(0x1)
#define AHCI_PORT_PXIS_0_DPS_SW_DEFAULT                    (_MK_MASK_CONST(0x00000000)
#define AHCI_PORT_PXIS_0_DPS_SW_DEFAULT_MASK               (_MK_MASK_CONST(0x1)
#define AHCI_PORT_PXIS_0_DPS__NOPRDCHK                     _MK_ENUM_CONST(0x00000001)                                                       // ----V
#define AHCI_PORT_PXIS_0_DPS_NOTDONE                       _MK_ENUM_CONST(0x00000000)                                                       // R-I-V
#define AHCI_PORT_PXIS_0_DPS_DONE                          _MK_ENUM_CONST(0x00000001)                                                       // R---V
#define AHCI_PORT_PXIS_0_DPS_CLEAR                         _MK_ENUM_CONST(0x00000001)                                                       // -W--C
#define AHCI_PORT_PXIS_0_PCS_SHIFT                          _MK_SHIFT_CONST(6)                                                              // R-IVF
#define AHCI_PORT_PXIS_0_PCS_FIELD                         (_MK_SHIFT_CONST(0x1) << AHCI_PORT_PXIS_0_PCS_SHIFT)
#define AHCI_PORT_PXIS_0_PCS_RANGE                         6:6
#define AHCI_PORT_PXIS_0_PCS_WOFFSET                       0
#define AHCI_PORT_PXIS_0_PCS_DEFAULT                       (_MK_MASK_CONST(0x00000000)
#define AHCI_PORT_PXIS_0_PCS_DEFAULT_MASK                  (_MK_MASK_CONST(0x1)
#define AHCI_PORT_PXIS_0_PCS_SW_DEFAULT                    (_MK_MASK_CONST(0x00000000)
#define AHCI_PORT_PXIS_0_PCS_SW_DEFAULT_MASK               (_MK_MASK_CONST(0x1)
#define AHCI_PORT_PXIS_0_PCS__NOPRDCHK                     _MK_ENUM_CONST(0x00000001)                                                       // ----V
#define AHCI_PORT_PXIS_0_PCS_TRUE                          _MK_ENUM_CONST(0x00000001)                                                       // R---V
#define AHCI_PORT_PXIS_0_PCS_FALSE                         _MK_ENUM_CONST(0x00000000)                                                       // R-I-V
#define AHCI_PORT_PXIS_0_DMPS_SHIFT                         _MK_SHIFT_CONST(7)                                                              // C--VF
#define AHCI_PORT_PXIS_0_DMPS_FIELD                        (_MK_SHIFT_CONST(0x1) << AHCI_PORT_PXIS_0_DMPS_SHIFT)
#define AHCI_PORT_PXIS_0_DMPS_RANGE                        7:7
#define AHCI_PORT_PXIS_0_DMPS_WOFFSET                      0
#define AHCI_PORT_PXIS_0_DMPS__NOPRDCHK                    _MK_ENUM_CONST(0x00000001)                                                       // ----V
#define AHCI_PORT_PXIS_0_DMPS_OPEN                         _MK_ENUM_CONST(0x00000000)                                                       // C---V
#define AHCI_PORT_PXIS_0_DMPS_CLOSED                       _MK_ENUM_CONST(0x00000001)                                                       // ----V
#define AHCI_PORT_PXIS_0_DMPS_CLEAR                        _MK_ENUM_CONST(0x00000001)                                                       // ----V
#define AHCI_PORT_PXIS_0_RSVD_SHIFT                         _MK_SHIFT_CONST(8)                                                              // C--VF
#define AHCI_PORT_PXIS_0_RSVD_FIELD                        (_MK_SHIFT_CONST(0x3fff) << AHCI_PORT_PXIS_0_RSVD_SHIFT)
#define AHCI_PORT_PXIS_0_RSVD_RANGE                        21:8
#define AHCI_PORT_PXIS_0_RSVD_WOFFSET                      0
#define AHCI_PORT_PXIS_0_RSVD__NOPRDCHK                    _MK_ENUM_CONST(0x00000001)                                                       // ----V
#define AHCI_PORT_PXIS_0_RSVD_00                           _MK_ENUM_CONST(0x00000000)                                                       // C---V
#define AHCI_PORT_PXIS_0_PRCS_SHIFT                         _MK_SHIFT_CONST(22)                                                             // R-IVF
#define AHCI_PORT_PXIS_0_PRCS_FIELD                        (_MK_SHIFT_CONST(0x1) << AHCI_PORT_PXIS_0_PRCS_SHIFT)
#define AHCI_PORT_PXIS_0_PRCS_RANGE                        22:22
#define AHCI_PORT_PXIS_0_PRCS_WOFFSET                      0
#define AHCI_PORT_PXIS_0_PRCS_DEFAULT                      (_MK_MASK_CONST(0x00000000)
#define AHCI_PORT_PXIS_0_PRCS_DEFAULT_MASK                 (_MK_MASK_CONST(0x1)
#define AHCI_PORT_PXIS_0_PRCS_SW_DEFAULT                   (_MK_MASK_CONST(0x00000000)
#define AHCI_PORT_PXIS_0_PRCS_SW_DEFAULT_MASK              (_MK_MASK_CONST(0x1)
#define AHCI_PORT_PXIS_0_PRCS__NOPRDCHK                    _MK_ENUM_CONST(0x00000001)                                                       // ----V
#define AHCI_PORT_PXIS_0_PRCS_CLEAR                        _MK_ENUM_CONST(0x00000000)                                                       // R-I-V
#define AHCI_PORT_PXIS_0_PRCS_SET                          _MK_ENUM_CONST(0x00000001)                                                       // R---V
#define AHCI_PORT_PXIS_0_IPMS_SHIFT                         _MK_SHIFT_CONST(23)                                                             // RWIVF
#define AHCI_PORT_PXIS_0_IPMS_FIELD                        (_MK_SHIFT_CONST(0x1) << AHCI_PORT_PXIS_0_IPMS_SHIFT)
#define AHCI_PORT_PXIS_0_IPMS_RANGE                        23:23
#define AHCI_PORT_PXIS_0_IPMS_WOFFSET                      0
#define AHCI_PORT_PXIS_0_IPMS_DEFAULT                      (_MK_MASK_CONST(0x00000000)
#define AHCI_PORT_PXIS_0_IPMS_DEFAULT_MASK                 (_MK_MASK_CONST(0x1)
#define AHCI_PORT_PXIS_0_IPMS_SW_DEFAULT                   (_MK_MASK_CONST(0x00000000)
#define AHCI_PORT_PXIS_0_IPMS_SW_DEFAULT_MASK              (_MK_MASK_CONST(0x1)
#define AHCI_PORT_PXIS_0_IPMS__NOPRDCHK                    _MK_ENUM_CONST(0x00000001)                                                       // ----V
#define AHCI_PORT_PXIS_0_IPMS_NOTRCVD                      _MK_ENUM_CONST(0x00000000)                                                       // R-I-V
#define AHCI_PORT_PXIS_0_IPMS_RCVD                         _MK_ENUM_CONST(0x00000001)                                                       // R---V
#define AHCI_PORT_PXIS_0_IPMS_CLEAR                        _MK_ENUM_CONST(0x00000001)                                                       // -W--C
#define AHCI_PORT_PXIS_0_OFS_SHIFT                          _MK_SHIFT_CONST(24)                                                             // RWIVF
#define AHCI_PORT_PXIS_0_OFS_FIELD                         (_MK_SHIFT_CONST(0x1) << AHCI_PORT_PXIS_0_OFS_SHIFT)
#define AHCI_PORT_PXIS_0_OFS_RANGE                         24:24
#define AHCI_PORT_PXIS_0_OFS_WOFFSET                       0
#define AHCI_PORT_PXIS_0_OFS_DEFAULT                       (_MK_MASK_CONST(0x00000000)
#define AHCI_PORT_PXIS_0_OFS_DEFAULT_MASK                  (_MK_MASK_CONST(0x1)
#define AHCI_PORT_PXIS_0_OFS_SW_DEFAULT                    (_MK_MASK_CONST(0x00000000)
#define AHCI_PORT_PXIS_0_OFS_SW_DEFAULT_MASK               (_MK_MASK_CONST(0x1)
#define AHCI_PORT_PXIS_0_OFS__NOPRDCHK                     _MK_ENUM_CONST(0x00000001)                                                       // ----V
#define AHCI_PORT_PXIS_0_OFS_NOTRCVD                       _MK_ENUM_CONST(0x00000000)                                                       // R-I-V
#define AHCI_PORT_PXIS_0_OFS_RCVD                          _MK_ENUM_CONST(0x00000001)                                                       // R---V
#define AHCI_PORT_PXIS_0_OFS_CLEAR                         _MK_ENUM_CONST(0x00000001)                                                       // -W--C
#define AHCI_PORT_PXIS_0_INFS_SHIFT                         _MK_SHIFT_CONST(26)                                                             // RWIVF
#define AHCI_PORT_PXIS_0_INFS_FIELD                        (_MK_SHIFT_CONST(0x1) << AHCI_PORT_PXIS_0_INFS_SHIFT)
#define AHCI_PORT_PXIS_0_INFS_RANGE                        26:26
#define AHCI_PORT_PXIS_0_INFS_WOFFSET                      0
#define AHCI_PORT_PXIS_0_INFS_DEFAULT                      (_MK_MASK_CONST(0x00000000)
#define AHCI_PORT_PXIS_0_INFS_DEFAULT_MASK                 (_MK_MASK_CONST(0x1)
#define AHCI_PORT_PXIS_0_INFS_SW_DEFAULT                   (_MK_MASK_CONST(0x00000000)
#define AHCI_PORT_PXIS_0_INFS_SW_DEFAULT_MASK              (_MK_MASK_CONST(0x1)
#define AHCI_PORT_PXIS_0_INFS__NOPRDCHK                    _MK_ENUM_CONST(0x00000001)                                                       // ----V
#define AHCI_PORT_PXIS_0_INFS_NOTRCVD                      _MK_ENUM_CONST(0x00000000)                                                       // R-I-V
#define AHCI_PORT_PXIS_0_INFS_RCVD                         _MK_ENUM_CONST(0x00000001)                                                       // R---V
#define AHCI_PORT_PXIS_0_INFS_CLEAR                        _MK_ENUM_CONST(0x00000001)                                                       // -W--C
#define AHCI_PORT_PXIS_0_IFS_SHIFT                          _MK_SHIFT_CONST(27)                                                             // RWIVF
#define AHCI_PORT_PXIS_0_IFS_FIELD                         (_MK_SHIFT_CONST(0x1) << AHCI_PORT_PXIS_0_IFS_SHIFT)
#define AHCI_PORT_PXIS_0_IFS_RANGE                         27:27
#define AHCI_PORT_PXIS_0_IFS_WOFFSET                       0
#define AHCI_PORT_PXIS_0_IFS_DEFAULT                       (_MK_MASK_CONST(0x00000000)
#define AHCI_PORT_PXIS_0_IFS_DEFAULT_MASK                  (_MK_MASK_CONST(0x1)
#define AHCI_PORT_PXIS_0_IFS_SW_DEFAULT                    (_MK_MASK_CONST(0x00000000)
#define AHCI_PORT_PXIS_0_IFS_SW_DEFAULT_MASK               (_MK_MASK_CONST(0x1)
#define AHCI_PORT_PXIS_0_IFS__NOPRDCHK                     _MK_ENUM_CONST(0x00000001)                                                       // ----V
#define AHCI_PORT_PXIS_0_IFS_NOTRCVD                       _MK_ENUM_CONST(0x00000000)                                                       // R-I-V
#define AHCI_PORT_PXIS_0_IFS_RCVD                          _MK_ENUM_CONST(0x00000001)                                                       // R---V
#define AHCI_PORT_PXIS_0_IFS_CLEAR                         _MK_ENUM_CONST(0x00000001)                                                       // -W--C
#define AHCI_PORT_PXIS_0_HBDS_SHIFT                         _MK_SHIFT_CONST(28)                                                             // RWIVF
#define AHCI_PORT_PXIS_0_HBDS_FIELD                        (_MK_SHIFT_CONST(0x1) << AHCI_PORT_PXIS_0_HBDS_SHIFT)
#define AHCI_PORT_PXIS_0_HBDS_RANGE                        28:28
#define AHCI_PORT_PXIS_0_HBDS_WOFFSET                      0
#define AHCI_PORT_PXIS_0_HBDS_DEFAULT                      (_MK_MASK_CONST(0x00000000)
#define AHCI_PORT_PXIS_0_HBDS_DEFAULT_MASK                 (_MK_MASK_CONST(0x1)
#define AHCI_PORT_PXIS_0_HBDS_SW_DEFAULT                   (_MK_MASK_CONST(0x00000000)
#define AHCI_PORT_PXIS_0_HBDS_SW_DEFAULT_MASK              (_MK_MASK_CONST(0x1)
#define AHCI_PORT_PXIS_0_HBDS__NOPRDCHK                    _MK_ENUM_CONST(0x00000001)                                                       // ----V
#define AHCI_PORT_PXIS_0_HBDS_NOTRCVD                      _MK_ENUM_CONST(0x00000000)                                                       // R-I-V
#define AHCI_PORT_PXIS_0_HBDS_RCVD                         _MK_ENUM_CONST(0x00000001)                                                       // R---V
#define AHCI_PORT_PXIS_0_HBDS_CLEAR                        _MK_ENUM_CONST(0x00000001)                                                       // -W--C
#define AHCI_PORT_PXIS_0_HBFS_SHIFT                         _MK_SHIFT_CONST(29)                                                             // RWIVF
#define AHCI_PORT_PXIS_0_HBFS_FIELD                        (_MK_SHIFT_CONST(0x1) << AHCI_PORT_PXIS_0_HBFS_SHIFT)
#define AHCI_PORT_PXIS_0_HBFS_RANGE                        29:29
#define AHCI_PORT_PXIS_0_HBFS_WOFFSET                      0
#define AHCI_PORT_PXIS_0_HBFS_DEFAULT                      (_MK_MASK_CONST(0x00000000)
#define AHCI_PORT_PXIS_0_HBFS_DEFAULT_MASK                 (_MK_MASK_CONST(0x1)
#define AHCI_PORT_PXIS_0_HBFS_SW_DEFAULT                   (_MK_MASK_CONST(0x00000000)
#define AHCI_PORT_PXIS_0_HBFS_SW_DEFAULT_MASK              (_MK_MASK_CONST(0x1)
#define AHCI_PORT_PXIS_0_HBFS__NOPRDCHK                    _MK_ENUM_CONST(0x00000001)                                                       // ----V
#define AHCI_PORT_PXIS_0_HBFS_NOTRCVD                      _MK_ENUM_CONST(0x00000000)                                                       // R-I-V
#define AHCI_PORT_PXIS_0_HBFS_RCVD                         _MK_ENUM_CONST(0x00000001)                                                       // R---V
#define AHCI_PORT_PXIS_0_HBFS_CLEAR                        _MK_ENUM_CONST(0x00000001)                                                       // -W--C
#define AHCI_PORT_PXIS_0_TFES_SHIFT                         _MK_SHIFT_CONST(30)                                                             // RWIVF
#define AHCI_PORT_PXIS_0_TFES_FIELD                        (_MK_SHIFT_CONST(0x1) << AHCI_PORT_PXIS_0_TFES_SHIFT)
#define AHCI_PORT_PXIS_0_TFES_RANGE                        30:30
#define AHCI_PORT_PXIS_0_TFES_WOFFSET                      0
#define AHCI_PORT_PXIS_0_TFES_DEFAULT                      (_MK_MASK_CONST(0x00000000)
#define AHCI_PORT_PXIS_0_TFES_DEFAULT_MASK                 (_MK_MASK_CONST(0x1)
#define AHCI_PORT_PXIS_0_TFES_SW_DEFAULT                   (_MK_MASK_CONST(0x00000000)
#define AHCI_PORT_PXIS_0_TFES_SW_DEFAULT_MASK              (_MK_MASK_CONST(0x1)
#define AHCI_PORT_PXIS_0_TFES__NOPRDCHK                    _MK_ENUM_CONST(0x00000001)                                                       // ----V
#define AHCI_PORT_PXIS_0_TFES_NOTRCVD                      _MK_ENUM_CONST(0x00000000)                                                       // R-I-V
#define AHCI_PORT_PXIS_0_TFES_RCVD                         _MK_ENUM_CONST(0x00000001)                                                       // R---V
#define AHCI_PORT_PXIS_0_TFES_CLEAR                        _MK_ENUM_CONST(0x00000001)                                                       // -W--C
#define AHCI_PORT_PXIS_0_CPDS_SHIFT                         _MK_SHIFT_CONST(31)                                                             // RWIVF
#define AHCI_PORT_PXIS_0_CPDS_FIELD                        (_MK_SHIFT_CONST(0x1) << AHCI_PORT_PXIS_0_CPDS_SHIFT)
#define AHCI_PORT_PXIS_0_CPDS_RANGE                        31:31
#define AHCI_PORT_PXIS_0_CPDS_WOFFSET                      0
#define AHCI_PORT_PXIS_0_CPDS_DEFAULT                      (_MK_MASK_CONST(0x00000000)
#define AHCI_PORT_PXIS_0_CPDS_DEFAULT_MASK                 (_MK_MASK_CONST(0x1)
#define AHCI_PORT_PXIS_0_CPDS_SW_DEFAULT                   (_MK_MASK_CONST(0x00000000)
#define AHCI_PORT_PXIS_0_CPDS_SW_DEFAULT_MASK              (_MK_MASK_CONST(0x1)
#define AHCI_PORT_PXIS_0_CPDS__NOPRDCHK                    _MK_ENUM_CONST(0x00000001)                                                       // ----V
#define AHCI_PORT_PXIS_0_CPDS_NOTRCVD                      _MK_ENUM_CONST(0x00000000)                                                       // R-I-V
#define AHCI_PORT_PXIS_0_CPDS_RCVD                         _MK_ENUM_CONST(0x00000001)                                                       // R---V
#define AHCI_PORT_PXIS_0_CPDS_CLEAR                        _MK_ENUM_CONST(0x00000001)                                                       // -W--C
// 
// 
//              Figure 9-XXX Port Interrupt Status Register.
// 
// 
// 
// 
// .TITLE Port Interrupt Enable
// .FIELD
// 
// 
// 31           24 23           16 15            8 7             0
// .-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-.
// |0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0| PORT_PXIE
// `-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-'
// 
#define AHCI_PORT_PXIE_0                                   0x00000114                                                                       // RW-4R
#define AHCI_PORT_PXIE_0_SECURE                            0
#define AHCI_PORT_PXIE_0_WORD_COUNT                        1
#define AHCI_PORT_PXIE_0_RESET_VAL                         0x0
#define AHCI_PORT_PXIE_0_RESET_MASK                        0xfdc0007f
#define AHCI_PORT_PXIE_0_SW_DEFAULT_VAL                    0x0
#define AHCI_PORT_PXIE_0_SW_DEFAULT_MASK                   0xfdc0007f
#define AHCI_PORT_PXIE_0_READ_MASK                         0xfdffffff
#define AHCI_PORT_PXIE_0_WRITE_MASK                        0x7dc0007f
#define AHCI_PORT_PXIE_0_DHRE_SHIFT                         _MK_SHIFT_CONST(0)                                                              // RWIVF
#define AHCI_PORT_PXIE_0_DHRE_FIELD                        (_MK_SHIFT_CONST(0x1) << AHCI_PORT_PXIE_0_DHRE_SHIFT)
#define AHCI_PORT_PXIE_0_DHRE_RANGE                        0:0
#define AHCI_PORT_PXIE_0_DHRE_WOFFSET                      0
#define AHCI_PORT_PXIE_0_DHRE_DEFAULT                      (_MK_MASK_CONST(0x00000000)
#define AHCI_PORT_PXIE_0_DHRE_DEFAULT_MASK                 (_MK_MASK_CONST(0x1)
#define AHCI_PORT_PXIE_0_DHRE_SW_DEFAULT                   (_MK_MASK_CONST(0x00000000)
#define AHCI_PORT_PXIE_0_DHRE_SW_DEFAULT_MASK              (_MK_MASK_CONST(0x1)
#define AHCI_PORT_PXIE_0_DHRE_CLEAR                        _MK_ENUM_CONST(0x00000000)                                                       // RWI-V
#define AHCI_PORT_PXIE_0_DHRE_SET                          _MK_ENUM_CONST(0x00000001)                                                       // RW--V
#define AHCI_PORT_PXIE_0_PSE_SHIFT                          _MK_SHIFT_CONST(1)                                                              // RWIVF
#define AHCI_PORT_PXIE_0_PSE_FIELD                         (_MK_SHIFT_CONST(0x1) << AHCI_PORT_PXIE_0_PSE_SHIFT)
#define AHCI_PORT_PXIE_0_PSE_RANGE                         1:1
#define AHCI_PORT_PXIE_0_PSE_WOFFSET                       0
#define AHCI_PORT_PXIE_0_PSE_DEFAULT                       (_MK_MASK_CONST(0x00000000)
#define AHCI_PORT_PXIE_0_PSE_DEFAULT_MASK                  (_MK_MASK_CONST(0x1)
#define AHCI_PORT_PXIE_0_PSE_SW_DEFAULT                    (_MK_MASK_CONST(0x00000000)
#define AHCI_PORT_PXIE_0_PSE_SW_DEFAULT_MASK               (_MK_MASK_CONST(0x1)
#define AHCI_PORT_PXIE_0_PSE_CLEAR                         _MK_ENUM_CONST(0x00000000)                                                       // RWI-V
#define AHCI_PORT_PXIE_0_PSE_SET                           _MK_ENUM_CONST(0x00000001)                                                       // RW--V
#define AHCI_PORT_PXIE_0_DSE_SHIFT                          _MK_SHIFT_CONST(2)                                                              // RWIVF
#define AHCI_PORT_PXIE_0_DSE_FIELD                         (_MK_SHIFT_CONST(0x1) << AHCI_PORT_PXIE_0_DSE_SHIFT)
#define AHCI_PORT_PXIE_0_DSE_RANGE                         2:2
#define AHCI_PORT_PXIE_0_DSE_WOFFSET                       0
#define AHCI_PORT_PXIE_0_DSE_DEFAULT                       (_MK_MASK_CONST(0x00000000)
#define AHCI_PORT_PXIE_0_DSE_DEFAULT_MASK                  (_MK_MASK_CONST(0x1)
#define AHCI_PORT_PXIE_0_DSE_SW_DEFAULT                    (_MK_MASK_CONST(0x00000000)
#define AHCI_PORT_PXIE_0_DSE_SW_DEFAULT_MASK               (_MK_MASK_CONST(0x1)
#define AHCI_PORT_PXIE_0_DSE_SET                           _MK_ENUM_CONST(0x00000001)                                                       // RW--V
#define AHCI_PORT_PXIE_0_DSE_CLEAR                         _MK_ENUM_CONST(0x00000000)                                                       // RWI-V
#define AHCI_PORT_PXIE_0_SDBE_SHIFT                         _MK_SHIFT_CONST(3)                                                              // RWIVF
#define AHCI_PORT_PXIE_0_SDBE_FIELD                        (_MK_SHIFT_CONST(0x1) << AHCI_PORT_PXIE_0_SDBE_SHIFT)
#define AHCI_PORT_PXIE_0_SDBE_RANGE                        3:3
#define AHCI_PORT_PXIE_0_SDBE_WOFFSET                      0
#define AHCI_PORT_PXIE_0_SDBE_DEFAULT                      (_MK_MASK_CONST(0x00000000)
#define AHCI_PORT_PXIE_0_SDBE_DEFAULT_MASK                 (_MK_MASK_CONST(0x1)
#define AHCI_PORT_PXIE_0_SDBE_SW_DEFAULT                   (_MK_MASK_CONST(0x00000000)
#define AHCI_PORT_PXIE_0_SDBE_SW_DEFAULT_MASK              (_MK_MASK_CONST(0x1)
#define AHCI_PORT_PXIE_0_SDBE_CLEAR                        _MK_ENUM_CONST(0x00000000)                                                       // RWI-V
#define AHCI_PORT_PXIE_0_SDBE_SET                          _MK_ENUM_CONST(0x00000001)                                                       // RW--V
#define AHCI_PORT_PXIE_0_UFE_SHIFT                          _MK_SHIFT_CONST(4)                                                              // RWIVF
#define AHCI_PORT_PXIE_0_UFE_FIELD                         (_MK_SHIFT_CONST(0x1) << AHCI_PORT_PXIE_0_UFE_SHIFT)
#define AHCI_PORT_PXIE_0_UFE_RANGE                         4:4
#define AHCI_PORT_PXIE_0_UFE_WOFFSET                       0
#define AHCI_PORT_PXIE_0_UFE_DEFAULT                       (_MK_MASK_CONST(0x00000000)
#define AHCI_PORT_PXIE_0_UFE_DEFAULT_MASK                  (_MK_MASK_CONST(0x1)
#define AHCI_PORT_PXIE_0_UFE_SW_DEFAULT                    (_MK_MASK_CONST(0x00000000)
#define AHCI_PORT_PXIE_0_UFE_SW_DEFAULT_MASK               (_MK_MASK_CONST(0x1)
#define AHCI_PORT_PXIE_0_UFE_CLEAR                         _MK_ENUM_CONST(0x00000000)                                                       // RWI-V
#define AHCI_PORT_PXIE_0_UFE_SET                           _MK_ENUM_CONST(0x00000001)                                                       // RW--V
#define AHCI_PORT_PXIE_0_DPE_SHIFT                          _MK_SHIFT_CONST(5)                                                              // RWIVF
#define AHCI_PORT_PXIE_0_DPE_FIELD                         (_MK_SHIFT_CONST(0x1) << AHCI_PORT_PXIE_0_DPE_SHIFT)
#define AHCI_PORT_PXIE_0_DPE_RANGE                         5:5
#define AHCI_PORT_PXIE_0_DPE_WOFFSET                       0
#define AHCI_PORT_PXIE_0_DPE_DEFAULT                       (_MK_MASK_CONST(0x00000000)
#define AHCI_PORT_PXIE_0_DPE_DEFAULT_MASK                  (_MK_MASK_CONST(0x1)
#define AHCI_PORT_PXIE_0_DPE_SW_DEFAULT                    (_MK_MASK_CONST(0x00000000)
#define AHCI_PORT_PXIE_0_DPE_SW_DEFAULT_MASK               (_MK_MASK_CONST(0x1)
#define AHCI_PORT_PXIE_0_DPE_CLEAR                         _MK_ENUM_CONST(0x00000000)                                                       // RWI-V
#define AHCI_PORT_PXIE_0_DPE_SET                           _MK_ENUM_CONST(0x00000001)                                                       // RW--V
#define AHCI_PORT_PXIE_0_PCE_SHIFT                          _MK_SHIFT_CONST(6)                                                              // RWIVF
#define AHCI_PORT_PXIE_0_PCE_FIELD                         (_MK_SHIFT_CONST(0x1) << AHCI_PORT_PXIE_0_PCE_SHIFT)
#define AHCI_PORT_PXIE_0_PCE_RANGE                         6:6
#define AHCI_PORT_PXIE_0_PCE_WOFFSET                       0
#define AHCI_PORT_PXIE_0_PCE_DEFAULT                       (_MK_MASK_CONST(0x00000000)
#define AHCI_PORT_PXIE_0_PCE_DEFAULT_MASK                  (_MK_MASK_CONST(0x1)
#define AHCI_PORT_PXIE_0_PCE_SW_DEFAULT                    (_MK_MASK_CONST(0x00000000)
#define AHCI_PORT_PXIE_0_PCE_SW_DEFAULT_MASK               (_MK_MASK_CONST(0x1)
#define AHCI_PORT_PXIE_0_PCE_CLEAR                         _MK_ENUM_CONST(0x00000000)                                                       // RWI-V
#define AHCI_PORT_PXIE_0_PCE_SET                           _MK_ENUM_CONST(0x00000001)                                                       // RW--V
#define AHCI_PORT_PXIE_0_DMPE_SHIFT                         _MK_SHIFT_CONST(7)                                                              // C--VF
#define AHCI_PORT_PXIE_0_DMPE_FIELD                        (_MK_SHIFT_CONST(0x1) << AHCI_PORT_PXIE_0_DMPE_SHIFT)
#define AHCI_PORT_PXIE_0_DMPE_RANGE                        7:7
#define AHCI_PORT_PXIE_0_DMPE_WOFFSET                      0
#define AHCI_PORT_PXIE_0_DMPE_CLEAR                        _MK_ENUM_CONST(0x00000000)                                                       // C---V
#define AHCI_PORT_PXIE_0_DMPE_SET                          _MK_ENUM_CONST(0x00000001)                                                       // ----V
#define AHCI_PORT_PXIE_0_RSVD_SHIFT                         _MK_SHIFT_CONST(8)                                                              // C--VF
#define AHCI_PORT_PXIE_0_RSVD_FIELD                        (_MK_SHIFT_CONST(0x3fff) << AHCI_PORT_PXIE_0_RSVD_SHIFT)
#define AHCI_PORT_PXIE_0_RSVD_RANGE                        21:8
#define AHCI_PORT_PXIE_0_RSVD_WOFFSET                      0
#define AHCI_PORT_PXIE_0_RSVD_00                           _MK_ENUM_CONST(0x00000000)                                                       // C---V
#define AHCI_PORT_PXIE_0_PRCE_SHIFT                         _MK_SHIFT_CONST(22)                                                             // RWIVF
#define AHCI_PORT_PXIE_0_PRCE_FIELD                        (_MK_SHIFT_CONST(0x1) << AHCI_PORT_PXIE_0_PRCE_SHIFT)
#define AHCI_PORT_PXIE_0_PRCE_RANGE                        22:22
#define AHCI_PORT_PXIE_0_PRCE_WOFFSET                      0
#define AHCI_PORT_PXIE_0_PRCE_DEFAULT                      (_MK_MASK_CONST(0x00000000)
#define AHCI_PORT_PXIE_0_PRCE_DEFAULT_MASK                 (_MK_MASK_CONST(0x1)
#define AHCI_PORT_PXIE_0_PRCE_SW_DEFAULT                   (_MK_MASK_CONST(0x00000000)
#define AHCI_PORT_PXIE_0_PRCE_SW_DEFAULT_MASK              (_MK_MASK_CONST(0x1)
#define AHCI_PORT_PXIE_0_PRCE_CLEAR                        _MK_ENUM_CONST(0x00000000)                                                       // RWI-V
#define AHCI_PORT_PXIE_0_PRCE_SET                          _MK_ENUM_CONST(0x00000001)                                                       // RW--V
#define AHCI_PORT_PXIE_0_IPME_SHIFT                         _MK_SHIFT_CONST(23)                                                             // RWIVF
#define AHCI_PORT_PXIE_0_IPME_FIELD                        (_MK_SHIFT_CONST(0x1) << AHCI_PORT_PXIE_0_IPME_SHIFT)
#define AHCI_PORT_PXIE_0_IPME_RANGE                        23:23
#define AHCI_PORT_PXIE_0_IPME_WOFFSET                      0
#define AHCI_PORT_PXIE_0_IPME_DEFAULT                      (_MK_MASK_CONST(0x00000000)
#define AHCI_PORT_PXIE_0_IPME_DEFAULT_MASK                 (_MK_MASK_CONST(0x1)
#define AHCI_PORT_PXIE_0_IPME_SW_DEFAULT                   (_MK_MASK_CONST(0x00000000)
#define AHCI_PORT_PXIE_0_IPME_SW_DEFAULT_MASK              (_MK_MASK_CONST(0x1)
#define AHCI_PORT_PXIE_0_IPME_CLEAR                        _MK_ENUM_CONST(0x00000000)                                                       // RWI-V
#define AHCI_PORT_PXIE_0_IPME_SET                          _MK_ENUM_CONST(0x00000001)                                                       // RW--V
#define AHCI_PORT_PXIE_0_OFE_SHIFT                          _MK_SHIFT_CONST(24)                                                             // RWIVF
#define AHCI_PORT_PXIE_0_OFE_FIELD                         (_MK_SHIFT_CONST(0x1) << AHCI_PORT_PXIE_0_OFE_SHIFT)
#define AHCI_PORT_PXIE_0_OFE_RANGE                         24:24
#define AHCI_PORT_PXIE_0_OFE_WOFFSET                       0
#define AHCI_PORT_PXIE_0_OFE_DEFAULT                       (_MK_MASK_CONST(0x00000000)
#define AHCI_PORT_PXIE_0_OFE_DEFAULT_MASK                  (_MK_MASK_CONST(0x1)
#define AHCI_PORT_PXIE_0_OFE_SW_DEFAULT                    (_MK_MASK_CONST(0x00000000)
#define AHCI_PORT_PXIE_0_OFE_SW_DEFAULT_MASK               (_MK_MASK_CONST(0x1)
#define AHCI_PORT_PXIE_0_OFE_CLEAR                         _MK_ENUM_CONST(0x00000000)                                                       // RWI-V
#define AHCI_PORT_PXIE_0_OFE_SET                           _MK_ENUM_CONST(0x00000001)                                                       // RW--V
#define AHCI_PORT_PXIE_0_INFE_SHIFT                         _MK_SHIFT_CONST(26)                                                             // RWIVF
#define AHCI_PORT_PXIE_0_INFE_FIELD                        (_MK_SHIFT_CONST(0x1) << AHCI_PORT_PXIE_0_INFE_SHIFT)
#define AHCI_PORT_PXIE_0_INFE_RANGE                        26:26
#define AHCI_PORT_PXIE_0_INFE_WOFFSET                      0
#define AHCI_PORT_PXIE_0_INFE_DEFAULT                      (_MK_MASK_CONST(0x00000000)
#define AHCI_PORT_PXIE_0_INFE_DEFAULT_MASK                 (_MK_MASK_CONST(0x1)
#define AHCI_PORT_PXIE_0_INFE_SW_DEFAULT                   (_MK_MASK_CONST(0x00000000)
#define AHCI_PORT_PXIE_0_INFE_SW_DEFAULT_MASK              (_MK_MASK_CONST(0x1)
#define AHCI_PORT_PXIE_0_INFE_CLEAR                        _MK_ENUM_CONST(0x00000000)                                                       // RWI-V
#define AHCI_PORT_PXIE_0_INFE_SET                          _MK_ENUM_CONST(0x00000001)                                                       // RW--V
#define AHCI_PORT_PXIE_0_IFE_SHIFT                          _MK_SHIFT_CONST(27)                                                             // RWIVF
#define AHCI_PORT_PXIE_0_IFE_FIELD                         (_MK_SHIFT_CONST(0x1) << AHCI_PORT_PXIE_0_IFE_SHIFT)
#define AHCI_PORT_PXIE_0_IFE_RANGE                         27:27
#define AHCI_PORT_PXIE_0_IFE_WOFFSET                       0
#define AHCI_PORT_PXIE_0_IFE_DEFAULT                       (_MK_MASK_CONST(0x00000000)
#define AHCI_PORT_PXIE_0_IFE_DEFAULT_MASK                  (_MK_MASK_CONST(0x1)
#define AHCI_PORT_PXIE_0_IFE_SW_DEFAULT                    (_MK_MASK_CONST(0x00000000)
#define AHCI_PORT_PXIE_0_IFE_SW_DEFAULT_MASK               (_MK_MASK_CONST(0x1)
#define AHCI_PORT_PXIE_0_IFE_CLEAR                         _MK_ENUM_CONST(0x00000000)                                                       // RWI-V
#define AHCI_PORT_PXIE_0_IFE_SET                           _MK_ENUM_CONST(0x00000001)                                                       // RW--V
#define AHCI_PORT_PXIE_0_HBDE_SHIFT                         _MK_SHIFT_CONST(28)                                                             // RWIVF
#define AHCI_PORT_PXIE_0_HBDE_FIELD                        (_MK_SHIFT_CONST(0x1) << AHCI_PORT_PXIE_0_HBDE_SHIFT)
#define AHCI_PORT_PXIE_0_HBDE_RANGE                        28:28
#define AHCI_PORT_PXIE_0_HBDE_WOFFSET                      0
#define AHCI_PORT_PXIE_0_HBDE_DEFAULT                      (_MK_MASK_CONST(0x00000000)
#define AHCI_PORT_PXIE_0_HBDE_DEFAULT_MASK                 (_MK_MASK_CONST(0x1)
#define AHCI_PORT_PXIE_0_HBDE_SW_DEFAULT                   (_MK_MASK_CONST(0x00000000)
#define AHCI_PORT_PXIE_0_HBDE_SW_DEFAULT_MASK              (_MK_MASK_CONST(0x1)
#define AHCI_PORT_PXIE_0_HBDE_CLEAR                        _MK_ENUM_CONST(0x00000000)                                                       // RWI-V
#define AHCI_PORT_PXIE_0_HBDE_SET                          _MK_ENUM_CONST(0x00000001)                                                       // RW--V
#define AHCI_PORT_PXIE_0_HBFE_SHIFT                         _MK_SHIFT_CONST(29)                                                             // RWIVF
#define AHCI_PORT_PXIE_0_HBFE_FIELD                        (_MK_SHIFT_CONST(0x1) << AHCI_PORT_PXIE_0_HBFE_SHIFT)
#define AHCI_PORT_PXIE_0_HBFE_RANGE                        29:29
#define AHCI_PORT_PXIE_0_HBFE_WOFFSET                      0
#define AHCI_PORT_PXIE_0_HBFE_DEFAULT                      (_MK_MASK_CONST(0x00000000)
#define AHCI_PORT_PXIE_0_HBFE_DEFAULT_MASK                 (_MK_MASK_CONST(0x1)
#define AHCI_PORT_PXIE_0_HBFE_SW_DEFAULT                   (_MK_MASK_CONST(0x00000000)
#define AHCI_PORT_PXIE_0_HBFE_SW_DEFAULT_MASK              (_MK_MASK_CONST(0x1)
#define AHCI_PORT_PXIE_0_HBFE_CLEAR                        _MK_ENUM_CONST(0x00000000)                                                       // RWI-V
#define AHCI_PORT_PXIE_0_HBFE_SET                          _MK_ENUM_CONST(0x00000001)                                                       // RW--V
#define AHCI_PORT_PXIE_0_TFEE_SHIFT                         _MK_SHIFT_CONST(30)                                                             // RWIVF
#define AHCI_PORT_PXIE_0_TFEE_FIELD                        (_MK_SHIFT_CONST(0x1) << AHCI_PORT_PXIE_0_TFEE_SHIFT)
#define AHCI_PORT_PXIE_0_TFEE_RANGE                        30:30
#define AHCI_PORT_PXIE_0_TFEE_WOFFSET                      0
#define AHCI_PORT_PXIE_0_TFEE_DEFAULT                      (_MK_MASK_CONST(0x00000000)
#define AHCI_PORT_PXIE_0_TFEE_DEFAULT_MASK                 (_MK_MASK_CONST(0x1)
#define AHCI_PORT_PXIE_0_TFEE_SW_DEFAULT                   (_MK_MASK_CONST(0x00000000)
#define AHCI_PORT_PXIE_0_TFEE_SW_DEFAULT_MASK              (_MK_MASK_CONST(0x1)
#define AHCI_PORT_PXIE_0_TFEE_CLEAR                        _MK_ENUM_CONST(0x00000000)                                                       // RWI-V
#define AHCI_PORT_PXIE_0_TFEE_SET                          _MK_ENUM_CONST(0x00000001)                                                       // RW--V
#define AHCI_PORT_PXIE_0_CPDE_SHIFT                         _MK_SHIFT_CONST(31)                                                             // C-IVF
#define AHCI_PORT_PXIE_0_CPDE_FIELD                        (_MK_SHIFT_CONST(0x1) << AHCI_PORT_PXIE_0_CPDE_SHIFT)
#define AHCI_PORT_PXIE_0_CPDE_RANGE                        31:31
#define AHCI_PORT_PXIE_0_CPDE_WOFFSET                      0
#define AHCI_PORT_PXIE_0_CPDE_DEFAULT                      (_MK_MASK_CONST(0x00000000)
#define AHCI_PORT_PXIE_0_CPDE_DEFAULT_MASK                 (_MK_MASK_CONST(0x1)
#define AHCI_PORT_PXIE_0_CPDE_SW_DEFAULT                   (_MK_MASK_CONST(0x00000000)
#define AHCI_PORT_PXIE_0_CPDE_SW_DEFAULT_MASK              (_MK_MASK_CONST(0x1)
#define AHCI_PORT_PXIE_0_CPDE_CLEAR                        _MK_ENUM_CONST(0x00000000)                                                       // C-I-V
#define AHCI_PORT_PXIE_0_CPDE_SET                          _MK_ENUM_CONST(0x00000001)                                                       // ----V
// 
// 
//              Figure 9-XXX Port Interrupt Enable Register.
// 
// 
// .TITLE Port Command and Status
// .FIELD
// 
// 
// 31           24 23           16 15            8 7             0
// .-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-.
// |0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0| PORT_PXCMD
// `-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-'
// 
#define AHCI_PORT_PXCMD_0                                  0x00000118                                                                       // RW-4R
#define AHCI_PORT_PXCMD_0_SECURE                           0
#define AHCI_PORT_PXCMD_0_WORD_COUNT                       1
#define AHCI_PORT_PXCMD_0_RESET_VAL                        0x4
#define AHCI_PORT_PXCMD_0_RESET_MASK                       0xff83ff1f
#define AHCI_PORT_PXCMD_0_SW_DEFAULT_VAL                   0x4
#define AHCI_PORT_PXCMD_0_SW_DEFAULT_MASK                  0xff83ff1f
#define AHCI_PORT_PXCMD_0_READ_MASK                        0xffffff1f
#define AHCI_PORT_PXCMD_0_WRITE_MASK                       0xff82001b
#define AHCI_PORT_PXCMD_0_ST_SHIFT                          _MK_SHIFT_CONST(0)                                                              // RWIVF
#define AHCI_PORT_PXCMD_0_ST_FIELD                         (_MK_SHIFT_CONST(0x1) << AHCI_PORT_PXCMD_0_ST_SHIFT)
#define AHCI_PORT_PXCMD_0_ST_RANGE                         0:0
#define AHCI_PORT_PXCMD_0_ST_WOFFSET                       0
#define AHCI_PORT_PXCMD_0_ST_DEFAULT                       (_MK_MASK_CONST(0x00000000)
#define AHCI_PORT_PXCMD_0_ST_DEFAULT_MASK                  (_MK_MASK_CONST(0x1)
#define AHCI_PORT_PXCMD_0_ST_SW_DEFAULT                    (_MK_MASK_CONST(0x00000000)
#define AHCI_PORT_PXCMD_0_ST_SW_DEFAULT_MASK               (_MK_MASK_CONST(0x1)
#define AHCI_PORT_PXCMD_0_ST_CLEAR                         _MK_ENUM_CONST(0x00000000)                                                       // RWI-V
#define AHCI_PORT_PXCMD_0_ST_SET                           _MK_ENUM_CONST(0x00000001)                                                       // RW--V
#define AHCI_PORT_PXCMD_0_SUD_SHIFT                         _MK_SHIFT_CONST(1)                                                              // RWIVF
#define AHCI_PORT_PXCMD_0_SUD_FIELD                        (_MK_SHIFT_CONST(0x1) << AHCI_PORT_PXCMD_0_SUD_SHIFT)
#define AHCI_PORT_PXCMD_0_SUD_RANGE                        1:1
#define AHCI_PORT_PXCMD_0_SUD_WOFFSET                      0
#define AHCI_PORT_PXCMD_0_SUD_DEFAULT                      (_MK_MASK_CONST(0x00000000)
#define AHCI_PORT_PXCMD_0_SUD_DEFAULT_MASK                 (_MK_MASK_CONST(0x1)
#define AHCI_PORT_PXCMD_0_SUD_SW_DEFAULT                   (_MK_MASK_CONST(0x00000000)
#define AHCI_PORT_PXCMD_0_SUD_SW_DEFAULT_MASK              (_MK_MASK_CONST(0x1)
#define AHCI_PORT_PXCMD_0_SUD__NOPRDCHK                    _MK_ENUM_CONST(0x00000001)                                                       // ----V
#define AHCI_PORT_PXCMD_0_SUD_CLEAR                        _MK_ENUM_CONST(0x00000000)                                                       // RWI-V
#define AHCI_PORT_PXCMD_0_SUD_SET                          _MK_ENUM_CONST(0x00000001)                                                       // RW--V
#define AHCI_PORT_PXCMD_0_POD_SHIFT                         _MK_SHIFT_CONST(2)                                                              // R-IVF
#define AHCI_PORT_PXCMD_0_POD_FIELD                        (_MK_SHIFT_CONST(0x1) << AHCI_PORT_PXCMD_0_POD_SHIFT)
#define AHCI_PORT_PXCMD_0_POD_RANGE                        2:2
#define AHCI_PORT_PXCMD_0_POD_WOFFSET                      0
#define AHCI_PORT_PXCMD_0_POD_DEFAULT                      (_MK_MASK_CONST(0x00000001)
#define AHCI_PORT_PXCMD_0_POD_DEFAULT_MASK                 (_MK_MASK_CONST(0x1)
#define AHCI_PORT_PXCMD_0_POD_SW_DEFAULT                   (_MK_MASK_CONST(0x00000001)
#define AHCI_PORT_PXCMD_0_POD_SW_DEFAULT_MASK              (_MK_MASK_CONST(0x1)
#define AHCI_PORT_PXCMD_0_POD_CLEAR                        _MK_ENUM_CONST(0x00000000)                                                       // R---V
#define AHCI_PORT_PXCMD_0_POD_SET                          _MK_ENUM_CONST(0x00000001)                                                       // R-I-V
#define AHCI_PORT_PXCMD_0_CLO_SHIFT                         _MK_SHIFT_CONST(3)                                                              // RWIVF
#define AHCI_PORT_PXCMD_0_CLO_FIELD                        (_MK_SHIFT_CONST(0x1) << AHCI_PORT_PXCMD_0_CLO_SHIFT)
#define AHCI_PORT_PXCMD_0_CLO_RANGE                        3:3
#define AHCI_PORT_PXCMD_0_CLO_WOFFSET                      0
#define AHCI_PORT_PXCMD_0_CLO_DEFAULT                      (_MK_MASK_CONST(0x00000000)
#define AHCI_PORT_PXCMD_0_CLO_DEFAULT_MASK                 (_MK_MASK_CONST(0x1)
#define AHCI_PORT_PXCMD_0_CLO_SW_DEFAULT                   (_MK_MASK_CONST(0x00000000)
#define AHCI_PORT_PXCMD_0_CLO_SW_DEFAULT_MASK              (_MK_MASK_CONST(0x1)
#define AHCI_PORT_PXCMD_0_CLO_DISABLE                      _MK_ENUM_CONST(0x00000000)                                                       // R-I-V
#define AHCI_PORT_PXCMD_0_CLO_ENABLE                       _MK_ENUM_CONST(0x00000001)                                                       // -W--T
#define AHCI_PORT_PXCMD_0_FRE_SHIFT                         _MK_SHIFT_CONST(4)                                                              // RWIVF
#define AHCI_PORT_PXCMD_0_FRE_FIELD                        (_MK_SHIFT_CONST(0x1) << AHCI_PORT_PXCMD_0_FRE_SHIFT)
#define AHCI_PORT_PXCMD_0_FRE_RANGE                        4:4
#define AHCI_PORT_PXCMD_0_FRE_WOFFSET                      0
#define AHCI_PORT_PXCMD_0_FRE_DEFAULT                      (_MK_MASK_CONST(0x00000000)
#define AHCI_PORT_PXCMD_0_FRE_DEFAULT_MASK                 (_MK_MASK_CONST(0x1)
#define AHCI_PORT_PXCMD_0_FRE_SW_DEFAULT                   (_MK_MASK_CONST(0x00000000)
#define AHCI_PORT_PXCMD_0_FRE_SW_DEFAULT_MASK              (_MK_MASK_CONST(0x1)
#define AHCI_PORT_PXCMD_0_FRE_CLEAR                        _MK_ENUM_CONST(0x00000000)                                                       // RWI-V
#define AHCI_PORT_PXCMD_0_FRE_SET                          _MK_ENUM_CONST(0x00000001)                                                       // RW--V
#define AHCI_PORT_PXCMD_0_CCS_SHIFT                         _MK_SHIFT_CONST(8)                                                              // R-IVF
#define AHCI_PORT_PXCMD_0_CCS_FIELD                        (_MK_SHIFT_CONST(0x1f) << AHCI_PORT_PXCMD_0_CCS_SHIFT)
#define AHCI_PORT_PXCMD_0_CCS_RANGE                        12:8
#define AHCI_PORT_PXCMD_0_CCS_WOFFSET                      0
#define AHCI_PORT_PXCMD_0_CCS_DEFAULT                      (_MK_MASK_CONST(0x00000000)
#define AHCI_PORT_PXCMD_0_CCS_DEFAULT_MASK                 (_MK_MASK_CONST(0x1f)
#define AHCI_PORT_PXCMD_0_CCS_SW_DEFAULT                   (_MK_MASK_CONST(0x00000000)
#define AHCI_PORT_PXCMD_0_CCS_SW_DEFAULT_MASK              (_MK_MASK_CONST(0x1f)
#define AHCI_PORT_PXCMD_0_CCS__NOPRDCHK                    _MK_ENUM_CONST(0x00000001)                                                       // ----V
#define AHCI_PORT_PXCMD_0_CCS_00                           _MK_ENUM_CONST(0x00000000)                                                       // R-I-V
#define AHCI_PORT_PXCMD_0_CCS_16                           _MK_ENUM_CONST(0x0000000F)                                                       // R---V
#define AHCI_PORT_PXCMD_0_CCS_32                           _MK_ENUM_CONST(0x0000001F)                                                       // R---V
#define AHCI_PORT_PXCMD_0_MPSS_SHIFT                        _MK_SHIFT_CONST(13)                                                             // R-IVF
#define AHCI_PORT_PXCMD_0_MPSS_FIELD                       (_MK_SHIFT_CONST(0x1) << AHCI_PORT_PXCMD_0_MPSS_SHIFT)
#define AHCI_PORT_PXCMD_0_MPSS_RANGE                       13:13
#define AHCI_PORT_PXCMD_0_MPSS_WOFFSET                     0
#define AHCI_PORT_PXCMD_0_MPSS_DEFAULT                     (_MK_MASK_CONST(0x00000000)
#define AHCI_PORT_PXCMD_0_MPSS_DEFAULT_MASK                (_MK_MASK_CONST(0x1)
#define AHCI_PORT_PXCMD_0_MPSS_SW_DEFAULT                  (_MK_MASK_CONST(0x00000000)
#define AHCI_PORT_PXCMD_0_MPSS_SW_DEFAULT_MASK             (_MK_MASK_CONST(0x1)
#define AHCI_PORT_PXCMD_0_MPSS__NOPRDCHK                   _MK_ENUM_CONST(0x00000001)                                                       // ----V
#define AHCI_PORT_PXCMD_0_MPSS_CLOSED                      _MK_ENUM_CONST(0x00000000)                                                       // R-I-V
#define AHCI_PORT_PXCMD_0_MPSS_OPEN                        _MK_ENUM_CONST(0x00000001)                                                       // ----V
#define AHCI_PORT_PXCMD_0_FR_SHIFT                          _MK_SHIFT_CONST(14)                                                             // R-IVF
#define AHCI_PORT_PXCMD_0_FR_FIELD                         (_MK_SHIFT_CONST(0x1) << AHCI_PORT_PXCMD_0_FR_SHIFT)
#define AHCI_PORT_PXCMD_0_FR_RANGE                         14:14
#define AHCI_PORT_PXCMD_0_FR_WOFFSET                       0
#define AHCI_PORT_PXCMD_0_FR_DEFAULT                       (_MK_MASK_CONST(0x00000000)
#define AHCI_PORT_PXCMD_0_FR_DEFAULT_MASK                  (_MK_MASK_CONST(0x1)
#define AHCI_PORT_PXCMD_0_FR_SW_DEFAULT                    (_MK_MASK_CONST(0x00000000)
#define AHCI_PORT_PXCMD_0_FR_SW_DEFAULT_MASK               (_MK_MASK_CONST(0x1)
#define AHCI_PORT_PXCMD_0_FR__NOPRDCHK                     _MK_ENUM_CONST(0x00000001)                                                       // ----V
#define AHCI_PORT_PXCMD_0_FR_NOTRCVD                       _MK_ENUM_CONST(0x00000000)                                                       // R-I-V
#define AHCI_PORT_PXCMD_0_FR_RCVD                          _MK_ENUM_CONST(0x00000001)                                                       // R---V
#define AHCI_PORT_PXCMD_0_CR_SHIFT                          _MK_SHIFT_CONST(15)                                                             // R-IVF
#define AHCI_PORT_PXCMD_0_CR_FIELD                         (_MK_SHIFT_CONST(0x1) << AHCI_PORT_PXCMD_0_CR_SHIFT)
#define AHCI_PORT_PXCMD_0_CR_RANGE                         15:15
#define AHCI_PORT_PXCMD_0_CR_WOFFSET                       0
#define AHCI_PORT_PXCMD_0_CR_DEFAULT                       (_MK_MASK_CONST(0x00000000)
#define AHCI_PORT_PXCMD_0_CR_DEFAULT_MASK                  (_MK_MASK_CONST(0x1)
#define AHCI_PORT_PXCMD_0_CR_SW_DEFAULT                    (_MK_MASK_CONST(0x00000000)
#define AHCI_PORT_PXCMD_0_CR_SW_DEFAULT_MASK               (_MK_MASK_CONST(0x1)
#define AHCI_PORT_PXCMD_0_CR__NOPRDCHK                     _MK_ENUM_CONST(0x00000001)                                                       // ----V
#define AHCI_PORT_PXCMD_0_CR_NOTRCVD                       _MK_ENUM_CONST(0x00000000)                                                       // R-I-V
#define AHCI_PORT_PXCMD_0_CR_RCVD                          _MK_ENUM_CONST(0x00000001)                                                       // R---V
#define AHCI_PORT_PXCMD_0_CPS_SHIFT                         _MK_SHIFT_CONST(16)                                                             // R-IVF
#define AHCI_PORT_PXCMD_0_CPS_FIELD                        (_MK_SHIFT_CONST(0x1) << AHCI_PORT_PXCMD_0_CPS_SHIFT)
#define AHCI_PORT_PXCMD_0_CPS_RANGE                        16:16
#define AHCI_PORT_PXCMD_0_CPS_WOFFSET                      0
#define AHCI_PORT_PXCMD_0_CPS_DEFAULT                      (_MK_MASK_CONST(0x00000000)
#define AHCI_PORT_PXCMD_0_CPS_DEFAULT_MASK                 (_MK_MASK_CONST(0x1)
#define AHCI_PORT_PXCMD_0_CPS_SW_DEFAULT                   (_MK_MASK_CONST(0x00000000)
#define AHCI_PORT_PXCMD_0_CPS_SW_DEFAULT_MASK              (_MK_MASK_CONST(0x1)
#define AHCI_PORT_PXCMD_0_CPS__NOPRDCHK                    _MK_ENUM_CONST(0x00000001)                                                       // ----V
#define AHCI_PORT_PXCMD_0_CPS_NOTDETECT                    _MK_ENUM_CONST(0x00000000)                                                       // R-I-V
#define AHCI_PORT_PXCMD_0_CPS_DETECT                       _MK_ENUM_CONST(0x00000001)                                                       // R---V
#define AHCI_PORT_PXCMD_0_PMA_SHIFT                         _MK_SHIFT_CONST(17)                                                             // RWIVF
#define AHCI_PORT_PXCMD_0_PMA_FIELD                        (_MK_SHIFT_CONST(0x1) << AHCI_PORT_PXCMD_0_PMA_SHIFT)
#define AHCI_PORT_PXCMD_0_PMA_RANGE                        17:17
#define AHCI_PORT_PXCMD_0_PMA_WOFFSET                      0
#define AHCI_PORT_PXCMD_0_PMA_DEFAULT                      (_MK_MASK_CONST(0x00000000)
#define AHCI_PORT_PXCMD_0_PMA_DEFAULT_MASK                 (_MK_MASK_CONST(0x1)
#define AHCI_PORT_PXCMD_0_PMA_SW_DEFAULT                   (_MK_MASK_CONST(0x00000000)
#define AHCI_PORT_PXCMD_0_PMA_SW_DEFAULT_MASK              (_MK_MASK_CONST(0x1)
#define AHCI_PORT_PXCMD_0_PMA_FALSE                        _MK_ENUM_CONST(0x00000000)                                                       // RWI-V
#define AHCI_PORT_PXCMD_0_PMA_TRUE                         _MK_ENUM_CONST(0x00000001)                                                       // RW--V
#define AHCI_PORT_PXCMD_0_HPCP_SHIFT                        _MK_SHIFT_CONST(18)                                                             // R-WVF
#define AHCI_PORT_PXCMD_0_HPCP_FIELD                       (_MK_SHIFT_CONST(0x1) << AHCI_PORT_PXCMD_0_HPCP_SHIFT)
#define AHCI_PORT_PXCMD_0_HPCP_RANGE                       18:18
#define AHCI_PORT_PXCMD_0_HPCP_WOFFSET                     0
#define AHCI_PORT_PXCMD_0_HPCP_DEFAULT                     (_MK_MASK_CONST(0x00000001)
#define AHCI_PORT_PXCMD_0_HPCP_DEFAULT_MASK                (_MK_MASK_CONST(0x1)
#define AHCI_PORT_PXCMD_0_HPCP_SW_DEFAULT                  (_MK_MASK_CONST(0x00000001)
#define AHCI_PORT_PXCMD_0_HPCP_SW_DEFAULT_MASK             (_MK_MASK_CONST(0x1)
#define AHCI_PORT_PXCMD_0_HPCP__NOPRDCHK                   _MK_ENUM_CONST(0x00000001)                                                       // ----V
#define AHCI_PORT_PXCMD_0_HPCP_FALSE                       _MK_ENUM_CONST(0x00000000)                                                       // R---V
#define AHCI_PORT_PXCMD_0_HPCP_TRUE                        _MK_ENUM_CONST(0x00000001)                                                       // R-W-V
#define AHCI_PORT_PXCMD_0_MPSP_SHIFT                        _MK_SHIFT_CONST(19)                                                             // C--VF
#define AHCI_PORT_PXCMD_0_MPSP_FIELD                       (_MK_SHIFT_CONST(0x1) << AHCI_PORT_PXCMD_0_MPSP_SHIFT)
#define AHCI_PORT_PXCMD_0_MPSP_RANGE                       19:19
#define AHCI_PORT_PXCMD_0_MPSP_WOFFSET                     0
#define AHCI_PORT_PXCMD_0_MPSP__NOPRDCHK                   _MK_ENUM_CONST(0x00000001)                                                       // ----V
#define AHCI_PORT_PXCMD_0_MPSP_FALSE                       _MK_ENUM_CONST(0x00000000)                                                       // C---V
#define AHCI_PORT_PXCMD_0_MPSP_TRUE                        _MK_ENUM_CONST(0x00000001)                                                       // ----V
#define AHCI_PORT_PXCMD_0_CPD_SHIFT                         _MK_SHIFT_CONST(20)                                                             // R-WVF
#define AHCI_PORT_PXCMD_0_CPD_FIELD                        (_MK_SHIFT_CONST(0x1) << AHCI_PORT_PXCMD_0_CPD_SHIFT)
#define AHCI_PORT_PXCMD_0_CPD_RANGE                        20:20
#define AHCI_PORT_PXCMD_0_CPD_WOFFSET                      0
#define AHCI_PORT_PXCMD_0_CPD_DEFAULT                      (_MK_MASK_CONST(0x00000000)
#define AHCI_PORT_PXCMD_0_CPD_DEFAULT_MASK                 (_MK_MASK_CONST(0x1)
#define AHCI_PORT_PXCMD_0_CPD_SW_DEFAULT                   (_MK_MASK_CONST(0x00000000)
#define AHCI_PORT_PXCMD_0_CPD_SW_DEFAULT_MASK              (_MK_MASK_CONST(0x1)
#define AHCI_PORT_PXCMD_0_CPD__NOPRDCHK                    _MK_ENUM_CONST(0x00000001)                                                       // ----V
#define AHCI_PORT_PXCMD_0_CPD_NOTSUPPORTED                 _MK_ENUM_CONST(0x00000000)                                                       // R-W-V
#define AHCI_PORT_PXCMD_0_CPD_SUPPORTED                    _MK_ENUM_CONST(0x00000001)                                                       // R---V
#define AHCI_PORT_PXCMD_0_ESP_SHIFT                         _MK_SHIFT_CONST(21)                                                             // R-WVF
#define AHCI_PORT_PXCMD_0_ESP_FIELD                        (_MK_SHIFT_CONST(0x1) << AHCI_PORT_PXCMD_0_ESP_SHIFT)
#define AHCI_PORT_PXCMD_0_ESP_RANGE                        21:21
#define AHCI_PORT_PXCMD_0_ESP_WOFFSET                      0
#define AHCI_PORT_PXCMD_0_ESP_DEFAULT                      (_MK_MASK_CONST(0x00000000)
#define AHCI_PORT_PXCMD_0_ESP_DEFAULT_MASK                 (_MK_MASK_CONST(0x1)
#define AHCI_PORT_PXCMD_0_ESP_SW_DEFAULT                   (_MK_MASK_CONST(0x00000000)
#define AHCI_PORT_PXCMD_0_ESP_SW_DEFAULT_MASK              (_MK_MASK_CONST(0x1)
#define AHCI_PORT_PXCMD_0_ESP__NOPRDCHK                    _MK_ENUM_CONST(0x00000001)                                                       // ----V
#define AHCI_PORT_PXCMD_0_ESP_NOTSUPPORTED                 _MK_ENUM_CONST(0x00000000)                                                       // R-W-V
#define AHCI_PORT_PXCMD_0_ESP_SUPPORTED                    _MK_ENUM_CONST(0x00000001)                                                       // R---V
#define AHCI_PORT_PXCMD_0_FBSCP_SHIFT                       _MK_SHIFT_CONST(22)                                                             // R-WVF
#define AHCI_PORT_PXCMD_0_FBSCP_FIELD                      (_MK_SHIFT_CONST(0x1) << AHCI_PORT_PXCMD_0_FBSCP_SHIFT)
#define AHCI_PORT_PXCMD_0_FBSCP_RANGE                      22:22
#define AHCI_PORT_PXCMD_0_FBSCP_WOFFSET                    0
#define AHCI_PORT_PXCMD_0_FBSCP_DEFAULT                    (_MK_MASK_CONST(0x00000000)
#define AHCI_PORT_PXCMD_0_FBSCP_DEFAULT_MASK               (_MK_MASK_CONST(0x1)
#define AHCI_PORT_PXCMD_0_FBSCP_SW_DEFAULT                 (_MK_MASK_CONST(0x00000000)
#define AHCI_PORT_PXCMD_0_FBSCP_SW_DEFAULT_MASK            (_MK_MASK_CONST(0x1)
#define AHCI_PORT_PXCMD_0_FBSCP_TRUE                       _MK_ENUM_CONST(0x00000001)                                                       // R---V
#define AHCI_PORT_PXCMD_0_FBSCP_FALSE                      _MK_ENUM_CONST(0x00000000)                                                       // R-W-V
#define AHCI_PORT_PXCMD_0_APSTE_SHIFT                       _MK_SHIFT_CONST(23)                                                             // RWIVF
#define AHCI_PORT_PXCMD_0_APSTE_FIELD                      (_MK_SHIFT_CONST(0x1) << AHCI_PORT_PXCMD_0_APSTE_SHIFT)
#define AHCI_PORT_PXCMD_0_APSTE_RANGE                      23:23
#define AHCI_PORT_PXCMD_0_APSTE_WOFFSET                    0
#define AHCI_PORT_PXCMD_0_APSTE_DEFAULT                    (_MK_MASK_CONST(0x00000000)
#define AHCI_PORT_PXCMD_0_APSTE_DEFAULT_MASK               (_MK_MASK_CONST(0x1)
#define AHCI_PORT_PXCMD_0_APSTE_SW_DEFAULT                 (_MK_MASK_CONST(0x00000000)
#define AHCI_PORT_PXCMD_0_APSTE_SW_DEFAULT_MASK            (_MK_MASK_CONST(0x1)
#define AHCI_PORT_PXCMD_0_APSTE_TRUE                       _MK_ENUM_CONST(0x00000001)                                                       // RW--V
#define AHCI_PORT_PXCMD_0_APSTE_FALSE                      _MK_ENUM_CONST(0x00000000)                                                       // RWI-V
#define AHCI_PORT_PXCMD_0_ATAPI_SHIFT                       _MK_SHIFT_CONST(24)                                                             // RWIVF
#define AHCI_PORT_PXCMD_0_ATAPI_FIELD                      (_MK_SHIFT_CONST(0x1) << AHCI_PORT_PXCMD_0_ATAPI_SHIFT)
#define AHCI_PORT_PXCMD_0_ATAPI_RANGE                      24:24
#define AHCI_PORT_PXCMD_0_ATAPI_WOFFSET                    0
#define AHCI_PORT_PXCMD_0_ATAPI_DEFAULT                    (_MK_MASK_CONST(0x00000000)
#define AHCI_PORT_PXCMD_0_ATAPI_DEFAULT_MASK               (_MK_MASK_CONST(0x1)
#define AHCI_PORT_PXCMD_0_ATAPI_SW_DEFAULT                 (_MK_MASK_CONST(0x00000000)
#define AHCI_PORT_PXCMD_0_ATAPI_SW_DEFAULT_MASK            (_MK_MASK_CONST(0x1)
#define AHCI_PORT_PXCMD_0_ATAPI_DEVICE_NOTPRSNT            _MK_ENUM_CONST(0x00000000)                                                       // RWI-V
#define AHCI_PORT_PXCMD_0_ATAPI_DEVICE_PRSNT               _MK_ENUM_CONST(0x00000001)                                                       // RW--V
#define AHCI_PORT_PXCMD_0_DLAE_SHIFT                        _MK_SHIFT_CONST(25)                                                             // RWIVF
#define AHCI_PORT_PXCMD_0_DLAE_FIELD                       (_MK_SHIFT_CONST(0x1) << AHCI_PORT_PXCMD_0_DLAE_SHIFT)
#define AHCI_PORT_PXCMD_0_DLAE_RANGE                       25:25
#define AHCI_PORT_PXCMD_0_DLAE_WOFFSET                     0
#define AHCI_PORT_PXCMD_0_DLAE_DEFAULT                     (_MK_MASK_CONST(0x00000000)
#define AHCI_PORT_PXCMD_0_DLAE_DEFAULT_MASK                (_MK_MASK_CONST(0x1)
#define AHCI_PORT_PXCMD_0_DLAE_SW_DEFAULT                  (_MK_MASK_CONST(0x00000000)
#define AHCI_PORT_PXCMD_0_DLAE_SW_DEFAULT_MASK             (_MK_MASK_CONST(0x1)
#define AHCI_PORT_PXCMD_0_DLAE_DRV_LED_ALWYS               _MK_ENUM_CONST(0x00000001)                                                       // RW--V
#define AHCI_PORT_PXCMD_0_DLAE_DRV_LED_CMDS                _MK_ENUM_CONST(0x00000000)                                                       // RWI-V
#define AHCI_PORT_PXCMD_0_ALPE_SHIFT                        _MK_SHIFT_CONST(26)                                                             // RWIVF
#define AHCI_PORT_PXCMD_0_ALPE_FIELD                       (_MK_SHIFT_CONST(0x1) << AHCI_PORT_PXCMD_0_ALPE_SHIFT)
#define AHCI_PORT_PXCMD_0_ALPE_RANGE                       26:26
#define AHCI_PORT_PXCMD_0_ALPE_WOFFSET                     0
#define AHCI_PORT_PXCMD_0_ALPE_DEFAULT                     (_MK_MASK_CONST(0x00000000)
#define AHCI_PORT_PXCMD_0_ALPE_DEFAULT_MASK                (_MK_MASK_CONST(0x1)
#define AHCI_PORT_PXCMD_0_ALPE_SW_DEFAULT                  (_MK_MASK_CONST(0x00000000)
#define AHCI_PORT_PXCMD_0_ALPE_SW_DEFAULT_MASK             (_MK_MASK_CONST(0x1)
#define AHCI_PORT_PXCMD_0_ALPE_TRUE                        _MK_ENUM_CONST(0x00000001)                                                       // RW--V
#define AHCI_PORT_PXCMD_0_ALPE_FALSE                       _MK_ENUM_CONST(0x00000000)                                                       // RWI-V
#define AHCI_PORT_PXCMD_0_ASP_SHIFT                         _MK_SHIFT_CONST(27)                                                             // RWIVF
#define AHCI_PORT_PXCMD_0_ASP_FIELD                        (_MK_SHIFT_CONST(0x1) << AHCI_PORT_PXCMD_0_ASP_SHIFT)
#define AHCI_PORT_PXCMD_0_ASP_RANGE                        27:27
#define AHCI_PORT_PXCMD_0_ASP_WOFFSET                      0
#define AHCI_PORT_PXCMD_0_ASP_DEFAULT                      (_MK_MASK_CONST(0x00000000)
#define AHCI_PORT_PXCMD_0_ASP_DEFAULT_MASK                 (_MK_MASK_CONST(0x1)
#define AHCI_PORT_PXCMD_0_ASP_SW_DEFAULT                   (_MK_MASK_CONST(0x00000000)
#define AHCI_PORT_PXCMD_0_ASP_SW_DEFAULT_MASK              (_MK_MASK_CONST(0x1)
#define AHCI_PORT_PXCMD_0_ASP_DISABLE                      _MK_ENUM_CONST(0x00000000)                                                       // RWI-V
#define AHCI_PORT_PXCMD_0_ASP_ENABLE                       _MK_ENUM_CONST(0x00000001)                                                       // RW--V
#define AHCI_PORT_PXCMD_0_ICC_SHIFT                         _MK_SHIFT_CONST(28)                                                             // RWIVF
#define AHCI_PORT_PXCMD_0_ICC_FIELD                        (_MK_SHIFT_CONST(0xf) << AHCI_PORT_PXCMD_0_ICC_SHIFT)
#define AHCI_PORT_PXCMD_0_ICC_RANGE                        31:28
#define AHCI_PORT_PXCMD_0_ICC_WOFFSET                      0
#define AHCI_PORT_PXCMD_0_ICC_DEFAULT                      (_MK_MASK_CONST(0x00000000)
#define AHCI_PORT_PXCMD_0_ICC_DEFAULT_MASK                 (_MK_MASK_CONST(0xf)
#define AHCI_PORT_PXCMD_0_ICC_SW_DEFAULT                   (_MK_MASK_CONST(0x00000000)
#define AHCI_PORT_PXCMD_0_ICC_SW_DEFAULT_MASK              (_MK_MASK_CONST(0xf)
#define AHCI_PORT_PXCMD_0_ICC_IDLE                         _MK_ENUM_CONST(0x00000000)                                                       // RWI-V
#define AHCI_PORT_PXCMD_0_ICC_NO_OP                        _MK_ENUM_CONST(0x00000000)                                                       // RW--V
#define AHCI_PORT_PXCMD_0_ICC_ACTIVE                       _MK_ENUM_CONST(0x00000001)                                                       // RW--V
#define AHCI_PORT_PXCMD_0_ICC_PARTIAL                      _MK_ENUM_CONST(0x00000002)                                                       // RW--V
#define AHCI_PORT_PXCMD_0_ICC_SLUMBER                      _MK_ENUM_CONST(0x00000006)                                                       // RW--V
#define AHCI_PORT_PXCMD_0_ICC_DEVSLEEP                     _MK_ENUM_CONST(0x00000008)                                                       // RW--V
// 
// 
//              Figure 9-XXX Port Command and Status Register.
// 
// 
// .TITLE Port Task File Data
// .FIELD
// .PRIVATE
// TODO: Describe Error field more and add macros for extended error capabilities.
// .PUBLIC
// 
// 31           24 23           16 15            8 7             0
// .-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-.
// |0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0| PORT_PXTFD
// `-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-'
// 
#define AHCI_PORT_PXTFD_0                                  0x00000120                                                                       // RW-4R
#define AHCI_PORT_PXTFD_0_SECURE                           0
#define AHCI_PORT_PXTFD_0_WORD_COUNT                       1
#define AHCI_PORT_PXTFD_0_RESET_VAL                        0x7f
#define AHCI_PORT_PXTFD_0_RESET_MASK                       0xffff
#define AHCI_PORT_PXTFD_0_SW_DEFAULT_VAL                   0x7f
#define AHCI_PORT_PXTFD_0_SW_DEFAULT_MASK                  0xffff
#define AHCI_PORT_PXTFD_0_READ_MASK                        0xffffffff
#define AHCI_PORT_PXTFD_0_WRITE_MASK                       0x0
#define AHCI_PORT_PXTFD_0_STS_ERR_SHIFT                     _MK_SHIFT_CONST(0)                                                              // R-IVF
#define AHCI_PORT_PXTFD_0_STS_ERR_FIELD                    (_MK_SHIFT_CONST(0x1) << AHCI_PORT_PXTFD_0_STS_ERR_SHIFT)
#define AHCI_PORT_PXTFD_0_STS_ERR_RANGE                    0:0
#define AHCI_PORT_PXTFD_0_STS_ERR_WOFFSET                  0
#define AHCI_PORT_PXTFD_0_STS_ERR_DEFAULT                  (_MK_MASK_CONST(0x00000001)
#define AHCI_PORT_PXTFD_0_STS_ERR_DEFAULT_MASK             (_MK_MASK_CONST(0x1)
#define AHCI_PORT_PXTFD_0_STS_ERR_SW_DEFAULT               (_MK_MASK_CONST(0x00000001)
#define AHCI_PORT_PXTFD_0_STS_ERR_SW_DEFAULT_MASK          (_MK_MASK_CONST(0x1)
#define AHCI_PORT_PXTFD_0_STS_ERR__NOPRDCHK                _MK_ENUM_CONST(0x00000001)                                                       // ----V
#define AHCI_PORT_PXTFD_0_STS_ERR_CLEAR                    _MK_ENUM_CONST(0x00000000)                                                       // R---V
#define AHCI_PORT_PXTFD_0_STS_ERR_SET                      _MK_ENUM_CONST(0x00000001)                                                       // R-I-V
#define AHCI_PORT_PXTFD_0_STS_2_1_SHIFT                     _MK_SHIFT_CONST(1)                                                              // R-IVF
#define AHCI_PORT_PXTFD_0_STS_2_1_FIELD                    (_MK_SHIFT_CONST(0x3) << AHCI_PORT_PXTFD_0_STS_2_1_SHIFT)
#define AHCI_PORT_PXTFD_0_STS_2_1_RANGE                    2:1
#define AHCI_PORT_PXTFD_0_STS_2_1_WOFFSET                  0
#define AHCI_PORT_PXTFD_0_STS_2_1_DEFAULT                  (_MK_MASK_CONST(0x00000003)
#define AHCI_PORT_PXTFD_0_STS_2_1_DEFAULT_MASK             (_MK_MASK_CONST(0x3)
#define AHCI_PORT_PXTFD_0_STS_2_1_SW_DEFAULT               (_MK_MASK_CONST(0x00000003)
#define AHCI_PORT_PXTFD_0_STS_2_1_SW_DEFAULT_MASK          (_MK_MASK_CONST(0x3)
#define AHCI_PORT_PXTFD_0_STS_2_1__NOPRDCHK                _MK_ENUM_CONST(0x00000001)                                                       // ----V
#define AHCI_PORT_PXTFD_0_STS_2_1_INIT                     _MK_ENUM_CONST(0x00000003)                                                       // R-I-V
#define AHCI_PORT_PXTFD_0_STS_DRQ_SHIFT                     _MK_SHIFT_CONST(3)                                                              // R-IVF
#define AHCI_PORT_PXTFD_0_STS_DRQ_FIELD                    (_MK_SHIFT_CONST(0x1) << AHCI_PORT_PXTFD_0_STS_DRQ_SHIFT)
#define AHCI_PORT_PXTFD_0_STS_DRQ_RANGE                    3:3
#define AHCI_PORT_PXTFD_0_STS_DRQ_WOFFSET                  0
#define AHCI_PORT_PXTFD_0_STS_DRQ_DEFAULT                  (_MK_MASK_CONST(0x00000001)
#define AHCI_PORT_PXTFD_0_STS_DRQ_DEFAULT_MASK             (_MK_MASK_CONST(0x1)
#define AHCI_PORT_PXTFD_0_STS_DRQ_SW_DEFAULT               (_MK_MASK_CONST(0x00000001)
#define AHCI_PORT_PXTFD_0_STS_DRQ_SW_DEFAULT_MASK          (_MK_MASK_CONST(0x1)
#define AHCI_PORT_PXTFD_0_STS_DRQ__NOPRDCHK                _MK_ENUM_CONST(0x00000001)                                                       // ----V
#define AHCI_PORT_PXTFD_0_STS_DRQ_CLEAR                    _MK_ENUM_CONST(0x00000000)                                                       // R---V
#define AHCI_PORT_PXTFD_0_STS_DRQ_SET                      _MK_ENUM_CONST(0x00000001)                                                       // R-I-V
#define AHCI_PORT_PXTFD_0_STS_CS_SHIFT                      _MK_SHIFT_CONST(4)                                                              // R-IVF
#define AHCI_PORT_PXTFD_0_STS_CS_FIELD                     (_MK_SHIFT_CONST(0x1) << AHCI_PORT_PXTFD_0_STS_CS_SHIFT)
#define AHCI_PORT_PXTFD_0_STS_CS_RANGE                     4:4
#define AHCI_PORT_PXTFD_0_STS_CS_WOFFSET                   0
#define AHCI_PORT_PXTFD_0_STS_CS_DEFAULT                   (_MK_MASK_CONST(0x00000001)
#define AHCI_PORT_PXTFD_0_STS_CS_DEFAULT_MASK              (_MK_MASK_CONST(0x1)
#define AHCI_PORT_PXTFD_0_STS_CS_SW_DEFAULT                (_MK_MASK_CONST(0x00000001)
#define AHCI_PORT_PXTFD_0_STS_CS_SW_DEFAULT_MASK           (_MK_MASK_CONST(0x1)
#define AHCI_PORT_PXTFD_0_STS_CS__NOPRDCHK                 _MK_ENUM_CONST(0x00000001)                                                       // ----V
#define AHCI_PORT_PXTFD_0_STS_CS_CLEAR                     _MK_ENUM_CONST(0x00000000)                                                       // R---V
#define AHCI_PORT_PXTFD_0_STS_CS_SET                       _MK_ENUM_CONST(0x00000001)                                                       // R-I-V
#define AHCI_PORT_PXTFD_0_STS_DF_SHIFT                      _MK_SHIFT_CONST(5)                                                              // R-IVF
#define AHCI_PORT_PXTFD_0_STS_DF_FIELD                     (_MK_SHIFT_CONST(0x1) << AHCI_PORT_PXTFD_0_STS_DF_SHIFT)
#define AHCI_PORT_PXTFD_0_STS_DF_RANGE                     5:5
#define AHCI_PORT_PXTFD_0_STS_DF_WOFFSET                   0
#define AHCI_PORT_PXTFD_0_STS_DF_DEFAULT                   (_MK_MASK_CONST(0x00000001)
#define AHCI_PORT_PXTFD_0_STS_DF_DEFAULT_MASK              (_MK_MASK_CONST(0x1)
#define AHCI_PORT_PXTFD_0_STS_DF_SW_DEFAULT                (_MK_MASK_CONST(0x00000001)
#define AHCI_PORT_PXTFD_0_STS_DF_SW_DEFAULT_MASK           (_MK_MASK_CONST(0x1)
#define AHCI_PORT_PXTFD_0_STS_DF__NOPRDCHK                 _MK_ENUM_CONST(0x00000001)                                                       // ----V
#define AHCI_PORT_PXTFD_0_STS_DF_CLEAR                     _MK_ENUM_CONST(0x00000000)                                                       // R---V
#define AHCI_PORT_PXTFD_0_STS_DF_SET                       _MK_ENUM_CONST(0x00000001)                                                       // R-I-V
#define AHCI_PORT_PXTFD_0_STS_DRDY_SHIFT                    _MK_SHIFT_CONST(6)                                                              // R-IVF
#define AHCI_PORT_PXTFD_0_STS_DRDY_FIELD                   (_MK_SHIFT_CONST(0x1) << AHCI_PORT_PXTFD_0_STS_DRDY_SHIFT)
#define AHCI_PORT_PXTFD_0_STS_DRDY_RANGE                   6:6
#define AHCI_PORT_PXTFD_0_STS_DRDY_WOFFSET                 0
#define AHCI_PORT_PXTFD_0_STS_DRDY_DEFAULT                 (_MK_MASK_CONST(0x00000001)
#define AHCI_PORT_PXTFD_0_STS_DRDY_DEFAULT_MASK            (_MK_MASK_CONST(0x1)
#define AHCI_PORT_PXTFD_0_STS_DRDY_SW_DEFAULT              (_MK_MASK_CONST(0x00000001)
#define AHCI_PORT_PXTFD_0_STS_DRDY_SW_DEFAULT_MASK         (_MK_MASK_CONST(0x1)
#define AHCI_PORT_PXTFD_0_STS_DRDY__NOPRDCHK               _MK_ENUM_CONST(0x00000001)                                                       // ----V
#define AHCI_PORT_PXTFD_0_STS_DRDY_CLEAR                   _MK_ENUM_CONST(0x00000000)                                                       // R---V
#define AHCI_PORT_PXTFD_0_STS_DRDY_SET                     _MK_ENUM_CONST(0x00000001)                                                       // R-I-V
#define AHCI_PORT_PXTFD_0_STS_BSY_SHIFT                     _MK_SHIFT_CONST(7)                                                              // R-IVF
#define AHCI_PORT_PXTFD_0_STS_BSY_FIELD                    (_MK_SHIFT_CONST(0x1) << AHCI_PORT_PXTFD_0_STS_BSY_SHIFT)
#define AHCI_PORT_PXTFD_0_STS_BSY_RANGE                    7:7
#define AHCI_PORT_PXTFD_0_STS_BSY_WOFFSET                  0
#define AHCI_PORT_PXTFD_0_STS_BSY_DEFAULT                  (_MK_MASK_CONST(0x00000000)
#define AHCI_PORT_PXTFD_0_STS_BSY_DEFAULT_MASK             (_MK_MASK_CONST(0x1)
#define AHCI_PORT_PXTFD_0_STS_BSY_SW_DEFAULT               (_MK_MASK_CONST(0x00000000)
#define AHCI_PORT_PXTFD_0_STS_BSY_SW_DEFAULT_MASK          (_MK_MASK_CONST(0x1)
#define AHCI_PORT_PXTFD_0_STS_BSY__NOPRDCHK                _MK_ENUM_CONST(0x00000001)                                                       // ----V
#define AHCI_PORT_PXTFD_0_STS_BSY_CLEAR                    _MK_ENUM_CONST(0x00000000)                                                       // R-I-V
#define AHCI_PORT_PXTFD_0_STS_BSY_SET                      _MK_ENUM_CONST(0x00000001)                                                       // R---V
#define AHCI_PORT_PXTFD_0_ERR_SHIFT                         _MK_SHIFT_CONST(8)                                                              // R-IVF
#define AHCI_PORT_PXTFD_0_ERR_FIELD                        (_MK_SHIFT_CONST(0xff) << AHCI_PORT_PXTFD_0_ERR_SHIFT)
#define AHCI_PORT_PXTFD_0_ERR_RANGE                        15:8
#define AHCI_PORT_PXTFD_0_ERR_WOFFSET                      0
#define AHCI_PORT_PXTFD_0_ERR_DEFAULT                      (_MK_MASK_CONST(0x00000000)
#define AHCI_PORT_PXTFD_0_ERR_DEFAULT_MASK                 (_MK_MASK_CONST(0xff)
#define AHCI_PORT_PXTFD_0_ERR_SW_DEFAULT                   (_MK_MASK_CONST(0x00000000)
#define AHCI_PORT_PXTFD_0_ERR_SW_DEFAULT_MASK              (_MK_MASK_CONST(0xff)
#define AHCI_PORT_PXTFD_0_ERR__NOPRDCHK                    _MK_ENUM_CONST(0x00000001)                                                       // ----V
#define AHCI_PORT_PXTFD_0_ERR_00                           _MK_ENUM_CONST(0x00000000)                                                       // R-I-V
#define AHCI_PORT_PXTFD_0_RSVD_SHIFT                        _MK_SHIFT_CONST(16)                                                             // C--VF
#define AHCI_PORT_PXTFD_0_RSVD_FIELD                       (_MK_SHIFT_CONST(0xffff) << AHCI_PORT_PXTFD_0_RSVD_SHIFT)
#define AHCI_PORT_PXTFD_0_RSVD_RANGE                       31:16
#define AHCI_PORT_PXTFD_0_RSVD_WOFFSET                     0
#define AHCI_PORT_PXTFD_0_RSVD__NOPRDCHK                   _MK_ENUM_CONST(0x00000001)                                                       // ----V
#define AHCI_PORT_PXTFD_0_RSVD_00                          _MK_ENUM_CONST(0x00000000)                                                       // C---V
// 
// 
//              Figure 9-XXX Port Task File Data Register.
// 
// 
// 
// .TITLE Port Signature
// .FIELD
// 
// 31           24 23           16 15            8 7             0
// .-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-.
// |0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0| PORT_PXSIG
// `-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-'
// 
#define AHCI_PORT_PXSIG_0                                  0x00000124                                                                       // RW-4R
#define AHCI_PORT_PXSIG_0_SECURE                           0
#define AHCI_PORT_PXSIG_0_WORD_COUNT                       1
#define AHCI_PORT_PXSIG_0_RESET_VAL                        0xffffffff
#define AHCI_PORT_PXSIG_0_RESET_MASK                       0xffffffff
#define AHCI_PORT_PXSIG_0_SW_DEFAULT_VAL                   0xffffffff
#define AHCI_PORT_PXSIG_0_SW_DEFAULT_MASK                  0xffffffff
#define AHCI_PORT_PXSIG_0_READ_MASK                        0xffffffff
#define AHCI_PORT_PXSIG_0_WRITE_MASK                       0x0
#define AHCI_PORT_PXSIG_0_SECTOR_CNT_SHIFT                  _MK_SHIFT_CONST(0)                                                              // R-IVF
#define AHCI_PORT_PXSIG_0_SECTOR_CNT_FIELD                 (_MK_SHIFT_CONST(0xff) << AHCI_PORT_PXSIG_0_SECTOR_CNT_SHIFT)
#define AHCI_PORT_PXSIG_0_SECTOR_CNT_RANGE                 7:0
#define AHCI_PORT_PXSIG_0_SECTOR_CNT_WOFFSET               0
#define AHCI_PORT_PXSIG_0_SECTOR_CNT_DEFAULT               (_MK_MASK_CONST(0x000000FF)
#define AHCI_PORT_PXSIG_0_SECTOR_CNT_DEFAULT_MASK          (_MK_MASK_CONST(0xff)
#define AHCI_PORT_PXSIG_0_SECTOR_CNT_SW_DEFAULT            (_MK_MASK_CONST(0x000000FF)
#define AHCI_PORT_PXSIG_0_SECTOR_CNT_SW_DEFAULT_MASK       (_MK_MASK_CONST(0xff)
#define AHCI_PORT_PXSIG_0_SECTOR_CNT__NOPRDCHK             _MK_ENUM_CONST(0x00000001)                                                       // ----V
#define AHCI_PORT_PXSIG_0_SECTOR_CNT_INIT                  _MK_ENUM_CONST(0x000000FF)                                                       // R-I-V
#define AHCI_PORT_PXSIG_0_SECTOR_CNT_00                    _MK_ENUM_CONST(0x00000000)                                                       // R---V
#define AHCI_PORT_PXSIG_0_LBA_LOW_SHIFT                     _MK_SHIFT_CONST(8)                                                              // R-IVF
#define AHCI_PORT_PXSIG_0_LBA_LOW_FIELD                    (_MK_SHIFT_CONST(0xff) << AHCI_PORT_PXSIG_0_LBA_LOW_SHIFT)
#define AHCI_PORT_PXSIG_0_LBA_LOW_RANGE                    15:8
#define AHCI_PORT_PXSIG_0_LBA_LOW_WOFFSET                  0
#define AHCI_PORT_PXSIG_0_LBA_LOW_DEFAULT                  (_MK_MASK_CONST(0x000000FF)
#define AHCI_PORT_PXSIG_0_LBA_LOW_DEFAULT_MASK             (_MK_MASK_CONST(0xff)
#define AHCI_PORT_PXSIG_0_LBA_LOW_SW_DEFAULT               (_MK_MASK_CONST(0x000000FF)
#define AHCI_PORT_PXSIG_0_LBA_LOW_SW_DEFAULT_MASK          (_MK_MASK_CONST(0xff)
#define AHCI_PORT_PXSIG_0_LBA_LOW__NOPRDCHK                _MK_ENUM_CONST(0x00000001)                                                       // ----V
#define AHCI_PORT_PXSIG_0_LBA_LOW_INIT                     _MK_ENUM_CONST(0x000000FF)                                                       // R-I-V
#define AHCI_PORT_PXSIG_0_LBA_LOW_00                       _MK_ENUM_CONST(0x00000000)                                                       // R---V
#define AHCI_PORT_PXSIG_0_LBA_MID_SHIFT                     _MK_SHIFT_CONST(16)                                                             // R-IVF
#define AHCI_PORT_PXSIG_0_LBA_MID_FIELD                    (_MK_SHIFT_CONST(0xff) << AHCI_PORT_PXSIG_0_LBA_MID_SHIFT)
#define AHCI_PORT_PXSIG_0_LBA_MID_RANGE                    23:16
#define AHCI_PORT_PXSIG_0_LBA_MID_WOFFSET                  0
#define AHCI_PORT_PXSIG_0_LBA_MID_DEFAULT                  (_MK_MASK_CONST(0x000000FF)
#define AHCI_PORT_PXSIG_0_LBA_MID_DEFAULT_MASK             (_MK_MASK_CONST(0xff)
#define AHCI_PORT_PXSIG_0_LBA_MID_SW_DEFAULT               (_MK_MASK_CONST(0x000000FF)
#define AHCI_PORT_PXSIG_0_LBA_MID_SW_DEFAULT_MASK          (_MK_MASK_CONST(0xff)
#define AHCI_PORT_PXSIG_0_LBA_MID__NOPRDCHK                _MK_ENUM_CONST(0x00000001)                                                       // ----V
#define AHCI_PORT_PXSIG_0_LBA_MID_INIT                     _MK_ENUM_CONST(0x000000FF)                                                       // R-I-V
#define AHCI_PORT_PXSIG_0_LBA_MID_00                       _MK_ENUM_CONST(0x00000000)                                                       // R---V
#define AHCI_PORT_PXSIG_0_LBA_HIGH_SHIFT                    _MK_SHIFT_CONST(24)                                                             // R-IVF
#define AHCI_PORT_PXSIG_0_LBA_HIGH_FIELD                   (_MK_SHIFT_CONST(0xff) << AHCI_PORT_PXSIG_0_LBA_HIGH_SHIFT)
#define AHCI_PORT_PXSIG_0_LBA_HIGH_RANGE                   31:24
#define AHCI_PORT_PXSIG_0_LBA_HIGH_WOFFSET                 0
#define AHCI_PORT_PXSIG_0_LBA_HIGH_DEFAULT                 (_MK_MASK_CONST(0x000000FF)
#define AHCI_PORT_PXSIG_0_LBA_HIGH_DEFAULT_MASK            (_MK_MASK_CONST(0xff)
#define AHCI_PORT_PXSIG_0_LBA_HIGH_SW_DEFAULT              (_MK_MASK_CONST(0x000000FF)
#define AHCI_PORT_PXSIG_0_LBA_HIGH_SW_DEFAULT_MASK         (_MK_MASK_CONST(0xff)
#define AHCI_PORT_PXSIG_0_LBA_HIGH__NOPRDCHK               _MK_ENUM_CONST(0x00000001)                                                       // ----V
#define AHCI_PORT_PXSIG_0_LBA_HIGH_INIT                    _MK_ENUM_CONST(0x000000FF)                                                       // R-I-V
#define AHCI_PORT_PXSIG_0_LBA_HIGH_00                      _MK_ENUM_CONST(0x00000000)                                                       // R---V
// 
// 
//              Figure 9-XXX Port Signature Register.
// 
// 
// 
// .TITLE Port Serial ATA Status
// .FIELD
// 
// 31           24 23           16 15            8 7             0
// .-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-.
// |0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0| PORT_PXSSTS
// `-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-'
// 
#define AHCI_PORT_PXSSTS_0                                 0x00000128                                                                       // RW-4R
#define AHCI_PORT_PXSSTS_0_SECURE                          0
#define AHCI_PORT_PXSSTS_0_WORD_COUNT                      1
#define AHCI_PORT_PXSSTS_0_RESET_VAL                       0x0
#define AHCI_PORT_PXSSTS_0_RESET_MASK                      0xfff
#define AHCI_PORT_PXSSTS_0_SW_DEFAULT_VAL                  0x0
#define AHCI_PORT_PXSSTS_0_SW_DEFAULT_MASK                 0xfff
#define AHCI_PORT_PXSSTS_0_READ_MASK                       0xfff
#define AHCI_PORT_PXSSTS_0_WRITE_MASK                      0x0
#define AHCI_PORT_PXSSTS_0_DET_SHIFT                        _MK_SHIFT_CONST(0)                                                              // R-IVF
#define AHCI_PORT_PXSSTS_0_DET_FIELD                       (_MK_SHIFT_CONST(0xf) << AHCI_PORT_PXSSTS_0_DET_SHIFT)
#define AHCI_PORT_PXSSTS_0_DET_RANGE                       3:0
#define AHCI_PORT_PXSSTS_0_DET_WOFFSET                     0
#define AHCI_PORT_PXSSTS_0_DET_DEFAULT                     (_MK_MASK_CONST(0x00000000)
#define AHCI_PORT_PXSSTS_0_DET_DEFAULT_MASK                (_MK_MASK_CONST(0xf)
#define AHCI_PORT_PXSSTS_0_DET_SW_DEFAULT                  (_MK_MASK_CONST(0x00000000)
#define AHCI_PORT_PXSSTS_0_DET_SW_DEFAULT_MASK             (_MK_MASK_CONST(0xf)
#define AHCI_PORT_PXSSTS_0_DET__NOPRDCHK                   _MK_ENUM_CONST(0x00000001)                                                       // ----V
#define AHCI_PORT_PXSSTS_0_DET_NO_DEV                      _MK_ENUM_CONST(0x00000000)                                                       // R-I-V
#define AHCI_PORT_PXSSTS_0_DET_DEV_PRSNT_NO_PHY_COMM       _MK_ENUM_CONST(0x00000001)                                                       // R---V
#define AHCI_PORT_PXSSTS_0_DET_DEV_PRSNT_PHY_COMM          _MK_ENUM_CONST(0x00000003)                                                       // R---V
#define AHCI_PORT_PXSSTS_0_DET_BIST_LPBK                   _MK_ENUM_CONST(0x00000004)                                                       // R---V
#define AHCI_PORT_PXSSTS_0_SPD_SHIFT                        _MK_SHIFT_CONST(4)                                                              // R-IVF
#define AHCI_PORT_PXSSTS_0_SPD_FIELD                       (_MK_SHIFT_CONST(0xf) << AHCI_PORT_PXSSTS_0_SPD_SHIFT)
#define AHCI_PORT_PXSSTS_0_SPD_RANGE                       7:4
#define AHCI_PORT_PXSSTS_0_SPD_WOFFSET                     0
#define AHCI_PORT_PXSSTS_0_SPD_DEFAULT                     (_MK_MASK_CONST(0x00000000)
#define AHCI_PORT_PXSSTS_0_SPD_DEFAULT_MASK                (_MK_MASK_CONST(0xf)
#define AHCI_PORT_PXSSTS_0_SPD_SW_DEFAULT                  (_MK_MASK_CONST(0x00000000)
#define AHCI_PORT_PXSSTS_0_SPD_SW_DEFAULT_MASK             (_MK_MASK_CONST(0xf)
#define AHCI_PORT_PXSSTS_0_SPD__NOPRDCHK                   _MK_ENUM_CONST(0x00000001)                                                       // ----V
#define AHCI_PORT_PXSSTS_0_SPD_NO_DEV                      _MK_ENUM_CONST(0x00000000)                                                       // R-I-V
#define AHCI_PORT_PXSSTS_0_SPD_GEN1                        _MK_ENUM_CONST(0x00000001)                                                       // R---V
#define AHCI_PORT_PXSSTS_0_SPD_GEN2                        _MK_ENUM_CONST(0x00000002)                                                       // R---V
#define AHCI_PORT_PXSSTS_0_SPD_GEN3                        _MK_ENUM_CONST(0x00000003)                                                       // R---V
#define AHCI_PORT_PXSSTS_0_IPM_SHIFT                        _MK_SHIFT_CONST(8)                                                              // R-IVF
#define AHCI_PORT_PXSSTS_0_IPM_FIELD                       (_MK_SHIFT_CONST(0xf) << AHCI_PORT_PXSSTS_0_IPM_SHIFT)
#define AHCI_PORT_PXSSTS_0_IPM_RANGE                       11:8
#define AHCI_PORT_PXSSTS_0_IPM_WOFFSET                     0
#define AHCI_PORT_PXSSTS_0_IPM_DEFAULT                     (_MK_MASK_CONST(0x00000000)
#define AHCI_PORT_PXSSTS_0_IPM_DEFAULT_MASK                (_MK_MASK_CONST(0xf)
#define AHCI_PORT_PXSSTS_0_IPM_SW_DEFAULT                  (_MK_MASK_CONST(0x00000000)
#define AHCI_PORT_PXSSTS_0_IPM_SW_DEFAULT_MASK             (_MK_MASK_CONST(0xf)
#define AHCI_PORT_PXSSTS_0_IPM__NOPRDCHK                   _MK_ENUM_CONST(0x00000001)                                                       // ----V
#define AHCI_PORT_PXSSTS_0_IPM_NO_DEV                      _MK_ENUM_CONST(0x00000000)                                                       // R-I-V
#define AHCI_PORT_PXSSTS_0_IPM_ACT_ST                      _MK_ENUM_CONST(0x00000001)                                                       // R---V
#define AHCI_PORT_PXSSTS_0_IPM_PARTIAL_ST                  _MK_ENUM_CONST(0x00000002)                                                       // R---V
#define AHCI_PORT_PXSSTS_0_IPM_SLUMBER_ST                  _MK_ENUM_CONST(0x00000006)                                                       // R---V
#define AHCI_PORT_PXSSTS_0_IPM_DEVSLEEP_ST                 _MK_ENUM_CONST(0x00000008)                                                       // R---V
// 
// .LABEL PRIVATE
// .LABEL PUBLIC
// 
//              Figure 9-XXX Port Serial ATA Status Register.
// 
// 
// 
// .TITLE Port Serial ATA Control
// .FIELD
// .LABEL PRIVATE
// SW_INIT required for field PXSCTL_IPM to enable IPM
// .LABEL PUBLIC
// 31           24 23           16 15            8 7             0
// .-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-.
// |0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0| PORT_PXSCTL
// `-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-'
// 
#define AHCI_PORT_PXSCTL_0                                 0x0000012C                                                                       // RW-4R
#define AHCI_PORT_PXSCTL_0_SECURE                          0
#define AHCI_PORT_PXSCTL_0_WORD_COUNT                      1
#define AHCI_PORT_PXSCTL_0_RESET_VAL                       0x0
#define AHCI_PORT_PXSCTL_0_RESET_MASK                      0xfff
#define AHCI_PORT_PXSCTL_0_SW_DEFAULT_VAL                  0x0
#define AHCI_PORT_PXSCTL_0_SW_DEFAULT_MASK                 0xfff
#define AHCI_PORT_PXSCTL_0_READ_MASK                       0xfffff
#define AHCI_PORT_PXSCTL_0_WRITE_MASK                      0xfff
#define AHCI_PORT_PXSCTL_0_DET_SHIFT                        _MK_SHIFT_CONST(0)                                                              // RWIVF
#define AHCI_PORT_PXSCTL_0_DET_FIELD                       (_MK_SHIFT_CONST(0xf) << AHCI_PORT_PXSCTL_0_DET_SHIFT)
#define AHCI_PORT_PXSCTL_0_DET_RANGE                       3:0
#define AHCI_PORT_PXSCTL_0_DET_WOFFSET                     0
#define AHCI_PORT_PXSCTL_0_DET_DEFAULT                     (_MK_MASK_CONST(0x00000000)
#define AHCI_PORT_PXSCTL_0_DET_DEFAULT_MASK                (_MK_MASK_CONST(0xf)
#define AHCI_PORT_PXSCTL_0_DET_SW_DEFAULT                  (_MK_MASK_CONST(0x00000000)
#define AHCI_PORT_PXSCTL_0_DET_SW_DEFAULT_MASK             (_MK_MASK_CONST(0xf)
#define AHCI_PORT_PXSCTL_0_DET_NO_DEV_RQD                  _MK_ENUM_CONST(0x00000000)                                                       // RWI-V
#define AHCI_PORT_PXSCTL_0_DET_INTF_INIT                   _MK_ENUM_CONST(0x00000001)                                                       // RW--V
#define AHCI_PORT_PXSCTL_0_DET_PHY_OFFLINE                 _MK_ENUM_CONST(0x00000004)                                                       // RW--V
#define AHCI_PORT_PXSCTL_0_SPD_SHIFT                        _MK_SHIFT_CONST(4)                                                              // RWIVF
#define AHCI_PORT_PXSCTL_0_SPD_FIELD                       (_MK_SHIFT_CONST(0xf) << AHCI_PORT_PXSCTL_0_SPD_SHIFT)
#define AHCI_PORT_PXSCTL_0_SPD_RANGE                       7:4
#define AHCI_PORT_PXSCTL_0_SPD_WOFFSET                     0
#define AHCI_PORT_PXSCTL_0_SPD_DEFAULT                     (_MK_MASK_CONST(0x00000000)
#define AHCI_PORT_PXSCTL_0_SPD_DEFAULT_MASK                (_MK_MASK_CONST(0xf)
#define AHCI_PORT_PXSCTL_0_SPD_SW_DEFAULT                  (_MK_MASK_CONST(0x00000000)
#define AHCI_PORT_PXSCTL_0_SPD_SW_DEFAULT_MASK             (_MK_MASK_CONST(0xf)
#define AHCI_PORT_PXSCTL_0_SPD_00                          _MK_ENUM_CONST(0x00000000)                                                       // RWI-V
#define AHCI_PORT_PXSCTL_0_SPD_GEN1                        _MK_ENUM_CONST(0x00000001)                                                       // RW--V
#define AHCI_PORT_PXSCTL_0_SPD_GEN2                        _MK_ENUM_CONST(0x00000002)                                                       // RW--V
#define AHCI_PORT_PXSCTL_0_IPM_SHIFT                        _MK_SHIFT_CONST(8)                                                              // RWIVF
#define AHCI_PORT_PXSCTL_0_IPM_FIELD                       (_MK_SHIFT_CONST(0xf) << AHCI_PORT_PXSCTL_0_IPM_SHIFT)
#define AHCI_PORT_PXSCTL_0_IPM_RANGE                       11:8
#define AHCI_PORT_PXSCTL_0_IPM_WOFFSET                     0
#define AHCI_PORT_PXSCTL_0_IPM_DEFAULT                     (_MK_MASK_CONST(0x00000000)
#define AHCI_PORT_PXSCTL_0_IPM_DEFAULT_MASK                (_MK_MASK_CONST(0xf)
#define AHCI_PORT_PXSCTL_0_IPM_SW_DEFAULT                  (_MK_MASK_CONST(0x00000000)
#define AHCI_PORT_PXSCTL_0_IPM_SW_DEFAULT_MASK             (_MK_MASK_CONST(0xf)
#define AHCI_PORT_PXSCTL_0_IPM_NO_RSTCT                    _MK_ENUM_CONST(0x00000000)                                                       // RWI-V
#define AHCI_PORT_PXSCTL_0_IPM_PARTIAL_ST_DISABLED         _MK_ENUM_CONST(0x00000001)                                                       // RW--V
#define AHCI_PORT_PXSCTL_0_IPM_SLUMBER_ST_DISABLED         _MK_ENUM_CONST(0x00000002)                                                       // RW--V
#define AHCI_PORT_PXSCTL_0_IPM_PART_SLUM_ST_DISABLED       _MK_ENUM_CONST(0x00000003)                                                       // RW--V
#define AHCI_PORT_PXSCTL_0_IPM_DEVSLEEP_ST_DISABLED        _MK_ENUM_CONST(0x00000004)                                                       // RW--V
#define AHCI_PORT_PXSCTL_0_IPM_PART_DEVSLP_ST_DISABLED     _MK_ENUM_CONST(0x00000005)                                                       // RW--V
#define AHCI_PORT_PXSCTL_0_IPM_SLUM_DEVSLP_ST_DISABLED     _MK_ENUM_CONST(0x00000006)                                                       // RW--V
#define AHCI_PORT_PXSCTL_0_IPM_PART_SLUM_DEVSLP_ST_DISABLED _MK_ENUM_CONST(0x00000007)                                                       // RW--V
#define AHCI_PORT_PXSCTL_0_SPM_SHIFT                        _MK_SHIFT_CONST(12)                                                             // C--VF
#define AHCI_PORT_PXSCTL_0_SPM_FIELD                       (_MK_SHIFT_CONST(0xf) << AHCI_PORT_PXSCTL_0_SPM_SHIFT)
#define AHCI_PORT_PXSCTL_0_SPM_RANGE                       15:12
#define AHCI_PORT_PXSCTL_0_SPM_WOFFSET                     0
#define AHCI_PORT_PXSCTL_0_SPM_00                          _MK_ENUM_CONST(0x00000000)                                                       // C---V
#define AHCI_PORT_PXSCTL_0_PMP_SHIFT                        _MK_SHIFT_CONST(16)                                                             // C--VF
#define AHCI_PORT_PXSCTL_0_PMP_FIELD                       (_MK_SHIFT_CONST(0xf) << AHCI_PORT_PXSCTL_0_PMP_SHIFT)
#define AHCI_PORT_PXSCTL_0_PMP_RANGE                       19:16
#define AHCI_PORT_PXSCTL_0_PMP_WOFFSET                     0
#define AHCI_PORT_PXSCTL_0_PMP_00                          _MK_ENUM_CONST(0x00000000)                                                       // C---V
// 
// 
//              Figure 9-XXX Port Serial ATA Control Register.
// 
// 
// 
// .TITLE Port Serial ATA Error
// .FIELD
// 
// 31           24 23           16 15            8 7             0
// .-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-.
// |0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0| PORT_PXSERR
// `-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-'
// 
#define AHCI_PORT_PXSERR_0                                 0x00000130                                                                       // RW-4R
#define AHCI_PORT_PXSERR_0_SECURE                          0
#define AHCI_PORT_PXSERR_0_WORD_COUNT                      1
#define AHCI_PORT_PXSERR_0_RESET_VAL                       0x0
#define AHCI_PORT_PXSERR_0_RESET_MASK                      0x7ff0f03
#define AHCI_PORT_PXSERR_0_SW_DEFAULT_VAL                  0x0
#define AHCI_PORT_PXSERR_0_SW_DEFAULT_MASK                 0x7ff0f03
#define AHCI_PORT_PXSERR_0_READ_MASK                       0x7ff0f03
#define AHCI_PORT_PXSERR_0_WRITE_MASK                      0x7ff0f03
#define AHCI_PORT_PXSERR_0_ERR_I_SHIFT                      _MK_SHIFT_CONST(0)                                                              // RWIVF
#define AHCI_PORT_PXSERR_0_ERR_I_FIELD                     (_MK_SHIFT_CONST(0x1) << AHCI_PORT_PXSERR_0_ERR_I_SHIFT)
#define AHCI_PORT_PXSERR_0_ERR_I_RANGE                     0:0
#define AHCI_PORT_PXSERR_0_ERR_I_WOFFSET                   0
#define AHCI_PORT_PXSERR_0_ERR_I_DEFAULT                   (_MK_MASK_CONST(0x00000000)
#define AHCI_PORT_PXSERR_0_ERR_I_DEFAULT_MASK              (_MK_MASK_CONST(0x1)
#define AHCI_PORT_PXSERR_0_ERR_I_SW_DEFAULT                (_MK_MASK_CONST(0x00000000)
#define AHCI_PORT_PXSERR_0_ERR_I_SW_DEFAULT_MASK           (_MK_MASK_CONST(0x1)
#define AHCI_PORT_PXSERR_0_ERR_I__NOPRDCHK                 _MK_ENUM_CONST(0x00000001)                                                       // ----V
#define AHCI_PORT_PXSERR_0_ERR_I_FALSE                     _MK_ENUM_CONST(0x00000000)                                                       // R-I-V
#define AHCI_PORT_PXSERR_0_ERR_I_TRUE                      _MK_ENUM_CONST(0x00000001)                                                       // R---V
#define AHCI_PORT_PXSERR_0_ERR_I_CLEAR                     _MK_ENUM_CONST(0x00000001)                                                       // -W--C
#define AHCI_PORT_PXSERR_0_ERR_M_SHIFT                      _MK_SHIFT_CONST(1)                                                              // RWIVF
#define AHCI_PORT_PXSERR_0_ERR_M_FIELD                     (_MK_SHIFT_CONST(0x1) << AHCI_PORT_PXSERR_0_ERR_M_SHIFT)
#define AHCI_PORT_PXSERR_0_ERR_M_RANGE                     1:1
#define AHCI_PORT_PXSERR_0_ERR_M_WOFFSET                   0
#define AHCI_PORT_PXSERR_0_ERR_M_DEFAULT                   (_MK_MASK_CONST(0x00000000)
#define AHCI_PORT_PXSERR_0_ERR_M_DEFAULT_MASK              (_MK_MASK_CONST(0x1)
#define AHCI_PORT_PXSERR_0_ERR_M_SW_DEFAULT                (_MK_MASK_CONST(0x00000000)
#define AHCI_PORT_PXSERR_0_ERR_M_SW_DEFAULT_MASK           (_MK_MASK_CONST(0x1)
#define AHCI_PORT_PXSERR_0_ERR_M__NOPRDCHK                 _MK_ENUM_CONST(0x00000001)                                                       // ----V
#define AHCI_PORT_PXSERR_0_ERR_M_FALSE                     _MK_ENUM_CONST(0x00000000)                                                       // R-I-V
#define AHCI_PORT_PXSERR_0_ERR_M_TRUE                      _MK_ENUM_CONST(0x00000001)                                                       // R---V
#define AHCI_PORT_PXSERR_0_ERR_M_CLEAR                     _MK_ENUM_CONST(0x00000001)                                                       // -W--C
#define AHCI_PORT_PXSERR_0_ERR_T_SHIFT                      _MK_SHIFT_CONST(8)                                                              // RWIVF
#define AHCI_PORT_PXSERR_0_ERR_T_FIELD                     (_MK_SHIFT_CONST(0x1) << AHCI_PORT_PXSERR_0_ERR_T_SHIFT)
#define AHCI_PORT_PXSERR_0_ERR_T_RANGE                     8:8
#define AHCI_PORT_PXSERR_0_ERR_T_WOFFSET                   0
#define AHCI_PORT_PXSERR_0_ERR_T_DEFAULT                   (_MK_MASK_CONST(0x00000000)
#define AHCI_PORT_PXSERR_0_ERR_T_DEFAULT_MASK              (_MK_MASK_CONST(0x1)
#define AHCI_PORT_PXSERR_0_ERR_T_SW_DEFAULT                (_MK_MASK_CONST(0x00000000)
#define AHCI_PORT_PXSERR_0_ERR_T_SW_DEFAULT_MASK           (_MK_MASK_CONST(0x1)
#define AHCI_PORT_PXSERR_0_ERR_T__NOPRDCHK                 _MK_ENUM_CONST(0x00000001)                                                       // ----V
#define AHCI_PORT_PXSERR_0_ERR_T_FALSE                     _MK_ENUM_CONST(0x00000000)                                                       // R-I-V
#define AHCI_PORT_PXSERR_0_ERR_T_TRUE                      _MK_ENUM_CONST(0x00000001)                                                       // R---V
#define AHCI_PORT_PXSERR_0_ERR_T_CLEAR                     _MK_ENUM_CONST(0x00000001)                                                       // -W--C
#define AHCI_PORT_PXSERR_0_ERR_C_SHIFT                      _MK_SHIFT_CONST(9)                                                              // RWIVF
#define AHCI_PORT_PXSERR_0_ERR_C_FIELD                     (_MK_SHIFT_CONST(0x1) << AHCI_PORT_PXSERR_0_ERR_C_SHIFT)
#define AHCI_PORT_PXSERR_0_ERR_C_RANGE                     9:9
#define AHCI_PORT_PXSERR_0_ERR_C_WOFFSET                   0
#define AHCI_PORT_PXSERR_0_ERR_C_DEFAULT                   (_MK_MASK_CONST(0x00000000)
#define AHCI_PORT_PXSERR_0_ERR_C_DEFAULT_MASK              (_MK_MASK_CONST(0x1)
#define AHCI_PORT_PXSERR_0_ERR_C_SW_DEFAULT                (_MK_MASK_CONST(0x00000000)
#define AHCI_PORT_PXSERR_0_ERR_C_SW_DEFAULT_MASK           (_MK_MASK_CONST(0x1)
#define AHCI_PORT_PXSERR_0_ERR_C__NOPRDCHK                 _MK_ENUM_CONST(0x00000001)                                                       // ----V
#define AHCI_PORT_PXSERR_0_ERR_C_FALSE                     _MK_ENUM_CONST(0x00000000)                                                       // R-I-V
#define AHCI_PORT_PXSERR_0_ERR_C_TRUE                      _MK_ENUM_CONST(0x00000001)                                                       // R---V
#define AHCI_PORT_PXSERR_0_ERR_C_CLEAR                     _MK_ENUM_CONST(0x00000001)                                                       // -W--C
#define AHCI_PORT_PXSERR_0_ERR_P_SHIFT                      _MK_SHIFT_CONST(10)                                                             // RWIVF
#define AHCI_PORT_PXSERR_0_ERR_P_FIELD                     (_MK_SHIFT_CONST(0x1) << AHCI_PORT_PXSERR_0_ERR_P_SHIFT)
#define AHCI_PORT_PXSERR_0_ERR_P_RANGE                     10:10
#define AHCI_PORT_PXSERR_0_ERR_P_WOFFSET                   0
#define AHCI_PORT_PXSERR_0_ERR_P_DEFAULT                   (_MK_MASK_CONST(0x00000000)
#define AHCI_PORT_PXSERR_0_ERR_P_DEFAULT_MASK              (_MK_MASK_CONST(0x1)
#define AHCI_PORT_PXSERR_0_ERR_P_SW_DEFAULT                (_MK_MASK_CONST(0x00000000)
#define AHCI_PORT_PXSERR_0_ERR_P_SW_DEFAULT_MASK           (_MK_MASK_CONST(0x1)
#define AHCI_PORT_PXSERR_0_ERR_P__NOPRDCHK                 _MK_ENUM_CONST(0x00000001)                                                       // ----V
#define AHCI_PORT_PXSERR_0_ERR_P_FALSE                     _MK_ENUM_CONST(0x00000000)                                                       // R-I-V
#define AHCI_PORT_PXSERR_0_ERR_P_TRUE                      _MK_ENUM_CONST(0x00000001)                                                       // R---V
#define AHCI_PORT_PXSERR_0_ERR_P_CLEAR                     _MK_ENUM_CONST(0x00000001)                                                       // -W--C
#define AHCI_PORT_PXSERR_0_ERR_E_SHIFT                      _MK_SHIFT_CONST(11)                                                             // RWIVF
#define AHCI_PORT_PXSERR_0_ERR_E_FIELD                     (_MK_SHIFT_CONST(0x1) << AHCI_PORT_PXSERR_0_ERR_E_SHIFT)
#define AHCI_PORT_PXSERR_0_ERR_E_RANGE                     11:11
#define AHCI_PORT_PXSERR_0_ERR_E_WOFFSET                   0
#define AHCI_PORT_PXSERR_0_ERR_E_DEFAULT                   (_MK_MASK_CONST(0x00000000)
#define AHCI_PORT_PXSERR_0_ERR_E_DEFAULT_MASK              (_MK_MASK_CONST(0x1)
#define AHCI_PORT_PXSERR_0_ERR_E_SW_DEFAULT                (_MK_MASK_CONST(0x00000000)
#define AHCI_PORT_PXSERR_0_ERR_E_SW_DEFAULT_MASK           (_MK_MASK_CONST(0x1)
#define AHCI_PORT_PXSERR_0_ERR_E__NOPRDCHK                 _MK_ENUM_CONST(0x00000001)                                                       // ----V
#define AHCI_PORT_PXSERR_0_ERR_E_FALSE                     _MK_ENUM_CONST(0x00000000)                                                       // R-I-V
#define AHCI_PORT_PXSERR_0_ERR_E_TRUE                      _MK_ENUM_CONST(0x00000001)                                                       // R---V
#define AHCI_PORT_PXSERR_0_ERR_E_CLEAR                     _MK_ENUM_CONST(0x00000001)                                                       // -W--C
#define AHCI_PORT_PXSERR_0_DIAG_N_SHIFT                     _MK_SHIFT_CONST(16)                                                             // RWIVF
#define AHCI_PORT_PXSERR_0_DIAG_N_FIELD                    (_MK_SHIFT_CONST(0x1) << AHCI_PORT_PXSERR_0_DIAG_N_SHIFT)
#define AHCI_PORT_PXSERR_0_DIAG_N_RANGE                    16:16
#define AHCI_PORT_PXSERR_0_DIAG_N_WOFFSET                  0
#define AHCI_PORT_PXSERR_0_DIAG_N_DEFAULT                  (_MK_MASK_CONST(0x00000000)
#define AHCI_PORT_PXSERR_0_DIAG_N_DEFAULT_MASK             (_MK_MASK_CONST(0x1)
#define AHCI_PORT_PXSERR_0_DIAG_N_SW_DEFAULT               (_MK_MASK_CONST(0x00000000)
#define AHCI_PORT_PXSERR_0_DIAG_N_SW_DEFAULT_MASK          (_MK_MASK_CONST(0x1)
#define AHCI_PORT_PXSERR_0_DIAG_N__NOPRDCHK                _MK_ENUM_CONST(0x00000001)                                                       // ----V
#define AHCI_PORT_PXSERR_0_DIAG_N_FALSE                    _MK_ENUM_CONST(0x00000000)                                                       // R-I-V
#define AHCI_PORT_PXSERR_0_DIAG_N_TRUE                     _MK_ENUM_CONST(0x00000001)                                                       // R---V
#define AHCI_PORT_PXSERR_0_DIAG_N_CLEAR                    _MK_ENUM_CONST(0x00000001)                                                       // -W--C
#define AHCI_PORT_PXSERR_0_DIAG_I_SHIFT                     _MK_SHIFT_CONST(17)                                                             // RWIVF
#define AHCI_PORT_PXSERR_0_DIAG_I_FIELD                    (_MK_SHIFT_CONST(0x1) << AHCI_PORT_PXSERR_0_DIAG_I_SHIFT)
#define AHCI_PORT_PXSERR_0_DIAG_I_RANGE                    17:17
#define AHCI_PORT_PXSERR_0_DIAG_I_WOFFSET                  0
#define AHCI_PORT_PXSERR_0_DIAG_I_DEFAULT                  (_MK_MASK_CONST(0x00000000)
#define AHCI_PORT_PXSERR_0_DIAG_I_DEFAULT_MASK             (_MK_MASK_CONST(0x1)
#define AHCI_PORT_PXSERR_0_DIAG_I_SW_DEFAULT               (_MK_MASK_CONST(0x00000000)
#define AHCI_PORT_PXSERR_0_DIAG_I_SW_DEFAULT_MASK          (_MK_MASK_CONST(0x1)
#define AHCI_PORT_PXSERR_0_DIAG_I__NOPRDCHK                _MK_ENUM_CONST(0x00000001)                                                       // ----V
#define AHCI_PORT_PXSERR_0_DIAG_I_FALSE                    _MK_ENUM_CONST(0x00000000)                                                       // R-I-V
#define AHCI_PORT_PXSERR_0_DIAG_I_TRUE                     _MK_ENUM_CONST(0x00000001)                                                       // R---V
#define AHCI_PORT_PXSERR_0_DIAG_I_CLEAR                    _MK_ENUM_CONST(0x00000001)                                                       // -W--C
#define AHCI_PORT_PXSERR_0_DIAG_W_SHIFT                     _MK_SHIFT_CONST(18)                                                             // RWIVF
#define AHCI_PORT_PXSERR_0_DIAG_W_FIELD                    (_MK_SHIFT_CONST(0x1) << AHCI_PORT_PXSERR_0_DIAG_W_SHIFT)
#define AHCI_PORT_PXSERR_0_DIAG_W_RANGE                    18:18
#define AHCI_PORT_PXSERR_0_DIAG_W_WOFFSET                  0
#define AHCI_PORT_PXSERR_0_DIAG_W_DEFAULT                  (_MK_MASK_CONST(0x00000000)
#define AHCI_PORT_PXSERR_0_DIAG_W_DEFAULT_MASK             (_MK_MASK_CONST(0x1)
#define AHCI_PORT_PXSERR_0_DIAG_W_SW_DEFAULT               (_MK_MASK_CONST(0x00000000)
#define AHCI_PORT_PXSERR_0_DIAG_W_SW_DEFAULT_MASK          (_MK_MASK_CONST(0x1)
#define AHCI_PORT_PXSERR_0_DIAG_W__NOPRDCHK                _MK_ENUM_CONST(0x00000001)                                                       // ----V
#define AHCI_PORT_PXSERR_0_DIAG_W_FALSE                    _MK_ENUM_CONST(0x00000000)                                                       // R-I-V
#define AHCI_PORT_PXSERR_0_DIAG_W_TRUE                     _MK_ENUM_CONST(0x00000001)                                                       // R---V
#define AHCI_PORT_PXSERR_0_DIAG_W_CLEAR                    _MK_ENUM_CONST(0x00000001)                                                       // -W--C
#define AHCI_PORT_PXSERR_0_DIAG_B_SHIFT                     _MK_SHIFT_CONST(19)                                                             // RWIVF
#define AHCI_PORT_PXSERR_0_DIAG_B_FIELD                    (_MK_SHIFT_CONST(0x1) << AHCI_PORT_PXSERR_0_DIAG_B_SHIFT)
#define AHCI_PORT_PXSERR_0_DIAG_B_RANGE                    19:19
#define AHCI_PORT_PXSERR_0_DIAG_B_WOFFSET                  0
#define AHCI_PORT_PXSERR_0_DIAG_B_DEFAULT                  (_MK_MASK_CONST(0x00000000)
#define AHCI_PORT_PXSERR_0_DIAG_B_DEFAULT_MASK             (_MK_MASK_CONST(0x1)
#define AHCI_PORT_PXSERR_0_DIAG_B_SW_DEFAULT               (_MK_MASK_CONST(0x00000000)
#define AHCI_PORT_PXSERR_0_DIAG_B_SW_DEFAULT_MASK          (_MK_MASK_CONST(0x1)
#define AHCI_PORT_PXSERR_0_DIAG_B__NOPRDCHK                _MK_ENUM_CONST(0x00000001)                                                       // ----V
#define AHCI_PORT_PXSERR_0_DIAG_B_FALSE                    _MK_ENUM_CONST(0x00000000)                                                       // R-I-V
#define AHCI_PORT_PXSERR_0_DIAG_B_TRUE                     _MK_ENUM_CONST(0x00000001)                                                       // R---V
#define AHCI_PORT_PXSERR_0_DIAG_B_CLEAR                    _MK_ENUM_CONST(0x00000001)                                                       // -W--C
#define AHCI_PORT_PXSERR_0_DIAG_D_SHIFT                     _MK_SHIFT_CONST(20)                                                             // RWIVF
#define AHCI_PORT_PXSERR_0_DIAG_D_FIELD                    (_MK_SHIFT_CONST(0x1) << AHCI_PORT_PXSERR_0_DIAG_D_SHIFT)
#define AHCI_PORT_PXSERR_0_DIAG_D_RANGE                    20:20
#define AHCI_PORT_PXSERR_0_DIAG_D_WOFFSET                  0
#define AHCI_PORT_PXSERR_0_DIAG_D_DEFAULT                  (_MK_MASK_CONST(0x00000000)
#define AHCI_PORT_PXSERR_0_DIAG_D_DEFAULT_MASK             (_MK_MASK_CONST(0x1)
#define AHCI_PORT_PXSERR_0_DIAG_D_SW_DEFAULT               (_MK_MASK_CONST(0x00000000)
#define AHCI_PORT_PXSERR_0_DIAG_D_SW_DEFAULT_MASK          (_MK_MASK_CONST(0x1)
#define AHCI_PORT_PXSERR_0_DIAG_D__NOPRDCHK                _MK_ENUM_CONST(0x00000001)                                                       // ----V
#define AHCI_PORT_PXSERR_0_DIAG_D_FALSE                    _MK_ENUM_CONST(0x00000000)                                                       // R-I-V
#define AHCI_PORT_PXSERR_0_DIAG_D_TRUE                     _MK_ENUM_CONST(0x00000001)                                                       // R---V
#define AHCI_PORT_PXSERR_0_DIAG_D_CLEAR                    _MK_ENUM_CONST(0x00000001)                                                       // -W--C
#define AHCI_PORT_PXSERR_0_DIAG_C_SHIFT                     _MK_SHIFT_CONST(21)                                                             // RWIVF
#define AHCI_PORT_PXSERR_0_DIAG_C_FIELD                    (_MK_SHIFT_CONST(0x1) << AHCI_PORT_PXSERR_0_DIAG_C_SHIFT)
#define AHCI_PORT_PXSERR_0_DIAG_C_RANGE                    21:21
#define AHCI_PORT_PXSERR_0_DIAG_C_WOFFSET                  0
#define AHCI_PORT_PXSERR_0_DIAG_C_DEFAULT                  (_MK_MASK_CONST(0x00000000)
#define AHCI_PORT_PXSERR_0_DIAG_C_DEFAULT_MASK             (_MK_MASK_CONST(0x1)
#define AHCI_PORT_PXSERR_0_DIAG_C_SW_DEFAULT               (_MK_MASK_CONST(0x00000000)
#define AHCI_PORT_PXSERR_0_DIAG_C_SW_DEFAULT_MASK          (_MK_MASK_CONST(0x1)
#define AHCI_PORT_PXSERR_0_DIAG_C__NOPRDCHK                _MK_ENUM_CONST(0x00000001)                                                       // ----V
#define AHCI_PORT_PXSERR_0_DIAG_C_FALSE                    _MK_ENUM_CONST(0x00000000)                                                       // R-I-V
#define AHCI_PORT_PXSERR_0_DIAG_C_TRUE                     _MK_ENUM_CONST(0x00000001)                                                       // R---V
#define AHCI_PORT_PXSERR_0_DIAG_C_CLEAR                    _MK_ENUM_CONST(0x00000001)                                                       // -W--C
#define AHCI_PORT_PXSERR_0_DIAG_H_SHIFT                     _MK_SHIFT_CONST(22)                                                             // RWIVF
#define AHCI_PORT_PXSERR_0_DIAG_H_FIELD                    (_MK_SHIFT_CONST(0x1) << AHCI_PORT_PXSERR_0_DIAG_H_SHIFT)
#define AHCI_PORT_PXSERR_0_DIAG_H_RANGE                    22:22
#define AHCI_PORT_PXSERR_0_DIAG_H_WOFFSET                  0
#define AHCI_PORT_PXSERR_0_DIAG_H_DEFAULT                  (_MK_MASK_CONST(0x00000000)
#define AHCI_PORT_PXSERR_0_DIAG_H_DEFAULT_MASK             (_MK_MASK_CONST(0x1)
#define AHCI_PORT_PXSERR_0_DIAG_H_SW_DEFAULT               (_MK_MASK_CONST(0x00000000)
#define AHCI_PORT_PXSERR_0_DIAG_H_SW_DEFAULT_MASK          (_MK_MASK_CONST(0x1)
#define AHCI_PORT_PXSERR_0_DIAG_H__NOPRDCHK                _MK_ENUM_CONST(0x00000001)                                                       // ----V
#define AHCI_PORT_PXSERR_0_DIAG_H_FALSE                    _MK_ENUM_CONST(0x00000000)                                                       // R-I-V
#define AHCI_PORT_PXSERR_0_DIAG_H_TRUE                     _MK_ENUM_CONST(0x00000001)                                                       // R---V
#define AHCI_PORT_PXSERR_0_DIAG_H_CLEAR                    _MK_ENUM_CONST(0x00000001)                                                       // -W--C
#define AHCI_PORT_PXSERR_0_DIAG_S_SHIFT                     _MK_SHIFT_CONST(23)                                                             // RWIVF
#define AHCI_PORT_PXSERR_0_DIAG_S_FIELD                    (_MK_SHIFT_CONST(0x1) << AHCI_PORT_PXSERR_0_DIAG_S_SHIFT)
#define AHCI_PORT_PXSERR_0_DIAG_S_RANGE                    23:23
#define AHCI_PORT_PXSERR_0_DIAG_S_WOFFSET                  0
#define AHCI_PORT_PXSERR_0_DIAG_S_DEFAULT                  (_MK_MASK_CONST(0x00000000)
#define AHCI_PORT_PXSERR_0_DIAG_S_DEFAULT_MASK             (_MK_MASK_CONST(0x1)
#define AHCI_PORT_PXSERR_0_DIAG_S_SW_DEFAULT               (_MK_MASK_CONST(0x00000000)
#define AHCI_PORT_PXSERR_0_DIAG_S_SW_DEFAULT_MASK          (_MK_MASK_CONST(0x1)
#define AHCI_PORT_PXSERR_0_DIAG_S__NOPRDCHK                _MK_ENUM_CONST(0x00000001)                                                       // ----V
#define AHCI_PORT_PXSERR_0_DIAG_S_FALSE                    _MK_ENUM_CONST(0x00000000)                                                       // R-I-V
#define AHCI_PORT_PXSERR_0_DIAG_S_TRUE                     _MK_ENUM_CONST(0x00000001)                                                       // R---V
#define AHCI_PORT_PXSERR_0_DIAG_S_CLEAR                    _MK_ENUM_CONST(0x00000001)                                                       // -W--C
#define AHCI_PORT_PXSERR_0_DIAG_T_SHIFT                     _MK_SHIFT_CONST(24)                                                             // RWIVF
#define AHCI_PORT_PXSERR_0_DIAG_T_FIELD                    (_MK_SHIFT_CONST(0x1) << AHCI_PORT_PXSERR_0_DIAG_T_SHIFT)
#define AHCI_PORT_PXSERR_0_DIAG_T_RANGE                    24:24
#define AHCI_PORT_PXSERR_0_DIAG_T_WOFFSET                  0
#define AHCI_PORT_PXSERR_0_DIAG_T_DEFAULT                  (_MK_MASK_CONST(0x00000000)
#define AHCI_PORT_PXSERR_0_DIAG_T_DEFAULT_MASK             (_MK_MASK_CONST(0x1)
#define AHCI_PORT_PXSERR_0_DIAG_T_SW_DEFAULT               (_MK_MASK_CONST(0x00000000)
#define AHCI_PORT_PXSERR_0_DIAG_T_SW_DEFAULT_MASK          (_MK_MASK_CONST(0x1)
#define AHCI_PORT_PXSERR_0_DIAG_T__NOPRDCHK                _MK_ENUM_CONST(0x00000001)                                                       // ----V
#define AHCI_PORT_PXSERR_0_DIAG_T_FALSE                    _MK_ENUM_CONST(0x00000000)                                                       // R-I-V
#define AHCI_PORT_PXSERR_0_DIAG_T_TRUE                     _MK_ENUM_CONST(0x00000001)                                                       // R---V
#define AHCI_PORT_PXSERR_0_DIAG_T_CLEAR                    _MK_ENUM_CONST(0x00000001)                                                       // -W--C
#define AHCI_PORT_PXSERR_0_DIAG_F_SHIFT                     _MK_SHIFT_CONST(25)                                                             // RWIVF
#define AHCI_PORT_PXSERR_0_DIAG_F_FIELD                    (_MK_SHIFT_CONST(0x1) << AHCI_PORT_PXSERR_0_DIAG_F_SHIFT)
#define AHCI_PORT_PXSERR_0_DIAG_F_RANGE                    25:25
#define AHCI_PORT_PXSERR_0_DIAG_F_WOFFSET                  0
#define AHCI_PORT_PXSERR_0_DIAG_F_DEFAULT                  (_MK_MASK_CONST(0x00000000)
#define AHCI_PORT_PXSERR_0_DIAG_F_DEFAULT_MASK             (_MK_MASK_CONST(0x1)
#define AHCI_PORT_PXSERR_0_DIAG_F_SW_DEFAULT               (_MK_MASK_CONST(0x00000000)
#define AHCI_PORT_PXSERR_0_DIAG_F_SW_DEFAULT_MASK          (_MK_MASK_CONST(0x1)
#define AHCI_PORT_PXSERR_0_DIAG_F__NOPRDCHK                _MK_ENUM_CONST(0x00000001)                                                       // ----V
#define AHCI_PORT_PXSERR_0_DIAG_F_FALSE                    _MK_ENUM_CONST(0x00000000)                                                       // R-I-V
#define AHCI_PORT_PXSERR_0_DIAG_F_TRUE                     _MK_ENUM_CONST(0x00000001)                                                       // R---V
#define AHCI_PORT_PXSERR_0_DIAG_F_CLEAR                    _MK_ENUM_CONST(0x00000001)                                                       // -W--C
#define AHCI_PORT_PXSERR_0_DIAG_X_SHIFT                     _MK_SHIFT_CONST(26)                                                             // RWIVF
#define AHCI_PORT_PXSERR_0_DIAG_X_FIELD                    (_MK_SHIFT_CONST(0x1) << AHCI_PORT_PXSERR_0_DIAG_X_SHIFT)
#define AHCI_PORT_PXSERR_0_DIAG_X_RANGE                    26:26
#define AHCI_PORT_PXSERR_0_DIAG_X_WOFFSET                  0
#define AHCI_PORT_PXSERR_0_DIAG_X_DEFAULT                  (_MK_MASK_CONST(0x00000000)
#define AHCI_PORT_PXSERR_0_DIAG_X_DEFAULT_MASK             (_MK_MASK_CONST(0x1)
#define AHCI_PORT_PXSERR_0_DIAG_X_SW_DEFAULT               (_MK_MASK_CONST(0x00000000)
#define AHCI_PORT_PXSERR_0_DIAG_X_SW_DEFAULT_MASK          (_MK_MASK_CONST(0x1)
#define AHCI_PORT_PXSERR_0_DIAG_X__NOPRDCHK                _MK_ENUM_CONST(0x00000001)                                                       // ----V
#define AHCI_PORT_PXSERR_0_DIAG_X_FALSE                    _MK_ENUM_CONST(0x00000000)                                                       // R-I-V
#define AHCI_PORT_PXSERR_0_DIAG_X_TRUE                     _MK_ENUM_CONST(0x00000001)                                                       // R---V
#define AHCI_PORT_PXSERR_0_DIAG_X_CLEAR                    _MK_ENUM_CONST(0x00000001)                                                       // -W--C
// 
// 
//              Figure 9-XXX Port Serial ATA Error Register.
// 
// 
// 
// .TITLE Port Serial ATA Active
// .FIELD DS
// This field is bit significant. Each bit corresponds to the TAG and
// command slot of a native queued command, where bit 0 corresponds to TAG 0 and
// command slot 0. This field is set by software prior to issuing a native queued command
// for a particular command slot. Prior to writing PxCI[TAG] to 1, software will set
// DS[TAG] to 1 to indicate that a command with that TAG is outstanding. The device
// clears bits in this field by sending a Set Device Bits FIS to the host. The HBA clears
// bits in this field that are set to 1 in the SActive field of the Set Device Bits FIS. The
// HBA only clears bits that correspond to native queued commands that have completed
// successfully.
// Software should only write this field when PxCMD.ST is set to 1. This field is cleared
// when PxCMD.ST is written from a 1 to a 0 by software. This field is not cleared by a
// COMRESET or a software reset.
// 
// 
// 31           24 23           16 15            8 7             0
// .-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-.
// |0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0| PORT_PXSACT
// `-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-'
// 
#define AHCI_PORT_PXSACT_0                                 0x00000134                                                                       // RW-4R
#define AHCI_PORT_PXSACT_0_SECURE                          0
#define AHCI_PORT_PXSACT_0_WORD_COUNT                      1
#define AHCI_PORT_PXSACT_0_RESET_VAL                       0x0
#define AHCI_PORT_PXSACT_0_RESET_MASK                      0xffffffff
#define AHCI_PORT_PXSACT_0_SW_DEFAULT_VAL                  0x0
#define AHCI_PORT_PXSACT_0_SW_DEFAULT_MASK                 0xffffffff
#define AHCI_PORT_PXSACT_0_READ_MASK                       0xffffffff
#define AHCI_PORT_PXSACT_0_WRITE_MASK                      0xffffffff
#define AHCI_PORT_PXSACT_0_DS0_SHIFT                        _MK_SHIFT_CONST(0)                                                              // RWIVF
#define AHCI_PORT_PXSACT_0_DS0_FIELD                       (_MK_SHIFT_CONST(0x1) << AHCI_PORT_PXSACT_0_DS0_SHIFT)
#define AHCI_PORT_PXSACT_0_DS0_RANGE                       0:0
#define AHCI_PORT_PXSACT_0_DS0_WOFFSET                     0
#define AHCI_PORT_PXSACT_0_DS0_DEFAULT                     (_MK_MASK_CONST(0x00000000)
#define AHCI_PORT_PXSACT_0_DS0_DEFAULT_MASK                (_MK_MASK_CONST(0x1)
#define AHCI_PORT_PXSACT_0_DS0_SW_DEFAULT                  (_MK_MASK_CONST(0x00000000)
#define AHCI_PORT_PXSACT_0_DS0_SW_DEFAULT_MASK             (_MK_MASK_CONST(0x1)
#define AHCI_PORT_PXSACT_0_DS0__NOPRDCHK                   _MK_ENUM_CONST(0x00000001)                                                       // ----V
#define AHCI_PORT_PXSACT_0_DS0_NOT_PRSNT                   _MK_ENUM_CONST(0x00000000)                                                       // R-I-V
#define AHCI_PORT_PXSACT_0_DS0_SET                         _MK_ENUM_CONST(0x00000001)                                                       // R---V
#define AHCI_PORT_PXSACT_0_DS0_PRSNT                       _MK_ENUM_CONST(0x00000001)                                                       // -W--T
#define AHCI_PORT_PXSACT_0_DS1_SHIFT                        _MK_SHIFT_CONST(1)                                                              // RWIVF
#define AHCI_PORT_PXSACT_0_DS1_FIELD                       (_MK_SHIFT_CONST(0x1) << AHCI_PORT_PXSACT_0_DS1_SHIFT)
#define AHCI_PORT_PXSACT_0_DS1_RANGE                       1:1
#define AHCI_PORT_PXSACT_0_DS1_WOFFSET                     0
#define AHCI_PORT_PXSACT_0_DS1_DEFAULT                     (_MK_MASK_CONST(0x00000000)
#define AHCI_PORT_PXSACT_0_DS1_DEFAULT_MASK                (_MK_MASK_CONST(0x1)
#define AHCI_PORT_PXSACT_0_DS1_SW_DEFAULT                  (_MK_MASK_CONST(0x00000000)
#define AHCI_PORT_PXSACT_0_DS1_SW_DEFAULT_MASK             (_MK_MASK_CONST(0x1)
#define AHCI_PORT_PXSACT_0_DS1__NOPRDCHK                   _MK_ENUM_CONST(0x00000001)                                                       // ----V
#define AHCI_PORT_PXSACT_0_DS1_NOT_PRSNT                   _MK_ENUM_CONST(0x00000000)                                                       // R-I-V
#define AHCI_PORT_PXSACT_0_DS1_SET                         _MK_ENUM_CONST(0x00000001)                                                       // R---V
#define AHCI_PORT_PXSACT_0_DS1_PRSNT                       _MK_ENUM_CONST(0x00000001)                                                       // -W--T
#define AHCI_PORT_PXSACT_0_DS2_SHIFT                        _MK_SHIFT_CONST(2)                                                              // RWIVF
#define AHCI_PORT_PXSACT_0_DS2_FIELD                       (_MK_SHIFT_CONST(0x1) << AHCI_PORT_PXSACT_0_DS2_SHIFT)
#define AHCI_PORT_PXSACT_0_DS2_RANGE                       2:2
#define AHCI_PORT_PXSACT_0_DS2_WOFFSET                     0
#define AHCI_PORT_PXSACT_0_DS2_DEFAULT                     (_MK_MASK_CONST(0x00000000)
#define AHCI_PORT_PXSACT_0_DS2_DEFAULT_MASK                (_MK_MASK_CONST(0x1)
#define AHCI_PORT_PXSACT_0_DS2_SW_DEFAULT                  (_MK_MASK_CONST(0x00000000)
#define AHCI_PORT_PXSACT_0_DS2_SW_DEFAULT_MASK             (_MK_MASK_CONST(0x1)
#define AHCI_PORT_PXSACT_0_DS2__NOPRDCHK                   _MK_ENUM_CONST(0x00000001)                                                       // ----V
#define AHCI_PORT_PXSACT_0_DS2_NOT_PRSNT                   _MK_ENUM_CONST(0x00000000)                                                       // R-I-V
#define AHCI_PORT_PXSACT_0_DS2_SET                         _MK_ENUM_CONST(0x00000001)                                                       // R---V
#define AHCI_PORT_PXSACT_0_DS2_PRSNT                       _MK_ENUM_CONST(0x00000001)                                                       // -W--T
#define AHCI_PORT_PXSACT_0_DS3_SHIFT                        _MK_SHIFT_CONST(3)                                                              // RWIVF
#define AHCI_PORT_PXSACT_0_DS3_FIELD                       (_MK_SHIFT_CONST(0x1) << AHCI_PORT_PXSACT_0_DS3_SHIFT)
#define AHCI_PORT_PXSACT_0_DS3_RANGE                       3:3
#define AHCI_PORT_PXSACT_0_DS3_WOFFSET                     0
#define AHCI_PORT_PXSACT_0_DS3_DEFAULT                     (_MK_MASK_CONST(0x00000000)
#define AHCI_PORT_PXSACT_0_DS3_DEFAULT_MASK                (_MK_MASK_CONST(0x1)
#define AHCI_PORT_PXSACT_0_DS3_SW_DEFAULT                  (_MK_MASK_CONST(0x00000000)
#define AHCI_PORT_PXSACT_0_DS3_SW_DEFAULT_MASK             (_MK_MASK_CONST(0x1)
#define AHCI_PORT_PXSACT_0_DS3__NOPRDCHK                   _MK_ENUM_CONST(0x00000001)                                                       // ----V
#define AHCI_PORT_PXSACT_0_DS3_NOT_PRSNT                   _MK_ENUM_CONST(0x00000000)                                                       // R-I-V
#define AHCI_PORT_PXSACT_0_DS3_SET                         _MK_ENUM_CONST(0x00000001)                                                       // R---V
#define AHCI_PORT_PXSACT_0_DS3_PRSNT                       _MK_ENUM_CONST(0x00000001)                                                       // -W--T
#define AHCI_PORT_PXSACT_0_DS4_SHIFT                        _MK_SHIFT_CONST(4)                                                              // RWIVF
#define AHCI_PORT_PXSACT_0_DS4_FIELD                       (_MK_SHIFT_CONST(0x1) << AHCI_PORT_PXSACT_0_DS4_SHIFT)
#define AHCI_PORT_PXSACT_0_DS4_RANGE                       4:4
#define AHCI_PORT_PXSACT_0_DS4_WOFFSET                     0
#define AHCI_PORT_PXSACT_0_DS4_DEFAULT                     (_MK_MASK_CONST(0x00000000)
#define AHCI_PORT_PXSACT_0_DS4_DEFAULT_MASK                (_MK_MASK_CONST(0x1)
#define AHCI_PORT_PXSACT_0_DS4_SW_DEFAULT                  (_MK_MASK_CONST(0x00000000)
#define AHCI_PORT_PXSACT_0_DS4_SW_DEFAULT_MASK             (_MK_MASK_CONST(0x1)
#define AHCI_PORT_PXSACT_0_DS4__NOPRDCHK                   _MK_ENUM_CONST(0x00000001)                                                       // ----V
#define AHCI_PORT_PXSACT_0_DS4_NOT_PRSNT                   _MK_ENUM_CONST(0x00000000)                                                       // R-I-V
#define AHCI_PORT_PXSACT_0_DS4_SET                         _MK_ENUM_CONST(0x00000001)                                                       // R---V
#define AHCI_PORT_PXSACT_0_DS4_PRSNT                       _MK_ENUM_CONST(0x00000001)                                                       // -W--T
#define AHCI_PORT_PXSACT_0_DS5_SHIFT                        _MK_SHIFT_CONST(5)                                                              // RWIVF
#define AHCI_PORT_PXSACT_0_DS5_FIELD                       (_MK_SHIFT_CONST(0x1) << AHCI_PORT_PXSACT_0_DS5_SHIFT)
#define AHCI_PORT_PXSACT_0_DS5_RANGE                       5:5
#define AHCI_PORT_PXSACT_0_DS5_WOFFSET                     0
#define AHCI_PORT_PXSACT_0_DS5_DEFAULT                     (_MK_MASK_CONST(0x00000000)
#define AHCI_PORT_PXSACT_0_DS5_DEFAULT_MASK                (_MK_MASK_CONST(0x1)
#define AHCI_PORT_PXSACT_0_DS5_SW_DEFAULT                  (_MK_MASK_CONST(0x00000000)
#define AHCI_PORT_PXSACT_0_DS5_SW_DEFAULT_MASK             (_MK_MASK_CONST(0x1)
#define AHCI_PORT_PXSACT_0_DS5__NOPRDCHK                   _MK_ENUM_CONST(0x00000001)                                                       // ----V
#define AHCI_PORT_PXSACT_0_DS5_NOT_PRSNT                   _MK_ENUM_CONST(0x00000000)                                                       // R-I-V
#define AHCI_PORT_PXSACT_0_DS5_SET                         _MK_ENUM_CONST(0x00000001)                                                       // R---V
#define AHCI_PORT_PXSACT_0_DS5_PRSNT                       _MK_ENUM_CONST(0x00000001)                                                       // -W--T
#define AHCI_PORT_PXSACT_0_DS6_SHIFT                        _MK_SHIFT_CONST(6)                                                              // RWIVF
#define AHCI_PORT_PXSACT_0_DS6_FIELD                       (_MK_SHIFT_CONST(0x1) << AHCI_PORT_PXSACT_0_DS6_SHIFT)
#define AHCI_PORT_PXSACT_0_DS6_RANGE                       6:6
#define AHCI_PORT_PXSACT_0_DS6_WOFFSET                     0
#define AHCI_PORT_PXSACT_0_DS6_DEFAULT                     (_MK_MASK_CONST(0x00000000)
#define AHCI_PORT_PXSACT_0_DS6_DEFAULT_MASK                (_MK_MASK_CONST(0x1)
#define AHCI_PORT_PXSACT_0_DS6_SW_DEFAULT                  (_MK_MASK_CONST(0x00000000)
#define AHCI_PORT_PXSACT_0_DS6_SW_DEFAULT_MASK             (_MK_MASK_CONST(0x1)
#define AHCI_PORT_PXSACT_0_DS6__NOPRDCHK                   _MK_ENUM_CONST(0x00000001)                                                       // ----V
#define AHCI_PORT_PXSACT_0_DS6_NOT_PRSNT                   _MK_ENUM_CONST(0x00000000)                                                       // R-I-V
#define AHCI_PORT_PXSACT_0_DS6_SET                         _MK_ENUM_CONST(0x00000001)                                                       // R---V
#define AHCI_PORT_PXSACT_0_DS6_PRSNT                       _MK_ENUM_CONST(0x00000001)                                                       // -W--T
#define AHCI_PORT_PXSACT_0_DS7_SHIFT                        _MK_SHIFT_CONST(7)                                                              // RWIVF
#define AHCI_PORT_PXSACT_0_DS7_FIELD                       (_MK_SHIFT_CONST(0x1) << AHCI_PORT_PXSACT_0_DS7_SHIFT)
#define AHCI_PORT_PXSACT_0_DS7_RANGE                       7:7
#define AHCI_PORT_PXSACT_0_DS7_WOFFSET                     0
#define AHCI_PORT_PXSACT_0_DS7_DEFAULT                     (_MK_MASK_CONST(0x00000000)
#define AHCI_PORT_PXSACT_0_DS7_DEFAULT_MASK                (_MK_MASK_CONST(0x1)
#define AHCI_PORT_PXSACT_0_DS7_SW_DEFAULT                  (_MK_MASK_CONST(0x00000000)
#define AHCI_PORT_PXSACT_0_DS7_SW_DEFAULT_MASK             (_MK_MASK_CONST(0x1)
#define AHCI_PORT_PXSACT_0_DS7__NOPRDCHK                   _MK_ENUM_CONST(0x00000001)                                                       // ----V
#define AHCI_PORT_PXSACT_0_DS7_NOT_PRSNT                   _MK_ENUM_CONST(0x00000000)                                                       // R-I-V
#define AHCI_PORT_PXSACT_0_DS7_SET                         _MK_ENUM_CONST(0x00000001)                                                       // R---V
#define AHCI_PORT_PXSACT_0_DS7_PRSNT                       _MK_ENUM_CONST(0x00000001)                                                       // -W--T
#define AHCI_PORT_PXSACT_0_DS8_SHIFT                        _MK_SHIFT_CONST(8)                                                              // RWIVF
#define AHCI_PORT_PXSACT_0_DS8_FIELD                       (_MK_SHIFT_CONST(0x1) << AHCI_PORT_PXSACT_0_DS8_SHIFT)
#define AHCI_PORT_PXSACT_0_DS8_RANGE                       8:8
#define AHCI_PORT_PXSACT_0_DS8_WOFFSET                     0
#define AHCI_PORT_PXSACT_0_DS8_DEFAULT                     (_MK_MASK_CONST(0x00000000)
#define AHCI_PORT_PXSACT_0_DS8_DEFAULT_MASK                (_MK_MASK_CONST(0x1)
#define AHCI_PORT_PXSACT_0_DS8_SW_DEFAULT                  (_MK_MASK_CONST(0x00000000)
#define AHCI_PORT_PXSACT_0_DS8_SW_DEFAULT_MASK             (_MK_MASK_CONST(0x1)
#define AHCI_PORT_PXSACT_0_DS8__NOPRDCHK                   _MK_ENUM_CONST(0x00000001)                                                       // ----V
#define AHCI_PORT_PXSACT_0_DS8_NOT_PRSNT                   _MK_ENUM_CONST(0x00000000)                                                       // R-I-V
#define AHCI_PORT_PXSACT_0_DS8_SET                         _MK_ENUM_CONST(0x00000001)                                                       // R---V
#define AHCI_PORT_PXSACT_0_DS8_PRSNT                       _MK_ENUM_CONST(0x00000001)                                                       // -W--T
#define AHCI_PORT_PXSACT_0_DS9_SHIFT                        _MK_SHIFT_CONST(9)                                                              // RWIVF
#define AHCI_PORT_PXSACT_0_DS9_FIELD                       (_MK_SHIFT_CONST(0x1) << AHCI_PORT_PXSACT_0_DS9_SHIFT)
#define AHCI_PORT_PXSACT_0_DS9_RANGE                       9:9
#define AHCI_PORT_PXSACT_0_DS9_WOFFSET                     0
#define AHCI_PORT_PXSACT_0_DS9_DEFAULT                     (_MK_MASK_CONST(0x00000000)
#define AHCI_PORT_PXSACT_0_DS9_DEFAULT_MASK                (_MK_MASK_CONST(0x1)
#define AHCI_PORT_PXSACT_0_DS9_SW_DEFAULT                  (_MK_MASK_CONST(0x00000000)
#define AHCI_PORT_PXSACT_0_DS9_SW_DEFAULT_MASK             (_MK_MASK_CONST(0x1)
#define AHCI_PORT_PXSACT_0_DS9__NOPRDCHK                   _MK_ENUM_CONST(0x00000001)                                                       // ----V
#define AHCI_PORT_PXSACT_0_DS9_NOT_PRSNT                   _MK_ENUM_CONST(0x00000000)                                                       // R-I-V
#define AHCI_PORT_PXSACT_0_DS9_SET                         _MK_ENUM_CONST(0x00000001)                                                       // R---V
#define AHCI_PORT_PXSACT_0_DS9_PRSNT                       _MK_ENUM_CONST(0x00000001)                                                       // -W--T
#define AHCI_PORT_PXSACT_0_DS10_SHIFT                       _MK_SHIFT_CONST(10)                                                             // RWIVF
#define AHCI_PORT_PXSACT_0_DS10_FIELD                      (_MK_SHIFT_CONST(0x1) << AHCI_PORT_PXSACT_0_DS10_SHIFT)
#define AHCI_PORT_PXSACT_0_DS10_RANGE                      10:10
#define AHCI_PORT_PXSACT_0_DS10_WOFFSET                    0
#define AHCI_PORT_PXSACT_0_DS10_DEFAULT                    (_MK_MASK_CONST(0x00000000)
#define AHCI_PORT_PXSACT_0_DS10_DEFAULT_MASK               (_MK_MASK_CONST(0x1)
#define AHCI_PORT_PXSACT_0_DS10_SW_DEFAULT                 (_MK_MASK_CONST(0x00000000)
#define AHCI_PORT_PXSACT_0_DS10_SW_DEFAULT_MASK            (_MK_MASK_CONST(0x1)
#define AHCI_PORT_PXSACT_0_DS10__NOPRDCHK                  _MK_ENUM_CONST(0x00000001)                                                       // ----V
#define AHCI_PORT_PXSACT_0_DS10_NOT_PRSNT                  _MK_ENUM_CONST(0x00000000)                                                       // R-I-V
#define AHCI_PORT_PXSACT_0_DS10_SET                        _MK_ENUM_CONST(0x00000001)                                                       // R---V
#define AHCI_PORT_PXSACT_0_DS10_PRSNT                      _MK_ENUM_CONST(0x00000001)                                                       // -W--T
#define AHCI_PORT_PXSACT_0_DS11_SHIFT                       _MK_SHIFT_CONST(11)                                                             // RWIVF
#define AHCI_PORT_PXSACT_0_DS11_FIELD                      (_MK_SHIFT_CONST(0x1) << AHCI_PORT_PXSACT_0_DS11_SHIFT)
#define AHCI_PORT_PXSACT_0_DS11_RANGE                      11:11
#define AHCI_PORT_PXSACT_0_DS11_WOFFSET                    0
#define AHCI_PORT_PXSACT_0_DS11_DEFAULT                    (_MK_MASK_CONST(0x00000000)
#define AHCI_PORT_PXSACT_0_DS11_DEFAULT_MASK               (_MK_MASK_CONST(0x1)
#define AHCI_PORT_PXSACT_0_DS11_SW_DEFAULT                 (_MK_MASK_CONST(0x00000000)
#define AHCI_PORT_PXSACT_0_DS11_SW_DEFAULT_MASK            (_MK_MASK_CONST(0x1)
#define AHCI_PORT_PXSACT_0_DS11__NOPRDCHK                  _MK_ENUM_CONST(0x00000001)                                                       // ----V
#define AHCI_PORT_PXSACT_0_DS11_NOT_PRSNT                  _MK_ENUM_CONST(0x00000000)                                                       // R-I-V
#define AHCI_PORT_PXSACT_0_DS11_SET                        _MK_ENUM_CONST(0x00000001)                                                       // R---V
#define AHCI_PORT_PXSACT_0_DS11_PRSNT                      _MK_ENUM_CONST(0x00000001)                                                       // -W--T
#define AHCI_PORT_PXSACT_0_DS12_SHIFT                       _MK_SHIFT_CONST(12)                                                             // RWIVF
#define AHCI_PORT_PXSACT_0_DS12_FIELD                      (_MK_SHIFT_CONST(0x1) << AHCI_PORT_PXSACT_0_DS12_SHIFT)
#define AHCI_PORT_PXSACT_0_DS12_RANGE                      12:12
#define AHCI_PORT_PXSACT_0_DS12_WOFFSET                    0
#define AHCI_PORT_PXSACT_0_DS12_DEFAULT                    (_MK_MASK_CONST(0x00000000)
#define AHCI_PORT_PXSACT_0_DS12_DEFAULT_MASK               (_MK_MASK_CONST(0x1)
#define AHCI_PORT_PXSACT_0_DS12_SW_DEFAULT                 (_MK_MASK_CONST(0x00000000)
#define AHCI_PORT_PXSACT_0_DS12_SW_DEFAULT_MASK            (_MK_MASK_CONST(0x1)
#define AHCI_PORT_PXSACT_0_DS12__NOPRDCHK                  _MK_ENUM_CONST(0x00000001)                                                       // ----V
#define AHCI_PORT_PXSACT_0_DS12_NOT_PRSNT                  _MK_ENUM_CONST(0x00000000)                                                       // R-I-V
#define AHCI_PORT_PXSACT_0_DS12_SET                        _MK_ENUM_CONST(0x00000001)                                                       // R---V
#define AHCI_PORT_PXSACT_0_DS12_PRSNT                      _MK_ENUM_CONST(0x00000001)                                                       // -W--T
#define AHCI_PORT_PXSACT_0_DS13_SHIFT                       _MK_SHIFT_CONST(13)                                                             // RWIVF
#define AHCI_PORT_PXSACT_0_DS13_FIELD                      (_MK_SHIFT_CONST(0x1) << AHCI_PORT_PXSACT_0_DS13_SHIFT)
#define AHCI_PORT_PXSACT_0_DS13_RANGE                      13:13
#define AHCI_PORT_PXSACT_0_DS13_WOFFSET                    0
#define AHCI_PORT_PXSACT_0_DS13_DEFAULT                    (_MK_MASK_CONST(0x00000000)
#define AHCI_PORT_PXSACT_0_DS13_DEFAULT_MASK               (_MK_MASK_CONST(0x1)
#define AHCI_PORT_PXSACT_0_DS13_SW_DEFAULT                 (_MK_MASK_CONST(0x00000000)
#define AHCI_PORT_PXSACT_0_DS13_SW_DEFAULT_MASK            (_MK_MASK_CONST(0x1)
#define AHCI_PORT_PXSACT_0_DS13__NOPRDCHK                  _MK_ENUM_CONST(0x00000001)                                                       // ----V
#define AHCI_PORT_PXSACT_0_DS13_NOT_PRSNT                  _MK_ENUM_CONST(0x00000000)                                                       // R-I-V
#define AHCI_PORT_PXSACT_0_DS13_SET                        _MK_ENUM_CONST(0x00000001)                                                       // R---V
#define AHCI_PORT_PXSACT_0_DS13_PRSNT                      _MK_ENUM_CONST(0x00000001)                                                       // -W--T
#define AHCI_PORT_PXSACT_0_DS14_SHIFT                       _MK_SHIFT_CONST(14)                                                             // RWIVF
#define AHCI_PORT_PXSACT_0_DS14_FIELD                      (_MK_SHIFT_CONST(0x1) << AHCI_PORT_PXSACT_0_DS14_SHIFT)
#define AHCI_PORT_PXSACT_0_DS14_RANGE                      14:14
#define AHCI_PORT_PXSACT_0_DS14_WOFFSET                    0
#define AHCI_PORT_PXSACT_0_DS14_DEFAULT                    (_MK_MASK_CONST(0x00000000)
#define AHCI_PORT_PXSACT_0_DS14_DEFAULT_MASK               (_MK_MASK_CONST(0x1)
#define AHCI_PORT_PXSACT_0_DS14_SW_DEFAULT                 (_MK_MASK_CONST(0x00000000)
#define AHCI_PORT_PXSACT_0_DS14_SW_DEFAULT_MASK            (_MK_MASK_CONST(0x1)
#define AHCI_PORT_PXSACT_0_DS14__NOPRDCHK                  _MK_ENUM_CONST(0x00000001)                                                       // ----V
#define AHCI_PORT_PXSACT_0_DS14_NOT_PRSNT                  _MK_ENUM_CONST(0x00000000)                                                       // R-I-V
#define AHCI_PORT_PXSACT_0_DS14_SET                        _MK_ENUM_CONST(0x00000001)                                                       // R---V
#define AHCI_PORT_PXSACT_0_DS14_PRSNT                      _MK_ENUM_CONST(0x00000001)                                                       // -W--T
#define AHCI_PORT_PXSACT_0_DS15_SHIFT                       _MK_SHIFT_CONST(15)                                                             // RWIVF
#define AHCI_PORT_PXSACT_0_DS15_FIELD                      (_MK_SHIFT_CONST(0x1) << AHCI_PORT_PXSACT_0_DS15_SHIFT)
#define AHCI_PORT_PXSACT_0_DS15_RANGE                      15:15
#define AHCI_PORT_PXSACT_0_DS15_WOFFSET                    0
#define AHCI_PORT_PXSACT_0_DS15_DEFAULT                    (_MK_MASK_CONST(0x00000000)
#define AHCI_PORT_PXSACT_0_DS15_DEFAULT_MASK               (_MK_MASK_CONST(0x1)
#define AHCI_PORT_PXSACT_0_DS15_SW_DEFAULT                 (_MK_MASK_CONST(0x00000000)
#define AHCI_PORT_PXSACT_0_DS15_SW_DEFAULT_MASK            (_MK_MASK_CONST(0x1)
#define AHCI_PORT_PXSACT_0_DS15__NOPRDCHK                  _MK_ENUM_CONST(0x00000001)                                                       // ----V
#define AHCI_PORT_PXSACT_0_DS15_NOT_PRSNT                  _MK_ENUM_CONST(0x00000000)                                                       // R-I-V
#define AHCI_PORT_PXSACT_0_DS15_SET                        _MK_ENUM_CONST(0x00000001)                                                       // R---V
#define AHCI_PORT_PXSACT_0_DS15_PRSNT                      _MK_ENUM_CONST(0x00000001)                                                       // -W--T
#define AHCI_PORT_PXSACT_0_DS16_SHIFT                       _MK_SHIFT_CONST(16)                                                             // RWIVF
#define AHCI_PORT_PXSACT_0_DS16_FIELD                      (_MK_SHIFT_CONST(0x1) << AHCI_PORT_PXSACT_0_DS16_SHIFT)
#define AHCI_PORT_PXSACT_0_DS16_RANGE                      16:16
#define AHCI_PORT_PXSACT_0_DS16_WOFFSET                    0
#define AHCI_PORT_PXSACT_0_DS16_DEFAULT                    (_MK_MASK_CONST(0x00000000)
#define AHCI_PORT_PXSACT_0_DS16_DEFAULT_MASK               (_MK_MASK_CONST(0x1)
#define AHCI_PORT_PXSACT_0_DS16_SW_DEFAULT                 (_MK_MASK_CONST(0x00000000)
#define AHCI_PORT_PXSACT_0_DS16_SW_DEFAULT_MASK            (_MK_MASK_CONST(0x1)
#define AHCI_PORT_PXSACT_0_DS16__NOPRDCHK                  _MK_ENUM_CONST(0x00000001)                                                       // ----V
#define AHCI_PORT_PXSACT_0_DS16_NOT_PRSNT                  _MK_ENUM_CONST(0x00000000)                                                       // R-I-V
#define AHCI_PORT_PXSACT_0_DS16_SET                        _MK_ENUM_CONST(0x00000001)                                                       // R---V
#define AHCI_PORT_PXSACT_0_DS16_PRSNT                      _MK_ENUM_CONST(0x00000001)                                                       // -W--T
#define AHCI_PORT_PXSACT_0_DS17_SHIFT                       _MK_SHIFT_CONST(17)                                                             // RWIVF
#define AHCI_PORT_PXSACT_0_DS17_FIELD                      (_MK_SHIFT_CONST(0x1) << AHCI_PORT_PXSACT_0_DS17_SHIFT)
#define AHCI_PORT_PXSACT_0_DS17_RANGE                      17:17
#define AHCI_PORT_PXSACT_0_DS17_WOFFSET                    0
#define AHCI_PORT_PXSACT_0_DS17_DEFAULT                    (_MK_MASK_CONST(0x00000000)
#define AHCI_PORT_PXSACT_0_DS17_DEFAULT_MASK               (_MK_MASK_CONST(0x1)
#define AHCI_PORT_PXSACT_0_DS17_SW_DEFAULT                 (_MK_MASK_CONST(0x00000000)
#define AHCI_PORT_PXSACT_0_DS17_SW_DEFAULT_MASK            (_MK_MASK_CONST(0x1)
#define AHCI_PORT_PXSACT_0_DS17__NOPRDCHK                  _MK_ENUM_CONST(0x00000001)                                                       // ----V
#define AHCI_PORT_PXSACT_0_DS17_NOT_PRSNT                  _MK_ENUM_CONST(0x00000000)                                                       // R-I-V
#define AHCI_PORT_PXSACT_0_DS17_SET                        _MK_ENUM_CONST(0x00000001)                                                       // R---V
#define AHCI_PORT_PXSACT_0_DS17_PRSNT                      _MK_ENUM_CONST(0x00000001)                                                       // -W--T
#define AHCI_PORT_PXSACT_0_DS18_SHIFT                       _MK_SHIFT_CONST(18)                                                             // RWIVF
#define AHCI_PORT_PXSACT_0_DS18_FIELD                      (_MK_SHIFT_CONST(0x1) << AHCI_PORT_PXSACT_0_DS18_SHIFT)
#define AHCI_PORT_PXSACT_0_DS18_RANGE                      18:18
#define AHCI_PORT_PXSACT_0_DS18_WOFFSET                    0
#define AHCI_PORT_PXSACT_0_DS18_DEFAULT                    (_MK_MASK_CONST(0x00000000)
#define AHCI_PORT_PXSACT_0_DS18_DEFAULT_MASK               (_MK_MASK_CONST(0x1)
#define AHCI_PORT_PXSACT_0_DS18_SW_DEFAULT                 (_MK_MASK_CONST(0x00000000)
#define AHCI_PORT_PXSACT_0_DS18_SW_DEFAULT_MASK            (_MK_MASK_CONST(0x1)
#define AHCI_PORT_PXSACT_0_DS18__NOPRDCHK                  _MK_ENUM_CONST(0x00000001)                                                       // ----V
#define AHCI_PORT_PXSACT_0_DS18_NOT_PRSNT                  _MK_ENUM_CONST(0x00000000)                                                       // R-I-V
#define AHCI_PORT_PXSACT_0_DS18_SET                        _MK_ENUM_CONST(0x00000001)                                                       // R---V
#define AHCI_PORT_PXSACT_0_DS18_PRSNT                      _MK_ENUM_CONST(0x00000001)                                                       // -W--T
#define AHCI_PORT_PXSACT_0_DS19_SHIFT                       _MK_SHIFT_CONST(19)                                                             // RWIVF
#define AHCI_PORT_PXSACT_0_DS19_FIELD                      (_MK_SHIFT_CONST(0x1) << AHCI_PORT_PXSACT_0_DS19_SHIFT)
#define AHCI_PORT_PXSACT_0_DS19_RANGE                      19:19
#define AHCI_PORT_PXSACT_0_DS19_WOFFSET                    0
#define AHCI_PORT_PXSACT_0_DS19_DEFAULT                    (_MK_MASK_CONST(0x00000000)
#define AHCI_PORT_PXSACT_0_DS19_DEFAULT_MASK               (_MK_MASK_CONST(0x1)
#define AHCI_PORT_PXSACT_0_DS19_SW_DEFAULT                 (_MK_MASK_CONST(0x00000000)
#define AHCI_PORT_PXSACT_0_DS19_SW_DEFAULT_MASK            (_MK_MASK_CONST(0x1)
#define AHCI_PORT_PXSACT_0_DS19__NOPRDCHK                  _MK_ENUM_CONST(0x00000001)                                                       // ----V
#define AHCI_PORT_PXSACT_0_DS19_NOT_PRSNT                  _MK_ENUM_CONST(0x00000000)                                                       // R-I-V
#define AHCI_PORT_PXSACT_0_DS19_SET                        _MK_ENUM_CONST(0x00000001)                                                       // R---V
#define AHCI_PORT_PXSACT_0_DS19_PRSNT                      _MK_ENUM_CONST(0x00000001)                                                       // -W--T
#define AHCI_PORT_PXSACT_0_DS20_SHIFT                       _MK_SHIFT_CONST(20)                                                             // RWIVF
#define AHCI_PORT_PXSACT_0_DS20_FIELD                      (_MK_SHIFT_CONST(0x1) << AHCI_PORT_PXSACT_0_DS20_SHIFT)
#define AHCI_PORT_PXSACT_0_DS20_RANGE                      20:20
#define AHCI_PORT_PXSACT_0_DS20_WOFFSET                    0
#define AHCI_PORT_PXSACT_0_DS20_DEFAULT                    (_MK_MASK_CONST(0x00000000)
#define AHCI_PORT_PXSACT_0_DS20_DEFAULT_MASK               (_MK_MASK_CONST(0x1)
#define AHCI_PORT_PXSACT_0_DS20_SW_DEFAULT                 (_MK_MASK_CONST(0x00000000)
#define AHCI_PORT_PXSACT_0_DS20_SW_DEFAULT_MASK            (_MK_MASK_CONST(0x1)
#define AHCI_PORT_PXSACT_0_DS20__NOPRDCHK                  _MK_ENUM_CONST(0x00000001)                                                       // ----V
#define AHCI_PORT_PXSACT_0_DS20_NOT_PRSNT                  _MK_ENUM_CONST(0x00000000)                                                       // R-I-V
#define AHCI_PORT_PXSACT_0_DS20_SET                        _MK_ENUM_CONST(0x00000001)                                                       // R---V
#define AHCI_PORT_PXSACT_0_DS20_PRSNT                      _MK_ENUM_CONST(0x00000001)                                                       // -W--T
#define AHCI_PORT_PXSACT_0_DS21_SHIFT                       _MK_SHIFT_CONST(21)                                                             // RWIVF
#define AHCI_PORT_PXSACT_0_DS21_FIELD                      (_MK_SHIFT_CONST(0x1) << AHCI_PORT_PXSACT_0_DS21_SHIFT)
#define AHCI_PORT_PXSACT_0_DS21_RANGE                      21:21
#define AHCI_PORT_PXSACT_0_DS21_WOFFSET                    0
#define AHCI_PORT_PXSACT_0_DS21_DEFAULT                    (_MK_MASK_CONST(0x00000000)
#define AHCI_PORT_PXSACT_0_DS21_DEFAULT_MASK               (_MK_MASK_CONST(0x1)
#define AHCI_PORT_PXSACT_0_DS21_SW_DEFAULT                 (_MK_MASK_CONST(0x00000000)
#define AHCI_PORT_PXSACT_0_DS21_SW_DEFAULT_MASK            (_MK_MASK_CONST(0x1)
#define AHCI_PORT_PXSACT_0_DS21__NOPRDCHK                  _MK_ENUM_CONST(0x00000001)                                                       // ----V
#define AHCI_PORT_PXSACT_0_DS21_NOT_PRSNT                  _MK_ENUM_CONST(0x00000000)                                                       // R-I-V
#define AHCI_PORT_PXSACT_0_DS21_SET                        _MK_ENUM_CONST(0x00000001)                                                       // R---V
#define AHCI_PORT_PXSACT_0_DS21_PRSNT                      _MK_ENUM_CONST(0x00000001)                                                       // -W--T
#define AHCI_PORT_PXSACT_0_DS22_SHIFT                       _MK_SHIFT_CONST(22)                                                             // RWIVF
#define AHCI_PORT_PXSACT_0_DS22_FIELD                      (_MK_SHIFT_CONST(0x1) << AHCI_PORT_PXSACT_0_DS22_SHIFT)
#define AHCI_PORT_PXSACT_0_DS22_RANGE                      22:22
#define AHCI_PORT_PXSACT_0_DS22_WOFFSET                    0
#define AHCI_PORT_PXSACT_0_DS22_DEFAULT                    (_MK_MASK_CONST(0x00000000)
#define AHCI_PORT_PXSACT_0_DS22_DEFAULT_MASK               (_MK_MASK_CONST(0x1)
#define AHCI_PORT_PXSACT_0_DS22_SW_DEFAULT                 (_MK_MASK_CONST(0x00000000)
#define AHCI_PORT_PXSACT_0_DS22_SW_DEFAULT_MASK            (_MK_MASK_CONST(0x1)
#define AHCI_PORT_PXSACT_0_DS22__NOPRDCHK                  _MK_ENUM_CONST(0x00000001)                                                       // ----V
#define AHCI_PORT_PXSACT_0_DS22_NOT_PRSNT                  _MK_ENUM_CONST(0x00000000)                                                       // R-I-V
#define AHCI_PORT_PXSACT_0_DS22_SET                        _MK_ENUM_CONST(0x00000001)                                                       // R---V
#define AHCI_PORT_PXSACT_0_DS22_PRSNT                      _MK_ENUM_CONST(0x00000001)                                                       // -W--T
#define AHCI_PORT_PXSACT_0_DS23_SHIFT                       _MK_SHIFT_CONST(23)                                                             // RWIVF
#define AHCI_PORT_PXSACT_0_DS23_FIELD                      (_MK_SHIFT_CONST(0x1) << AHCI_PORT_PXSACT_0_DS23_SHIFT)
#define AHCI_PORT_PXSACT_0_DS23_RANGE                      23:23
#define AHCI_PORT_PXSACT_0_DS23_WOFFSET                    0
#define AHCI_PORT_PXSACT_0_DS23_DEFAULT                    (_MK_MASK_CONST(0x00000000)
#define AHCI_PORT_PXSACT_0_DS23_DEFAULT_MASK               (_MK_MASK_CONST(0x1)
#define AHCI_PORT_PXSACT_0_DS23_SW_DEFAULT                 (_MK_MASK_CONST(0x00000000)
#define AHCI_PORT_PXSACT_0_DS23_SW_DEFAULT_MASK            (_MK_MASK_CONST(0x1)
#define AHCI_PORT_PXSACT_0_DS23__NOPRDCHK                  _MK_ENUM_CONST(0x00000001)                                                       // ----V
#define AHCI_PORT_PXSACT_0_DS23_NOT_PRSNT                  _MK_ENUM_CONST(0x00000000)                                                       // R-I-V
#define AHCI_PORT_PXSACT_0_DS23_SET                        _MK_ENUM_CONST(0x00000001)                                                       // R---V
#define AHCI_PORT_PXSACT_0_DS23_PRSNT                      _MK_ENUM_CONST(0x00000001)                                                       // -W--T
#define AHCI_PORT_PXSACT_0_DS24_SHIFT                       _MK_SHIFT_CONST(24)                                                             // RWIVF
#define AHCI_PORT_PXSACT_0_DS24_FIELD                      (_MK_SHIFT_CONST(0x1) << AHCI_PORT_PXSACT_0_DS24_SHIFT)
#define AHCI_PORT_PXSACT_0_DS24_RANGE                      24:24
#define AHCI_PORT_PXSACT_0_DS24_WOFFSET                    0
#define AHCI_PORT_PXSACT_0_DS24_DEFAULT                    (_MK_MASK_CONST(0x00000000)
#define AHCI_PORT_PXSACT_0_DS24_DEFAULT_MASK               (_MK_MASK_CONST(0x1)
#define AHCI_PORT_PXSACT_0_DS24_SW_DEFAULT                 (_MK_MASK_CONST(0x00000000)
#define AHCI_PORT_PXSACT_0_DS24_SW_DEFAULT_MASK            (_MK_MASK_CONST(0x1)
#define AHCI_PORT_PXSACT_0_DS24__NOPRDCHK                  _MK_ENUM_CONST(0x00000001)                                                       // ----V
#define AHCI_PORT_PXSACT_0_DS24_NOT_PRSNT                  _MK_ENUM_CONST(0x00000000)                                                       // R-I-V
#define AHCI_PORT_PXSACT_0_DS24_SET                        _MK_ENUM_CONST(0x00000001)                                                       // R---V
#define AHCI_PORT_PXSACT_0_DS24_PRSNT                      _MK_ENUM_CONST(0x00000001)                                                       // -W--T
#define AHCI_PORT_PXSACT_0_DS25_SHIFT                       _MK_SHIFT_CONST(25)                                                             // RWIVF
#define AHCI_PORT_PXSACT_0_DS25_FIELD                      (_MK_SHIFT_CONST(0x1) << AHCI_PORT_PXSACT_0_DS25_SHIFT)
#define AHCI_PORT_PXSACT_0_DS25_RANGE                      25:25
#define AHCI_PORT_PXSACT_0_DS25_WOFFSET                    0
#define AHCI_PORT_PXSACT_0_DS25_DEFAULT                    (_MK_MASK_CONST(0x00000000)
#define AHCI_PORT_PXSACT_0_DS25_DEFAULT_MASK               (_MK_MASK_CONST(0x1)
#define AHCI_PORT_PXSACT_0_DS25_SW_DEFAULT                 (_MK_MASK_CONST(0x00000000)
#define AHCI_PORT_PXSACT_0_DS25_SW_DEFAULT_MASK            (_MK_MASK_CONST(0x1)
#define AHCI_PORT_PXSACT_0_DS25__NOPRDCHK                  _MK_ENUM_CONST(0x00000001)                                                       // ----V
#define AHCI_PORT_PXSACT_0_DS25_NOT_PRSNT                  _MK_ENUM_CONST(0x00000000)                                                       // R-I-V
#define AHCI_PORT_PXSACT_0_DS25_SET                        _MK_ENUM_CONST(0x00000001)                                                       // R---V
#define AHCI_PORT_PXSACT_0_DS25_PRSNT                      _MK_ENUM_CONST(0x00000001)                                                       // -W--T
#define AHCI_PORT_PXSACT_0_DS26_SHIFT                       _MK_SHIFT_CONST(26)                                                             // RWIVF
#define AHCI_PORT_PXSACT_0_DS26_FIELD                      (_MK_SHIFT_CONST(0x1) << AHCI_PORT_PXSACT_0_DS26_SHIFT)
#define AHCI_PORT_PXSACT_0_DS26_RANGE                      26:26
#define AHCI_PORT_PXSACT_0_DS26_WOFFSET                    0
#define AHCI_PORT_PXSACT_0_DS26_DEFAULT                    (_MK_MASK_CONST(0x00000000)
#define AHCI_PORT_PXSACT_0_DS26_DEFAULT_MASK               (_MK_MASK_CONST(0x1)
#define AHCI_PORT_PXSACT_0_DS26_SW_DEFAULT                 (_MK_MASK_CONST(0x00000000)
#define AHCI_PORT_PXSACT_0_DS26_SW_DEFAULT_MASK            (_MK_MASK_CONST(0x1)
#define AHCI_PORT_PXSACT_0_DS26__NOPRDCHK                  _MK_ENUM_CONST(0x00000001)                                                       // ----V
#define AHCI_PORT_PXSACT_0_DS26_NOT_PRSNT                  _MK_ENUM_CONST(0x00000000)                                                       // R-I-V
#define AHCI_PORT_PXSACT_0_DS26_SET                        _MK_ENUM_CONST(0x00000001)                                                       // R---V
#define AHCI_PORT_PXSACT_0_DS26_PRSNT                      _MK_ENUM_CONST(0x00000001)                                                       // -W--T
#define AHCI_PORT_PXSACT_0_DS27_SHIFT                       _MK_SHIFT_CONST(27)                                                             // RWIVF
#define AHCI_PORT_PXSACT_0_DS27_FIELD                      (_MK_SHIFT_CONST(0x1) << AHCI_PORT_PXSACT_0_DS27_SHIFT)
#define AHCI_PORT_PXSACT_0_DS27_RANGE                      27:27
#define AHCI_PORT_PXSACT_0_DS27_WOFFSET                    0
#define AHCI_PORT_PXSACT_0_DS27_DEFAULT                    (_MK_MASK_CONST(0x00000000)
#define AHCI_PORT_PXSACT_0_DS27_DEFAULT_MASK               (_MK_MASK_CONST(0x1)
#define AHCI_PORT_PXSACT_0_DS27_SW_DEFAULT                 (_MK_MASK_CONST(0x00000000)
#define AHCI_PORT_PXSACT_0_DS27_SW_DEFAULT_MASK            (_MK_MASK_CONST(0x1)
#define AHCI_PORT_PXSACT_0_DS27__NOPRDCHK                  _MK_ENUM_CONST(0x00000001)                                                       // ----V
#define AHCI_PORT_PXSACT_0_DS27_NOT_PRSNT                  _MK_ENUM_CONST(0x00000000)                                                       // R-I-V
#define AHCI_PORT_PXSACT_0_DS27_SET                        _MK_ENUM_CONST(0x00000001)                                                       // R---V
#define AHCI_PORT_PXSACT_0_DS27_PRSNT                      _MK_ENUM_CONST(0x00000001)                                                       // -W--T
#define AHCI_PORT_PXSACT_0_DS28_SHIFT                       _MK_SHIFT_CONST(28)                                                             // RWIVF
#define AHCI_PORT_PXSACT_0_DS28_FIELD                      (_MK_SHIFT_CONST(0x1) << AHCI_PORT_PXSACT_0_DS28_SHIFT)
#define AHCI_PORT_PXSACT_0_DS28_RANGE                      28:28
#define AHCI_PORT_PXSACT_0_DS28_WOFFSET                    0
#define AHCI_PORT_PXSACT_0_DS28_DEFAULT                    (_MK_MASK_CONST(0x00000000)
#define AHCI_PORT_PXSACT_0_DS28_DEFAULT_MASK               (_MK_MASK_CONST(0x1)
#define AHCI_PORT_PXSACT_0_DS28_SW_DEFAULT                 (_MK_MASK_CONST(0x00000000)
#define AHCI_PORT_PXSACT_0_DS28_SW_DEFAULT_MASK            (_MK_MASK_CONST(0x1)
#define AHCI_PORT_PXSACT_0_DS28__NOPRDCHK                  _MK_ENUM_CONST(0x00000001)                                                       // ----V
#define AHCI_PORT_PXSACT_0_DS28_NOT_PRSNT                  _MK_ENUM_CONST(0x00000000)                                                       // R-I-V
#define AHCI_PORT_PXSACT_0_DS28_SET                        _MK_ENUM_CONST(0x00000001)                                                       // R---V
#define AHCI_PORT_PXSACT_0_DS28_PRSNT                      _MK_ENUM_CONST(0x00000001)                                                       // -W--T
#define AHCI_PORT_PXSACT_0_DS29_SHIFT                       _MK_SHIFT_CONST(29)                                                             // RWIVF
#define AHCI_PORT_PXSACT_0_DS29_FIELD                      (_MK_SHIFT_CONST(0x1) << AHCI_PORT_PXSACT_0_DS29_SHIFT)
#define AHCI_PORT_PXSACT_0_DS29_RANGE                      29:29
#define AHCI_PORT_PXSACT_0_DS29_WOFFSET                    0
#define AHCI_PORT_PXSACT_0_DS29_DEFAULT                    (_MK_MASK_CONST(0x00000000)
#define AHCI_PORT_PXSACT_0_DS29_DEFAULT_MASK               (_MK_MASK_CONST(0x1)
#define AHCI_PORT_PXSACT_0_DS29_SW_DEFAULT                 (_MK_MASK_CONST(0x00000000)
#define AHCI_PORT_PXSACT_0_DS29_SW_DEFAULT_MASK            (_MK_MASK_CONST(0x1)
#define AHCI_PORT_PXSACT_0_DS29__NOPRDCHK                  _MK_ENUM_CONST(0x00000001)                                                       // ----V
#define AHCI_PORT_PXSACT_0_DS29_NOT_PRSNT                  _MK_ENUM_CONST(0x00000000)                                                       // R-I-V
#define AHCI_PORT_PXSACT_0_DS29_SET                        _MK_ENUM_CONST(0x00000001)                                                       // R---V
#define AHCI_PORT_PXSACT_0_DS29_PRSNT                      _MK_ENUM_CONST(0x00000001)                                                       // -W--T
#define AHCI_PORT_PXSACT_0_DS30_SHIFT                       _MK_SHIFT_CONST(30)                                                             // RWIVF
#define AHCI_PORT_PXSACT_0_DS30_FIELD                      (_MK_SHIFT_CONST(0x1) << AHCI_PORT_PXSACT_0_DS30_SHIFT)
#define AHCI_PORT_PXSACT_0_DS30_RANGE                      30:30
#define AHCI_PORT_PXSACT_0_DS30_WOFFSET                    0
#define AHCI_PORT_PXSACT_0_DS30_DEFAULT                    (_MK_MASK_CONST(0x00000000)
#define AHCI_PORT_PXSACT_0_DS30_DEFAULT_MASK               (_MK_MASK_CONST(0x1)
#define AHCI_PORT_PXSACT_0_DS30_SW_DEFAULT                 (_MK_MASK_CONST(0x00000000)
#define AHCI_PORT_PXSACT_0_DS30_SW_DEFAULT_MASK            (_MK_MASK_CONST(0x1)
#define AHCI_PORT_PXSACT_0_DS30__NOPRDCHK                  _MK_ENUM_CONST(0x00000001)                                                       // ----V
#define AHCI_PORT_PXSACT_0_DS30_NOT_PRSNT                  _MK_ENUM_CONST(0x00000000)                                                       // R-I-V
#define AHCI_PORT_PXSACT_0_DS30_SET                        _MK_ENUM_CONST(0x00000001)                                                       // R---V
#define AHCI_PORT_PXSACT_0_DS30_PRSNT                      _MK_ENUM_CONST(0x00000001)                                                       // -W--T
#define AHCI_PORT_PXSACT_0_DS31_SHIFT                       _MK_SHIFT_CONST(31)                                                             // RWIVF
#define AHCI_PORT_PXSACT_0_DS31_FIELD                      (_MK_SHIFT_CONST(0x1) << AHCI_PORT_PXSACT_0_DS31_SHIFT)
#define AHCI_PORT_PXSACT_0_DS31_RANGE                      31:31
#define AHCI_PORT_PXSACT_0_DS31_WOFFSET                    0
#define AHCI_PORT_PXSACT_0_DS31_DEFAULT                    (_MK_MASK_CONST(0x00000000)
#define AHCI_PORT_PXSACT_0_DS31_DEFAULT_MASK               (_MK_MASK_CONST(0x1)
#define AHCI_PORT_PXSACT_0_DS31_SW_DEFAULT                 (_MK_MASK_CONST(0x00000000)
#define AHCI_PORT_PXSACT_0_DS31_SW_DEFAULT_MASK            (_MK_MASK_CONST(0x1)
#define AHCI_PORT_PXSACT_0_DS31__NOPRDCHK                  _MK_ENUM_CONST(0x00000001)                                                       // ----V
#define AHCI_PORT_PXSACT_0_DS31_NOT_PRSNT                  _MK_ENUM_CONST(0x00000000)                                                       // R-I-V
#define AHCI_PORT_PXSACT_0_DS31_SET                        _MK_ENUM_CONST(0x00000001)                                                       // R---V
#define AHCI_PORT_PXSACT_0_DS31_PRSNT                      _MK_ENUM_CONST(0x00000001)                                                       // -W--T
// 
// 
//              Figure 9-XXX Port Serial ATA Active Register.
// 
// 
// 
// .TITLE Port Command Issue
// .FIELD CI
// This field is bit significant. Each bit corresponds to a
// command slot, where bit 0 corresponds to command slot 0. This field is set by software
// to indicate to the HBA that a command has been built in system memory for a
// command slot and may be sent to the device. When the HBA receives a FIS which
// clears the BSY, DRQ, and ERR bits for the command, it clears the corresponding bit in
// this register for that command slot. Bits in this field shall only be set to 1 by software
// when PxCMD.ST is set to 1.
// This field is also cleared when PxCMD.ST is written from a 1 to a 0 by software
// 
// 
// 31           24 23           16 15            8 7             0
// .-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-.
// |0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0| PORT_PXCI
// `-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-'
// 
#define AHCI_PORT_PXCI_0                                   0x00000138                                                                       // RW-4R
#define AHCI_PORT_PXCI_0_SECURE                            0
#define AHCI_PORT_PXCI_0_WORD_COUNT                        1
#define AHCI_PORT_PXCI_0_RESET_VAL                         0x0
#define AHCI_PORT_PXCI_0_RESET_MASK                        0xffffffff
#define AHCI_PORT_PXCI_0_SW_DEFAULT_VAL                    0x0
#define AHCI_PORT_PXCI_0_SW_DEFAULT_MASK                   0xffffffff
#define AHCI_PORT_PXCI_0_READ_MASK                         0xffffffff
#define AHCI_PORT_PXCI_0_WRITE_MASK                        0xffffffff
#define AHCI_PORT_PXCI_0_CI0_SHIFT                          _MK_SHIFT_CONST(0)                                                              // RWIVF
#define AHCI_PORT_PXCI_0_CI0_FIELD                         (_MK_SHIFT_CONST(0x1) << AHCI_PORT_PXCI_0_CI0_SHIFT)
#define AHCI_PORT_PXCI_0_CI0_RANGE                         0:0
#define AHCI_PORT_PXCI_0_CI0_WOFFSET                       0
#define AHCI_PORT_PXCI_0_CI0_DEFAULT                       (_MK_MASK_CONST(0x00000000)
#define AHCI_PORT_PXCI_0_CI0_DEFAULT_MASK                  (_MK_MASK_CONST(0x1)
#define AHCI_PORT_PXCI_0_CI0_SW_DEFAULT                    (_MK_MASK_CONST(0x00000000)
#define AHCI_PORT_PXCI_0_CI0_SW_DEFAULT_MASK               (_MK_MASK_CONST(0x1)
#define AHCI_PORT_PXCI_0_CI0__NOPRDCHK                     _MK_ENUM_CONST(0x00000001)                                                       // ----V
#define AHCI_PORT_PXCI_0_CI0_CMD_NOT_PRSNT                 _MK_ENUM_CONST(0x00000000)                                                       // R-I-V
#define AHCI_PORT_PXCI_0_CI0_CMD_PRSNT                     _MK_ENUM_CONST(0x00000001)                                                       // R---V
#define AHCI_PORT_PXCI_0_CI0_CMD_SET                       _MK_ENUM_CONST(0x00000001)                                                       // -W--T
#define AHCI_PORT_PXCI_0_CI1_SHIFT                          _MK_SHIFT_CONST(1)                                                              // RWIVF
#define AHCI_PORT_PXCI_0_CI1_FIELD                         (_MK_SHIFT_CONST(0x1) << AHCI_PORT_PXCI_0_CI1_SHIFT)
#define AHCI_PORT_PXCI_0_CI1_RANGE                         1:1
#define AHCI_PORT_PXCI_0_CI1_WOFFSET                       0
#define AHCI_PORT_PXCI_0_CI1_DEFAULT                       (_MK_MASK_CONST(0x00000000)
#define AHCI_PORT_PXCI_0_CI1_DEFAULT_MASK                  (_MK_MASK_CONST(0x1)
#define AHCI_PORT_PXCI_0_CI1_SW_DEFAULT                    (_MK_MASK_CONST(0x00000000)
#define AHCI_PORT_PXCI_0_CI1_SW_DEFAULT_MASK               (_MK_MASK_CONST(0x1)
#define AHCI_PORT_PXCI_0_CI1__NOPRDCHK                     _MK_ENUM_CONST(0x00000001)                                                       // ----V
#define AHCI_PORT_PXCI_0_CI1_CMD_NOT_PRSNT                 _MK_ENUM_CONST(0x00000000)                                                       // R-I-V
#define AHCI_PORT_PXCI_0_CI1_CMD_PRSNT                     _MK_ENUM_CONST(0x00000001)                                                       // R---V
#define AHCI_PORT_PXCI_0_CI1_CMD_SET                       _MK_ENUM_CONST(0x00000001)                                                       // -W--T
#define AHCI_PORT_PXCI_0_CI2_SHIFT                          _MK_SHIFT_CONST(2)                                                              // RWIVF
#define AHCI_PORT_PXCI_0_CI2_FIELD                         (_MK_SHIFT_CONST(0x1) << AHCI_PORT_PXCI_0_CI2_SHIFT)
#define AHCI_PORT_PXCI_0_CI2_RANGE                         2:2
#define AHCI_PORT_PXCI_0_CI2_WOFFSET                       0
#define AHCI_PORT_PXCI_0_CI2_DEFAULT                       (_MK_MASK_CONST(0x00000000)
#define AHCI_PORT_PXCI_0_CI2_DEFAULT_MASK                  (_MK_MASK_CONST(0x1)
#define AHCI_PORT_PXCI_0_CI2_SW_DEFAULT                    (_MK_MASK_CONST(0x00000000)
#define AHCI_PORT_PXCI_0_CI2_SW_DEFAULT_MASK               (_MK_MASK_CONST(0x1)
#define AHCI_PORT_PXCI_0_CI2__NOPRDCHK                     _MK_ENUM_CONST(0x00000001)                                                       // ----V
#define AHCI_PORT_PXCI_0_CI2_CMD_NOT_PRSNT                 _MK_ENUM_CONST(0x00000000)                                                       // R-I-V
#define AHCI_PORT_PXCI_0_CI2_CMD_PRSNT                     _MK_ENUM_CONST(0x00000001)                                                       // R---V
#define AHCI_PORT_PXCI_0_CI2_CMD_SET                       _MK_ENUM_CONST(0x00000001)                                                       // -W--T
#define AHCI_PORT_PXCI_0_CI3_SHIFT                          _MK_SHIFT_CONST(3)                                                              // RWIVF
#define AHCI_PORT_PXCI_0_CI3_FIELD                         (_MK_SHIFT_CONST(0x1) << AHCI_PORT_PXCI_0_CI3_SHIFT)
#define AHCI_PORT_PXCI_0_CI3_RANGE                         3:3
#define AHCI_PORT_PXCI_0_CI3_WOFFSET                       0
#define AHCI_PORT_PXCI_0_CI3_DEFAULT                       (_MK_MASK_CONST(0x00000000)
#define AHCI_PORT_PXCI_0_CI3_DEFAULT_MASK                  (_MK_MASK_CONST(0x1)
#define AHCI_PORT_PXCI_0_CI3_SW_DEFAULT                    (_MK_MASK_CONST(0x00000000)
#define AHCI_PORT_PXCI_0_CI3_SW_DEFAULT_MASK               (_MK_MASK_CONST(0x1)
#define AHCI_PORT_PXCI_0_CI3__NOPRDCHK                     _MK_ENUM_CONST(0x00000001)                                                       // ----V
#define AHCI_PORT_PXCI_0_CI3_CMD_NOT_PRSNT                 _MK_ENUM_CONST(0x00000000)                                                       // R-I-V
#define AHCI_PORT_PXCI_0_CI3_CMD_PRSNT                     _MK_ENUM_CONST(0x00000001)                                                       // R---V
#define AHCI_PORT_PXCI_0_CI3_CMD_SET                       _MK_ENUM_CONST(0x00000001)                                                       // -W--T
#define AHCI_PORT_PXCI_0_CI4_SHIFT                          _MK_SHIFT_CONST(4)                                                              // RWIVF
#define AHCI_PORT_PXCI_0_CI4_FIELD                         (_MK_SHIFT_CONST(0x1) << AHCI_PORT_PXCI_0_CI4_SHIFT)
#define AHCI_PORT_PXCI_0_CI4_RANGE                         4:4
#define AHCI_PORT_PXCI_0_CI4_WOFFSET                       0
#define AHCI_PORT_PXCI_0_CI4_DEFAULT                       (_MK_MASK_CONST(0x00000000)
#define AHCI_PORT_PXCI_0_CI4_DEFAULT_MASK                  (_MK_MASK_CONST(0x1)
#define AHCI_PORT_PXCI_0_CI4_SW_DEFAULT                    (_MK_MASK_CONST(0x00000000)
#define AHCI_PORT_PXCI_0_CI4_SW_DEFAULT_MASK               (_MK_MASK_CONST(0x1)
#define AHCI_PORT_PXCI_0_CI4__NOPRDCHK                     _MK_ENUM_CONST(0x00000001)                                                       // ----V
#define AHCI_PORT_PXCI_0_CI4_CMD_NOT_PRSNT                 _MK_ENUM_CONST(0x00000000)                                                       // R-I-V
#define AHCI_PORT_PXCI_0_CI4_CMD_PRSNT                     _MK_ENUM_CONST(0x00000001)                                                       // R---V
#define AHCI_PORT_PXCI_0_CI4_CMD_SET                       _MK_ENUM_CONST(0x00000001)                                                       // -W--T
#define AHCI_PORT_PXCI_0_CI5_SHIFT                          _MK_SHIFT_CONST(5)                                                              // RWIVF
#define AHCI_PORT_PXCI_0_CI5_FIELD                         (_MK_SHIFT_CONST(0x1) << AHCI_PORT_PXCI_0_CI5_SHIFT)
#define AHCI_PORT_PXCI_0_CI5_RANGE                         5:5
#define AHCI_PORT_PXCI_0_CI5_WOFFSET                       0
#define AHCI_PORT_PXCI_0_CI5_DEFAULT                       (_MK_MASK_CONST(0x00000000)
#define AHCI_PORT_PXCI_0_CI5_DEFAULT_MASK                  (_MK_MASK_CONST(0x1)
#define AHCI_PORT_PXCI_0_CI5_SW_DEFAULT                    (_MK_MASK_CONST(0x00000000)
#define AHCI_PORT_PXCI_0_CI5_SW_DEFAULT_MASK               (_MK_MASK_CONST(0x1)
#define AHCI_PORT_PXCI_0_CI5__NOPRDCHK                     _MK_ENUM_CONST(0x00000001)                                                       // ----V
#define AHCI_PORT_PXCI_0_CI5_CMD_NOT_PRSNT                 _MK_ENUM_CONST(0x00000000)                                                       // R-I-V
#define AHCI_PORT_PXCI_0_CI5_CMD_PRSNT                     _MK_ENUM_CONST(0x00000001)                                                       // R---V
#define AHCI_PORT_PXCI_0_CI5_CMD_SET                       _MK_ENUM_CONST(0x00000001)                                                       // -W--T
#define AHCI_PORT_PXCI_0_CI6_SHIFT                          _MK_SHIFT_CONST(6)                                                              // RWIVF
#define AHCI_PORT_PXCI_0_CI6_FIELD                         (_MK_SHIFT_CONST(0x1) << AHCI_PORT_PXCI_0_CI6_SHIFT)
#define AHCI_PORT_PXCI_0_CI6_RANGE                         6:6
#define AHCI_PORT_PXCI_0_CI6_WOFFSET                       0
#define AHCI_PORT_PXCI_0_CI6_DEFAULT                       (_MK_MASK_CONST(0x00000000)
#define AHCI_PORT_PXCI_0_CI6_DEFAULT_MASK                  (_MK_MASK_CONST(0x1)
#define AHCI_PORT_PXCI_0_CI6_SW_DEFAULT                    (_MK_MASK_CONST(0x00000000)
#define AHCI_PORT_PXCI_0_CI6_SW_DEFAULT_MASK               (_MK_MASK_CONST(0x1)
#define AHCI_PORT_PXCI_0_CI6__NOPRDCHK                     _MK_ENUM_CONST(0x00000001)                                                       // ----V
#define AHCI_PORT_PXCI_0_CI6_CMD_NOT_PRSNT                 _MK_ENUM_CONST(0x00000000)                                                       // R-I-V
#define AHCI_PORT_PXCI_0_CI6_CMD_PRSNT                     _MK_ENUM_CONST(0x00000001)                                                       // R---V
#define AHCI_PORT_PXCI_0_CI6_CMD_SET                       _MK_ENUM_CONST(0x00000001)                                                       // -W--T
#define AHCI_PORT_PXCI_0_CI7_SHIFT                          _MK_SHIFT_CONST(7)                                                              // RWIVF
#define AHCI_PORT_PXCI_0_CI7_FIELD                         (_MK_SHIFT_CONST(0x1) << AHCI_PORT_PXCI_0_CI7_SHIFT)
#define AHCI_PORT_PXCI_0_CI7_RANGE                         7:7
#define AHCI_PORT_PXCI_0_CI7_WOFFSET                       0
#define AHCI_PORT_PXCI_0_CI7_DEFAULT                       (_MK_MASK_CONST(0x00000000)
#define AHCI_PORT_PXCI_0_CI7_DEFAULT_MASK                  (_MK_MASK_CONST(0x1)
#define AHCI_PORT_PXCI_0_CI7_SW_DEFAULT                    (_MK_MASK_CONST(0x00000000)
#define AHCI_PORT_PXCI_0_CI7_SW_DEFAULT_MASK               (_MK_MASK_CONST(0x1)
#define AHCI_PORT_PXCI_0_CI7__NOPRDCHK                     _MK_ENUM_CONST(0x00000001)                                                       // ----V
#define AHCI_PORT_PXCI_0_CI7_CMD_NOT_PRSNT                 _MK_ENUM_CONST(0x00000000)                                                       // R-I-V
#define AHCI_PORT_PXCI_0_CI7_CMD_PRSNT                     _MK_ENUM_CONST(0x00000001)                                                       // R---V
#define AHCI_PORT_PXCI_0_CI7_CMD_SET                       _MK_ENUM_CONST(0x00000001)                                                       // -W--T
#define AHCI_PORT_PXCI_0_CI8_SHIFT                          _MK_SHIFT_CONST(8)                                                              // RWIVF
#define AHCI_PORT_PXCI_0_CI8_FIELD                         (_MK_SHIFT_CONST(0x1) << AHCI_PORT_PXCI_0_CI8_SHIFT)
#define AHCI_PORT_PXCI_0_CI8_RANGE                         8:8
#define AHCI_PORT_PXCI_0_CI8_WOFFSET                       0
#define AHCI_PORT_PXCI_0_CI8_DEFAULT                       (_MK_MASK_CONST(0x00000000)
#define AHCI_PORT_PXCI_0_CI8_DEFAULT_MASK                  (_MK_MASK_CONST(0x1)
#define AHCI_PORT_PXCI_0_CI8_SW_DEFAULT                    (_MK_MASK_CONST(0x00000000)
#define AHCI_PORT_PXCI_0_CI8_SW_DEFAULT_MASK               (_MK_MASK_CONST(0x1)
#define AHCI_PORT_PXCI_0_CI8__NOPRDCHK                     _MK_ENUM_CONST(0x00000001)                                                       // ----V
#define AHCI_PORT_PXCI_0_CI8_CMD_NOT_PRSNT                 _MK_ENUM_CONST(0x00000000)                                                       // R-I-V
#define AHCI_PORT_PXCI_0_CI8_CMD_PRSNT                     _MK_ENUM_CONST(0x00000001)                                                       // R---V
#define AHCI_PORT_PXCI_0_CI8_CMD_SET                       _MK_ENUM_CONST(0x00000001)                                                       // -W--T
#define AHCI_PORT_PXCI_0_CI9_SHIFT                          _MK_SHIFT_CONST(9)                                                              // RWIVF
#define AHCI_PORT_PXCI_0_CI9_FIELD                         (_MK_SHIFT_CONST(0x1) << AHCI_PORT_PXCI_0_CI9_SHIFT)
#define AHCI_PORT_PXCI_0_CI9_RANGE                         9:9
#define AHCI_PORT_PXCI_0_CI9_WOFFSET                       0
#define AHCI_PORT_PXCI_0_CI9_DEFAULT                       (_MK_MASK_CONST(0x00000000)
#define AHCI_PORT_PXCI_0_CI9_DEFAULT_MASK                  (_MK_MASK_CONST(0x1)
#define AHCI_PORT_PXCI_0_CI9_SW_DEFAULT                    (_MK_MASK_CONST(0x00000000)
#define AHCI_PORT_PXCI_0_CI9_SW_DEFAULT_MASK               (_MK_MASK_CONST(0x1)
#define AHCI_PORT_PXCI_0_CI9__NOPRDCHK                     _MK_ENUM_CONST(0x00000001)                                                       // ----V
#define AHCI_PORT_PXCI_0_CI9_CMD_NOT_PRSNT                 _MK_ENUM_CONST(0x00000000)                                                       // R-I-V
#define AHCI_PORT_PXCI_0_CI9_CMD_PRSNT                     _MK_ENUM_CONST(0x00000001)                                                       // R---V
#define AHCI_PORT_PXCI_0_CI9_CMD_SET                       _MK_ENUM_CONST(0x00000001)                                                       // -W--T
#define AHCI_PORT_PXCI_0_CI10_SHIFT                         _MK_SHIFT_CONST(10)                                                             // RWIVF
#define AHCI_PORT_PXCI_0_CI10_FIELD                        (_MK_SHIFT_CONST(0x1) << AHCI_PORT_PXCI_0_CI10_SHIFT)
#define AHCI_PORT_PXCI_0_CI10_RANGE                        10:10
#define AHCI_PORT_PXCI_0_CI10_WOFFSET                      0
#define AHCI_PORT_PXCI_0_CI10_DEFAULT                      (_MK_MASK_CONST(0x00000000)
#define AHCI_PORT_PXCI_0_CI10_DEFAULT_MASK                 (_MK_MASK_CONST(0x1)
#define AHCI_PORT_PXCI_0_CI10_SW_DEFAULT                   (_MK_MASK_CONST(0x00000000)
#define AHCI_PORT_PXCI_0_CI10_SW_DEFAULT_MASK              (_MK_MASK_CONST(0x1)
#define AHCI_PORT_PXCI_0_CI10__NOPRDCHK                    _MK_ENUM_CONST(0x00000001)                                                       // ----V
#define AHCI_PORT_PXCI_0_CI10_CMD_NOT_PRSNT                _MK_ENUM_CONST(0x00000000)                                                       // R-I-V
#define AHCI_PORT_PXCI_0_CI10_CMD_PRSNT                    _MK_ENUM_CONST(0x00000001)                                                       // R---V
#define AHCI_PORT_PXCI_0_CI10_CMD_SET                      _MK_ENUM_CONST(0x00000001)                                                       // -W--T
#define AHCI_PORT_PXCI_0_CI11_SHIFT                         _MK_SHIFT_CONST(11)                                                             // RWIVF
#define AHCI_PORT_PXCI_0_CI11_FIELD                        (_MK_SHIFT_CONST(0x1) << AHCI_PORT_PXCI_0_CI11_SHIFT)
#define AHCI_PORT_PXCI_0_CI11_RANGE                        11:11
#define AHCI_PORT_PXCI_0_CI11_WOFFSET                      0
#define AHCI_PORT_PXCI_0_CI11_DEFAULT                      (_MK_MASK_CONST(0x00000000)
#define AHCI_PORT_PXCI_0_CI11_DEFAULT_MASK                 (_MK_MASK_CONST(0x1)
#define AHCI_PORT_PXCI_0_CI11_SW_DEFAULT                   (_MK_MASK_CONST(0x00000000)
#define AHCI_PORT_PXCI_0_CI11_SW_DEFAULT_MASK              (_MK_MASK_CONST(0x1)
#define AHCI_PORT_PXCI_0_CI11__NOPRDCHK                    _MK_ENUM_CONST(0x00000001)                                                       // ----V
#define AHCI_PORT_PXCI_0_CI11_CMD_NOT_PRSNT                _MK_ENUM_CONST(0x00000000)                                                       // R-I-V
#define AHCI_PORT_PXCI_0_CI11_CMD_PRSNT                    _MK_ENUM_CONST(0x00000001)                                                       // R---V
#define AHCI_PORT_PXCI_0_CI11_CMD_SET                      _MK_ENUM_CONST(0x00000001)                                                       // -W--T
#define AHCI_PORT_PXCI_0_CI12_SHIFT                         _MK_SHIFT_CONST(12)                                                             // RWIVF
#define AHCI_PORT_PXCI_0_CI12_FIELD                        (_MK_SHIFT_CONST(0x1) << AHCI_PORT_PXCI_0_CI12_SHIFT)
#define AHCI_PORT_PXCI_0_CI12_RANGE                        12:12
#define AHCI_PORT_PXCI_0_CI12_WOFFSET                      0
#define AHCI_PORT_PXCI_0_CI12_DEFAULT                      (_MK_MASK_CONST(0x00000000)
#define AHCI_PORT_PXCI_0_CI12_DEFAULT_MASK                 (_MK_MASK_CONST(0x1)
#define AHCI_PORT_PXCI_0_CI12_SW_DEFAULT                   (_MK_MASK_CONST(0x00000000)
#define AHCI_PORT_PXCI_0_CI12_SW_DEFAULT_MASK              (_MK_MASK_CONST(0x1)
#define AHCI_PORT_PXCI_0_CI12__NOPRDCHK                    _MK_ENUM_CONST(0x00000001)                                                       // ----V
#define AHCI_PORT_PXCI_0_CI12_CMD_NOT_PRSNT                _MK_ENUM_CONST(0x00000000)                                                       // R-I-V
#define AHCI_PORT_PXCI_0_CI12_CMD_PRSNT                    _MK_ENUM_CONST(0x00000001)                                                       // R---V
#define AHCI_PORT_PXCI_0_CI12_CMD_SET                      _MK_ENUM_CONST(0x00000001)                                                       // -W--T
#define AHCI_PORT_PXCI_0_CI13_SHIFT                         _MK_SHIFT_CONST(13)                                                             // RWIVF
#define AHCI_PORT_PXCI_0_CI13_FIELD                        (_MK_SHIFT_CONST(0x1) << AHCI_PORT_PXCI_0_CI13_SHIFT)
#define AHCI_PORT_PXCI_0_CI13_RANGE                        13:13
#define AHCI_PORT_PXCI_0_CI13_WOFFSET                      0
#define AHCI_PORT_PXCI_0_CI13_DEFAULT                      (_MK_MASK_CONST(0x00000000)
#define AHCI_PORT_PXCI_0_CI13_DEFAULT_MASK                 (_MK_MASK_CONST(0x1)
#define AHCI_PORT_PXCI_0_CI13_SW_DEFAULT                   (_MK_MASK_CONST(0x00000000)
#define AHCI_PORT_PXCI_0_CI13_SW_DEFAULT_MASK              (_MK_MASK_CONST(0x1)
#define AHCI_PORT_PXCI_0_CI13__NOPRDCHK                    _MK_ENUM_CONST(0x00000001)                                                       // ----V
#define AHCI_PORT_PXCI_0_CI13_CMD_NOT_PRSNT                _MK_ENUM_CONST(0x00000000)                                                       // R-I-V
#define AHCI_PORT_PXCI_0_CI13_CMD_PRSNT                    _MK_ENUM_CONST(0x00000001)                                                       // R---V
#define AHCI_PORT_PXCI_0_CI13_CMD_SET                      _MK_ENUM_CONST(0x00000001)                                                       // -W--T
#define AHCI_PORT_PXCI_0_CI14_SHIFT                         _MK_SHIFT_CONST(14)                                                             // RWIVF
#define AHCI_PORT_PXCI_0_CI14_FIELD                        (_MK_SHIFT_CONST(0x1) << AHCI_PORT_PXCI_0_CI14_SHIFT)
#define AHCI_PORT_PXCI_0_CI14_RANGE                        14:14
#define AHCI_PORT_PXCI_0_CI14_WOFFSET                      0
#define AHCI_PORT_PXCI_0_CI14_DEFAULT                      (_MK_MASK_CONST(0x00000000)
#define AHCI_PORT_PXCI_0_CI14_DEFAULT_MASK                 (_MK_MASK_CONST(0x1)
#define AHCI_PORT_PXCI_0_CI14_SW_DEFAULT                   (_MK_MASK_CONST(0x00000000)
#define AHCI_PORT_PXCI_0_CI14_SW_DEFAULT_MASK              (_MK_MASK_CONST(0x1)
#define AHCI_PORT_PXCI_0_CI14__NOPRDCHK                    _MK_ENUM_CONST(0x00000001)                                                       // ----V
#define AHCI_PORT_PXCI_0_CI14_CMD_NOT_PRSNT                _MK_ENUM_CONST(0x00000000)                                                       // R-I-V
#define AHCI_PORT_PXCI_0_CI14_CMD_PRSNT                    _MK_ENUM_CONST(0x00000001)                                                       // R---V
#define AHCI_PORT_PXCI_0_CI14_CMD_SET                      _MK_ENUM_CONST(0x00000001)                                                       // -W--T
#define AHCI_PORT_PXCI_0_CI15_SHIFT                         _MK_SHIFT_CONST(15)                                                             // RWIVF
#define AHCI_PORT_PXCI_0_CI15_FIELD                        (_MK_SHIFT_CONST(0x1) << AHCI_PORT_PXCI_0_CI15_SHIFT)
#define AHCI_PORT_PXCI_0_CI15_RANGE                        15:15
#define AHCI_PORT_PXCI_0_CI15_WOFFSET                      0
#define AHCI_PORT_PXCI_0_CI15_DEFAULT                      (_MK_MASK_CONST(0x00000000)
#define AHCI_PORT_PXCI_0_CI15_DEFAULT_MASK                 (_MK_MASK_CONST(0x1)
#define AHCI_PORT_PXCI_0_CI15_SW_DEFAULT                   (_MK_MASK_CONST(0x00000000)
#define AHCI_PORT_PXCI_0_CI15_SW_DEFAULT_MASK              (_MK_MASK_CONST(0x1)
#define AHCI_PORT_PXCI_0_CI15__NOPRDCHK                    _MK_ENUM_CONST(0x00000001)                                                       // ----V
#define AHCI_PORT_PXCI_0_CI15_CMD_NOT_PRSNT                _MK_ENUM_CONST(0x00000000)                                                       // R-I-V
#define AHCI_PORT_PXCI_0_CI15_CMD_PRSNT                    _MK_ENUM_CONST(0x00000001)                                                       // R---V
#define AHCI_PORT_PXCI_0_CI15_CMD_SET                      _MK_ENUM_CONST(0x00000001)                                                       // -W--T
#define AHCI_PORT_PXCI_0_CI16_SHIFT                         _MK_SHIFT_CONST(16)                                                             // RWIVF
#define AHCI_PORT_PXCI_0_CI16_FIELD                        (_MK_SHIFT_CONST(0x1) << AHCI_PORT_PXCI_0_CI16_SHIFT)
#define AHCI_PORT_PXCI_0_CI16_RANGE                        16:16
#define AHCI_PORT_PXCI_0_CI16_WOFFSET                      0
#define AHCI_PORT_PXCI_0_CI16_DEFAULT                      (_MK_MASK_CONST(0x00000000)
#define AHCI_PORT_PXCI_0_CI16_DEFAULT_MASK                 (_MK_MASK_CONST(0x1)
#define AHCI_PORT_PXCI_0_CI16_SW_DEFAULT                   (_MK_MASK_CONST(0x00000000)
#define AHCI_PORT_PXCI_0_CI16_SW_DEFAULT_MASK              (_MK_MASK_CONST(0x1)
#define AHCI_PORT_PXCI_0_CI16__NOPRDCHK                    _MK_ENUM_CONST(0x00000001)                                                       // ----V
#define AHCI_PORT_PXCI_0_CI16_CMD_NOT_PRSNT                _MK_ENUM_CONST(0x00000000)                                                       // R-I-V
#define AHCI_PORT_PXCI_0_CI16_CMD_PRSNT                    _MK_ENUM_CONST(0x00000001)                                                       // R---V
#define AHCI_PORT_PXCI_0_CI16_CMD_SET                      _MK_ENUM_CONST(0x00000001)                                                       // -W--T
#define AHCI_PORT_PXCI_0_CI17_SHIFT                         _MK_SHIFT_CONST(17)                                                             // RWIVF
#define AHCI_PORT_PXCI_0_CI17_FIELD                        (_MK_SHIFT_CONST(0x1) << AHCI_PORT_PXCI_0_CI17_SHIFT)
#define AHCI_PORT_PXCI_0_CI17_RANGE                        17:17
#define AHCI_PORT_PXCI_0_CI17_WOFFSET                      0
#define AHCI_PORT_PXCI_0_CI17_DEFAULT                      (_MK_MASK_CONST(0x00000000)
#define AHCI_PORT_PXCI_0_CI17_DEFAULT_MASK                 (_MK_MASK_CONST(0x1)
#define AHCI_PORT_PXCI_0_CI17_SW_DEFAULT                   (_MK_MASK_CONST(0x00000000)
#define AHCI_PORT_PXCI_0_CI17_SW_DEFAULT_MASK              (_MK_MASK_CONST(0x1)
#define AHCI_PORT_PXCI_0_CI17__NOPRDCHK                    _MK_ENUM_CONST(0x00000001)                                                       // ----V
#define AHCI_PORT_PXCI_0_CI17_CMD_NOT_PRSNT                _MK_ENUM_CONST(0x00000000)                                                       // R-I-V
#define AHCI_PORT_PXCI_0_CI17_CMD_PRSNT                    _MK_ENUM_CONST(0x00000001)                                                       // R---V
#define AHCI_PORT_PXCI_0_CI17_CMD_SET                      _MK_ENUM_CONST(0x00000001)                                                       // -W--T
#define AHCI_PORT_PXCI_0_CI18_SHIFT                         _MK_SHIFT_CONST(18)                                                             // RWIVF
#define AHCI_PORT_PXCI_0_CI18_FIELD                        (_MK_SHIFT_CONST(0x1) << AHCI_PORT_PXCI_0_CI18_SHIFT)
#define AHCI_PORT_PXCI_0_CI18_RANGE                        18:18
#define AHCI_PORT_PXCI_0_CI18_WOFFSET                      0
#define AHCI_PORT_PXCI_0_CI18_DEFAULT                      (_MK_MASK_CONST(0x00000000)
#define AHCI_PORT_PXCI_0_CI18_DEFAULT_MASK                 (_MK_MASK_CONST(0x1)
#define AHCI_PORT_PXCI_0_CI18_SW_DEFAULT                   (_MK_MASK_CONST(0x00000000)
#define AHCI_PORT_PXCI_0_CI18_SW_DEFAULT_MASK              (_MK_MASK_CONST(0x1)
#define AHCI_PORT_PXCI_0_CI18__NOPRDCHK                    _MK_ENUM_CONST(0x00000001)                                                       // ----V
#define AHCI_PORT_PXCI_0_CI18_CMD_NOT_PRSNT                _MK_ENUM_CONST(0x00000000)                                                       // R-I-V
#define AHCI_PORT_PXCI_0_CI18_CMD_PRSNT                    _MK_ENUM_CONST(0x00000001)                                                       // R---V
#define AHCI_PORT_PXCI_0_CI18_CMD_SET                      _MK_ENUM_CONST(0x00000001)                                                       // -W--T
#define AHCI_PORT_PXCI_0_CI19_SHIFT                         _MK_SHIFT_CONST(19)                                                             // RWIVF
#define AHCI_PORT_PXCI_0_CI19_FIELD                        (_MK_SHIFT_CONST(0x1) << AHCI_PORT_PXCI_0_CI19_SHIFT)
#define AHCI_PORT_PXCI_0_CI19_RANGE                        19:19
#define AHCI_PORT_PXCI_0_CI19_WOFFSET                      0
#define AHCI_PORT_PXCI_0_CI19_DEFAULT                      (_MK_MASK_CONST(0x00000000)
#define AHCI_PORT_PXCI_0_CI19_DEFAULT_MASK                 (_MK_MASK_CONST(0x1)
#define AHCI_PORT_PXCI_0_CI19_SW_DEFAULT                   (_MK_MASK_CONST(0x00000000)
#define AHCI_PORT_PXCI_0_CI19_SW_DEFAULT_MASK              (_MK_MASK_CONST(0x1)
#define AHCI_PORT_PXCI_0_CI19__NOPRDCHK                    _MK_ENUM_CONST(0x00000001)                                                       // ----V
#define AHCI_PORT_PXCI_0_CI19_CMD_NOT_PRSNT                _MK_ENUM_CONST(0x00000000)                                                       // R-I-V
#define AHCI_PORT_PXCI_0_CI19_CMD_PRSNT                    _MK_ENUM_CONST(0x00000001)                                                       // R---V
#define AHCI_PORT_PXCI_0_CI19_CMD_SET                      _MK_ENUM_CONST(0x00000001)                                                       // -W--T
#define AHCI_PORT_PXCI_0_CI20_SHIFT                         _MK_SHIFT_CONST(20)                                                             // RWIVF
#define AHCI_PORT_PXCI_0_CI20_FIELD                        (_MK_SHIFT_CONST(0x1) << AHCI_PORT_PXCI_0_CI20_SHIFT)
#define AHCI_PORT_PXCI_0_CI20_RANGE                        20:20
#define AHCI_PORT_PXCI_0_CI20_WOFFSET                      0
#define AHCI_PORT_PXCI_0_CI20_DEFAULT                      (_MK_MASK_CONST(0x00000000)
#define AHCI_PORT_PXCI_0_CI20_DEFAULT_MASK                 (_MK_MASK_CONST(0x1)
#define AHCI_PORT_PXCI_0_CI20_SW_DEFAULT                   (_MK_MASK_CONST(0x00000000)
#define AHCI_PORT_PXCI_0_CI20_SW_DEFAULT_MASK              (_MK_MASK_CONST(0x1)
#define AHCI_PORT_PXCI_0_CI20__NOPRDCHK                    _MK_ENUM_CONST(0x00000001)                                                       // ----V
#define AHCI_PORT_PXCI_0_CI20_CMD_NOT_PRSNT                _MK_ENUM_CONST(0x00000000)                                                       // R-I-V
#define AHCI_PORT_PXCI_0_CI20_CMD_PRSNT                    _MK_ENUM_CONST(0x00000001)                                                       // R---V
#define AHCI_PORT_PXCI_0_CI20_CMD_SET                      _MK_ENUM_CONST(0x00000001)                                                       // -W--T
#define AHCI_PORT_PXCI_0_CI21_SHIFT                         _MK_SHIFT_CONST(21)                                                             // RWIVF
#define AHCI_PORT_PXCI_0_CI21_FIELD                        (_MK_SHIFT_CONST(0x1) << AHCI_PORT_PXCI_0_CI21_SHIFT)
#define AHCI_PORT_PXCI_0_CI21_RANGE                        21:21
#define AHCI_PORT_PXCI_0_CI21_WOFFSET                      0
#define AHCI_PORT_PXCI_0_CI21_DEFAULT                      (_MK_MASK_CONST(0x00000000)
#define AHCI_PORT_PXCI_0_CI21_DEFAULT_MASK                 (_MK_MASK_CONST(0x1)
#define AHCI_PORT_PXCI_0_CI21_SW_DEFAULT                   (_MK_MASK_CONST(0x00000000)
#define AHCI_PORT_PXCI_0_CI21_SW_DEFAULT_MASK              (_MK_MASK_CONST(0x1)
#define AHCI_PORT_PXCI_0_CI21__NOPRDCHK                    _MK_ENUM_CONST(0x00000001)                                                       // ----V
#define AHCI_PORT_PXCI_0_CI21_CMD_NOT_PRSNT                _MK_ENUM_CONST(0x00000000)                                                       // R-I-V
#define AHCI_PORT_PXCI_0_CI21_CMD_PRSNT                    _MK_ENUM_CONST(0x00000001)                                                       // R---V
#define AHCI_PORT_PXCI_0_CI21_CMD_SET                      _MK_ENUM_CONST(0x00000001)                                                       // -W--T
#define AHCI_PORT_PXCI_0_CI22_SHIFT                         _MK_SHIFT_CONST(22)                                                             // RWIVF
#define AHCI_PORT_PXCI_0_CI22_FIELD                        (_MK_SHIFT_CONST(0x1) << AHCI_PORT_PXCI_0_CI22_SHIFT)
#define AHCI_PORT_PXCI_0_CI22_RANGE                        22:22
#define AHCI_PORT_PXCI_0_CI22_WOFFSET                      0
#define AHCI_PORT_PXCI_0_CI22_DEFAULT                      (_MK_MASK_CONST(0x00000000)
#define AHCI_PORT_PXCI_0_CI22_DEFAULT_MASK                 (_MK_MASK_CONST(0x1)
#define AHCI_PORT_PXCI_0_CI22_SW_DEFAULT                   (_MK_MASK_CONST(0x00000000)
#define AHCI_PORT_PXCI_0_CI22_SW_DEFAULT_MASK              (_MK_MASK_CONST(0x1)
#define AHCI_PORT_PXCI_0_CI22__NOPRDCHK                    _MK_ENUM_CONST(0x00000001)                                                       // ----V
#define AHCI_PORT_PXCI_0_CI22_CMD_NOT_PRSNT                _MK_ENUM_CONST(0x00000000)                                                       // R-I-V
#define AHCI_PORT_PXCI_0_CI22_CMD_PRSNT                    _MK_ENUM_CONST(0x00000001)                                                       // R---V
#define AHCI_PORT_PXCI_0_CI22_CMD_SET                      _MK_ENUM_CONST(0x00000001)                                                       // -W--T
#define AHCI_PORT_PXCI_0_CI23_SHIFT                         _MK_SHIFT_CONST(23)                                                             // RWIVF
#define AHCI_PORT_PXCI_0_CI23_FIELD                        (_MK_SHIFT_CONST(0x1) << AHCI_PORT_PXCI_0_CI23_SHIFT)
#define AHCI_PORT_PXCI_0_CI23_RANGE                        23:23
#define AHCI_PORT_PXCI_0_CI23_WOFFSET                      0
#define AHCI_PORT_PXCI_0_CI23_DEFAULT                      (_MK_MASK_CONST(0x00000000)
#define AHCI_PORT_PXCI_0_CI23_DEFAULT_MASK                 (_MK_MASK_CONST(0x1)
#define AHCI_PORT_PXCI_0_CI23_SW_DEFAULT                   (_MK_MASK_CONST(0x00000000)
#define AHCI_PORT_PXCI_0_CI23_SW_DEFAULT_MASK              (_MK_MASK_CONST(0x1)
#define AHCI_PORT_PXCI_0_CI23__NOPRDCHK                    _MK_ENUM_CONST(0x00000001)                                                       // ----V
#define AHCI_PORT_PXCI_0_CI23_CMD_NOT_PRSNT                _MK_ENUM_CONST(0x00000000)                                                       // R-I-V
#define AHCI_PORT_PXCI_0_CI23_CMD_PRSNT                    _MK_ENUM_CONST(0x00000001)                                                       // R---V
#define AHCI_PORT_PXCI_0_CI23_CMD_SET                      _MK_ENUM_CONST(0x00000001)                                                       // -W--T
#define AHCI_PORT_PXCI_0_CI24_SHIFT                         _MK_SHIFT_CONST(24)                                                             // RWIVF
#define AHCI_PORT_PXCI_0_CI24_FIELD                        (_MK_SHIFT_CONST(0x1) << AHCI_PORT_PXCI_0_CI24_SHIFT)
#define AHCI_PORT_PXCI_0_CI24_RANGE                        24:24
#define AHCI_PORT_PXCI_0_CI24_WOFFSET                      0
#define AHCI_PORT_PXCI_0_CI24_DEFAULT                      (_MK_MASK_CONST(0x00000000)
#define AHCI_PORT_PXCI_0_CI24_DEFAULT_MASK                 (_MK_MASK_CONST(0x1)
#define AHCI_PORT_PXCI_0_CI24_SW_DEFAULT                   (_MK_MASK_CONST(0x00000000)
#define AHCI_PORT_PXCI_0_CI24_SW_DEFAULT_MASK              (_MK_MASK_CONST(0x1)
#define AHCI_PORT_PXCI_0_CI24__NOPRDCHK                    _MK_ENUM_CONST(0x00000001)                                                       // ----V
#define AHCI_PORT_PXCI_0_CI24_CMD_NOT_PRSNT                _MK_ENUM_CONST(0x00000000)                                                       // R-I-V
#define AHCI_PORT_PXCI_0_CI24_CMD_PRSNT                    _MK_ENUM_CONST(0x00000001)                                                       // R---V
#define AHCI_PORT_PXCI_0_CI24_CMD_SET                      _MK_ENUM_CONST(0x00000001)                                                       // -W--T
#define AHCI_PORT_PXCI_0_CI25_SHIFT                         _MK_SHIFT_CONST(25)                                                             // RWIVF
#define AHCI_PORT_PXCI_0_CI25_FIELD                        (_MK_SHIFT_CONST(0x1) << AHCI_PORT_PXCI_0_CI25_SHIFT)
#define AHCI_PORT_PXCI_0_CI25_RANGE                        25:25
#define AHCI_PORT_PXCI_0_CI25_WOFFSET                      0
#define AHCI_PORT_PXCI_0_CI25_DEFAULT                      (_MK_MASK_CONST(0x00000000)
#define AHCI_PORT_PXCI_0_CI25_DEFAULT_MASK                 (_MK_MASK_CONST(0x1)
#define AHCI_PORT_PXCI_0_CI25_SW_DEFAULT                   (_MK_MASK_CONST(0x00000000)
#define AHCI_PORT_PXCI_0_CI25_SW_DEFAULT_MASK              (_MK_MASK_CONST(0x1)
#define AHCI_PORT_PXCI_0_CI25__NOPRDCHK                    _MK_ENUM_CONST(0x00000001)                                                       // ----V
#define AHCI_PORT_PXCI_0_CI25_CMD_NOT_PRSNT                _MK_ENUM_CONST(0x00000000)                                                       // R-I-V
#define AHCI_PORT_PXCI_0_CI25_CMD_PRSNT                    _MK_ENUM_CONST(0x00000001)                                                       // R---V
#define AHCI_PORT_PXCI_0_CI25_CMD_SET                      _MK_ENUM_CONST(0x00000001)                                                       // -W--T
#define AHCI_PORT_PXCI_0_CI26_SHIFT                         _MK_SHIFT_CONST(26)                                                             // RWIVF
#define AHCI_PORT_PXCI_0_CI26_FIELD                        (_MK_SHIFT_CONST(0x1) << AHCI_PORT_PXCI_0_CI26_SHIFT)
#define AHCI_PORT_PXCI_0_CI26_RANGE                        26:26
#define AHCI_PORT_PXCI_0_CI26_WOFFSET                      0
#define AHCI_PORT_PXCI_0_CI26_DEFAULT                      (_MK_MASK_CONST(0x00000000)
#define AHCI_PORT_PXCI_0_CI26_DEFAULT_MASK                 (_MK_MASK_CONST(0x1)
#define AHCI_PORT_PXCI_0_CI26_SW_DEFAULT                   (_MK_MASK_CONST(0x00000000)
#define AHCI_PORT_PXCI_0_CI26_SW_DEFAULT_MASK              (_MK_MASK_CONST(0x1)
#define AHCI_PORT_PXCI_0_CI26__NOPRDCHK                    _MK_ENUM_CONST(0x00000001)                                                       // ----V
#define AHCI_PORT_PXCI_0_CI26_CMD_NOT_PRSNT                _MK_ENUM_CONST(0x00000000)                                                       // R-I-V
#define AHCI_PORT_PXCI_0_CI26_CMD_PRSNT                    _MK_ENUM_CONST(0x00000001)                                                       // R---V
#define AHCI_PORT_PXCI_0_CI26_CMD_SET                      _MK_ENUM_CONST(0x00000001)                                                       // -W--T
#define AHCI_PORT_PXCI_0_CI27_SHIFT                         _MK_SHIFT_CONST(27)                                                             // RWIVF
#define AHCI_PORT_PXCI_0_CI27_FIELD                        (_MK_SHIFT_CONST(0x1) << AHCI_PORT_PXCI_0_CI27_SHIFT)
#define AHCI_PORT_PXCI_0_CI27_RANGE                        27:27
#define AHCI_PORT_PXCI_0_CI27_WOFFSET                      0
#define AHCI_PORT_PXCI_0_CI27_DEFAULT                      (_MK_MASK_CONST(0x00000000)
#define AHCI_PORT_PXCI_0_CI27_DEFAULT_MASK                 (_MK_MASK_CONST(0x1)
#define AHCI_PORT_PXCI_0_CI27_SW_DEFAULT                   (_MK_MASK_CONST(0x00000000)
#define AHCI_PORT_PXCI_0_CI27_SW_DEFAULT_MASK              (_MK_MASK_CONST(0x1)
#define AHCI_PORT_PXCI_0_CI27__NOPRDCHK                    _MK_ENUM_CONST(0x00000001)                                                       // ----V
#define AHCI_PORT_PXCI_0_CI27_CMD_NOT_PRSNT                _MK_ENUM_CONST(0x00000000)                                                       // R-I-V
#define AHCI_PORT_PXCI_0_CI27_CMD_PRSNT                    _MK_ENUM_CONST(0x00000001)                                                       // R---V
#define AHCI_PORT_PXCI_0_CI27_CMD_SET                      _MK_ENUM_CONST(0x00000001)                                                       // -W--T
#define AHCI_PORT_PXCI_0_CI28_SHIFT                         _MK_SHIFT_CONST(28)                                                             // RWIVF
#define AHCI_PORT_PXCI_0_CI28_FIELD                        (_MK_SHIFT_CONST(0x1) << AHCI_PORT_PXCI_0_CI28_SHIFT)
#define AHCI_PORT_PXCI_0_CI28_RANGE                        28:28
#define AHCI_PORT_PXCI_0_CI28_WOFFSET                      0
#define AHCI_PORT_PXCI_0_CI28_DEFAULT                      (_MK_MASK_CONST(0x00000000)
#define AHCI_PORT_PXCI_0_CI28_DEFAULT_MASK                 (_MK_MASK_CONST(0x1)
#define AHCI_PORT_PXCI_0_CI28_SW_DEFAULT                   (_MK_MASK_CONST(0x00000000)
#define AHCI_PORT_PXCI_0_CI28_SW_DEFAULT_MASK              (_MK_MASK_CONST(0x1)
#define AHCI_PORT_PXCI_0_CI28__NOPRDCHK                    _MK_ENUM_CONST(0x00000001)                                                       // ----V
#define AHCI_PORT_PXCI_0_CI28_CMD_NOT_PRSNT                _MK_ENUM_CONST(0x00000000)                                                       // R-I-V
#define AHCI_PORT_PXCI_0_CI28_CMD_PRSNT                    _MK_ENUM_CONST(0x00000001)                                                       // R---V
#define AHCI_PORT_PXCI_0_CI28_CMD_SET                      _MK_ENUM_CONST(0x00000001)                                                       // -W--T
#define AHCI_PORT_PXCI_0_CI29_SHIFT                         _MK_SHIFT_CONST(29)                                                             // RWIVF
#define AHCI_PORT_PXCI_0_CI29_FIELD                        (_MK_SHIFT_CONST(0x1) << AHCI_PORT_PXCI_0_CI29_SHIFT)
#define AHCI_PORT_PXCI_0_CI29_RANGE                        29:29
#define AHCI_PORT_PXCI_0_CI29_WOFFSET                      0
#define AHCI_PORT_PXCI_0_CI29_DEFAULT                      (_MK_MASK_CONST(0x00000000)
#define AHCI_PORT_PXCI_0_CI29_DEFAULT_MASK                 (_MK_MASK_CONST(0x1)
#define AHCI_PORT_PXCI_0_CI29_SW_DEFAULT                   (_MK_MASK_CONST(0x00000000)
#define AHCI_PORT_PXCI_0_CI29_SW_DEFAULT_MASK              (_MK_MASK_CONST(0x1)
#define AHCI_PORT_PXCI_0_CI29__NOPRDCHK                    _MK_ENUM_CONST(0x00000001)                                                       // ----V
#define AHCI_PORT_PXCI_0_CI29_CMD_NOT_PRSNT                _MK_ENUM_CONST(0x00000000)                                                       // R-I-V
#define AHCI_PORT_PXCI_0_CI29_CMD_PRSNT                    _MK_ENUM_CONST(0x00000001)                                                       // R---V
#define AHCI_PORT_PXCI_0_CI29_CMD_SET                      _MK_ENUM_CONST(0x00000001)                                                       // -W--T
#define AHCI_PORT_PXCI_0_CI30_SHIFT                         _MK_SHIFT_CONST(30)                                                             // RWIVF
#define AHCI_PORT_PXCI_0_CI30_FIELD                        (_MK_SHIFT_CONST(0x1) << AHCI_PORT_PXCI_0_CI30_SHIFT)
#define AHCI_PORT_PXCI_0_CI30_RANGE                        30:30
#define AHCI_PORT_PXCI_0_CI30_WOFFSET                      0
#define AHCI_PORT_PXCI_0_CI30_DEFAULT                      (_MK_MASK_CONST(0x00000000)
#define AHCI_PORT_PXCI_0_CI30_DEFAULT_MASK                 (_MK_MASK_CONST(0x1)
#define AHCI_PORT_PXCI_0_CI30_SW_DEFAULT                   (_MK_MASK_CONST(0x00000000)
#define AHCI_PORT_PXCI_0_CI30_SW_DEFAULT_MASK              (_MK_MASK_CONST(0x1)
#define AHCI_PORT_PXCI_0_CI30__NOPRDCHK                    _MK_ENUM_CONST(0x00000001)                                                       // ----V
#define AHCI_PORT_PXCI_0_CI30_CMD_NOT_PRSNT                _MK_ENUM_CONST(0x00000000)                                                       // R-I-V
#define AHCI_PORT_PXCI_0_CI30_CMD_PRSNT                    _MK_ENUM_CONST(0x00000001)                                                       // R---V
#define AHCI_PORT_PXCI_0_CI30_CMD_SET                      _MK_ENUM_CONST(0x00000001)                                                       // -W--T
#define AHCI_PORT_PXCI_0_CI31_SHIFT                         _MK_SHIFT_CONST(31)                                                             // RWIVF
#define AHCI_PORT_PXCI_0_CI31_FIELD                        (_MK_SHIFT_CONST(0x1) << AHCI_PORT_PXCI_0_CI31_SHIFT)
#define AHCI_PORT_PXCI_0_CI31_RANGE                        31:31
#define AHCI_PORT_PXCI_0_CI31_WOFFSET                      0
#define AHCI_PORT_PXCI_0_CI31_DEFAULT                      (_MK_MASK_CONST(0x00000000)
#define AHCI_PORT_PXCI_0_CI31_DEFAULT_MASK                 (_MK_MASK_CONST(0x1)
#define AHCI_PORT_PXCI_0_CI31_SW_DEFAULT                   (_MK_MASK_CONST(0x00000000)
#define AHCI_PORT_PXCI_0_CI31_SW_DEFAULT_MASK              (_MK_MASK_CONST(0x1)
#define AHCI_PORT_PXCI_0_CI31__NOPRDCHK                    _MK_ENUM_CONST(0x00000001)                                                       // ----V
#define AHCI_PORT_PXCI_0_CI31_CMD_NOT_PRSNT                _MK_ENUM_CONST(0x00000000)                                                       // R-I-V
#define AHCI_PORT_PXCI_0_CI31_CMD_PRSNT                    _MK_ENUM_CONST(0x00000001)                                                       // R---V
#define AHCI_PORT_PXCI_0_CI31_CMD_SET                      _MK_ENUM_CONST(0x00000001)                                                       // -W--T
// 
// 
//              Figure 9-XXX Port Command Issue Register.
// 
// 
// 
// .TITLE Port SNotification
// .FIELD
// 
// 31           24 23           16 15            8 7             0
// .-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-.
// |0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0| PORT_PXSNTF
// `-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-'
// 
#define AHCI_PORT_PXSNTF_0                                 0x0000013C                                                                       // RW-4R
#define AHCI_PORT_PXSNTF_0_SECURE                          0
#define AHCI_PORT_PXSNTF_0_WORD_COUNT                      1
#define AHCI_PORT_PXSNTF_0_RESET_VAL                       0x0
#define AHCI_PORT_PXSNTF_0_RESET_MASK                      0xffff
#define AHCI_PORT_PXSNTF_0_SW_DEFAULT_VAL                  0x0
#define AHCI_PORT_PXSNTF_0_SW_DEFAULT_MASK                 0xffff
#define AHCI_PORT_PXSNTF_0_READ_MASK                       0xffff
#define AHCI_PORT_PXSNTF_0_WRITE_MASK                      0xffff
#define AHCI_PORT_PXSNTF_0_PMN_PORT0_SHIFT                  _MK_SHIFT_CONST(0)                                                              // RWIVF
#define AHCI_PORT_PXSNTF_0_PMN_PORT0_FIELD                 (_MK_SHIFT_CONST(0x1) << AHCI_PORT_PXSNTF_0_PMN_PORT0_SHIFT)
#define AHCI_PORT_PXSNTF_0_PMN_PORT0_RANGE                 0:0
#define AHCI_PORT_PXSNTF_0_PMN_PORT0_WOFFSET               0
#define AHCI_PORT_PXSNTF_0_PMN_PORT0_DEFAULT               (_MK_MASK_CONST(0x00000000)
#define AHCI_PORT_PXSNTF_0_PMN_PORT0_DEFAULT_MASK          (_MK_MASK_CONST(0x1)
#define AHCI_PORT_PXSNTF_0_PMN_PORT0_SW_DEFAULT            (_MK_MASK_CONST(0x00000000)
#define AHCI_PORT_PXSNTF_0_PMN_PORT0_SW_DEFAULT_MASK       (_MK_MASK_CONST(0x1)
#define AHCI_PORT_PXSNTF_0_PMN_PORT0__NOPRDCHK             _MK_ENUM_CONST(0x00000001)                                                       // ----V
#define AHCI_PORT_PXSNTF_0_PMN_PORT0_NOT_SET               _MK_ENUM_CONST(0x00000000)                                                       // R-I-V
#define AHCI_PORT_PXSNTF_0_PMN_PORT0_SET                   _MK_ENUM_CONST(0x00000001)                                                       // R---V
#define AHCI_PORT_PXSNTF_0_PMN_PORT0_CLEAR                 _MK_ENUM_CONST(0x00000001)                                                       // -W--C
#define AHCI_PORT_PXSNTF_0_PMN_PORT1_SHIFT                  _MK_SHIFT_CONST(1)                                                              // RWIVF
#define AHCI_PORT_PXSNTF_0_PMN_PORT1_FIELD                 (_MK_SHIFT_CONST(0x1) << AHCI_PORT_PXSNTF_0_PMN_PORT1_SHIFT)
#define AHCI_PORT_PXSNTF_0_PMN_PORT1_RANGE                 1:1
#define AHCI_PORT_PXSNTF_0_PMN_PORT1_WOFFSET               0
#define AHCI_PORT_PXSNTF_0_PMN_PORT1_DEFAULT               (_MK_MASK_CONST(0x00000000)
#define AHCI_PORT_PXSNTF_0_PMN_PORT1_DEFAULT_MASK          (_MK_MASK_CONST(0x1)
#define AHCI_PORT_PXSNTF_0_PMN_PORT1_SW_DEFAULT            (_MK_MASK_CONST(0x00000000)
#define AHCI_PORT_PXSNTF_0_PMN_PORT1_SW_DEFAULT_MASK       (_MK_MASK_CONST(0x1)
#define AHCI_PORT_PXSNTF_0_PMN_PORT1__NOPRDCHK             _MK_ENUM_CONST(0x00000001)                                                       // ----V
#define AHCI_PORT_PXSNTF_0_PMN_PORT1_NOT_SET               _MK_ENUM_CONST(0x00000000)                                                       // R-I-V
#define AHCI_PORT_PXSNTF_0_PMN_PORT1_SET                   _MK_ENUM_CONST(0x00000001)                                                       // R---V
#define AHCI_PORT_PXSNTF_0_PMN_PORT1_CLEAR                 _MK_ENUM_CONST(0x00000001)                                                       // -W--C
#define AHCI_PORT_PXSNTF_0_PMN_PORT2_SHIFT                  _MK_SHIFT_CONST(2)                                                              // RWIVF
#define AHCI_PORT_PXSNTF_0_PMN_PORT2_FIELD                 (_MK_SHIFT_CONST(0x1) << AHCI_PORT_PXSNTF_0_PMN_PORT2_SHIFT)
#define AHCI_PORT_PXSNTF_0_PMN_PORT2_RANGE                 2:2
#define AHCI_PORT_PXSNTF_0_PMN_PORT2_WOFFSET               0
#define AHCI_PORT_PXSNTF_0_PMN_PORT2_DEFAULT               (_MK_MASK_CONST(0x00000000)
#define AHCI_PORT_PXSNTF_0_PMN_PORT2_DEFAULT_MASK          (_MK_MASK_CONST(0x1)
#define AHCI_PORT_PXSNTF_0_PMN_PORT2_SW_DEFAULT            (_MK_MASK_CONST(0x00000000)
#define AHCI_PORT_PXSNTF_0_PMN_PORT2_SW_DEFAULT_MASK       (_MK_MASK_CONST(0x1)
#define AHCI_PORT_PXSNTF_0_PMN_PORT2__NOPRDCHK             _MK_ENUM_CONST(0x00000001)                                                       // ----V
#define AHCI_PORT_PXSNTF_0_PMN_PORT2_NOT_SET               _MK_ENUM_CONST(0x00000000)                                                       // R-I-V
#define AHCI_PORT_PXSNTF_0_PMN_PORT2_SET                   _MK_ENUM_CONST(0x00000001)                                                       // R---V
#define AHCI_PORT_PXSNTF_0_PMN_PORT2_CLEAR                 _MK_ENUM_CONST(0x00000001)                                                       // -W--C
#define AHCI_PORT_PXSNTF_0_PMN_PORT3_SHIFT                  _MK_SHIFT_CONST(3)                                                              // RWIVF
#define AHCI_PORT_PXSNTF_0_PMN_PORT3_FIELD                 (_MK_SHIFT_CONST(0x1) << AHCI_PORT_PXSNTF_0_PMN_PORT3_SHIFT)
#define AHCI_PORT_PXSNTF_0_PMN_PORT3_RANGE                 3:3
#define AHCI_PORT_PXSNTF_0_PMN_PORT3_WOFFSET               0
#define AHCI_PORT_PXSNTF_0_PMN_PORT3_DEFAULT               (_MK_MASK_CONST(0x00000000)
#define AHCI_PORT_PXSNTF_0_PMN_PORT3_DEFAULT_MASK          (_MK_MASK_CONST(0x1)
#define AHCI_PORT_PXSNTF_0_PMN_PORT3_SW_DEFAULT            (_MK_MASK_CONST(0x00000000)
#define AHCI_PORT_PXSNTF_0_PMN_PORT3_SW_DEFAULT_MASK       (_MK_MASK_CONST(0x1)
#define AHCI_PORT_PXSNTF_0_PMN_PORT3__NOPRDCHK             _MK_ENUM_CONST(0x00000001)                                                       // ----V
#define AHCI_PORT_PXSNTF_0_PMN_PORT3_NOT_SET               _MK_ENUM_CONST(0x00000000)                                                       // R-I-V
#define AHCI_PORT_PXSNTF_0_PMN_PORT3_SET                   _MK_ENUM_CONST(0x00000001)                                                       // R---V
#define AHCI_PORT_PXSNTF_0_PMN_PORT3_CLEAR                 _MK_ENUM_CONST(0x00000001)                                                       // -W--C
#define AHCI_PORT_PXSNTF_0_PMN_PORT4_SHIFT                  _MK_SHIFT_CONST(4)                                                              // RWIVF
#define AHCI_PORT_PXSNTF_0_PMN_PORT4_FIELD                 (_MK_SHIFT_CONST(0x1) << AHCI_PORT_PXSNTF_0_PMN_PORT4_SHIFT)
#define AHCI_PORT_PXSNTF_0_PMN_PORT4_RANGE                 4:4
#define AHCI_PORT_PXSNTF_0_PMN_PORT4_WOFFSET               0
#define AHCI_PORT_PXSNTF_0_PMN_PORT4_DEFAULT               (_MK_MASK_CONST(0x00000000)
#define AHCI_PORT_PXSNTF_0_PMN_PORT4_DEFAULT_MASK          (_MK_MASK_CONST(0x1)
#define AHCI_PORT_PXSNTF_0_PMN_PORT4_SW_DEFAULT            (_MK_MASK_CONST(0x00000000)
#define AHCI_PORT_PXSNTF_0_PMN_PORT4_SW_DEFAULT_MASK       (_MK_MASK_CONST(0x1)
#define AHCI_PORT_PXSNTF_0_PMN_PORT4__NOPRDCHK             _MK_ENUM_CONST(0x00000001)                                                       // ----V
#define AHCI_PORT_PXSNTF_0_PMN_PORT4_NOT_SET               _MK_ENUM_CONST(0x00000000)                                                       // R-I-V
#define AHCI_PORT_PXSNTF_0_PMN_PORT4_SET                   _MK_ENUM_CONST(0x00000001)                                                       // R---V
#define AHCI_PORT_PXSNTF_0_PMN_PORT4_CLEAR                 _MK_ENUM_CONST(0x00000001)                                                       // -W--C
#define AHCI_PORT_PXSNTF_0_PMN_PORT5_SHIFT                  _MK_SHIFT_CONST(5)                                                              // RWIVF
#define AHCI_PORT_PXSNTF_0_PMN_PORT5_FIELD                 (_MK_SHIFT_CONST(0x1) << AHCI_PORT_PXSNTF_0_PMN_PORT5_SHIFT)
#define AHCI_PORT_PXSNTF_0_PMN_PORT5_RANGE                 5:5
#define AHCI_PORT_PXSNTF_0_PMN_PORT5_WOFFSET               0
#define AHCI_PORT_PXSNTF_0_PMN_PORT5_DEFAULT               (_MK_MASK_CONST(0x00000000)
#define AHCI_PORT_PXSNTF_0_PMN_PORT5_DEFAULT_MASK          (_MK_MASK_CONST(0x1)
#define AHCI_PORT_PXSNTF_0_PMN_PORT5_SW_DEFAULT            (_MK_MASK_CONST(0x00000000)
#define AHCI_PORT_PXSNTF_0_PMN_PORT5_SW_DEFAULT_MASK       (_MK_MASK_CONST(0x1)
#define AHCI_PORT_PXSNTF_0_PMN_PORT5__NOPRDCHK             _MK_ENUM_CONST(0x00000001)                                                       // ----V
#define AHCI_PORT_PXSNTF_0_PMN_PORT5_NOT_SET               _MK_ENUM_CONST(0x00000000)                                                       // R-I-V
#define AHCI_PORT_PXSNTF_0_PMN_PORT5_SET                   _MK_ENUM_CONST(0x00000001)                                                       // R---V
#define AHCI_PORT_PXSNTF_0_PMN_PORT5_CLEAR                 _MK_ENUM_CONST(0x00000001)                                                       // -W--C
#define AHCI_PORT_PXSNTF_0_PMN_PORT6_SHIFT                  _MK_SHIFT_CONST(6)                                                              // RWIVF
#define AHCI_PORT_PXSNTF_0_PMN_PORT6_FIELD                 (_MK_SHIFT_CONST(0x1) << AHCI_PORT_PXSNTF_0_PMN_PORT6_SHIFT)
#define AHCI_PORT_PXSNTF_0_PMN_PORT6_RANGE                 6:6
#define AHCI_PORT_PXSNTF_0_PMN_PORT6_WOFFSET               0
#define AHCI_PORT_PXSNTF_0_PMN_PORT6_DEFAULT               (_MK_MASK_CONST(0x00000000)
#define AHCI_PORT_PXSNTF_0_PMN_PORT6_DEFAULT_MASK          (_MK_MASK_CONST(0x1)
#define AHCI_PORT_PXSNTF_0_PMN_PORT6_SW_DEFAULT            (_MK_MASK_CONST(0x00000000)
#define AHCI_PORT_PXSNTF_0_PMN_PORT6_SW_DEFAULT_MASK       (_MK_MASK_CONST(0x1)
#define AHCI_PORT_PXSNTF_0_PMN_PORT6__NOPRDCHK             _MK_ENUM_CONST(0x00000001)                                                       // ----V
#define AHCI_PORT_PXSNTF_0_PMN_PORT6_NOT_SET               _MK_ENUM_CONST(0x00000000)                                                       // R-I-V
#define AHCI_PORT_PXSNTF_0_PMN_PORT6_SET                   _MK_ENUM_CONST(0x00000001)                                                       // R---V
#define AHCI_PORT_PXSNTF_0_PMN_PORT6_CLEAR                 _MK_ENUM_CONST(0x00000001)                                                       // -W--C
#define AHCI_PORT_PXSNTF_0_PMN_PORT7_SHIFT                  _MK_SHIFT_CONST(7)                                                              // RWIVF
#define AHCI_PORT_PXSNTF_0_PMN_PORT7_FIELD                 (_MK_SHIFT_CONST(0x1) << AHCI_PORT_PXSNTF_0_PMN_PORT7_SHIFT)
#define AHCI_PORT_PXSNTF_0_PMN_PORT7_RANGE                 7:7
#define AHCI_PORT_PXSNTF_0_PMN_PORT7_WOFFSET               0
#define AHCI_PORT_PXSNTF_0_PMN_PORT7_DEFAULT               (_MK_MASK_CONST(0x00000000)
#define AHCI_PORT_PXSNTF_0_PMN_PORT7_DEFAULT_MASK          (_MK_MASK_CONST(0x1)
#define AHCI_PORT_PXSNTF_0_PMN_PORT7_SW_DEFAULT            (_MK_MASK_CONST(0x00000000)
#define AHCI_PORT_PXSNTF_0_PMN_PORT7_SW_DEFAULT_MASK       (_MK_MASK_CONST(0x1)
#define AHCI_PORT_PXSNTF_0_PMN_PORT7__NOPRDCHK             _MK_ENUM_CONST(0x00000001)                                                       // ----V
#define AHCI_PORT_PXSNTF_0_PMN_PORT7_NOT_SET               _MK_ENUM_CONST(0x00000000)                                                       // R-I-V
#define AHCI_PORT_PXSNTF_0_PMN_PORT7_SET                   _MK_ENUM_CONST(0x00000001)                                                       // R---V
#define AHCI_PORT_PXSNTF_0_PMN_PORT7_CLEAR                 _MK_ENUM_CONST(0x00000001)                                                       // -W--C
#define AHCI_PORT_PXSNTF_0_PMN_PORT8_SHIFT                  _MK_SHIFT_CONST(8)                                                              // RWIVF
#define AHCI_PORT_PXSNTF_0_PMN_PORT8_FIELD                 (_MK_SHIFT_CONST(0x1) << AHCI_PORT_PXSNTF_0_PMN_PORT8_SHIFT)
#define AHCI_PORT_PXSNTF_0_PMN_PORT8_RANGE                 8:8
#define AHCI_PORT_PXSNTF_0_PMN_PORT8_WOFFSET               0
#define AHCI_PORT_PXSNTF_0_PMN_PORT8_DEFAULT               (_MK_MASK_CONST(0x00000000)
#define AHCI_PORT_PXSNTF_0_PMN_PORT8_DEFAULT_MASK          (_MK_MASK_CONST(0x1)
#define AHCI_PORT_PXSNTF_0_PMN_PORT8_SW_DEFAULT            (_MK_MASK_CONST(0x00000000)
#define AHCI_PORT_PXSNTF_0_PMN_PORT8_SW_DEFAULT_MASK       (_MK_MASK_CONST(0x1)
#define AHCI_PORT_PXSNTF_0_PMN_PORT8__NOPRDCHK             _MK_ENUM_CONST(0x00000001)                                                       // ----V
#define AHCI_PORT_PXSNTF_0_PMN_PORT8_NOT_SET               _MK_ENUM_CONST(0x00000000)                                                       // R-I-V
#define AHCI_PORT_PXSNTF_0_PMN_PORT8_SET                   _MK_ENUM_CONST(0x00000001)                                                       // R---V
#define AHCI_PORT_PXSNTF_0_PMN_PORT8_CLEAR                 _MK_ENUM_CONST(0x00000001)                                                       // -W--C
#define AHCI_PORT_PXSNTF_0_PMN_PORT9_SHIFT                  _MK_SHIFT_CONST(9)                                                              // RWIVF
#define AHCI_PORT_PXSNTF_0_PMN_PORT9_FIELD                 (_MK_SHIFT_CONST(0x1) << AHCI_PORT_PXSNTF_0_PMN_PORT9_SHIFT)
#define AHCI_PORT_PXSNTF_0_PMN_PORT9_RANGE                 9:9
#define AHCI_PORT_PXSNTF_0_PMN_PORT9_WOFFSET               0
#define AHCI_PORT_PXSNTF_0_PMN_PORT9_DEFAULT               (_MK_MASK_CONST(0x00000000)
#define AHCI_PORT_PXSNTF_0_PMN_PORT9_DEFAULT_MASK          (_MK_MASK_CONST(0x1)
#define AHCI_PORT_PXSNTF_0_PMN_PORT9_SW_DEFAULT            (_MK_MASK_CONST(0x00000000)
#define AHCI_PORT_PXSNTF_0_PMN_PORT9_SW_DEFAULT_MASK       (_MK_MASK_CONST(0x1)
#define AHCI_PORT_PXSNTF_0_PMN_PORT9__NOPRDCHK             _MK_ENUM_CONST(0x00000001)                                                       // ----V
#define AHCI_PORT_PXSNTF_0_PMN_PORT9_NOT_SET               _MK_ENUM_CONST(0x00000000)                                                       // R-I-V
#define AHCI_PORT_PXSNTF_0_PMN_PORT9_SET                   _MK_ENUM_CONST(0x00000001)                                                       // R---V
#define AHCI_PORT_PXSNTF_0_PMN_PORT9_CLEAR                 _MK_ENUM_CONST(0x00000001)                                                       // -W--C
#define AHCI_PORT_PXSNTF_0_PMN_PORT10_SHIFT                 _MK_SHIFT_CONST(10)                                                             // RWIVF
#define AHCI_PORT_PXSNTF_0_PMN_PORT10_FIELD                (_MK_SHIFT_CONST(0x1) << AHCI_PORT_PXSNTF_0_PMN_PORT10_SHIFT)
#define AHCI_PORT_PXSNTF_0_PMN_PORT10_RANGE                10:10
#define AHCI_PORT_PXSNTF_0_PMN_PORT10_WOFFSET              0
#define AHCI_PORT_PXSNTF_0_PMN_PORT10_DEFAULT              (_MK_MASK_CONST(0x00000000)
#define AHCI_PORT_PXSNTF_0_PMN_PORT10_DEFAULT_MASK         (_MK_MASK_CONST(0x1)
#define AHCI_PORT_PXSNTF_0_PMN_PORT10_SW_DEFAULT           (_MK_MASK_CONST(0x00000000)
#define AHCI_PORT_PXSNTF_0_PMN_PORT10_SW_DEFAULT_MASK      (_MK_MASK_CONST(0x1)
#define AHCI_PORT_PXSNTF_0_PMN_PORT10__NOPRDCHK            _MK_ENUM_CONST(0x00000001)                                                       // ----V
#define AHCI_PORT_PXSNTF_0_PMN_PORT10_NOT_SET              _MK_ENUM_CONST(0x00000000)                                                       // R-I-V
#define AHCI_PORT_PXSNTF_0_PMN_PORT10_SET                  _MK_ENUM_CONST(0x00000001)                                                       // R---V
#define AHCI_PORT_PXSNTF_0_PMN_PORT10_CLEAR                _MK_ENUM_CONST(0x00000001)                                                       // -W--C
#define AHCI_PORT_PXSNTF_0_PMN_PORT11_SHIFT                 _MK_SHIFT_CONST(11)                                                             // RWIVF
#define AHCI_PORT_PXSNTF_0_PMN_PORT11_FIELD                (_MK_SHIFT_CONST(0x1) << AHCI_PORT_PXSNTF_0_PMN_PORT11_SHIFT)
#define AHCI_PORT_PXSNTF_0_PMN_PORT11_RANGE                11:11
#define AHCI_PORT_PXSNTF_0_PMN_PORT11_WOFFSET              0
#define AHCI_PORT_PXSNTF_0_PMN_PORT11_DEFAULT              (_MK_MASK_CONST(0x00000000)
#define AHCI_PORT_PXSNTF_0_PMN_PORT11_DEFAULT_MASK         (_MK_MASK_CONST(0x1)
#define AHCI_PORT_PXSNTF_0_PMN_PORT11_SW_DEFAULT           (_MK_MASK_CONST(0x00000000)
#define AHCI_PORT_PXSNTF_0_PMN_PORT11_SW_DEFAULT_MASK      (_MK_MASK_CONST(0x1)
#define AHCI_PORT_PXSNTF_0_PMN_PORT11__NOPRDCHK            _MK_ENUM_CONST(0x00000001)                                                       // ----V
#define AHCI_PORT_PXSNTF_0_PMN_PORT11_NOT_SET              _MK_ENUM_CONST(0x00000000)                                                       // R-I-V
#define AHCI_PORT_PXSNTF_0_PMN_PORT11_SET                  _MK_ENUM_CONST(0x00000001)                                                       // R---V
#define AHCI_PORT_PXSNTF_0_PMN_PORT11_CLEAR                _MK_ENUM_CONST(0x00000001)                                                       // -W--C
#define AHCI_PORT_PXSNTF_0_PMN_PORT12_SHIFT                 _MK_SHIFT_CONST(12)                                                             // RWIVF
#define AHCI_PORT_PXSNTF_0_PMN_PORT12_FIELD                (_MK_SHIFT_CONST(0x1) << AHCI_PORT_PXSNTF_0_PMN_PORT12_SHIFT)
#define AHCI_PORT_PXSNTF_0_PMN_PORT12_RANGE                12:12
#define AHCI_PORT_PXSNTF_0_PMN_PORT12_WOFFSET              0
#define AHCI_PORT_PXSNTF_0_PMN_PORT12_DEFAULT              (_MK_MASK_CONST(0x00000000)
#define AHCI_PORT_PXSNTF_0_PMN_PORT12_DEFAULT_MASK         (_MK_MASK_CONST(0x1)
#define AHCI_PORT_PXSNTF_0_PMN_PORT12_SW_DEFAULT           (_MK_MASK_CONST(0x00000000)
#define AHCI_PORT_PXSNTF_0_PMN_PORT12_SW_DEFAULT_MASK      (_MK_MASK_CONST(0x1)
#define AHCI_PORT_PXSNTF_0_PMN_PORT12__NOPRDCHK            _MK_ENUM_CONST(0x00000001)                                                       // ----V
#define AHCI_PORT_PXSNTF_0_PMN_PORT12_NOT_SET              _MK_ENUM_CONST(0x00000000)                                                       // R-I-V
#define AHCI_PORT_PXSNTF_0_PMN_PORT12_SET                  _MK_ENUM_CONST(0x00000001)                                                       // R---V
#define AHCI_PORT_PXSNTF_0_PMN_PORT12_CLEAR                _MK_ENUM_CONST(0x00000001)                                                       // -W--C
#define AHCI_PORT_PXSNTF_0_PMN_PORT13_SHIFT                 _MK_SHIFT_CONST(13)                                                             // RWIVF
#define AHCI_PORT_PXSNTF_0_PMN_PORT13_FIELD                (_MK_SHIFT_CONST(0x1) << AHCI_PORT_PXSNTF_0_PMN_PORT13_SHIFT)
#define AHCI_PORT_PXSNTF_0_PMN_PORT13_RANGE                13:13
#define AHCI_PORT_PXSNTF_0_PMN_PORT13_WOFFSET              0
#define AHCI_PORT_PXSNTF_0_PMN_PORT13_DEFAULT              (_MK_MASK_CONST(0x00000000)
#define AHCI_PORT_PXSNTF_0_PMN_PORT13_DEFAULT_MASK         (_MK_MASK_CONST(0x1)
#define AHCI_PORT_PXSNTF_0_PMN_PORT13_SW_DEFAULT           (_MK_MASK_CONST(0x00000000)
#define AHCI_PORT_PXSNTF_0_PMN_PORT13_SW_DEFAULT_MASK      (_MK_MASK_CONST(0x1)
#define AHCI_PORT_PXSNTF_0_PMN_PORT13__NOPRDCHK            _MK_ENUM_CONST(0x00000001)                                                       // ----V
#define AHCI_PORT_PXSNTF_0_PMN_PORT13_NOT_SET              _MK_ENUM_CONST(0x00000000)                                                       // R-I-V
#define AHCI_PORT_PXSNTF_0_PMN_PORT13_SET                  _MK_ENUM_CONST(0x00000001)                                                       // R---V
#define AHCI_PORT_PXSNTF_0_PMN_PORT13_CLEAR                _MK_ENUM_CONST(0x00000001)                                                       // -W--C
#define AHCI_PORT_PXSNTF_0_PMN_PORT14_SHIFT                 _MK_SHIFT_CONST(14)                                                             // RWIVF
#define AHCI_PORT_PXSNTF_0_PMN_PORT14_FIELD                (_MK_SHIFT_CONST(0x1) << AHCI_PORT_PXSNTF_0_PMN_PORT14_SHIFT)
#define AHCI_PORT_PXSNTF_0_PMN_PORT14_RANGE                14:14
#define AHCI_PORT_PXSNTF_0_PMN_PORT14_WOFFSET              0
#define AHCI_PORT_PXSNTF_0_PMN_PORT14_DEFAULT              (_MK_MASK_CONST(0x00000000)
#define AHCI_PORT_PXSNTF_0_PMN_PORT14_DEFAULT_MASK         (_MK_MASK_CONST(0x1)
#define AHCI_PORT_PXSNTF_0_PMN_PORT14_SW_DEFAULT           (_MK_MASK_CONST(0x00000000)
#define AHCI_PORT_PXSNTF_0_PMN_PORT14_SW_DEFAULT_MASK      (_MK_MASK_CONST(0x1)
#define AHCI_PORT_PXSNTF_0_PMN_PORT14__NOPRDCHK            _MK_ENUM_CONST(0x00000001)                                                       // ----V
#define AHCI_PORT_PXSNTF_0_PMN_PORT14_NOT_SET              _MK_ENUM_CONST(0x00000000)                                                       // R-I-V
#define AHCI_PORT_PXSNTF_0_PMN_PORT14_SET                  _MK_ENUM_CONST(0x00000001)                                                       // R---V
#define AHCI_PORT_PXSNTF_0_PMN_PORT14_CLEAR                _MK_ENUM_CONST(0x00000001)                                                       // -W--C
#define AHCI_PORT_PXSNTF_0_PMN_PORT15_SHIFT                 _MK_SHIFT_CONST(15)                                                             // RWIVF
#define AHCI_PORT_PXSNTF_0_PMN_PORT15_FIELD                (_MK_SHIFT_CONST(0x1) << AHCI_PORT_PXSNTF_0_PMN_PORT15_SHIFT)
#define AHCI_PORT_PXSNTF_0_PMN_PORT15_RANGE                15:15
#define AHCI_PORT_PXSNTF_0_PMN_PORT15_WOFFSET              0
#define AHCI_PORT_PXSNTF_0_PMN_PORT15_DEFAULT              (_MK_MASK_CONST(0x00000000)
#define AHCI_PORT_PXSNTF_0_PMN_PORT15_DEFAULT_MASK         (_MK_MASK_CONST(0x1)
#define AHCI_PORT_PXSNTF_0_PMN_PORT15_SW_DEFAULT           (_MK_MASK_CONST(0x00000000)
#define AHCI_PORT_PXSNTF_0_PMN_PORT15_SW_DEFAULT_MASK      (_MK_MASK_CONST(0x1)
#define AHCI_PORT_PXSNTF_0_PMN_PORT15__NOPRDCHK            _MK_ENUM_CONST(0x00000001)                                                       // ----V
#define AHCI_PORT_PXSNTF_0_PMN_PORT15_NOT_SET              _MK_ENUM_CONST(0x00000000)                                                       // R-I-V
#define AHCI_PORT_PXSNTF_0_PMN_PORT15_SET                  _MK_ENUM_CONST(0x00000001)                                                       // R---V
#define AHCI_PORT_PXSNTF_0_PMN_PORT15_CLEAR                _MK_ENUM_CONST(0x00000001)                                                       // -W--C
// 
// 
//              Figure 9-XXX Port SNotification Register.
// 
// 
// 
// 
// .TITLE Port Rsvd for FIS Based Switiching
// .FIELD
// 
// 31           24 23           16 15            8 7             0
// .-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-.
// |0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0| PORT_PXFBS
// `-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-'
#define AHCI_PORT_PXFBS_0                                  0x00000140                                                                       // RW-4R
#define AHCI_PORT_PXFBS_0_SECURE                           0
#define AHCI_PORT_PXFBS_0_WORD_COUNT                       1
#define AHCI_PORT_PXFBS_0_RESET_VAL                        0xf000
#define AHCI_PORT_PXFBS_0_RESET_MASK                       0xfff06
#define AHCI_PORT_PXFBS_0_SW_DEFAULT_VAL                   0xf000
#define AHCI_PORT_PXFBS_0_SW_DEFAULT_MASK                  0xfff06
#define AHCI_PORT_PXFBS_0_READ_MASK                        0xffffffff
#define AHCI_PORT_PXFBS_0_WRITE_MASK                       0xf02
#define AHCI_PORT_PXFBS_0_EN_SHIFT                          _MK_SHIFT_CONST(0)                                                              // C--VF
#define AHCI_PORT_PXFBS_0_EN_FIELD                         (_MK_SHIFT_CONST(0x1) << AHCI_PORT_PXFBS_0_EN_SHIFT)
#define AHCI_PORT_PXFBS_0_EN_RANGE                         0:0
#define AHCI_PORT_PXFBS_0_EN_WOFFSET                       0
#define AHCI_PORT_PXFBS_0_EN_FALSE                         _MK_ENUM_CONST(0x00000000)                                                       // C---V
#define AHCI_PORT_PXFBS_0_DEC_SHIFT                         _MK_SHIFT_CONST(1)                                                              // RWIVF
#define AHCI_PORT_PXFBS_0_DEC_FIELD                        (_MK_SHIFT_CONST(0x1) << AHCI_PORT_PXFBS_0_DEC_SHIFT)
#define AHCI_PORT_PXFBS_0_DEC_RANGE                        1:1
#define AHCI_PORT_PXFBS_0_DEC_WOFFSET                      0
#define AHCI_PORT_PXFBS_0_DEC_DEFAULT                      (_MK_MASK_CONST(0x00000000)
#define AHCI_PORT_PXFBS_0_DEC_DEFAULT_MASK                 (_MK_MASK_CONST(0x1)
#define AHCI_PORT_PXFBS_0_DEC_SW_DEFAULT                   (_MK_MASK_CONST(0x00000000)
#define AHCI_PORT_PXFBS_0_DEC_SW_DEFAULT_MASK              (_MK_MASK_CONST(0x1)
#define AHCI_PORT_PXFBS_0_DEC_NOT                          _MK_ENUM_CONST(0x00000000)                                                       // R-I-V
#define AHCI_PORT_PXFBS_0_DEC_TRUE                         _MK_ENUM_CONST(0x00000001)                                                       // R---V
#define AHCI_PORT_PXFBS_0_DEC_SET                          _MK_ENUM_CONST(0x00000001)                                                       // -W--T
#define AHCI_PORT_PXFBS_0_SDE_SHIFT                         _MK_SHIFT_CONST(2)                                                              // R-I-F
#define AHCI_PORT_PXFBS_0_SDE_FIELD                        (_MK_SHIFT_CONST(0x1) << AHCI_PORT_PXFBS_0_SDE_SHIFT)
#define AHCI_PORT_PXFBS_0_SDE_RANGE                        2:2
#define AHCI_PORT_PXFBS_0_SDE_WOFFSET                      0
#define AHCI_PORT_PXFBS_0_SDE_DEFAULT                      (_MK_MASK_CONST(0)
#define AHCI_PORT_PXFBS_0_SDE_DEFAULT_MASK                 (_MK_MASK_CONST(0x1)
#define AHCI_PORT_PXFBS_0_SDE_SW_DEFAULT                   (_MK_MASK_CONST(0)
#define AHCI_PORT_PXFBS_0_SDE_SW_DEFAULT_MASK              (_MK_MASK_CONST(0x1)
#define AHCI_PORT_PXFBS_0_RSVD_7_3_SHIFT                    _MK_SHIFT_CONST(3)                                                              // C--VF
#define AHCI_PORT_PXFBS_0_RSVD_7_3_FIELD                   (_MK_SHIFT_CONST(0x1f) << AHCI_PORT_PXFBS_0_RSVD_7_3_SHIFT)
#define AHCI_PORT_PXFBS_0_RSVD_7_3_RANGE                   7:3
#define AHCI_PORT_PXFBS_0_RSVD_7_3_WOFFSET                 0
#define AHCI_PORT_PXFBS_0_RSVD_7_3_0                       _MK_ENUM_CONST(0x00000000)                                                       // C---V
#define AHCI_PORT_PXFBS_0_DEV_SHIFT                         _MK_SHIFT_CONST(8)                                                              // RWI-F
#define AHCI_PORT_PXFBS_0_DEV_FIELD                        (_MK_SHIFT_CONST(0xf) << AHCI_PORT_PXFBS_0_DEV_SHIFT)
#define AHCI_PORT_PXFBS_0_DEV_RANGE                        11:8
#define AHCI_PORT_PXFBS_0_DEV_WOFFSET                      0
#define AHCI_PORT_PXFBS_0_DEV_DEFAULT                      (_MK_MASK_CONST(0x00000000)
#define AHCI_PORT_PXFBS_0_DEV_DEFAULT_MASK                 (_MK_MASK_CONST(0xf)
#define AHCI_PORT_PXFBS_0_DEV_SW_DEFAULT                   (_MK_MASK_CONST(0x00000000)
#define AHCI_PORT_PXFBS_0_DEV_SW_DEFAULT_MASK              (_MK_MASK_CONST(0xf)
#define AHCI_PORT_PXFBS_0_ADO_SHIFT                         _MK_SHIFT_CONST(12)                                                             // R-I-F
#define AHCI_PORT_PXFBS_0_ADO_FIELD                        (_MK_SHIFT_CONST(0xf) << AHCI_PORT_PXFBS_0_ADO_SHIFT)
#define AHCI_PORT_PXFBS_0_ADO_RANGE                        15:12
#define AHCI_PORT_PXFBS_0_ADO_WOFFSET                      0
#define AHCI_PORT_PXFBS_0_ADO_DEFAULT                      (_MK_MASK_CONST(0x0000000F)
#define AHCI_PORT_PXFBS_0_ADO_DEFAULT_MASK                 (_MK_MASK_CONST(0xf)
#define AHCI_PORT_PXFBS_0_ADO_SW_DEFAULT                   (_MK_MASK_CONST(0x0000000F)
#define AHCI_PORT_PXFBS_0_ADO_SW_DEFAULT_MASK              (_MK_MASK_CONST(0xf)
#define AHCI_PORT_PXFBS_0_DWE_SHIFT                         _MK_SHIFT_CONST(16)                                                             // R-I-F
#define AHCI_PORT_PXFBS_0_DWE_FIELD                        (_MK_SHIFT_CONST(0xf) << AHCI_PORT_PXFBS_0_DWE_SHIFT)
#define AHCI_PORT_PXFBS_0_DWE_RANGE                        19:16
#define AHCI_PORT_PXFBS_0_DWE_WOFFSET                      0
#define AHCI_PORT_PXFBS_0_DWE_DEFAULT                      (_MK_MASK_CONST(0x00000000)
#define AHCI_PORT_PXFBS_0_DWE_DEFAULT_MASK                 (_MK_MASK_CONST(0xf)
#define AHCI_PORT_PXFBS_0_DWE_SW_DEFAULT                   (_MK_MASK_CONST(0x00000000)
#define AHCI_PORT_PXFBS_0_DWE_SW_DEFAULT_MASK              (_MK_MASK_CONST(0xf)
#define AHCI_PORT_PXFBS_0_RSVD_31_20_SHIFT                  _MK_SHIFT_CONST(20)                                                             // C--VF
#define AHCI_PORT_PXFBS_0_RSVD_31_20_FIELD                 (_MK_SHIFT_CONST(0xfff) << AHCI_PORT_PXFBS_0_RSVD_31_20_SHIFT)
#define AHCI_PORT_PXFBS_0_RSVD_31_20_RANGE                 31:20
#define AHCI_PORT_PXFBS_0_RSVD_31_20_WOFFSET               0
#define AHCI_PORT_PXFBS_0_RSVD_31_20_0                     _MK_ENUM_CONST(0x00000000)                                                       // C---V
// 
//              Figure 9-XXX Port Rsvd for FIS Based Switiching Register.
// 
// .TITLE Port Device Sleep
// .FIELD
// 
// 31           24 23           16 15            8 7             0
// .-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-.
// |0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0| PORT_PXDEVSLP
// `-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-'
// 
#define AHCI_PORT_PXDEVSLP_0                               0x00000144                                                                       // RW-4R
#define AHCI_PORT_PXDEVSLP_0_SECURE                        0
#define AHCI_PORT_PXDEVSLP_0_WORD_COUNT                    1
#define AHCI_PORT_PXDEVSLP_0_RESET_VAL                     0x52450
#define AHCI_PORT_PXDEVSLP_0_RESET_MASK                    0x1ffffff
#define AHCI_PORT_PXDEVSLP_0_SW_DEFAULT_VAL                0x52450
#define AHCI_PORT_PXDEVSLP_0_SW_DEFAULT_MASK               0x1ffffff
#define AHCI_PORT_PXDEVSLP_0_READ_MASK                     0xffffffff
#define AHCI_PORT_PXDEVSLP_0_WRITE_MASK                    0x1fffffd
#define AHCI_PORT_PXDEVSLP_0_ADSE_SHIFT                     _MK_SHIFT_CONST(0)                                                              // RWIVF
#define AHCI_PORT_PXDEVSLP_0_ADSE_FIELD                    (_MK_SHIFT_CONST(0x1) << AHCI_PORT_PXDEVSLP_0_ADSE_SHIFT)
#define AHCI_PORT_PXDEVSLP_0_ADSE_RANGE                    0:0
#define AHCI_PORT_PXDEVSLP_0_ADSE_WOFFSET                  0
#define AHCI_PORT_PXDEVSLP_0_ADSE_DEFAULT                  (_MK_MASK_CONST(0x00000000)
#define AHCI_PORT_PXDEVSLP_0_ADSE_DEFAULT_MASK             (_MK_MASK_CONST(0x1)
#define AHCI_PORT_PXDEVSLP_0_ADSE_SW_DEFAULT               (_MK_MASK_CONST(0x00000000)
#define AHCI_PORT_PXDEVSLP_0_ADSE_SW_DEFAULT_MASK          (_MK_MASK_CONST(0x1)
#define AHCI_PORT_PXDEVSLP_0_ADSE_TRUE                     _MK_ENUM_CONST(0x00000000)                                                       // RWI-V
#define AHCI_PORT_PXDEVSLP_0_ADSE_FALSE                    _MK_ENUM_CONST(0x00000001)                                                       // R---V
#define AHCI_PORT_PXDEVSLP_0_DSP_SHIFT                      _MK_SHIFT_CONST(1)                                                              // R-IVF
#define AHCI_PORT_PXDEVSLP_0_DSP_FIELD                     (_MK_SHIFT_CONST(0x1) << AHCI_PORT_PXDEVSLP_0_DSP_SHIFT)
#define AHCI_PORT_PXDEVSLP_0_DSP_RANGE                     1:1
#define AHCI_PORT_PXDEVSLP_0_DSP_WOFFSET                   0
#define AHCI_PORT_PXDEVSLP_0_DSP_DEFAULT                   (_MK_MASK_CONST(0x00000000)
#define AHCI_PORT_PXDEVSLP_0_DSP_DEFAULT_MASK              (_MK_MASK_CONST(0x1)
#define AHCI_PORT_PXDEVSLP_0_DSP_SW_DEFAULT                (_MK_MASK_CONST(0x00000000)
#define AHCI_PORT_PXDEVSLP_0_DSP_SW_DEFAULT_MASK           (_MK_MASK_CONST(0x1)
#define AHCI_PORT_PXDEVSLP_0_DSP_TRUE                      _MK_ENUM_CONST(0x00000000)                                                       // R-I-V
#define AHCI_PORT_PXDEVSLP_0_DSP_FALSE                     _MK_ENUM_CONST(0x00000001)                                                       // R---V
#define AHCI_PORT_PXDEVSLP_0_DETO_SHIFT                     _MK_SHIFT_CONST(2)                                                              // RWIVF
#define AHCI_PORT_PXDEVSLP_0_DETO_FIELD                    (_MK_SHIFT_CONST(0xff) << AHCI_PORT_PXDEVSLP_0_DETO_SHIFT)
#define AHCI_PORT_PXDEVSLP_0_DETO_RANGE                    9:2
#define AHCI_PORT_PXDEVSLP_0_DETO_WOFFSET                  0
#define AHCI_PORT_PXDEVSLP_0_DETO_DEFAULT                  (_MK_MASK_CONST(0x00000014)
#define AHCI_PORT_PXDEVSLP_0_DETO_DEFAULT_MASK             (_MK_MASK_CONST(0xff)
#define AHCI_PORT_PXDEVSLP_0_DETO_SW_DEFAULT               (_MK_MASK_CONST(0x00000014)
#define AHCI_PORT_PXDEVSLP_0_DETO_SW_DEFAULT_MASK          (_MK_MASK_CONST(0xff)
#define AHCI_PORT_PXDEVSLP_0_MDAT_SHIFT                     _MK_SHIFT_CONST(10)                                                             // RWIVF
#define AHCI_PORT_PXDEVSLP_0_MDAT_FIELD                    (_MK_SHIFT_CONST(0x1f) << AHCI_PORT_PXDEVSLP_0_MDAT_SHIFT)
#define AHCI_PORT_PXDEVSLP_0_MDAT_RANGE                    14:10
#define AHCI_PORT_PXDEVSLP_0_MDAT_WOFFSET                  0
#define AHCI_PORT_PXDEVSLP_0_MDAT_DEFAULT                  (_MK_MASK_CONST(0x00000009)
#define AHCI_PORT_PXDEVSLP_0_MDAT_DEFAULT_MASK             (_MK_MASK_CONST(0x1f)
#define AHCI_PORT_PXDEVSLP_0_MDAT_SW_DEFAULT               (_MK_MASK_CONST(0x00000009)
#define AHCI_PORT_PXDEVSLP_0_MDAT_SW_DEFAULT_MASK          (_MK_MASK_CONST(0x1f)
#define AHCI_PORT_PXDEVSLP_0_DITO_SHIFT                     _MK_SHIFT_CONST(15)                                                             // RWIVF
#define AHCI_PORT_PXDEVSLP_0_DITO_FIELD                    (_MK_SHIFT_CONST(0x3ff) << AHCI_PORT_PXDEVSLP_0_DITO_SHIFT)
#define AHCI_PORT_PXDEVSLP_0_DITO_RANGE                    24:15
#define AHCI_PORT_PXDEVSLP_0_DITO_WOFFSET                  0
#define AHCI_PORT_PXDEVSLP_0_DITO_DEFAULT                  (_MK_MASK_CONST(0x0000000A)
#define AHCI_PORT_PXDEVSLP_0_DITO_DEFAULT_MASK             (_MK_MASK_CONST(0x3ff)
#define AHCI_PORT_PXDEVSLP_0_DITO_SW_DEFAULT               (_MK_MASK_CONST(0x0000000A)
#define AHCI_PORT_PXDEVSLP_0_DITO_SW_DEFAULT_MASK          (_MK_MASK_CONST(0x3ff)
#define AHCI_PORT_PXDEVSLP_0_DM_SHIFT                       _MK_SHIFT_CONST(25)                                                             // R-WVF
#define AHCI_PORT_PXDEVSLP_0_DM_FIELD                      (_MK_SHIFT_CONST(0xf) << AHCI_PORT_PXDEVSLP_0_DM_SHIFT)
#define AHCI_PORT_PXDEVSLP_0_DM_RANGE                      28:25
#define AHCI_PORT_PXDEVSLP_0_DM_WOFFSET                    0
#define AHCI_PORT_PXDEVSLP_0_DM_DEFAULT                    (_MK_MASK_CONST(0x00000000)
#define AHCI_PORT_PXDEVSLP_0_DM_DEFAULT_MASK               (_MK_MASK_CONST(0xf)
#define AHCI_PORT_PXDEVSLP_0_DM_SW_DEFAULT                 (_MK_MASK_CONST(0x00000000)
#define AHCI_PORT_PXDEVSLP_0_DM_SW_DEFAULT_MASK            (_MK_MASK_CONST(0xf)
#define AHCI_PORT_PXDEVSLP_0_RSVD_31_29_SHIFT               _MK_SHIFT_CONST(29)                                                             // C--VF
#define AHCI_PORT_PXDEVSLP_0_RSVD_31_29_FIELD              (_MK_SHIFT_CONST(0x7) << AHCI_PORT_PXDEVSLP_0_RSVD_31_29_SHIFT)
#define AHCI_PORT_PXDEVSLP_0_RSVD_31_29_RANGE              31:29
#define AHCI_PORT_PXDEVSLP_0_RSVD_31_29_WOFFSET            0
#define AHCI_PORT_PXDEVSLP_0_RSVD_31_29_0                  _MK_ENUM_CONST(0x00000000)                                                       // C---V
// 
//                         Figure 9- XXX Port Device Sleep
// 
// .TITLE Port Vendor Specific Regsiters
// 
// .LABEL PRIVATE INT_REL
// .FIELD CLAMP_THIS_CH
//     This is used to enable/disable Clamping capability for individual channel(both devclk and txclk)
//     NO_CLAMP_SHUTDOWN should be made 0 if CLAMP_THIS_CH are used.
// 
// .LABEL PUBLIC
// .FIELD PORT_UNCONNECTED
//   This is to be written by the BIOS during the initial boot-up when it finds a port unconnected
// 
// 31           24 23           16 15            8 7             0
// .-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-.
// |0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0| PORT_BKDR
// `-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-'
#define AHCI_PORT_BKDR_0                                   0x00000170                                                                       // RW-4R
#define AHCI_PORT_BKDR_0_SECURE                            0
#define AHCI_PORT_BKDR_0_WORD_COUNT                        1
#define AHCI_PORT_BKDR_0_RESET_VAL                         0x0
#define AHCI_PORT_BKDR_0_RESET_MASK                        0xff1f00f0
#define AHCI_PORT_BKDR_0_SW_DEFAULT_VAL                    0x0
#define AHCI_PORT_BKDR_0_SW_DEFAULT_MASK                   0xff1f00f0
#define AHCI_PORT_BKDR_0_READ_MASK                         0xff1fffff
#define AHCI_PORT_BKDR_0_WRITE_MASK                        0xff1fffff
#define AHCI_PORT_BKDR_0_EXT_SATA_SUPP_SHIFT                _MK_SHIFT_CONST(0)                                                              // RWCVF
#define AHCI_PORT_BKDR_0_EXT_SATA_SUPP_FIELD               (_MK_SHIFT_CONST(0x1) << AHCI_PORT_BKDR_0_EXT_SATA_SUPP_SHIFT)
#define AHCI_PORT_BKDR_0_EXT_SATA_SUPP_RANGE               0:0
#define AHCI_PORT_BKDR_0_EXT_SATA_SUPP_WOFFSET             0
#define AHCI_PORT_BKDR_0_EXT_SATA_SUPP_TRUE                _MK_ENUM_CONST(0x00000001)                                                       // RW--V
#define AHCI_PORT_BKDR_0_EXT_SATA_SUPP_FALSE               _MK_ENUM_CONST(0x00000000)                                                       // RWC-V
#define AHCI_PORT_BKDR_0_COLD_PRSN_DET_SHIFT                _MK_SHIFT_CONST(1)                                                              // RWCVF
#define AHCI_PORT_BKDR_0_COLD_PRSN_DET_FIELD               (_MK_SHIFT_CONST(0x1) << AHCI_PORT_BKDR_0_COLD_PRSN_DET_SHIFT)
#define AHCI_PORT_BKDR_0_COLD_PRSN_DET_RANGE               1:1
#define AHCI_PORT_BKDR_0_COLD_PRSN_DET_WOFFSET             0
#define AHCI_PORT_BKDR_0_COLD_PRSN_DET_SUPP                _MK_ENUM_CONST(0x00000001)                                                       // RW--V
#define AHCI_PORT_BKDR_0_COLD_PRSN_DET_NOT_SUPP            _MK_ENUM_CONST(0x00000000)                                                       // RWC-V
#define AHCI_PORT_BKDR_0_MECH_SWITCH_SHIFT                  _MK_SHIFT_CONST(2)                                                              // RWCVF
#define AHCI_PORT_BKDR_0_MECH_SWITCH_FIELD                 (_MK_SHIFT_CONST(0x1) << AHCI_PORT_BKDR_0_MECH_SWITCH_SHIFT)
#define AHCI_PORT_BKDR_0_MECH_SWITCH_RANGE                 2:2
#define AHCI_PORT_BKDR_0_MECH_SWITCH_WOFFSET               0
#define AHCI_PORT_BKDR_0_MECH_SWITCH_SUPP                  _MK_ENUM_CONST(0x00000001)                                                       // RW--V
#define AHCI_PORT_BKDR_0_MECH_SWITCH_NOT_SUPP              _MK_ENUM_CONST(0x00000000)                                                       // RWC-V
#define AHCI_PORT_BKDR_0_HOTPLUG_CAP_SHIFT                  _MK_SHIFT_CONST(3)                                                              // RWCVF
#define AHCI_PORT_BKDR_0_HOTPLUG_CAP_FIELD                 (_MK_SHIFT_CONST(0x1) << AHCI_PORT_BKDR_0_HOTPLUG_CAP_SHIFT)
#define AHCI_PORT_BKDR_0_HOTPLUG_CAP_RANGE                 3:3
#define AHCI_PORT_BKDR_0_HOTPLUG_CAP_WOFFSET               0
#define AHCI_PORT_BKDR_0_HOTPLUG_CAP_SUPP                  _MK_ENUM_CONST(0x00000001)                                                       // RW--V
#define AHCI_PORT_BKDR_0_HOTPLUG_CAP_NOT_SUPP              _MK_ENUM_CONST(0x00000000)                                                       // RWC-V
#define AHCI_PORT_BKDR_0_CLK_CLAMP_CTRL_DEVCLK_CLAMP_SHIFT  _MK_SHIFT_CONST(4)                                                              // RWI-F
#define AHCI_PORT_BKDR_0_CLK_CLAMP_CTRL_DEVCLK_CLAMP_FIELD (_MK_SHIFT_CONST(0x1) << AHCI_PORT_BKDR_0_CLK_CLAMP_CTRL_DEVCLK_CLAMP_SHIFT)
#define AHCI_PORT_BKDR_0_CLK_CLAMP_CTRL_DEVCLK_CLAMP_RANGE 4:4
#define AHCI_PORT_BKDR_0_CLK_CLAMP_CTRL_DEVCLK_CLAMP_WOFFSET 0
#define AHCI_PORT_BKDR_0_CLK_CLAMP_CTRL_DEVCLK_CLAMP_DEFAULT (_MK_MASK_CONST(0x00000000)
#define AHCI_PORT_BKDR_0_CLK_CLAMP_CTRL_DEVCLK_CLAMP_DEFAULT_MASK (_MK_MASK_CONST(0x1)
#define AHCI_PORT_BKDR_0_CLK_CLAMP_CTRL_DEVCLK_CLAMP_SW_DEFAULT (_MK_MASK_CONST(0x00000000)
#define AHCI_PORT_BKDR_0_CLK_CLAMP_CTRL_DEVCLK_CLAMP_SW_DEFAULT_MASK (_MK_MASK_CONST(0x1)
#define AHCI_PORT_BKDR_0_CLK_CLAMP_CTRL_DEVCLK_CLAMP_NO    _MK_ENUM_CONST(0x00000000)                                                       // RWI-V
#define AHCI_PORT_BKDR_0_CLK_CLAMP_CTRL_DEVCLK_CLAMP_YES   _MK_ENUM_CONST(0x00000001)                                                       // RW--V
#define AHCI_PORT_BKDR_0_CLK_CLAMP_CTRL_DEVCLK_CLAMP_SET   _MK_ENUM_CONST(0x00000001)                                                       // -W--T
#define AHCI_PORT_BKDR_0_CLK_CLAMP_CTRL_DEVCLK_UNCLAMP_SHIFT  _MK_SHIFT_CONST(5)                                                              // RWI-F
#define AHCI_PORT_BKDR_0_CLK_CLAMP_CTRL_DEVCLK_UNCLAMP_FIELD (_MK_SHIFT_CONST(0x1) << AHCI_PORT_BKDR_0_CLK_CLAMP_CTRL_DEVCLK_UNCLAMP_SHIFT)
#define AHCI_PORT_BKDR_0_CLK_CLAMP_CTRL_DEVCLK_UNCLAMP_RANGE 5:5
#define AHCI_PORT_BKDR_0_CLK_CLAMP_CTRL_DEVCLK_UNCLAMP_WOFFSET 0
#define AHCI_PORT_BKDR_0_CLK_CLAMP_CTRL_DEVCLK_UNCLAMP_DEFAULT (_MK_MASK_CONST(0x00000000)
#define AHCI_PORT_BKDR_0_CLK_CLAMP_CTRL_DEVCLK_UNCLAMP_DEFAULT_MASK (_MK_MASK_CONST(0x1)
#define AHCI_PORT_BKDR_0_CLK_CLAMP_CTRL_DEVCLK_UNCLAMP_SW_DEFAULT (_MK_MASK_CONST(0x00000000)
#define AHCI_PORT_BKDR_0_CLK_CLAMP_CTRL_DEVCLK_UNCLAMP_SW_DEFAULT_MASK (_MK_MASK_CONST(0x1)
#define AHCI_PORT_BKDR_0_CLK_CLAMP_CTRL_DEVCLK_UNCLAMP_NO  _MK_ENUM_CONST(0x00000000)                                                       // RWI-V
#define AHCI_PORT_BKDR_0_CLK_CLAMP_CTRL_DEVCLK_UNCLAMP_YES _MK_ENUM_CONST(0x00000001)                                                       // RW--V
#define AHCI_PORT_BKDR_0_CLK_CLAMP_CTRL_DEVCLK_UNCLAMP_SET _MK_ENUM_CONST(0x00000001)                                                       // -W--T
#define AHCI_PORT_BKDR_0_CLK_CLAMP_CTRL_TXRXCLK_CLAMP_SHIFT  _MK_SHIFT_CONST(6)                                                              // RWI-F
#define AHCI_PORT_BKDR_0_CLK_CLAMP_CTRL_TXRXCLK_CLAMP_FIELD (_MK_SHIFT_CONST(0x1) << AHCI_PORT_BKDR_0_CLK_CLAMP_CTRL_TXRXCLK_CLAMP_SHIFT)
#define AHCI_PORT_BKDR_0_CLK_CLAMP_CTRL_TXRXCLK_CLAMP_RANGE 6:6
#define AHCI_PORT_BKDR_0_CLK_CLAMP_CTRL_TXRXCLK_CLAMP_WOFFSET 0
#define AHCI_PORT_BKDR_0_CLK_CLAMP_CTRL_TXRXCLK_CLAMP_DEFAULT (_MK_MASK_CONST(0x00000000)
#define AHCI_PORT_BKDR_0_CLK_CLAMP_CTRL_TXRXCLK_CLAMP_DEFAULT_MASK (_MK_MASK_CONST(0x1)
#define AHCI_PORT_BKDR_0_CLK_CLAMP_CTRL_TXRXCLK_CLAMP_SW_DEFAULT (_MK_MASK_CONST(0x00000000)
#define AHCI_PORT_BKDR_0_CLK_CLAMP_CTRL_TXRXCLK_CLAMP_SW_DEFAULT_MASK (_MK_MASK_CONST(0x1)
#define AHCI_PORT_BKDR_0_CLK_CLAMP_CTRL_TXRXCLK_CLAMP_NO   _MK_ENUM_CONST(0x00000000)                                                       // RWI-V
#define AHCI_PORT_BKDR_0_CLK_CLAMP_CTRL_TXRXCLK_CLAMP_YES  _MK_ENUM_CONST(0x00000001)                                                       // RW--V
#define AHCI_PORT_BKDR_0_CLK_CLAMP_CTRL_TXRXCLK_CLAMP_SET  _MK_ENUM_CONST(0x00000001)                                                       // -W--T
#define AHCI_PORT_BKDR_0_CLK_CLAMP_CTRL_TXRXCLK_UNCLAMP_SHIFT  _MK_SHIFT_CONST(7)                                                              // RWI-F
#define AHCI_PORT_BKDR_0_CLK_CLAMP_CTRL_TXRXCLK_UNCLAMP_FIELD (_MK_SHIFT_CONST(0x1) << AHCI_PORT_BKDR_0_CLK_CLAMP_CTRL_TXRXCLK_UNCLAMP_SHIFT)
#define AHCI_PORT_BKDR_0_CLK_CLAMP_CTRL_TXRXCLK_UNCLAMP_RANGE 7:7
#define AHCI_PORT_BKDR_0_CLK_CLAMP_CTRL_TXRXCLK_UNCLAMP_WOFFSET 0
#define AHCI_PORT_BKDR_0_CLK_CLAMP_CTRL_TXRXCLK_UNCLAMP_DEFAULT (_MK_MASK_CONST(0x00000000)
#define AHCI_PORT_BKDR_0_CLK_CLAMP_CTRL_TXRXCLK_UNCLAMP_DEFAULT_MASK (_MK_MASK_CONST(0x1)
#define AHCI_PORT_BKDR_0_CLK_CLAMP_CTRL_TXRXCLK_UNCLAMP_SW_DEFAULT (_MK_MASK_CONST(0x00000000)
#define AHCI_PORT_BKDR_0_CLK_CLAMP_CTRL_TXRXCLK_UNCLAMP_SW_DEFAULT_MASK (_MK_MASK_CONST(0x1)
#define AHCI_PORT_BKDR_0_CLK_CLAMP_CTRL_TXRXCLK_UNCLAMP_NO _MK_ENUM_CONST(0x00000000)                                                       // RWI-V
#define AHCI_PORT_BKDR_0_CLK_CLAMP_CTRL_TXRXCLK_UNCLAMP_YES _MK_ENUM_CONST(0x00000001)                                                       // RW--V
#define AHCI_PORT_BKDR_0_CLK_CLAMP_CTRL_TXRXCLK_UNCLAMP_SET _MK_ENUM_CONST(0x00000001)                                                       // -W--T
#define AHCI_PORT_BKDR_0_CLK_CLAMP_CTRL_CLAMP_THIS_CH_SHIFT  _MK_SHIFT_CONST(8)                                                              // RWC-F
#define AHCI_PORT_BKDR_0_CLK_CLAMP_CTRL_CLAMP_THIS_CH_FIELD (_MK_SHIFT_CONST(0x1) << AHCI_PORT_BKDR_0_CLK_CLAMP_CTRL_CLAMP_THIS_CH_SHIFT)
#define AHCI_PORT_BKDR_0_CLK_CLAMP_CTRL_CLAMP_THIS_CH_RANGE 8:8
#define AHCI_PORT_BKDR_0_CLK_CLAMP_CTRL_CLAMP_THIS_CH_WOFFSET 0
#define AHCI_PORT_BKDR_0_CLK_CLAMP_CTRL_CLAMP_THIS_CH_YES  _MK_ENUM_CONST(0x00000001)                                                       // RWC-V
#define AHCI_PORT_BKDR_0_CLK_CLAMP_CTRL_CLAMP_THIS_CH_NO   _MK_ENUM_CONST(0x00000000)                                                       // RW--V
#define AHCI_PORT_BKDR_0_PORT_UNCONNECTED_SHIFT             _MK_SHIFT_CONST(9)                                                              // RWC-F
#define AHCI_PORT_BKDR_0_PORT_UNCONNECTED_FIELD            (_MK_SHIFT_CONST(0x1) << AHCI_PORT_BKDR_0_PORT_UNCONNECTED_SHIFT)
#define AHCI_PORT_BKDR_0_PORT_UNCONNECTED_RANGE            9:9
#define AHCI_PORT_BKDR_0_PORT_UNCONNECTED_WOFFSET          0
#define AHCI_PORT_BKDR_0_PORT_UNCONNECTED_YES              _MK_ENUM_CONST(0x00000001)                                                       // RW--V
#define AHCI_PORT_BKDR_0_PORT_UNCONNECTED_NO               _MK_ENUM_CONST(0x00000000)                                                       // RWC-V
#define AHCI_PORT_BKDR_0_PORT_UNCONNECTED_DONE             _MK_ENUM_CONST(0x00000001)                                                       // -W--T
#define AHCI_PORT_BKDR_0_PXDEVSLP_DM_SHIFT                  _MK_SHIFT_CONST(10)                                                             // RWWVF
#define AHCI_PORT_BKDR_0_PXDEVSLP_DM_FIELD                 (_MK_SHIFT_CONST(0xf) << AHCI_PORT_BKDR_0_PXDEVSLP_DM_SHIFT)
#define AHCI_PORT_BKDR_0_PXDEVSLP_DM_RANGE                 13:10
#define AHCI_PORT_BKDR_0_PXDEVSLP_DM_WOFFSET               0
#define AHCI_PORT_BKDR_0_PXDEVSLP_MDAT_OVERRIDE_SHIFT       _MK_SHIFT_CONST(14)                                                             // RWWVF
#define AHCI_PORT_BKDR_0_PXDEVSLP_MDAT_OVERRIDE_FIELD      (_MK_SHIFT_CONST(0x1) << AHCI_PORT_BKDR_0_PXDEVSLP_MDAT_OVERRIDE_SHIFT)
#define AHCI_PORT_BKDR_0_PXDEVSLP_MDAT_OVERRIDE_RANGE      14:14
#define AHCI_PORT_BKDR_0_PXDEVSLP_MDAT_OVERRIDE_WOFFSET    0
#define AHCI_PORT_BKDR_0_PXDEVSLP_DETO_OVERRIDE_SHIFT       _MK_SHIFT_CONST(15)                                                             // RWWVF
#define AHCI_PORT_BKDR_0_PXDEVSLP_DETO_OVERRIDE_FIELD      (_MK_SHIFT_CONST(0x1) << AHCI_PORT_BKDR_0_PXDEVSLP_DETO_OVERRIDE_SHIFT)
#define AHCI_PORT_BKDR_0_PXDEVSLP_DETO_OVERRIDE_RANGE      15:15
#define AHCI_PORT_BKDR_0_PXDEVSLP_DETO_OVERRIDE_WOFFSET    0
#define AHCI_PORT_BKDR_0_PXDEVSLP_MDAT_OVERRIDE_VAL_SHIFT   _MK_SHIFT_CONST(16)                                                             // RWIVF
#define AHCI_PORT_BKDR_0_PXDEVSLP_MDAT_OVERRIDE_VAL_FIELD  (_MK_SHIFT_CONST(0x1f) << AHCI_PORT_BKDR_0_PXDEVSLP_MDAT_OVERRIDE_VAL_SHIFT)
#define AHCI_PORT_BKDR_0_PXDEVSLP_MDAT_OVERRIDE_VAL_RANGE  20:16
#define AHCI_PORT_BKDR_0_PXDEVSLP_MDAT_OVERRIDE_VAL_WOFFSET 0
#define AHCI_PORT_BKDR_0_PXDEVSLP_MDAT_OVERRIDE_VAL_DEFAULT (_MK_MASK_CONST(0x00000000)
#define AHCI_PORT_BKDR_0_PXDEVSLP_MDAT_OVERRIDE_VAL_DEFAULT_MASK (_MK_MASK_CONST(0x1f)
#define AHCI_PORT_BKDR_0_PXDEVSLP_MDAT_OVERRIDE_VAL_SW_DEFAULT (_MK_MASK_CONST(0x00000000)
#define AHCI_PORT_BKDR_0_PXDEVSLP_MDAT_OVERRIDE_VAL_SW_DEFAULT_MASK (_MK_MASK_CONST(0x1f)
#define AHCI_PORT_BKDR_0_PXDEVSLP_DETO_OVERRIDE_VAL_SHIFT   _MK_SHIFT_CONST(24)                                                             // RWIVF
#define AHCI_PORT_BKDR_0_PXDEVSLP_DETO_OVERRIDE_VAL_FIELD  (_MK_SHIFT_CONST(0xff) << AHCI_PORT_BKDR_0_PXDEVSLP_DETO_OVERRIDE_VAL_SHIFT)
#define AHCI_PORT_BKDR_0_PXDEVSLP_DETO_OVERRIDE_VAL_RANGE  31:24
#define AHCI_PORT_BKDR_0_PXDEVSLP_DETO_OVERRIDE_VAL_WOFFSET 0
#define AHCI_PORT_BKDR_0_PXDEVSLP_DETO_OVERRIDE_VAL_DEFAULT (_MK_MASK_CONST(0x00000000)
#define AHCI_PORT_BKDR_0_PXDEVSLP_DETO_OVERRIDE_VAL_DEFAULT_MASK (_MK_MASK_CONST(0xff)
#define AHCI_PORT_BKDR_0_PXDEVSLP_DETO_OVERRIDE_VAL_SW_DEFAULT (_MK_MASK_CONST(0x00000000)
#define AHCI_PORT_BKDR_0_PXDEVSLP_DETO_OVERRIDE_VAL_SW_DEFAULT_MASK (_MK_MASK_CONST(0xff)
// 
// .LABEL PRIVATE INT_REL
// 
// 
// 
// 
// 
// .LABEL PUBLIC
// 
// .LABEL PRIVATE INT_REL
// 
// 
// .TITLE Port Interrupt Source
// Each of the field indicates what specific condition caused the DUT to raise a fatal/non-fatal interrupt.
// Each of the fields can be masked by the corresponding mask register.
// 
// 31           24 23           16 15            8 7             0
// .-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-.
// |0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0| PORT_INT
// `-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-'
#define AHCI_PORT_INTR_0                                   0x00000174                                                                       // RWI4R
#define AHCI_PORT_INTR_0_SECURE                            0
#define AHCI_PORT_INTR_0_WORD_COUNT                        1
#define AHCI_PORT_INTR_0_RESET_VAL                         0x0
#define AHCI_PORT_INTR_0_RESET_MASK                        0x0
#define AHCI_PORT_INTR_0_SW_DEFAULT_VAL                    0x0
#define AHCI_PORT_INTR_0_SW_DEFAULT_MASK                   0x0
#define AHCI_PORT_INTR_0_READ_MASK                         0xffffffff
#define AHCI_PORT_INTR_0_WRITE_MASK                        0xffff0000
#define AHCI_PORT_INTR_0_OFS_RX_SHIFT                       _MK_SHIFT_CONST(0)                                                              // R-CVF
#define AHCI_PORT_INTR_0_OFS_RX_FIELD                      (_MK_SHIFT_CONST(0x1) << AHCI_PORT_INTR_0_OFS_RX_SHIFT)
#define AHCI_PORT_INTR_0_OFS_RX_RANGE                      0:0
#define AHCI_PORT_INTR_0_OFS_RX_WOFFSET                    0
#define AHCI_PORT_INTR_0_OFS_RX_CLEAR                      _MK_ENUM_CONST(0x00000000)                                                       // R-C-V
#define AHCI_PORT_INTR_0_OFS_RX_SET                        _MK_ENUM_CONST(0x00000001)                                                       // R---V
#define AHCI_PORT_INTR_0_OFS_TX_SHIFT                       _MK_SHIFT_CONST(1)                                                              // R-CVF
#define AHCI_PORT_INTR_0_OFS_TX_FIELD                      (_MK_SHIFT_CONST(0x1) << AHCI_PORT_INTR_0_OFS_TX_SHIFT)
#define AHCI_PORT_INTR_0_OFS_TX_RANGE                      1:1
#define AHCI_PORT_INTR_0_OFS_TX_WOFFSET                    0
#define AHCI_PORT_INTR_0_OFS_TX_CLEAR                      _MK_ENUM_CONST(0x00000000)                                                       // R-C-V
#define AHCI_PORT_INTR_0_OFS_TX_SET                        _MK_ENUM_CONST(0x00000001)                                                       // R---V
#define AHCI_PORT_INTR_0_IFS_NCQ_TX_RX_SHIFT                _MK_SHIFT_CONST(2)                                                              // R-CVF
#define AHCI_PORT_INTR_0_IFS_NCQ_TX_RX_FIELD               (_MK_SHIFT_CONST(0x1) << AHCI_PORT_INTR_0_IFS_NCQ_TX_RX_SHIFT)
#define AHCI_PORT_INTR_0_IFS_NCQ_TX_RX_RANGE               2:2
#define AHCI_PORT_INTR_0_IFS_NCQ_TX_RX_WOFFSET             0
#define AHCI_PORT_INTR_0_IFS_NCQ_TX_RX_CLEAR               _MK_ENUM_CONST(0x00000000)                                                       // R-C-V
#define AHCI_PORT_INTR_0_IFS_NCQ_TX_RX_SET                 _MK_ENUM_CONST(0x00000001)                                                       // R---V
#define AHCI_PORT_INTR_0_IFS_ATAPI_CMD_XMIT_SHIFT           _MK_SHIFT_CONST(3)                                                              // R-CVF
#define AHCI_PORT_INTR_0_IFS_ATAPI_CMD_XMIT_FIELD          (_MK_SHIFT_CONST(0x1) << AHCI_PORT_INTR_0_IFS_ATAPI_CMD_XMIT_SHIFT)
#define AHCI_PORT_INTR_0_IFS_ATAPI_CMD_XMIT_RANGE          3:3
#define AHCI_PORT_INTR_0_IFS_ATAPI_CMD_XMIT_WOFFSET        0
#define AHCI_PORT_INTR_0_IFS_ATAPI_CMD_XMIT_CLEAR          _MK_ENUM_CONST(0x00000000)                                                       // R-C-V
#define AHCI_PORT_INTR_0_IFS_ATAPI_CMD_XMIT_SET            _MK_ENUM_CONST(0x00000001)                                                       // R---V
#define AHCI_PORT_INTR_0_IFS_DATA_FIS_XMIT_SHIFT            _MK_SHIFT_CONST(4)                                                              // R-CVF
#define AHCI_PORT_INTR_0_IFS_DATA_FIS_XMIT_FIELD           (_MK_SHIFT_CONST(0x1) << AHCI_PORT_INTR_0_IFS_DATA_FIS_XMIT_SHIFT)
#define AHCI_PORT_INTR_0_IFS_DATA_FIS_XMIT_RANGE           4:4
#define AHCI_PORT_INTR_0_IFS_DATA_FIS_XMIT_WOFFSET         0
#define AHCI_PORT_INTR_0_IFS_DATA_FIS_XMIT_CLEAR           _MK_ENUM_CONST(0x00000000)                                                       // R-C-V
#define AHCI_PORT_INTR_0_IFS_DATA_FIS_XMIT_SET             _MK_ENUM_CONST(0x00000001)                                                       // R---V
#define AHCI_PORT_INTR_0_IFS_DATA_FIS_RECV_SHIFT            _MK_SHIFT_CONST(5)                                                              // R-CVF
#define AHCI_PORT_INTR_0_IFS_DATA_FIS_RECV_FIELD           (_MK_SHIFT_CONST(0x1) << AHCI_PORT_INTR_0_IFS_DATA_FIS_RECV_SHIFT)
#define AHCI_PORT_INTR_0_IFS_DATA_FIS_RECV_RANGE           5:5
#define AHCI_PORT_INTR_0_IFS_DATA_FIS_RECV_WOFFSET         0
#define AHCI_PORT_INTR_0_IFS_DATA_FIS_RECV_CLEAR           _MK_ENUM_CONST(0x00000000)                                                       // R-C-V
#define AHCI_PORT_INTR_0_IFS_DATA_FIS_RECV_SET             _MK_ENUM_CONST(0x00000001)                                                       // R---V
#define AHCI_PORT_INTR_0_IFS_NONNCQ_TX_RX_SHIFT             _MK_SHIFT_CONST(6)                                                              // R-CVF
#define AHCI_PORT_INTR_0_IFS_NONNCQ_TX_RX_FIELD            (_MK_SHIFT_CONST(0x1) << AHCI_PORT_INTR_0_IFS_NONNCQ_TX_RX_SHIFT)
#define AHCI_PORT_INTR_0_IFS_NONNCQ_TX_RX_RANGE            6:6
#define AHCI_PORT_INTR_0_IFS_NONNCQ_TX_RX_WOFFSET          0
#define AHCI_PORT_INTR_0_IFS_NONNCQ_TX_RX_CLEAR            _MK_ENUM_CONST(0x00000000)                                                       // R-C-V
#define AHCI_PORT_INTR_0_IFS_NONNCQ_TX_RX_SET              _MK_ENUM_CONST(0x00000001)                                                       // R---V
#define AHCI_PORT_INTR_0_IFS_SYNC_ESCAPE_RECV_SHIFT         _MK_SHIFT_CONST(7)                                                              // R-CVF
#define AHCI_PORT_INTR_0_IFS_SYNC_ESCAPE_RECV_FIELD        (_MK_SHIFT_CONST(0x1) << AHCI_PORT_INTR_0_IFS_SYNC_ESCAPE_RECV_SHIFT)
#define AHCI_PORT_INTR_0_IFS_SYNC_ESCAPE_RECV_RANGE        7:7
#define AHCI_PORT_INTR_0_IFS_SYNC_ESCAPE_RECV_WOFFSET      0
#define AHCI_PORT_INTR_0_IFS_SYNC_ESCAPE_RECV_CLEAR        _MK_ENUM_CONST(0x00000000)                                                       // R-C-V
#define AHCI_PORT_INTR_0_IFS_SYNC_ESCAPE_RECV_SET          _MK_ENUM_CONST(0x00000001)                                                       // R---V
#define AHCI_PORT_INTR_0_IFS_FIFO_OVERWRITTEN_SHIFT         _MK_SHIFT_CONST(8)                                                              // R-CVF
#define AHCI_PORT_INTR_0_IFS_FIFO_OVERWRITTEN_FIELD        (_MK_SHIFT_CONST(0x1) << AHCI_PORT_INTR_0_IFS_FIFO_OVERWRITTEN_SHIFT)
#define AHCI_PORT_INTR_0_IFS_FIFO_OVERWRITTEN_RANGE        8:8
#define AHCI_PORT_INTR_0_IFS_FIFO_OVERWRITTEN_WOFFSET      0
#define AHCI_PORT_INTR_0_IFS_FIFO_OVERWRITTEN_CLEAR        _MK_ENUM_CONST(0x00000000)                                                       // R-C-V
#define AHCI_PORT_INTR_0_IFS_FIFO_OVERWRITTEN_SET          _MK_ENUM_CONST(0x00000001)                                                       // R---V
#define AHCI_PORT_INTR_0_IFS_DMA_CNT_ERROR_SHIFT            _MK_SHIFT_CONST(9)                                                              // R-CVF
#define AHCI_PORT_INTR_0_IFS_DMA_CNT_ERROR_FIELD           (_MK_SHIFT_CONST(0x1) << AHCI_PORT_INTR_0_IFS_DMA_CNT_ERROR_SHIFT)
#define AHCI_PORT_INTR_0_IFS_DMA_CNT_ERROR_RANGE           9:9
#define AHCI_PORT_INTR_0_IFS_DMA_CNT_ERROR_WOFFSET         0
#define AHCI_PORT_INTR_0_IFS_DMA_CNT_ERROR_CLEAR           _MK_ENUM_CONST(0x00000000)                                                       // R-C-V
#define AHCI_PORT_INTR_0_IFS_DMA_CNT_ERROR_SET             _MK_ENUM_CONST(0x00000001)                                                       // R---V
#define AHCI_PORT_INTR_0_INFS_UFIS_SIZE_SHIFT               _MK_SHIFT_CONST(10)                                                             // R-CVF
#define AHCI_PORT_INTR_0_INFS_UFIS_SIZE_FIELD              (_MK_SHIFT_CONST(0x1) << AHCI_PORT_INTR_0_INFS_UFIS_SIZE_SHIFT)
#define AHCI_PORT_INTR_0_INFS_UFIS_SIZE_RANGE              10:10
#define AHCI_PORT_INTR_0_INFS_UFIS_SIZE_WOFFSET            0
#define AHCI_PORT_INTR_0_INFS_UFIS_SIZE_CLEAR              _MK_ENUM_CONST(0x00000000)                                                       // R-C-V
#define AHCI_PORT_INTR_0_INFS_UFIS_SIZE_SET                _MK_ENUM_CONST(0x00000001)                                                       // R---V
#define AHCI_PORT_INTR_0_INFS_NONDATA_FIS_SIZE_SHIFT        _MK_SHIFT_CONST(11)                                                             // R-CVF
#define AHCI_PORT_INTR_0_INFS_NONDATA_FIS_SIZE_FIELD       (_MK_SHIFT_CONST(0x1) << AHCI_PORT_INTR_0_INFS_NONDATA_FIS_SIZE_SHIFT)
#define AHCI_PORT_INTR_0_INFS_NONDATA_FIS_SIZE_RANGE       11:11
#define AHCI_PORT_INTR_0_INFS_NONDATA_FIS_SIZE_WOFFSET     0
#define AHCI_PORT_INTR_0_INFS_NONDATA_FIS_SIZE_CLEAR       _MK_ENUM_CONST(0x00000000)                                                       // R-C-V
#define AHCI_PORT_INTR_0_INFS_NONDATA_FIS_SIZE_SET         _MK_ENUM_CONST(0x00000001)                                                       // R---V
#define AHCI_PORT_INTR_0_INFS_PMP_MISMATCH_SHIFT            _MK_SHIFT_CONST(12)                                                             // R-CVF
#define AHCI_PORT_INTR_0_INFS_PMP_MISMATCH_FIELD           (_MK_SHIFT_CONST(0x1) << AHCI_PORT_INTR_0_INFS_PMP_MISMATCH_SHIFT)
#define AHCI_PORT_INTR_0_INFS_PMP_MISMATCH_RANGE           12:12
#define AHCI_PORT_INTR_0_INFS_PMP_MISMATCH_WOFFSET         0
#define AHCI_PORT_INTR_0_INFS_PMP_MISMATCH_CLEAR           _MK_ENUM_CONST(0x00000000)                                                       // R-C-V
#define AHCI_PORT_INTR_0_INFS_PMP_MISMATCH_SET             _MK_ENUM_CONST(0x00000001)                                                       // R---V
#define AHCI_PORT_INTR_0_INFS_NONDATA_FIS_CRC_ERROR_SHIFT   _MK_SHIFT_CONST(13)                                                             // R-CVF
#define AHCI_PORT_INTR_0_INFS_NONDATA_FIS_CRC_ERROR_FIELD  (_MK_SHIFT_CONST(0x1) << AHCI_PORT_INTR_0_INFS_NONDATA_FIS_CRC_ERROR_SHIFT)
#define AHCI_PORT_INTR_0_INFS_NONDATA_FIS_CRC_ERROR_RANGE  13:13
#define AHCI_PORT_INTR_0_INFS_NONDATA_FIS_CRC_ERROR_WOFFSET 0
#define AHCI_PORT_INTR_0_INFS_NONDATA_FIS_CRC_ERROR_CLEAR  _MK_ENUM_CONST(0x00000000)                                                       // R-C-V
#define AHCI_PORT_INTR_0_INFS_NONDATA_FIS_CRC_ERROR_SET    _MK_ENUM_CONST(0x00000001)                                                       // R---V
#define AHCI_PORT_INTR_0_IFS_FPDMA_TAG_ERROR_SHIFT          _MK_SHIFT_CONST(14)                                                             // R-CVF
#define AHCI_PORT_INTR_0_IFS_FPDMA_TAG_ERROR_FIELD         (_MK_SHIFT_CONST(0x1) << AHCI_PORT_INTR_0_IFS_FPDMA_TAG_ERROR_SHIFT)
#define AHCI_PORT_INTR_0_IFS_FPDMA_TAG_ERROR_RANGE         14:14
#define AHCI_PORT_INTR_0_IFS_FPDMA_TAG_ERROR_WOFFSET       0
#define AHCI_PORT_INTR_0_IFS_FPDMA_TAG_ERROR_CLEAR         _MK_ENUM_CONST(0x00000000)                                                       // R-C-V
#define AHCI_PORT_INTR_0_IFS_FPDMA_TAG_ERROR_SET           _MK_ENUM_CONST(0x00000001)                                                       // R---V
#define AHCI_PORT_INTR_0_IFS_NCQ_NON_NCQ_MIX_SHIFT          _MK_SHIFT_CONST(15)                                                             // R-CVF
#define AHCI_PORT_INTR_0_IFS_NCQ_NON_NCQ_MIX_FIELD         (_MK_SHIFT_CONST(0x1) << AHCI_PORT_INTR_0_IFS_NCQ_NON_NCQ_MIX_SHIFT)
#define AHCI_PORT_INTR_0_IFS_NCQ_NON_NCQ_MIX_RANGE         15:15
#define AHCI_PORT_INTR_0_IFS_NCQ_NON_NCQ_MIX_WOFFSET       0
#define AHCI_PORT_INTR_0_IFS_NCQ_NON_NCQ_MIX_INIT          _MK_ENUM_CONST(0x00000000)                                                       // R-C-V
#define AHCI_PORT_INTR_0_IFS_NCQ_NON_NCQ_MIX_SET           _MK_ENUM_CONST(0x00000001)                                                       // R---V
#define AHCI_PORT_INTR_0_EN_OFS_RX_SHIFT                    _MK_SHIFT_CONST(16)                                                             // RWCVF
#define AHCI_PORT_INTR_0_EN_OFS_RX_FIELD                   (_MK_SHIFT_CONST(0x1) << AHCI_PORT_INTR_0_EN_OFS_RX_SHIFT)
#define AHCI_PORT_INTR_0_EN_OFS_RX_RANGE                   16:16
#define AHCI_PORT_INTR_0_EN_OFS_RX_WOFFSET                 0
#define AHCI_PORT_INTR_0_EN_OFS_RX_CLEARED                 _MK_ENUM_CONST(0x00000000)                                                       // RW--V
#define AHCI_PORT_INTR_0_EN_OFS_RX_SET                     _MK_ENUM_CONST(0x00000001)                                                       // RWC-V
#define AHCI_PORT_INTR_0_EN_OFS_TX_SHIFT                    _MK_SHIFT_CONST(17)                                                             // RWCVF
#define AHCI_PORT_INTR_0_EN_OFS_TX_FIELD                   (_MK_SHIFT_CONST(0x1) << AHCI_PORT_INTR_0_EN_OFS_TX_SHIFT)
#define AHCI_PORT_INTR_0_EN_OFS_TX_RANGE                   17:17
#define AHCI_PORT_INTR_0_EN_OFS_TX_WOFFSET                 0
#define AHCI_PORT_INTR_0_EN_OFS_TX_CLEARED                 _MK_ENUM_CONST(0x00000000)                                                       // RW--V
#define AHCI_PORT_INTR_0_EN_OFS_TX_SET                     _MK_ENUM_CONST(0x00000001)                                                       // RWC-V
#define AHCI_PORT_INTR_0_EN_IFS_NCQ_TX_RX_UNDERFLOW_SHIFT   _MK_SHIFT_CONST(18)                                                             // RWCVF
#define AHCI_PORT_INTR_0_EN_IFS_NCQ_TX_RX_UNDERFLOW_FIELD  (_MK_SHIFT_CONST(0x1) << AHCI_PORT_INTR_0_EN_IFS_NCQ_TX_RX_UNDERFLOW_SHIFT)
#define AHCI_PORT_INTR_0_EN_IFS_NCQ_TX_RX_UNDERFLOW_RANGE  18:18
#define AHCI_PORT_INTR_0_EN_IFS_NCQ_TX_RX_UNDERFLOW_WOFFSET 0
#define AHCI_PORT_INTR_0_EN_IFS_NCQ_TX_RX_UNDERFLOW_CLEARED _MK_ENUM_CONST(0x00000000)                                                       // RW--V
#define AHCI_PORT_INTR_0_EN_IFS_NCQ_TX_RX_UNDERFLOW_SET    _MK_ENUM_CONST(0x00000000)                                                       // RWC-V
#define AHCI_PORT_INTR_0_EN_IFS_ATAPI_CMD_XMIT_SHIFT        _MK_SHIFT_CONST(19)                                                             // RWCVF
#define AHCI_PORT_INTR_0_EN_IFS_ATAPI_CMD_XMIT_FIELD       (_MK_SHIFT_CONST(0x1) << AHCI_PORT_INTR_0_EN_IFS_ATAPI_CMD_XMIT_SHIFT)
#define AHCI_PORT_INTR_0_EN_IFS_ATAPI_CMD_XMIT_RANGE       19:19
#define AHCI_PORT_INTR_0_EN_IFS_ATAPI_CMD_XMIT_WOFFSET     0
#define AHCI_PORT_INTR_0_EN_IFS_ATAPI_CMD_XMIT_CLEARED     _MK_ENUM_CONST(0x00000000)                                                       // RW--V
#define AHCI_PORT_INTR_0_EN_IFS_ATAPI_CMD_XMIT_SET         _MK_ENUM_CONST(0x00000001)                                                       // RWC-V
#define AHCI_PORT_INTR_0_EN_IFS_DATA_FIS_XMIT_SHIFT         _MK_SHIFT_CONST(20)                                                             // RWCVF
#define AHCI_PORT_INTR_0_EN_IFS_DATA_FIS_XMIT_FIELD        (_MK_SHIFT_CONST(0x1) << AHCI_PORT_INTR_0_EN_IFS_DATA_FIS_XMIT_SHIFT)
#define AHCI_PORT_INTR_0_EN_IFS_DATA_FIS_XMIT_RANGE        20:20
#define AHCI_PORT_INTR_0_EN_IFS_DATA_FIS_XMIT_WOFFSET      0
#define AHCI_PORT_INTR_0_EN_IFS_DATA_FIS_XMIT_CLEARED      _MK_ENUM_CONST(0x00000000)                                                       // RW--V
#define AHCI_PORT_INTR_0_EN_IFS_DATA_FIS_XMIT_SET          _MK_ENUM_CONST(0x00000001)                                                       // RWC-V
#define AHCI_PORT_INTR_0_EN_IFS_DATA_FIS_RECV_SHIFT         _MK_SHIFT_CONST(21)                                                             // RWCVF
#define AHCI_PORT_INTR_0_EN_IFS_DATA_FIS_RECV_FIELD        (_MK_SHIFT_CONST(0x1) << AHCI_PORT_INTR_0_EN_IFS_DATA_FIS_RECV_SHIFT)
#define AHCI_PORT_INTR_0_EN_IFS_DATA_FIS_RECV_RANGE        21:21
#define AHCI_PORT_INTR_0_EN_IFS_DATA_FIS_RECV_WOFFSET      0
#define AHCI_PORT_INTR_0_EN_IFS_DATA_FIS_RECV_CLEARED      _MK_ENUM_CONST(0x00000000)                                                       // RW--V
#define AHCI_PORT_INTR_0_EN_IFS_DATA_FIS_RECV_SET          _MK_ENUM_CONST(0x00000001)                                                       // RWC-V
#define AHCI_PORT_INTR_0_EN_IFS_NONNCQ_TX_RX_UNDERFLOW_SHIFT  _MK_SHIFT_CONST(22)                                                             // RWCVF
#define AHCI_PORT_INTR_0_EN_IFS_NONNCQ_TX_RX_UNDERFLOW_FIELD (_MK_SHIFT_CONST(0x1) << AHCI_PORT_INTR_0_EN_IFS_NONNCQ_TX_RX_UNDERFLOW_SHIFT)
#define AHCI_PORT_INTR_0_EN_IFS_NONNCQ_TX_RX_UNDERFLOW_RANGE 22:22
#define AHCI_PORT_INTR_0_EN_IFS_NONNCQ_TX_RX_UNDERFLOW_WOFFSET 0
#define AHCI_PORT_INTR_0_EN_IFS_NONNCQ_TX_RX_UNDERFLOW_CLEARED _MK_ENUM_CONST(0x00000000)                                                       // RW--V
#define AHCI_PORT_INTR_0_EN_IFS_NONNCQ_TX_RX_UNDERFLOW_SET _MK_ENUM_CONST(0x00000001)                                                       // RWC-V
#define AHCI_PORT_INTR_0_EN_IFS_SYNC_ESCAPE_RECV_SHIFT      _MK_SHIFT_CONST(23)                                                             // RWCVF
#define AHCI_PORT_INTR_0_EN_IFS_SYNC_ESCAPE_RECV_FIELD     (_MK_SHIFT_CONST(0x1) << AHCI_PORT_INTR_0_EN_IFS_SYNC_ESCAPE_RECV_SHIFT)
#define AHCI_PORT_INTR_0_EN_IFS_SYNC_ESCAPE_RECV_RANGE     23:23
#define AHCI_PORT_INTR_0_EN_IFS_SYNC_ESCAPE_RECV_WOFFSET   0
#define AHCI_PORT_INTR_0_EN_IFS_SYNC_ESCAPE_RECV_CLEARED   _MK_ENUM_CONST(0x00000000)                                                       // RW--V
#define AHCI_PORT_INTR_0_EN_IFS_SYNC_ESCAPE_RECV_SET       _MK_ENUM_CONST(0x00000001)                                                       // RWC-V
#define AHCI_PORT_INTR_0_EN_IFS_FIFO_OVERWRITTEN_SHIFT      _MK_SHIFT_CONST(24)                                                             // RWCVF
#define AHCI_PORT_INTR_0_EN_IFS_FIFO_OVERWRITTEN_FIELD     (_MK_SHIFT_CONST(0x1) << AHCI_PORT_INTR_0_EN_IFS_FIFO_OVERWRITTEN_SHIFT)
#define AHCI_PORT_INTR_0_EN_IFS_FIFO_OVERWRITTEN_RANGE     24:24
#define AHCI_PORT_INTR_0_EN_IFS_FIFO_OVERWRITTEN_WOFFSET   0
#define AHCI_PORT_INTR_0_EN_IFS_FIFO_OVERWRITTEN_CLEARED   _MK_ENUM_CONST(0x00000000)                                                       // RW--V
#define AHCI_PORT_INTR_0_EN_IFS_FIFO_OVERWRITTEN_SET       _MK_ENUM_CONST(0x00000001)                                                       // RWC-V
#define AHCI_PORT_INTR_0_EN_IFS_DMA_CNT_ERROR_SHIFT         _MK_SHIFT_CONST(25)                                                             // RWCVF
#define AHCI_PORT_INTR_0_EN_IFS_DMA_CNT_ERROR_FIELD        (_MK_SHIFT_CONST(0x1) << AHCI_PORT_INTR_0_EN_IFS_DMA_CNT_ERROR_SHIFT)
#define AHCI_PORT_INTR_0_EN_IFS_DMA_CNT_ERROR_RANGE        25:25
#define AHCI_PORT_INTR_0_EN_IFS_DMA_CNT_ERROR_WOFFSET      0
#define AHCI_PORT_INTR_0_EN_IFS_DMA_CNT_ERROR_CLEARED      _MK_ENUM_CONST(0x00000000)                                                       // RW--V
#define AHCI_PORT_INTR_0_EN_IFS_DMA_CNT_ERROR_SET          _MK_ENUM_CONST(0x00000001)                                                       // RWC-V
#define AHCI_PORT_INTR_0_EN_INFS_UFIS_SIZE_SHIFT            _MK_SHIFT_CONST(26)                                                             // RWCVF
#define AHCI_PORT_INTR_0_EN_INFS_UFIS_SIZE_FIELD           (_MK_SHIFT_CONST(0x1) << AHCI_PORT_INTR_0_EN_INFS_UFIS_SIZE_SHIFT)
#define AHCI_PORT_INTR_0_EN_INFS_UFIS_SIZE_RANGE           26:26
#define AHCI_PORT_INTR_0_EN_INFS_UFIS_SIZE_WOFFSET         0
#define AHCI_PORT_INTR_0_EN_INFS_UFIS_SIZE_CLEARED         _MK_ENUM_CONST(0x00000000)                                                       // RW--V
#define AHCI_PORT_INTR_0_EN_INFS_UFIS_SIZE_SET             _MK_ENUM_CONST(0x00000001)                                                       // RWC-V
#define AHCI_PORT_INTR_0_EN_INFS_NONDATA_FIS_SIZE_SHIFT     _MK_SHIFT_CONST(27)                                                             // RWCVF
#define AHCI_PORT_INTR_0_EN_INFS_NONDATA_FIS_SIZE_FIELD    (_MK_SHIFT_CONST(0x1) << AHCI_PORT_INTR_0_EN_INFS_NONDATA_FIS_SIZE_SHIFT)
#define AHCI_PORT_INTR_0_EN_INFS_NONDATA_FIS_SIZE_RANGE    27:27
#define AHCI_PORT_INTR_0_EN_INFS_NONDATA_FIS_SIZE_WOFFSET  0
#define AHCI_PORT_INTR_0_EN_INFS_NONDATA_FIS_SIZE_CLEARED  _MK_ENUM_CONST(0x00000000)                                                       // RW--V
#define AHCI_PORT_INTR_0_EN_INFS_NONDATA_FIS_SIZE_SET      _MK_ENUM_CONST(0x00000001)                                                       // RWC-V
#define AHCI_PORT_INTR_0_EN_INFS_PMP_MISMATCH_SHIFT         _MK_SHIFT_CONST(28)                                                             // RWCVF
#define AHCI_PORT_INTR_0_EN_INFS_PMP_MISMATCH_FIELD        (_MK_SHIFT_CONST(0x1) << AHCI_PORT_INTR_0_EN_INFS_PMP_MISMATCH_SHIFT)
#define AHCI_PORT_INTR_0_EN_INFS_PMP_MISMATCH_RANGE        28:28
#define AHCI_PORT_INTR_0_EN_INFS_PMP_MISMATCH_WOFFSET      0
#define AHCI_PORT_INTR_0_EN_INFS_PMP_MISMATCH_CLEARED      _MK_ENUM_CONST(0x00000000)                                                       // RW--V
#define AHCI_PORT_INTR_0_EN_INFS_PMP_MISMATCH_SET          _MK_ENUM_CONST(0x00000001)                                                       // RWC-V
#define AHCI_PORT_INTR_0_EN_INFS_NONDATA_FIS_CRC_ERROR_SHIFT  _MK_SHIFT_CONST(29)                                                             // RWCVF
#define AHCI_PORT_INTR_0_EN_INFS_NONDATA_FIS_CRC_ERROR_FIELD (_MK_SHIFT_CONST(0x1) << AHCI_PORT_INTR_0_EN_INFS_NONDATA_FIS_CRC_ERROR_SHIFT)
#define AHCI_PORT_INTR_0_EN_INFS_NONDATA_FIS_CRC_ERROR_RANGE 29:29
#define AHCI_PORT_INTR_0_EN_INFS_NONDATA_FIS_CRC_ERROR_WOFFSET 0
#define AHCI_PORT_INTR_0_EN_INFS_NONDATA_FIS_CRC_ERROR_CLEARED _MK_ENUM_CONST(0x00000000)                                                       // RW--V
#define AHCI_PORT_INTR_0_EN_INFS_NONDATA_FIS_CRC_ERROR_SET _MK_ENUM_CONST(0x00000001)                                                       // RWC-V
#define AHCI_PORT_INTR_0_EN_IFS_FPDMA_TAG_ERROR_SHIFT       _MK_SHIFT_CONST(30)                                                             // RWCVF
#define AHCI_PORT_INTR_0_EN_IFS_FPDMA_TAG_ERROR_FIELD      (_MK_SHIFT_CONST(0x1) << AHCI_PORT_INTR_0_EN_IFS_FPDMA_TAG_ERROR_SHIFT)
#define AHCI_PORT_INTR_0_EN_IFS_FPDMA_TAG_ERROR_RANGE      30:30
#define AHCI_PORT_INTR_0_EN_IFS_FPDMA_TAG_ERROR_WOFFSET    0
#define AHCI_PORT_INTR_0_EN_IFS_FPDMA_TAG_ERROR_CLEARED    _MK_ENUM_CONST(0x00000000)                                                       // RW--V
#define AHCI_PORT_INTR_0_EN_IFS_FPDMA_TAG_ERROR_SET        _MK_ENUM_CONST(0x00000001)                                                       // RWC-V
#define AHCI_PORT_INTR_0_EN_IFS_NCQ_NON_NCQ_MIX_SHIFT       _MK_SHIFT_CONST(31)                                                             // RWCVF
#define AHCI_PORT_INTR_0_EN_IFS_NCQ_NON_NCQ_MIX_FIELD      (_MK_SHIFT_CONST(0x1) << AHCI_PORT_INTR_0_EN_IFS_NCQ_NON_NCQ_MIX_SHIFT)
#define AHCI_PORT_INTR_0_EN_IFS_NCQ_NON_NCQ_MIX_RANGE      31:31
#define AHCI_PORT_INTR_0_EN_IFS_NCQ_NON_NCQ_MIX_WOFFSET    0
#define AHCI_PORT_INTR_0_EN_IFS_NCQ_NON_NCQ_MIX_CLEARED    _MK_ENUM_CONST(0x00000000)                                                       // RW--V
#define AHCI_PORT_INTR_0_EN_IFS_NCQ_NON_NCQ_MIX_SET        _MK_ENUM_CONST(0x00000001)                                                       // RWC-V
// 
// 
// 
// 
// 
// .TITLE FBS_RX_PMP_REG_FIS
// .LABEL PRIVATE INT_REL
// This register implements per pmp status of register fis reception
// 
//  31           24 23           16 15            8 7             0
// .-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-.
// |0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0| PORT_FBS_RX_PMP_REG_FIS
// +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
#define AHCI_PORT_FBS_RX_PMP_REG_FIS_0                     0x00000178                                                                       // RWI4R
#define AHCI_PORT_FBS_RX_PMP_REG_FIS_0_SECURE              0
#define AHCI_PORT_FBS_RX_PMP_REG_FIS_0_WORD_COUNT          1
#define AHCI_PORT_FBS_RX_PMP_REG_FIS_0_RESET_VAL           0x0
#define AHCI_PORT_FBS_RX_PMP_REG_FIS_0_RESET_MASK          0xffff
#define AHCI_PORT_FBS_RX_PMP_REG_FIS_0_SW_DEFAULT_VAL      0x0
#define AHCI_PORT_FBS_RX_PMP_REG_FIS_0_SW_DEFAULT_MASK     0xffff
#define AHCI_PORT_FBS_RX_PMP_REG_FIS_0_READ_MASK           0xffffffff
#define AHCI_PORT_FBS_RX_PMP_REG_FIS_0_WRITE_MASK          0xffffffff
#define AHCI_PORT_FBS_RX_PMP_REG_FIS_0_PMP0_SHIFT           _MK_SHIFT_CONST(0)                                                              // RWIVF
#define AHCI_PORT_FBS_RX_PMP_REG_FIS_0_PMP0_FIELD          (_MK_SHIFT_CONST(0x1) << AHCI_PORT_FBS_RX_PMP_REG_FIS_0_PMP0_SHIFT)
#define AHCI_PORT_FBS_RX_PMP_REG_FIS_0_PMP0_RANGE          0:0
#define AHCI_PORT_FBS_RX_PMP_REG_FIS_0_PMP0_WOFFSET        0
#define AHCI_PORT_FBS_RX_PMP_REG_FIS_0_PMP0_DEFAULT        (_MK_MASK_CONST(0x00000000)
#define AHCI_PORT_FBS_RX_PMP_REG_FIS_0_PMP0_DEFAULT_MASK   (_MK_MASK_CONST(0x1)
#define AHCI_PORT_FBS_RX_PMP_REG_FIS_0_PMP0_SW_DEFAULT     (_MK_MASK_CONST(0x00000000)
#define AHCI_PORT_FBS_RX_PMP_REG_FIS_0_PMP0_SW_DEFAULT_MASK (_MK_MASK_CONST(0x1)
#define AHCI_PORT_FBS_RX_PMP_REG_FIS_0_PMP0_INIT           _MK_ENUM_CONST(0x00000000)                                                       // R-I-V
#define AHCI_PORT_FBS_RX_PMP_REG_FIS_0_PMP0_CLR            _MK_ENUM_CONST(0x00000001)                                                       // -W--C
#define AHCI_PORT_FBS_RX_PMP_REG_FIS_0_PMP1_SHIFT           _MK_SHIFT_CONST(1)                                                              // RWIVF
#define AHCI_PORT_FBS_RX_PMP_REG_FIS_0_PMP1_FIELD          (_MK_SHIFT_CONST(0x1) << AHCI_PORT_FBS_RX_PMP_REG_FIS_0_PMP1_SHIFT)
#define AHCI_PORT_FBS_RX_PMP_REG_FIS_0_PMP1_RANGE          1:1
#define AHCI_PORT_FBS_RX_PMP_REG_FIS_0_PMP1_WOFFSET        0
#define AHCI_PORT_FBS_RX_PMP_REG_FIS_0_PMP1_DEFAULT        (_MK_MASK_CONST(0x00000000)
#define AHCI_PORT_FBS_RX_PMP_REG_FIS_0_PMP1_DEFAULT_MASK   (_MK_MASK_CONST(0x1)
#define AHCI_PORT_FBS_RX_PMP_REG_FIS_0_PMP1_SW_DEFAULT     (_MK_MASK_CONST(0x00000000)
#define AHCI_PORT_FBS_RX_PMP_REG_FIS_0_PMP1_SW_DEFAULT_MASK (_MK_MASK_CONST(0x1)
#define AHCI_PORT_FBS_RX_PMP_REG_FIS_0_PMP1_INIT           _MK_ENUM_CONST(0x00000000)                                                       // R-I-V
#define AHCI_PORT_FBS_RX_PMP_REG_FIS_0_PMP1_CLR            _MK_ENUM_CONST(0x00000001)                                                       // -W--C
#define AHCI_PORT_FBS_RX_PMP_REG_FIS_0_PMP2_SHIFT           _MK_SHIFT_CONST(2)                                                              // RWIVF
#define AHCI_PORT_FBS_RX_PMP_REG_FIS_0_PMP2_FIELD          (_MK_SHIFT_CONST(0x1) << AHCI_PORT_FBS_RX_PMP_REG_FIS_0_PMP2_SHIFT)
#define AHCI_PORT_FBS_RX_PMP_REG_FIS_0_PMP2_RANGE          2:2
#define AHCI_PORT_FBS_RX_PMP_REG_FIS_0_PMP2_WOFFSET        0
#define AHCI_PORT_FBS_RX_PMP_REG_FIS_0_PMP2_DEFAULT        (_MK_MASK_CONST(0x00000000)
#define AHCI_PORT_FBS_RX_PMP_REG_FIS_0_PMP2_DEFAULT_MASK   (_MK_MASK_CONST(0x1)
#define AHCI_PORT_FBS_RX_PMP_REG_FIS_0_PMP2_SW_DEFAULT     (_MK_MASK_CONST(0x00000000)
#define AHCI_PORT_FBS_RX_PMP_REG_FIS_0_PMP2_SW_DEFAULT_MASK (_MK_MASK_CONST(0x1)
#define AHCI_PORT_FBS_RX_PMP_REG_FIS_0_PMP2_INIT           _MK_ENUM_CONST(0x00000000)                                                       // R-I-V
#define AHCI_PORT_FBS_RX_PMP_REG_FIS_0_PMP2_CLR            _MK_ENUM_CONST(0x00000001)                                                       // -W--C
#define AHCI_PORT_FBS_RX_PMP_REG_FIS_0_PMP3_SHIFT           _MK_SHIFT_CONST(3)                                                              // RWIVF
#define AHCI_PORT_FBS_RX_PMP_REG_FIS_0_PMP3_FIELD          (_MK_SHIFT_CONST(0x1) << AHCI_PORT_FBS_RX_PMP_REG_FIS_0_PMP3_SHIFT)
#define AHCI_PORT_FBS_RX_PMP_REG_FIS_0_PMP3_RANGE          3:3
#define AHCI_PORT_FBS_RX_PMP_REG_FIS_0_PMP3_WOFFSET        0
#define AHCI_PORT_FBS_RX_PMP_REG_FIS_0_PMP3_DEFAULT        (_MK_MASK_CONST(0x00000000)
#define AHCI_PORT_FBS_RX_PMP_REG_FIS_0_PMP3_DEFAULT_MASK   (_MK_MASK_CONST(0x1)
#define AHCI_PORT_FBS_RX_PMP_REG_FIS_0_PMP3_SW_DEFAULT     (_MK_MASK_CONST(0x00000000)
#define AHCI_PORT_FBS_RX_PMP_REG_FIS_0_PMP3_SW_DEFAULT_MASK (_MK_MASK_CONST(0x1)
#define AHCI_PORT_FBS_RX_PMP_REG_FIS_0_PMP3_INIT           _MK_ENUM_CONST(0x00000000)                                                       // R-I-V
#define AHCI_PORT_FBS_RX_PMP_REG_FIS_0_PMP3_CLR            _MK_ENUM_CONST(0x00000001)                                                       // -W--C
#define AHCI_PORT_FBS_RX_PMP_REG_FIS_0_PMP4_SHIFT           _MK_SHIFT_CONST(4)                                                              // RWIVF
#define AHCI_PORT_FBS_RX_PMP_REG_FIS_0_PMP4_FIELD          (_MK_SHIFT_CONST(0x1) << AHCI_PORT_FBS_RX_PMP_REG_FIS_0_PMP4_SHIFT)
#define AHCI_PORT_FBS_RX_PMP_REG_FIS_0_PMP4_RANGE          4:4
#define AHCI_PORT_FBS_RX_PMP_REG_FIS_0_PMP4_WOFFSET        0
#define AHCI_PORT_FBS_RX_PMP_REG_FIS_0_PMP4_DEFAULT        (_MK_MASK_CONST(0x00000000)
#define AHCI_PORT_FBS_RX_PMP_REG_FIS_0_PMP4_DEFAULT_MASK   (_MK_MASK_CONST(0x1)
#define AHCI_PORT_FBS_RX_PMP_REG_FIS_0_PMP4_SW_DEFAULT     (_MK_MASK_CONST(0x00000000)
#define AHCI_PORT_FBS_RX_PMP_REG_FIS_0_PMP4_SW_DEFAULT_MASK (_MK_MASK_CONST(0x1)
#define AHCI_PORT_FBS_RX_PMP_REG_FIS_0_PMP4_INIT           _MK_ENUM_CONST(0x00000000)                                                       // R-I-V
#define AHCI_PORT_FBS_RX_PMP_REG_FIS_0_PMP4_CLR            _MK_ENUM_CONST(0x00000001)                                                       // -W--C
#define AHCI_PORT_FBS_RX_PMP_REG_FIS_0_PMP5_SHIFT           _MK_SHIFT_CONST(5)                                                              // RWIVF
#define AHCI_PORT_FBS_RX_PMP_REG_FIS_0_PMP5_FIELD          (_MK_SHIFT_CONST(0x1) << AHCI_PORT_FBS_RX_PMP_REG_FIS_0_PMP5_SHIFT)
#define AHCI_PORT_FBS_RX_PMP_REG_FIS_0_PMP5_RANGE          5:5
#define AHCI_PORT_FBS_RX_PMP_REG_FIS_0_PMP5_WOFFSET        0
#define AHCI_PORT_FBS_RX_PMP_REG_FIS_0_PMP5_DEFAULT        (_MK_MASK_CONST(0x00000000)
#define AHCI_PORT_FBS_RX_PMP_REG_FIS_0_PMP5_DEFAULT_MASK   (_MK_MASK_CONST(0x1)
#define AHCI_PORT_FBS_RX_PMP_REG_FIS_0_PMP5_SW_DEFAULT     (_MK_MASK_CONST(0x00000000)
#define AHCI_PORT_FBS_RX_PMP_REG_FIS_0_PMP5_SW_DEFAULT_MASK (_MK_MASK_CONST(0x1)
#define AHCI_PORT_FBS_RX_PMP_REG_FIS_0_PMP5_INIT           _MK_ENUM_CONST(0x00000000)                                                       // R-I-V
#define AHCI_PORT_FBS_RX_PMP_REG_FIS_0_PMP5_CLR            _MK_ENUM_CONST(0x00000001)                                                       // -W--C
#define AHCI_PORT_FBS_RX_PMP_REG_FIS_0_PMP6_SHIFT           _MK_SHIFT_CONST(6)                                                              // RWIVF
#define AHCI_PORT_FBS_RX_PMP_REG_FIS_0_PMP6_FIELD          (_MK_SHIFT_CONST(0x1) << AHCI_PORT_FBS_RX_PMP_REG_FIS_0_PMP6_SHIFT)
#define AHCI_PORT_FBS_RX_PMP_REG_FIS_0_PMP6_RANGE          6:6
#define AHCI_PORT_FBS_RX_PMP_REG_FIS_0_PMP6_WOFFSET        0
#define AHCI_PORT_FBS_RX_PMP_REG_FIS_0_PMP6_DEFAULT        (_MK_MASK_CONST(0x00000000)
#define AHCI_PORT_FBS_RX_PMP_REG_FIS_0_PMP6_DEFAULT_MASK   (_MK_MASK_CONST(0x1)
#define AHCI_PORT_FBS_RX_PMP_REG_FIS_0_PMP6_SW_DEFAULT     (_MK_MASK_CONST(0x00000000)
#define AHCI_PORT_FBS_RX_PMP_REG_FIS_0_PMP6_SW_DEFAULT_MASK (_MK_MASK_CONST(0x1)
#define AHCI_PORT_FBS_RX_PMP_REG_FIS_0_PMP6_INIT           _MK_ENUM_CONST(0x00000000)                                                       // R-I-V
#define AHCI_PORT_FBS_RX_PMP_REG_FIS_0_PMP6_CLR            _MK_ENUM_CONST(0x00000001)                                                       // -W--C
#define AHCI_PORT_FBS_RX_PMP_REG_FIS_0_PMP7_SHIFT           _MK_SHIFT_CONST(7)                                                              // RWIVF
#define AHCI_PORT_FBS_RX_PMP_REG_FIS_0_PMP7_FIELD          (_MK_SHIFT_CONST(0x1) << AHCI_PORT_FBS_RX_PMP_REG_FIS_0_PMP7_SHIFT)
#define AHCI_PORT_FBS_RX_PMP_REG_FIS_0_PMP7_RANGE          7:7
#define AHCI_PORT_FBS_RX_PMP_REG_FIS_0_PMP7_WOFFSET        0
#define AHCI_PORT_FBS_RX_PMP_REG_FIS_0_PMP7_DEFAULT        (_MK_MASK_CONST(0x00000000)
#define AHCI_PORT_FBS_RX_PMP_REG_FIS_0_PMP7_DEFAULT_MASK   (_MK_MASK_CONST(0x1)
#define AHCI_PORT_FBS_RX_PMP_REG_FIS_0_PMP7_SW_DEFAULT     (_MK_MASK_CONST(0x00000000)
#define AHCI_PORT_FBS_RX_PMP_REG_FIS_0_PMP7_SW_DEFAULT_MASK (_MK_MASK_CONST(0x1)
#define AHCI_PORT_FBS_RX_PMP_REG_FIS_0_PMP7_INIT           _MK_ENUM_CONST(0x00000000)                                                       // R-I-V
#define AHCI_PORT_FBS_RX_PMP_REG_FIS_0_PMP7_CLR            _MK_ENUM_CONST(0x00000001)                                                       // -W--C
#define AHCI_PORT_FBS_RX_PMP_REG_FIS_0_PMP8_SHIFT           _MK_SHIFT_CONST(8)                                                              // RWIVF
#define AHCI_PORT_FBS_RX_PMP_REG_FIS_0_PMP8_FIELD          (_MK_SHIFT_CONST(0x1) << AHCI_PORT_FBS_RX_PMP_REG_FIS_0_PMP8_SHIFT)
#define AHCI_PORT_FBS_RX_PMP_REG_FIS_0_PMP8_RANGE          8:8
#define AHCI_PORT_FBS_RX_PMP_REG_FIS_0_PMP8_WOFFSET        0
#define AHCI_PORT_FBS_RX_PMP_REG_FIS_0_PMP8_DEFAULT        (_MK_MASK_CONST(0x00000000)
#define AHCI_PORT_FBS_RX_PMP_REG_FIS_0_PMP8_DEFAULT_MASK   (_MK_MASK_CONST(0x1)
#define AHCI_PORT_FBS_RX_PMP_REG_FIS_0_PMP8_SW_DEFAULT     (_MK_MASK_CONST(0x00000000)
#define AHCI_PORT_FBS_RX_PMP_REG_FIS_0_PMP8_SW_DEFAULT_MASK (_MK_MASK_CONST(0x1)
#define AHCI_PORT_FBS_RX_PMP_REG_FIS_0_PMP8_INIT           _MK_ENUM_CONST(0x00000000)                                                       // R-I-V
#define AHCI_PORT_FBS_RX_PMP_REG_FIS_0_PMP8_CLR            _MK_ENUM_CONST(0x00000001)                                                       // -W--C
#define AHCI_PORT_FBS_RX_PMP_REG_FIS_0_PMP9_SHIFT           _MK_SHIFT_CONST(9)                                                              // RWIVF
#define AHCI_PORT_FBS_RX_PMP_REG_FIS_0_PMP9_FIELD          (_MK_SHIFT_CONST(0x1) << AHCI_PORT_FBS_RX_PMP_REG_FIS_0_PMP9_SHIFT)
#define AHCI_PORT_FBS_RX_PMP_REG_FIS_0_PMP9_RANGE          9:9
#define AHCI_PORT_FBS_RX_PMP_REG_FIS_0_PMP9_WOFFSET        0
#define AHCI_PORT_FBS_RX_PMP_REG_FIS_0_PMP9_DEFAULT        (_MK_MASK_CONST(0x00000000)
#define AHCI_PORT_FBS_RX_PMP_REG_FIS_0_PMP9_DEFAULT_MASK   (_MK_MASK_CONST(0x1)
#define AHCI_PORT_FBS_RX_PMP_REG_FIS_0_PMP9_SW_DEFAULT     (_MK_MASK_CONST(0x00000000)
#define AHCI_PORT_FBS_RX_PMP_REG_FIS_0_PMP9_SW_DEFAULT_MASK (_MK_MASK_CONST(0x1)
#define AHCI_PORT_FBS_RX_PMP_REG_FIS_0_PMP9_INIT           _MK_ENUM_CONST(0x00000000)                                                       // R-I-V
#define AHCI_PORT_FBS_RX_PMP_REG_FIS_0_PMP9_CLR            _MK_ENUM_CONST(0x00000001)                                                       // -W--C
#define AHCI_PORT_FBS_RX_PMP_REG_FIS_0_PMP10_SHIFT          _MK_SHIFT_CONST(10)                                                             // RWIVF
#define AHCI_PORT_FBS_RX_PMP_REG_FIS_0_PMP10_FIELD         (_MK_SHIFT_CONST(0x1) << AHCI_PORT_FBS_RX_PMP_REG_FIS_0_PMP10_SHIFT)
#define AHCI_PORT_FBS_RX_PMP_REG_FIS_0_PMP10_RANGE         10:10
#define AHCI_PORT_FBS_RX_PMP_REG_FIS_0_PMP10_WOFFSET       0
#define AHCI_PORT_FBS_RX_PMP_REG_FIS_0_PMP10_DEFAULT       (_MK_MASK_CONST(0x00000000)
#define AHCI_PORT_FBS_RX_PMP_REG_FIS_0_PMP10_DEFAULT_MASK  (_MK_MASK_CONST(0x1)
#define AHCI_PORT_FBS_RX_PMP_REG_FIS_0_PMP10_SW_DEFAULT    (_MK_MASK_CONST(0x00000000)
#define AHCI_PORT_FBS_RX_PMP_REG_FIS_0_PMP10_SW_DEFAULT_MASK (_MK_MASK_CONST(0x1)
#define AHCI_PORT_FBS_RX_PMP_REG_FIS_0_PMP10_INIT          _MK_ENUM_CONST(0x00000000)                                                       // R-I-V
#define AHCI_PORT_FBS_RX_PMP_REG_FIS_0_PMP10_CLR           _MK_ENUM_CONST(0x00000001)                                                       // -W--C
#define AHCI_PORT_FBS_RX_PMP_REG_FIS_0_PMP11_SHIFT          _MK_SHIFT_CONST(11)                                                             // RWIVF
#define AHCI_PORT_FBS_RX_PMP_REG_FIS_0_PMP11_FIELD         (_MK_SHIFT_CONST(0x1) << AHCI_PORT_FBS_RX_PMP_REG_FIS_0_PMP11_SHIFT)
#define AHCI_PORT_FBS_RX_PMP_REG_FIS_0_PMP11_RANGE         11:11
#define AHCI_PORT_FBS_RX_PMP_REG_FIS_0_PMP11_WOFFSET       0
#define AHCI_PORT_FBS_RX_PMP_REG_FIS_0_PMP11_DEFAULT       (_MK_MASK_CONST(0x00000000)
#define AHCI_PORT_FBS_RX_PMP_REG_FIS_0_PMP11_DEFAULT_MASK  (_MK_MASK_CONST(0x1)
#define AHCI_PORT_FBS_RX_PMP_REG_FIS_0_PMP11_SW_DEFAULT    (_MK_MASK_CONST(0x00000000)
#define AHCI_PORT_FBS_RX_PMP_REG_FIS_0_PMP11_SW_DEFAULT_MASK (_MK_MASK_CONST(0x1)
#define AHCI_PORT_FBS_RX_PMP_REG_FIS_0_PMP11_INIT          _MK_ENUM_CONST(0x00000000)                                                       // R-I-V
#define AHCI_PORT_FBS_RX_PMP_REG_FIS_0_PMP11_CLR           _MK_ENUM_CONST(0x00000001)                                                       // -W--C
#define AHCI_PORT_FBS_RX_PMP_REG_FIS_0_PMP12_SHIFT          _MK_SHIFT_CONST(12)                                                             // RWIVF
#define AHCI_PORT_FBS_RX_PMP_REG_FIS_0_PMP12_FIELD         (_MK_SHIFT_CONST(0x1) << AHCI_PORT_FBS_RX_PMP_REG_FIS_0_PMP12_SHIFT)
#define AHCI_PORT_FBS_RX_PMP_REG_FIS_0_PMP12_RANGE         12:12
#define AHCI_PORT_FBS_RX_PMP_REG_FIS_0_PMP12_WOFFSET       0
#define AHCI_PORT_FBS_RX_PMP_REG_FIS_0_PMP12_DEFAULT       (_MK_MASK_CONST(0x00000000)
#define AHCI_PORT_FBS_RX_PMP_REG_FIS_0_PMP12_DEFAULT_MASK  (_MK_MASK_CONST(0x1)
#define AHCI_PORT_FBS_RX_PMP_REG_FIS_0_PMP12_SW_DEFAULT    (_MK_MASK_CONST(0x00000000)
#define AHCI_PORT_FBS_RX_PMP_REG_FIS_0_PMP12_SW_DEFAULT_MASK (_MK_MASK_CONST(0x1)
#define AHCI_PORT_FBS_RX_PMP_REG_FIS_0_PMP12_INIT          _MK_ENUM_CONST(0x00000000)                                                       // R-I-V
#define AHCI_PORT_FBS_RX_PMP_REG_FIS_0_PMP12_CLR           _MK_ENUM_CONST(0x00000001)                                                       // -W--C
#define AHCI_PORT_FBS_RX_PMP_REG_FIS_0_PMP13_SHIFT          _MK_SHIFT_CONST(13)                                                             // RWIVF
#define AHCI_PORT_FBS_RX_PMP_REG_FIS_0_PMP13_FIELD         (_MK_SHIFT_CONST(0x1) << AHCI_PORT_FBS_RX_PMP_REG_FIS_0_PMP13_SHIFT)
#define AHCI_PORT_FBS_RX_PMP_REG_FIS_0_PMP13_RANGE         13:13
#define AHCI_PORT_FBS_RX_PMP_REG_FIS_0_PMP13_WOFFSET       0
#define AHCI_PORT_FBS_RX_PMP_REG_FIS_0_PMP13_DEFAULT       (_MK_MASK_CONST(0x00000000)
#define AHCI_PORT_FBS_RX_PMP_REG_FIS_0_PMP13_DEFAULT_MASK  (_MK_MASK_CONST(0x1)
#define AHCI_PORT_FBS_RX_PMP_REG_FIS_0_PMP13_SW_DEFAULT    (_MK_MASK_CONST(0x00000000)
#define AHCI_PORT_FBS_RX_PMP_REG_FIS_0_PMP13_SW_DEFAULT_MASK (_MK_MASK_CONST(0x1)
#define AHCI_PORT_FBS_RX_PMP_REG_FIS_0_PMP13_INIT          _MK_ENUM_CONST(0x00000000)                                                       // R-I-V
#define AHCI_PORT_FBS_RX_PMP_REG_FIS_0_PMP13_CLR           _MK_ENUM_CONST(0x00000001)                                                       // -W--C
#define AHCI_PORT_FBS_RX_PMP_REG_FIS_0_PMP14_SHIFT          _MK_SHIFT_CONST(14)                                                             // RWIVF
#define AHCI_PORT_FBS_RX_PMP_REG_FIS_0_PMP14_FIELD         (_MK_SHIFT_CONST(0x1) << AHCI_PORT_FBS_RX_PMP_REG_FIS_0_PMP14_SHIFT)
#define AHCI_PORT_FBS_RX_PMP_REG_FIS_0_PMP14_RANGE         14:14
#define AHCI_PORT_FBS_RX_PMP_REG_FIS_0_PMP14_WOFFSET       0
#define AHCI_PORT_FBS_RX_PMP_REG_FIS_0_PMP14_DEFAULT       (_MK_MASK_CONST(0x00000000)
#define AHCI_PORT_FBS_RX_PMP_REG_FIS_0_PMP14_DEFAULT_MASK  (_MK_MASK_CONST(0x1)
#define AHCI_PORT_FBS_RX_PMP_REG_FIS_0_PMP14_SW_DEFAULT    (_MK_MASK_CONST(0x00000000)
#define AHCI_PORT_FBS_RX_PMP_REG_FIS_0_PMP14_SW_DEFAULT_MASK (_MK_MASK_CONST(0x1)
#define AHCI_PORT_FBS_RX_PMP_REG_FIS_0_PMP14_INIT          _MK_ENUM_CONST(0x00000000)                                                       // R-I-V
#define AHCI_PORT_FBS_RX_PMP_REG_FIS_0_PMP14_CLR           _MK_ENUM_CONST(0x00000001)                                                       // -W--C
#define AHCI_PORT_FBS_RX_PMP_REG_FIS_0_PMP15_SHIFT          _MK_SHIFT_CONST(15)                                                             // RWIVF
#define AHCI_PORT_FBS_RX_PMP_REG_FIS_0_PMP15_FIELD         (_MK_SHIFT_CONST(0x1) << AHCI_PORT_FBS_RX_PMP_REG_FIS_0_PMP15_SHIFT)
#define AHCI_PORT_FBS_RX_PMP_REG_FIS_0_PMP15_RANGE         15:15
#define AHCI_PORT_FBS_RX_PMP_REG_FIS_0_PMP15_WOFFSET       0
#define AHCI_PORT_FBS_RX_PMP_REG_FIS_0_PMP15_DEFAULT       (_MK_MASK_CONST(0x00000000)
#define AHCI_PORT_FBS_RX_PMP_REG_FIS_0_PMP15_DEFAULT_MASK  (_MK_MASK_CONST(0x1)
#define AHCI_PORT_FBS_RX_PMP_REG_FIS_0_PMP15_SW_DEFAULT    (_MK_MASK_CONST(0x00000000)
#define AHCI_PORT_FBS_RX_PMP_REG_FIS_0_PMP15_SW_DEFAULT_MASK (_MK_MASK_CONST(0x1)
#define AHCI_PORT_FBS_RX_PMP_REG_FIS_0_PMP15_INIT          _MK_ENUM_CONST(0x00000000)                                                       // R-I-V
#define AHCI_PORT_FBS_RX_PMP_REG_FIS_0_PMP15_CLR           _MK_ENUM_CONST(0x00000001)                                                       // -W--C
#define AHCI_PORT_FBS_RX_PMP_REG_FIS_0_SPARE_31_16_SHIFT    _MK_SHIFT_CONST(16)                                                             // RWCVF
#define AHCI_PORT_FBS_RX_PMP_REG_FIS_0_SPARE_31_16_FIELD   (_MK_SHIFT_CONST(0xffff) << AHCI_PORT_FBS_RX_PMP_REG_FIS_0_SPARE_31_16_SHIFT)
#define AHCI_PORT_FBS_RX_PMP_REG_FIS_0_SPARE_31_16_RANGE   31:16
#define AHCI_PORT_FBS_RX_PMP_REG_FIS_0_SPARE_31_16_WOFFSET 0
#define AHCI_PORT_FBS_RX_PMP_REG_FIS_0_SPARE_31_16_INIT    _MK_ENUM_CONST(0x0000F0F0)                                                       // RW--V
// 
// 
// 
// .LABEL PRIVATE INT_REL
// .TITLE Motion Protection
// .LABEL PRIVATE
// Motion protection is a feature that prevents damage to Hard Disk by issuing IDLE IMMEDIATE command to the disk.
// .LABEL PRIVATE INT_REL
// 31           24 23           16 15            8 7             0
// .-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-.
// |0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0| PORT_MP
// `-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-'
#define AHCI_PORT_MP_0                                     0x0000017C                                                                       // RWC4R
#define AHCI_PORT_MP_0_SECURE                              0
#define AHCI_PORT_MP_0_WORD_COUNT                          1
#define AHCI_PORT_MP_0_RESET_VAL                           0x0
#define AHCI_PORT_MP_0_RESET_MASK                          0x0
#define AHCI_PORT_MP_0_SW_DEFAULT_VAL                      0x0
#define AHCI_PORT_MP_0_SW_DEFAULT_MASK                     0x0
#define AHCI_PORT_MP_0_READ_MASK                           0xffffffff
#define AHCI_PORT_MP_0_WRITE_MASK                          0xffffffef
#define AHCI_PORT_MP_0_MPE_SHIFT                            _MK_SHIFT_CONST(0)                                                              // RWCVF
#define AHCI_PORT_MP_0_MPE_FIELD                           (_MK_SHIFT_CONST(0x1) << AHCI_PORT_MP_0_MPE_SHIFT)
#define AHCI_PORT_MP_0_MPE_RANGE                           0:0
#define AHCI_PORT_MP_0_MPE_WOFFSET                         0
#define AHCI_PORT_MP_0_MPE_SET                             _MK_ENUM_CONST(0x00000001)                                                       // RW--V
#define AHCI_PORT_MP_0_MPE_CLEAR                           _MK_ENUM_CONST(0x00000000)                                                       // RW--V
#define AHCI_PORT_MP_0_MPGBE_SHIFT                          _MK_SHIFT_CONST(1)                                                              // RWCVF
#define AHCI_PORT_MP_0_MPGBE_FIELD                         (_MK_SHIFT_CONST(0x1) << AHCI_PORT_MP_0_MPGBE_SHIFT)
#define AHCI_PORT_MP_0_MPGBE_RANGE                         1:1
#define AHCI_PORT_MP_0_MPGBE_WOFFSET                       0
#define AHCI_PORT_MP_0_MPGBE_SET                           _MK_ENUM_CONST(0x00000001)                                                       // RW--V
#define AHCI_PORT_MP_0_MPGBE_CLEAR                         _MK_ENUM_CONST(0x00000000)                                                       // RW--V
#define AHCI_PORT_MP_0_MPSIE_SHIFT                          _MK_SHIFT_CONST(2)                                                              // RWCVF
#define AHCI_PORT_MP_0_MPSIE_FIELD                         (_MK_SHIFT_CONST(0x1) << AHCI_PORT_MP_0_MPSIE_SHIFT)
#define AHCI_PORT_MP_0_MPSIE_RANGE                         2:2
#define AHCI_PORT_MP_0_MPSIE_WOFFSET                       0
#define AHCI_PORT_MP_0_MPSIE_SET                           _MK_ENUM_CONST(0x00000001)                                                       // RW--V
#define AHCI_PORT_MP_0_MPSIE_CLEAR                         _MK_ENUM_CONST(0x00000000)                                                       // RW--V
#define AHCI_PORT_MP_0_MPRSVD_0_SHIFT                       _MK_SHIFT_CONST(3)                                                              // RWCVF
#define AHCI_PORT_MP_0_MPRSVD_0_FIELD                      (_MK_SHIFT_CONST(0x1) << AHCI_PORT_MP_0_MPRSVD_0_SHIFT)
#define AHCI_PORT_MP_0_MPRSVD_0_RANGE                      3:3
#define AHCI_PORT_MP_0_MPRSVD_0_WOFFSET                    0
#define AHCI_PORT_MP_0_MPRSVD_0_0                          _MK_ENUM_CONST(0x00000000)                                                       // RWC-V
#define AHCI_PORT_MP_0_MPES_SHIFT                           _MK_SHIFT_CONST(4)                                                              // R-CVF
#define AHCI_PORT_MP_0_MPES_FIELD                          (_MK_SHIFT_CONST(0x1) << AHCI_PORT_MP_0_MPES_SHIFT)
#define AHCI_PORT_MP_0_MPES_RANGE                          4:4
#define AHCI_PORT_MP_0_MPES_WOFFSET                        0
#define AHCI_PORT_MP_0_MPES_SET                            _MK_ENUM_CONST(0x00000001)                                                       // R---V
#define AHCI_PORT_MP_0_MPES_CLEAR                          _MK_ENUM_CONST(0x00000000)                                                       // R---V
#define AHCI_PORT_MP_0_MPIS_SHIFT                           _MK_SHIFT_CONST(5)                                                              // RWCVF
#define AHCI_PORT_MP_0_MPIS_FIELD                          (_MK_SHIFT_CONST(0x1) << AHCI_PORT_MP_0_MPIS_SHIFT)
#define AHCI_PORT_MP_0_MPIS_RANGE                          5:5
#define AHCI_PORT_MP_0_MPIS_WOFFSET                        0
#define AHCI_PORT_MP_0_MPIS_ZERO                           _MK_ENUM_CONST(0x00000000)                                                       // R-C-V
#define AHCI_PORT_MP_0_MPIS_SET                            _MK_ENUM_CONST(0x00000001)                                                       // R---V
#define AHCI_PORT_MP_0_MPIS_CLEAR                          _MK_ENUM_CONST(0x00000001)                                                       // -W--C
#define AHCI_PORT_MP_0_MPRSVD_1_SHIFT                       _MK_SHIFT_CONST(6)                                                              // RWCVF
#define AHCI_PORT_MP_0_MPRSVD_1_FIELD                      (_MK_SHIFT_CONST(0x1) << AHCI_PORT_MP_0_MPRSVD_1_SHIFT)
#define AHCI_PORT_MP_0_MPRSVD_1_RANGE                      6:6
#define AHCI_PORT_MP_0_MPRSVD_1_WOFFSET                    0
#define AHCI_PORT_MP_0_MPRSVD_1_0                          _MK_ENUM_CONST(0x00000000)                                                       // RWC-V
#define AHCI_PORT_MP_0_MPA_SHIFT                            _MK_SHIFT_CONST(7)                                                              // RWCVF
#define AHCI_PORT_MP_0_MPA_FIELD                           (_MK_SHIFT_CONST(0x1) << AHCI_PORT_MP_0_MPA_SHIFT)
#define AHCI_PORT_MP_0_MPA_RANGE                           7:7
#define AHCI_PORT_MP_0_MPA_WOFFSET                         0
#define AHCI_PORT_MP_0_MPA_SET                             _MK_ENUM_CONST(0x00000001)                                                       // RW--V
#define AHCI_PORT_MP_0_MPA_CLEAR                           _MK_ENUM_CONST(0x00000000)                                                       // RW--V
#define AHCI_PORT_MP_0_UNLOAD_WITH_COMRESET_SHIFT           _MK_SHIFT_CONST(8)                                                              // RWCVF
#define AHCI_PORT_MP_0_UNLOAD_WITH_COMRESET_FIELD          (_MK_SHIFT_CONST(0x1) << AHCI_PORT_MP_0_UNLOAD_WITH_COMRESET_SHIFT)
#define AHCI_PORT_MP_0_UNLOAD_WITH_COMRESET_RANGE          8:8
#define AHCI_PORT_MP_0_UNLOAD_WITH_COMRESET_WOFFSET        0
#define AHCI_PORT_MP_0_UNLOAD_WITH_COMRESET_SET            _MK_ENUM_CONST(0x00000001)                                                       // RW--V
#define AHCI_PORT_MP_0_UNLOAD_WITH_COMRESET_RESET          _MK_ENUM_CONST(0x00000000)                                                       // RW--V
#define AHCI_PORT_MP_0_COMRESET_ON_TIMEOUT_SHIFT            _MK_SHIFT_CONST(9)                                                              // RWCVF
#define AHCI_PORT_MP_0_COMRESET_ON_TIMEOUT_FIELD           (_MK_SHIFT_CONST(0x1) << AHCI_PORT_MP_0_COMRESET_ON_TIMEOUT_SHIFT)
#define AHCI_PORT_MP_0_COMRESET_ON_TIMEOUT_RANGE           9:9
#define AHCI_PORT_MP_0_COMRESET_ON_TIMEOUT_WOFFSET         0
#define AHCI_PORT_MP_0_COMRESET_ON_TIMEOUT_SET             _MK_ENUM_CONST(0x00000001)                                                       // RW--V
#define AHCI_PORT_MP_0_COMRESET_ON_TIMEOUT_RESET           _MK_ENUM_CONST(0x00000000)                                                       // RW--V
#define AHCI_PORT_MP_0_USE_EOF_DETECTION_SHIFT              _MK_SHIFT_CONST(10)                                                             // RWCVF
#define AHCI_PORT_MP_0_USE_EOF_DETECTION_FIELD             (_MK_SHIFT_CONST(0x1) << AHCI_PORT_MP_0_USE_EOF_DETECTION_SHIFT)
#define AHCI_PORT_MP_0_USE_EOF_DETECTION_RANGE             10:10
#define AHCI_PORT_MP_0_USE_EOF_DETECTION_WOFFSET           0
#define AHCI_PORT_MP_0_USE_EOF_DETECTION_SET               _MK_ENUM_CONST(0x00000001)                                                       // RW--V
#define AHCI_PORT_MP_0_USE_EOF_DETECTION_RESET             _MK_ENUM_CONST(0x00000000)                                                       // RW--V
#define AHCI_PORT_MP_0_MPRSVD_2_SHIFT                       _MK_SHIFT_CONST(11)                                                             // RWCVF
#define AHCI_PORT_MP_0_MPRSVD_2_FIELD                      (_MK_SHIFT_CONST(0x1fffff) << AHCI_PORT_MP_0_MPRSVD_2_SHIFT)
#define AHCI_PORT_MP_0_MPRSVD_2_RANGE                      31:11
#define AHCI_PORT_MP_0_MPRSVD_2_WOFFSET                    0
// 
// 
// 
// 
// .LABEL PRIVATE
// 
// APPENDIX E  -  KEY
// 
//         Read
//           ' ' = Other Information
//           '-' = Field is part of a write-only register
//           'C' = Value read is always the same, constant value line follows (C)
//           'R' = Value is read
// 
//         Write
//           ' ' = Other Information
//           '-' = Must not be written (D), value ignored when written (R,A,F)
//           'W' = Can be written
// 
//         Internal State
//           ' ' = Other Information
//           '-' = No internal state
//           'X' = Internal state, initial value is unknown
//           'I' = Internal state, initial value is known and follows (I)
// 
//         Declaration/Size
//           ' ' = Other Information
//           '-' = Does Not Apply
//           'V' = Type is void
//           'U' = Type is unsigned integer
//           'S' = Type is signed integer
//           'F' = Type is IEEE floating point
//           '1' = Byte size (008)
//           '2' = Short size (016)
//           '3' = Three byte size (024)
//           '4' = Word size (032)
//           '8' = Double size (064)
// 
//         Define Indicator
//           ' ' = Other Information
//           'D' = Device
//           'M' = Memory
//           'R' = Register
//           'A' = Array of Registers
//           'F' = Field
//           'V' = Value
// 
// 
// 
// 
// 
// 
// 
// 
// 
// 
// 

// REGISTER LIST

#define LIST_AHCI_REGS(_op_) \
  _op_(AHCI_HBA_CAP_0) \
  _op_(AHCI_HBA_GHC_0) \
  _op_(AHCI_HBA_IS_0) \
  _op_(AHCI_HBA_PI_0) \
  _op_(AHCI_HBA_VS_0) \
  _op_(AHCI_HBA_CCC_CTL_0) \
  _op_(AHCI_HBA_CCC_PORTS_0) \
  _op_(AHCI_HBA_EM_LOC_0) \
  _op_(AHCI_HBA_EM_CTL_0) \
  _op_(AHCI_HBA_CAP2_0) \
  _op_(AHCI_HBA_BOHC_0) \
  _op_(AHCI_HBA_CAP_BKDR_0) \
  _op_(AHCI_HBA_SPARE_0_0) \
  _op_(AHCI_HBA_PLL_CTRL_0) \
  _op_(AHCI_HBA_SHUTDOWN_TIMER_0) \
  _op_(AHCI_HBA_DEBUG_BUS_REG0_0) \
  _op_(AHCI_HBA_DEBUG_BUS_REG1_0) \
  _op_(AHCI_HBA_SPARE_3_0) \
  _op_(AHCI_PORT_PXCLB_0) \
  _op_(AHCI_PORT_PXCLBU_0) \
  _op_(AHCI_PORT_PXFB_0) \
  _op_(AHCI_PORT_PXFBU_0) \
  _op_(AHCI_PORT_PXIS_0) \
  _op_(AHCI_PORT_PXIE_0) \
  _op_(AHCI_PORT_PXCMD_0) \
  _op_(AHCI_PORT_PXTFD_0) \
  _op_(AHCI_PORT_PXSIG_0) \
  _op_(AHCI_PORT_PXSSTS_0) \
  _op_(AHCI_PORT_PXSCTL_0) \
  _op_(AHCI_PORT_PXSERR_0) \
  _op_(AHCI_PORT_PXSACT_0) \
  _op_(AHCI_PORT_PXCI_0) \
  _op_(AHCI_PORT_PXSNTF_0) \
  _op_(AHCI_PORT_PXFBS_0) \
  _op_(AHCI_PORT_PXDEVSLP_0) \
  _op_(AHCI_PORT_BKDR_0) \
  _op_(AHCI_PORT_INTR_0) \
  _op_(AHCI_PORT_FBS_RX_PMP_REG_FIS_0) \
  _op_(AHCI_PORT_MP_0) 


#ifndef _MK_SHIFT_CONST
  #define _MK_SHIFT_CONST(_constant_) _constant_
#endif
#ifndef _MK_MASK_CONST
  #define _MK_MASK_CONST(_constant_) _constant_
#endif
#ifndef _MK_ENUM_CONST
  #define _MK_ENUM_CONST(_constant_) (_constant_ ## UL)
#endif
#ifndef _MK_ADDR_CONST
  #define _MK_ADDR_CONST(_constant_) _constant_
#endif

#endif
