//
// Copyright (c) 2018 NVIDIA Corporation.
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are met:
//
// Redistributions of source code must retain the above copyright notice,
// this list of conditions and the following disclaimer.
//
// Redistributions in binary form must reproduce the above copyright notice,
// this list of conditions and the following disclaimer in the documentation
// and/or other materials provided with the distribution.
//
// Neither the name of the NVIDIA Corporation nor the names of its contributors
// may be used to endorse or promote products derived from this software
// without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
// POSSIBILITY OF SUCH DAMAGE.
//

//
// DO NOT EDIT - generated by simspec!
//

#ifndef ___ARPMC_IMPL_H_INC_
#define ___ARPMC_IMPL_H_INC_
#define NV_MOBILE_ARPMC_IMPL_H_UNIT_OF_OFFSET 1B


// Register PMC_IMPL_CNTRL_0
#define PMC_IMPL_CNTRL_0                        _MK_ADDR_CONST(0x0)
#define PMC_IMPL_CNTRL_0_SECURE                         0x0
#define PMC_IMPL_CNTRL_0_DUAL                   0x0
#define PMC_IMPL_CNTRL_0_SCR                    CNTRL_SCR_0
#define PMC_IMPL_CNTRL_0_WORD_COUNT                     0x1
#define PMC_IMPL_CNTRL_0_RESET_VAL                      _MK_MASK_CONST(0x400a00)
#define PMC_IMPL_CNTRL_0_RESET_MASK                     _MK_MASK_CONST(0x447f9f)
#define PMC_IMPL_CNTRL_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define PMC_IMPL_CNTRL_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_CNTRL_0_READ_MASK                      _MK_MASK_CONST(0x447f9f)
#define PMC_IMPL_CNTRL_0_WRITE_MASK                     _MK_MASK_CONST(0x447f9f)
#define PMC_IMPL_CNTRL_0_RESERVED_1_SHIFT                       _MK_SHIFT_CONST(0)
#define PMC_IMPL_CNTRL_0_RESERVED_1_FIELD                       _MK_FIELD_CONST(0x1, PMC_IMPL_CNTRL_0_RESERVED_1_SHIFT)
#define PMC_IMPL_CNTRL_0_RESERVED_1_RANGE                       0:0
#define PMC_IMPL_CNTRL_0_RESERVED_1_WOFFSET                     0x0
#define PMC_IMPL_CNTRL_0_RESERVED_1_DEFAULT                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_CNTRL_0_RESERVED_1_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define PMC_IMPL_CNTRL_0_RESERVED_1_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define PMC_IMPL_CNTRL_0_RESERVED_1_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_CNTRL_0_RESERVED_1_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_CNTRL_0_RESERVED_1_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define PMC_IMPL_CNTRL_0_RTC_CLK_DIS_SHIFT                      _MK_SHIFT_CONST(1)
#define PMC_IMPL_CNTRL_0_RTC_CLK_DIS_FIELD                      _MK_FIELD_CONST(0x1, PMC_IMPL_CNTRL_0_RTC_CLK_DIS_SHIFT)
#define PMC_IMPL_CNTRL_0_RTC_CLK_DIS_RANGE                      1:1
#define PMC_IMPL_CNTRL_0_RTC_CLK_DIS_WOFFSET                    0x0
#define PMC_IMPL_CNTRL_0_RTC_CLK_DIS_DEFAULT                    _MK_MASK_CONST(0x0)
#define PMC_IMPL_CNTRL_0_RTC_CLK_DIS_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define PMC_IMPL_CNTRL_0_RTC_CLK_DIS_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define PMC_IMPL_CNTRL_0_RTC_CLK_DIS_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define PMC_IMPL_CNTRL_0_RTC_CLK_DIS_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define PMC_IMPL_CNTRL_0_RTC_CLK_DIS_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define PMC_IMPL_CNTRL_0_RTC_CLK_DIS_DISABLE                    _MK_ENUM_CONST(0)
#define PMC_IMPL_CNTRL_0_RTC_CLK_DIS_ENABLE                     _MK_ENUM_CONST(1)

#define PMC_IMPL_CNTRL_0_RTC_RST_SHIFT                  _MK_SHIFT_CONST(2)
#define PMC_IMPL_CNTRL_0_RTC_RST_FIELD                  _MK_FIELD_CONST(0x1, PMC_IMPL_CNTRL_0_RTC_RST_SHIFT)
#define PMC_IMPL_CNTRL_0_RTC_RST_RANGE                  2:2
#define PMC_IMPL_CNTRL_0_RTC_RST_WOFFSET                        0x0
#define PMC_IMPL_CNTRL_0_RTC_RST_DEFAULT                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_CNTRL_0_RTC_RST_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define PMC_IMPL_CNTRL_0_RTC_RST_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_CNTRL_0_RTC_RST_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_CNTRL_0_RTC_RST_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_CNTRL_0_RTC_RST_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define PMC_IMPL_CNTRL_0_RTC_RST_DISABLE                        _MK_ENUM_CONST(0)
#define PMC_IMPL_CNTRL_0_RTC_RST_ENABLE                 _MK_ENUM_CONST(1)

#define PMC_IMPL_CNTRL_0_RESERVED_2_SHIFT                       _MK_SHIFT_CONST(3)
#define PMC_IMPL_CNTRL_0_RESERVED_2_FIELD                       _MK_FIELD_CONST(0x1, PMC_IMPL_CNTRL_0_RESERVED_2_SHIFT)
#define PMC_IMPL_CNTRL_0_RESERVED_2_RANGE                       3:3
#define PMC_IMPL_CNTRL_0_RESERVED_2_WOFFSET                     0x0
#define PMC_IMPL_CNTRL_0_RESERVED_2_DEFAULT                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_CNTRL_0_RESERVED_2_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define PMC_IMPL_CNTRL_0_RESERVED_2_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define PMC_IMPL_CNTRL_0_RESERVED_2_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_CNTRL_0_RESERVED_2_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_CNTRL_0_RESERVED_2_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define PMC_IMPL_CNTRL_0_MAIN_RST_SHIFT                 _MK_SHIFT_CONST(4)
#define PMC_IMPL_CNTRL_0_MAIN_RST_FIELD                 _MK_FIELD_CONST(0x1, PMC_IMPL_CNTRL_0_MAIN_RST_SHIFT)
#define PMC_IMPL_CNTRL_0_MAIN_RST_RANGE                 4:4
#define PMC_IMPL_CNTRL_0_MAIN_RST_WOFFSET                       0x0
#define PMC_IMPL_CNTRL_0_MAIN_RST_DEFAULT                       _MK_MASK_CONST(0x0)
#define PMC_IMPL_CNTRL_0_MAIN_RST_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define PMC_IMPL_CNTRL_0_MAIN_RST_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define PMC_IMPL_CNTRL_0_MAIN_RST_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define PMC_IMPL_CNTRL_0_MAIN_RST_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_CNTRL_0_MAIN_RST_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)
#define PMC_IMPL_CNTRL_0_MAIN_RST_DISABLE                       _MK_ENUM_CONST(0)
#define PMC_IMPL_CNTRL_0_MAIN_RST_ENABLE                        _MK_ENUM_CONST(1)

#define PMC_IMPL_CNTRL_0_BLINK_EN_SHIFT                 _MK_SHIFT_CONST(7)
#define PMC_IMPL_CNTRL_0_BLINK_EN_FIELD                 _MK_FIELD_CONST(0x1, PMC_IMPL_CNTRL_0_BLINK_EN_SHIFT)
#define PMC_IMPL_CNTRL_0_BLINK_EN_RANGE                 7:7
#define PMC_IMPL_CNTRL_0_BLINK_EN_WOFFSET                       0x0
#define PMC_IMPL_CNTRL_0_BLINK_EN_DEFAULT                       _MK_MASK_CONST(0x0)
#define PMC_IMPL_CNTRL_0_BLINK_EN_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define PMC_IMPL_CNTRL_0_BLINK_EN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define PMC_IMPL_CNTRL_0_BLINK_EN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define PMC_IMPL_CNTRL_0_BLINK_EN_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_CNTRL_0_BLINK_EN_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)
#define PMC_IMPL_CNTRL_0_BLINK_EN_DISABLE                       _MK_ENUM_CONST(0)
#define PMC_IMPL_CNTRL_0_BLINK_EN_ENABLE                        _MK_ENUM_CONST(1)

#define PMC_IMPL_CNTRL_0_PWRREQ_POLARITY_SHIFT                  _MK_SHIFT_CONST(8)
#define PMC_IMPL_CNTRL_0_PWRREQ_POLARITY_FIELD                  _MK_FIELD_CONST(0x1, PMC_IMPL_CNTRL_0_PWRREQ_POLARITY_SHIFT)
#define PMC_IMPL_CNTRL_0_PWRREQ_POLARITY_RANGE                  8:8
#define PMC_IMPL_CNTRL_0_PWRREQ_POLARITY_WOFFSET                        0x0
#define PMC_IMPL_CNTRL_0_PWRREQ_POLARITY_DEFAULT                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_CNTRL_0_PWRREQ_POLARITY_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define PMC_IMPL_CNTRL_0_PWRREQ_POLARITY_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_CNTRL_0_PWRREQ_POLARITY_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_CNTRL_0_PWRREQ_POLARITY_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_CNTRL_0_PWRREQ_POLARITY_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define PMC_IMPL_CNTRL_0_PWRREQ_POLARITY_NORMAL                 _MK_ENUM_CONST(0)
#define PMC_IMPL_CNTRL_0_PWRREQ_POLARITY_INVERT                 _MK_ENUM_CONST(1)

#define PMC_IMPL_CNTRL_0_PWRREQ_OE_SHIFT                        _MK_SHIFT_CONST(9)
#define PMC_IMPL_CNTRL_0_PWRREQ_OE_FIELD                        _MK_FIELD_CONST(0x1, PMC_IMPL_CNTRL_0_PWRREQ_OE_SHIFT)
#define PMC_IMPL_CNTRL_0_PWRREQ_OE_RANGE                        9:9
#define PMC_IMPL_CNTRL_0_PWRREQ_OE_WOFFSET                      0x0
#define PMC_IMPL_CNTRL_0_PWRREQ_OE_DEFAULT                      _MK_MASK_CONST(0x1)
#define PMC_IMPL_CNTRL_0_PWRREQ_OE_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define PMC_IMPL_CNTRL_0_PWRREQ_OE_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_CNTRL_0_PWRREQ_OE_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_CNTRL_0_PWRREQ_OE_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define PMC_IMPL_CNTRL_0_PWRREQ_OE_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)
#define PMC_IMPL_CNTRL_0_PWRREQ_OE_DISABLE                      _MK_ENUM_CONST(0)
#define PMC_IMPL_CNTRL_0_PWRREQ_OE_ENABLE                       _MK_ENUM_CONST(1)

#define PMC_IMPL_CNTRL_0_SYSCLK_POLARITY_SHIFT                  _MK_SHIFT_CONST(10)
#define PMC_IMPL_CNTRL_0_SYSCLK_POLARITY_FIELD                  _MK_FIELD_CONST(0x1, PMC_IMPL_CNTRL_0_SYSCLK_POLARITY_SHIFT)
#define PMC_IMPL_CNTRL_0_SYSCLK_POLARITY_RANGE                  10:10
#define PMC_IMPL_CNTRL_0_SYSCLK_POLARITY_WOFFSET                        0x0
#define PMC_IMPL_CNTRL_0_SYSCLK_POLARITY_DEFAULT                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_CNTRL_0_SYSCLK_POLARITY_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define PMC_IMPL_CNTRL_0_SYSCLK_POLARITY_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_CNTRL_0_SYSCLK_POLARITY_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_CNTRL_0_SYSCLK_POLARITY_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_CNTRL_0_SYSCLK_POLARITY_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define PMC_IMPL_CNTRL_0_SYSCLK_POLARITY_NORMAL                 _MK_ENUM_CONST(0)
#define PMC_IMPL_CNTRL_0_SYSCLK_POLARITY_INVERT                 _MK_ENUM_CONST(1)

#define PMC_IMPL_CNTRL_0_SYSCLK_OE_SHIFT                        _MK_SHIFT_CONST(11)
#define PMC_IMPL_CNTRL_0_SYSCLK_OE_FIELD                        _MK_FIELD_CONST(0x1, PMC_IMPL_CNTRL_0_SYSCLK_OE_SHIFT)
#define PMC_IMPL_CNTRL_0_SYSCLK_OE_RANGE                        11:11
#define PMC_IMPL_CNTRL_0_SYSCLK_OE_WOFFSET                      0x0
#define PMC_IMPL_CNTRL_0_SYSCLK_OE_DEFAULT                      _MK_MASK_CONST(0x1)
#define PMC_IMPL_CNTRL_0_SYSCLK_OE_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define PMC_IMPL_CNTRL_0_SYSCLK_OE_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_CNTRL_0_SYSCLK_OE_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_CNTRL_0_SYSCLK_OE_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define PMC_IMPL_CNTRL_0_SYSCLK_OE_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)
#define PMC_IMPL_CNTRL_0_SYSCLK_OE_DISABLE                      _MK_ENUM_CONST(0)
#define PMC_IMPL_CNTRL_0_SYSCLK_OE_ENABLE                       _MK_ENUM_CONST(1)

#define PMC_IMPL_CNTRL_0_PWRGATE_DIS_SHIFT                      _MK_SHIFT_CONST(12)
#define PMC_IMPL_CNTRL_0_PWRGATE_DIS_FIELD                      _MK_FIELD_CONST(0x1, PMC_IMPL_CNTRL_0_PWRGATE_DIS_SHIFT)
#define PMC_IMPL_CNTRL_0_PWRGATE_DIS_RANGE                      12:12
#define PMC_IMPL_CNTRL_0_PWRGATE_DIS_WOFFSET                    0x0
#define PMC_IMPL_CNTRL_0_PWRGATE_DIS_DEFAULT                    _MK_MASK_CONST(0x0)
#define PMC_IMPL_CNTRL_0_PWRGATE_DIS_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define PMC_IMPL_CNTRL_0_PWRGATE_DIS_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define PMC_IMPL_CNTRL_0_PWRGATE_DIS_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define PMC_IMPL_CNTRL_0_PWRGATE_DIS_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define PMC_IMPL_CNTRL_0_PWRGATE_DIS_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define PMC_IMPL_CNTRL_0_PWRGATE_DIS_DISABLE                    _MK_ENUM_CONST(0)
#define PMC_IMPL_CNTRL_0_PWRGATE_DIS_ENABLE                     _MK_ENUM_CONST(1)

#define PMC_IMPL_CNTRL_0_AOINIT_SHIFT                   _MK_SHIFT_CONST(13)
#define PMC_IMPL_CNTRL_0_AOINIT_FIELD                   _MK_FIELD_CONST(0x1, PMC_IMPL_CNTRL_0_AOINIT_SHIFT)
#define PMC_IMPL_CNTRL_0_AOINIT_RANGE                   13:13
#define PMC_IMPL_CNTRL_0_AOINIT_WOFFSET                 0x0
#define PMC_IMPL_CNTRL_0_AOINIT_DEFAULT                 _MK_MASK_CONST(0x0)
#define PMC_IMPL_CNTRL_0_AOINIT_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define PMC_IMPL_CNTRL_0_AOINIT_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_CNTRL_0_AOINIT_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define PMC_IMPL_CNTRL_0_AOINIT_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define PMC_IMPL_CNTRL_0_AOINIT_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define PMC_IMPL_CNTRL_0_AOINIT_NOTDONE                 _MK_ENUM_CONST(0)
#define PMC_IMPL_CNTRL_0_AOINIT_DONE                    _MK_ENUM_CONST(1)

#define PMC_IMPL_CNTRL_0_SIDE_EFFECT_LP0_SHIFT                  _MK_SHIFT_CONST(14)
#define PMC_IMPL_CNTRL_0_SIDE_EFFECT_LP0_FIELD                  _MK_FIELD_CONST(0x1, PMC_IMPL_CNTRL_0_SIDE_EFFECT_LP0_SHIFT)
#define PMC_IMPL_CNTRL_0_SIDE_EFFECT_LP0_RANGE                  14:14
#define PMC_IMPL_CNTRL_0_SIDE_EFFECT_LP0_WOFFSET                        0x0
#define PMC_IMPL_CNTRL_0_SIDE_EFFECT_LP0_DEFAULT                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_CNTRL_0_SIDE_EFFECT_LP0_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define PMC_IMPL_CNTRL_0_SIDE_EFFECT_LP0_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_CNTRL_0_SIDE_EFFECT_LP0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_CNTRL_0_SIDE_EFFECT_LP0_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_CNTRL_0_SIDE_EFFECT_LP0_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define PMC_IMPL_CNTRL_0_SIDE_EFFECT_LP0_DISABLE                        _MK_ENUM_CONST(0)
#define PMC_IMPL_CNTRL_0_SIDE_EFFECT_LP0_ENABLE                 _MK_ENUM_CONST(1)

#define PMC_IMPL_CNTRL_0_FUSE_OVERRIDE_SHIFT                    _MK_SHIFT_CONST(18)
#define PMC_IMPL_CNTRL_0_FUSE_OVERRIDE_FIELD                    _MK_FIELD_CONST(0x1, PMC_IMPL_CNTRL_0_FUSE_OVERRIDE_SHIFT)
#define PMC_IMPL_CNTRL_0_FUSE_OVERRIDE_RANGE                    18:18
#define PMC_IMPL_CNTRL_0_FUSE_OVERRIDE_WOFFSET                  0x0
#define PMC_IMPL_CNTRL_0_FUSE_OVERRIDE_DEFAULT                  _MK_MASK_CONST(0x0)
#define PMC_IMPL_CNTRL_0_FUSE_OVERRIDE_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define PMC_IMPL_CNTRL_0_FUSE_OVERRIDE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define PMC_IMPL_CNTRL_0_FUSE_OVERRIDE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define PMC_IMPL_CNTRL_0_FUSE_OVERRIDE_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_CNTRL_0_FUSE_OVERRIDE_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)
#define PMC_IMPL_CNTRL_0_FUSE_OVERRIDE_DISABLE                  _MK_ENUM_CONST(0)
#define PMC_IMPL_CNTRL_0_FUSE_OVERRIDE_ENABLE                   _MK_ENUM_CONST(1)

#define PMC_IMPL_CNTRL_0_SHUTDOWN_OE_SHIFT                      _MK_SHIFT_CONST(22)
#define PMC_IMPL_CNTRL_0_SHUTDOWN_OE_FIELD                      _MK_FIELD_CONST(0x1, PMC_IMPL_CNTRL_0_SHUTDOWN_OE_SHIFT)
#define PMC_IMPL_CNTRL_0_SHUTDOWN_OE_RANGE                      22:22
#define PMC_IMPL_CNTRL_0_SHUTDOWN_OE_WOFFSET                    0x0
#define PMC_IMPL_CNTRL_0_SHUTDOWN_OE_DEFAULT                    _MK_MASK_CONST(0x1)
#define PMC_IMPL_CNTRL_0_SHUTDOWN_OE_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define PMC_IMPL_CNTRL_0_SHUTDOWN_OE_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define PMC_IMPL_CNTRL_0_SHUTDOWN_OE_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define PMC_IMPL_CNTRL_0_SHUTDOWN_OE_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define PMC_IMPL_CNTRL_0_SHUTDOWN_OE_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define PMC_IMPL_CNTRL_0_SHUTDOWN_OE_DISABLE                    _MK_ENUM_CONST(0)
#define PMC_IMPL_CNTRL_0_SHUTDOWN_OE_ENABLE                     _MK_ENUM_CONST(1)


// Register PMC_IMPL_SLCG_CTRL_0
#define PMC_IMPL_SLCG_CTRL_0                    _MK_ADDR_CONST(0x4)
#define PMC_IMPL_SLCG_CTRL_0_SECURE                     0x0
#define PMC_IMPL_SLCG_CTRL_0_DUAL                       0x0
#define PMC_IMPL_SLCG_CTRL_0_SCR                        CNTRL_SCR_0
#define PMC_IMPL_SLCG_CTRL_0_WORD_COUNT                         0x1
#define PMC_IMPL_SLCG_CTRL_0_RESET_VAL                  _MK_MASK_CONST(0x70000)
#define PMC_IMPL_SLCG_CTRL_0_RESET_MASK                         _MK_MASK_CONST(0xff0707)
#define PMC_IMPL_SLCG_CTRL_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_SLCG_CTRL_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define PMC_IMPL_SLCG_CTRL_0_READ_MASK                  _MK_MASK_CONST(0xff0707)
#define PMC_IMPL_SLCG_CTRL_0_WRITE_MASK                         _MK_MASK_CONST(0xff0707)
#define PMC_IMPL_SLCG_CTRL_0_PCLK_SLCG_EN_SHIFT                 _MK_SHIFT_CONST(0)
#define PMC_IMPL_SLCG_CTRL_0_PCLK_SLCG_EN_FIELD                 _MK_FIELD_CONST(0x1, PMC_IMPL_SLCG_CTRL_0_PCLK_SLCG_EN_SHIFT)
#define PMC_IMPL_SLCG_CTRL_0_PCLK_SLCG_EN_RANGE                 0:0
#define PMC_IMPL_SLCG_CTRL_0_PCLK_SLCG_EN_WOFFSET                       0x0
#define PMC_IMPL_SLCG_CTRL_0_PCLK_SLCG_EN_DEFAULT                       _MK_MASK_CONST(0x0)
#define PMC_IMPL_SLCG_CTRL_0_PCLK_SLCG_EN_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define PMC_IMPL_SLCG_CTRL_0_PCLK_SLCG_EN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define PMC_IMPL_SLCG_CTRL_0_PCLK_SLCG_EN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define PMC_IMPL_SLCG_CTRL_0_PCLK_SLCG_EN_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_SLCG_CTRL_0_PCLK_SLCG_EN_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)
#define PMC_IMPL_SLCG_CTRL_0_PCLK_SLCG_EN_INIT_ENUM                     DISABLE
#define PMC_IMPL_SLCG_CTRL_0_PCLK_SLCG_EN_DISABLE                       _MK_ENUM_CONST(0)
#define PMC_IMPL_SLCG_CTRL_0_PCLK_SLCG_EN_ENABLE                        _MK_ENUM_CONST(1)

#define PMC_IMPL_SLCG_CTRL_0_CLK32_SLCG_EN_SHIFT                        _MK_SHIFT_CONST(1)
#define PMC_IMPL_SLCG_CTRL_0_CLK32_SLCG_EN_FIELD                        _MK_FIELD_CONST(0x1, PMC_IMPL_SLCG_CTRL_0_CLK32_SLCG_EN_SHIFT)
#define PMC_IMPL_SLCG_CTRL_0_CLK32_SLCG_EN_RANGE                        1:1
#define PMC_IMPL_SLCG_CTRL_0_CLK32_SLCG_EN_WOFFSET                      0x0
#define PMC_IMPL_SLCG_CTRL_0_CLK32_SLCG_EN_DEFAULT                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_SLCG_CTRL_0_CLK32_SLCG_EN_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define PMC_IMPL_SLCG_CTRL_0_CLK32_SLCG_EN_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_SLCG_CTRL_0_CLK32_SLCG_EN_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_SLCG_CTRL_0_CLK32_SLCG_EN_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define PMC_IMPL_SLCG_CTRL_0_CLK32_SLCG_EN_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)
#define PMC_IMPL_SLCG_CTRL_0_CLK32_SLCG_EN_INIT_ENUM                    DISABLE
#define PMC_IMPL_SLCG_CTRL_0_CLK32_SLCG_EN_DISABLE                      _MK_ENUM_CONST(0)
#define PMC_IMPL_SLCG_CTRL_0_CLK32_SLCG_EN_ENABLE                       _MK_ENUM_CONST(1)

#define PMC_IMPL_SLCG_CTRL_0_FUSE_SLCG_EN_SHIFT                 _MK_SHIFT_CONST(2)
#define PMC_IMPL_SLCG_CTRL_0_FUSE_SLCG_EN_FIELD                 _MK_FIELD_CONST(0x1, PMC_IMPL_SLCG_CTRL_0_FUSE_SLCG_EN_SHIFT)
#define PMC_IMPL_SLCG_CTRL_0_FUSE_SLCG_EN_RANGE                 2:2
#define PMC_IMPL_SLCG_CTRL_0_FUSE_SLCG_EN_WOFFSET                       0x0
#define PMC_IMPL_SLCG_CTRL_0_FUSE_SLCG_EN_DEFAULT                       _MK_MASK_CONST(0x0)
#define PMC_IMPL_SLCG_CTRL_0_FUSE_SLCG_EN_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define PMC_IMPL_SLCG_CTRL_0_FUSE_SLCG_EN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define PMC_IMPL_SLCG_CTRL_0_FUSE_SLCG_EN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define PMC_IMPL_SLCG_CTRL_0_FUSE_SLCG_EN_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_SLCG_CTRL_0_FUSE_SLCG_EN_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)
#define PMC_IMPL_SLCG_CTRL_0_FUSE_SLCG_EN_INIT_ENUM                     DISABLE
#define PMC_IMPL_SLCG_CTRL_0_FUSE_SLCG_EN_DISABLE                       _MK_ENUM_CONST(0)
#define PMC_IMPL_SLCG_CTRL_0_FUSE_SLCG_EN_ENABLE                        _MK_ENUM_CONST(1)

#define PMC_IMPL_SLCG_CTRL_0_PCLK_REG_SLCG_EN_SHIFT                     _MK_SHIFT_CONST(8)
#define PMC_IMPL_SLCG_CTRL_0_PCLK_REG_SLCG_EN_FIELD                     _MK_FIELD_CONST(0x1, PMC_IMPL_SLCG_CTRL_0_PCLK_REG_SLCG_EN_SHIFT)
#define PMC_IMPL_SLCG_CTRL_0_PCLK_REG_SLCG_EN_RANGE                     8:8
#define PMC_IMPL_SLCG_CTRL_0_PCLK_REG_SLCG_EN_WOFFSET                   0x0
#define PMC_IMPL_SLCG_CTRL_0_PCLK_REG_SLCG_EN_DEFAULT                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_SLCG_CTRL_0_PCLK_REG_SLCG_EN_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define PMC_IMPL_SLCG_CTRL_0_PCLK_REG_SLCG_EN_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_SLCG_CTRL_0_PCLK_REG_SLCG_EN_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_SLCG_CTRL_0_PCLK_REG_SLCG_EN_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define PMC_IMPL_SLCG_CTRL_0_PCLK_REG_SLCG_EN_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define PMC_IMPL_SLCG_CTRL_0_PCLK_REG_SLCG_EN_INIT_ENUM                 DISABLE
#define PMC_IMPL_SLCG_CTRL_0_PCLK_REG_SLCG_EN_DISABLE                   _MK_ENUM_CONST(0)
#define PMC_IMPL_SLCG_CTRL_0_PCLK_REG_SLCG_EN_ENABLE                    _MK_ENUM_CONST(1)

#define PMC_IMPL_SLCG_CTRL_0_PCLK_PG_SLCG_EN_SHIFT                      _MK_SHIFT_CONST(9)
#define PMC_IMPL_SLCG_CTRL_0_PCLK_PG_SLCG_EN_FIELD                      _MK_FIELD_CONST(0x1, PMC_IMPL_SLCG_CTRL_0_PCLK_PG_SLCG_EN_SHIFT)
#define PMC_IMPL_SLCG_CTRL_0_PCLK_PG_SLCG_EN_RANGE                      9:9
#define PMC_IMPL_SLCG_CTRL_0_PCLK_PG_SLCG_EN_WOFFSET                    0x0
#define PMC_IMPL_SLCG_CTRL_0_PCLK_PG_SLCG_EN_DEFAULT                    _MK_MASK_CONST(0x0)
#define PMC_IMPL_SLCG_CTRL_0_PCLK_PG_SLCG_EN_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define PMC_IMPL_SLCG_CTRL_0_PCLK_PG_SLCG_EN_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define PMC_IMPL_SLCG_CTRL_0_PCLK_PG_SLCG_EN_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define PMC_IMPL_SLCG_CTRL_0_PCLK_PG_SLCG_EN_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define PMC_IMPL_SLCG_CTRL_0_PCLK_PG_SLCG_EN_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define PMC_IMPL_SLCG_CTRL_0_PCLK_PG_SLCG_EN_INIT_ENUM                  DISABLE
#define PMC_IMPL_SLCG_CTRL_0_PCLK_PG_SLCG_EN_DISABLE                    _MK_ENUM_CONST(0)
#define PMC_IMPL_SLCG_CTRL_0_PCLK_PG_SLCG_EN_ENABLE                     _MK_ENUM_CONST(1)

#define PMC_IMPL_SLCG_CTRL_0_PCLK_DPD_SLCG_EN_SHIFT                     _MK_SHIFT_CONST(10)
#define PMC_IMPL_SLCG_CTRL_0_PCLK_DPD_SLCG_EN_FIELD                     _MK_FIELD_CONST(0x1, PMC_IMPL_SLCG_CTRL_0_PCLK_DPD_SLCG_EN_SHIFT)
#define PMC_IMPL_SLCG_CTRL_0_PCLK_DPD_SLCG_EN_RANGE                     10:10
#define PMC_IMPL_SLCG_CTRL_0_PCLK_DPD_SLCG_EN_WOFFSET                   0x0
#define PMC_IMPL_SLCG_CTRL_0_PCLK_DPD_SLCG_EN_DEFAULT                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_SLCG_CTRL_0_PCLK_DPD_SLCG_EN_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define PMC_IMPL_SLCG_CTRL_0_PCLK_DPD_SLCG_EN_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_SLCG_CTRL_0_PCLK_DPD_SLCG_EN_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_SLCG_CTRL_0_PCLK_DPD_SLCG_EN_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define PMC_IMPL_SLCG_CTRL_0_PCLK_DPD_SLCG_EN_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define PMC_IMPL_SLCG_CTRL_0_PCLK_DPD_SLCG_EN_INIT_ENUM                 DISABLE
#define PMC_IMPL_SLCG_CTRL_0_PCLK_DPD_SLCG_EN_DISABLE                   _MK_ENUM_CONST(0)
#define PMC_IMPL_SLCG_CTRL_0_PCLK_DPD_SLCG_EN_ENABLE                    _MK_ENUM_CONST(1)

#define PMC_IMPL_SLCG_CTRL_0_PCLK_REG_SLCG_TIMER_SHIFT                  _MK_SHIFT_CONST(16)
#define PMC_IMPL_SLCG_CTRL_0_PCLK_REG_SLCG_TIMER_FIELD                  _MK_FIELD_CONST(0xff, PMC_IMPL_SLCG_CTRL_0_PCLK_REG_SLCG_TIMER_SHIFT)
#define PMC_IMPL_SLCG_CTRL_0_PCLK_REG_SLCG_TIMER_RANGE                  23:16
#define PMC_IMPL_SLCG_CTRL_0_PCLK_REG_SLCG_TIMER_WOFFSET                        0x0
#define PMC_IMPL_SLCG_CTRL_0_PCLK_REG_SLCG_TIMER_DEFAULT                        _MK_MASK_CONST(0x7)
#define PMC_IMPL_SLCG_CTRL_0_PCLK_REG_SLCG_TIMER_DEFAULT_MASK                   _MK_MASK_CONST(0xff)
#define PMC_IMPL_SLCG_CTRL_0_PCLK_REG_SLCG_TIMER_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_SLCG_CTRL_0_PCLK_REG_SLCG_TIMER_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_SLCG_CTRL_0_PCLK_REG_SLCG_TIMER_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_SLCG_CTRL_0_PCLK_REG_SLCG_TIMER_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)


// Register PMC_IMPL_DPD_PADS_ORIDE_0
#define PMC_IMPL_DPD_PADS_ORIDE_0                       _MK_ADDR_CONST(0x8)
#define PMC_IMPL_DPD_PADS_ORIDE_0_SECURE                        0x0
#define PMC_IMPL_DPD_PADS_ORIDE_0_DUAL                  0x0
#define PMC_IMPL_DPD_PADS_ORIDE_0_SCR                   DPD_PADS_ORIDE_SCR_0
#define PMC_IMPL_DPD_PADS_ORIDE_0_WORD_COUNT                    0x1
#define PMC_IMPL_DPD_PADS_ORIDE_0_RESET_VAL                     _MK_MASK_CONST(0x200000)
#define PMC_IMPL_DPD_PADS_ORIDE_0_RESET_MASK                    _MK_MASK_CONST(0xffffffff)
#define PMC_IMPL_DPD_PADS_ORIDE_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_DPD_PADS_ORIDE_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define PMC_IMPL_DPD_PADS_ORIDE_0_READ_MASK                     _MK_MASK_CONST(0xffffffff)
#define PMC_IMPL_DPD_PADS_ORIDE_0_WRITE_MASK                    _MK_MASK_CONST(0xffffffff)
#define PMC_IMPL_DPD_PADS_ORIDE_0_RESERVED_1_SHIFT                      _MK_SHIFT_CONST(0)
#define PMC_IMPL_DPD_PADS_ORIDE_0_RESERVED_1_FIELD                      _MK_FIELD_CONST(0xfffff, PMC_IMPL_DPD_PADS_ORIDE_0_RESERVED_1_SHIFT)
#define PMC_IMPL_DPD_PADS_ORIDE_0_RESERVED_1_RANGE                      19:0
#define PMC_IMPL_DPD_PADS_ORIDE_0_RESERVED_1_WOFFSET                    0x0
#define PMC_IMPL_DPD_PADS_ORIDE_0_RESERVED_1_DEFAULT                    _MK_MASK_CONST(0x0)
#define PMC_IMPL_DPD_PADS_ORIDE_0_RESERVED_1_DEFAULT_MASK                       _MK_MASK_CONST(0xfffff)
#define PMC_IMPL_DPD_PADS_ORIDE_0_RESERVED_1_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define PMC_IMPL_DPD_PADS_ORIDE_0_RESERVED_1_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define PMC_IMPL_DPD_PADS_ORIDE_0_RESERVED_1_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define PMC_IMPL_DPD_PADS_ORIDE_0_RESERVED_1_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)

#define PMC_IMPL_DPD_PADS_ORIDE_0_BLINK_SHIFT                   _MK_SHIFT_CONST(20)
#define PMC_IMPL_DPD_PADS_ORIDE_0_BLINK_FIELD                   _MK_FIELD_CONST(0x1, PMC_IMPL_DPD_PADS_ORIDE_0_BLINK_SHIFT)
#define PMC_IMPL_DPD_PADS_ORIDE_0_BLINK_RANGE                   20:20
#define PMC_IMPL_DPD_PADS_ORIDE_0_BLINK_WOFFSET                 0x0
#define PMC_IMPL_DPD_PADS_ORIDE_0_BLINK_DEFAULT                 _MK_MASK_CONST(0x0)
#define PMC_IMPL_DPD_PADS_ORIDE_0_BLINK_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define PMC_IMPL_DPD_PADS_ORIDE_0_BLINK_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_DPD_PADS_ORIDE_0_BLINK_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define PMC_IMPL_DPD_PADS_ORIDE_0_BLINK_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define PMC_IMPL_DPD_PADS_ORIDE_0_BLINK_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define PMC_IMPL_DPD_PADS_ORIDE_0_BLINK_DISABLE                 _MK_ENUM_CONST(0)
#define PMC_IMPL_DPD_PADS_ORIDE_0_BLINK_ENABLE                  _MK_ENUM_CONST(1)

#define PMC_IMPL_DPD_PADS_ORIDE_0_SYS_CLK_SHIFT                 _MK_SHIFT_CONST(21)
#define PMC_IMPL_DPD_PADS_ORIDE_0_SYS_CLK_FIELD                 _MK_FIELD_CONST(0x1, PMC_IMPL_DPD_PADS_ORIDE_0_SYS_CLK_SHIFT)
#define PMC_IMPL_DPD_PADS_ORIDE_0_SYS_CLK_RANGE                 21:21
#define PMC_IMPL_DPD_PADS_ORIDE_0_SYS_CLK_WOFFSET                       0x0
#define PMC_IMPL_DPD_PADS_ORIDE_0_SYS_CLK_DEFAULT                       _MK_MASK_CONST(0x1)
#define PMC_IMPL_DPD_PADS_ORIDE_0_SYS_CLK_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define PMC_IMPL_DPD_PADS_ORIDE_0_SYS_CLK_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define PMC_IMPL_DPD_PADS_ORIDE_0_SYS_CLK_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define PMC_IMPL_DPD_PADS_ORIDE_0_SYS_CLK_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_DPD_PADS_ORIDE_0_SYS_CLK_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)
#define PMC_IMPL_DPD_PADS_ORIDE_0_SYS_CLK_DISABLE                       _MK_ENUM_CONST(0)
#define PMC_IMPL_DPD_PADS_ORIDE_0_SYS_CLK_ENABLE                        _MK_ENUM_CONST(1)

#define PMC_IMPL_DPD_PADS_ORIDE_0_RESERVED_2_SHIFT                      _MK_SHIFT_CONST(22)
#define PMC_IMPL_DPD_PADS_ORIDE_0_RESERVED_2_FIELD                      _MK_FIELD_CONST(0x3ff, PMC_IMPL_DPD_PADS_ORIDE_0_RESERVED_2_SHIFT)
#define PMC_IMPL_DPD_PADS_ORIDE_0_RESERVED_2_RANGE                      31:22
#define PMC_IMPL_DPD_PADS_ORIDE_0_RESERVED_2_WOFFSET                    0x0
#define PMC_IMPL_DPD_PADS_ORIDE_0_RESERVED_2_DEFAULT                    _MK_MASK_CONST(0x0)
#define PMC_IMPL_DPD_PADS_ORIDE_0_RESERVED_2_DEFAULT_MASK                       _MK_MASK_CONST(0x3ff)
#define PMC_IMPL_DPD_PADS_ORIDE_0_RESERVED_2_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define PMC_IMPL_DPD_PADS_ORIDE_0_RESERVED_2_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define PMC_IMPL_DPD_PADS_ORIDE_0_RESERVED_2_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define PMC_IMPL_DPD_PADS_ORIDE_0_RESERVED_2_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)


// Reserved address 0xc

// Register PMC_IMPL_DPD_ENABLE_0
#define PMC_IMPL_DPD_ENABLE_0                   _MK_ADDR_CONST(0x10)
#define PMC_IMPL_DPD_ENABLE_0_SECURE                    0x0
#define PMC_IMPL_DPD_ENABLE_0_DUAL                      0x0
#define PMC_IMPL_DPD_ENABLE_0_SCR                       DPD_ENABLE_SCR_0
#define PMC_IMPL_DPD_ENABLE_0_WORD_COUNT                        0x1
#define PMC_IMPL_DPD_ENABLE_0_RESET_VAL                         _MK_MASK_CONST(0x0)
#define PMC_IMPL_DPD_ENABLE_0_RESET_MASK                        _MK_MASK_CONST(0x3)
#define PMC_IMPL_DPD_ENABLE_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define PMC_IMPL_DPD_ENABLE_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_DPD_ENABLE_0_READ_MASK                         _MK_MASK_CONST(0x3)
#define PMC_IMPL_DPD_ENABLE_0_WRITE_MASK                        _MK_MASK_CONST(0x3)
#define PMC_IMPL_DPD_ENABLE_0_TSC_MULT_EN_SHIFT                 _MK_SHIFT_CONST(1)
#define PMC_IMPL_DPD_ENABLE_0_TSC_MULT_EN_FIELD                 _MK_FIELD_CONST(0x1, PMC_IMPL_DPD_ENABLE_0_TSC_MULT_EN_SHIFT)
#define PMC_IMPL_DPD_ENABLE_0_TSC_MULT_EN_RANGE                 1:1
#define PMC_IMPL_DPD_ENABLE_0_TSC_MULT_EN_WOFFSET                       0x0
#define PMC_IMPL_DPD_ENABLE_0_TSC_MULT_EN_DEFAULT                       _MK_MASK_CONST(0x0)
#define PMC_IMPL_DPD_ENABLE_0_TSC_MULT_EN_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define PMC_IMPL_DPD_ENABLE_0_TSC_MULT_EN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define PMC_IMPL_DPD_ENABLE_0_TSC_MULT_EN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define PMC_IMPL_DPD_ENABLE_0_TSC_MULT_EN_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_DPD_ENABLE_0_TSC_MULT_EN_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)
#define PMC_IMPL_DPD_ENABLE_0_TSC_MULT_EN_DISABLE                       _MK_ENUM_CONST(0)
#define PMC_IMPL_DPD_ENABLE_0_TSC_MULT_EN_ENABLE                        _MK_ENUM_CONST(1)

#define PMC_IMPL_DPD_ENABLE_0_ON_SHIFT                  _MK_SHIFT_CONST(0)
#define PMC_IMPL_DPD_ENABLE_0_ON_FIELD                  _MK_FIELD_CONST(0x1, PMC_IMPL_DPD_ENABLE_0_ON_SHIFT)
#define PMC_IMPL_DPD_ENABLE_0_ON_RANGE                  0:0
#define PMC_IMPL_DPD_ENABLE_0_ON_WOFFSET                        0x0
#define PMC_IMPL_DPD_ENABLE_0_ON_DEFAULT                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_DPD_ENABLE_0_ON_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define PMC_IMPL_DPD_ENABLE_0_ON_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_DPD_ENABLE_0_ON_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_DPD_ENABLE_0_ON_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_DPD_ENABLE_0_ON_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define PMC_IMPL_DPD_ENABLE_0_ON_DISABLE                        _MK_ENUM_CONST(0)
#define PMC_IMPL_DPD_ENABLE_0_ON_ENABLE                 _MK_ENUM_CONST(1)


// Register PMC_IMPL_SC7_CONFIG_0
#define PMC_IMPL_SC7_CONFIG_0                   _MK_ADDR_CONST(0x14)
#define PMC_IMPL_SC7_CONFIG_0_SECURE                    0x0
#define PMC_IMPL_SC7_CONFIG_0_DUAL                      0x0
#define PMC_IMPL_SC7_CONFIG_0_SCR                       SC78_SCR_0
#define PMC_IMPL_SC7_CONFIG_0_WORD_COUNT                        0x1
#define PMC_IMPL_SC7_CONFIG_0_RESET_VAL                         _MK_MASK_CONST(0x40400)
#define PMC_IMPL_SC7_CONFIG_0_RESET_MASK                        _MK_MASK_CONST(0xffff03)
#define PMC_IMPL_SC7_CONFIG_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define PMC_IMPL_SC7_CONFIG_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_SC7_CONFIG_0_READ_MASK                         _MK_MASK_CONST(0xffff03)
#define PMC_IMPL_SC7_CONFIG_0_WRITE_MASK                        _MK_MASK_CONST(0xffff03)
#define PMC_IMPL_SC7_CONFIG_0_SC7_TARGET_SHIFT                  _MK_SHIFT_CONST(0)
#define PMC_IMPL_SC7_CONFIG_0_SC7_TARGET_FIELD                  _MK_FIELD_CONST(0x1, PMC_IMPL_SC7_CONFIG_0_SC7_TARGET_SHIFT)
#define PMC_IMPL_SC7_CONFIG_0_SC7_TARGET_RANGE                  0:0
#define PMC_IMPL_SC7_CONFIG_0_SC7_TARGET_WOFFSET                        0x0
#define PMC_IMPL_SC7_CONFIG_0_SC7_TARGET_DEFAULT                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_SC7_CONFIG_0_SC7_TARGET_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define PMC_IMPL_SC7_CONFIG_0_SC7_TARGET_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_SC7_CONFIG_0_SC7_TARGET_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_SC7_CONFIG_0_SC7_TARGET_PARITY_PROTECTION                      _MK_MASK_CONST(0x1)
#define PMC_IMPL_SC7_CONFIG_0_SC7_TARGET_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define PMC_IMPL_SC7_CONFIG_0_SC7_TARGET_INIT_ENUM                      SC7
#define PMC_IMPL_SC7_CONFIG_0_SC7_TARGET_SC7                    _MK_ENUM_CONST(0)
#define PMC_IMPL_SC7_CONFIG_0_SC7_TARGET_SC8                    _MK_ENUM_CONST(1)

#define PMC_IMPL_SC7_CONFIG_0_SC8_HW_BYPASS_SHIFT                       _MK_SHIFT_CONST(1)
#define PMC_IMPL_SC7_CONFIG_0_SC8_HW_BYPASS_FIELD                       _MK_FIELD_CONST(0x1, PMC_IMPL_SC7_CONFIG_0_SC8_HW_BYPASS_SHIFT)
#define PMC_IMPL_SC7_CONFIG_0_SC8_HW_BYPASS_RANGE                       1:1
#define PMC_IMPL_SC7_CONFIG_0_SC8_HW_BYPASS_WOFFSET                     0x0
#define PMC_IMPL_SC7_CONFIG_0_SC8_HW_BYPASS_DEFAULT                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_SC7_CONFIG_0_SC8_HW_BYPASS_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define PMC_IMPL_SC7_CONFIG_0_SC8_HW_BYPASS_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define PMC_IMPL_SC7_CONFIG_0_SC8_HW_BYPASS_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_SC7_CONFIG_0_SC8_HW_BYPASS_PARITY_PROTECTION                   _MK_MASK_CONST(0x1)
#define PMC_IMPL_SC7_CONFIG_0_SC8_HW_BYPASS_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define PMC_IMPL_SC7_CONFIG_0_SC8_HW_BYPASS_INIT_ENUM                   OFF
#define PMC_IMPL_SC7_CONFIG_0_SC8_HW_BYPASS_OFF                 _MK_ENUM_CONST(0)
#define PMC_IMPL_SC7_CONFIG_0_SC8_HW_BYPASS_ON                  _MK_ENUM_CONST(1)

#define PMC_IMPL_SC7_CONFIG_0_SC7_DPD_TIMER_SHIFT                       _MK_SHIFT_CONST(8)
#define PMC_IMPL_SC7_CONFIG_0_SC7_DPD_TIMER_FIELD                       _MK_FIELD_CONST(0xff, PMC_IMPL_SC7_CONFIG_0_SC7_DPD_TIMER_SHIFT)
#define PMC_IMPL_SC7_CONFIG_0_SC7_DPD_TIMER_RANGE                       15:8
#define PMC_IMPL_SC7_CONFIG_0_SC7_DPD_TIMER_WOFFSET                     0x0
#define PMC_IMPL_SC7_CONFIG_0_SC7_DPD_TIMER_DEFAULT                     _MK_MASK_CONST(0x4)
#define PMC_IMPL_SC7_CONFIG_0_SC7_DPD_TIMER_DEFAULT_MASK                        _MK_MASK_CONST(0xff)
#define PMC_IMPL_SC7_CONFIG_0_SC7_DPD_TIMER_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define PMC_IMPL_SC7_CONFIG_0_SC7_DPD_TIMER_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_SC7_CONFIG_0_SC7_DPD_TIMER_PARITY_PROTECTION                   _MK_MASK_CONST(0x1)
#define PMC_IMPL_SC7_CONFIG_0_SC7_DPD_TIMER_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define PMC_IMPL_SC7_CONFIG_0_SC7_RES_TIMER_SHIFT                       _MK_SHIFT_CONST(16)
#define PMC_IMPL_SC7_CONFIG_0_SC7_RES_TIMER_FIELD                       _MK_FIELD_CONST(0xff, PMC_IMPL_SC7_CONFIG_0_SC7_RES_TIMER_SHIFT)
#define PMC_IMPL_SC7_CONFIG_0_SC7_RES_TIMER_RANGE                       23:16
#define PMC_IMPL_SC7_CONFIG_0_SC7_RES_TIMER_WOFFSET                     0x0
#define PMC_IMPL_SC7_CONFIG_0_SC7_RES_TIMER_DEFAULT                     _MK_MASK_CONST(0x4)
#define PMC_IMPL_SC7_CONFIG_0_SC7_RES_TIMER_DEFAULT_MASK                        _MK_MASK_CONST(0xff)
#define PMC_IMPL_SC7_CONFIG_0_SC7_RES_TIMER_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define PMC_IMPL_SC7_CONFIG_0_SC7_RES_TIMER_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_SC7_CONFIG_0_SC7_RES_TIMER_PARITY_PROTECTION                   _MK_MASK_CONST(0x1)
#define PMC_IMPL_SC7_CONFIG_0_SC7_RES_TIMER_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)


// Register PMC_IMPL_SC7_STATUS_0
#define PMC_IMPL_SC7_STATUS_0                   _MK_ADDR_CONST(0x18)
#define PMC_IMPL_SC7_STATUS_0_SECURE                    0x0
#define PMC_IMPL_SC7_STATUS_0_DUAL                      0x0
#define PMC_IMPL_SC7_STATUS_0_SCR                       SC78_SCR_0
#define PMC_IMPL_SC7_STATUS_0_WORD_COUNT                        0x1
#define PMC_IMPL_SC7_STATUS_0_RESET_VAL                         _MK_MASK_CONST(0x10)
#define PMC_IMPL_SC7_STATUS_0_RESET_MASK                        _MK_MASK_CONST(0x1f)
#define PMC_IMPL_SC7_STATUS_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define PMC_IMPL_SC7_STATUS_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_SC7_STATUS_0_READ_MASK                         _MK_MASK_CONST(0x1f)
#define PMC_IMPL_SC7_STATUS_0_WRITE_MASK                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_SC7_STATUS_0_SC_STATE_SHIFT                    _MK_SHIFT_CONST(0)
#define PMC_IMPL_SC7_STATUS_0_SC_STATE_FIELD                    _MK_FIELD_CONST(0x3, PMC_IMPL_SC7_STATUS_0_SC_STATE_SHIFT)
#define PMC_IMPL_SC7_STATUS_0_SC_STATE_RANGE                    1:0
#define PMC_IMPL_SC7_STATUS_0_SC_STATE_WOFFSET                  0x0
#define PMC_IMPL_SC7_STATUS_0_SC_STATE_DEFAULT                  _MK_MASK_CONST(0x0)
#define PMC_IMPL_SC7_STATUS_0_SC_STATE_DEFAULT_MASK                     _MK_MASK_CONST(0x3)
#define PMC_IMPL_SC7_STATUS_0_SC_STATE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define PMC_IMPL_SC7_STATUS_0_SC_STATE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define PMC_IMPL_SC7_STATUS_0_SC_STATE_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_SC7_STATUS_0_SC_STATE_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)
#define PMC_IMPL_SC7_STATUS_0_SC_STATE_INIT_ENUM                        NONE
#define PMC_IMPL_SC7_STATUS_0_SC_STATE_NONE                     _MK_ENUM_CONST(0)
#define PMC_IMPL_SC7_STATUS_0_SC_STATE_SC7                      _MK_ENUM_CONST(1)
#define PMC_IMPL_SC7_STATUS_0_SC_STATE_SC8                      _MK_ENUM_CONST(2)

#define PMC_IMPL_SC7_STATUS_0_SC7_FSM_BUSY_SHIFT                        _MK_SHIFT_CONST(2)
#define PMC_IMPL_SC7_STATUS_0_SC7_FSM_BUSY_FIELD                        _MK_FIELD_CONST(0x1, PMC_IMPL_SC7_STATUS_0_SC7_FSM_BUSY_SHIFT)
#define PMC_IMPL_SC7_STATUS_0_SC7_FSM_BUSY_RANGE                        2:2
#define PMC_IMPL_SC7_STATUS_0_SC7_FSM_BUSY_WOFFSET                      0x0
#define PMC_IMPL_SC7_STATUS_0_SC7_FSM_BUSY_DEFAULT                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_SC7_STATUS_0_SC7_FSM_BUSY_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define PMC_IMPL_SC7_STATUS_0_SC7_FSM_BUSY_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_SC7_STATUS_0_SC7_FSM_BUSY_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_SC7_STATUS_0_SC7_FSM_BUSY_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define PMC_IMPL_SC7_STATUS_0_SC7_FSM_BUSY_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)
#define PMC_IMPL_SC7_STATUS_0_SC7_FSM_BUSY_INIT_ENUM                    FALSE
#define PMC_IMPL_SC7_STATUS_0_SC7_FSM_BUSY_FALSE                        _MK_ENUM_CONST(0)
#define PMC_IMPL_SC7_STATUS_0_SC7_FSM_BUSY_TRUE                 _MK_ENUM_CONST(1)

#define PMC_IMPL_SC7_STATUS_0_SC7_WAIT_DPD_DIS_SHIFT                    _MK_SHIFT_CONST(3)
#define PMC_IMPL_SC7_STATUS_0_SC7_WAIT_DPD_DIS_FIELD                    _MK_FIELD_CONST(0x1, PMC_IMPL_SC7_STATUS_0_SC7_WAIT_DPD_DIS_SHIFT)
#define PMC_IMPL_SC7_STATUS_0_SC7_WAIT_DPD_DIS_RANGE                    3:3
#define PMC_IMPL_SC7_STATUS_0_SC7_WAIT_DPD_DIS_WOFFSET                  0x0
#define PMC_IMPL_SC7_STATUS_0_SC7_WAIT_DPD_DIS_DEFAULT                  _MK_MASK_CONST(0x0)
#define PMC_IMPL_SC7_STATUS_0_SC7_WAIT_DPD_DIS_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define PMC_IMPL_SC7_STATUS_0_SC7_WAIT_DPD_DIS_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define PMC_IMPL_SC7_STATUS_0_SC7_WAIT_DPD_DIS_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define PMC_IMPL_SC7_STATUS_0_SC7_WAIT_DPD_DIS_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_SC7_STATUS_0_SC7_WAIT_DPD_DIS_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)
#define PMC_IMPL_SC7_STATUS_0_SC7_WAIT_DPD_DIS_INIT_ENUM                        FALSE
#define PMC_IMPL_SC7_STATUS_0_SC7_WAIT_DPD_DIS_FALSE                    _MK_ENUM_CONST(0)
#define PMC_IMPL_SC7_STATUS_0_SC7_WAIT_DPD_DIS_TRUE                     _MK_ENUM_CONST(1)

#define PMC_IMPL_SC7_STATUS_0_PWRGOOD_ABS_SHIFT                 _MK_SHIFT_CONST(4)
#define PMC_IMPL_SC7_STATUS_0_PWRGOOD_ABS_FIELD                 _MK_FIELD_CONST(0x1, PMC_IMPL_SC7_STATUS_0_PWRGOOD_ABS_SHIFT)
#define PMC_IMPL_SC7_STATUS_0_PWRGOOD_ABS_RANGE                 4:4
#define PMC_IMPL_SC7_STATUS_0_PWRGOOD_ABS_WOFFSET                       0x0
#define PMC_IMPL_SC7_STATUS_0_PWRGOOD_ABS_DEFAULT                       _MK_MASK_CONST(0x1)
#define PMC_IMPL_SC7_STATUS_0_PWRGOOD_ABS_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define PMC_IMPL_SC7_STATUS_0_PWRGOOD_ABS_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define PMC_IMPL_SC7_STATUS_0_PWRGOOD_ABS_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define PMC_IMPL_SC7_STATUS_0_PWRGOOD_ABS_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_SC7_STATUS_0_PWRGOOD_ABS_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)
#define PMC_IMPL_SC7_STATUS_0_PWRGOOD_ABS_INIT_ENUM                     TRUE
#define PMC_IMPL_SC7_STATUS_0_PWRGOOD_ABS_FALSE                 _MK_ENUM_CONST(0)
#define PMC_IMPL_SC7_STATUS_0_PWRGOOD_ABS_TRUE                  _MK_ENUM_CONST(1)


// Register PMC_IMPL_SC8_FSM_INIT_0
#define PMC_IMPL_SC8_FSM_INIT_0                 _MK_ADDR_CONST(0x1c)
#define PMC_IMPL_SC8_FSM_INIT_0_SECURE                  0x0
#define PMC_IMPL_SC8_FSM_INIT_0_DUAL                    0x0
#define PMC_IMPL_SC8_FSM_INIT_0_SCR                     SC78_SCR_0
#define PMC_IMPL_SC8_FSM_INIT_0_WORD_COUNT                      0x1
#define PMC_IMPL_SC8_FSM_INIT_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define PMC_IMPL_SC8_FSM_INIT_0_RESET_MASK                      _MK_MASK_CONST(0x1)
#define PMC_IMPL_SC8_FSM_INIT_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define PMC_IMPL_SC8_FSM_INIT_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define PMC_IMPL_SC8_FSM_INIT_0_READ_MASK                       _MK_MASK_CONST(0x1)
#define PMC_IMPL_SC8_FSM_INIT_0_WRITE_MASK                      _MK_MASK_CONST(0x1)
#define PMC_IMPL_SC8_FSM_INIT_0_FSM_INIT_SHIFT                  _MK_SHIFT_CONST(0)
#define PMC_IMPL_SC8_FSM_INIT_0_FSM_INIT_FIELD                  _MK_FIELD_CONST(0x1, PMC_IMPL_SC8_FSM_INIT_0_FSM_INIT_SHIFT)
#define PMC_IMPL_SC8_FSM_INIT_0_FSM_INIT_RANGE                  0:0
#define PMC_IMPL_SC8_FSM_INIT_0_FSM_INIT_WOFFSET                        0x0
#define PMC_IMPL_SC8_FSM_INIT_0_FSM_INIT_DEFAULT                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_SC8_FSM_INIT_0_FSM_INIT_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define PMC_IMPL_SC8_FSM_INIT_0_FSM_INIT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_SC8_FSM_INIT_0_FSM_INIT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_SC8_FSM_INIT_0_FSM_INIT_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_SC8_FSM_INIT_0_FSM_INIT_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define PMC_IMPL_SC8_FSM_INIT_0_FSM_INIT_DONE                   _MK_ENUM_CONST(0)
#define PMC_IMPL_SC8_FSM_INIT_0_FSM_INIT_PENDING                        _MK_ENUM_CONST(1)


// Register PMC_IMPL_SC8_CONTROL_0
#define PMC_IMPL_SC8_CONTROL_0                  _MK_ADDR_CONST(0x20)
#define PMC_IMPL_SC8_CONTROL_0_SECURE                   0x0
#define PMC_IMPL_SC8_CONTROL_0_DUAL                     0x0
#define PMC_IMPL_SC8_CONTROL_0_SCR                      SC78_SCR_0
#define PMC_IMPL_SC8_CONTROL_0_WORD_COUNT                       0x1
#define PMC_IMPL_SC8_CONTROL_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_SC8_CONTROL_0_RESET_MASK                       _MK_MASK_CONST(0x1f)
#define PMC_IMPL_SC8_CONTROL_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_SC8_CONTROL_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define PMC_IMPL_SC8_CONTROL_0_READ_MASK                        _MK_MASK_CONST(0x1f)
#define PMC_IMPL_SC8_CONTROL_0_WRITE_MASK                       _MK_MASK_CONST(0x1f)
#define PMC_IMPL_SC8_CONTROL_0_REMOVE_RESET_SHIFT                       _MK_SHIFT_CONST(0)
#define PMC_IMPL_SC8_CONTROL_0_REMOVE_RESET_FIELD                       _MK_FIELD_CONST(0x1, PMC_IMPL_SC8_CONTROL_0_REMOVE_RESET_SHIFT)
#define PMC_IMPL_SC8_CONTROL_0_REMOVE_RESET_RANGE                       0:0
#define PMC_IMPL_SC8_CONTROL_0_REMOVE_RESET_WOFFSET                     0x0
#define PMC_IMPL_SC8_CONTROL_0_REMOVE_RESET_DEFAULT                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_SC8_CONTROL_0_REMOVE_RESET_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define PMC_IMPL_SC8_CONTROL_0_REMOVE_RESET_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define PMC_IMPL_SC8_CONTROL_0_REMOVE_RESET_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_SC8_CONTROL_0_REMOVE_RESET_PARITY_PROTECTION                   _MK_MASK_CONST(0x1)
#define PMC_IMPL_SC8_CONTROL_0_REMOVE_RESET_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define PMC_IMPL_SC8_CONTROL_0_REMOVE_RESET_DONE                        _MK_ENUM_CONST(0)
#define PMC_IMPL_SC8_CONTROL_0_REMOVE_RESET_PENDING                     _MK_ENUM_CONST(1)

#define PMC_IMPL_SC8_CONTROL_0_REMOVE_CLAMP_SHIFT                       _MK_SHIFT_CONST(1)
#define PMC_IMPL_SC8_CONTROL_0_REMOVE_CLAMP_FIELD                       _MK_FIELD_CONST(0x1, PMC_IMPL_SC8_CONTROL_0_REMOVE_CLAMP_SHIFT)
#define PMC_IMPL_SC8_CONTROL_0_REMOVE_CLAMP_RANGE                       1:1
#define PMC_IMPL_SC8_CONTROL_0_REMOVE_CLAMP_WOFFSET                     0x0
#define PMC_IMPL_SC8_CONTROL_0_REMOVE_CLAMP_DEFAULT                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_SC8_CONTROL_0_REMOVE_CLAMP_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define PMC_IMPL_SC8_CONTROL_0_REMOVE_CLAMP_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define PMC_IMPL_SC8_CONTROL_0_REMOVE_CLAMP_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_SC8_CONTROL_0_REMOVE_CLAMP_PARITY_PROTECTION                   _MK_MASK_CONST(0x1)
#define PMC_IMPL_SC8_CONTROL_0_REMOVE_CLAMP_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define PMC_IMPL_SC8_CONTROL_0_REMOVE_CLAMP_DONE                        _MK_ENUM_CONST(0)
#define PMC_IMPL_SC8_CONTROL_0_REMOVE_CLAMP_PENDING                     _MK_ENUM_CONST(1)

#define PMC_IMPL_SC8_CONTROL_0_REMOVE_EDPD_SHIFT                        _MK_SHIFT_CONST(2)
#define PMC_IMPL_SC8_CONTROL_0_REMOVE_EDPD_FIELD                        _MK_FIELD_CONST(0x1, PMC_IMPL_SC8_CONTROL_0_REMOVE_EDPD_SHIFT)
#define PMC_IMPL_SC8_CONTROL_0_REMOVE_EDPD_RANGE                        2:2
#define PMC_IMPL_SC8_CONTROL_0_REMOVE_EDPD_WOFFSET                      0x0
#define PMC_IMPL_SC8_CONTROL_0_REMOVE_EDPD_DEFAULT                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_SC8_CONTROL_0_REMOVE_EDPD_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define PMC_IMPL_SC8_CONTROL_0_REMOVE_EDPD_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_SC8_CONTROL_0_REMOVE_EDPD_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_SC8_CONTROL_0_REMOVE_EDPD_PARITY_PROTECTION                    _MK_MASK_CONST(0x1)
#define PMC_IMPL_SC8_CONTROL_0_REMOVE_EDPD_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)
#define PMC_IMPL_SC8_CONTROL_0_REMOVE_EDPD_DONE                 _MK_ENUM_CONST(0)
#define PMC_IMPL_SC8_CONTROL_0_REMOVE_EDPD_PENDING                      _MK_ENUM_CONST(1)

#define PMC_IMPL_SC8_CONTROL_0_REMOVE_SELDPD_SHIFT                      _MK_SHIFT_CONST(3)
#define PMC_IMPL_SC8_CONTROL_0_REMOVE_SELDPD_FIELD                      _MK_FIELD_CONST(0x1, PMC_IMPL_SC8_CONTROL_0_REMOVE_SELDPD_SHIFT)
#define PMC_IMPL_SC8_CONTROL_0_REMOVE_SELDPD_RANGE                      3:3
#define PMC_IMPL_SC8_CONTROL_0_REMOVE_SELDPD_WOFFSET                    0x0
#define PMC_IMPL_SC8_CONTROL_0_REMOVE_SELDPD_DEFAULT                    _MK_MASK_CONST(0x0)
#define PMC_IMPL_SC8_CONTROL_0_REMOVE_SELDPD_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define PMC_IMPL_SC8_CONTROL_0_REMOVE_SELDPD_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define PMC_IMPL_SC8_CONTROL_0_REMOVE_SELDPD_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define PMC_IMPL_SC8_CONTROL_0_REMOVE_SELDPD_PARITY_PROTECTION                  _MK_MASK_CONST(0x1)
#define PMC_IMPL_SC8_CONTROL_0_REMOVE_SELDPD_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define PMC_IMPL_SC8_CONTROL_0_REMOVE_SELDPD_DONE                       _MK_ENUM_CONST(0)
#define PMC_IMPL_SC8_CONTROL_0_REMOVE_SELDPD_PENDING                    _MK_ENUM_CONST(1)

#define PMC_IMPL_SC8_CONTROL_0_REMOVE_SLEEP_SHIFT                       _MK_SHIFT_CONST(4)
#define PMC_IMPL_SC8_CONTROL_0_REMOVE_SLEEP_FIELD                       _MK_FIELD_CONST(0x1, PMC_IMPL_SC8_CONTROL_0_REMOVE_SLEEP_SHIFT)
#define PMC_IMPL_SC8_CONTROL_0_REMOVE_SLEEP_RANGE                       4:4
#define PMC_IMPL_SC8_CONTROL_0_REMOVE_SLEEP_WOFFSET                     0x0
#define PMC_IMPL_SC8_CONTROL_0_REMOVE_SLEEP_DEFAULT                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_SC8_CONTROL_0_REMOVE_SLEEP_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define PMC_IMPL_SC8_CONTROL_0_REMOVE_SLEEP_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define PMC_IMPL_SC8_CONTROL_0_REMOVE_SLEEP_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_SC8_CONTROL_0_REMOVE_SLEEP_PARITY_PROTECTION                   _MK_MASK_CONST(0x1)
#define PMC_IMPL_SC8_CONTROL_0_REMOVE_SLEEP_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define PMC_IMPL_SC8_CONTROL_0_REMOVE_SLEEP_DONE                        _MK_ENUM_CONST(0)
#define PMC_IMPL_SC8_CONTROL_0_REMOVE_SLEEP_PENDING                     _MK_ENUM_CONST(1)


// Register PMC_IMPL_RETENTION_CONTROL_0
#define PMC_IMPL_RETENTION_CONTROL_0                    _MK_ADDR_CONST(0x24)
#define PMC_IMPL_RETENTION_CONTROL_0_SECURE                     0x0
#define PMC_IMPL_RETENTION_CONTROL_0_DUAL                       0x0
#define PMC_IMPL_RETENTION_CONTROL_0_SCR                        SC78_SCR_0
#define PMC_IMPL_RETENTION_CONTROL_0_WORD_COUNT                         0x1
#define PMC_IMPL_RETENTION_CONTROL_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define PMC_IMPL_RETENTION_CONTROL_0_RESET_MASK                         _MK_MASK_CONST(0x1ff)
#define PMC_IMPL_RETENTION_CONTROL_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_RETENTION_CONTROL_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define PMC_IMPL_RETENTION_CONTROL_0_READ_MASK                  _MK_MASK_CONST(0x1ff)
#define PMC_IMPL_RETENTION_CONTROL_0_WRITE_MASK                         _MK_MASK_CONST(0x1ff)
#define PMC_IMPL_RETENTION_CONTROL_0_RAIL_RET_EXIT_DELAY_SHIFT                  _MK_SHIFT_CONST(0)
#define PMC_IMPL_RETENTION_CONTROL_0_RAIL_RET_EXIT_DELAY_FIELD                  _MK_FIELD_CONST(0xff, PMC_IMPL_RETENTION_CONTROL_0_RAIL_RET_EXIT_DELAY_SHIFT)
#define PMC_IMPL_RETENTION_CONTROL_0_RAIL_RET_EXIT_DELAY_RANGE                  7:0
#define PMC_IMPL_RETENTION_CONTROL_0_RAIL_RET_EXIT_DELAY_WOFFSET                        0x0
#define PMC_IMPL_RETENTION_CONTROL_0_RAIL_RET_EXIT_DELAY_DEFAULT                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_RETENTION_CONTROL_0_RAIL_RET_EXIT_DELAY_DEFAULT_MASK                   _MK_MASK_CONST(0xff)
#define PMC_IMPL_RETENTION_CONTROL_0_RAIL_RET_EXIT_DELAY_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_RETENTION_CONTROL_0_RAIL_RET_EXIT_DELAY_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_RETENTION_CONTROL_0_RAIL_RET_EXIT_DELAY_PARITY_PROTECTION                      _MK_MASK_CONST(0x1)
#define PMC_IMPL_RETENTION_CONTROL_0_RAIL_RET_EXIT_DELAY_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)

#define PMC_IMPL_RETENTION_CONTROL_0_GPIO_AO_RET_EN_SHIFT                       _MK_SHIFT_CONST(8)
#define PMC_IMPL_RETENTION_CONTROL_0_GPIO_AO_RET_EN_FIELD                       _MK_FIELD_CONST(0x1, PMC_IMPL_RETENTION_CONTROL_0_GPIO_AO_RET_EN_SHIFT)
#define PMC_IMPL_RETENTION_CONTROL_0_GPIO_AO_RET_EN_RANGE                       8:8
#define PMC_IMPL_RETENTION_CONTROL_0_GPIO_AO_RET_EN_WOFFSET                     0x0
#define PMC_IMPL_RETENTION_CONTROL_0_GPIO_AO_RET_EN_DEFAULT                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_RETENTION_CONTROL_0_GPIO_AO_RET_EN_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define PMC_IMPL_RETENTION_CONTROL_0_GPIO_AO_RET_EN_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define PMC_IMPL_RETENTION_CONTROL_0_GPIO_AO_RET_EN_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_RETENTION_CONTROL_0_GPIO_AO_RET_EN_PARITY_PROTECTION                   _MK_MASK_CONST(0x1)
#define PMC_IMPL_RETENTION_CONTROL_0_GPIO_AO_RET_EN_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define PMC_IMPL_RETENTION_CONTROL_0_GPIO_AO_RET_EN_DISABLE                     _MK_ENUM_CONST(0)
#define PMC_IMPL_RETENTION_CONTROL_0_GPIO_AO_RET_EN_ENABLE                      _MK_ENUM_CONST(1)


// Register PMC_IMPL_SC7_DEBUG_CTRL_0
#define PMC_IMPL_SC7_DEBUG_CTRL_0                       _MK_ADDR_CONST(0x28)
#define PMC_IMPL_SC7_DEBUG_CTRL_0_SECURE                        0x0
#define PMC_IMPL_SC7_DEBUG_CTRL_0_DUAL                  0x0
#define PMC_IMPL_SC7_DEBUG_CTRL_0_SCR                   SC7_DEBUG_SCR_0
#define PMC_IMPL_SC7_DEBUG_CTRL_0_WORD_COUNT                    0x1
#define PMC_IMPL_SC7_DEBUG_CTRL_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_SC7_DEBUG_CTRL_0_RESET_MASK                    _MK_MASK_CONST(0x1ff)
#define PMC_IMPL_SC7_DEBUG_CTRL_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_SC7_DEBUG_CTRL_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define PMC_IMPL_SC7_DEBUG_CTRL_0_READ_MASK                     _MK_MASK_CONST(0x1ff)
#define PMC_IMPL_SC7_DEBUG_CTRL_0_WRITE_MASK                    _MK_MASK_CONST(0x1ff)
#define PMC_IMPL_SC7_DEBUG_CTRL_0_GLITCH_FREE_CLKEN_SHIFT                       _MK_SHIFT_CONST(8)
#define PMC_IMPL_SC7_DEBUG_CTRL_0_GLITCH_FREE_CLKEN_FIELD                       _MK_FIELD_CONST(0x1, PMC_IMPL_SC7_DEBUG_CTRL_0_GLITCH_FREE_CLKEN_SHIFT)
#define PMC_IMPL_SC7_DEBUG_CTRL_0_GLITCH_FREE_CLKEN_RANGE                       8:8
#define PMC_IMPL_SC7_DEBUG_CTRL_0_GLITCH_FREE_CLKEN_WOFFSET                     0x0
#define PMC_IMPL_SC7_DEBUG_CTRL_0_GLITCH_FREE_CLKEN_DEFAULT                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_SC7_DEBUG_CTRL_0_GLITCH_FREE_CLKEN_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define PMC_IMPL_SC7_DEBUG_CTRL_0_GLITCH_FREE_CLKEN_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define PMC_IMPL_SC7_DEBUG_CTRL_0_GLITCH_FREE_CLKEN_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_SC7_DEBUG_CTRL_0_GLITCH_FREE_CLKEN_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_SC7_DEBUG_CTRL_0_GLITCH_FREE_CLKEN_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define PMC_IMPL_SC7_DEBUG_CTRL_0_GLITCH_FREE_CLKEN_INIT_ENUM                   DISABLE
#define PMC_IMPL_SC7_DEBUG_CTRL_0_GLITCH_FREE_CLKEN_DISABLE                     _MK_ENUM_CONST(0)
#define PMC_IMPL_SC7_DEBUG_CTRL_0_GLITCH_FREE_CLKEN_ENABLE                      _MK_ENUM_CONST(1)

#define PMC_IMPL_SC7_DEBUG_CTRL_0_DBG_SLEEP_SKIP_SHIFT                  _MK_SHIFT_CONST(7)
#define PMC_IMPL_SC7_DEBUG_CTRL_0_DBG_SLEEP_SKIP_FIELD                  _MK_FIELD_CONST(0x1, PMC_IMPL_SC7_DEBUG_CTRL_0_DBG_SLEEP_SKIP_SHIFT)
#define PMC_IMPL_SC7_DEBUG_CTRL_0_DBG_SLEEP_SKIP_RANGE                  7:7
#define PMC_IMPL_SC7_DEBUG_CTRL_0_DBG_SLEEP_SKIP_WOFFSET                        0x0
#define PMC_IMPL_SC7_DEBUG_CTRL_0_DBG_SLEEP_SKIP_DEFAULT                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_SC7_DEBUG_CTRL_0_DBG_SLEEP_SKIP_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define PMC_IMPL_SC7_DEBUG_CTRL_0_DBG_SLEEP_SKIP_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_SC7_DEBUG_CTRL_0_DBG_SLEEP_SKIP_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_SC7_DEBUG_CTRL_0_DBG_SLEEP_SKIP_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_SC7_DEBUG_CTRL_0_DBG_SLEEP_SKIP_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define PMC_IMPL_SC7_DEBUG_CTRL_0_DBG_SLEEP_SKIP_INIT_ENUM                      DISABLE
#define PMC_IMPL_SC7_DEBUG_CTRL_0_DBG_SLEEP_SKIP_DISABLE                        _MK_ENUM_CONST(0)
#define PMC_IMPL_SC7_DEBUG_CTRL_0_DBG_SLEEP_SKIP_ENABLE                 _MK_ENUM_CONST(1)

#define PMC_IMPL_SC7_DEBUG_CTRL_0_DFD_CLAMP_OVERRIDE_SHIFT                      _MK_SHIFT_CONST(6)
#define PMC_IMPL_SC7_DEBUG_CTRL_0_DFD_CLAMP_OVERRIDE_FIELD                      _MK_FIELD_CONST(0x1, PMC_IMPL_SC7_DEBUG_CTRL_0_DFD_CLAMP_OVERRIDE_SHIFT)
#define PMC_IMPL_SC7_DEBUG_CTRL_0_DFD_CLAMP_OVERRIDE_RANGE                      6:6
#define PMC_IMPL_SC7_DEBUG_CTRL_0_DFD_CLAMP_OVERRIDE_WOFFSET                    0x0
#define PMC_IMPL_SC7_DEBUG_CTRL_0_DFD_CLAMP_OVERRIDE_DEFAULT                    _MK_MASK_CONST(0x0)
#define PMC_IMPL_SC7_DEBUG_CTRL_0_DFD_CLAMP_OVERRIDE_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define PMC_IMPL_SC7_DEBUG_CTRL_0_DFD_CLAMP_OVERRIDE_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define PMC_IMPL_SC7_DEBUG_CTRL_0_DFD_CLAMP_OVERRIDE_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define PMC_IMPL_SC7_DEBUG_CTRL_0_DFD_CLAMP_OVERRIDE_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define PMC_IMPL_SC7_DEBUG_CTRL_0_DFD_CLAMP_OVERRIDE_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)

#define PMC_IMPL_SC7_DEBUG_CTRL_0_DBGRST_OVR_SHIFT                      _MK_SHIFT_CONST(5)
#define PMC_IMPL_SC7_DEBUG_CTRL_0_DBGRST_OVR_FIELD                      _MK_FIELD_CONST(0x1, PMC_IMPL_SC7_DEBUG_CTRL_0_DBGRST_OVR_SHIFT)
#define PMC_IMPL_SC7_DEBUG_CTRL_0_DBGRST_OVR_RANGE                      5:5
#define PMC_IMPL_SC7_DEBUG_CTRL_0_DBGRST_OVR_WOFFSET                    0x0
#define PMC_IMPL_SC7_DEBUG_CTRL_0_DBGRST_OVR_DEFAULT                    _MK_MASK_CONST(0x0)
#define PMC_IMPL_SC7_DEBUG_CTRL_0_DBGRST_OVR_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define PMC_IMPL_SC7_DEBUG_CTRL_0_DBGRST_OVR_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define PMC_IMPL_SC7_DEBUG_CTRL_0_DBGRST_OVR_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define PMC_IMPL_SC7_DEBUG_CTRL_0_DBGRST_OVR_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define PMC_IMPL_SC7_DEBUG_CTRL_0_DBGRST_OVR_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)

#define PMC_IMPL_SC7_DEBUG_CTRL_0_RESET_DEBUG_SHIFT                     _MK_SHIFT_CONST(4)
#define PMC_IMPL_SC7_DEBUG_CTRL_0_RESET_DEBUG_FIELD                     _MK_FIELD_CONST(0x1, PMC_IMPL_SC7_DEBUG_CTRL_0_RESET_DEBUG_SHIFT)
#define PMC_IMPL_SC7_DEBUG_CTRL_0_RESET_DEBUG_RANGE                     4:4
#define PMC_IMPL_SC7_DEBUG_CTRL_0_RESET_DEBUG_WOFFSET                   0x0
#define PMC_IMPL_SC7_DEBUG_CTRL_0_RESET_DEBUG_DEFAULT                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_SC7_DEBUG_CTRL_0_RESET_DEBUG_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define PMC_IMPL_SC7_DEBUG_CTRL_0_RESET_DEBUG_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_SC7_DEBUG_CTRL_0_RESET_DEBUG_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_SC7_DEBUG_CTRL_0_RESET_DEBUG_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define PMC_IMPL_SC7_DEBUG_CTRL_0_RESET_DEBUG_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define PMC_IMPL_SC7_DEBUG_CTRL_0_RESET_DEBUG_INIT_ENUM                 OFF
#define PMC_IMPL_SC7_DEBUG_CTRL_0_RESET_DEBUG_OFF                       _MK_ENUM_CONST(0)
#define PMC_IMPL_SC7_DEBUG_CTRL_0_RESET_DEBUG_ON                        _MK_ENUM_CONST(1)

#define PMC_IMPL_SC7_DEBUG_CTRL_0_DPD_ENABLE_DEBUG_SHIFT                        _MK_SHIFT_CONST(3)
#define PMC_IMPL_SC7_DEBUG_CTRL_0_DPD_ENABLE_DEBUG_FIELD                        _MK_FIELD_CONST(0x1, PMC_IMPL_SC7_DEBUG_CTRL_0_DPD_ENABLE_DEBUG_SHIFT)
#define PMC_IMPL_SC7_DEBUG_CTRL_0_DPD_ENABLE_DEBUG_RANGE                        3:3
#define PMC_IMPL_SC7_DEBUG_CTRL_0_DPD_ENABLE_DEBUG_WOFFSET                      0x0
#define PMC_IMPL_SC7_DEBUG_CTRL_0_DPD_ENABLE_DEBUG_DEFAULT                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_SC7_DEBUG_CTRL_0_DPD_ENABLE_DEBUG_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define PMC_IMPL_SC7_DEBUG_CTRL_0_DPD_ENABLE_DEBUG_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_SC7_DEBUG_CTRL_0_DPD_ENABLE_DEBUG_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_SC7_DEBUG_CTRL_0_DPD_ENABLE_DEBUG_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define PMC_IMPL_SC7_DEBUG_CTRL_0_DPD_ENABLE_DEBUG_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)
#define PMC_IMPL_SC7_DEBUG_CTRL_0_DPD_ENABLE_DEBUG_INIT_ENUM                    OFF
#define PMC_IMPL_SC7_DEBUG_CTRL_0_DPD_ENABLE_DEBUG_OFF                  _MK_ENUM_CONST(0)
#define PMC_IMPL_SC7_DEBUG_CTRL_0_DPD_ENABLE_DEBUG_ON                   _MK_ENUM_CONST(1)

#define PMC_IMPL_SC7_DEBUG_CTRL_0_MAIN_CLAMP_DEBUG_SHIFT                        _MK_SHIFT_CONST(2)
#define PMC_IMPL_SC7_DEBUG_CTRL_0_MAIN_CLAMP_DEBUG_FIELD                        _MK_FIELD_CONST(0x1, PMC_IMPL_SC7_DEBUG_CTRL_0_MAIN_CLAMP_DEBUG_SHIFT)
#define PMC_IMPL_SC7_DEBUG_CTRL_0_MAIN_CLAMP_DEBUG_RANGE                        2:2
#define PMC_IMPL_SC7_DEBUG_CTRL_0_MAIN_CLAMP_DEBUG_WOFFSET                      0x0
#define PMC_IMPL_SC7_DEBUG_CTRL_0_MAIN_CLAMP_DEBUG_DEFAULT                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_SC7_DEBUG_CTRL_0_MAIN_CLAMP_DEBUG_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define PMC_IMPL_SC7_DEBUG_CTRL_0_MAIN_CLAMP_DEBUG_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_SC7_DEBUG_CTRL_0_MAIN_CLAMP_DEBUG_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_SC7_DEBUG_CTRL_0_MAIN_CLAMP_DEBUG_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define PMC_IMPL_SC7_DEBUG_CTRL_0_MAIN_CLAMP_DEBUG_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)
#define PMC_IMPL_SC7_DEBUG_CTRL_0_MAIN_CLAMP_DEBUG_INIT_ENUM                    OFF
#define PMC_IMPL_SC7_DEBUG_CTRL_0_MAIN_CLAMP_DEBUG_OFF                  _MK_ENUM_CONST(0)
#define PMC_IMPL_SC7_DEBUG_CTRL_0_MAIN_CLAMP_DEBUG_ON                   _MK_ENUM_CONST(1)

#define PMC_IMPL_SC7_DEBUG_CTRL_0_OP_SHIFT                      _MK_SHIFT_CONST(0)
#define PMC_IMPL_SC7_DEBUG_CTRL_0_OP_FIELD                      _MK_FIELD_CONST(0x3, PMC_IMPL_SC7_DEBUG_CTRL_0_OP_SHIFT)
#define PMC_IMPL_SC7_DEBUG_CTRL_0_OP_RANGE                      1:0
#define PMC_IMPL_SC7_DEBUG_CTRL_0_OP_WOFFSET                    0x0
#define PMC_IMPL_SC7_DEBUG_CTRL_0_OP_DEFAULT                    _MK_MASK_CONST(0x0)
#define PMC_IMPL_SC7_DEBUG_CTRL_0_OP_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
#define PMC_IMPL_SC7_DEBUG_CTRL_0_OP_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define PMC_IMPL_SC7_DEBUG_CTRL_0_OP_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define PMC_IMPL_SC7_DEBUG_CTRL_0_OP_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define PMC_IMPL_SC7_DEBUG_CTRL_0_OP_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define PMC_IMPL_SC7_DEBUG_CTRL_0_OP_INIT_ENUM                  NONE
#define PMC_IMPL_SC7_DEBUG_CTRL_0_OP_NONE                       _MK_ENUM_CONST(0)
#define PMC_IMPL_SC7_DEBUG_CTRL_0_OP_FORCE_ON                   _MK_ENUM_CONST(1)
#define PMC_IMPL_SC7_DEBUG_CTRL_0_OP_FORCE_OFF                  _MK_ENUM_CONST(2)


// Register PMC_IMPL_PWRGOOD_TIMER_0
#define PMC_IMPL_PWRGOOD_TIMER_0                        _MK_ADDR_CONST(0x2c)
#define PMC_IMPL_PWRGOOD_TIMER_0_SECURE                         0x0
#define PMC_IMPL_PWRGOOD_TIMER_0_DUAL                   0x0
#define PMC_IMPL_PWRGOOD_TIMER_0_SCR                    PWRGOOD_TIMER_SCR_0
#define PMC_IMPL_PWRGOOD_TIMER_0_WORD_COUNT                     0x1
#define PMC_IMPL_PWRGOOD_TIMER_0_RESET_VAL                      _MK_MASK_CONST(0x3f00007f)
#define PMC_IMPL_PWRGOOD_TIMER_0_RESET_MASK                     _MK_MASK_CONST(0xffffffff)
#define PMC_IMPL_PWRGOOD_TIMER_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define PMC_IMPL_PWRGOOD_TIMER_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_PWRGOOD_TIMER_0_READ_MASK                      _MK_MASK_CONST(0xffffffff)
#define PMC_IMPL_PWRGOOD_TIMER_0_WRITE_MASK                     _MK_MASK_CONST(0xffffffff)
#define PMC_IMPL_PWRGOOD_TIMER_0_PWRGOOD_SHIFT                  _MK_SHIFT_CONST(0)
#define PMC_IMPL_PWRGOOD_TIMER_0_PWRGOOD_FIELD                  _MK_FIELD_CONST(0xffff, PMC_IMPL_PWRGOOD_TIMER_0_PWRGOOD_SHIFT)
#define PMC_IMPL_PWRGOOD_TIMER_0_PWRGOOD_RANGE                  15:0
#define PMC_IMPL_PWRGOOD_TIMER_0_PWRGOOD_WOFFSET                        0x0
#define PMC_IMPL_PWRGOOD_TIMER_0_PWRGOOD_DEFAULT                        _MK_MASK_CONST(0x7f)
#define PMC_IMPL_PWRGOOD_TIMER_0_PWRGOOD_DEFAULT_MASK                   _MK_MASK_CONST(0xffff)
#define PMC_IMPL_PWRGOOD_TIMER_0_PWRGOOD_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_PWRGOOD_TIMER_0_PWRGOOD_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_PWRGOOD_TIMER_0_PWRGOOD_PARITY_PROTECTION                      _MK_MASK_CONST(0x1)
#define PMC_IMPL_PWRGOOD_TIMER_0_PWRGOOD_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)

#define PMC_IMPL_PWRGOOD_TIMER_0_OSC_POSTPWR_SHIFT                      _MK_SHIFT_CONST(16)
#define PMC_IMPL_PWRGOOD_TIMER_0_OSC_POSTPWR_FIELD                      _MK_FIELD_CONST(0xff, PMC_IMPL_PWRGOOD_TIMER_0_OSC_POSTPWR_SHIFT)
#define PMC_IMPL_PWRGOOD_TIMER_0_OSC_POSTPWR_RANGE                      23:16
#define PMC_IMPL_PWRGOOD_TIMER_0_OSC_POSTPWR_WOFFSET                    0x0
#define PMC_IMPL_PWRGOOD_TIMER_0_OSC_POSTPWR_DEFAULT                    _MK_MASK_CONST(0x0)
#define PMC_IMPL_PWRGOOD_TIMER_0_OSC_POSTPWR_DEFAULT_MASK                       _MK_MASK_CONST(0xff)
#define PMC_IMPL_PWRGOOD_TIMER_0_OSC_POSTPWR_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define PMC_IMPL_PWRGOOD_TIMER_0_OSC_POSTPWR_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define PMC_IMPL_PWRGOOD_TIMER_0_OSC_POSTPWR_PARITY_PROTECTION                  _MK_MASK_CONST(0x1)
#define PMC_IMPL_PWRGOOD_TIMER_0_OSC_POSTPWR_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)

#define PMC_IMPL_PWRGOOD_TIMER_0_OSC_PREPWR_SHIFT                       _MK_SHIFT_CONST(24)
#define PMC_IMPL_PWRGOOD_TIMER_0_OSC_PREPWR_FIELD                       _MK_FIELD_CONST(0xff, PMC_IMPL_PWRGOOD_TIMER_0_OSC_PREPWR_SHIFT)
#define PMC_IMPL_PWRGOOD_TIMER_0_OSC_PREPWR_RANGE                       31:24
#define PMC_IMPL_PWRGOOD_TIMER_0_OSC_PREPWR_WOFFSET                     0x0
#define PMC_IMPL_PWRGOOD_TIMER_0_OSC_PREPWR_DEFAULT                     _MK_MASK_CONST(0x3f)
#define PMC_IMPL_PWRGOOD_TIMER_0_OSC_PREPWR_DEFAULT_MASK                        _MK_MASK_CONST(0xff)
#define PMC_IMPL_PWRGOOD_TIMER_0_OSC_PREPWR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define PMC_IMPL_PWRGOOD_TIMER_0_OSC_PREPWR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_PWRGOOD_TIMER_0_OSC_PREPWR_PARITY_PROTECTION                   _MK_MASK_CONST(0x1)
#define PMC_IMPL_PWRGOOD_TIMER_0_OSC_PREPWR_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)


// Register PMC_IMPL_BLINK_TIMER_0
#define PMC_IMPL_BLINK_TIMER_0                  _MK_ADDR_CONST(0x30)
#define PMC_IMPL_BLINK_TIMER_0_SECURE                   0x0
#define PMC_IMPL_BLINK_TIMER_0_DUAL                     0x0
#define PMC_IMPL_BLINK_TIMER_0_SCR                      BLINK_TIMER_SCR_0
#define PMC_IMPL_BLINK_TIMER_0_WORD_COUNT                       0x1
#define PMC_IMPL_BLINK_TIMER_0_RESET_VAL                        _MK_MASK_CONST(0xffffffff)
#define PMC_IMPL_BLINK_TIMER_0_RESET_MASK                       _MK_MASK_CONST(0xffffffff)
#define PMC_IMPL_BLINK_TIMER_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_BLINK_TIMER_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define PMC_IMPL_BLINK_TIMER_0_READ_MASK                        _MK_MASK_CONST(0xffffffff)
#define PMC_IMPL_BLINK_TIMER_0_WRITE_MASK                       _MK_MASK_CONST(0xffffffff)
#define PMC_IMPL_BLINK_TIMER_0_DATA_ON_SHIFT                    _MK_SHIFT_CONST(0)
#define PMC_IMPL_BLINK_TIMER_0_DATA_ON_FIELD                    _MK_FIELD_CONST(0x7fff, PMC_IMPL_BLINK_TIMER_0_DATA_ON_SHIFT)
#define PMC_IMPL_BLINK_TIMER_0_DATA_ON_RANGE                    14:0
#define PMC_IMPL_BLINK_TIMER_0_DATA_ON_WOFFSET                  0x0
#define PMC_IMPL_BLINK_TIMER_0_DATA_ON_DEFAULT                  _MK_MASK_CONST(0x7fff)
#define PMC_IMPL_BLINK_TIMER_0_DATA_ON_DEFAULT_MASK                     _MK_MASK_CONST(0x7fff)
#define PMC_IMPL_BLINK_TIMER_0_DATA_ON_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define PMC_IMPL_BLINK_TIMER_0_DATA_ON_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define PMC_IMPL_BLINK_TIMER_0_DATA_ON_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_BLINK_TIMER_0_DATA_ON_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)

#define PMC_IMPL_BLINK_TIMER_0_FORCE_BLINK_SHIFT                        _MK_SHIFT_CONST(15)
#define PMC_IMPL_BLINK_TIMER_0_FORCE_BLINK_FIELD                        _MK_FIELD_CONST(0x1, PMC_IMPL_BLINK_TIMER_0_FORCE_BLINK_SHIFT)
#define PMC_IMPL_BLINK_TIMER_0_FORCE_BLINK_RANGE                        15:15
#define PMC_IMPL_BLINK_TIMER_0_FORCE_BLINK_WOFFSET                      0x0
#define PMC_IMPL_BLINK_TIMER_0_FORCE_BLINK_DEFAULT                      _MK_MASK_CONST(0x1)
#define PMC_IMPL_BLINK_TIMER_0_FORCE_BLINK_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define PMC_IMPL_BLINK_TIMER_0_FORCE_BLINK_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_BLINK_TIMER_0_FORCE_BLINK_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_BLINK_TIMER_0_FORCE_BLINK_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define PMC_IMPL_BLINK_TIMER_0_FORCE_BLINK_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define PMC_IMPL_BLINK_TIMER_0_DATA_OFF_SHIFT                   _MK_SHIFT_CONST(16)
#define PMC_IMPL_BLINK_TIMER_0_DATA_OFF_FIELD                   _MK_FIELD_CONST(0xffff, PMC_IMPL_BLINK_TIMER_0_DATA_OFF_SHIFT)
#define PMC_IMPL_BLINK_TIMER_0_DATA_OFF_RANGE                   31:16
#define PMC_IMPL_BLINK_TIMER_0_DATA_OFF_WOFFSET                 0x0
#define PMC_IMPL_BLINK_TIMER_0_DATA_OFF_DEFAULT                 _MK_MASK_CONST(0xffff)
#define PMC_IMPL_BLINK_TIMER_0_DATA_OFF_DEFAULT_MASK                    _MK_MASK_CONST(0xffff)
#define PMC_IMPL_BLINK_TIMER_0_DATA_OFF_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_BLINK_TIMER_0_DATA_OFF_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define PMC_IMPL_BLINK_TIMER_0_DATA_OFF_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define PMC_IMPL_BLINK_TIMER_0_DATA_OFF_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)


// Register PMC_IMPL_NO_IOPOWER_0
#define PMC_IMPL_NO_IOPOWER_0                   _MK_ADDR_CONST(0x34)
#define PMC_IMPL_NO_IOPOWER_0_SECURE                    0x0
#define PMC_IMPL_NO_IOPOWER_0_DUAL                      0x0
#define PMC_IMPL_NO_IOPOWER_0_SCR                       NO_IOPOWER_SCR_0
#define PMC_IMPL_NO_IOPOWER_0_WORD_COUNT                        0x1
#define PMC_IMPL_NO_IOPOWER_0_RESET_VAL                         _MK_MASK_CONST(0x0)
#define PMC_IMPL_NO_IOPOWER_0_RESET_MASK                        _MK_MASK_CONST(0x448467d)
#define PMC_IMPL_NO_IOPOWER_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define PMC_IMPL_NO_IOPOWER_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_NO_IOPOWER_0_READ_MASK                         _MK_MASK_CONST(0x448467d)
#define PMC_IMPL_NO_IOPOWER_0_WRITE_MASK                        _MK_MASK_CONST(0x448467d)
#define PMC_IMPL_NO_IOPOWER_0_SYS_SHIFT                 _MK_SHIFT_CONST(0)
#define PMC_IMPL_NO_IOPOWER_0_SYS_FIELD                 _MK_FIELD_CONST(0x1, PMC_IMPL_NO_IOPOWER_0_SYS_SHIFT)
#define PMC_IMPL_NO_IOPOWER_0_SYS_RANGE                 0:0
#define PMC_IMPL_NO_IOPOWER_0_SYS_WOFFSET                       0x0
#define PMC_IMPL_NO_IOPOWER_0_SYS_DEFAULT                       _MK_MASK_CONST(0x0)
#define PMC_IMPL_NO_IOPOWER_0_SYS_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define PMC_IMPL_NO_IOPOWER_0_SYS_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define PMC_IMPL_NO_IOPOWER_0_SYS_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define PMC_IMPL_NO_IOPOWER_0_SYS_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_NO_IOPOWER_0_SYS_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)
#define PMC_IMPL_NO_IOPOWER_0_SYS_INIT_ENUM                     DISABLE
#define PMC_IMPL_NO_IOPOWER_0_SYS_DISABLE                       _MK_ENUM_CONST(0)
#define PMC_IMPL_NO_IOPOWER_0_SYS_ENABLE                        _MK_ENUM_CONST(1)

#define PMC_IMPL_NO_IOPOWER_0_UART_SHIFT                        _MK_SHIFT_CONST(2)
#define PMC_IMPL_NO_IOPOWER_0_UART_FIELD                        _MK_FIELD_CONST(0x1, PMC_IMPL_NO_IOPOWER_0_UART_SHIFT)
#define PMC_IMPL_NO_IOPOWER_0_UART_RANGE                        2:2
#define PMC_IMPL_NO_IOPOWER_0_UART_WOFFSET                      0x0
#define PMC_IMPL_NO_IOPOWER_0_UART_DEFAULT                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_NO_IOPOWER_0_UART_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define PMC_IMPL_NO_IOPOWER_0_UART_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_NO_IOPOWER_0_UART_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_NO_IOPOWER_0_UART_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define PMC_IMPL_NO_IOPOWER_0_UART_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)
#define PMC_IMPL_NO_IOPOWER_0_UART_INIT_ENUM                    DISABLE
#define PMC_IMPL_NO_IOPOWER_0_UART_DISABLE                      _MK_ENUM_CONST(0)
#define PMC_IMPL_NO_IOPOWER_0_UART_ENABLE                       _MK_ENUM_CONST(1)

#define PMC_IMPL_NO_IOPOWER_0_CONN_SHIFT                        _MK_SHIFT_CONST(3)
#define PMC_IMPL_NO_IOPOWER_0_CONN_FIELD                        _MK_FIELD_CONST(0x1, PMC_IMPL_NO_IOPOWER_0_CONN_SHIFT)
#define PMC_IMPL_NO_IOPOWER_0_CONN_RANGE                        3:3
#define PMC_IMPL_NO_IOPOWER_0_CONN_WOFFSET                      0x0
#define PMC_IMPL_NO_IOPOWER_0_CONN_DEFAULT                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_NO_IOPOWER_0_CONN_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define PMC_IMPL_NO_IOPOWER_0_CONN_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_NO_IOPOWER_0_CONN_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_NO_IOPOWER_0_CONN_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define PMC_IMPL_NO_IOPOWER_0_CONN_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)
#define PMC_IMPL_NO_IOPOWER_0_CONN_INIT_ENUM                    DISABLE
#define PMC_IMPL_NO_IOPOWER_0_CONN_DISABLE                      _MK_ENUM_CONST(0)
#define PMC_IMPL_NO_IOPOWER_0_CONN_ENABLE                       _MK_ENUM_CONST(1)

#define PMC_IMPL_NO_IOPOWER_0_EDP_SHIFT                 _MK_SHIFT_CONST(4)
#define PMC_IMPL_NO_IOPOWER_0_EDP_FIELD                 _MK_FIELD_CONST(0x1, PMC_IMPL_NO_IOPOWER_0_EDP_SHIFT)
#define PMC_IMPL_NO_IOPOWER_0_EDP_RANGE                 4:4
#define PMC_IMPL_NO_IOPOWER_0_EDP_WOFFSET                       0x0
#define PMC_IMPL_NO_IOPOWER_0_EDP_DEFAULT                       _MK_MASK_CONST(0x0)
#define PMC_IMPL_NO_IOPOWER_0_EDP_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define PMC_IMPL_NO_IOPOWER_0_EDP_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define PMC_IMPL_NO_IOPOWER_0_EDP_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define PMC_IMPL_NO_IOPOWER_0_EDP_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_NO_IOPOWER_0_EDP_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)
#define PMC_IMPL_NO_IOPOWER_0_EDP_INIT_ENUM                     DISABLE
#define PMC_IMPL_NO_IOPOWER_0_EDP_DISABLE                       _MK_ENUM_CONST(0)
#define PMC_IMPL_NO_IOPOWER_0_EDP_ENABLE                        _MK_ENUM_CONST(1)

#define PMC_IMPL_NO_IOPOWER_0_AUDIO_SHIFT                       _MK_SHIFT_CONST(5)
#define PMC_IMPL_NO_IOPOWER_0_AUDIO_FIELD                       _MK_FIELD_CONST(0x1, PMC_IMPL_NO_IOPOWER_0_AUDIO_SHIFT)
#define PMC_IMPL_NO_IOPOWER_0_AUDIO_RANGE                       5:5
#define PMC_IMPL_NO_IOPOWER_0_AUDIO_WOFFSET                     0x0
#define PMC_IMPL_NO_IOPOWER_0_AUDIO_DEFAULT                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_NO_IOPOWER_0_AUDIO_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define PMC_IMPL_NO_IOPOWER_0_AUDIO_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define PMC_IMPL_NO_IOPOWER_0_AUDIO_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_NO_IOPOWER_0_AUDIO_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_NO_IOPOWER_0_AUDIO_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define PMC_IMPL_NO_IOPOWER_0_AUDIO_INIT_ENUM                   DISABLE
#define PMC_IMPL_NO_IOPOWER_0_AUDIO_DISABLE                     _MK_ENUM_CONST(0)
#define PMC_IMPL_NO_IOPOWER_0_AUDIO_ENABLE                      _MK_ENUM_CONST(1)

#define PMC_IMPL_NO_IOPOWER_0_UFS_SHIFT                 _MK_SHIFT_CONST(6)
#define PMC_IMPL_NO_IOPOWER_0_UFS_FIELD                 _MK_FIELD_CONST(0x1, PMC_IMPL_NO_IOPOWER_0_UFS_SHIFT)
#define PMC_IMPL_NO_IOPOWER_0_UFS_RANGE                 6:6
#define PMC_IMPL_NO_IOPOWER_0_UFS_WOFFSET                       0x0
#define PMC_IMPL_NO_IOPOWER_0_UFS_DEFAULT                       _MK_MASK_CONST(0x0)
#define PMC_IMPL_NO_IOPOWER_0_UFS_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define PMC_IMPL_NO_IOPOWER_0_UFS_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define PMC_IMPL_NO_IOPOWER_0_UFS_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define PMC_IMPL_NO_IOPOWER_0_UFS_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_NO_IOPOWER_0_UFS_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)
#define PMC_IMPL_NO_IOPOWER_0_UFS_INIT_ENUM                     DISABLE
#define PMC_IMPL_NO_IOPOWER_0_UFS_DISABLE                       _MK_ENUM_CONST(0)
#define PMC_IMPL_NO_IOPOWER_0_UFS_ENABLE                        _MK_ENUM_CONST(1)

#define PMC_IMPL_NO_IOPOWER_0_MIPI_SHIFT                        _MK_SHIFT_CONST(9)
#define PMC_IMPL_NO_IOPOWER_0_MIPI_FIELD                        _MK_FIELD_CONST(0x1, PMC_IMPL_NO_IOPOWER_0_MIPI_SHIFT)
#define PMC_IMPL_NO_IOPOWER_0_MIPI_RANGE                        9:9
#define PMC_IMPL_NO_IOPOWER_0_MIPI_WOFFSET                      0x0
#define PMC_IMPL_NO_IOPOWER_0_MIPI_DEFAULT                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_NO_IOPOWER_0_MIPI_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define PMC_IMPL_NO_IOPOWER_0_MIPI_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_NO_IOPOWER_0_MIPI_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_NO_IOPOWER_0_MIPI_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define PMC_IMPL_NO_IOPOWER_0_MIPI_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)
#define PMC_IMPL_NO_IOPOWER_0_MIPI_INIT_ENUM                    DISABLE
#define PMC_IMPL_NO_IOPOWER_0_MIPI_DISABLE                      _MK_ENUM_CONST(0)
#define PMC_IMPL_NO_IOPOWER_0_MIPI_ENABLE                       _MK_ENUM_CONST(1)

#define PMC_IMPL_NO_IOPOWER_0_CAM_SHIFT                 _MK_SHIFT_CONST(10)
#define PMC_IMPL_NO_IOPOWER_0_CAM_FIELD                 _MK_FIELD_CONST(0x1, PMC_IMPL_NO_IOPOWER_0_CAM_SHIFT)
#define PMC_IMPL_NO_IOPOWER_0_CAM_RANGE                 10:10
#define PMC_IMPL_NO_IOPOWER_0_CAM_WOFFSET                       0x0
#define PMC_IMPL_NO_IOPOWER_0_CAM_DEFAULT                       _MK_MASK_CONST(0x0)
#define PMC_IMPL_NO_IOPOWER_0_CAM_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define PMC_IMPL_NO_IOPOWER_0_CAM_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define PMC_IMPL_NO_IOPOWER_0_CAM_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define PMC_IMPL_NO_IOPOWER_0_CAM_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_NO_IOPOWER_0_CAM_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)
#define PMC_IMPL_NO_IOPOWER_0_CAM_INIT_ENUM                     DISABLE
#define PMC_IMPL_NO_IOPOWER_0_CAM_DISABLE                       _MK_ENUM_CONST(0)
#define PMC_IMPL_NO_IOPOWER_0_CAM_ENABLE                        _MK_ENUM_CONST(1)

#define PMC_IMPL_NO_IOPOWER_0_SDMMC4_SHIFT                      _MK_SHIFT_CONST(14)
#define PMC_IMPL_NO_IOPOWER_0_SDMMC4_FIELD                      _MK_FIELD_CONST(0x1, PMC_IMPL_NO_IOPOWER_0_SDMMC4_SHIFT)
#define PMC_IMPL_NO_IOPOWER_0_SDMMC4_RANGE                      14:14
#define PMC_IMPL_NO_IOPOWER_0_SDMMC4_WOFFSET                    0x0
#define PMC_IMPL_NO_IOPOWER_0_SDMMC4_DEFAULT                    _MK_MASK_CONST(0x0)
#define PMC_IMPL_NO_IOPOWER_0_SDMMC4_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define PMC_IMPL_NO_IOPOWER_0_SDMMC4_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define PMC_IMPL_NO_IOPOWER_0_SDMMC4_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define PMC_IMPL_NO_IOPOWER_0_SDMMC4_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define PMC_IMPL_NO_IOPOWER_0_SDMMC4_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define PMC_IMPL_NO_IOPOWER_0_SDMMC4_INIT_ENUM                  DISABLE
#define PMC_IMPL_NO_IOPOWER_0_SDMMC4_DISABLE                    _MK_ENUM_CONST(0)
#define PMC_IMPL_NO_IOPOWER_0_SDMMC4_ENABLE                     _MK_ENUM_CONST(1)

#define PMC_IMPL_NO_IOPOWER_0_DBG_SHIFT                 _MK_SHIFT_CONST(19)
#define PMC_IMPL_NO_IOPOWER_0_DBG_FIELD                 _MK_FIELD_CONST(0x1, PMC_IMPL_NO_IOPOWER_0_DBG_SHIFT)
#define PMC_IMPL_NO_IOPOWER_0_DBG_RANGE                 19:19
#define PMC_IMPL_NO_IOPOWER_0_DBG_WOFFSET                       0x0
#define PMC_IMPL_NO_IOPOWER_0_DBG_DEFAULT                       _MK_MASK_CONST(0x0)
#define PMC_IMPL_NO_IOPOWER_0_DBG_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define PMC_IMPL_NO_IOPOWER_0_DBG_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define PMC_IMPL_NO_IOPOWER_0_DBG_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define PMC_IMPL_NO_IOPOWER_0_DBG_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_NO_IOPOWER_0_DBG_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)
#define PMC_IMPL_NO_IOPOWER_0_DBG_INIT_ENUM                     DISABLE
#define PMC_IMPL_NO_IOPOWER_0_DBG_DISABLE                       _MK_ENUM_CONST(0)
#define PMC_IMPL_NO_IOPOWER_0_DBG_ENABLE                        _MK_ENUM_CONST(1)

#define PMC_IMPL_NO_IOPOWER_0_SPI_SHIFT                 _MK_SHIFT_CONST(22)
#define PMC_IMPL_NO_IOPOWER_0_SPI_FIELD                 _MK_FIELD_CONST(0x1, PMC_IMPL_NO_IOPOWER_0_SPI_SHIFT)
#define PMC_IMPL_NO_IOPOWER_0_SPI_RANGE                 22:22
#define PMC_IMPL_NO_IOPOWER_0_SPI_WOFFSET                       0x0
#define PMC_IMPL_NO_IOPOWER_0_SPI_DEFAULT                       _MK_MASK_CONST(0x0)
#define PMC_IMPL_NO_IOPOWER_0_SPI_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define PMC_IMPL_NO_IOPOWER_0_SPI_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define PMC_IMPL_NO_IOPOWER_0_SPI_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define PMC_IMPL_NO_IOPOWER_0_SPI_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_NO_IOPOWER_0_SPI_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)
#define PMC_IMPL_NO_IOPOWER_0_SPI_INIT_ENUM                     DISABLE
#define PMC_IMPL_NO_IOPOWER_0_SPI_DISABLE                       _MK_ENUM_CONST(0)
#define PMC_IMPL_NO_IOPOWER_0_SPI_ENABLE                        _MK_ENUM_CONST(1)

#define PMC_IMPL_NO_IOPOWER_0_AO_SHIFT                  _MK_SHIFT_CONST(26)
#define PMC_IMPL_NO_IOPOWER_0_AO_FIELD                  _MK_FIELD_CONST(0x1, PMC_IMPL_NO_IOPOWER_0_AO_SHIFT)
#define PMC_IMPL_NO_IOPOWER_0_AO_RANGE                  26:26
#define PMC_IMPL_NO_IOPOWER_0_AO_WOFFSET                        0x0
#define PMC_IMPL_NO_IOPOWER_0_AO_DEFAULT                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_NO_IOPOWER_0_AO_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define PMC_IMPL_NO_IOPOWER_0_AO_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_NO_IOPOWER_0_AO_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_NO_IOPOWER_0_AO_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_NO_IOPOWER_0_AO_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define PMC_IMPL_NO_IOPOWER_0_AO_INIT_ENUM                      DISABLE
#define PMC_IMPL_NO_IOPOWER_0_AO_DISABLE                        _MK_ENUM_CONST(0)
#define PMC_IMPL_NO_IOPOWER_0_AO_ENABLE                 _MK_ENUM_CONST(1)


// Reserved address 0x38

// Register PMC_IMPL_E_18V_PWR_0
#define PMC_IMPL_E_18V_PWR_0                    _MK_ADDR_CONST(0x3c)
#define PMC_IMPL_E_18V_PWR_0_SECURE                     0x0
#define PMC_IMPL_E_18V_PWR_0_DUAL                       0x0
#define PMC_IMPL_E_18V_PWR_0_SCR                        E_18V_PWR_SCR_0
#define PMC_IMPL_E_18V_PWR_0_WORD_COUNT                         0x1
#define PMC_IMPL_E_18V_PWR_0_RESET_VAL                  _MK_MASK_CONST(0x70)
#define PMC_IMPL_E_18V_PWR_0_RESET_MASK                         _MK_MASK_CONST(0x72)
#define PMC_IMPL_E_18V_PWR_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_E_18V_PWR_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define PMC_IMPL_E_18V_PWR_0_READ_MASK                  _MK_MASK_CONST(0x72)
#define PMC_IMPL_E_18V_PWR_0_WRITE_MASK                         _MK_MASK_CONST(0x72)
#define PMC_IMPL_E_18V_PWR_0_UFS_SHIFT                  _MK_SHIFT_CONST(1)
#define PMC_IMPL_E_18V_PWR_0_UFS_FIELD                  _MK_FIELD_CONST(0x1, PMC_IMPL_E_18V_PWR_0_UFS_SHIFT)
#define PMC_IMPL_E_18V_PWR_0_UFS_RANGE                  1:1
#define PMC_IMPL_E_18V_PWR_0_UFS_WOFFSET                        0x0
#define PMC_IMPL_E_18V_PWR_0_UFS_DEFAULT                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_E_18V_PWR_0_UFS_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define PMC_IMPL_E_18V_PWR_0_UFS_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_E_18V_PWR_0_UFS_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_E_18V_PWR_0_UFS_PARITY_PROTECTION                      _MK_MASK_CONST(0x1)
#define PMC_IMPL_E_18V_PWR_0_UFS_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define PMC_IMPL_E_18V_PWR_0_UFS_INIT_ENUM                      DISABLE
#define PMC_IMPL_E_18V_PWR_0_UFS_DISABLE                        _MK_ENUM_CONST(0)
#define PMC_IMPL_E_18V_PWR_0_UFS_ENABLE                 _MK_ENUM_CONST(1)

#define PMC_IMPL_E_18V_PWR_0_DBG_SHIFT                  _MK_SHIFT_CONST(4)
#define PMC_IMPL_E_18V_PWR_0_DBG_FIELD                  _MK_FIELD_CONST(0x1, PMC_IMPL_E_18V_PWR_0_DBG_SHIFT)
#define PMC_IMPL_E_18V_PWR_0_DBG_RANGE                  4:4
#define PMC_IMPL_E_18V_PWR_0_DBG_WOFFSET                        0x0
#define PMC_IMPL_E_18V_PWR_0_DBG_DEFAULT                        _MK_MASK_CONST(0x1)
#define PMC_IMPL_E_18V_PWR_0_DBG_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define PMC_IMPL_E_18V_PWR_0_DBG_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_E_18V_PWR_0_DBG_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_E_18V_PWR_0_DBG_PARITY_PROTECTION                      _MK_MASK_CONST(0x1)
#define PMC_IMPL_E_18V_PWR_0_DBG_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define PMC_IMPL_E_18V_PWR_0_DBG_INIT_ENUM                      ENABLE
#define PMC_IMPL_E_18V_PWR_0_DBG_DISABLE                        _MK_ENUM_CONST(0)
#define PMC_IMPL_E_18V_PWR_0_DBG_ENABLE                 _MK_ENUM_CONST(1)

#define PMC_IMPL_E_18V_PWR_0_SPI_SHIFT                  _MK_SHIFT_CONST(5)
#define PMC_IMPL_E_18V_PWR_0_SPI_FIELD                  _MK_FIELD_CONST(0x1, PMC_IMPL_E_18V_PWR_0_SPI_SHIFT)
#define PMC_IMPL_E_18V_PWR_0_SPI_RANGE                  5:5
#define PMC_IMPL_E_18V_PWR_0_SPI_WOFFSET                        0x0
#define PMC_IMPL_E_18V_PWR_0_SPI_DEFAULT                        _MK_MASK_CONST(0x1)
#define PMC_IMPL_E_18V_PWR_0_SPI_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define PMC_IMPL_E_18V_PWR_0_SPI_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_E_18V_PWR_0_SPI_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_E_18V_PWR_0_SPI_PARITY_PROTECTION                      _MK_MASK_CONST(0x1)
#define PMC_IMPL_E_18V_PWR_0_SPI_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define PMC_IMPL_E_18V_PWR_0_SPI_INIT_ENUM                      ENABLE
#define PMC_IMPL_E_18V_PWR_0_SPI_DISABLE                        _MK_ENUM_CONST(0)
#define PMC_IMPL_E_18V_PWR_0_SPI_ENABLE                 _MK_ENUM_CONST(1)

#define PMC_IMPL_E_18V_PWR_0_EQOS_SHIFT                 _MK_SHIFT_CONST(6)
#define PMC_IMPL_E_18V_PWR_0_EQOS_FIELD                 _MK_FIELD_CONST(0x1, PMC_IMPL_E_18V_PWR_0_EQOS_SHIFT)
#define PMC_IMPL_E_18V_PWR_0_EQOS_RANGE                 6:6
#define PMC_IMPL_E_18V_PWR_0_EQOS_WOFFSET                       0x0
#define PMC_IMPL_E_18V_PWR_0_EQOS_DEFAULT                       _MK_MASK_CONST(0x1)
#define PMC_IMPL_E_18V_PWR_0_EQOS_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define PMC_IMPL_E_18V_PWR_0_EQOS_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define PMC_IMPL_E_18V_PWR_0_EQOS_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define PMC_IMPL_E_18V_PWR_0_EQOS_PARITY_PROTECTION                     _MK_MASK_CONST(0x1)
#define PMC_IMPL_E_18V_PWR_0_EQOS_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)
#define PMC_IMPL_E_18V_PWR_0_EQOS_INIT_ENUM                     ENABLE
#define PMC_IMPL_E_18V_PWR_0_EQOS_DISABLE                       _MK_ENUM_CONST(0)
#define PMC_IMPL_E_18V_PWR_0_EQOS_ENABLE                        _MK_ENUM_CONST(1)


// Register PMC_IMPL_E_33V_PWR_0
#define PMC_IMPL_E_33V_PWR_0                    _MK_ADDR_CONST(0x40)
#define PMC_IMPL_E_33V_PWR_0_SECURE                     0x0
#define PMC_IMPL_E_33V_PWR_0_DUAL                       0x0
#define PMC_IMPL_E_33V_PWR_0_SCR                        E_33V_PWR_SCR_0
#define PMC_IMPL_E_33V_PWR_0_WORD_COUNT                         0x1
#define PMC_IMPL_E_33V_PWR_0_RESET_VAL                  _MK_MASK_CONST(0x53)
#define PMC_IMPL_E_33V_PWR_0_RESET_MASK                         _MK_MASK_CONST(0x53)
#define PMC_IMPL_E_33V_PWR_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_E_33V_PWR_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define PMC_IMPL_E_33V_PWR_0_READ_MASK                  _MK_MASK_CONST(0x53)
#define PMC_IMPL_E_33V_PWR_0_WRITE_MASK                         _MK_MASK_CONST(0x53)
#define PMC_IMPL_E_33V_PWR_0_AO_HV_SHIFT                        _MK_SHIFT_CONST(0)
#define PMC_IMPL_E_33V_PWR_0_AO_HV_FIELD                        _MK_FIELD_CONST(0x1, PMC_IMPL_E_33V_PWR_0_AO_HV_SHIFT)
#define PMC_IMPL_E_33V_PWR_0_AO_HV_RANGE                        0:0
#define PMC_IMPL_E_33V_PWR_0_AO_HV_WOFFSET                      0x0
#define PMC_IMPL_E_33V_PWR_0_AO_HV_DEFAULT                      _MK_MASK_CONST(0x1)
#define PMC_IMPL_E_33V_PWR_0_AO_HV_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define PMC_IMPL_E_33V_PWR_0_AO_HV_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_E_33V_PWR_0_AO_HV_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_E_33V_PWR_0_AO_HV_PARITY_PROTECTION                    _MK_MASK_CONST(0x1)
#define PMC_IMPL_E_33V_PWR_0_AO_HV_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)
#define PMC_IMPL_E_33V_PWR_0_AO_HV_INIT_ENUM                    ENABLE
#define PMC_IMPL_E_33V_PWR_0_AO_HV_DISABLE                      _MK_ENUM_CONST(0)
#define PMC_IMPL_E_33V_PWR_0_AO_HV_ENABLE                       _MK_ENUM_CONST(1)

#define PMC_IMPL_E_33V_PWR_0_AUDIO_HV_SHIFT                     _MK_SHIFT_CONST(1)
#define PMC_IMPL_E_33V_PWR_0_AUDIO_HV_FIELD                     _MK_FIELD_CONST(0x1, PMC_IMPL_E_33V_PWR_0_AUDIO_HV_SHIFT)
#define PMC_IMPL_E_33V_PWR_0_AUDIO_HV_RANGE                     1:1
#define PMC_IMPL_E_33V_PWR_0_AUDIO_HV_WOFFSET                   0x0
#define PMC_IMPL_E_33V_PWR_0_AUDIO_HV_DEFAULT                   _MK_MASK_CONST(0x1)
#define PMC_IMPL_E_33V_PWR_0_AUDIO_HV_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define PMC_IMPL_E_33V_PWR_0_AUDIO_HV_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_E_33V_PWR_0_AUDIO_HV_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_E_33V_PWR_0_AUDIO_HV_PARITY_PROTECTION                 _MK_MASK_CONST(0x1)
#define PMC_IMPL_E_33V_PWR_0_AUDIO_HV_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define PMC_IMPL_E_33V_PWR_0_AUDIO_HV_INIT_ENUM                 ENABLE
#define PMC_IMPL_E_33V_PWR_0_AUDIO_HV_DISABLE                   _MK_ENUM_CONST(0)
#define PMC_IMPL_E_33V_PWR_0_AUDIO_HV_ENABLE                    _MK_ENUM_CONST(1)

#define PMC_IMPL_E_33V_PWR_0_SDMMC1_HV_SHIFT                    _MK_SHIFT_CONST(4)
#define PMC_IMPL_E_33V_PWR_0_SDMMC1_HV_FIELD                    _MK_FIELD_CONST(0x1, PMC_IMPL_E_33V_PWR_0_SDMMC1_HV_SHIFT)
#define PMC_IMPL_E_33V_PWR_0_SDMMC1_HV_RANGE                    4:4
#define PMC_IMPL_E_33V_PWR_0_SDMMC1_HV_WOFFSET                  0x0
#define PMC_IMPL_E_33V_PWR_0_SDMMC1_HV_DEFAULT                  _MK_MASK_CONST(0x1)
#define PMC_IMPL_E_33V_PWR_0_SDMMC1_HV_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define PMC_IMPL_E_33V_PWR_0_SDMMC1_HV_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define PMC_IMPL_E_33V_PWR_0_SDMMC1_HV_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define PMC_IMPL_E_33V_PWR_0_SDMMC1_HV_PARITY_PROTECTION                        _MK_MASK_CONST(0x1)
#define PMC_IMPL_E_33V_PWR_0_SDMMC1_HV_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)
#define PMC_IMPL_E_33V_PWR_0_SDMMC1_HV_INIT_ENUM                        ENABLE
#define PMC_IMPL_E_33V_PWR_0_SDMMC1_HV_DISABLE                  _MK_ENUM_CONST(0)
#define PMC_IMPL_E_33V_PWR_0_SDMMC1_HV_ENABLE                   _MK_ENUM_CONST(1)

#define PMC_IMPL_E_33V_PWR_0_SDMMC3_HV_SHIFT                    _MK_SHIFT_CONST(6)
#define PMC_IMPL_E_33V_PWR_0_SDMMC3_HV_FIELD                    _MK_FIELD_CONST(0x1, PMC_IMPL_E_33V_PWR_0_SDMMC3_HV_SHIFT)
#define PMC_IMPL_E_33V_PWR_0_SDMMC3_HV_RANGE                    6:6
#define PMC_IMPL_E_33V_PWR_0_SDMMC3_HV_WOFFSET                  0x0
#define PMC_IMPL_E_33V_PWR_0_SDMMC3_HV_DEFAULT                  _MK_MASK_CONST(0x1)
#define PMC_IMPL_E_33V_PWR_0_SDMMC3_HV_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define PMC_IMPL_E_33V_PWR_0_SDMMC3_HV_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define PMC_IMPL_E_33V_PWR_0_SDMMC3_HV_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define PMC_IMPL_E_33V_PWR_0_SDMMC3_HV_PARITY_PROTECTION                        _MK_MASK_CONST(0x1)
#define PMC_IMPL_E_33V_PWR_0_SDMMC3_HV_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)
#define PMC_IMPL_E_33V_PWR_0_SDMMC3_HV_INIT_ENUM                        ENABLE
#define PMC_IMPL_E_33V_PWR_0_SDMMC3_HV_DISABLE                  _MK_ENUM_CONST(0)
#define PMC_IMPL_E_33V_PWR_0_SDMMC3_HV_ENABLE                   _MK_ENUM_CONST(1)


// Reserved address 0x44

// Reserved address 0x48

// Reserved address 0x4c

// Reserved address 0x50

// Reserved address 0x54

// Reserved address 0x58

// Reserved address 0x5c

// Register PMC_IMPL_OSC_EDPD_OVER_0
#define PMC_IMPL_OSC_EDPD_OVER_0                        _MK_ADDR_CONST(0x60)
#define PMC_IMPL_OSC_EDPD_OVER_0_SECURE                         0x0
#define PMC_IMPL_OSC_EDPD_OVER_0_DUAL                   0x0
#define PMC_IMPL_OSC_EDPD_OVER_0_SCR                    CNTRL_SCR_0
#define PMC_IMPL_OSC_EDPD_OVER_0_WORD_COUNT                     0x1
#define PMC_IMPL_OSC_EDPD_OVER_0_RESET_VAL                      _MK_MASK_CONST(0x2)
#define PMC_IMPL_OSC_EDPD_OVER_0_RESET_MASK                     _MK_MASK_CONST(0xffffff)
#define PMC_IMPL_OSC_EDPD_OVER_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define PMC_IMPL_OSC_EDPD_OVER_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_OSC_EDPD_OVER_0_READ_MASK                      _MK_MASK_CONST(0xffffff)
#define PMC_IMPL_OSC_EDPD_OVER_0_WRITE_MASK                     _MK_MASK_CONST(0xffffff)
#define PMC_IMPL_OSC_EDPD_OVER_0_CLK_OK_SHIFT                   _MK_SHIFT_CONST(23)
#define PMC_IMPL_OSC_EDPD_OVER_0_CLK_OK_FIELD                   _MK_FIELD_CONST(0x1, PMC_IMPL_OSC_EDPD_OVER_0_CLK_OK_SHIFT)
#define PMC_IMPL_OSC_EDPD_OVER_0_CLK_OK_RANGE                   23:23
#define PMC_IMPL_OSC_EDPD_OVER_0_CLK_OK_WOFFSET                 0x0
#define PMC_IMPL_OSC_EDPD_OVER_0_CLK_OK_DEFAULT                 _MK_MASK_CONST(0x0)
#define PMC_IMPL_OSC_EDPD_OVER_0_CLK_OK_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define PMC_IMPL_OSC_EDPD_OVER_0_CLK_OK_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_OSC_EDPD_OVER_0_CLK_OK_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define PMC_IMPL_OSC_EDPD_OVER_0_CLK_OK_PARITY_PROTECTION                       _MK_MASK_CONST(0x1)
#define PMC_IMPL_OSC_EDPD_OVER_0_CLK_OK_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define PMC_IMPL_OSC_EDPD_OVER_0_CLK_OK_DISABLE                 _MK_ENUM_CONST(0)
#define PMC_IMPL_OSC_EDPD_OVER_0_CLK_OK_ENABLE                  _MK_ENUM_CONST(1)

#define PMC_IMPL_OSC_EDPD_OVER_0_OSC_CTRL_SELECT_SHIFT                  _MK_SHIFT_CONST(22)
#define PMC_IMPL_OSC_EDPD_OVER_0_OSC_CTRL_SELECT_FIELD                  _MK_FIELD_CONST(0x1, PMC_IMPL_OSC_EDPD_OVER_0_OSC_CTRL_SELECT_SHIFT)
#define PMC_IMPL_OSC_EDPD_OVER_0_OSC_CTRL_SELECT_RANGE                  22:22
#define PMC_IMPL_OSC_EDPD_OVER_0_OSC_CTRL_SELECT_WOFFSET                        0x0
#define PMC_IMPL_OSC_EDPD_OVER_0_OSC_CTRL_SELECT_DEFAULT                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_OSC_EDPD_OVER_0_OSC_CTRL_SELECT_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define PMC_IMPL_OSC_EDPD_OVER_0_OSC_CTRL_SELECT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_OSC_EDPD_OVER_0_OSC_CTRL_SELECT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_OSC_EDPD_OVER_0_OSC_CTRL_SELECT_PARITY_PROTECTION                      _MK_MASK_CONST(0x1)
#define PMC_IMPL_OSC_EDPD_OVER_0_OSC_CTRL_SELECT_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define PMC_IMPL_OSC_EDPD_OVER_0_OSC_CTRL_SELECT_CAR                    _MK_ENUM_CONST(0)
#define PMC_IMPL_OSC_EDPD_OVER_0_OSC_CTRL_SELECT_PMC                    _MK_ENUM_CONST(1)

#define PMC_IMPL_OSC_EDPD_OVER_0_XO_LP0_MODE_SHIFT                      _MK_SHIFT_CONST(20)
#define PMC_IMPL_OSC_EDPD_OVER_0_XO_LP0_MODE_FIELD                      _MK_FIELD_CONST(0x3, PMC_IMPL_OSC_EDPD_OVER_0_XO_LP0_MODE_SHIFT)
#define PMC_IMPL_OSC_EDPD_OVER_0_XO_LP0_MODE_RANGE                      21:20
#define PMC_IMPL_OSC_EDPD_OVER_0_XO_LP0_MODE_WOFFSET                    0x0
#define PMC_IMPL_OSC_EDPD_OVER_0_XO_LP0_MODE_DEFAULT                    _MK_MASK_CONST(0x0)
#define PMC_IMPL_OSC_EDPD_OVER_0_XO_LP0_MODE_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
#define PMC_IMPL_OSC_EDPD_OVER_0_XO_LP0_MODE_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define PMC_IMPL_OSC_EDPD_OVER_0_XO_LP0_MODE_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define PMC_IMPL_OSC_EDPD_OVER_0_XO_LP0_MODE_PARITY_PROTECTION                  _MK_MASK_CONST(0x1)
#define PMC_IMPL_OSC_EDPD_OVER_0_XO_LP0_MODE_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define PMC_IMPL_OSC_EDPD_OVER_0_XO_LP0_MODE_DPD                        _MK_ENUM_CONST(0)
#define PMC_IMPL_OSC_EDPD_OVER_0_XO_LP0_MODE_OFF                        _MK_ENUM_CONST(1)
#define PMC_IMPL_OSC_EDPD_OVER_0_XO_LP0_MODE_ON                 _MK_ENUM_CONST(2)
#define PMC_IMPL_OSC_EDPD_OVER_0_XO_LP0_MODE_EXT_REQ                    _MK_ENUM_CONST(3)

#define PMC_IMPL_OSC_EDPD_OVER_0_OSCFI_SPARE_SHIFT                      _MK_SHIFT_CONST(12)
#define PMC_IMPL_OSC_EDPD_OVER_0_OSCFI_SPARE_FIELD                      _MK_FIELD_CONST(0xff, PMC_IMPL_OSC_EDPD_OVER_0_OSCFI_SPARE_SHIFT)
#define PMC_IMPL_OSC_EDPD_OVER_0_OSCFI_SPARE_RANGE                      19:12
#define PMC_IMPL_OSC_EDPD_OVER_0_OSCFI_SPARE_WOFFSET                    0x0
#define PMC_IMPL_OSC_EDPD_OVER_0_OSCFI_SPARE_DEFAULT                    _MK_MASK_CONST(0x0)
#define PMC_IMPL_OSC_EDPD_OVER_0_OSCFI_SPARE_DEFAULT_MASK                       _MK_MASK_CONST(0xff)
#define PMC_IMPL_OSC_EDPD_OVER_0_OSCFI_SPARE_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define PMC_IMPL_OSC_EDPD_OVER_0_OSCFI_SPARE_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define PMC_IMPL_OSC_EDPD_OVER_0_OSCFI_SPARE_PARITY_PROTECTION                  _MK_MASK_CONST(0x1)
#define PMC_IMPL_OSC_EDPD_OVER_0_OSCFI_SPARE_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)

#define PMC_IMPL_OSC_EDPD_OVER_0_XODS_SHIFT                     _MK_SHIFT_CONST(7)
#define PMC_IMPL_OSC_EDPD_OVER_0_XODS_FIELD                     _MK_FIELD_CONST(0x1f, PMC_IMPL_OSC_EDPD_OVER_0_XODS_SHIFT)
#define PMC_IMPL_OSC_EDPD_OVER_0_XODS_RANGE                     11:7
#define PMC_IMPL_OSC_EDPD_OVER_0_XODS_WOFFSET                   0x0
#define PMC_IMPL_OSC_EDPD_OVER_0_XODS_DEFAULT                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_OSC_EDPD_OVER_0_XODS_DEFAULT_MASK                      _MK_MASK_CONST(0x1f)
#define PMC_IMPL_OSC_EDPD_OVER_0_XODS_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_OSC_EDPD_OVER_0_XODS_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_OSC_EDPD_OVER_0_XODS_PARITY_PROTECTION                 _MK_MASK_CONST(0x1)
#define PMC_IMPL_OSC_EDPD_OVER_0_XODS_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)

#define PMC_IMPL_OSC_EDPD_OVER_0_XOFS_SHIFT                     _MK_SHIFT_CONST(1)
#define PMC_IMPL_OSC_EDPD_OVER_0_XOFS_FIELD                     _MK_FIELD_CONST(0x3f, PMC_IMPL_OSC_EDPD_OVER_0_XOFS_SHIFT)
#define PMC_IMPL_OSC_EDPD_OVER_0_XOFS_RANGE                     6:1
#define PMC_IMPL_OSC_EDPD_OVER_0_XOFS_WOFFSET                   0x0
#define PMC_IMPL_OSC_EDPD_OVER_0_XOFS_DEFAULT                   _MK_MASK_CONST(0x1)
#define PMC_IMPL_OSC_EDPD_OVER_0_XOFS_DEFAULT_MASK                      _MK_MASK_CONST(0x3f)
#define PMC_IMPL_OSC_EDPD_OVER_0_XOFS_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_OSC_EDPD_OVER_0_XOFS_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_OSC_EDPD_OVER_0_XOFS_PARITY_PROTECTION                 _MK_MASK_CONST(0x1)
#define PMC_IMPL_OSC_EDPD_OVER_0_XOFS_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)

#define PMC_IMPL_OSC_EDPD_OVER_0_XOBP_SHIFT                     _MK_SHIFT_CONST(0)
#define PMC_IMPL_OSC_EDPD_OVER_0_XOBP_FIELD                     _MK_FIELD_CONST(0x1, PMC_IMPL_OSC_EDPD_OVER_0_XOBP_SHIFT)
#define PMC_IMPL_OSC_EDPD_OVER_0_XOBP_RANGE                     0:0
#define PMC_IMPL_OSC_EDPD_OVER_0_XOBP_WOFFSET                   0x0
#define PMC_IMPL_OSC_EDPD_OVER_0_XOBP_DEFAULT                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_OSC_EDPD_OVER_0_XOBP_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define PMC_IMPL_OSC_EDPD_OVER_0_XOBP_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_OSC_EDPD_OVER_0_XOBP_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_OSC_EDPD_OVER_0_XOBP_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define PMC_IMPL_OSC_EDPD_OVER_0_XOBP_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)


// Register PMC_IMPL_CLK_OUT_CNTRL_0
#define PMC_IMPL_CLK_OUT_CNTRL_0                        _MK_ADDR_CONST(0x64)
#define PMC_IMPL_CLK_OUT_CNTRL_0_SECURE                         0x0
#define PMC_IMPL_CLK_OUT_CNTRL_0_DUAL                   0x0
#define PMC_IMPL_CLK_OUT_CNTRL_0_SCR                    CNTRL_SCR_0
#define PMC_IMPL_CLK_OUT_CNTRL_0_WORD_COUNT                     0x1
#define PMC_IMPL_CLK_OUT_CNTRL_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_CLK_OUT_CNTRL_0_RESET_MASK                     _MK_MASK_CONST(0xffffff)
#define PMC_IMPL_CLK_OUT_CNTRL_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define PMC_IMPL_CLK_OUT_CNTRL_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_CLK_OUT_CNTRL_0_READ_MASK                      _MK_MASK_CONST(0xffffff)
#define PMC_IMPL_CLK_OUT_CNTRL_0_WRITE_MASK                     _MK_MASK_CONST(0xffffff)
#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK1_ACCEPT_REQ_SHIFT                  _MK_SHIFT_CONST(0)
#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK1_ACCEPT_REQ_FIELD                  _MK_FIELD_CONST(0x1, PMC_IMPL_CLK_OUT_CNTRL_0_CLK1_ACCEPT_REQ_SHIFT)
#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK1_ACCEPT_REQ_RANGE                  0:0
#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK1_ACCEPT_REQ_WOFFSET                        0x0
#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK1_ACCEPT_REQ_DEFAULT                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK1_ACCEPT_REQ_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK1_ACCEPT_REQ_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK1_ACCEPT_REQ_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK1_ACCEPT_REQ_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK1_ACCEPT_REQ_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)

#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK1_INVERT_REQ_SHIFT                  _MK_SHIFT_CONST(1)
#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK1_INVERT_REQ_FIELD                  _MK_FIELD_CONST(0x1, PMC_IMPL_CLK_OUT_CNTRL_0_CLK1_INVERT_REQ_SHIFT)
#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK1_INVERT_REQ_RANGE                  1:1
#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK1_INVERT_REQ_WOFFSET                        0x0
#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK1_INVERT_REQ_DEFAULT                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK1_INVERT_REQ_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK1_INVERT_REQ_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK1_INVERT_REQ_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK1_INVERT_REQ_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK1_INVERT_REQ_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)

#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK1_FORCE_EN_SHIFT                    _MK_SHIFT_CONST(2)
#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK1_FORCE_EN_FIELD                    _MK_FIELD_CONST(0x1, PMC_IMPL_CLK_OUT_CNTRL_0_CLK1_FORCE_EN_SHIFT)
#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK1_FORCE_EN_RANGE                    2:2
#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK1_FORCE_EN_WOFFSET                  0x0
#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK1_FORCE_EN_DEFAULT                  _MK_MASK_CONST(0x0)
#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK1_FORCE_EN_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK1_FORCE_EN_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK1_FORCE_EN_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK1_FORCE_EN_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK1_FORCE_EN_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)

#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK1_RESERVED_SHIFT                    _MK_SHIFT_CONST(3)
#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK1_RESERVED_FIELD                    _MK_FIELD_CONST(0x1, PMC_IMPL_CLK_OUT_CNTRL_0_CLK1_RESERVED_SHIFT)
#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK1_RESERVED_RANGE                    3:3
#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK1_RESERVED_WOFFSET                  0x0
#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK1_RESERVED_DEFAULT                  _MK_MASK_CONST(0x0)
#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK1_RESERVED_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK1_RESERVED_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK1_RESERVED_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK1_RESERVED_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK1_RESERVED_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)

#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK1_IDLE_STATE_SHIFT                  _MK_SHIFT_CONST(4)
#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK1_IDLE_STATE_FIELD                  _MK_FIELD_CONST(0x3, PMC_IMPL_CLK_OUT_CNTRL_0_CLK1_IDLE_STATE_SHIFT)
#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK1_IDLE_STATE_RANGE                  5:4
#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK1_IDLE_STATE_WOFFSET                        0x0
#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK1_IDLE_STATE_DEFAULT                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK1_IDLE_STATE_DEFAULT_MASK                   _MK_MASK_CONST(0x3)
#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK1_IDLE_STATE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK1_IDLE_STATE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK1_IDLE_STATE_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK1_IDLE_STATE_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK1_IDLE_STATE_LOW                    _MK_ENUM_CONST(0)
#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK1_IDLE_STATE_HIGH                   _MK_ENUM_CONST(1)
#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK1_IDLE_STATE_TRIS                   _MK_ENUM_CONST(2)

#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK1_SRC_SEL_SHIFT                     _MK_SHIFT_CONST(6)
#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK1_SRC_SEL_FIELD                     _MK_FIELD_CONST(0x3, PMC_IMPL_CLK_OUT_CNTRL_0_CLK1_SRC_SEL_SHIFT)
#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK1_SRC_SEL_RANGE                     7:6
#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK1_SRC_SEL_WOFFSET                   0x0
#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK1_SRC_SEL_DEFAULT                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK1_SRC_SEL_DEFAULT_MASK                      _MK_MASK_CONST(0x3)
#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK1_SRC_SEL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK1_SRC_SEL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK1_SRC_SEL_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK1_SRC_SEL_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK1_SRC_SEL_OSC_DIV1                  _MK_ENUM_CONST(0)
#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK1_SRC_SEL_OSC_DIV2                  _MK_ENUM_CONST(1)
#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK1_SRC_SEL_OSC_DIV3                  _MK_ENUM_CONST(2)
#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK1_SRC_SEL_CAR                       _MK_ENUM_CONST(3)

#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK2_ACCEPT_REQ_SHIFT                  _MK_SHIFT_CONST(8)
#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK2_ACCEPT_REQ_FIELD                  _MK_FIELD_CONST(0x1, PMC_IMPL_CLK_OUT_CNTRL_0_CLK2_ACCEPT_REQ_SHIFT)
#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK2_ACCEPT_REQ_RANGE                  8:8
#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK2_ACCEPT_REQ_WOFFSET                        0x0
#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK2_ACCEPT_REQ_DEFAULT                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK2_ACCEPT_REQ_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK2_ACCEPT_REQ_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK2_ACCEPT_REQ_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK2_ACCEPT_REQ_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK2_ACCEPT_REQ_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)

#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK2_INVERT_REQ_SHIFT                  _MK_SHIFT_CONST(9)
#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK2_INVERT_REQ_FIELD                  _MK_FIELD_CONST(0x1, PMC_IMPL_CLK_OUT_CNTRL_0_CLK2_INVERT_REQ_SHIFT)
#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK2_INVERT_REQ_RANGE                  9:9
#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK2_INVERT_REQ_WOFFSET                        0x0
#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK2_INVERT_REQ_DEFAULT                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK2_INVERT_REQ_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK2_INVERT_REQ_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK2_INVERT_REQ_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK2_INVERT_REQ_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK2_INVERT_REQ_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)

#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK2_FORCE_EN_SHIFT                    _MK_SHIFT_CONST(10)
#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK2_FORCE_EN_FIELD                    _MK_FIELD_CONST(0x1, PMC_IMPL_CLK_OUT_CNTRL_0_CLK2_FORCE_EN_SHIFT)
#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK2_FORCE_EN_RANGE                    10:10
#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK2_FORCE_EN_WOFFSET                  0x0
#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK2_FORCE_EN_DEFAULT                  _MK_MASK_CONST(0x0)
#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK2_FORCE_EN_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK2_FORCE_EN_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK2_FORCE_EN_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK2_FORCE_EN_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK2_FORCE_EN_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)

#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK2_RESERVED_SHIFT                    _MK_SHIFT_CONST(11)
#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK2_RESERVED_FIELD                    _MK_FIELD_CONST(0x1, PMC_IMPL_CLK_OUT_CNTRL_0_CLK2_RESERVED_SHIFT)
#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK2_RESERVED_RANGE                    11:11
#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK2_RESERVED_WOFFSET                  0x0
#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK2_RESERVED_DEFAULT                  _MK_MASK_CONST(0x0)
#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK2_RESERVED_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK2_RESERVED_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK2_RESERVED_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK2_RESERVED_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK2_RESERVED_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)

#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK2_IDLE_STATE_SHIFT                  _MK_SHIFT_CONST(12)
#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK2_IDLE_STATE_FIELD                  _MK_FIELD_CONST(0x3, PMC_IMPL_CLK_OUT_CNTRL_0_CLK2_IDLE_STATE_SHIFT)
#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK2_IDLE_STATE_RANGE                  13:12
#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK2_IDLE_STATE_WOFFSET                        0x0
#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK2_IDLE_STATE_DEFAULT                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK2_IDLE_STATE_DEFAULT_MASK                   _MK_MASK_CONST(0x3)
#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK2_IDLE_STATE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK2_IDLE_STATE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK2_IDLE_STATE_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK2_IDLE_STATE_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK2_IDLE_STATE_LOW                    _MK_ENUM_CONST(0)
#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK2_IDLE_STATE_HIGH                   _MK_ENUM_CONST(1)
#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK2_IDLE_STATE_TRIS                   _MK_ENUM_CONST(2)

#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK2_SRC_SEL_SHIFT                     _MK_SHIFT_CONST(14)
#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK2_SRC_SEL_FIELD                     _MK_FIELD_CONST(0x3, PMC_IMPL_CLK_OUT_CNTRL_0_CLK2_SRC_SEL_SHIFT)
#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK2_SRC_SEL_RANGE                     15:14
#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK2_SRC_SEL_WOFFSET                   0x0
#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK2_SRC_SEL_DEFAULT                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK2_SRC_SEL_DEFAULT_MASK                      _MK_MASK_CONST(0x3)
#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK2_SRC_SEL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK2_SRC_SEL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK2_SRC_SEL_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK2_SRC_SEL_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK2_SRC_SEL_OSC_DIV1                  _MK_ENUM_CONST(0)
#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK2_SRC_SEL_OSC_DIV2                  _MK_ENUM_CONST(1)
#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK2_SRC_SEL_OSC_DIV3                  _MK_ENUM_CONST(2)
#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK2_SRC_SEL_CAR                       _MK_ENUM_CONST(3)

#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK3_ACCEPT_REQ_SHIFT                  _MK_SHIFT_CONST(16)
#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK3_ACCEPT_REQ_FIELD                  _MK_FIELD_CONST(0x1, PMC_IMPL_CLK_OUT_CNTRL_0_CLK3_ACCEPT_REQ_SHIFT)
#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK3_ACCEPT_REQ_RANGE                  16:16
#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK3_ACCEPT_REQ_WOFFSET                        0x0
#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK3_ACCEPT_REQ_DEFAULT                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK3_ACCEPT_REQ_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK3_ACCEPT_REQ_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK3_ACCEPT_REQ_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK3_ACCEPT_REQ_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK3_ACCEPT_REQ_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)

#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK3_INVERT_REQ_SHIFT                  _MK_SHIFT_CONST(17)
#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK3_INVERT_REQ_FIELD                  _MK_FIELD_CONST(0x1, PMC_IMPL_CLK_OUT_CNTRL_0_CLK3_INVERT_REQ_SHIFT)
#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK3_INVERT_REQ_RANGE                  17:17
#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK3_INVERT_REQ_WOFFSET                        0x0
#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK3_INVERT_REQ_DEFAULT                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK3_INVERT_REQ_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK3_INVERT_REQ_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK3_INVERT_REQ_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK3_INVERT_REQ_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK3_INVERT_REQ_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)

#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK3_FORCE_EN_SHIFT                    _MK_SHIFT_CONST(18)
#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK3_FORCE_EN_FIELD                    _MK_FIELD_CONST(0x1, PMC_IMPL_CLK_OUT_CNTRL_0_CLK3_FORCE_EN_SHIFT)
#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK3_FORCE_EN_RANGE                    18:18
#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK3_FORCE_EN_WOFFSET                  0x0
#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK3_FORCE_EN_DEFAULT                  _MK_MASK_CONST(0x0)
#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK3_FORCE_EN_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK3_FORCE_EN_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK3_FORCE_EN_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK3_FORCE_EN_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK3_FORCE_EN_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)

#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK3_RESERVED_SHIFT                    _MK_SHIFT_CONST(19)
#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK3_RESERVED_FIELD                    _MK_FIELD_CONST(0x1, PMC_IMPL_CLK_OUT_CNTRL_0_CLK3_RESERVED_SHIFT)
#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK3_RESERVED_RANGE                    19:19
#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK3_RESERVED_WOFFSET                  0x0
#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK3_RESERVED_DEFAULT                  _MK_MASK_CONST(0x0)
#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK3_RESERVED_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK3_RESERVED_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK3_RESERVED_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK3_RESERVED_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK3_RESERVED_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)

#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK3_IDLE_STATE_SHIFT                  _MK_SHIFT_CONST(20)
#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK3_IDLE_STATE_FIELD                  _MK_FIELD_CONST(0x3, PMC_IMPL_CLK_OUT_CNTRL_0_CLK3_IDLE_STATE_SHIFT)
#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK3_IDLE_STATE_RANGE                  21:20
#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK3_IDLE_STATE_WOFFSET                        0x0
#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK3_IDLE_STATE_DEFAULT                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK3_IDLE_STATE_DEFAULT_MASK                   _MK_MASK_CONST(0x3)
#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK3_IDLE_STATE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK3_IDLE_STATE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK3_IDLE_STATE_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK3_IDLE_STATE_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK3_IDLE_STATE_LOW                    _MK_ENUM_CONST(0)
#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK3_IDLE_STATE_HIGH                   _MK_ENUM_CONST(1)
#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK3_IDLE_STATE_TRIS                   _MK_ENUM_CONST(2)

#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK3_SRC_SEL_SHIFT                     _MK_SHIFT_CONST(22)
#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK3_SRC_SEL_FIELD                     _MK_FIELD_CONST(0x3, PMC_IMPL_CLK_OUT_CNTRL_0_CLK3_SRC_SEL_SHIFT)
#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK3_SRC_SEL_RANGE                     23:22
#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK3_SRC_SEL_WOFFSET                   0x0
#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK3_SRC_SEL_DEFAULT                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK3_SRC_SEL_DEFAULT_MASK                      _MK_MASK_CONST(0x3)
#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK3_SRC_SEL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK3_SRC_SEL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK3_SRC_SEL_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK3_SRC_SEL_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK3_SRC_SEL_OSC_DIV1                  _MK_ENUM_CONST(0)
#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK3_SRC_SEL_OSC_DIV2                  _MK_ENUM_CONST(1)
#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK3_SRC_SEL_OSC_DIV3                  _MK_ENUM_CONST(2)
#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK3_SRC_SEL_CAR                       _MK_ENUM_CONST(3)


// Reserved address 0x68

// Register PMC_IMPL_SENSOR_CTRL_0
#define PMC_IMPL_SENSOR_CTRL_0                  _MK_ADDR_CONST(0x6c)
#define PMC_IMPL_SENSOR_CTRL_0_SECURE                   0x0
#define PMC_IMPL_SENSOR_CTRL_0_DUAL                     0x0
#define PMC_IMPL_SENSOR_CTRL_0_SCR                      CNTRL_SCR_0
#define PMC_IMPL_SENSOR_CTRL_0_WORD_COUNT                       0x1
#define PMC_IMPL_SENSOR_CTRL_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_SENSOR_CTRL_0_RESET_MASK                       _MK_MASK_CONST(0x7)
#define PMC_IMPL_SENSOR_CTRL_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_SENSOR_CTRL_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define PMC_IMPL_SENSOR_CTRL_0_READ_MASK                        _MK_MASK_CONST(0x7)
#define PMC_IMPL_SENSOR_CTRL_0_WRITE_MASK                       _MK_MASK_CONST(0x7)
#define PMC_IMPL_SENSOR_CTRL_0_ENABLE_PG_SHIFT                  _MK_SHIFT_CONST(0)
#define PMC_IMPL_SENSOR_CTRL_0_ENABLE_PG_FIELD                  _MK_FIELD_CONST(0x1, PMC_IMPL_SENSOR_CTRL_0_ENABLE_PG_SHIFT)
#define PMC_IMPL_SENSOR_CTRL_0_ENABLE_PG_RANGE                  0:0
#define PMC_IMPL_SENSOR_CTRL_0_ENABLE_PG_WOFFSET                        0x0
#define PMC_IMPL_SENSOR_CTRL_0_ENABLE_PG_DEFAULT                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_SENSOR_CTRL_0_ENABLE_PG_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define PMC_IMPL_SENSOR_CTRL_0_ENABLE_PG_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_SENSOR_CTRL_0_ENABLE_PG_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_SENSOR_CTRL_0_ENABLE_PG_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_SENSOR_CTRL_0_ENABLE_PG_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define PMC_IMPL_SENSOR_CTRL_0_ENABLE_PG_OFF                    _MK_ENUM_CONST(0)
#define PMC_IMPL_SENSOR_CTRL_0_ENABLE_PG_ON                     _MK_ENUM_CONST(1)

#define PMC_IMPL_SENSOR_CTRL_0_ENABLE_RST_SHIFT                 _MK_SHIFT_CONST(1)
#define PMC_IMPL_SENSOR_CTRL_0_ENABLE_RST_FIELD                 _MK_FIELD_CONST(0x1, PMC_IMPL_SENSOR_CTRL_0_ENABLE_RST_SHIFT)
#define PMC_IMPL_SENSOR_CTRL_0_ENABLE_RST_RANGE                 1:1
#define PMC_IMPL_SENSOR_CTRL_0_ENABLE_RST_WOFFSET                       0x0
#define PMC_IMPL_SENSOR_CTRL_0_ENABLE_RST_DEFAULT                       _MK_MASK_CONST(0x0)
#define PMC_IMPL_SENSOR_CTRL_0_ENABLE_RST_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define PMC_IMPL_SENSOR_CTRL_0_ENABLE_RST_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define PMC_IMPL_SENSOR_CTRL_0_ENABLE_RST_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define PMC_IMPL_SENSOR_CTRL_0_ENABLE_RST_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_SENSOR_CTRL_0_ENABLE_RST_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)
#define PMC_IMPL_SENSOR_CTRL_0_ENABLE_RST_OFF                   _MK_ENUM_CONST(0)
#define PMC_IMPL_SENSOR_CTRL_0_ENABLE_RST_ON                    _MK_ENUM_CONST(1)

#define PMC_IMPL_SENSOR_CTRL_0_BLOCK_SCRATCH_WRITE_SHIFT                        _MK_SHIFT_CONST(2)
#define PMC_IMPL_SENSOR_CTRL_0_BLOCK_SCRATCH_WRITE_FIELD                        _MK_FIELD_CONST(0x1, PMC_IMPL_SENSOR_CTRL_0_BLOCK_SCRATCH_WRITE_SHIFT)
#define PMC_IMPL_SENSOR_CTRL_0_BLOCK_SCRATCH_WRITE_RANGE                        2:2
#define PMC_IMPL_SENSOR_CTRL_0_BLOCK_SCRATCH_WRITE_WOFFSET                      0x0
#define PMC_IMPL_SENSOR_CTRL_0_BLOCK_SCRATCH_WRITE_DEFAULT                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_SENSOR_CTRL_0_BLOCK_SCRATCH_WRITE_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define PMC_IMPL_SENSOR_CTRL_0_BLOCK_SCRATCH_WRITE_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_SENSOR_CTRL_0_BLOCK_SCRATCH_WRITE_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_SENSOR_CTRL_0_BLOCK_SCRATCH_WRITE_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define PMC_IMPL_SENSOR_CTRL_0_BLOCK_SCRATCH_WRITE_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)
#define PMC_IMPL_SENSOR_CTRL_0_BLOCK_SCRATCH_WRITE_OFF_ON                       _MK_ENUM_CONST(0)


// Register PMC_IMPL_RST_STATUS_0
#define PMC_IMPL_RST_STATUS_0                   _MK_ADDR_CONST(0x70)
#define PMC_IMPL_RST_STATUS_0_SECURE                    0x0
#define PMC_IMPL_RST_STATUS_0_DUAL                      0x0
#define PMC_IMPL_RST_STATUS_0_SCR                       CNTRL_SCR_0
#define PMC_IMPL_RST_STATUS_0_WORD_COUNT                        0x1
#define PMC_IMPL_RST_STATUS_0_RESET_VAL                         _MK_MASK_CONST(0x0)
#define PMC_IMPL_RST_STATUS_0_RESET_MASK                        _MK_MASK_CONST(0x7f)
#define PMC_IMPL_RST_STATUS_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define PMC_IMPL_RST_STATUS_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_RST_STATUS_0_READ_MASK                         _MK_MASK_CONST(0x7f)
#define PMC_IMPL_RST_STATUS_0_WRITE_MASK                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_RST_STATUS_0_RST_LEVEL_SHIFT                   _MK_SHIFT_CONST(0)
#define PMC_IMPL_RST_STATUS_0_RST_LEVEL_FIELD                   _MK_FIELD_CONST(0x3, PMC_IMPL_RST_STATUS_0_RST_LEVEL_SHIFT)
#define PMC_IMPL_RST_STATUS_0_RST_LEVEL_RANGE                   1:0
#define PMC_IMPL_RST_STATUS_0_RST_LEVEL_WOFFSET                 0x0
#define PMC_IMPL_RST_STATUS_0_RST_LEVEL_DEFAULT                 _MK_MASK_CONST(0x0)
#define PMC_IMPL_RST_STATUS_0_RST_LEVEL_DEFAULT_MASK                    _MK_MASK_CONST(0x3)
#define PMC_IMPL_RST_STATUS_0_RST_LEVEL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_RST_STATUS_0_RST_LEVEL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define PMC_IMPL_RST_STATUS_0_RST_LEVEL_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define PMC_IMPL_RST_STATUS_0_RST_LEVEL_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define PMC_IMPL_RST_STATUS_0_RST_LEVEL_INIT_ENUM                       L0
#define PMC_IMPL_RST_STATUS_0_RST_LEVEL_L0                      _MK_ENUM_CONST(0)
#define PMC_IMPL_RST_STATUS_0_RST_LEVEL_L1                      _MK_ENUM_CONST(1)
#define PMC_IMPL_RST_STATUS_0_RST_LEVEL_L2                      _MK_ENUM_CONST(2)
#define PMC_IMPL_RST_STATUS_0_RST_LEVEL_WARM                    _MK_ENUM_CONST(3)

#define PMC_IMPL_RST_STATUS_0_RST_SOURCE_SHIFT                  _MK_SHIFT_CONST(2)
#define PMC_IMPL_RST_STATUS_0_RST_SOURCE_FIELD                  _MK_FIELD_CONST(0x1f, PMC_IMPL_RST_STATUS_0_RST_SOURCE_SHIFT)
#define PMC_IMPL_RST_STATUS_0_RST_SOURCE_RANGE                  6:2
#define PMC_IMPL_RST_STATUS_0_RST_SOURCE_WOFFSET                        0x0
#define PMC_IMPL_RST_STATUS_0_RST_SOURCE_DEFAULT                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_RST_STATUS_0_RST_SOURCE_DEFAULT_MASK                   _MK_MASK_CONST(0x1f)
#define PMC_IMPL_RST_STATUS_0_RST_SOURCE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_RST_STATUS_0_RST_SOURCE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_RST_STATUS_0_RST_SOURCE_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_RST_STATUS_0_RST_SOURCE_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define PMC_IMPL_RST_STATUS_0_RST_SOURCE_INIT_ENUM                      SYS_RESET_N
#define PMC_IMPL_RST_STATUS_0_RST_SOURCE_SYS_RESET_N                    _MK_ENUM_CONST(0)
#define PMC_IMPL_RST_STATUS_0_RST_SOURCE_AOWDT                  _MK_ENUM_CONST(1)
#define PMC_IMPL_RST_STATUS_0_RST_SOURCE_BCCPLEXWDT                     _MK_ENUM_CONST(2)
#define PMC_IMPL_RST_STATUS_0_RST_SOURCE_BPMPWDT                        _MK_ENUM_CONST(3)
#define PMC_IMPL_RST_STATUS_0_RST_SOURCE_SCEWDT                 _MK_ENUM_CONST(4)
#define PMC_IMPL_RST_STATUS_0_RST_SOURCE_SPEWDT                 _MK_ENUM_CONST(5)
#define PMC_IMPL_RST_STATUS_0_RST_SOURCE_APEWDT                 _MK_ENUM_CONST(6)
#define PMC_IMPL_RST_STATUS_0_RST_SOURCE_LCCPLEXWDT                     _MK_ENUM_CONST(7)
#define PMC_IMPL_RST_STATUS_0_RST_SOURCE_SENSOR                 _MK_ENUM_CONST(8)
#define PMC_IMPL_RST_STATUS_0_RST_SOURCE_AOTAG                  _MK_ENUM_CONST(9)
#define PMC_IMPL_RST_STATUS_0_RST_SOURCE_VFSENSOR                       _MK_ENUM_CONST(10)
#define PMC_IMPL_RST_STATUS_0_RST_SOURCE_MAINSWRST                      _MK_ENUM_CONST(11)
#define PMC_IMPL_RST_STATUS_0_RST_SOURCE_SC7                    _MK_ENUM_CONST(12)
#define PMC_IMPL_RST_STATUS_0_RST_SOURCE_HSM                    _MK_ENUM_CONST(13)
#define PMC_IMPL_RST_STATUS_0_RST_SOURCE_CSITE                  _MK_ENUM_CONST(14)
#define PMC_IMPL_RST_STATUS_0_RST_SOURCE_RCEWDT                 _MK_ENUM_CONST(15)
#define PMC_IMPL_RST_STATUS_0_RST_SOURCE_PVA0WDT                        _MK_ENUM_CONST(16)
#define PMC_IMPL_RST_STATUS_0_RST_SOURCE_PVA1WDT                        _MK_ENUM_CONST(17)
#define PMC_IMPL_RST_STATUS_0_RST_SOURCE_L1A_ASYNC                      _MK_ENUM_CONST(18)
#define PMC_IMPL_RST_STATUS_0_RST_SOURCE_BPMPBOOT                       _MK_ENUM_CONST(19)
#define PMC_IMPL_RST_STATUS_0_RST_SOURCE_FUSECRC                        _MK_ENUM_CONST(20)


// Register PMC_IMPL_IO_DPD_REQ_0
#define PMC_IMPL_IO_DPD_REQ_0                   _MK_ADDR_CONST(0x74)
#define PMC_IMPL_IO_DPD_REQ_0_SECURE                    0x0
#define PMC_IMPL_IO_DPD_REQ_0_DUAL                      0x0
#define PMC_IMPL_IO_DPD_REQ_0_SCR                       IODPD1_SCR_0
#define PMC_IMPL_IO_DPD_REQ_0_WORD_COUNT                        0x1
#define PMC_IMPL_IO_DPD_REQ_0_RESET_VAL                         _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD_REQ_0_RESET_MASK                        _MK_MASK_CONST(0xffffdffb)
#define PMC_IMPL_IO_DPD_REQ_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD_REQ_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD_REQ_0_READ_MASK                         _MK_MASK_CONST(0xffffdffb)
#define PMC_IMPL_IO_DPD_REQ_0_WRITE_MASK                        _MK_MASK_CONST(0xffffdffb)
#define PMC_IMPL_IO_DPD_REQ_0_CSIA_SHIFT                        _MK_SHIFT_CONST(0)
#define PMC_IMPL_IO_DPD_REQ_0_CSIA_FIELD                        _MK_FIELD_CONST(0x1, PMC_IMPL_IO_DPD_REQ_0_CSIA_SHIFT)
#define PMC_IMPL_IO_DPD_REQ_0_CSIA_RANGE                        0:0
#define PMC_IMPL_IO_DPD_REQ_0_CSIA_WOFFSET                      0x0
#define PMC_IMPL_IO_DPD_REQ_0_CSIA_DEFAULT                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD_REQ_0_CSIA_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DPD_REQ_0_CSIA_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD_REQ_0_CSIA_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD_REQ_0_CSIA_PARITY_PROTECTION                    _MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DPD_REQ_0_CSIA_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DPD_REQ_0_CSIA_OFF                  _MK_ENUM_CONST(0)
#define PMC_IMPL_IO_DPD_REQ_0_CSIA_ON                   _MK_ENUM_CONST(1)

#define PMC_IMPL_IO_DPD_REQ_0_CSIB_SHIFT                        _MK_SHIFT_CONST(1)
#define PMC_IMPL_IO_DPD_REQ_0_CSIB_FIELD                        _MK_FIELD_CONST(0x1, PMC_IMPL_IO_DPD_REQ_0_CSIB_SHIFT)
#define PMC_IMPL_IO_DPD_REQ_0_CSIB_RANGE                        1:1
#define PMC_IMPL_IO_DPD_REQ_0_CSIB_WOFFSET                      0x0
#define PMC_IMPL_IO_DPD_REQ_0_CSIB_DEFAULT                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD_REQ_0_CSIB_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DPD_REQ_0_CSIB_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD_REQ_0_CSIB_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD_REQ_0_CSIB_PARITY_PROTECTION                    _MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DPD_REQ_0_CSIB_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DPD_REQ_0_CSIB_OFF                  _MK_ENUM_CONST(0)
#define PMC_IMPL_IO_DPD_REQ_0_CSIB_ON                   _MK_ENUM_CONST(1)

#define PMC_IMPL_IO_DPD_REQ_0_MIPI_BIAS_SHIFT                   _MK_SHIFT_CONST(3)
#define PMC_IMPL_IO_DPD_REQ_0_MIPI_BIAS_FIELD                   _MK_FIELD_CONST(0x1, PMC_IMPL_IO_DPD_REQ_0_MIPI_BIAS_SHIFT)
#define PMC_IMPL_IO_DPD_REQ_0_MIPI_BIAS_RANGE                   3:3
#define PMC_IMPL_IO_DPD_REQ_0_MIPI_BIAS_WOFFSET                 0x0
#define PMC_IMPL_IO_DPD_REQ_0_MIPI_BIAS_DEFAULT                 _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD_REQ_0_MIPI_BIAS_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DPD_REQ_0_MIPI_BIAS_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD_REQ_0_MIPI_BIAS_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD_REQ_0_MIPI_BIAS_PARITY_PROTECTION                       _MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DPD_REQ_0_MIPI_BIAS_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DPD_REQ_0_MIPI_BIAS_OFF                     _MK_ENUM_CONST(0)
#define PMC_IMPL_IO_DPD_REQ_0_MIPI_BIAS_ON                      _MK_ENUM_CONST(1)

#define PMC_IMPL_IO_DPD_REQ_0_PEX_CLK_BIAS_SHIFT                        _MK_SHIFT_CONST(4)
#define PMC_IMPL_IO_DPD_REQ_0_PEX_CLK_BIAS_FIELD                        _MK_FIELD_CONST(0x1, PMC_IMPL_IO_DPD_REQ_0_PEX_CLK_BIAS_SHIFT)
#define PMC_IMPL_IO_DPD_REQ_0_PEX_CLK_BIAS_RANGE                        4:4
#define PMC_IMPL_IO_DPD_REQ_0_PEX_CLK_BIAS_WOFFSET                      0x0
#define PMC_IMPL_IO_DPD_REQ_0_PEX_CLK_BIAS_DEFAULT                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD_REQ_0_PEX_CLK_BIAS_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DPD_REQ_0_PEX_CLK_BIAS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD_REQ_0_PEX_CLK_BIAS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD_REQ_0_PEX_CLK_BIAS_PARITY_PROTECTION                    _MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DPD_REQ_0_PEX_CLK_BIAS_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DPD_REQ_0_PEX_CLK_BIAS_OFF                  _MK_ENUM_CONST(0)
#define PMC_IMPL_IO_DPD_REQ_0_PEX_CLK_BIAS_ON                   _MK_ENUM_CONST(1)

#define PMC_IMPL_IO_DPD_REQ_0_PEX_CLK3_SHIFT                    _MK_SHIFT_CONST(5)
#define PMC_IMPL_IO_DPD_REQ_0_PEX_CLK3_FIELD                    _MK_FIELD_CONST(0x1, PMC_IMPL_IO_DPD_REQ_0_PEX_CLK3_SHIFT)
#define PMC_IMPL_IO_DPD_REQ_0_PEX_CLK3_RANGE                    5:5
#define PMC_IMPL_IO_DPD_REQ_0_PEX_CLK3_WOFFSET                  0x0
#define PMC_IMPL_IO_DPD_REQ_0_PEX_CLK3_DEFAULT                  _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD_REQ_0_PEX_CLK3_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DPD_REQ_0_PEX_CLK3_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD_REQ_0_PEX_CLK3_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD_REQ_0_PEX_CLK3_PARITY_PROTECTION                        _MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DPD_REQ_0_PEX_CLK3_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DPD_REQ_0_PEX_CLK3_OFF                      _MK_ENUM_CONST(0)
#define PMC_IMPL_IO_DPD_REQ_0_PEX_CLK3_ON                       _MK_ENUM_CONST(1)

#define PMC_IMPL_IO_DPD_REQ_0_PEX_CLK2_SHIFT                    _MK_SHIFT_CONST(6)
#define PMC_IMPL_IO_DPD_REQ_0_PEX_CLK2_FIELD                    _MK_FIELD_CONST(0x1, PMC_IMPL_IO_DPD_REQ_0_PEX_CLK2_SHIFT)
#define PMC_IMPL_IO_DPD_REQ_0_PEX_CLK2_RANGE                    6:6
#define PMC_IMPL_IO_DPD_REQ_0_PEX_CLK2_WOFFSET                  0x0
#define PMC_IMPL_IO_DPD_REQ_0_PEX_CLK2_DEFAULT                  _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD_REQ_0_PEX_CLK2_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DPD_REQ_0_PEX_CLK2_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD_REQ_0_PEX_CLK2_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD_REQ_0_PEX_CLK2_PARITY_PROTECTION                        _MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DPD_REQ_0_PEX_CLK2_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DPD_REQ_0_PEX_CLK2_OFF                      _MK_ENUM_CONST(0)
#define PMC_IMPL_IO_DPD_REQ_0_PEX_CLK2_ON                       _MK_ENUM_CONST(1)

#define PMC_IMPL_IO_DPD_REQ_0_PEX_CLK1_SHIFT                    _MK_SHIFT_CONST(7)
#define PMC_IMPL_IO_DPD_REQ_0_PEX_CLK1_FIELD                    _MK_FIELD_CONST(0x1, PMC_IMPL_IO_DPD_REQ_0_PEX_CLK1_SHIFT)
#define PMC_IMPL_IO_DPD_REQ_0_PEX_CLK1_RANGE                    7:7
#define PMC_IMPL_IO_DPD_REQ_0_PEX_CLK1_WOFFSET                  0x0
#define PMC_IMPL_IO_DPD_REQ_0_PEX_CLK1_DEFAULT                  _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD_REQ_0_PEX_CLK1_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DPD_REQ_0_PEX_CLK1_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD_REQ_0_PEX_CLK1_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD_REQ_0_PEX_CLK1_PARITY_PROTECTION                        _MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DPD_REQ_0_PEX_CLK1_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DPD_REQ_0_PEX_CLK1_OFF                      _MK_ENUM_CONST(0)
#define PMC_IMPL_IO_DPD_REQ_0_PEX_CLK1_ON                       _MK_ENUM_CONST(1)

#define PMC_IMPL_IO_DPD_REQ_0_EQOS_SHIFT                        _MK_SHIFT_CONST(8)
#define PMC_IMPL_IO_DPD_REQ_0_EQOS_FIELD                        _MK_FIELD_CONST(0x1, PMC_IMPL_IO_DPD_REQ_0_EQOS_SHIFT)
#define PMC_IMPL_IO_DPD_REQ_0_EQOS_RANGE                        8:8
#define PMC_IMPL_IO_DPD_REQ_0_EQOS_WOFFSET                      0x0
#define PMC_IMPL_IO_DPD_REQ_0_EQOS_DEFAULT                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD_REQ_0_EQOS_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DPD_REQ_0_EQOS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD_REQ_0_EQOS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD_REQ_0_EQOS_PARITY_PROTECTION                    _MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DPD_REQ_0_EQOS_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DPD_REQ_0_EQOS_OFF                  _MK_ENUM_CONST(0)
#define PMC_IMPL_IO_DPD_REQ_0_EQOS_ON                   _MK_ENUM_CONST(1)

#define PMC_IMPL_IO_DPD_REQ_0_PEX_CLK_2_BIAS_SHIFT                      _MK_SHIFT_CONST(9)
#define PMC_IMPL_IO_DPD_REQ_0_PEX_CLK_2_BIAS_FIELD                      _MK_FIELD_CONST(0x1, PMC_IMPL_IO_DPD_REQ_0_PEX_CLK_2_BIAS_SHIFT)
#define PMC_IMPL_IO_DPD_REQ_0_PEX_CLK_2_BIAS_RANGE                      9:9
#define PMC_IMPL_IO_DPD_REQ_0_PEX_CLK_2_BIAS_WOFFSET                    0x0
#define PMC_IMPL_IO_DPD_REQ_0_PEX_CLK_2_BIAS_DEFAULT                    _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD_REQ_0_PEX_CLK_2_BIAS_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DPD_REQ_0_PEX_CLK_2_BIAS_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD_REQ_0_PEX_CLK_2_BIAS_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD_REQ_0_PEX_CLK_2_BIAS_PARITY_PROTECTION                  _MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DPD_REQ_0_PEX_CLK_2_BIAS_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DPD_REQ_0_PEX_CLK_2_BIAS_OFF                        _MK_ENUM_CONST(0)
#define PMC_IMPL_IO_DPD_REQ_0_PEX_CLK_2_BIAS_ON                 _MK_ENUM_CONST(1)

#define PMC_IMPL_IO_DPD_REQ_0_PEX_CLK_2_SHIFT                   _MK_SHIFT_CONST(10)
#define PMC_IMPL_IO_DPD_REQ_0_PEX_CLK_2_FIELD                   _MK_FIELD_CONST(0x1, PMC_IMPL_IO_DPD_REQ_0_PEX_CLK_2_SHIFT)
#define PMC_IMPL_IO_DPD_REQ_0_PEX_CLK_2_RANGE                   10:10
#define PMC_IMPL_IO_DPD_REQ_0_PEX_CLK_2_WOFFSET                 0x0
#define PMC_IMPL_IO_DPD_REQ_0_PEX_CLK_2_DEFAULT                 _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD_REQ_0_PEX_CLK_2_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DPD_REQ_0_PEX_CLK_2_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD_REQ_0_PEX_CLK_2_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD_REQ_0_PEX_CLK_2_PARITY_PROTECTION                       _MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DPD_REQ_0_PEX_CLK_2_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DPD_REQ_0_PEX_CLK_2_OFF                     _MK_ENUM_CONST(0)
#define PMC_IMPL_IO_DPD_REQ_0_PEX_CLK_2_ON                      _MK_ENUM_CONST(1)

#define PMC_IMPL_IO_DPD_REQ_0_DAP3_SHIFT                        _MK_SHIFT_CONST(11)
#define PMC_IMPL_IO_DPD_REQ_0_DAP3_FIELD                        _MK_FIELD_CONST(0x1, PMC_IMPL_IO_DPD_REQ_0_DAP3_SHIFT)
#define PMC_IMPL_IO_DPD_REQ_0_DAP3_RANGE                        11:11
#define PMC_IMPL_IO_DPD_REQ_0_DAP3_WOFFSET                      0x0
#define PMC_IMPL_IO_DPD_REQ_0_DAP3_DEFAULT                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD_REQ_0_DAP3_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DPD_REQ_0_DAP3_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD_REQ_0_DAP3_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD_REQ_0_DAP3_PARITY_PROTECTION                    _MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DPD_REQ_0_DAP3_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DPD_REQ_0_DAP3_OFF                  _MK_ENUM_CONST(0)
#define PMC_IMPL_IO_DPD_REQ_0_DAP3_ON                   _MK_ENUM_CONST(1)

#define PMC_IMPL_IO_DPD_REQ_0_DAP5_SHIFT                        _MK_SHIFT_CONST(12)
#define PMC_IMPL_IO_DPD_REQ_0_DAP5_FIELD                        _MK_FIELD_CONST(0x1, PMC_IMPL_IO_DPD_REQ_0_DAP5_SHIFT)
#define PMC_IMPL_IO_DPD_REQ_0_DAP5_RANGE                        12:12
#define PMC_IMPL_IO_DPD_REQ_0_DAP5_WOFFSET                      0x0
#define PMC_IMPL_IO_DPD_REQ_0_DAP5_DEFAULT                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD_REQ_0_DAP5_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DPD_REQ_0_DAP5_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD_REQ_0_DAP5_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD_REQ_0_DAP5_PARITY_PROTECTION                    _MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DPD_REQ_0_DAP5_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DPD_REQ_0_DAP5_OFF                  _MK_ENUM_CONST(0)
#define PMC_IMPL_IO_DPD_REQ_0_DAP5_ON                   _MK_ENUM_CONST(1)

#define PMC_IMPL_IO_DPD_REQ_0_UART_SHIFT                        _MK_SHIFT_CONST(14)
#define PMC_IMPL_IO_DPD_REQ_0_UART_FIELD                        _MK_FIELD_CONST(0x1, PMC_IMPL_IO_DPD_REQ_0_UART_SHIFT)
#define PMC_IMPL_IO_DPD_REQ_0_UART_RANGE                        14:14
#define PMC_IMPL_IO_DPD_REQ_0_UART_WOFFSET                      0x0
#define PMC_IMPL_IO_DPD_REQ_0_UART_DEFAULT                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD_REQ_0_UART_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DPD_REQ_0_UART_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD_REQ_0_UART_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD_REQ_0_UART_PARITY_PROTECTION                    _MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DPD_REQ_0_UART_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DPD_REQ_0_UART_OFF                  _MK_ENUM_CONST(0)
#define PMC_IMPL_IO_DPD_REQ_0_UART_ON                   _MK_ENUM_CONST(1)

#define PMC_IMPL_IO_DPD_REQ_0_PWR_CTL_SHIFT                     _MK_SHIFT_CONST(15)
#define PMC_IMPL_IO_DPD_REQ_0_PWR_CTL_FIELD                     _MK_FIELD_CONST(0x1, PMC_IMPL_IO_DPD_REQ_0_PWR_CTL_SHIFT)
#define PMC_IMPL_IO_DPD_REQ_0_PWR_CTL_RANGE                     15:15
#define PMC_IMPL_IO_DPD_REQ_0_PWR_CTL_WOFFSET                   0x0
#define PMC_IMPL_IO_DPD_REQ_0_PWR_CTL_DEFAULT                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD_REQ_0_PWR_CTL_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DPD_REQ_0_PWR_CTL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD_REQ_0_PWR_CTL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD_REQ_0_PWR_CTL_PARITY_PROTECTION                 _MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DPD_REQ_0_PWR_CTL_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DPD_REQ_0_PWR_CTL_OFF                       _MK_ENUM_CONST(0)
#define PMC_IMPL_IO_DPD_REQ_0_PWR_CTL_ON                        _MK_ENUM_CONST(1)

#define PMC_IMPL_IO_DPD_REQ_0_SOC_GPIO53_SHIFT                  _MK_SHIFT_CONST(16)
#define PMC_IMPL_IO_DPD_REQ_0_SOC_GPIO53_FIELD                  _MK_FIELD_CONST(0x1, PMC_IMPL_IO_DPD_REQ_0_SOC_GPIO53_SHIFT)
#define PMC_IMPL_IO_DPD_REQ_0_SOC_GPIO53_RANGE                  16:16
#define PMC_IMPL_IO_DPD_REQ_0_SOC_GPIO53_WOFFSET                        0x0
#define PMC_IMPL_IO_DPD_REQ_0_SOC_GPIO53_DEFAULT                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD_REQ_0_SOC_GPIO53_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DPD_REQ_0_SOC_GPIO53_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD_REQ_0_SOC_GPIO53_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD_REQ_0_SOC_GPIO53_PARITY_PROTECTION                      _MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DPD_REQ_0_SOC_GPIO53_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DPD_REQ_0_SOC_GPIO53_OFF                    _MK_ENUM_CONST(0)
#define PMC_IMPL_IO_DPD_REQ_0_SOC_GPIO53_ON                     _MK_ENUM_CONST(1)

#define PMC_IMPL_IO_DPD_REQ_0_AUDIO_SHIFT                       _MK_SHIFT_CONST(17)
#define PMC_IMPL_IO_DPD_REQ_0_AUDIO_FIELD                       _MK_FIELD_CONST(0x1, PMC_IMPL_IO_DPD_REQ_0_AUDIO_SHIFT)
#define PMC_IMPL_IO_DPD_REQ_0_AUDIO_RANGE                       17:17
#define PMC_IMPL_IO_DPD_REQ_0_AUDIO_WOFFSET                     0x0
#define PMC_IMPL_IO_DPD_REQ_0_AUDIO_DEFAULT                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD_REQ_0_AUDIO_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DPD_REQ_0_AUDIO_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD_REQ_0_AUDIO_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD_REQ_0_AUDIO_PARITY_PROTECTION                   _MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DPD_REQ_0_AUDIO_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DPD_REQ_0_AUDIO_OFF                 _MK_ENUM_CONST(0)
#define PMC_IMPL_IO_DPD_REQ_0_AUDIO_ON                  _MK_ENUM_CONST(1)

#define PMC_IMPL_IO_DPD_REQ_0_GP_PWM2_SHIFT                     _MK_SHIFT_CONST(18)
#define PMC_IMPL_IO_DPD_REQ_0_GP_PWM2_FIELD                     _MK_FIELD_CONST(0x1, PMC_IMPL_IO_DPD_REQ_0_GP_PWM2_SHIFT)
#define PMC_IMPL_IO_DPD_REQ_0_GP_PWM2_RANGE                     18:18
#define PMC_IMPL_IO_DPD_REQ_0_GP_PWM2_WOFFSET                   0x0
#define PMC_IMPL_IO_DPD_REQ_0_GP_PWM2_DEFAULT                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD_REQ_0_GP_PWM2_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DPD_REQ_0_GP_PWM2_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD_REQ_0_GP_PWM2_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD_REQ_0_GP_PWM2_PARITY_PROTECTION                 _MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DPD_REQ_0_GP_PWM2_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DPD_REQ_0_GP_PWM2_OFF                       _MK_ENUM_CONST(0)
#define PMC_IMPL_IO_DPD_REQ_0_GP_PWM2_ON                        _MK_ENUM_CONST(1)

#define PMC_IMPL_IO_DPD_REQ_0_GP_PWM3_SHIFT                     _MK_SHIFT_CONST(19)
#define PMC_IMPL_IO_DPD_REQ_0_GP_PWM3_FIELD                     _MK_FIELD_CONST(0x1, PMC_IMPL_IO_DPD_REQ_0_GP_PWM3_SHIFT)
#define PMC_IMPL_IO_DPD_REQ_0_GP_PWM3_RANGE                     19:19
#define PMC_IMPL_IO_DPD_REQ_0_GP_PWM3_WOFFSET                   0x0
#define PMC_IMPL_IO_DPD_REQ_0_GP_PWM3_DEFAULT                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD_REQ_0_GP_PWM3_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DPD_REQ_0_GP_PWM3_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD_REQ_0_GP_PWM3_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD_REQ_0_GP_PWM3_PARITY_PROTECTION                 _MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DPD_REQ_0_GP_PWM3_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DPD_REQ_0_GP_PWM3_OFF                       _MK_ENUM_CONST(0)
#define PMC_IMPL_IO_DPD_REQ_0_GP_PWM3_ON                        _MK_ENUM_CONST(1)

#define PMC_IMPL_IO_DPD_REQ_0_SOC_GPIO12_SHIFT                  _MK_SHIFT_CONST(20)
#define PMC_IMPL_IO_DPD_REQ_0_SOC_GPIO12_FIELD                  _MK_FIELD_CONST(0x1, PMC_IMPL_IO_DPD_REQ_0_SOC_GPIO12_SHIFT)
#define PMC_IMPL_IO_DPD_REQ_0_SOC_GPIO12_RANGE                  20:20
#define PMC_IMPL_IO_DPD_REQ_0_SOC_GPIO12_WOFFSET                        0x0
#define PMC_IMPL_IO_DPD_REQ_0_SOC_GPIO12_DEFAULT                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD_REQ_0_SOC_GPIO12_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DPD_REQ_0_SOC_GPIO12_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD_REQ_0_SOC_GPIO12_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD_REQ_0_SOC_GPIO12_PARITY_PROTECTION                      _MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DPD_REQ_0_SOC_GPIO12_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DPD_REQ_0_SOC_GPIO12_OFF                    _MK_ENUM_CONST(0)
#define PMC_IMPL_IO_DPD_REQ_0_SOC_GPIO12_ON                     _MK_ENUM_CONST(1)

#define PMC_IMPL_IO_DPD_REQ_0_SOC_GPIO13_SHIFT                  _MK_SHIFT_CONST(21)
#define PMC_IMPL_IO_DPD_REQ_0_SOC_GPIO13_FIELD                  _MK_FIELD_CONST(0x1, PMC_IMPL_IO_DPD_REQ_0_SOC_GPIO13_SHIFT)
#define PMC_IMPL_IO_DPD_REQ_0_SOC_GPIO13_RANGE                  21:21
#define PMC_IMPL_IO_DPD_REQ_0_SOC_GPIO13_WOFFSET                        0x0
#define PMC_IMPL_IO_DPD_REQ_0_SOC_GPIO13_DEFAULT                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD_REQ_0_SOC_GPIO13_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DPD_REQ_0_SOC_GPIO13_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD_REQ_0_SOC_GPIO13_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD_REQ_0_SOC_GPIO13_PARITY_PROTECTION                      _MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DPD_REQ_0_SOC_GPIO13_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DPD_REQ_0_SOC_GPIO13_OFF                    _MK_ENUM_CONST(0)
#define PMC_IMPL_IO_DPD_REQ_0_SOC_GPIO13_ON                     _MK_ENUM_CONST(1)

#define PMC_IMPL_IO_DPD_REQ_0_SOC_GPIO10_SHIFT                  _MK_SHIFT_CONST(22)
#define PMC_IMPL_IO_DPD_REQ_0_SOC_GPIO10_FIELD                  _MK_FIELD_CONST(0x1, PMC_IMPL_IO_DPD_REQ_0_SOC_GPIO10_SHIFT)
#define PMC_IMPL_IO_DPD_REQ_0_SOC_GPIO10_RANGE                  22:22
#define PMC_IMPL_IO_DPD_REQ_0_SOC_GPIO10_WOFFSET                        0x0
#define PMC_IMPL_IO_DPD_REQ_0_SOC_GPIO10_DEFAULT                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD_REQ_0_SOC_GPIO10_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DPD_REQ_0_SOC_GPIO10_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD_REQ_0_SOC_GPIO10_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD_REQ_0_SOC_GPIO10_PARITY_PROTECTION                      _MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DPD_REQ_0_SOC_GPIO10_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DPD_REQ_0_SOC_GPIO10_OFF                    _MK_ENUM_CONST(0)
#define PMC_IMPL_IO_DPD_REQ_0_SOC_GPIO10_ON                     _MK_ENUM_CONST(1)

#define PMC_IMPL_IO_DPD_REQ_0_UART4_SHIFT                       _MK_SHIFT_CONST(23)
#define PMC_IMPL_IO_DPD_REQ_0_UART4_FIELD                       _MK_FIELD_CONST(0x1, PMC_IMPL_IO_DPD_REQ_0_UART4_SHIFT)
#define PMC_IMPL_IO_DPD_REQ_0_UART4_RANGE                       23:23
#define PMC_IMPL_IO_DPD_REQ_0_UART4_WOFFSET                     0x0
#define PMC_IMPL_IO_DPD_REQ_0_UART4_DEFAULT                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD_REQ_0_UART4_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DPD_REQ_0_UART4_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD_REQ_0_UART4_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD_REQ_0_UART4_PARITY_PROTECTION                   _MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DPD_REQ_0_UART4_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DPD_REQ_0_UART4_OFF                 _MK_ENUM_CONST(0)
#define PMC_IMPL_IO_DPD_REQ_0_UART4_ON                  _MK_ENUM_CONST(1)

#define PMC_IMPL_IO_DPD_REQ_0_UART5_SHIFT                       _MK_SHIFT_CONST(24)
#define PMC_IMPL_IO_DPD_REQ_0_UART5_FIELD                       _MK_FIELD_CONST(0x1, PMC_IMPL_IO_DPD_REQ_0_UART5_SHIFT)
#define PMC_IMPL_IO_DPD_REQ_0_UART5_RANGE                       24:24
#define PMC_IMPL_IO_DPD_REQ_0_UART5_WOFFSET                     0x0
#define PMC_IMPL_IO_DPD_REQ_0_UART5_DEFAULT                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD_REQ_0_UART5_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DPD_REQ_0_UART5_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD_REQ_0_UART5_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD_REQ_0_UART5_PARITY_PROTECTION                   _MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DPD_REQ_0_UART5_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DPD_REQ_0_UART5_OFF                 _MK_ENUM_CONST(0)
#define PMC_IMPL_IO_DPD_REQ_0_UART5_ON                  _MK_ENUM_CONST(1)

#define PMC_IMPL_IO_DPD_REQ_0_DBG_SHIFT                 _MK_SHIFT_CONST(25)
#define PMC_IMPL_IO_DPD_REQ_0_DBG_FIELD                 _MK_FIELD_CONST(0x1, PMC_IMPL_IO_DPD_REQ_0_DBG_SHIFT)
#define PMC_IMPL_IO_DPD_REQ_0_DBG_RANGE                 25:25
#define PMC_IMPL_IO_DPD_REQ_0_DBG_WOFFSET                       0x0
#define PMC_IMPL_IO_DPD_REQ_0_DBG_DEFAULT                       _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD_REQ_0_DBG_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DPD_REQ_0_DBG_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD_REQ_0_DBG_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD_REQ_0_DBG_PARITY_PROTECTION                     _MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DPD_REQ_0_DBG_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DPD_REQ_0_DBG_OFF                   _MK_ENUM_CONST(0)
#define PMC_IMPL_IO_DPD_REQ_0_DBG_ON                    _MK_ENUM_CONST(1)

#define PMC_IMPL_IO_DPD_REQ_0_HDMI_DP3_SHIFT                    _MK_SHIFT_CONST(26)
#define PMC_IMPL_IO_DPD_REQ_0_HDMI_DP3_FIELD                    _MK_FIELD_CONST(0x1, PMC_IMPL_IO_DPD_REQ_0_HDMI_DP3_SHIFT)
#define PMC_IMPL_IO_DPD_REQ_0_HDMI_DP3_RANGE                    26:26
#define PMC_IMPL_IO_DPD_REQ_0_HDMI_DP3_WOFFSET                  0x0
#define PMC_IMPL_IO_DPD_REQ_0_HDMI_DP3_DEFAULT                  _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD_REQ_0_HDMI_DP3_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DPD_REQ_0_HDMI_DP3_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD_REQ_0_HDMI_DP3_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD_REQ_0_HDMI_DP3_PARITY_PROTECTION                        _MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DPD_REQ_0_HDMI_DP3_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DPD_REQ_0_HDMI_DP3_OFF                      _MK_ENUM_CONST(0)
#define PMC_IMPL_IO_DPD_REQ_0_HDMI_DP3_ON                       _MK_ENUM_CONST(1)

#define PMC_IMPL_IO_DPD_REQ_0_HDMI_DP2_SHIFT                    _MK_SHIFT_CONST(27)
#define PMC_IMPL_IO_DPD_REQ_0_HDMI_DP2_FIELD                    _MK_FIELD_CONST(0x1, PMC_IMPL_IO_DPD_REQ_0_HDMI_DP2_SHIFT)
#define PMC_IMPL_IO_DPD_REQ_0_HDMI_DP2_RANGE                    27:27
#define PMC_IMPL_IO_DPD_REQ_0_HDMI_DP2_WOFFSET                  0x0
#define PMC_IMPL_IO_DPD_REQ_0_HDMI_DP2_DEFAULT                  _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD_REQ_0_HDMI_DP2_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DPD_REQ_0_HDMI_DP2_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD_REQ_0_HDMI_DP2_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD_REQ_0_HDMI_DP2_PARITY_PROTECTION                        _MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DPD_REQ_0_HDMI_DP2_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DPD_REQ_0_HDMI_DP2_OFF                      _MK_ENUM_CONST(0)
#define PMC_IMPL_IO_DPD_REQ_0_HDMI_DP2_ON                       _MK_ENUM_CONST(1)

#define PMC_IMPL_IO_DPD_REQ_0_HDMI_DP0_SHIFT                    _MK_SHIFT_CONST(28)
#define PMC_IMPL_IO_DPD_REQ_0_HDMI_DP0_FIELD                    _MK_FIELD_CONST(0x1, PMC_IMPL_IO_DPD_REQ_0_HDMI_DP0_SHIFT)
#define PMC_IMPL_IO_DPD_REQ_0_HDMI_DP0_RANGE                    28:28
#define PMC_IMPL_IO_DPD_REQ_0_HDMI_DP0_WOFFSET                  0x0
#define PMC_IMPL_IO_DPD_REQ_0_HDMI_DP0_DEFAULT                  _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD_REQ_0_HDMI_DP0_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DPD_REQ_0_HDMI_DP0_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD_REQ_0_HDMI_DP0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD_REQ_0_HDMI_DP0_PARITY_PROTECTION                        _MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DPD_REQ_0_HDMI_DP0_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DPD_REQ_0_HDMI_DP0_OFF                      _MK_ENUM_CONST(0)
#define PMC_IMPL_IO_DPD_REQ_0_HDMI_DP0_ON                       _MK_ENUM_CONST(1)

#define PMC_IMPL_IO_DPD_REQ_0_HDMI_DP1_SHIFT                    _MK_SHIFT_CONST(29)
#define PMC_IMPL_IO_DPD_REQ_0_HDMI_DP1_FIELD                    _MK_FIELD_CONST(0x1, PMC_IMPL_IO_DPD_REQ_0_HDMI_DP1_SHIFT)
#define PMC_IMPL_IO_DPD_REQ_0_HDMI_DP1_RANGE                    29:29
#define PMC_IMPL_IO_DPD_REQ_0_HDMI_DP1_WOFFSET                  0x0
#define PMC_IMPL_IO_DPD_REQ_0_HDMI_DP1_DEFAULT                  _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD_REQ_0_HDMI_DP1_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DPD_REQ_0_HDMI_DP1_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD_REQ_0_HDMI_DP1_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD_REQ_0_HDMI_DP1_PARITY_PROTECTION                        _MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DPD_REQ_0_HDMI_DP1_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DPD_REQ_0_HDMI_DP1_OFF                      _MK_ENUM_CONST(0)
#define PMC_IMPL_IO_DPD_REQ_0_HDMI_DP1_ON                       _MK_ENUM_CONST(1)

#define PMC_IMPL_IO_DPD_REQ_0_CODE_SHIFT                        _MK_SHIFT_CONST(30)
#define PMC_IMPL_IO_DPD_REQ_0_CODE_FIELD                        _MK_FIELD_CONST(0x3, PMC_IMPL_IO_DPD_REQ_0_CODE_SHIFT)
#define PMC_IMPL_IO_DPD_REQ_0_CODE_RANGE                        31:30
#define PMC_IMPL_IO_DPD_REQ_0_CODE_WOFFSET                      0x0
#define PMC_IMPL_IO_DPD_REQ_0_CODE_DEFAULT                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD_REQ_0_CODE_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define PMC_IMPL_IO_DPD_REQ_0_CODE_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD_REQ_0_CODE_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD_REQ_0_CODE_PARITY_PROTECTION                    _MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DPD_REQ_0_CODE_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DPD_REQ_0_CODE_IDLE                 _MK_ENUM_CONST(0)
#define PMC_IMPL_IO_DPD_REQ_0_CODE_DPD_OFF                      _MK_ENUM_CONST(1)
#define PMC_IMPL_IO_DPD_REQ_0_CODE_DPD_ON                       _MK_ENUM_CONST(2)


// Register PMC_IMPL_IO_DPD_STATUS_0
#define PMC_IMPL_IO_DPD_STATUS_0                        _MK_ADDR_CONST(0x78)
#define PMC_IMPL_IO_DPD_STATUS_0_SECURE                         0x0
#define PMC_IMPL_IO_DPD_STATUS_0_DUAL                   0x0
#define PMC_IMPL_IO_DPD_STATUS_0_SCR                    IODPD1_SCR_0
#define PMC_IMPL_IO_DPD_STATUS_0_WORD_COUNT                     0x1
#define PMC_IMPL_IO_DPD_STATUS_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD_STATUS_0_RESET_MASK                     _MK_MASK_CONST(0x3fffdffb)
#define PMC_IMPL_IO_DPD_STATUS_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD_STATUS_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD_STATUS_0_READ_MASK                      _MK_MASK_CONST(0x3fffdffb)
#define PMC_IMPL_IO_DPD_STATUS_0_WRITE_MASK                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD_STATUS_0_CSIA_SHIFT                     _MK_SHIFT_CONST(0)
#define PMC_IMPL_IO_DPD_STATUS_0_CSIA_FIELD                     _MK_FIELD_CONST(0x1, PMC_IMPL_IO_DPD_STATUS_0_CSIA_SHIFT)
#define PMC_IMPL_IO_DPD_STATUS_0_CSIA_RANGE                     0:0
#define PMC_IMPL_IO_DPD_STATUS_0_CSIA_WOFFSET                   0x0
#define PMC_IMPL_IO_DPD_STATUS_0_CSIA_DEFAULT                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD_STATUS_0_CSIA_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DPD_STATUS_0_CSIA_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD_STATUS_0_CSIA_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD_STATUS_0_CSIA_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD_STATUS_0_CSIA_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DPD_STATUS_0_CSIA_OFF                       _MK_ENUM_CONST(0)
#define PMC_IMPL_IO_DPD_STATUS_0_CSIA_ON                        _MK_ENUM_CONST(1)

#define PMC_IMPL_IO_DPD_STATUS_0_CSIB_SHIFT                     _MK_SHIFT_CONST(1)
#define PMC_IMPL_IO_DPD_STATUS_0_CSIB_FIELD                     _MK_FIELD_CONST(0x1, PMC_IMPL_IO_DPD_STATUS_0_CSIB_SHIFT)
#define PMC_IMPL_IO_DPD_STATUS_0_CSIB_RANGE                     1:1
#define PMC_IMPL_IO_DPD_STATUS_0_CSIB_WOFFSET                   0x0
#define PMC_IMPL_IO_DPD_STATUS_0_CSIB_DEFAULT                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD_STATUS_0_CSIB_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DPD_STATUS_0_CSIB_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD_STATUS_0_CSIB_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD_STATUS_0_CSIB_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD_STATUS_0_CSIB_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DPD_STATUS_0_CSIB_OFF                       _MK_ENUM_CONST(0)
#define PMC_IMPL_IO_DPD_STATUS_0_CSIB_ON                        _MK_ENUM_CONST(1)

#define PMC_IMPL_IO_DPD_STATUS_0_MIPI_BIAS_SHIFT                        _MK_SHIFT_CONST(3)
#define PMC_IMPL_IO_DPD_STATUS_0_MIPI_BIAS_FIELD                        _MK_FIELD_CONST(0x1, PMC_IMPL_IO_DPD_STATUS_0_MIPI_BIAS_SHIFT)
#define PMC_IMPL_IO_DPD_STATUS_0_MIPI_BIAS_RANGE                        3:3
#define PMC_IMPL_IO_DPD_STATUS_0_MIPI_BIAS_WOFFSET                      0x0
#define PMC_IMPL_IO_DPD_STATUS_0_MIPI_BIAS_DEFAULT                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD_STATUS_0_MIPI_BIAS_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DPD_STATUS_0_MIPI_BIAS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD_STATUS_0_MIPI_BIAS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD_STATUS_0_MIPI_BIAS_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD_STATUS_0_MIPI_BIAS_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DPD_STATUS_0_MIPI_BIAS_OFF                  _MK_ENUM_CONST(0)
#define PMC_IMPL_IO_DPD_STATUS_0_MIPI_BIAS_ON                   _MK_ENUM_CONST(1)

#define PMC_IMPL_IO_DPD_STATUS_0_PEX_CLK_BIAS_SHIFT                     _MK_SHIFT_CONST(4)
#define PMC_IMPL_IO_DPD_STATUS_0_PEX_CLK_BIAS_FIELD                     _MK_FIELD_CONST(0x1, PMC_IMPL_IO_DPD_STATUS_0_PEX_CLK_BIAS_SHIFT)
#define PMC_IMPL_IO_DPD_STATUS_0_PEX_CLK_BIAS_RANGE                     4:4
#define PMC_IMPL_IO_DPD_STATUS_0_PEX_CLK_BIAS_WOFFSET                   0x0
#define PMC_IMPL_IO_DPD_STATUS_0_PEX_CLK_BIAS_DEFAULT                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD_STATUS_0_PEX_CLK_BIAS_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DPD_STATUS_0_PEX_CLK_BIAS_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD_STATUS_0_PEX_CLK_BIAS_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD_STATUS_0_PEX_CLK_BIAS_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD_STATUS_0_PEX_CLK_BIAS_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DPD_STATUS_0_PEX_CLK_BIAS_OFF                       _MK_ENUM_CONST(0)
#define PMC_IMPL_IO_DPD_STATUS_0_PEX_CLK_BIAS_ON                        _MK_ENUM_CONST(1)

#define PMC_IMPL_IO_DPD_STATUS_0_PEX_CLK3_SHIFT                 _MK_SHIFT_CONST(5)
#define PMC_IMPL_IO_DPD_STATUS_0_PEX_CLK3_FIELD                 _MK_FIELD_CONST(0x1, PMC_IMPL_IO_DPD_STATUS_0_PEX_CLK3_SHIFT)
#define PMC_IMPL_IO_DPD_STATUS_0_PEX_CLK3_RANGE                 5:5
#define PMC_IMPL_IO_DPD_STATUS_0_PEX_CLK3_WOFFSET                       0x0
#define PMC_IMPL_IO_DPD_STATUS_0_PEX_CLK3_DEFAULT                       _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD_STATUS_0_PEX_CLK3_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DPD_STATUS_0_PEX_CLK3_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD_STATUS_0_PEX_CLK3_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD_STATUS_0_PEX_CLK3_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD_STATUS_0_PEX_CLK3_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DPD_STATUS_0_PEX_CLK3_OFF                   _MK_ENUM_CONST(0)
#define PMC_IMPL_IO_DPD_STATUS_0_PEX_CLK3_ON                    _MK_ENUM_CONST(1)

#define PMC_IMPL_IO_DPD_STATUS_0_PEX_CLK2_SHIFT                 _MK_SHIFT_CONST(6)
#define PMC_IMPL_IO_DPD_STATUS_0_PEX_CLK2_FIELD                 _MK_FIELD_CONST(0x1, PMC_IMPL_IO_DPD_STATUS_0_PEX_CLK2_SHIFT)
#define PMC_IMPL_IO_DPD_STATUS_0_PEX_CLK2_RANGE                 6:6
#define PMC_IMPL_IO_DPD_STATUS_0_PEX_CLK2_WOFFSET                       0x0
#define PMC_IMPL_IO_DPD_STATUS_0_PEX_CLK2_DEFAULT                       _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD_STATUS_0_PEX_CLK2_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DPD_STATUS_0_PEX_CLK2_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD_STATUS_0_PEX_CLK2_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD_STATUS_0_PEX_CLK2_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD_STATUS_0_PEX_CLK2_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DPD_STATUS_0_PEX_CLK2_OFF                   _MK_ENUM_CONST(0)
#define PMC_IMPL_IO_DPD_STATUS_0_PEX_CLK2_ON                    _MK_ENUM_CONST(1)

#define PMC_IMPL_IO_DPD_STATUS_0_PEX_CLK1_SHIFT                 _MK_SHIFT_CONST(7)
#define PMC_IMPL_IO_DPD_STATUS_0_PEX_CLK1_FIELD                 _MK_FIELD_CONST(0x1, PMC_IMPL_IO_DPD_STATUS_0_PEX_CLK1_SHIFT)
#define PMC_IMPL_IO_DPD_STATUS_0_PEX_CLK1_RANGE                 7:7
#define PMC_IMPL_IO_DPD_STATUS_0_PEX_CLK1_WOFFSET                       0x0
#define PMC_IMPL_IO_DPD_STATUS_0_PEX_CLK1_DEFAULT                       _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD_STATUS_0_PEX_CLK1_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DPD_STATUS_0_PEX_CLK1_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD_STATUS_0_PEX_CLK1_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD_STATUS_0_PEX_CLK1_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD_STATUS_0_PEX_CLK1_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DPD_STATUS_0_PEX_CLK1_OFF                   _MK_ENUM_CONST(0)
#define PMC_IMPL_IO_DPD_STATUS_0_PEX_CLK1_ON                    _MK_ENUM_CONST(1)

#define PMC_IMPL_IO_DPD_STATUS_0_EQOS_SHIFT                     _MK_SHIFT_CONST(8)
#define PMC_IMPL_IO_DPD_STATUS_0_EQOS_FIELD                     _MK_FIELD_CONST(0x1, PMC_IMPL_IO_DPD_STATUS_0_EQOS_SHIFT)
#define PMC_IMPL_IO_DPD_STATUS_0_EQOS_RANGE                     8:8
#define PMC_IMPL_IO_DPD_STATUS_0_EQOS_WOFFSET                   0x0
#define PMC_IMPL_IO_DPD_STATUS_0_EQOS_DEFAULT                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD_STATUS_0_EQOS_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DPD_STATUS_0_EQOS_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD_STATUS_0_EQOS_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD_STATUS_0_EQOS_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD_STATUS_0_EQOS_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DPD_STATUS_0_EQOS_OFF                       _MK_ENUM_CONST(0)
#define PMC_IMPL_IO_DPD_STATUS_0_EQOS_ON                        _MK_ENUM_CONST(1)

#define PMC_IMPL_IO_DPD_STATUS_0_PEX_CLK_2_BIAS_SHIFT                   _MK_SHIFT_CONST(9)
#define PMC_IMPL_IO_DPD_STATUS_0_PEX_CLK_2_BIAS_FIELD                   _MK_FIELD_CONST(0x1, PMC_IMPL_IO_DPD_STATUS_0_PEX_CLK_2_BIAS_SHIFT)
#define PMC_IMPL_IO_DPD_STATUS_0_PEX_CLK_2_BIAS_RANGE                   9:9
#define PMC_IMPL_IO_DPD_STATUS_0_PEX_CLK_2_BIAS_WOFFSET                 0x0
#define PMC_IMPL_IO_DPD_STATUS_0_PEX_CLK_2_BIAS_DEFAULT                 _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD_STATUS_0_PEX_CLK_2_BIAS_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DPD_STATUS_0_PEX_CLK_2_BIAS_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD_STATUS_0_PEX_CLK_2_BIAS_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD_STATUS_0_PEX_CLK_2_BIAS_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD_STATUS_0_PEX_CLK_2_BIAS_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DPD_STATUS_0_PEX_CLK_2_BIAS_OFF                     _MK_ENUM_CONST(0)
#define PMC_IMPL_IO_DPD_STATUS_0_PEX_CLK_2_BIAS_ON                      _MK_ENUM_CONST(1)

#define PMC_IMPL_IO_DPD_STATUS_0_PEX_CLK_2_SHIFT                        _MK_SHIFT_CONST(10)
#define PMC_IMPL_IO_DPD_STATUS_0_PEX_CLK_2_FIELD                        _MK_FIELD_CONST(0x1, PMC_IMPL_IO_DPD_STATUS_0_PEX_CLK_2_SHIFT)
#define PMC_IMPL_IO_DPD_STATUS_0_PEX_CLK_2_RANGE                        10:10
#define PMC_IMPL_IO_DPD_STATUS_0_PEX_CLK_2_WOFFSET                      0x0
#define PMC_IMPL_IO_DPD_STATUS_0_PEX_CLK_2_DEFAULT                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD_STATUS_0_PEX_CLK_2_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DPD_STATUS_0_PEX_CLK_2_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD_STATUS_0_PEX_CLK_2_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD_STATUS_0_PEX_CLK_2_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD_STATUS_0_PEX_CLK_2_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DPD_STATUS_0_PEX_CLK_2_OFF                  _MK_ENUM_CONST(0)
#define PMC_IMPL_IO_DPD_STATUS_0_PEX_CLK_2_ON                   _MK_ENUM_CONST(1)

#define PMC_IMPL_IO_DPD_STATUS_0_DAP3_SHIFT                     _MK_SHIFT_CONST(11)
#define PMC_IMPL_IO_DPD_STATUS_0_DAP3_FIELD                     _MK_FIELD_CONST(0x1, PMC_IMPL_IO_DPD_STATUS_0_DAP3_SHIFT)
#define PMC_IMPL_IO_DPD_STATUS_0_DAP3_RANGE                     11:11
#define PMC_IMPL_IO_DPD_STATUS_0_DAP3_WOFFSET                   0x0
#define PMC_IMPL_IO_DPD_STATUS_0_DAP3_DEFAULT                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD_STATUS_0_DAP3_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DPD_STATUS_0_DAP3_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD_STATUS_0_DAP3_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD_STATUS_0_DAP3_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD_STATUS_0_DAP3_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DPD_STATUS_0_DAP3_OFF                       _MK_ENUM_CONST(0)
#define PMC_IMPL_IO_DPD_STATUS_0_DAP3_ON                        _MK_ENUM_CONST(1)

#define PMC_IMPL_IO_DPD_STATUS_0_DAP5_SHIFT                     _MK_SHIFT_CONST(12)
#define PMC_IMPL_IO_DPD_STATUS_0_DAP5_FIELD                     _MK_FIELD_CONST(0x1, PMC_IMPL_IO_DPD_STATUS_0_DAP5_SHIFT)
#define PMC_IMPL_IO_DPD_STATUS_0_DAP5_RANGE                     12:12
#define PMC_IMPL_IO_DPD_STATUS_0_DAP5_WOFFSET                   0x0
#define PMC_IMPL_IO_DPD_STATUS_0_DAP5_DEFAULT                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD_STATUS_0_DAP5_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DPD_STATUS_0_DAP5_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD_STATUS_0_DAP5_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD_STATUS_0_DAP5_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD_STATUS_0_DAP5_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DPD_STATUS_0_DAP5_OFF                       _MK_ENUM_CONST(0)
#define PMC_IMPL_IO_DPD_STATUS_0_DAP5_ON                        _MK_ENUM_CONST(1)

#define PMC_IMPL_IO_DPD_STATUS_0_UART_SHIFT                     _MK_SHIFT_CONST(14)
#define PMC_IMPL_IO_DPD_STATUS_0_UART_FIELD                     _MK_FIELD_CONST(0x1, PMC_IMPL_IO_DPD_STATUS_0_UART_SHIFT)
#define PMC_IMPL_IO_DPD_STATUS_0_UART_RANGE                     14:14
#define PMC_IMPL_IO_DPD_STATUS_0_UART_WOFFSET                   0x0
#define PMC_IMPL_IO_DPD_STATUS_0_UART_DEFAULT                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD_STATUS_0_UART_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DPD_STATUS_0_UART_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD_STATUS_0_UART_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD_STATUS_0_UART_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD_STATUS_0_UART_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DPD_STATUS_0_UART_OFF                       _MK_ENUM_CONST(0)
#define PMC_IMPL_IO_DPD_STATUS_0_UART_ON                        _MK_ENUM_CONST(1)

#define PMC_IMPL_IO_DPD_STATUS_0_PWR_CTL_SHIFT                  _MK_SHIFT_CONST(15)
#define PMC_IMPL_IO_DPD_STATUS_0_PWR_CTL_FIELD                  _MK_FIELD_CONST(0x1, PMC_IMPL_IO_DPD_STATUS_0_PWR_CTL_SHIFT)
#define PMC_IMPL_IO_DPD_STATUS_0_PWR_CTL_RANGE                  15:15
#define PMC_IMPL_IO_DPD_STATUS_0_PWR_CTL_WOFFSET                        0x0
#define PMC_IMPL_IO_DPD_STATUS_0_PWR_CTL_DEFAULT                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD_STATUS_0_PWR_CTL_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DPD_STATUS_0_PWR_CTL_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD_STATUS_0_PWR_CTL_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD_STATUS_0_PWR_CTL_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD_STATUS_0_PWR_CTL_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DPD_STATUS_0_PWR_CTL_OFF                    _MK_ENUM_CONST(0)
#define PMC_IMPL_IO_DPD_STATUS_0_PWR_CTL_ON                     _MK_ENUM_CONST(1)

#define PMC_IMPL_IO_DPD_STATUS_0_SOC_GPIO53_SHIFT                       _MK_SHIFT_CONST(16)
#define PMC_IMPL_IO_DPD_STATUS_0_SOC_GPIO53_FIELD                       _MK_FIELD_CONST(0x1, PMC_IMPL_IO_DPD_STATUS_0_SOC_GPIO53_SHIFT)
#define PMC_IMPL_IO_DPD_STATUS_0_SOC_GPIO53_RANGE                       16:16
#define PMC_IMPL_IO_DPD_STATUS_0_SOC_GPIO53_WOFFSET                     0x0
#define PMC_IMPL_IO_DPD_STATUS_0_SOC_GPIO53_DEFAULT                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD_STATUS_0_SOC_GPIO53_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DPD_STATUS_0_SOC_GPIO53_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD_STATUS_0_SOC_GPIO53_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD_STATUS_0_SOC_GPIO53_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD_STATUS_0_SOC_GPIO53_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DPD_STATUS_0_SOC_GPIO53_OFF                 _MK_ENUM_CONST(0)
#define PMC_IMPL_IO_DPD_STATUS_0_SOC_GPIO53_ON                  _MK_ENUM_CONST(1)

#define PMC_IMPL_IO_DPD_STATUS_0_AUDIO_SHIFT                    _MK_SHIFT_CONST(17)
#define PMC_IMPL_IO_DPD_STATUS_0_AUDIO_FIELD                    _MK_FIELD_CONST(0x1, PMC_IMPL_IO_DPD_STATUS_0_AUDIO_SHIFT)
#define PMC_IMPL_IO_DPD_STATUS_0_AUDIO_RANGE                    17:17
#define PMC_IMPL_IO_DPD_STATUS_0_AUDIO_WOFFSET                  0x0
#define PMC_IMPL_IO_DPD_STATUS_0_AUDIO_DEFAULT                  _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD_STATUS_0_AUDIO_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DPD_STATUS_0_AUDIO_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD_STATUS_0_AUDIO_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD_STATUS_0_AUDIO_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD_STATUS_0_AUDIO_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DPD_STATUS_0_AUDIO_OFF                      _MK_ENUM_CONST(0)
#define PMC_IMPL_IO_DPD_STATUS_0_AUDIO_ON                       _MK_ENUM_CONST(1)

#define PMC_IMPL_IO_DPD_STATUS_0_GP_PWM2_SHIFT                  _MK_SHIFT_CONST(18)
#define PMC_IMPL_IO_DPD_STATUS_0_GP_PWM2_FIELD                  _MK_FIELD_CONST(0x1, PMC_IMPL_IO_DPD_STATUS_0_GP_PWM2_SHIFT)
#define PMC_IMPL_IO_DPD_STATUS_0_GP_PWM2_RANGE                  18:18
#define PMC_IMPL_IO_DPD_STATUS_0_GP_PWM2_WOFFSET                        0x0
#define PMC_IMPL_IO_DPD_STATUS_0_GP_PWM2_DEFAULT                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD_STATUS_0_GP_PWM2_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DPD_STATUS_0_GP_PWM2_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD_STATUS_0_GP_PWM2_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD_STATUS_0_GP_PWM2_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD_STATUS_0_GP_PWM2_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DPD_STATUS_0_GP_PWM2_OFF                    _MK_ENUM_CONST(0)
#define PMC_IMPL_IO_DPD_STATUS_0_GP_PWM2_ON                     _MK_ENUM_CONST(1)

#define PMC_IMPL_IO_DPD_STATUS_0_GP_PWM3_SHIFT                  _MK_SHIFT_CONST(19)
#define PMC_IMPL_IO_DPD_STATUS_0_GP_PWM3_FIELD                  _MK_FIELD_CONST(0x1, PMC_IMPL_IO_DPD_STATUS_0_GP_PWM3_SHIFT)
#define PMC_IMPL_IO_DPD_STATUS_0_GP_PWM3_RANGE                  19:19
#define PMC_IMPL_IO_DPD_STATUS_0_GP_PWM3_WOFFSET                        0x0
#define PMC_IMPL_IO_DPD_STATUS_0_GP_PWM3_DEFAULT                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD_STATUS_0_GP_PWM3_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DPD_STATUS_0_GP_PWM3_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD_STATUS_0_GP_PWM3_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD_STATUS_0_GP_PWM3_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD_STATUS_0_GP_PWM3_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DPD_STATUS_0_GP_PWM3_OFF                    _MK_ENUM_CONST(0)
#define PMC_IMPL_IO_DPD_STATUS_0_GP_PWM3_ON                     _MK_ENUM_CONST(1)

#define PMC_IMPL_IO_DPD_STATUS_0_SOC_GPIO12_SHIFT                       _MK_SHIFT_CONST(20)
#define PMC_IMPL_IO_DPD_STATUS_0_SOC_GPIO12_FIELD                       _MK_FIELD_CONST(0x1, PMC_IMPL_IO_DPD_STATUS_0_SOC_GPIO12_SHIFT)
#define PMC_IMPL_IO_DPD_STATUS_0_SOC_GPIO12_RANGE                       20:20
#define PMC_IMPL_IO_DPD_STATUS_0_SOC_GPIO12_WOFFSET                     0x0
#define PMC_IMPL_IO_DPD_STATUS_0_SOC_GPIO12_DEFAULT                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD_STATUS_0_SOC_GPIO12_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DPD_STATUS_0_SOC_GPIO12_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD_STATUS_0_SOC_GPIO12_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD_STATUS_0_SOC_GPIO12_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD_STATUS_0_SOC_GPIO12_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DPD_STATUS_0_SOC_GPIO12_OFF                 _MK_ENUM_CONST(0)
#define PMC_IMPL_IO_DPD_STATUS_0_SOC_GPIO12_ON                  _MK_ENUM_CONST(1)

#define PMC_IMPL_IO_DPD_STATUS_0_SOC_GPIO13_SHIFT                       _MK_SHIFT_CONST(21)
#define PMC_IMPL_IO_DPD_STATUS_0_SOC_GPIO13_FIELD                       _MK_FIELD_CONST(0x1, PMC_IMPL_IO_DPD_STATUS_0_SOC_GPIO13_SHIFT)
#define PMC_IMPL_IO_DPD_STATUS_0_SOC_GPIO13_RANGE                       21:21
#define PMC_IMPL_IO_DPD_STATUS_0_SOC_GPIO13_WOFFSET                     0x0
#define PMC_IMPL_IO_DPD_STATUS_0_SOC_GPIO13_DEFAULT                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD_STATUS_0_SOC_GPIO13_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DPD_STATUS_0_SOC_GPIO13_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD_STATUS_0_SOC_GPIO13_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD_STATUS_0_SOC_GPIO13_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD_STATUS_0_SOC_GPIO13_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DPD_STATUS_0_SOC_GPIO13_OFF                 _MK_ENUM_CONST(0)
#define PMC_IMPL_IO_DPD_STATUS_0_SOC_GPIO13_ON                  _MK_ENUM_CONST(1)

#define PMC_IMPL_IO_DPD_STATUS_0_SOC_GPIO10_SHIFT                       _MK_SHIFT_CONST(22)
#define PMC_IMPL_IO_DPD_STATUS_0_SOC_GPIO10_FIELD                       _MK_FIELD_CONST(0x1, PMC_IMPL_IO_DPD_STATUS_0_SOC_GPIO10_SHIFT)
#define PMC_IMPL_IO_DPD_STATUS_0_SOC_GPIO10_RANGE                       22:22
#define PMC_IMPL_IO_DPD_STATUS_0_SOC_GPIO10_WOFFSET                     0x0
#define PMC_IMPL_IO_DPD_STATUS_0_SOC_GPIO10_DEFAULT                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD_STATUS_0_SOC_GPIO10_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DPD_STATUS_0_SOC_GPIO10_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD_STATUS_0_SOC_GPIO10_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD_STATUS_0_SOC_GPIO10_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD_STATUS_0_SOC_GPIO10_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DPD_STATUS_0_SOC_GPIO10_OFF                 _MK_ENUM_CONST(0)
#define PMC_IMPL_IO_DPD_STATUS_0_SOC_GPIO10_ON                  _MK_ENUM_CONST(1)

#define PMC_IMPL_IO_DPD_STATUS_0_UART4_SHIFT                    _MK_SHIFT_CONST(23)
#define PMC_IMPL_IO_DPD_STATUS_0_UART4_FIELD                    _MK_FIELD_CONST(0x1, PMC_IMPL_IO_DPD_STATUS_0_UART4_SHIFT)
#define PMC_IMPL_IO_DPD_STATUS_0_UART4_RANGE                    23:23
#define PMC_IMPL_IO_DPD_STATUS_0_UART4_WOFFSET                  0x0
#define PMC_IMPL_IO_DPD_STATUS_0_UART4_DEFAULT                  _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD_STATUS_0_UART4_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DPD_STATUS_0_UART4_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD_STATUS_0_UART4_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD_STATUS_0_UART4_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD_STATUS_0_UART4_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DPD_STATUS_0_UART4_OFF                      _MK_ENUM_CONST(0)
#define PMC_IMPL_IO_DPD_STATUS_0_UART4_ON                       _MK_ENUM_CONST(1)

#define PMC_IMPL_IO_DPD_STATUS_0_UART5_SHIFT                    _MK_SHIFT_CONST(24)
#define PMC_IMPL_IO_DPD_STATUS_0_UART5_FIELD                    _MK_FIELD_CONST(0x1, PMC_IMPL_IO_DPD_STATUS_0_UART5_SHIFT)
#define PMC_IMPL_IO_DPD_STATUS_0_UART5_RANGE                    24:24
#define PMC_IMPL_IO_DPD_STATUS_0_UART5_WOFFSET                  0x0
#define PMC_IMPL_IO_DPD_STATUS_0_UART5_DEFAULT                  _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD_STATUS_0_UART5_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DPD_STATUS_0_UART5_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD_STATUS_0_UART5_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD_STATUS_0_UART5_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD_STATUS_0_UART5_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DPD_STATUS_0_UART5_OFF                      _MK_ENUM_CONST(0)
#define PMC_IMPL_IO_DPD_STATUS_0_UART5_ON                       _MK_ENUM_CONST(1)

#define PMC_IMPL_IO_DPD_STATUS_0_DBG_SHIFT                      _MK_SHIFT_CONST(25)
#define PMC_IMPL_IO_DPD_STATUS_0_DBG_FIELD                      _MK_FIELD_CONST(0x1, PMC_IMPL_IO_DPD_STATUS_0_DBG_SHIFT)
#define PMC_IMPL_IO_DPD_STATUS_0_DBG_RANGE                      25:25
#define PMC_IMPL_IO_DPD_STATUS_0_DBG_WOFFSET                    0x0
#define PMC_IMPL_IO_DPD_STATUS_0_DBG_DEFAULT                    _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD_STATUS_0_DBG_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DPD_STATUS_0_DBG_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD_STATUS_0_DBG_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD_STATUS_0_DBG_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD_STATUS_0_DBG_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DPD_STATUS_0_DBG_OFF                        _MK_ENUM_CONST(0)
#define PMC_IMPL_IO_DPD_STATUS_0_DBG_ON                 _MK_ENUM_CONST(1)

#define PMC_IMPL_IO_DPD_STATUS_0_HDMI_DP3_SHIFT                 _MK_SHIFT_CONST(26)
#define PMC_IMPL_IO_DPD_STATUS_0_HDMI_DP3_FIELD                 _MK_FIELD_CONST(0x1, PMC_IMPL_IO_DPD_STATUS_0_HDMI_DP3_SHIFT)
#define PMC_IMPL_IO_DPD_STATUS_0_HDMI_DP3_RANGE                 26:26
#define PMC_IMPL_IO_DPD_STATUS_0_HDMI_DP3_WOFFSET                       0x0
#define PMC_IMPL_IO_DPD_STATUS_0_HDMI_DP3_DEFAULT                       _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD_STATUS_0_HDMI_DP3_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DPD_STATUS_0_HDMI_DP3_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD_STATUS_0_HDMI_DP3_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD_STATUS_0_HDMI_DP3_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD_STATUS_0_HDMI_DP3_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DPD_STATUS_0_HDMI_DP3_OFF                   _MK_ENUM_CONST(0)
#define PMC_IMPL_IO_DPD_STATUS_0_HDMI_DP3_ON                    _MK_ENUM_CONST(1)

#define PMC_IMPL_IO_DPD_STATUS_0_HDMI_DP2_SHIFT                 _MK_SHIFT_CONST(27)
#define PMC_IMPL_IO_DPD_STATUS_0_HDMI_DP2_FIELD                 _MK_FIELD_CONST(0x1, PMC_IMPL_IO_DPD_STATUS_0_HDMI_DP2_SHIFT)
#define PMC_IMPL_IO_DPD_STATUS_0_HDMI_DP2_RANGE                 27:27
#define PMC_IMPL_IO_DPD_STATUS_0_HDMI_DP2_WOFFSET                       0x0
#define PMC_IMPL_IO_DPD_STATUS_0_HDMI_DP2_DEFAULT                       _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD_STATUS_0_HDMI_DP2_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DPD_STATUS_0_HDMI_DP2_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD_STATUS_0_HDMI_DP2_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD_STATUS_0_HDMI_DP2_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD_STATUS_0_HDMI_DP2_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DPD_STATUS_0_HDMI_DP2_OFF                   _MK_ENUM_CONST(0)
#define PMC_IMPL_IO_DPD_STATUS_0_HDMI_DP2_ON                    _MK_ENUM_CONST(1)

#define PMC_IMPL_IO_DPD_STATUS_0_HDMI_DP0_SHIFT                 _MK_SHIFT_CONST(28)
#define PMC_IMPL_IO_DPD_STATUS_0_HDMI_DP0_FIELD                 _MK_FIELD_CONST(0x1, PMC_IMPL_IO_DPD_STATUS_0_HDMI_DP0_SHIFT)
#define PMC_IMPL_IO_DPD_STATUS_0_HDMI_DP0_RANGE                 28:28
#define PMC_IMPL_IO_DPD_STATUS_0_HDMI_DP0_WOFFSET                       0x0
#define PMC_IMPL_IO_DPD_STATUS_0_HDMI_DP0_DEFAULT                       _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD_STATUS_0_HDMI_DP0_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DPD_STATUS_0_HDMI_DP0_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD_STATUS_0_HDMI_DP0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD_STATUS_0_HDMI_DP0_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD_STATUS_0_HDMI_DP0_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DPD_STATUS_0_HDMI_DP0_OFF                   _MK_ENUM_CONST(0)
#define PMC_IMPL_IO_DPD_STATUS_0_HDMI_DP0_ON                    _MK_ENUM_CONST(1)

#define PMC_IMPL_IO_DPD_STATUS_0_HDMI_DP1_SHIFT                 _MK_SHIFT_CONST(29)
#define PMC_IMPL_IO_DPD_STATUS_0_HDMI_DP1_FIELD                 _MK_FIELD_CONST(0x1, PMC_IMPL_IO_DPD_STATUS_0_HDMI_DP1_SHIFT)
#define PMC_IMPL_IO_DPD_STATUS_0_HDMI_DP1_RANGE                 29:29
#define PMC_IMPL_IO_DPD_STATUS_0_HDMI_DP1_WOFFSET                       0x0
#define PMC_IMPL_IO_DPD_STATUS_0_HDMI_DP1_DEFAULT                       _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD_STATUS_0_HDMI_DP1_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DPD_STATUS_0_HDMI_DP1_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD_STATUS_0_HDMI_DP1_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD_STATUS_0_HDMI_DP1_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD_STATUS_0_HDMI_DP1_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DPD_STATUS_0_HDMI_DP1_OFF                   _MK_ENUM_CONST(0)
#define PMC_IMPL_IO_DPD_STATUS_0_HDMI_DP1_ON                    _MK_ENUM_CONST(1)


// Register PMC_IMPL_IO_DPD2_REQ_0
#define PMC_IMPL_IO_DPD2_REQ_0                  _MK_ADDR_CONST(0x7c)
#define PMC_IMPL_IO_DPD2_REQ_0_SECURE                   0x0
#define PMC_IMPL_IO_DPD2_REQ_0_DUAL                     0x0
#define PMC_IMPL_IO_DPD2_REQ_0_SCR                      IODPD2_SCR_0
#define PMC_IMPL_IO_DPD2_REQ_0_WORD_COUNT                       0x1
#define PMC_IMPL_IO_DPD2_REQ_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD2_REQ_0_RESET_MASK                       _MK_MASK_CONST(0xf1aef87f)
#define PMC_IMPL_IO_DPD2_REQ_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD2_REQ_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD2_REQ_0_READ_MASK                        _MK_MASK_CONST(0xf1aef87f)
#define PMC_IMPL_IO_DPD2_REQ_0_WRITE_MASK                       _MK_MASK_CONST(0xf1aef87f)
#define PMC_IMPL_IO_DPD2_REQ_0_PEX_CNTRL_SHIFT                  _MK_SHIFT_CONST(0)
#define PMC_IMPL_IO_DPD2_REQ_0_PEX_CNTRL_FIELD                  _MK_FIELD_CONST(0x1, PMC_IMPL_IO_DPD2_REQ_0_PEX_CNTRL_SHIFT)
#define PMC_IMPL_IO_DPD2_REQ_0_PEX_CNTRL_RANGE                  0:0
#define PMC_IMPL_IO_DPD2_REQ_0_PEX_CNTRL_WOFFSET                        0x0
#define PMC_IMPL_IO_DPD2_REQ_0_PEX_CNTRL_DEFAULT                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD2_REQ_0_PEX_CNTRL_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DPD2_REQ_0_PEX_CNTRL_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD2_REQ_0_PEX_CNTRL_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD2_REQ_0_PEX_CNTRL_PARITY_PROTECTION                      _MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DPD2_REQ_0_PEX_CNTRL_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DPD2_REQ_0_PEX_CNTRL_INIT_ENUM                      OFF
#define PMC_IMPL_IO_DPD2_REQ_0_PEX_CNTRL_OFF                    _MK_ENUM_CONST(0)
#define PMC_IMPL_IO_DPD2_REQ_0_PEX_CNTRL_ON                     _MK_ENUM_CONST(1)

#define PMC_IMPL_IO_DPD2_REQ_0_PEX_CTL_2_SHIFT                  _MK_SHIFT_CONST(1)
#define PMC_IMPL_IO_DPD2_REQ_0_PEX_CTL_2_FIELD                  _MK_FIELD_CONST(0x1, PMC_IMPL_IO_DPD2_REQ_0_PEX_CTL_2_SHIFT)
#define PMC_IMPL_IO_DPD2_REQ_0_PEX_CTL_2_RANGE                  1:1
#define PMC_IMPL_IO_DPD2_REQ_0_PEX_CTL_2_WOFFSET                        0x0
#define PMC_IMPL_IO_DPD2_REQ_0_PEX_CTL_2_DEFAULT                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD2_REQ_0_PEX_CTL_2_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DPD2_REQ_0_PEX_CTL_2_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD2_REQ_0_PEX_CTL_2_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD2_REQ_0_PEX_CTL_2_PARITY_PROTECTION                      _MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DPD2_REQ_0_PEX_CTL_2_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DPD2_REQ_0_PEX_CTL_2_INIT_ENUM                      OFF
#define PMC_IMPL_IO_DPD2_REQ_0_PEX_CTL_2_OFF                    _MK_ENUM_CONST(0)
#define PMC_IMPL_IO_DPD2_REQ_0_PEX_CTL_2_ON                     _MK_ENUM_CONST(1)

#define PMC_IMPL_IO_DPD2_REQ_0_PEX_L0_RST_N_SHIFT                       _MK_SHIFT_CONST(2)
#define PMC_IMPL_IO_DPD2_REQ_0_PEX_L0_RST_N_FIELD                       _MK_FIELD_CONST(0x1, PMC_IMPL_IO_DPD2_REQ_0_PEX_L0_RST_N_SHIFT)
#define PMC_IMPL_IO_DPD2_REQ_0_PEX_L0_RST_N_RANGE                       2:2
#define PMC_IMPL_IO_DPD2_REQ_0_PEX_L0_RST_N_WOFFSET                     0x0
#define PMC_IMPL_IO_DPD2_REQ_0_PEX_L0_RST_N_DEFAULT                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD2_REQ_0_PEX_L0_RST_N_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DPD2_REQ_0_PEX_L0_RST_N_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD2_REQ_0_PEX_L0_RST_N_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD2_REQ_0_PEX_L0_RST_N_PARITY_PROTECTION                   _MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DPD2_REQ_0_PEX_L0_RST_N_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DPD2_REQ_0_PEX_L0_RST_N_INIT_ENUM                   OFF
#define PMC_IMPL_IO_DPD2_REQ_0_PEX_L0_RST_N_OFF                 _MK_ENUM_CONST(0)
#define PMC_IMPL_IO_DPD2_REQ_0_PEX_L0_RST_N_ON                  _MK_ENUM_CONST(1)

#define PMC_IMPL_IO_DPD2_REQ_0_PEX_L1_RST_N_SHIFT                       _MK_SHIFT_CONST(3)
#define PMC_IMPL_IO_DPD2_REQ_0_PEX_L1_RST_N_FIELD                       _MK_FIELD_CONST(0x1, PMC_IMPL_IO_DPD2_REQ_0_PEX_L1_RST_N_SHIFT)
#define PMC_IMPL_IO_DPD2_REQ_0_PEX_L1_RST_N_RANGE                       3:3
#define PMC_IMPL_IO_DPD2_REQ_0_PEX_L1_RST_N_WOFFSET                     0x0
#define PMC_IMPL_IO_DPD2_REQ_0_PEX_L1_RST_N_DEFAULT                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD2_REQ_0_PEX_L1_RST_N_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DPD2_REQ_0_PEX_L1_RST_N_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD2_REQ_0_PEX_L1_RST_N_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD2_REQ_0_PEX_L1_RST_N_PARITY_PROTECTION                   _MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DPD2_REQ_0_PEX_L1_RST_N_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DPD2_REQ_0_PEX_L1_RST_N_INIT_ENUM                   OFF
#define PMC_IMPL_IO_DPD2_REQ_0_PEX_L1_RST_N_OFF                 _MK_ENUM_CONST(0)
#define PMC_IMPL_IO_DPD2_REQ_0_PEX_L1_RST_N_ON                  _MK_ENUM_CONST(1)

#define PMC_IMPL_IO_DPD2_REQ_0_SDMMC4_SHIFT                     _MK_SHIFT_CONST(4)
#define PMC_IMPL_IO_DPD2_REQ_0_SDMMC4_FIELD                     _MK_FIELD_CONST(0x1, PMC_IMPL_IO_DPD2_REQ_0_SDMMC4_SHIFT)
#define PMC_IMPL_IO_DPD2_REQ_0_SDMMC4_RANGE                     4:4
#define PMC_IMPL_IO_DPD2_REQ_0_SDMMC4_WOFFSET                   0x0
#define PMC_IMPL_IO_DPD2_REQ_0_SDMMC4_DEFAULT                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD2_REQ_0_SDMMC4_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DPD2_REQ_0_SDMMC4_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD2_REQ_0_SDMMC4_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD2_REQ_0_SDMMC4_PARITY_PROTECTION                 _MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DPD2_REQ_0_SDMMC4_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DPD2_REQ_0_SDMMC4_INIT_ENUM                 OFF
#define PMC_IMPL_IO_DPD2_REQ_0_SDMMC4_OFF                       _MK_ENUM_CONST(0)
#define PMC_IMPL_IO_DPD2_REQ_0_SDMMC4_ON                        _MK_ENUM_CONST(1)

#define PMC_IMPL_IO_DPD2_REQ_0_PEX_L5_RST_N_SHIFT                       _MK_SHIFT_CONST(5)
#define PMC_IMPL_IO_DPD2_REQ_0_PEX_L5_RST_N_FIELD                       _MK_FIELD_CONST(0x1, PMC_IMPL_IO_DPD2_REQ_0_PEX_L5_RST_N_SHIFT)
#define PMC_IMPL_IO_DPD2_REQ_0_PEX_L5_RST_N_RANGE                       5:5
#define PMC_IMPL_IO_DPD2_REQ_0_PEX_L5_RST_N_WOFFSET                     0x0
#define PMC_IMPL_IO_DPD2_REQ_0_PEX_L5_RST_N_DEFAULT                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD2_REQ_0_PEX_L5_RST_N_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DPD2_REQ_0_PEX_L5_RST_N_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD2_REQ_0_PEX_L5_RST_N_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD2_REQ_0_PEX_L5_RST_N_PARITY_PROTECTION                   _MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DPD2_REQ_0_PEX_L5_RST_N_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DPD2_REQ_0_PEX_L5_RST_N_OFF                 _MK_ENUM_CONST(0)
#define PMC_IMPL_IO_DPD2_REQ_0_PEX_L5_RST_N_ON                  _MK_ENUM_CONST(1)

#define PMC_IMPL_IO_DPD2_REQ_0_CAM_SHIFT                        _MK_SHIFT_CONST(6)
#define PMC_IMPL_IO_DPD2_REQ_0_CAM_FIELD                        _MK_FIELD_CONST(0x1, PMC_IMPL_IO_DPD2_REQ_0_CAM_SHIFT)
#define PMC_IMPL_IO_DPD2_REQ_0_CAM_RANGE                        6:6
#define PMC_IMPL_IO_DPD2_REQ_0_CAM_WOFFSET                      0x0
#define PMC_IMPL_IO_DPD2_REQ_0_CAM_DEFAULT                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD2_REQ_0_CAM_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DPD2_REQ_0_CAM_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD2_REQ_0_CAM_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD2_REQ_0_CAM_PARITY_PROTECTION                    _MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DPD2_REQ_0_CAM_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DPD2_REQ_0_CAM_INIT_ENUM                    OFF
#define PMC_IMPL_IO_DPD2_REQ_0_CAM_OFF                  _MK_ENUM_CONST(0)
#define PMC_IMPL_IO_DPD2_REQ_0_CAM_ON                   _MK_ENUM_CONST(1)

#define PMC_IMPL_IO_DPD2_REQ_0_CSIC_SHIFT                       _MK_SHIFT_CONST(11)
#define PMC_IMPL_IO_DPD2_REQ_0_CSIC_FIELD                       _MK_FIELD_CONST(0x1, PMC_IMPL_IO_DPD2_REQ_0_CSIC_SHIFT)
#define PMC_IMPL_IO_DPD2_REQ_0_CSIC_RANGE                       11:11
#define PMC_IMPL_IO_DPD2_REQ_0_CSIC_WOFFSET                     0x0
#define PMC_IMPL_IO_DPD2_REQ_0_CSIC_DEFAULT                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD2_REQ_0_CSIC_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DPD2_REQ_0_CSIC_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD2_REQ_0_CSIC_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD2_REQ_0_CSIC_PARITY_PROTECTION                   _MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DPD2_REQ_0_CSIC_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DPD2_REQ_0_CSIC_INIT_ENUM                   OFF
#define PMC_IMPL_IO_DPD2_REQ_0_CSIC_OFF                 _MK_ENUM_CONST(0)
#define PMC_IMPL_IO_DPD2_REQ_0_CSIC_ON                  _MK_ENUM_CONST(1)

#define PMC_IMPL_IO_DPD2_REQ_0_CSID_SHIFT                       _MK_SHIFT_CONST(12)
#define PMC_IMPL_IO_DPD2_REQ_0_CSID_FIELD                       _MK_FIELD_CONST(0x1, PMC_IMPL_IO_DPD2_REQ_0_CSID_SHIFT)
#define PMC_IMPL_IO_DPD2_REQ_0_CSID_RANGE                       12:12
#define PMC_IMPL_IO_DPD2_REQ_0_CSID_WOFFSET                     0x0
#define PMC_IMPL_IO_DPD2_REQ_0_CSID_DEFAULT                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD2_REQ_0_CSID_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DPD2_REQ_0_CSID_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD2_REQ_0_CSID_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD2_REQ_0_CSID_PARITY_PROTECTION                   _MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DPD2_REQ_0_CSID_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DPD2_REQ_0_CSID_INIT_ENUM                   OFF
#define PMC_IMPL_IO_DPD2_REQ_0_CSID_OFF                 _MK_ENUM_CONST(0)
#define PMC_IMPL_IO_DPD2_REQ_0_CSID_ON                  _MK_ENUM_CONST(1)

#define PMC_IMPL_IO_DPD2_REQ_0_CSIE_SHIFT                       _MK_SHIFT_CONST(13)
#define PMC_IMPL_IO_DPD2_REQ_0_CSIE_FIELD                       _MK_FIELD_CONST(0x1, PMC_IMPL_IO_DPD2_REQ_0_CSIE_SHIFT)
#define PMC_IMPL_IO_DPD2_REQ_0_CSIE_RANGE                       13:13
#define PMC_IMPL_IO_DPD2_REQ_0_CSIE_WOFFSET                     0x0
#define PMC_IMPL_IO_DPD2_REQ_0_CSIE_DEFAULT                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD2_REQ_0_CSIE_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DPD2_REQ_0_CSIE_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD2_REQ_0_CSIE_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD2_REQ_0_CSIE_PARITY_PROTECTION                   _MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DPD2_REQ_0_CSIE_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DPD2_REQ_0_CSIE_INIT_ENUM                   OFF
#define PMC_IMPL_IO_DPD2_REQ_0_CSIE_OFF                 _MK_ENUM_CONST(0)
#define PMC_IMPL_IO_DPD2_REQ_0_CSIE_ON                  _MK_ENUM_CONST(1)

#define PMC_IMPL_IO_DPD2_REQ_0_CSIF_SHIFT                       _MK_SHIFT_CONST(14)
#define PMC_IMPL_IO_DPD2_REQ_0_CSIF_FIELD                       _MK_FIELD_CONST(0x1, PMC_IMPL_IO_DPD2_REQ_0_CSIF_SHIFT)
#define PMC_IMPL_IO_DPD2_REQ_0_CSIF_RANGE                       14:14
#define PMC_IMPL_IO_DPD2_REQ_0_CSIF_WOFFSET                     0x0
#define PMC_IMPL_IO_DPD2_REQ_0_CSIF_DEFAULT                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD2_REQ_0_CSIF_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DPD2_REQ_0_CSIF_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD2_REQ_0_CSIF_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD2_REQ_0_CSIF_PARITY_PROTECTION                   _MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DPD2_REQ_0_CSIF_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DPD2_REQ_0_CSIF_INIT_ENUM                   OFF
#define PMC_IMPL_IO_DPD2_REQ_0_CSIF_OFF                 _MK_ENUM_CONST(0)
#define PMC_IMPL_IO_DPD2_REQ_0_CSIF_ON                  _MK_ENUM_CONST(1)

#define PMC_IMPL_IO_DPD2_REQ_0_SPI_SHIFT                        _MK_SHIFT_CONST(15)
#define PMC_IMPL_IO_DPD2_REQ_0_SPI_FIELD                        _MK_FIELD_CONST(0x1, PMC_IMPL_IO_DPD2_REQ_0_SPI_SHIFT)
#define PMC_IMPL_IO_DPD2_REQ_0_SPI_RANGE                        15:15
#define PMC_IMPL_IO_DPD2_REQ_0_SPI_WOFFSET                      0x0
#define PMC_IMPL_IO_DPD2_REQ_0_SPI_DEFAULT                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD2_REQ_0_SPI_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DPD2_REQ_0_SPI_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD2_REQ_0_SPI_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD2_REQ_0_SPI_PARITY_PROTECTION                    _MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DPD2_REQ_0_SPI_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DPD2_REQ_0_SPI_INIT_ENUM                    OFF
#define PMC_IMPL_IO_DPD2_REQ_0_SPI_OFF                  _MK_ENUM_CONST(0)
#define PMC_IMPL_IO_DPD2_REQ_0_SPI_ON                   _MK_ENUM_CONST(1)

#define PMC_IMPL_IO_DPD2_REQ_0_UFS_SHIFT                        _MK_SHIFT_CONST(17)
#define PMC_IMPL_IO_DPD2_REQ_0_UFS_FIELD                        _MK_FIELD_CONST(0x1, PMC_IMPL_IO_DPD2_REQ_0_UFS_SHIFT)
#define PMC_IMPL_IO_DPD2_REQ_0_UFS_RANGE                        17:17
#define PMC_IMPL_IO_DPD2_REQ_0_UFS_WOFFSET                      0x0
#define PMC_IMPL_IO_DPD2_REQ_0_UFS_DEFAULT                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD2_REQ_0_UFS_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DPD2_REQ_0_UFS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD2_REQ_0_UFS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD2_REQ_0_UFS_PARITY_PROTECTION                    _MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DPD2_REQ_0_UFS_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DPD2_REQ_0_UFS_INIT_ENUM                    OFF
#define PMC_IMPL_IO_DPD2_REQ_0_UFS_OFF                  _MK_ENUM_CONST(0)
#define PMC_IMPL_IO_DPD2_REQ_0_UFS_ON                   _MK_ENUM_CONST(1)

#define PMC_IMPL_IO_DPD2_REQ_0_CSIG_SHIFT                       _MK_SHIFT_CONST(18)
#define PMC_IMPL_IO_DPD2_REQ_0_CSIG_FIELD                       _MK_FIELD_CONST(0x1, PMC_IMPL_IO_DPD2_REQ_0_CSIG_SHIFT)
#define PMC_IMPL_IO_DPD2_REQ_0_CSIG_RANGE                       18:18
#define PMC_IMPL_IO_DPD2_REQ_0_CSIG_WOFFSET                     0x0
#define PMC_IMPL_IO_DPD2_REQ_0_CSIG_DEFAULT                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD2_REQ_0_CSIG_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DPD2_REQ_0_CSIG_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD2_REQ_0_CSIG_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD2_REQ_0_CSIG_PARITY_PROTECTION                   _MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DPD2_REQ_0_CSIG_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DPD2_REQ_0_CSIG_INIT_ENUM                   OFF
#define PMC_IMPL_IO_DPD2_REQ_0_CSIG_OFF                 _MK_ENUM_CONST(0)
#define PMC_IMPL_IO_DPD2_REQ_0_CSIG_ON                  _MK_ENUM_CONST(1)

#define PMC_IMPL_IO_DPD2_REQ_0_CSIH_SHIFT                       _MK_SHIFT_CONST(19)
#define PMC_IMPL_IO_DPD2_REQ_0_CSIH_FIELD                       _MK_FIELD_CONST(0x1, PMC_IMPL_IO_DPD2_REQ_0_CSIH_SHIFT)
#define PMC_IMPL_IO_DPD2_REQ_0_CSIH_RANGE                       19:19
#define PMC_IMPL_IO_DPD2_REQ_0_CSIH_WOFFSET                     0x0
#define PMC_IMPL_IO_DPD2_REQ_0_CSIH_DEFAULT                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD2_REQ_0_CSIH_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DPD2_REQ_0_CSIH_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD2_REQ_0_CSIH_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD2_REQ_0_CSIH_PARITY_PROTECTION                   _MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DPD2_REQ_0_CSIH_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DPD2_REQ_0_CSIH_INIT_ENUM                   OFF
#define PMC_IMPL_IO_DPD2_REQ_0_CSIH_OFF                 _MK_ENUM_CONST(0)
#define PMC_IMPL_IO_DPD2_REQ_0_CSIH_ON                  _MK_ENUM_CONST(1)

#define PMC_IMPL_IO_DPD2_REQ_0_EDP_SHIFT                        _MK_SHIFT_CONST(21)
#define PMC_IMPL_IO_DPD2_REQ_0_EDP_FIELD                        _MK_FIELD_CONST(0x1, PMC_IMPL_IO_DPD2_REQ_0_EDP_SHIFT)
#define PMC_IMPL_IO_DPD2_REQ_0_EDP_RANGE                        21:21
#define PMC_IMPL_IO_DPD2_REQ_0_EDP_WOFFSET                      0x0
#define PMC_IMPL_IO_DPD2_REQ_0_EDP_DEFAULT                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD2_REQ_0_EDP_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DPD2_REQ_0_EDP_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD2_REQ_0_EDP_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD2_REQ_0_EDP_PARITY_PROTECTION                    _MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DPD2_REQ_0_EDP_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DPD2_REQ_0_EDP_INIT_ENUM                    OFF
#define PMC_IMPL_IO_DPD2_REQ_0_EDP_OFF                  _MK_ENUM_CONST(0)
#define PMC_IMPL_IO_DPD2_REQ_0_EDP_ON                   _MK_ENUM_CONST(1)

#define PMC_IMPL_IO_DPD2_REQ_0_SDMMC1_HV_SHIFT                  _MK_SHIFT_CONST(23)
#define PMC_IMPL_IO_DPD2_REQ_0_SDMMC1_HV_FIELD                  _MK_FIELD_CONST(0x1, PMC_IMPL_IO_DPD2_REQ_0_SDMMC1_HV_SHIFT)
#define PMC_IMPL_IO_DPD2_REQ_0_SDMMC1_HV_RANGE                  23:23
#define PMC_IMPL_IO_DPD2_REQ_0_SDMMC1_HV_WOFFSET                        0x0
#define PMC_IMPL_IO_DPD2_REQ_0_SDMMC1_HV_DEFAULT                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD2_REQ_0_SDMMC1_HV_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DPD2_REQ_0_SDMMC1_HV_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD2_REQ_0_SDMMC1_HV_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD2_REQ_0_SDMMC1_HV_PARITY_PROTECTION                      _MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DPD2_REQ_0_SDMMC1_HV_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DPD2_REQ_0_SDMMC1_HV_INIT_ENUM                      OFF
#define PMC_IMPL_IO_DPD2_REQ_0_SDMMC1_HV_OFF                    _MK_ENUM_CONST(0)
#define PMC_IMPL_IO_DPD2_REQ_0_SDMMC1_HV_ON                     _MK_ENUM_CONST(1)

#define PMC_IMPL_IO_DPD2_REQ_0_SDMMC3_HV_SHIFT                  _MK_SHIFT_CONST(24)
#define PMC_IMPL_IO_DPD2_REQ_0_SDMMC3_HV_FIELD                  _MK_FIELD_CONST(0x1, PMC_IMPL_IO_DPD2_REQ_0_SDMMC3_HV_SHIFT)
#define PMC_IMPL_IO_DPD2_REQ_0_SDMMC3_HV_RANGE                  24:24
#define PMC_IMPL_IO_DPD2_REQ_0_SDMMC3_HV_WOFFSET                        0x0
#define PMC_IMPL_IO_DPD2_REQ_0_SDMMC3_HV_DEFAULT                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD2_REQ_0_SDMMC3_HV_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DPD2_REQ_0_SDMMC3_HV_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD2_REQ_0_SDMMC3_HV_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD2_REQ_0_SDMMC3_HV_PARITY_PROTECTION                      _MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DPD2_REQ_0_SDMMC3_HV_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DPD2_REQ_0_SDMMC3_HV_INIT_ENUM                      OFF
#define PMC_IMPL_IO_DPD2_REQ_0_SDMMC3_HV_OFF                    _MK_ENUM_CONST(0)
#define PMC_IMPL_IO_DPD2_REQ_0_SDMMC3_HV_ON                     _MK_ENUM_CONST(1)

#define PMC_IMPL_IO_DPD2_REQ_0_CONN_SHIFT                       _MK_SHIFT_CONST(28)
#define PMC_IMPL_IO_DPD2_REQ_0_CONN_FIELD                       _MK_FIELD_CONST(0x1, PMC_IMPL_IO_DPD2_REQ_0_CONN_SHIFT)
#define PMC_IMPL_IO_DPD2_REQ_0_CONN_RANGE                       28:28
#define PMC_IMPL_IO_DPD2_REQ_0_CONN_WOFFSET                     0x0
#define PMC_IMPL_IO_DPD2_REQ_0_CONN_DEFAULT                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD2_REQ_0_CONN_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DPD2_REQ_0_CONN_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD2_REQ_0_CONN_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD2_REQ_0_CONN_PARITY_PROTECTION                   _MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DPD2_REQ_0_CONN_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DPD2_REQ_0_CONN_INIT_ENUM                   OFF
#define PMC_IMPL_IO_DPD2_REQ_0_CONN_OFF                 _MK_ENUM_CONST(0)
#define PMC_IMPL_IO_DPD2_REQ_0_CONN_ON                  _MK_ENUM_CONST(1)

#define PMC_IMPL_IO_DPD2_REQ_0_AUDIO_HV_SHIFT                   _MK_SHIFT_CONST(29)
#define PMC_IMPL_IO_DPD2_REQ_0_AUDIO_HV_FIELD                   _MK_FIELD_CONST(0x1, PMC_IMPL_IO_DPD2_REQ_0_AUDIO_HV_SHIFT)
#define PMC_IMPL_IO_DPD2_REQ_0_AUDIO_HV_RANGE                   29:29
#define PMC_IMPL_IO_DPD2_REQ_0_AUDIO_HV_WOFFSET                 0x0
#define PMC_IMPL_IO_DPD2_REQ_0_AUDIO_HV_DEFAULT                 _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD2_REQ_0_AUDIO_HV_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DPD2_REQ_0_AUDIO_HV_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD2_REQ_0_AUDIO_HV_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD2_REQ_0_AUDIO_HV_PARITY_PROTECTION                       _MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DPD2_REQ_0_AUDIO_HV_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DPD2_REQ_0_AUDIO_HV_INIT_ENUM                       OFF
#define PMC_IMPL_IO_DPD2_REQ_0_AUDIO_HV_OFF                     _MK_ENUM_CONST(0)
#define PMC_IMPL_IO_DPD2_REQ_0_AUDIO_HV_ON                      _MK_ENUM_CONST(1)

#define PMC_IMPL_IO_DPD2_REQ_0_CODE_SHIFT                       _MK_SHIFT_CONST(30)
#define PMC_IMPL_IO_DPD2_REQ_0_CODE_FIELD                       _MK_FIELD_CONST(0x3, PMC_IMPL_IO_DPD2_REQ_0_CODE_SHIFT)
#define PMC_IMPL_IO_DPD2_REQ_0_CODE_RANGE                       31:30
#define PMC_IMPL_IO_DPD2_REQ_0_CODE_WOFFSET                     0x0
#define PMC_IMPL_IO_DPD2_REQ_0_CODE_DEFAULT                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD2_REQ_0_CODE_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
#define PMC_IMPL_IO_DPD2_REQ_0_CODE_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD2_REQ_0_CODE_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD2_REQ_0_CODE_PARITY_PROTECTION                   _MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DPD2_REQ_0_CODE_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DPD2_REQ_0_CODE_IDLE                        _MK_ENUM_CONST(0)
#define PMC_IMPL_IO_DPD2_REQ_0_CODE_DPD_OFF                     _MK_ENUM_CONST(1)
#define PMC_IMPL_IO_DPD2_REQ_0_CODE_DPD_ON                      _MK_ENUM_CONST(2)


// Register PMC_IMPL_IO_DPD2_STATUS_0
#define PMC_IMPL_IO_DPD2_STATUS_0                       _MK_ADDR_CONST(0x80)
#define PMC_IMPL_IO_DPD2_STATUS_0_SECURE                        0x0
#define PMC_IMPL_IO_DPD2_STATUS_0_DUAL                  0x0
#define PMC_IMPL_IO_DPD2_STATUS_0_SCR                   IODPD2_SCR_0
#define PMC_IMPL_IO_DPD2_STATUS_0_WORD_COUNT                    0x1
#define PMC_IMPL_IO_DPD2_STATUS_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD2_STATUS_0_RESET_MASK                    _MK_MASK_CONST(0x31aef87f)
#define PMC_IMPL_IO_DPD2_STATUS_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD2_STATUS_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD2_STATUS_0_READ_MASK                     _MK_MASK_CONST(0x31aef87f)
#define PMC_IMPL_IO_DPD2_STATUS_0_WRITE_MASK                    _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD2_STATUS_0_PEX_CNTRL_SHIFT                       _MK_SHIFT_CONST(0)
#define PMC_IMPL_IO_DPD2_STATUS_0_PEX_CNTRL_FIELD                       _MK_FIELD_CONST(0x1, PMC_IMPL_IO_DPD2_STATUS_0_PEX_CNTRL_SHIFT)
#define PMC_IMPL_IO_DPD2_STATUS_0_PEX_CNTRL_RANGE                       0:0
#define PMC_IMPL_IO_DPD2_STATUS_0_PEX_CNTRL_WOFFSET                     0x0
#define PMC_IMPL_IO_DPD2_STATUS_0_PEX_CNTRL_DEFAULT                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD2_STATUS_0_PEX_CNTRL_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DPD2_STATUS_0_PEX_CNTRL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD2_STATUS_0_PEX_CNTRL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD2_STATUS_0_PEX_CNTRL_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD2_STATUS_0_PEX_CNTRL_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DPD2_STATUS_0_PEX_CNTRL_INIT_ENUM                   OFF
#define PMC_IMPL_IO_DPD2_STATUS_0_PEX_CNTRL_OFF                 _MK_ENUM_CONST(0)
#define PMC_IMPL_IO_DPD2_STATUS_0_PEX_CNTRL_ON                  _MK_ENUM_CONST(1)

#define PMC_IMPL_IO_DPD2_STATUS_0_PEX_CTL_2_SHIFT                       _MK_SHIFT_CONST(1)
#define PMC_IMPL_IO_DPD2_STATUS_0_PEX_CTL_2_FIELD                       _MK_FIELD_CONST(0x1, PMC_IMPL_IO_DPD2_STATUS_0_PEX_CTL_2_SHIFT)
#define PMC_IMPL_IO_DPD2_STATUS_0_PEX_CTL_2_RANGE                       1:1
#define PMC_IMPL_IO_DPD2_STATUS_0_PEX_CTL_2_WOFFSET                     0x0
#define PMC_IMPL_IO_DPD2_STATUS_0_PEX_CTL_2_DEFAULT                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD2_STATUS_0_PEX_CTL_2_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DPD2_STATUS_0_PEX_CTL_2_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD2_STATUS_0_PEX_CTL_2_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD2_STATUS_0_PEX_CTL_2_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD2_STATUS_0_PEX_CTL_2_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DPD2_STATUS_0_PEX_CTL_2_INIT_ENUM                   OFF
#define PMC_IMPL_IO_DPD2_STATUS_0_PEX_CTL_2_OFF                 _MK_ENUM_CONST(0)
#define PMC_IMPL_IO_DPD2_STATUS_0_PEX_CTL_2_ON                  _MK_ENUM_CONST(1)

#define PMC_IMPL_IO_DPD2_STATUS_0_PEX_L0_RST_N_SHIFT                    _MK_SHIFT_CONST(2)
#define PMC_IMPL_IO_DPD2_STATUS_0_PEX_L0_RST_N_FIELD                    _MK_FIELD_CONST(0x1, PMC_IMPL_IO_DPD2_STATUS_0_PEX_L0_RST_N_SHIFT)
#define PMC_IMPL_IO_DPD2_STATUS_0_PEX_L0_RST_N_RANGE                    2:2
#define PMC_IMPL_IO_DPD2_STATUS_0_PEX_L0_RST_N_WOFFSET                  0x0
#define PMC_IMPL_IO_DPD2_STATUS_0_PEX_L0_RST_N_DEFAULT                  _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD2_STATUS_0_PEX_L0_RST_N_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DPD2_STATUS_0_PEX_L0_RST_N_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD2_STATUS_0_PEX_L0_RST_N_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD2_STATUS_0_PEX_L0_RST_N_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD2_STATUS_0_PEX_L0_RST_N_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DPD2_STATUS_0_PEX_L0_RST_N_INIT_ENUM                        OFF
#define PMC_IMPL_IO_DPD2_STATUS_0_PEX_L0_RST_N_OFF                      _MK_ENUM_CONST(0)
#define PMC_IMPL_IO_DPD2_STATUS_0_PEX_L0_RST_N_ON                       _MK_ENUM_CONST(1)

#define PMC_IMPL_IO_DPD2_STATUS_0_PEX_L1_RST_N_SHIFT                    _MK_SHIFT_CONST(3)
#define PMC_IMPL_IO_DPD2_STATUS_0_PEX_L1_RST_N_FIELD                    _MK_FIELD_CONST(0x1, PMC_IMPL_IO_DPD2_STATUS_0_PEX_L1_RST_N_SHIFT)
#define PMC_IMPL_IO_DPD2_STATUS_0_PEX_L1_RST_N_RANGE                    3:3
#define PMC_IMPL_IO_DPD2_STATUS_0_PEX_L1_RST_N_WOFFSET                  0x0
#define PMC_IMPL_IO_DPD2_STATUS_0_PEX_L1_RST_N_DEFAULT                  _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD2_STATUS_0_PEX_L1_RST_N_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DPD2_STATUS_0_PEX_L1_RST_N_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD2_STATUS_0_PEX_L1_RST_N_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD2_STATUS_0_PEX_L1_RST_N_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD2_STATUS_0_PEX_L1_RST_N_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DPD2_STATUS_0_PEX_L1_RST_N_INIT_ENUM                        OFF
#define PMC_IMPL_IO_DPD2_STATUS_0_PEX_L1_RST_N_OFF                      _MK_ENUM_CONST(0)
#define PMC_IMPL_IO_DPD2_STATUS_0_PEX_L1_RST_N_ON                       _MK_ENUM_CONST(1)

#define PMC_IMPL_IO_DPD2_STATUS_0_SDMMC4_SHIFT                  _MK_SHIFT_CONST(4)
#define PMC_IMPL_IO_DPD2_STATUS_0_SDMMC4_FIELD                  _MK_FIELD_CONST(0x1, PMC_IMPL_IO_DPD2_STATUS_0_SDMMC4_SHIFT)
#define PMC_IMPL_IO_DPD2_STATUS_0_SDMMC4_RANGE                  4:4
#define PMC_IMPL_IO_DPD2_STATUS_0_SDMMC4_WOFFSET                        0x0
#define PMC_IMPL_IO_DPD2_STATUS_0_SDMMC4_DEFAULT                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD2_STATUS_0_SDMMC4_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DPD2_STATUS_0_SDMMC4_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD2_STATUS_0_SDMMC4_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD2_STATUS_0_SDMMC4_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD2_STATUS_0_SDMMC4_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DPD2_STATUS_0_SDMMC4_INIT_ENUM                      OFF
#define PMC_IMPL_IO_DPD2_STATUS_0_SDMMC4_OFF                    _MK_ENUM_CONST(0)
#define PMC_IMPL_IO_DPD2_STATUS_0_SDMMC4_ON                     _MK_ENUM_CONST(1)

#define PMC_IMPL_IO_DPD2_STATUS_0_PEX_L5_RST_N_SHIFT                    _MK_SHIFT_CONST(5)
#define PMC_IMPL_IO_DPD2_STATUS_0_PEX_L5_RST_N_FIELD                    _MK_FIELD_CONST(0x1, PMC_IMPL_IO_DPD2_STATUS_0_PEX_L5_RST_N_SHIFT)
#define PMC_IMPL_IO_DPD2_STATUS_0_PEX_L5_RST_N_RANGE                    5:5
#define PMC_IMPL_IO_DPD2_STATUS_0_PEX_L5_RST_N_WOFFSET                  0x0
#define PMC_IMPL_IO_DPD2_STATUS_0_PEX_L5_RST_N_DEFAULT                  _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD2_STATUS_0_PEX_L5_RST_N_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DPD2_STATUS_0_PEX_L5_RST_N_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD2_STATUS_0_PEX_L5_RST_N_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD2_STATUS_0_PEX_L5_RST_N_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD2_STATUS_0_PEX_L5_RST_N_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DPD2_STATUS_0_PEX_L5_RST_N_OFF                      _MK_ENUM_CONST(0)
#define PMC_IMPL_IO_DPD2_STATUS_0_PEX_L5_RST_N_ON                       _MK_ENUM_CONST(1)

#define PMC_IMPL_IO_DPD2_STATUS_0_CAM_SHIFT                     _MK_SHIFT_CONST(6)
#define PMC_IMPL_IO_DPD2_STATUS_0_CAM_FIELD                     _MK_FIELD_CONST(0x1, PMC_IMPL_IO_DPD2_STATUS_0_CAM_SHIFT)
#define PMC_IMPL_IO_DPD2_STATUS_0_CAM_RANGE                     6:6
#define PMC_IMPL_IO_DPD2_STATUS_0_CAM_WOFFSET                   0x0
#define PMC_IMPL_IO_DPD2_STATUS_0_CAM_DEFAULT                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD2_STATUS_0_CAM_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DPD2_STATUS_0_CAM_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD2_STATUS_0_CAM_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD2_STATUS_0_CAM_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD2_STATUS_0_CAM_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DPD2_STATUS_0_CAM_INIT_ENUM                 OFF
#define PMC_IMPL_IO_DPD2_STATUS_0_CAM_OFF                       _MK_ENUM_CONST(0)
#define PMC_IMPL_IO_DPD2_STATUS_0_CAM_ON                        _MK_ENUM_CONST(1)

#define PMC_IMPL_IO_DPD2_STATUS_0_CSIC_SHIFT                    _MK_SHIFT_CONST(11)
#define PMC_IMPL_IO_DPD2_STATUS_0_CSIC_FIELD                    _MK_FIELD_CONST(0x1, PMC_IMPL_IO_DPD2_STATUS_0_CSIC_SHIFT)
#define PMC_IMPL_IO_DPD2_STATUS_0_CSIC_RANGE                    11:11
#define PMC_IMPL_IO_DPD2_STATUS_0_CSIC_WOFFSET                  0x0
#define PMC_IMPL_IO_DPD2_STATUS_0_CSIC_DEFAULT                  _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD2_STATUS_0_CSIC_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DPD2_STATUS_0_CSIC_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD2_STATUS_0_CSIC_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD2_STATUS_0_CSIC_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD2_STATUS_0_CSIC_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DPD2_STATUS_0_CSIC_INIT_ENUM                        OFF
#define PMC_IMPL_IO_DPD2_STATUS_0_CSIC_OFF                      _MK_ENUM_CONST(0)
#define PMC_IMPL_IO_DPD2_STATUS_0_CSIC_ON                       _MK_ENUM_CONST(1)

#define PMC_IMPL_IO_DPD2_STATUS_0_CSID_SHIFT                    _MK_SHIFT_CONST(12)
#define PMC_IMPL_IO_DPD2_STATUS_0_CSID_FIELD                    _MK_FIELD_CONST(0x1, PMC_IMPL_IO_DPD2_STATUS_0_CSID_SHIFT)
#define PMC_IMPL_IO_DPD2_STATUS_0_CSID_RANGE                    12:12
#define PMC_IMPL_IO_DPD2_STATUS_0_CSID_WOFFSET                  0x0
#define PMC_IMPL_IO_DPD2_STATUS_0_CSID_DEFAULT                  _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD2_STATUS_0_CSID_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DPD2_STATUS_0_CSID_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD2_STATUS_0_CSID_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD2_STATUS_0_CSID_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD2_STATUS_0_CSID_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DPD2_STATUS_0_CSID_INIT_ENUM                        OFF
#define PMC_IMPL_IO_DPD2_STATUS_0_CSID_OFF                      _MK_ENUM_CONST(0)
#define PMC_IMPL_IO_DPD2_STATUS_0_CSID_ON                       _MK_ENUM_CONST(1)

#define PMC_IMPL_IO_DPD2_STATUS_0_CSIE_SHIFT                    _MK_SHIFT_CONST(13)
#define PMC_IMPL_IO_DPD2_STATUS_0_CSIE_FIELD                    _MK_FIELD_CONST(0x1, PMC_IMPL_IO_DPD2_STATUS_0_CSIE_SHIFT)
#define PMC_IMPL_IO_DPD2_STATUS_0_CSIE_RANGE                    13:13
#define PMC_IMPL_IO_DPD2_STATUS_0_CSIE_WOFFSET                  0x0
#define PMC_IMPL_IO_DPD2_STATUS_0_CSIE_DEFAULT                  _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD2_STATUS_0_CSIE_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DPD2_STATUS_0_CSIE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD2_STATUS_0_CSIE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD2_STATUS_0_CSIE_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD2_STATUS_0_CSIE_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DPD2_STATUS_0_CSIE_INIT_ENUM                        OFF
#define PMC_IMPL_IO_DPD2_STATUS_0_CSIE_OFF                      _MK_ENUM_CONST(0)
#define PMC_IMPL_IO_DPD2_STATUS_0_CSIE_ON                       _MK_ENUM_CONST(1)

#define PMC_IMPL_IO_DPD2_STATUS_0_CSIF_SHIFT                    _MK_SHIFT_CONST(14)
#define PMC_IMPL_IO_DPD2_STATUS_0_CSIF_FIELD                    _MK_FIELD_CONST(0x1, PMC_IMPL_IO_DPD2_STATUS_0_CSIF_SHIFT)
#define PMC_IMPL_IO_DPD2_STATUS_0_CSIF_RANGE                    14:14
#define PMC_IMPL_IO_DPD2_STATUS_0_CSIF_WOFFSET                  0x0
#define PMC_IMPL_IO_DPD2_STATUS_0_CSIF_DEFAULT                  _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD2_STATUS_0_CSIF_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DPD2_STATUS_0_CSIF_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD2_STATUS_0_CSIF_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD2_STATUS_0_CSIF_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD2_STATUS_0_CSIF_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DPD2_STATUS_0_CSIF_INIT_ENUM                        OFF
#define PMC_IMPL_IO_DPD2_STATUS_0_CSIF_OFF                      _MK_ENUM_CONST(0)
#define PMC_IMPL_IO_DPD2_STATUS_0_CSIF_ON                       _MK_ENUM_CONST(1)

#define PMC_IMPL_IO_DPD2_STATUS_0_SPI_SHIFT                     _MK_SHIFT_CONST(15)
#define PMC_IMPL_IO_DPD2_STATUS_0_SPI_FIELD                     _MK_FIELD_CONST(0x1, PMC_IMPL_IO_DPD2_STATUS_0_SPI_SHIFT)
#define PMC_IMPL_IO_DPD2_STATUS_0_SPI_RANGE                     15:15
#define PMC_IMPL_IO_DPD2_STATUS_0_SPI_WOFFSET                   0x0
#define PMC_IMPL_IO_DPD2_STATUS_0_SPI_DEFAULT                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD2_STATUS_0_SPI_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DPD2_STATUS_0_SPI_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD2_STATUS_0_SPI_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD2_STATUS_0_SPI_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD2_STATUS_0_SPI_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DPD2_STATUS_0_SPI_INIT_ENUM                 OFF
#define PMC_IMPL_IO_DPD2_STATUS_0_SPI_OFF                       _MK_ENUM_CONST(0)
#define PMC_IMPL_IO_DPD2_STATUS_0_SPI_ON                        _MK_ENUM_CONST(1)

#define PMC_IMPL_IO_DPD2_STATUS_0_UFS_SHIFT                     _MK_SHIFT_CONST(17)
#define PMC_IMPL_IO_DPD2_STATUS_0_UFS_FIELD                     _MK_FIELD_CONST(0x1, PMC_IMPL_IO_DPD2_STATUS_0_UFS_SHIFT)
#define PMC_IMPL_IO_DPD2_STATUS_0_UFS_RANGE                     17:17
#define PMC_IMPL_IO_DPD2_STATUS_0_UFS_WOFFSET                   0x0
#define PMC_IMPL_IO_DPD2_STATUS_0_UFS_DEFAULT                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD2_STATUS_0_UFS_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DPD2_STATUS_0_UFS_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD2_STATUS_0_UFS_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD2_STATUS_0_UFS_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD2_STATUS_0_UFS_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DPD2_STATUS_0_UFS_INIT_ENUM                 OFF
#define PMC_IMPL_IO_DPD2_STATUS_0_UFS_OFF                       _MK_ENUM_CONST(0)
#define PMC_IMPL_IO_DPD2_STATUS_0_UFS_ON                        _MK_ENUM_CONST(1)

#define PMC_IMPL_IO_DPD2_STATUS_0_CSIG_SHIFT                    _MK_SHIFT_CONST(18)
#define PMC_IMPL_IO_DPD2_STATUS_0_CSIG_FIELD                    _MK_FIELD_CONST(0x1, PMC_IMPL_IO_DPD2_STATUS_0_CSIG_SHIFT)
#define PMC_IMPL_IO_DPD2_STATUS_0_CSIG_RANGE                    18:18
#define PMC_IMPL_IO_DPD2_STATUS_0_CSIG_WOFFSET                  0x0
#define PMC_IMPL_IO_DPD2_STATUS_0_CSIG_DEFAULT                  _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD2_STATUS_0_CSIG_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DPD2_STATUS_0_CSIG_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD2_STATUS_0_CSIG_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD2_STATUS_0_CSIG_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD2_STATUS_0_CSIG_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DPD2_STATUS_0_CSIG_INIT_ENUM                        OFF
#define PMC_IMPL_IO_DPD2_STATUS_0_CSIG_OFF                      _MK_ENUM_CONST(0)
#define PMC_IMPL_IO_DPD2_STATUS_0_CSIG_ON                       _MK_ENUM_CONST(1)

#define PMC_IMPL_IO_DPD2_STATUS_0_CSIH_SHIFT                    _MK_SHIFT_CONST(19)
#define PMC_IMPL_IO_DPD2_STATUS_0_CSIH_FIELD                    _MK_FIELD_CONST(0x1, PMC_IMPL_IO_DPD2_STATUS_0_CSIH_SHIFT)
#define PMC_IMPL_IO_DPD2_STATUS_0_CSIH_RANGE                    19:19
#define PMC_IMPL_IO_DPD2_STATUS_0_CSIH_WOFFSET                  0x0
#define PMC_IMPL_IO_DPD2_STATUS_0_CSIH_DEFAULT                  _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD2_STATUS_0_CSIH_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DPD2_STATUS_0_CSIH_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD2_STATUS_0_CSIH_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD2_STATUS_0_CSIH_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD2_STATUS_0_CSIH_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DPD2_STATUS_0_CSIH_INIT_ENUM                        OFF
#define PMC_IMPL_IO_DPD2_STATUS_0_CSIH_OFF                      _MK_ENUM_CONST(0)
#define PMC_IMPL_IO_DPD2_STATUS_0_CSIH_ON                       _MK_ENUM_CONST(1)

#define PMC_IMPL_IO_DPD2_STATUS_0_EDP_SHIFT                     _MK_SHIFT_CONST(21)
#define PMC_IMPL_IO_DPD2_STATUS_0_EDP_FIELD                     _MK_FIELD_CONST(0x1, PMC_IMPL_IO_DPD2_STATUS_0_EDP_SHIFT)
#define PMC_IMPL_IO_DPD2_STATUS_0_EDP_RANGE                     21:21
#define PMC_IMPL_IO_DPD2_STATUS_0_EDP_WOFFSET                   0x0
#define PMC_IMPL_IO_DPD2_STATUS_0_EDP_DEFAULT                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD2_STATUS_0_EDP_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DPD2_STATUS_0_EDP_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD2_STATUS_0_EDP_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD2_STATUS_0_EDP_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD2_STATUS_0_EDP_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DPD2_STATUS_0_EDP_INIT_ENUM                 OFF
#define PMC_IMPL_IO_DPD2_STATUS_0_EDP_OFF                       _MK_ENUM_CONST(0)
#define PMC_IMPL_IO_DPD2_STATUS_0_EDP_ON                        _MK_ENUM_CONST(1)

#define PMC_IMPL_IO_DPD2_STATUS_0_SDMMC1_HV_SHIFT                       _MK_SHIFT_CONST(23)
#define PMC_IMPL_IO_DPD2_STATUS_0_SDMMC1_HV_FIELD                       _MK_FIELD_CONST(0x1, PMC_IMPL_IO_DPD2_STATUS_0_SDMMC1_HV_SHIFT)
#define PMC_IMPL_IO_DPD2_STATUS_0_SDMMC1_HV_RANGE                       23:23
#define PMC_IMPL_IO_DPD2_STATUS_0_SDMMC1_HV_WOFFSET                     0x0
#define PMC_IMPL_IO_DPD2_STATUS_0_SDMMC1_HV_DEFAULT                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD2_STATUS_0_SDMMC1_HV_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DPD2_STATUS_0_SDMMC1_HV_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD2_STATUS_0_SDMMC1_HV_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD2_STATUS_0_SDMMC1_HV_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD2_STATUS_0_SDMMC1_HV_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DPD2_STATUS_0_SDMMC1_HV_INIT_ENUM                   OFF
#define PMC_IMPL_IO_DPD2_STATUS_0_SDMMC1_HV_OFF                 _MK_ENUM_CONST(0)
#define PMC_IMPL_IO_DPD2_STATUS_0_SDMMC1_HV_ON                  _MK_ENUM_CONST(1)

#define PMC_IMPL_IO_DPD2_STATUS_0_SDMMC3_HV_SHIFT                       _MK_SHIFT_CONST(24)
#define PMC_IMPL_IO_DPD2_STATUS_0_SDMMC3_HV_FIELD                       _MK_FIELD_CONST(0x1, PMC_IMPL_IO_DPD2_STATUS_0_SDMMC3_HV_SHIFT)
#define PMC_IMPL_IO_DPD2_STATUS_0_SDMMC3_HV_RANGE                       24:24
#define PMC_IMPL_IO_DPD2_STATUS_0_SDMMC3_HV_WOFFSET                     0x0
#define PMC_IMPL_IO_DPD2_STATUS_0_SDMMC3_HV_DEFAULT                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD2_STATUS_0_SDMMC3_HV_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DPD2_STATUS_0_SDMMC3_HV_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD2_STATUS_0_SDMMC3_HV_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD2_STATUS_0_SDMMC3_HV_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD2_STATUS_0_SDMMC3_HV_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DPD2_STATUS_0_SDMMC3_HV_INIT_ENUM                   OFF
#define PMC_IMPL_IO_DPD2_STATUS_0_SDMMC3_HV_OFF                 _MK_ENUM_CONST(0)
#define PMC_IMPL_IO_DPD2_STATUS_0_SDMMC3_HV_ON                  _MK_ENUM_CONST(1)

#define PMC_IMPL_IO_DPD2_STATUS_0_CONN_SHIFT                    _MK_SHIFT_CONST(28)
#define PMC_IMPL_IO_DPD2_STATUS_0_CONN_FIELD                    _MK_FIELD_CONST(0x1, PMC_IMPL_IO_DPD2_STATUS_0_CONN_SHIFT)
#define PMC_IMPL_IO_DPD2_STATUS_0_CONN_RANGE                    28:28
#define PMC_IMPL_IO_DPD2_STATUS_0_CONN_WOFFSET                  0x0
#define PMC_IMPL_IO_DPD2_STATUS_0_CONN_DEFAULT                  _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD2_STATUS_0_CONN_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DPD2_STATUS_0_CONN_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD2_STATUS_0_CONN_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD2_STATUS_0_CONN_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD2_STATUS_0_CONN_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DPD2_STATUS_0_CONN_INIT_ENUM                        OFF
#define PMC_IMPL_IO_DPD2_STATUS_0_CONN_OFF                      _MK_ENUM_CONST(0)
#define PMC_IMPL_IO_DPD2_STATUS_0_CONN_ON                       _MK_ENUM_CONST(1)

#define PMC_IMPL_IO_DPD2_STATUS_0_AUDIO_HV_SHIFT                        _MK_SHIFT_CONST(29)
#define PMC_IMPL_IO_DPD2_STATUS_0_AUDIO_HV_FIELD                        _MK_FIELD_CONST(0x1, PMC_IMPL_IO_DPD2_STATUS_0_AUDIO_HV_SHIFT)
#define PMC_IMPL_IO_DPD2_STATUS_0_AUDIO_HV_RANGE                        29:29
#define PMC_IMPL_IO_DPD2_STATUS_0_AUDIO_HV_WOFFSET                      0x0
#define PMC_IMPL_IO_DPD2_STATUS_0_AUDIO_HV_DEFAULT                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD2_STATUS_0_AUDIO_HV_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DPD2_STATUS_0_AUDIO_HV_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD2_STATUS_0_AUDIO_HV_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD2_STATUS_0_AUDIO_HV_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD2_STATUS_0_AUDIO_HV_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DPD2_STATUS_0_AUDIO_HV_INIT_ENUM                    OFF
#define PMC_IMPL_IO_DPD2_STATUS_0_AUDIO_HV_OFF                  _MK_ENUM_CONST(0)
#define PMC_IMPL_IO_DPD2_STATUS_0_AUDIO_HV_ON                   _MK_ENUM_CONST(1)


// Reserved address 0x84

// Reserved address 0x88

// Reserved address 0x8c

// Reserved address 0x90

// Reserved address 0x94

// Reserved address 0x98

// Reserved address 0x9c

// Reserved address 0xa0

// Register PMC_IMPL_IO_DPD7_REQ_0
#define PMC_IMPL_IO_DPD7_REQ_0                  _MK_ADDR_CONST(0xa4)
#define PMC_IMPL_IO_DPD7_REQ_0_SECURE                   0x0
#define PMC_IMPL_IO_DPD7_REQ_0_DUAL                     0x0
#define PMC_IMPL_IO_DPD7_REQ_0_SCR                      IODPD7_SCR_0
#define PMC_IMPL_IO_DPD7_REQ_0_WORD_COUNT                       0x1
#define PMC_IMPL_IO_DPD7_REQ_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD7_REQ_0_RESET_MASK                       _MK_MASK_CONST(0xf3c03fff)
#define PMC_IMPL_IO_DPD7_REQ_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD7_REQ_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD7_REQ_0_READ_MASK                        _MK_MASK_CONST(0xf3c03fff)
#define PMC_IMPL_IO_DPD7_REQ_0_WRITE_MASK                       _MK_MASK_CONST(0xf3c03fff)
#define PMC_IMPL_IO_DPD7_REQ_0_BATT_OC_SHIFT                    _MK_SHIFT_CONST(0)
#define PMC_IMPL_IO_DPD7_REQ_0_BATT_OC_FIELD                    _MK_FIELD_CONST(0x1, PMC_IMPL_IO_DPD7_REQ_0_BATT_OC_SHIFT)
#define PMC_IMPL_IO_DPD7_REQ_0_BATT_OC_RANGE                    0:0
#define PMC_IMPL_IO_DPD7_REQ_0_BATT_OC_WOFFSET                  0x0
#define PMC_IMPL_IO_DPD7_REQ_0_BATT_OC_DEFAULT                  _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD7_REQ_0_BATT_OC_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DPD7_REQ_0_BATT_OC_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD7_REQ_0_BATT_OC_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD7_REQ_0_BATT_OC_PARITY_PROTECTION                        _MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DPD7_REQ_0_BATT_OC_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DPD7_REQ_0_BATT_OC_INIT_ENUM                        OFF
#define PMC_IMPL_IO_DPD7_REQ_0_BATT_OC_OFF                      _MK_ENUM_CONST(0)
#define PMC_IMPL_IO_DPD7_REQ_0_BATT_OC_ON                       _MK_ENUM_CONST(1)

#define PMC_IMPL_IO_DPD7_REQ_0_AO_RETENTION_SHIFT                       _MK_SHIFT_CONST(1)
#define PMC_IMPL_IO_DPD7_REQ_0_AO_RETENTION_FIELD                       _MK_FIELD_CONST(0x1, PMC_IMPL_IO_DPD7_REQ_0_AO_RETENTION_SHIFT)
#define PMC_IMPL_IO_DPD7_REQ_0_AO_RETENTION_RANGE                       1:1
#define PMC_IMPL_IO_DPD7_REQ_0_AO_RETENTION_WOFFSET                     0x0
#define PMC_IMPL_IO_DPD7_REQ_0_AO_RETENTION_DEFAULT                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD7_REQ_0_AO_RETENTION_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DPD7_REQ_0_AO_RETENTION_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD7_REQ_0_AO_RETENTION_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD7_REQ_0_AO_RETENTION_PARITY_PROTECTION                   _MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DPD7_REQ_0_AO_RETENTION_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DPD7_REQ_0_AO_RETENTION_INIT_ENUM                   OFF
#define PMC_IMPL_IO_DPD7_REQ_0_AO_RETENTION_OFF                 _MK_ENUM_CONST(0)
#define PMC_IMPL_IO_DPD7_REQ_0_AO_RETENTION_ON                  _MK_ENUM_CONST(1)

#define PMC_IMPL_IO_DPD7_REQ_0_CAN0_DIN_SHIFT                   _MK_SHIFT_CONST(2)
#define PMC_IMPL_IO_DPD7_REQ_0_CAN0_DIN_FIELD                   _MK_FIELD_CONST(0x1, PMC_IMPL_IO_DPD7_REQ_0_CAN0_DIN_SHIFT)
#define PMC_IMPL_IO_DPD7_REQ_0_CAN0_DIN_RANGE                   2:2
#define PMC_IMPL_IO_DPD7_REQ_0_CAN0_DIN_WOFFSET                 0x0
#define PMC_IMPL_IO_DPD7_REQ_0_CAN0_DIN_DEFAULT                 _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD7_REQ_0_CAN0_DIN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DPD7_REQ_0_CAN0_DIN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD7_REQ_0_CAN0_DIN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD7_REQ_0_CAN0_DIN_PARITY_PROTECTION                       _MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DPD7_REQ_0_CAN0_DIN_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DPD7_REQ_0_CAN0_DIN_INIT_ENUM                       OFF
#define PMC_IMPL_IO_DPD7_REQ_0_CAN0_DIN_OFF                     _MK_ENUM_CONST(0)
#define PMC_IMPL_IO_DPD7_REQ_0_CAN0_DIN_ON                      _MK_ENUM_CONST(1)

#define PMC_IMPL_IO_DPD7_REQ_0_CAN0_DOUT_SHIFT                  _MK_SHIFT_CONST(3)
#define PMC_IMPL_IO_DPD7_REQ_0_CAN0_DOUT_FIELD                  _MK_FIELD_CONST(0x1, PMC_IMPL_IO_DPD7_REQ_0_CAN0_DOUT_SHIFT)
#define PMC_IMPL_IO_DPD7_REQ_0_CAN0_DOUT_RANGE                  3:3
#define PMC_IMPL_IO_DPD7_REQ_0_CAN0_DOUT_WOFFSET                        0x0
#define PMC_IMPL_IO_DPD7_REQ_0_CAN0_DOUT_DEFAULT                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD7_REQ_0_CAN0_DOUT_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DPD7_REQ_0_CAN0_DOUT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD7_REQ_0_CAN0_DOUT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD7_REQ_0_CAN0_DOUT_PARITY_PROTECTION                      _MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DPD7_REQ_0_CAN0_DOUT_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DPD7_REQ_0_CAN0_DOUT_INIT_ENUM                      OFF
#define PMC_IMPL_IO_DPD7_REQ_0_CAN0_DOUT_OFF                    _MK_ENUM_CONST(0)
#define PMC_IMPL_IO_DPD7_REQ_0_CAN0_DOUT_ON                     _MK_ENUM_CONST(1)

#define PMC_IMPL_IO_DPD7_REQ_0_CAN1_DIN_SHIFT                   _MK_SHIFT_CONST(4)
#define PMC_IMPL_IO_DPD7_REQ_0_CAN1_DIN_FIELD                   _MK_FIELD_CONST(0x1, PMC_IMPL_IO_DPD7_REQ_0_CAN1_DIN_SHIFT)
#define PMC_IMPL_IO_DPD7_REQ_0_CAN1_DIN_RANGE                   4:4
#define PMC_IMPL_IO_DPD7_REQ_0_CAN1_DIN_WOFFSET                 0x0
#define PMC_IMPL_IO_DPD7_REQ_0_CAN1_DIN_DEFAULT                 _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD7_REQ_0_CAN1_DIN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DPD7_REQ_0_CAN1_DIN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD7_REQ_0_CAN1_DIN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD7_REQ_0_CAN1_DIN_PARITY_PROTECTION                       _MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DPD7_REQ_0_CAN1_DIN_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DPD7_REQ_0_CAN1_DIN_INIT_ENUM                       OFF
#define PMC_IMPL_IO_DPD7_REQ_0_CAN1_DIN_OFF                     _MK_ENUM_CONST(0)
#define PMC_IMPL_IO_DPD7_REQ_0_CAN1_DIN_ON                      _MK_ENUM_CONST(1)

#define PMC_IMPL_IO_DPD7_REQ_0_CAN1_DOUT_SHIFT                  _MK_SHIFT_CONST(5)
#define PMC_IMPL_IO_DPD7_REQ_0_CAN1_DOUT_FIELD                  _MK_FIELD_CONST(0x1, PMC_IMPL_IO_DPD7_REQ_0_CAN1_DOUT_SHIFT)
#define PMC_IMPL_IO_DPD7_REQ_0_CAN1_DOUT_RANGE                  5:5
#define PMC_IMPL_IO_DPD7_REQ_0_CAN1_DOUT_WOFFSET                        0x0
#define PMC_IMPL_IO_DPD7_REQ_0_CAN1_DOUT_DEFAULT                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD7_REQ_0_CAN1_DOUT_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DPD7_REQ_0_CAN1_DOUT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD7_REQ_0_CAN1_DOUT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD7_REQ_0_CAN1_DOUT_PARITY_PROTECTION                      _MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DPD7_REQ_0_CAN1_DOUT_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DPD7_REQ_0_CAN1_DOUT_INIT_ENUM                      OFF
#define PMC_IMPL_IO_DPD7_REQ_0_CAN1_DOUT_OFF                    _MK_ENUM_CONST(0)
#define PMC_IMPL_IO_DPD7_REQ_0_CAN1_DOUT_ON                     _MK_ENUM_CONST(1)

#define PMC_IMPL_IO_DPD7_REQ_0_CAN0_STB_SHIFT                   _MK_SHIFT_CONST(6)
#define PMC_IMPL_IO_DPD7_REQ_0_CAN0_STB_FIELD                   _MK_FIELD_CONST(0x1, PMC_IMPL_IO_DPD7_REQ_0_CAN0_STB_SHIFT)
#define PMC_IMPL_IO_DPD7_REQ_0_CAN0_STB_RANGE                   6:6
#define PMC_IMPL_IO_DPD7_REQ_0_CAN0_STB_WOFFSET                 0x0
#define PMC_IMPL_IO_DPD7_REQ_0_CAN0_STB_DEFAULT                 _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD7_REQ_0_CAN0_STB_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DPD7_REQ_0_CAN0_STB_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD7_REQ_0_CAN0_STB_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD7_REQ_0_CAN0_STB_PARITY_PROTECTION                       _MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DPD7_REQ_0_CAN0_STB_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DPD7_REQ_0_CAN0_STB_INIT_ENUM                       OFF
#define PMC_IMPL_IO_DPD7_REQ_0_CAN0_STB_OFF                     _MK_ENUM_CONST(0)
#define PMC_IMPL_IO_DPD7_REQ_0_CAN0_STB_ON                      _MK_ENUM_CONST(1)

#define PMC_IMPL_IO_DPD7_REQ_0_CAN0_EN_SHIFT                    _MK_SHIFT_CONST(7)
#define PMC_IMPL_IO_DPD7_REQ_0_CAN0_EN_FIELD                    _MK_FIELD_CONST(0x1, PMC_IMPL_IO_DPD7_REQ_0_CAN0_EN_SHIFT)
#define PMC_IMPL_IO_DPD7_REQ_0_CAN0_EN_RANGE                    7:7
#define PMC_IMPL_IO_DPD7_REQ_0_CAN0_EN_WOFFSET                  0x0
#define PMC_IMPL_IO_DPD7_REQ_0_CAN0_EN_DEFAULT                  _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD7_REQ_0_CAN0_EN_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DPD7_REQ_0_CAN0_EN_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD7_REQ_0_CAN0_EN_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD7_REQ_0_CAN0_EN_PARITY_PROTECTION                        _MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DPD7_REQ_0_CAN0_EN_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DPD7_REQ_0_CAN0_EN_INIT_ENUM                        OFF
#define PMC_IMPL_IO_DPD7_REQ_0_CAN0_EN_OFF                      _MK_ENUM_CONST(0)
#define PMC_IMPL_IO_DPD7_REQ_0_CAN0_EN_ON                       _MK_ENUM_CONST(1)

#define PMC_IMPL_IO_DPD7_REQ_0_GEN2_I2C_SCL_SHIFT                       _MK_SHIFT_CONST(8)
#define PMC_IMPL_IO_DPD7_REQ_0_GEN2_I2C_SCL_FIELD                       _MK_FIELD_CONST(0x1, PMC_IMPL_IO_DPD7_REQ_0_GEN2_I2C_SCL_SHIFT)
#define PMC_IMPL_IO_DPD7_REQ_0_GEN2_I2C_SCL_RANGE                       8:8
#define PMC_IMPL_IO_DPD7_REQ_0_GEN2_I2C_SCL_WOFFSET                     0x0
#define PMC_IMPL_IO_DPD7_REQ_0_GEN2_I2C_SCL_DEFAULT                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD7_REQ_0_GEN2_I2C_SCL_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DPD7_REQ_0_GEN2_I2C_SCL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD7_REQ_0_GEN2_I2C_SCL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD7_REQ_0_GEN2_I2C_SCL_PARITY_PROTECTION                   _MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DPD7_REQ_0_GEN2_I2C_SCL_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DPD7_REQ_0_GEN2_I2C_SCL_INIT_ENUM                   OFF
#define PMC_IMPL_IO_DPD7_REQ_0_GEN2_I2C_SCL_OFF                 _MK_ENUM_CONST(0)
#define PMC_IMPL_IO_DPD7_REQ_0_GEN2_I2C_SCL_ON                  _MK_ENUM_CONST(1)

#define PMC_IMPL_IO_DPD7_REQ_0_GEN2_I2C_SDA_SHIFT                       _MK_SHIFT_CONST(9)
#define PMC_IMPL_IO_DPD7_REQ_0_GEN2_I2C_SDA_FIELD                       _MK_FIELD_CONST(0x1, PMC_IMPL_IO_DPD7_REQ_0_GEN2_I2C_SDA_SHIFT)
#define PMC_IMPL_IO_DPD7_REQ_0_GEN2_I2C_SDA_RANGE                       9:9
#define PMC_IMPL_IO_DPD7_REQ_0_GEN2_I2C_SDA_WOFFSET                     0x0
#define PMC_IMPL_IO_DPD7_REQ_0_GEN2_I2C_SDA_DEFAULT                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD7_REQ_0_GEN2_I2C_SDA_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DPD7_REQ_0_GEN2_I2C_SDA_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD7_REQ_0_GEN2_I2C_SDA_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD7_REQ_0_GEN2_I2C_SDA_PARITY_PROTECTION                   _MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DPD7_REQ_0_GEN2_I2C_SDA_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DPD7_REQ_0_GEN2_I2C_SDA_INIT_ENUM                   OFF
#define PMC_IMPL_IO_DPD7_REQ_0_GEN2_I2C_SDA_OFF                 _MK_ENUM_CONST(0)
#define PMC_IMPL_IO_DPD7_REQ_0_GEN2_I2C_SDA_ON                  _MK_ENUM_CONST(1)

#define PMC_IMPL_IO_DPD7_REQ_0_SPI2_CS0_SHIFT                   _MK_SHIFT_CONST(10)
#define PMC_IMPL_IO_DPD7_REQ_0_SPI2_CS0_FIELD                   _MK_FIELD_CONST(0x1, PMC_IMPL_IO_DPD7_REQ_0_SPI2_CS0_SHIFT)
#define PMC_IMPL_IO_DPD7_REQ_0_SPI2_CS0_RANGE                   10:10
#define PMC_IMPL_IO_DPD7_REQ_0_SPI2_CS0_WOFFSET                 0x0
#define PMC_IMPL_IO_DPD7_REQ_0_SPI2_CS0_DEFAULT                 _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD7_REQ_0_SPI2_CS0_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DPD7_REQ_0_SPI2_CS0_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD7_REQ_0_SPI2_CS0_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD7_REQ_0_SPI2_CS0_PARITY_PROTECTION                       _MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DPD7_REQ_0_SPI2_CS0_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DPD7_REQ_0_SPI2_CS0_INIT_ENUM                       OFF
#define PMC_IMPL_IO_DPD7_REQ_0_SPI2_CS0_OFF                     _MK_ENUM_CONST(0)
#define PMC_IMPL_IO_DPD7_REQ_0_SPI2_CS0_ON                      _MK_ENUM_CONST(1)

#define PMC_IMPL_IO_DPD7_REQ_0_SPI2_MISO_SHIFT                  _MK_SHIFT_CONST(11)
#define PMC_IMPL_IO_DPD7_REQ_0_SPI2_MISO_FIELD                  _MK_FIELD_CONST(0x1, PMC_IMPL_IO_DPD7_REQ_0_SPI2_MISO_SHIFT)
#define PMC_IMPL_IO_DPD7_REQ_0_SPI2_MISO_RANGE                  11:11
#define PMC_IMPL_IO_DPD7_REQ_0_SPI2_MISO_WOFFSET                        0x0
#define PMC_IMPL_IO_DPD7_REQ_0_SPI2_MISO_DEFAULT                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD7_REQ_0_SPI2_MISO_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DPD7_REQ_0_SPI2_MISO_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD7_REQ_0_SPI2_MISO_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD7_REQ_0_SPI2_MISO_PARITY_PROTECTION                      _MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DPD7_REQ_0_SPI2_MISO_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DPD7_REQ_0_SPI2_MISO_INIT_ENUM                      OFF
#define PMC_IMPL_IO_DPD7_REQ_0_SPI2_MISO_OFF                    _MK_ENUM_CONST(0)
#define PMC_IMPL_IO_DPD7_REQ_0_SPI2_MISO_ON                     _MK_ENUM_CONST(1)

#define PMC_IMPL_IO_DPD7_REQ_0_SPI2_MOSI_SHIFT                  _MK_SHIFT_CONST(12)
#define PMC_IMPL_IO_DPD7_REQ_0_SPI2_MOSI_FIELD                  _MK_FIELD_CONST(0x1, PMC_IMPL_IO_DPD7_REQ_0_SPI2_MOSI_SHIFT)
#define PMC_IMPL_IO_DPD7_REQ_0_SPI2_MOSI_RANGE                  12:12
#define PMC_IMPL_IO_DPD7_REQ_0_SPI2_MOSI_WOFFSET                        0x0
#define PMC_IMPL_IO_DPD7_REQ_0_SPI2_MOSI_DEFAULT                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD7_REQ_0_SPI2_MOSI_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DPD7_REQ_0_SPI2_MOSI_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD7_REQ_0_SPI2_MOSI_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD7_REQ_0_SPI2_MOSI_PARITY_PROTECTION                      _MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DPD7_REQ_0_SPI2_MOSI_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DPD7_REQ_0_SPI2_MOSI_INIT_ENUM                      OFF
#define PMC_IMPL_IO_DPD7_REQ_0_SPI2_MOSI_OFF                    _MK_ENUM_CONST(0)
#define PMC_IMPL_IO_DPD7_REQ_0_SPI2_MOSI_ON                     _MK_ENUM_CONST(1)

#define PMC_IMPL_IO_DPD7_REQ_0_SPI2_SCK_SHIFT                   _MK_SHIFT_CONST(13)
#define PMC_IMPL_IO_DPD7_REQ_0_SPI2_SCK_FIELD                   _MK_FIELD_CONST(0x1, PMC_IMPL_IO_DPD7_REQ_0_SPI2_SCK_SHIFT)
#define PMC_IMPL_IO_DPD7_REQ_0_SPI2_SCK_RANGE                   13:13
#define PMC_IMPL_IO_DPD7_REQ_0_SPI2_SCK_WOFFSET                 0x0
#define PMC_IMPL_IO_DPD7_REQ_0_SPI2_SCK_DEFAULT                 _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD7_REQ_0_SPI2_SCK_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DPD7_REQ_0_SPI2_SCK_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD7_REQ_0_SPI2_SCK_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD7_REQ_0_SPI2_SCK_PARITY_PROTECTION                       _MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DPD7_REQ_0_SPI2_SCK_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DPD7_REQ_0_SPI2_SCK_INIT_ENUM                       OFF
#define PMC_IMPL_IO_DPD7_REQ_0_SPI2_SCK_OFF                     _MK_ENUM_CONST(0)
#define PMC_IMPL_IO_DPD7_REQ_0_SPI2_SCK_ON                      _MK_ENUM_CONST(1)

#define PMC_IMPL_IO_DPD7_REQ_0_CAN0_WAKE_SHIFT                  _MK_SHIFT_CONST(22)
#define PMC_IMPL_IO_DPD7_REQ_0_CAN0_WAKE_FIELD                  _MK_FIELD_CONST(0x1, PMC_IMPL_IO_DPD7_REQ_0_CAN0_WAKE_SHIFT)
#define PMC_IMPL_IO_DPD7_REQ_0_CAN0_WAKE_RANGE                  22:22
#define PMC_IMPL_IO_DPD7_REQ_0_CAN0_WAKE_WOFFSET                        0x0
#define PMC_IMPL_IO_DPD7_REQ_0_CAN0_WAKE_DEFAULT                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD7_REQ_0_CAN0_WAKE_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DPD7_REQ_0_CAN0_WAKE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD7_REQ_0_CAN0_WAKE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD7_REQ_0_CAN0_WAKE_PARITY_PROTECTION                      _MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DPD7_REQ_0_CAN0_WAKE_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DPD7_REQ_0_CAN0_WAKE_INIT_ENUM                      OFF
#define PMC_IMPL_IO_DPD7_REQ_0_CAN0_WAKE_OFF                    _MK_ENUM_CONST(0)
#define PMC_IMPL_IO_DPD7_REQ_0_CAN0_WAKE_ON                     _MK_ENUM_CONST(1)

#define PMC_IMPL_IO_DPD7_REQ_0_CAN0_ERR_SHIFT                   _MK_SHIFT_CONST(23)
#define PMC_IMPL_IO_DPD7_REQ_0_CAN0_ERR_FIELD                   _MK_FIELD_CONST(0x1, PMC_IMPL_IO_DPD7_REQ_0_CAN0_ERR_SHIFT)
#define PMC_IMPL_IO_DPD7_REQ_0_CAN0_ERR_RANGE                   23:23
#define PMC_IMPL_IO_DPD7_REQ_0_CAN0_ERR_WOFFSET                 0x0
#define PMC_IMPL_IO_DPD7_REQ_0_CAN0_ERR_DEFAULT                 _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD7_REQ_0_CAN0_ERR_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DPD7_REQ_0_CAN0_ERR_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD7_REQ_0_CAN0_ERR_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD7_REQ_0_CAN0_ERR_PARITY_PROTECTION                       _MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DPD7_REQ_0_CAN0_ERR_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DPD7_REQ_0_CAN0_ERR_INIT_ENUM                       OFF
#define PMC_IMPL_IO_DPD7_REQ_0_CAN0_ERR_OFF                     _MK_ENUM_CONST(0)
#define PMC_IMPL_IO_DPD7_REQ_0_CAN0_ERR_ON                      _MK_ENUM_CONST(1)

#define PMC_IMPL_IO_DPD7_REQ_0_CAN1_STB_SHIFT                   _MK_SHIFT_CONST(24)
#define PMC_IMPL_IO_DPD7_REQ_0_CAN1_STB_FIELD                   _MK_FIELD_CONST(0x1, PMC_IMPL_IO_DPD7_REQ_0_CAN1_STB_SHIFT)
#define PMC_IMPL_IO_DPD7_REQ_0_CAN1_STB_RANGE                   24:24
#define PMC_IMPL_IO_DPD7_REQ_0_CAN1_STB_WOFFSET                 0x0
#define PMC_IMPL_IO_DPD7_REQ_0_CAN1_STB_DEFAULT                 _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD7_REQ_0_CAN1_STB_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DPD7_REQ_0_CAN1_STB_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD7_REQ_0_CAN1_STB_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD7_REQ_0_CAN1_STB_PARITY_PROTECTION                       _MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DPD7_REQ_0_CAN1_STB_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DPD7_REQ_0_CAN1_STB_INIT_ENUM                       OFF
#define PMC_IMPL_IO_DPD7_REQ_0_CAN1_STB_OFF                     _MK_ENUM_CONST(0)
#define PMC_IMPL_IO_DPD7_REQ_0_CAN1_STB_ON                      _MK_ENUM_CONST(1)

#define PMC_IMPL_IO_DPD7_REQ_0_CAN1_EN_SHIFT                    _MK_SHIFT_CONST(25)
#define PMC_IMPL_IO_DPD7_REQ_0_CAN1_EN_FIELD                    _MK_FIELD_CONST(0x1, PMC_IMPL_IO_DPD7_REQ_0_CAN1_EN_SHIFT)
#define PMC_IMPL_IO_DPD7_REQ_0_CAN1_EN_RANGE                    25:25
#define PMC_IMPL_IO_DPD7_REQ_0_CAN1_EN_WOFFSET                  0x0
#define PMC_IMPL_IO_DPD7_REQ_0_CAN1_EN_DEFAULT                  _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD7_REQ_0_CAN1_EN_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DPD7_REQ_0_CAN1_EN_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD7_REQ_0_CAN1_EN_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD7_REQ_0_CAN1_EN_PARITY_PROTECTION                        _MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DPD7_REQ_0_CAN1_EN_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DPD7_REQ_0_CAN1_EN_INIT_ENUM                        OFF
#define PMC_IMPL_IO_DPD7_REQ_0_CAN1_EN_OFF                      _MK_ENUM_CONST(0)
#define PMC_IMPL_IO_DPD7_REQ_0_CAN1_EN_ON                       _MK_ENUM_CONST(1)

#define PMC_IMPL_IO_DPD7_REQ_0_UART3_RX_SHIFT                   _MK_SHIFT_CONST(28)
#define PMC_IMPL_IO_DPD7_REQ_0_UART3_RX_FIELD                   _MK_FIELD_CONST(0x1, PMC_IMPL_IO_DPD7_REQ_0_UART3_RX_SHIFT)
#define PMC_IMPL_IO_DPD7_REQ_0_UART3_RX_RANGE                   28:28
#define PMC_IMPL_IO_DPD7_REQ_0_UART3_RX_WOFFSET                 0x0
#define PMC_IMPL_IO_DPD7_REQ_0_UART3_RX_DEFAULT                 _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD7_REQ_0_UART3_RX_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DPD7_REQ_0_UART3_RX_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD7_REQ_0_UART3_RX_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD7_REQ_0_UART3_RX_PARITY_PROTECTION                       _MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DPD7_REQ_0_UART3_RX_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DPD7_REQ_0_UART3_RX_INIT_ENUM                       OFF
#define PMC_IMPL_IO_DPD7_REQ_0_UART3_RX_OFF                     _MK_ENUM_CONST(0)
#define PMC_IMPL_IO_DPD7_REQ_0_UART3_RX_ON                      _MK_ENUM_CONST(1)

#define PMC_IMPL_IO_DPD7_REQ_0_UART3_TX_SHIFT                   _MK_SHIFT_CONST(29)
#define PMC_IMPL_IO_DPD7_REQ_0_UART3_TX_FIELD                   _MK_FIELD_CONST(0x1, PMC_IMPL_IO_DPD7_REQ_0_UART3_TX_SHIFT)
#define PMC_IMPL_IO_DPD7_REQ_0_UART3_TX_RANGE                   29:29
#define PMC_IMPL_IO_DPD7_REQ_0_UART3_TX_WOFFSET                 0x0
#define PMC_IMPL_IO_DPD7_REQ_0_UART3_TX_DEFAULT                 _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD7_REQ_0_UART3_TX_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DPD7_REQ_0_UART3_TX_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD7_REQ_0_UART3_TX_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD7_REQ_0_UART3_TX_PARITY_PROTECTION                       _MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DPD7_REQ_0_UART3_TX_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DPD7_REQ_0_UART3_TX_INIT_ENUM                       OFF
#define PMC_IMPL_IO_DPD7_REQ_0_UART3_TX_OFF                     _MK_ENUM_CONST(0)
#define PMC_IMPL_IO_DPD7_REQ_0_UART3_TX_ON                      _MK_ENUM_CONST(1)

#define PMC_IMPL_IO_DPD7_REQ_0_CODE_SHIFT                       _MK_SHIFT_CONST(30)
#define PMC_IMPL_IO_DPD7_REQ_0_CODE_FIELD                       _MK_FIELD_CONST(0x3, PMC_IMPL_IO_DPD7_REQ_0_CODE_SHIFT)
#define PMC_IMPL_IO_DPD7_REQ_0_CODE_RANGE                       31:30
#define PMC_IMPL_IO_DPD7_REQ_0_CODE_WOFFSET                     0x0
#define PMC_IMPL_IO_DPD7_REQ_0_CODE_DEFAULT                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD7_REQ_0_CODE_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
#define PMC_IMPL_IO_DPD7_REQ_0_CODE_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD7_REQ_0_CODE_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD7_REQ_0_CODE_PARITY_PROTECTION                   _MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DPD7_REQ_0_CODE_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DPD7_REQ_0_CODE_INIT_ENUM                   IDLE
#define PMC_IMPL_IO_DPD7_REQ_0_CODE_IDLE                        _MK_ENUM_CONST(0)
#define PMC_IMPL_IO_DPD7_REQ_0_CODE_DPD_OFF                     _MK_ENUM_CONST(1)
#define PMC_IMPL_IO_DPD7_REQ_0_CODE_DPD_ON                      _MK_ENUM_CONST(2)


// Register PMC_IMPL_IO_DPD7_STATUS_0
#define PMC_IMPL_IO_DPD7_STATUS_0                       _MK_ADDR_CONST(0xa8)
#define PMC_IMPL_IO_DPD7_STATUS_0_SECURE                        0x0
#define PMC_IMPL_IO_DPD7_STATUS_0_DUAL                  0x0
#define PMC_IMPL_IO_DPD7_STATUS_0_SCR                   IODPD7_SCR_0
#define PMC_IMPL_IO_DPD7_STATUS_0_WORD_COUNT                    0x1
#define PMC_IMPL_IO_DPD7_STATUS_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD7_STATUS_0_RESET_MASK                    _MK_MASK_CONST(0x33c03fff)
#define PMC_IMPL_IO_DPD7_STATUS_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD7_STATUS_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD7_STATUS_0_READ_MASK                     _MK_MASK_CONST(0x33c03fff)
#define PMC_IMPL_IO_DPD7_STATUS_0_WRITE_MASK                    _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD7_STATUS_0_BATT_OC_SHIFT                 _MK_SHIFT_CONST(0)
#define PMC_IMPL_IO_DPD7_STATUS_0_BATT_OC_FIELD                 _MK_FIELD_CONST(0x1, PMC_IMPL_IO_DPD7_STATUS_0_BATT_OC_SHIFT)
#define PMC_IMPL_IO_DPD7_STATUS_0_BATT_OC_RANGE                 0:0
#define PMC_IMPL_IO_DPD7_STATUS_0_BATT_OC_WOFFSET                       0x0
#define PMC_IMPL_IO_DPD7_STATUS_0_BATT_OC_DEFAULT                       _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD7_STATUS_0_BATT_OC_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DPD7_STATUS_0_BATT_OC_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD7_STATUS_0_BATT_OC_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD7_STATUS_0_BATT_OC_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD7_STATUS_0_BATT_OC_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DPD7_STATUS_0_BATT_OC_INIT_ENUM                     OFF
#define PMC_IMPL_IO_DPD7_STATUS_0_BATT_OC_OFF                   _MK_ENUM_CONST(0)
#define PMC_IMPL_IO_DPD7_STATUS_0_BATT_OC_ON                    _MK_ENUM_CONST(1)

#define PMC_IMPL_IO_DPD7_STATUS_0_AO_RETENTION_SHIFT                    _MK_SHIFT_CONST(1)
#define PMC_IMPL_IO_DPD7_STATUS_0_AO_RETENTION_FIELD                    _MK_FIELD_CONST(0x1, PMC_IMPL_IO_DPD7_STATUS_0_AO_RETENTION_SHIFT)
#define PMC_IMPL_IO_DPD7_STATUS_0_AO_RETENTION_RANGE                    1:1
#define PMC_IMPL_IO_DPD7_STATUS_0_AO_RETENTION_WOFFSET                  0x0
#define PMC_IMPL_IO_DPD7_STATUS_0_AO_RETENTION_DEFAULT                  _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD7_STATUS_0_AO_RETENTION_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DPD7_STATUS_0_AO_RETENTION_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD7_STATUS_0_AO_RETENTION_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD7_STATUS_0_AO_RETENTION_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD7_STATUS_0_AO_RETENTION_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DPD7_STATUS_0_AO_RETENTION_INIT_ENUM                        OFF
#define PMC_IMPL_IO_DPD7_STATUS_0_AO_RETENTION_OFF                      _MK_ENUM_CONST(0)
#define PMC_IMPL_IO_DPD7_STATUS_0_AO_RETENTION_ON                       _MK_ENUM_CONST(1)

#define PMC_IMPL_IO_DPD7_STATUS_0_CAN0_DIN_SHIFT                        _MK_SHIFT_CONST(2)
#define PMC_IMPL_IO_DPD7_STATUS_0_CAN0_DIN_FIELD                        _MK_FIELD_CONST(0x1, PMC_IMPL_IO_DPD7_STATUS_0_CAN0_DIN_SHIFT)
#define PMC_IMPL_IO_DPD7_STATUS_0_CAN0_DIN_RANGE                        2:2
#define PMC_IMPL_IO_DPD7_STATUS_0_CAN0_DIN_WOFFSET                      0x0
#define PMC_IMPL_IO_DPD7_STATUS_0_CAN0_DIN_DEFAULT                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD7_STATUS_0_CAN0_DIN_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DPD7_STATUS_0_CAN0_DIN_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD7_STATUS_0_CAN0_DIN_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD7_STATUS_0_CAN0_DIN_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD7_STATUS_0_CAN0_DIN_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DPD7_STATUS_0_CAN0_DIN_INIT_ENUM                    OFF
#define PMC_IMPL_IO_DPD7_STATUS_0_CAN0_DIN_OFF                  _MK_ENUM_CONST(0)
#define PMC_IMPL_IO_DPD7_STATUS_0_CAN0_DIN_ON                   _MK_ENUM_CONST(1)

#define PMC_IMPL_IO_DPD7_STATUS_0_CAN0_DOUT_SHIFT                       _MK_SHIFT_CONST(3)
#define PMC_IMPL_IO_DPD7_STATUS_0_CAN0_DOUT_FIELD                       _MK_FIELD_CONST(0x1, PMC_IMPL_IO_DPD7_STATUS_0_CAN0_DOUT_SHIFT)
#define PMC_IMPL_IO_DPD7_STATUS_0_CAN0_DOUT_RANGE                       3:3
#define PMC_IMPL_IO_DPD7_STATUS_0_CAN0_DOUT_WOFFSET                     0x0
#define PMC_IMPL_IO_DPD7_STATUS_0_CAN0_DOUT_DEFAULT                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD7_STATUS_0_CAN0_DOUT_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DPD7_STATUS_0_CAN0_DOUT_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD7_STATUS_0_CAN0_DOUT_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD7_STATUS_0_CAN0_DOUT_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD7_STATUS_0_CAN0_DOUT_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DPD7_STATUS_0_CAN0_DOUT_INIT_ENUM                   OFF
#define PMC_IMPL_IO_DPD7_STATUS_0_CAN0_DOUT_OFF                 _MK_ENUM_CONST(0)
#define PMC_IMPL_IO_DPD7_STATUS_0_CAN0_DOUT_ON                  _MK_ENUM_CONST(1)

#define PMC_IMPL_IO_DPD7_STATUS_0_CAN1_DIN_SHIFT                        _MK_SHIFT_CONST(4)
#define PMC_IMPL_IO_DPD7_STATUS_0_CAN1_DIN_FIELD                        _MK_FIELD_CONST(0x1, PMC_IMPL_IO_DPD7_STATUS_0_CAN1_DIN_SHIFT)
#define PMC_IMPL_IO_DPD7_STATUS_0_CAN1_DIN_RANGE                        4:4
#define PMC_IMPL_IO_DPD7_STATUS_0_CAN1_DIN_WOFFSET                      0x0
#define PMC_IMPL_IO_DPD7_STATUS_0_CAN1_DIN_DEFAULT                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD7_STATUS_0_CAN1_DIN_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DPD7_STATUS_0_CAN1_DIN_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD7_STATUS_0_CAN1_DIN_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD7_STATUS_0_CAN1_DIN_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD7_STATUS_0_CAN1_DIN_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DPD7_STATUS_0_CAN1_DIN_INIT_ENUM                    OFF
#define PMC_IMPL_IO_DPD7_STATUS_0_CAN1_DIN_OFF                  _MK_ENUM_CONST(0)
#define PMC_IMPL_IO_DPD7_STATUS_0_CAN1_DIN_ON                   _MK_ENUM_CONST(1)

#define PMC_IMPL_IO_DPD7_STATUS_0_CAN1_DOUT_SHIFT                       _MK_SHIFT_CONST(5)
#define PMC_IMPL_IO_DPD7_STATUS_0_CAN1_DOUT_FIELD                       _MK_FIELD_CONST(0x1, PMC_IMPL_IO_DPD7_STATUS_0_CAN1_DOUT_SHIFT)
#define PMC_IMPL_IO_DPD7_STATUS_0_CAN1_DOUT_RANGE                       5:5
#define PMC_IMPL_IO_DPD7_STATUS_0_CAN1_DOUT_WOFFSET                     0x0
#define PMC_IMPL_IO_DPD7_STATUS_0_CAN1_DOUT_DEFAULT                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD7_STATUS_0_CAN1_DOUT_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DPD7_STATUS_0_CAN1_DOUT_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD7_STATUS_0_CAN1_DOUT_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD7_STATUS_0_CAN1_DOUT_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD7_STATUS_0_CAN1_DOUT_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DPD7_STATUS_0_CAN1_DOUT_INIT_ENUM                   OFF
#define PMC_IMPL_IO_DPD7_STATUS_0_CAN1_DOUT_OFF                 _MK_ENUM_CONST(0)
#define PMC_IMPL_IO_DPD7_STATUS_0_CAN1_DOUT_ON                  _MK_ENUM_CONST(1)

#define PMC_IMPL_IO_DPD7_STATUS_0_CAN0_STB_SHIFT                        _MK_SHIFT_CONST(6)
#define PMC_IMPL_IO_DPD7_STATUS_0_CAN0_STB_FIELD                        _MK_FIELD_CONST(0x1, PMC_IMPL_IO_DPD7_STATUS_0_CAN0_STB_SHIFT)
#define PMC_IMPL_IO_DPD7_STATUS_0_CAN0_STB_RANGE                        6:6
#define PMC_IMPL_IO_DPD7_STATUS_0_CAN0_STB_WOFFSET                      0x0
#define PMC_IMPL_IO_DPD7_STATUS_0_CAN0_STB_DEFAULT                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD7_STATUS_0_CAN0_STB_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DPD7_STATUS_0_CAN0_STB_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD7_STATUS_0_CAN0_STB_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD7_STATUS_0_CAN0_STB_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD7_STATUS_0_CAN0_STB_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DPD7_STATUS_0_CAN0_STB_INIT_ENUM                    OFF
#define PMC_IMPL_IO_DPD7_STATUS_0_CAN0_STB_OFF                  _MK_ENUM_CONST(0)
#define PMC_IMPL_IO_DPD7_STATUS_0_CAN0_STB_ON                   _MK_ENUM_CONST(1)

#define PMC_IMPL_IO_DPD7_STATUS_0_CAN0_EN_SHIFT                 _MK_SHIFT_CONST(7)
#define PMC_IMPL_IO_DPD7_STATUS_0_CAN0_EN_FIELD                 _MK_FIELD_CONST(0x1, PMC_IMPL_IO_DPD7_STATUS_0_CAN0_EN_SHIFT)
#define PMC_IMPL_IO_DPD7_STATUS_0_CAN0_EN_RANGE                 7:7
#define PMC_IMPL_IO_DPD7_STATUS_0_CAN0_EN_WOFFSET                       0x0
#define PMC_IMPL_IO_DPD7_STATUS_0_CAN0_EN_DEFAULT                       _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD7_STATUS_0_CAN0_EN_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DPD7_STATUS_0_CAN0_EN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD7_STATUS_0_CAN0_EN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD7_STATUS_0_CAN0_EN_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD7_STATUS_0_CAN0_EN_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DPD7_STATUS_0_CAN0_EN_INIT_ENUM                     OFF
#define PMC_IMPL_IO_DPD7_STATUS_0_CAN0_EN_OFF                   _MK_ENUM_CONST(0)
#define PMC_IMPL_IO_DPD7_STATUS_0_CAN0_EN_ON                    _MK_ENUM_CONST(1)

#define PMC_IMPL_IO_DPD7_STATUS_0_GEN2_I2C_SCL_SHIFT                    _MK_SHIFT_CONST(8)
#define PMC_IMPL_IO_DPD7_STATUS_0_GEN2_I2C_SCL_FIELD                    _MK_FIELD_CONST(0x1, PMC_IMPL_IO_DPD7_STATUS_0_GEN2_I2C_SCL_SHIFT)
#define PMC_IMPL_IO_DPD7_STATUS_0_GEN2_I2C_SCL_RANGE                    8:8
#define PMC_IMPL_IO_DPD7_STATUS_0_GEN2_I2C_SCL_WOFFSET                  0x0
#define PMC_IMPL_IO_DPD7_STATUS_0_GEN2_I2C_SCL_DEFAULT                  _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD7_STATUS_0_GEN2_I2C_SCL_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DPD7_STATUS_0_GEN2_I2C_SCL_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD7_STATUS_0_GEN2_I2C_SCL_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD7_STATUS_0_GEN2_I2C_SCL_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD7_STATUS_0_GEN2_I2C_SCL_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DPD7_STATUS_0_GEN2_I2C_SCL_INIT_ENUM                        OFF
#define PMC_IMPL_IO_DPD7_STATUS_0_GEN2_I2C_SCL_OFF                      _MK_ENUM_CONST(0)
#define PMC_IMPL_IO_DPD7_STATUS_0_GEN2_I2C_SCL_ON                       _MK_ENUM_CONST(1)

#define PMC_IMPL_IO_DPD7_STATUS_0_GEN2_I2C_SDA_SHIFT                    _MK_SHIFT_CONST(9)
#define PMC_IMPL_IO_DPD7_STATUS_0_GEN2_I2C_SDA_FIELD                    _MK_FIELD_CONST(0x1, PMC_IMPL_IO_DPD7_STATUS_0_GEN2_I2C_SDA_SHIFT)
#define PMC_IMPL_IO_DPD7_STATUS_0_GEN2_I2C_SDA_RANGE                    9:9
#define PMC_IMPL_IO_DPD7_STATUS_0_GEN2_I2C_SDA_WOFFSET                  0x0
#define PMC_IMPL_IO_DPD7_STATUS_0_GEN2_I2C_SDA_DEFAULT                  _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD7_STATUS_0_GEN2_I2C_SDA_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DPD7_STATUS_0_GEN2_I2C_SDA_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD7_STATUS_0_GEN2_I2C_SDA_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD7_STATUS_0_GEN2_I2C_SDA_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD7_STATUS_0_GEN2_I2C_SDA_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DPD7_STATUS_0_GEN2_I2C_SDA_INIT_ENUM                        OFF
#define PMC_IMPL_IO_DPD7_STATUS_0_GEN2_I2C_SDA_OFF                      _MK_ENUM_CONST(0)
#define PMC_IMPL_IO_DPD7_STATUS_0_GEN2_I2C_SDA_ON                       _MK_ENUM_CONST(1)

#define PMC_IMPL_IO_DPD7_STATUS_0_SPI2_CS0_SHIFT                        _MK_SHIFT_CONST(10)
#define PMC_IMPL_IO_DPD7_STATUS_0_SPI2_CS0_FIELD                        _MK_FIELD_CONST(0x1, PMC_IMPL_IO_DPD7_STATUS_0_SPI2_CS0_SHIFT)
#define PMC_IMPL_IO_DPD7_STATUS_0_SPI2_CS0_RANGE                        10:10
#define PMC_IMPL_IO_DPD7_STATUS_0_SPI2_CS0_WOFFSET                      0x0
#define PMC_IMPL_IO_DPD7_STATUS_0_SPI2_CS0_DEFAULT                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD7_STATUS_0_SPI2_CS0_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DPD7_STATUS_0_SPI2_CS0_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD7_STATUS_0_SPI2_CS0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD7_STATUS_0_SPI2_CS0_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD7_STATUS_0_SPI2_CS0_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DPD7_STATUS_0_SPI2_CS0_INIT_ENUM                    OFF
#define PMC_IMPL_IO_DPD7_STATUS_0_SPI2_CS0_OFF                  _MK_ENUM_CONST(0)
#define PMC_IMPL_IO_DPD7_STATUS_0_SPI2_CS0_ON                   _MK_ENUM_CONST(1)

#define PMC_IMPL_IO_DPD7_STATUS_0_SPI2_MISO_SHIFT                       _MK_SHIFT_CONST(11)
#define PMC_IMPL_IO_DPD7_STATUS_0_SPI2_MISO_FIELD                       _MK_FIELD_CONST(0x1, PMC_IMPL_IO_DPD7_STATUS_0_SPI2_MISO_SHIFT)
#define PMC_IMPL_IO_DPD7_STATUS_0_SPI2_MISO_RANGE                       11:11
#define PMC_IMPL_IO_DPD7_STATUS_0_SPI2_MISO_WOFFSET                     0x0
#define PMC_IMPL_IO_DPD7_STATUS_0_SPI2_MISO_DEFAULT                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD7_STATUS_0_SPI2_MISO_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DPD7_STATUS_0_SPI2_MISO_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD7_STATUS_0_SPI2_MISO_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD7_STATUS_0_SPI2_MISO_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD7_STATUS_0_SPI2_MISO_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DPD7_STATUS_0_SPI2_MISO_INIT_ENUM                   OFF
#define PMC_IMPL_IO_DPD7_STATUS_0_SPI2_MISO_OFF                 _MK_ENUM_CONST(0)
#define PMC_IMPL_IO_DPD7_STATUS_0_SPI2_MISO_ON                  _MK_ENUM_CONST(1)

#define PMC_IMPL_IO_DPD7_STATUS_0_SPI2_MOSI_SHIFT                       _MK_SHIFT_CONST(12)
#define PMC_IMPL_IO_DPD7_STATUS_0_SPI2_MOSI_FIELD                       _MK_FIELD_CONST(0x1, PMC_IMPL_IO_DPD7_STATUS_0_SPI2_MOSI_SHIFT)
#define PMC_IMPL_IO_DPD7_STATUS_0_SPI2_MOSI_RANGE                       12:12
#define PMC_IMPL_IO_DPD7_STATUS_0_SPI2_MOSI_WOFFSET                     0x0
#define PMC_IMPL_IO_DPD7_STATUS_0_SPI2_MOSI_DEFAULT                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD7_STATUS_0_SPI2_MOSI_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DPD7_STATUS_0_SPI2_MOSI_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD7_STATUS_0_SPI2_MOSI_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD7_STATUS_0_SPI2_MOSI_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD7_STATUS_0_SPI2_MOSI_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DPD7_STATUS_0_SPI2_MOSI_INIT_ENUM                   OFF
#define PMC_IMPL_IO_DPD7_STATUS_0_SPI2_MOSI_OFF                 _MK_ENUM_CONST(0)
#define PMC_IMPL_IO_DPD7_STATUS_0_SPI2_MOSI_ON                  _MK_ENUM_CONST(1)

#define PMC_IMPL_IO_DPD7_STATUS_0_SPI2_SCK_SHIFT                        _MK_SHIFT_CONST(13)
#define PMC_IMPL_IO_DPD7_STATUS_0_SPI2_SCK_FIELD                        _MK_FIELD_CONST(0x1, PMC_IMPL_IO_DPD7_STATUS_0_SPI2_SCK_SHIFT)
#define PMC_IMPL_IO_DPD7_STATUS_0_SPI2_SCK_RANGE                        13:13
#define PMC_IMPL_IO_DPD7_STATUS_0_SPI2_SCK_WOFFSET                      0x0
#define PMC_IMPL_IO_DPD7_STATUS_0_SPI2_SCK_DEFAULT                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD7_STATUS_0_SPI2_SCK_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DPD7_STATUS_0_SPI2_SCK_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD7_STATUS_0_SPI2_SCK_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD7_STATUS_0_SPI2_SCK_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD7_STATUS_0_SPI2_SCK_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DPD7_STATUS_0_SPI2_SCK_INIT_ENUM                    OFF
#define PMC_IMPL_IO_DPD7_STATUS_0_SPI2_SCK_OFF                  _MK_ENUM_CONST(0)
#define PMC_IMPL_IO_DPD7_STATUS_0_SPI2_SCK_ON                   _MK_ENUM_CONST(1)

#define PMC_IMPL_IO_DPD7_STATUS_0_CAN0_WAKE_SHIFT                       _MK_SHIFT_CONST(22)
#define PMC_IMPL_IO_DPD7_STATUS_0_CAN0_WAKE_FIELD                       _MK_FIELD_CONST(0x1, PMC_IMPL_IO_DPD7_STATUS_0_CAN0_WAKE_SHIFT)
#define PMC_IMPL_IO_DPD7_STATUS_0_CAN0_WAKE_RANGE                       22:22
#define PMC_IMPL_IO_DPD7_STATUS_0_CAN0_WAKE_WOFFSET                     0x0
#define PMC_IMPL_IO_DPD7_STATUS_0_CAN0_WAKE_DEFAULT                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD7_STATUS_0_CAN0_WAKE_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DPD7_STATUS_0_CAN0_WAKE_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD7_STATUS_0_CAN0_WAKE_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD7_STATUS_0_CAN0_WAKE_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD7_STATUS_0_CAN0_WAKE_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DPD7_STATUS_0_CAN0_WAKE_INIT_ENUM                   OFF
#define PMC_IMPL_IO_DPD7_STATUS_0_CAN0_WAKE_OFF                 _MK_ENUM_CONST(0)
#define PMC_IMPL_IO_DPD7_STATUS_0_CAN0_WAKE_ON                  _MK_ENUM_CONST(1)

#define PMC_IMPL_IO_DPD7_STATUS_0_CAN0_ERR_SHIFT                        _MK_SHIFT_CONST(23)
#define PMC_IMPL_IO_DPD7_STATUS_0_CAN0_ERR_FIELD                        _MK_FIELD_CONST(0x1, PMC_IMPL_IO_DPD7_STATUS_0_CAN0_ERR_SHIFT)
#define PMC_IMPL_IO_DPD7_STATUS_0_CAN0_ERR_RANGE                        23:23
#define PMC_IMPL_IO_DPD7_STATUS_0_CAN0_ERR_WOFFSET                      0x0
#define PMC_IMPL_IO_DPD7_STATUS_0_CAN0_ERR_DEFAULT                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD7_STATUS_0_CAN0_ERR_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DPD7_STATUS_0_CAN0_ERR_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD7_STATUS_0_CAN0_ERR_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD7_STATUS_0_CAN0_ERR_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD7_STATUS_0_CAN0_ERR_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DPD7_STATUS_0_CAN0_ERR_INIT_ENUM                    OFF
#define PMC_IMPL_IO_DPD7_STATUS_0_CAN0_ERR_OFF                  _MK_ENUM_CONST(0)
#define PMC_IMPL_IO_DPD7_STATUS_0_CAN0_ERR_ON                   _MK_ENUM_CONST(1)

#define PMC_IMPL_IO_DPD7_STATUS_0_CAN1_STB_SHIFT                        _MK_SHIFT_CONST(24)
#define PMC_IMPL_IO_DPD7_STATUS_0_CAN1_STB_FIELD                        _MK_FIELD_CONST(0x1, PMC_IMPL_IO_DPD7_STATUS_0_CAN1_STB_SHIFT)
#define PMC_IMPL_IO_DPD7_STATUS_0_CAN1_STB_RANGE                        24:24
#define PMC_IMPL_IO_DPD7_STATUS_0_CAN1_STB_WOFFSET                      0x0
#define PMC_IMPL_IO_DPD7_STATUS_0_CAN1_STB_DEFAULT                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD7_STATUS_0_CAN1_STB_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DPD7_STATUS_0_CAN1_STB_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD7_STATUS_0_CAN1_STB_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD7_STATUS_0_CAN1_STB_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD7_STATUS_0_CAN1_STB_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DPD7_STATUS_0_CAN1_STB_INIT_ENUM                    OFF
#define PMC_IMPL_IO_DPD7_STATUS_0_CAN1_STB_OFF                  _MK_ENUM_CONST(0)
#define PMC_IMPL_IO_DPD7_STATUS_0_CAN1_STB_ON                   _MK_ENUM_CONST(1)

#define PMC_IMPL_IO_DPD7_STATUS_0_CAN1_EN_SHIFT                 _MK_SHIFT_CONST(25)
#define PMC_IMPL_IO_DPD7_STATUS_0_CAN1_EN_FIELD                 _MK_FIELD_CONST(0x1, PMC_IMPL_IO_DPD7_STATUS_0_CAN1_EN_SHIFT)
#define PMC_IMPL_IO_DPD7_STATUS_0_CAN1_EN_RANGE                 25:25
#define PMC_IMPL_IO_DPD7_STATUS_0_CAN1_EN_WOFFSET                       0x0
#define PMC_IMPL_IO_DPD7_STATUS_0_CAN1_EN_DEFAULT                       _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD7_STATUS_0_CAN1_EN_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DPD7_STATUS_0_CAN1_EN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD7_STATUS_0_CAN1_EN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD7_STATUS_0_CAN1_EN_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD7_STATUS_0_CAN1_EN_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DPD7_STATUS_0_CAN1_EN_INIT_ENUM                     OFF
#define PMC_IMPL_IO_DPD7_STATUS_0_CAN1_EN_OFF                   _MK_ENUM_CONST(0)
#define PMC_IMPL_IO_DPD7_STATUS_0_CAN1_EN_ON                    _MK_ENUM_CONST(1)

#define PMC_IMPL_IO_DPD7_STATUS_0_UART3_RX_SHIFT                        _MK_SHIFT_CONST(28)
#define PMC_IMPL_IO_DPD7_STATUS_0_UART3_RX_FIELD                        _MK_FIELD_CONST(0x1, PMC_IMPL_IO_DPD7_STATUS_0_UART3_RX_SHIFT)
#define PMC_IMPL_IO_DPD7_STATUS_0_UART3_RX_RANGE                        28:28
#define PMC_IMPL_IO_DPD7_STATUS_0_UART3_RX_WOFFSET                      0x0
#define PMC_IMPL_IO_DPD7_STATUS_0_UART3_RX_DEFAULT                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD7_STATUS_0_UART3_RX_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DPD7_STATUS_0_UART3_RX_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD7_STATUS_0_UART3_RX_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD7_STATUS_0_UART3_RX_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD7_STATUS_0_UART3_RX_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DPD7_STATUS_0_UART3_RX_INIT_ENUM                    OFF
#define PMC_IMPL_IO_DPD7_STATUS_0_UART3_RX_OFF                  _MK_ENUM_CONST(0)
#define PMC_IMPL_IO_DPD7_STATUS_0_UART3_RX_ON                   _MK_ENUM_CONST(1)

#define PMC_IMPL_IO_DPD7_STATUS_0_UART3_TX_SHIFT                        _MK_SHIFT_CONST(29)
#define PMC_IMPL_IO_DPD7_STATUS_0_UART3_TX_FIELD                        _MK_FIELD_CONST(0x1, PMC_IMPL_IO_DPD7_STATUS_0_UART3_TX_SHIFT)
#define PMC_IMPL_IO_DPD7_STATUS_0_UART3_TX_RANGE                        29:29
#define PMC_IMPL_IO_DPD7_STATUS_0_UART3_TX_WOFFSET                      0x0
#define PMC_IMPL_IO_DPD7_STATUS_0_UART3_TX_DEFAULT                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD7_STATUS_0_UART3_TX_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DPD7_STATUS_0_UART3_TX_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD7_STATUS_0_UART3_TX_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD7_STATUS_0_UART3_TX_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD7_STATUS_0_UART3_TX_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DPD7_STATUS_0_UART3_TX_INIT_ENUM                    OFF
#define PMC_IMPL_IO_DPD7_STATUS_0_UART3_TX_OFF                  _MK_ENUM_CONST(0)
#define PMC_IMPL_IO_DPD7_STATUS_0_UART3_TX_ON                   _MK_ENUM_CONST(1)


// Register PMC_IMPL_IO_DPD8_REQ_0
#define PMC_IMPL_IO_DPD8_REQ_0                  _MK_ADDR_CONST(0xac)
#define PMC_IMPL_IO_DPD8_REQ_0_SECURE                   0x0
#define PMC_IMPL_IO_DPD8_REQ_0_DUAL                     0x0
#define PMC_IMPL_IO_DPD8_REQ_0_SCR                      IODPD8_SCR_0
#define PMC_IMPL_IO_DPD8_REQ_0_WORD_COUNT                       0x1
#define PMC_IMPL_IO_DPD8_REQ_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD8_REQ_0_RESET_MASK                       _MK_MASK_CONST(0xc78700c2)
#define PMC_IMPL_IO_DPD8_REQ_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD8_REQ_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD8_REQ_0_READ_MASK                        _MK_MASK_CONST(0xc78700c2)
#define PMC_IMPL_IO_DPD8_REQ_0_WRITE_MASK                       _MK_MASK_CONST(0xc78700c2)
#define PMC_IMPL_IO_DPD8_REQ_0_SAFE_STATE_SHIFT                 _MK_SHIFT_CONST(1)
#define PMC_IMPL_IO_DPD8_REQ_0_SAFE_STATE_FIELD                 _MK_FIELD_CONST(0x1, PMC_IMPL_IO_DPD8_REQ_0_SAFE_STATE_SHIFT)
#define PMC_IMPL_IO_DPD8_REQ_0_SAFE_STATE_RANGE                 1:1
#define PMC_IMPL_IO_DPD8_REQ_0_SAFE_STATE_WOFFSET                       0x0
#define PMC_IMPL_IO_DPD8_REQ_0_SAFE_STATE_DEFAULT                       _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD8_REQ_0_SAFE_STATE_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DPD8_REQ_0_SAFE_STATE_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD8_REQ_0_SAFE_STATE_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD8_REQ_0_SAFE_STATE_PARITY_PROTECTION                     _MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DPD8_REQ_0_SAFE_STATE_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DPD8_REQ_0_SAFE_STATE_INIT_ENUM                     OFF
#define PMC_IMPL_IO_DPD8_REQ_0_SAFE_STATE_OFF                   _MK_ENUM_CONST(0)
#define PMC_IMPL_IO_DPD8_REQ_0_SAFE_STATE_ON                    _MK_ENUM_CONST(1)

#define PMC_IMPL_IO_DPD8_REQ_0_GEN8_I2C_SCL_SHIFT                       _MK_SHIFT_CONST(6)
#define PMC_IMPL_IO_DPD8_REQ_0_GEN8_I2C_SCL_FIELD                       _MK_FIELD_CONST(0x1, PMC_IMPL_IO_DPD8_REQ_0_GEN8_I2C_SCL_SHIFT)
#define PMC_IMPL_IO_DPD8_REQ_0_GEN8_I2C_SCL_RANGE                       6:6
#define PMC_IMPL_IO_DPD8_REQ_0_GEN8_I2C_SCL_WOFFSET                     0x0
#define PMC_IMPL_IO_DPD8_REQ_0_GEN8_I2C_SCL_DEFAULT                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD8_REQ_0_GEN8_I2C_SCL_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DPD8_REQ_0_GEN8_I2C_SCL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD8_REQ_0_GEN8_I2C_SCL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD8_REQ_0_GEN8_I2C_SCL_PARITY_PROTECTION                   _MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DPD8_REQ_0_GEN8_I2C_SCL_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DPD8_REQ_0_GEN8_I2C_SCL_INIT_ENUM                   OFF
#define PMC_IMPL_IO_DPD8_REQ_0_GEN8_I2C_SCL_OFF                 _MK_ENUM_CONST(0)
#define PMC_IMPL_IO_DPD8_REQ_0_GEN8_I2C_SCL_ON                  _MK_ENUM_CONST(1)

#define PMC_IMPL_IO_DPD8_REQ_0_GEN8_I2C_SDA_SHIFT                       _MK_SHIFT_CONST(7)
#define PMC_IMPL_IO_DPD8_REQ_0_GEN8_I2C_SDA_FIELD                       _MK_FIELD_CONST(0x1, PMC_IMPL_IO_DPD8_REQ_0_GEN8_I2C_SDA_SHIFT)
#define PMC_IMPL_IO_DPD8_REQ_0_GEN8_I2C_SDA_RANGE                       7:7
#define PMC_IMPL_IO_DPD8_REQ_0_GEN8_I2C_SDA_WOFFSET                     0x0
#define PMC_IMPL_IO_DPD8_REQ_0_GEN8_I2C_SDA_DEFAULT                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD8_REQ_0_GEN8_I2C_SDA_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DPD8_REQ_0_GEN8_I2C_SDA_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD8_REQ_0_GEN8_I2C_SDA_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD8_REQ_0_GEN8_I2C_SDA_PARITY_PROTECTION                   _MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DPD8_REQ_0_GEN8_I2C_SDA_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DPD8_REQ_0_GEN8_I2C_SDA_INIT_ENUM                   OFF
#define PMC_IMPL_IO_DPD8_REQ_0_GEN8_I2C_SDA_OFF                 _MK_ENUM_CONST(0)
#define PMC_IMPL_IO_DPD8_REQ_0_GEN8_I2C_SDA_ON                  _MK_ENUM_CONST(1)

#define PMC_IMPL_IO_DPD8_REQ_0_POWER_ON_SHIFT                   _MK_SHIFT_CONST(16)
#define PMC_IMPL_IO_DPD8_REQ_0_POWER_ON_FIELD                   _MK_FIELD_CONST(0x1, PMC_IMPL_IO_DPD8_REQ_0_POWER_ON_SHIFT)
#define PMC_IMPL_IO_DPD8_REQ_0_POWER_ON_RANGE                   16:16
#define PMC_IMPL_IO_DPD8_REQ_0_POWER_ON_WOFFSET                 0x0
#define PMC_IMPL_IO_DPD8_REQ_0_POWER_ON_DEFAULT                 _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD8_REQ_0_POWER_ON_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DPD8_REQ_0_POWER_ON_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD8_REQ_0_POWER_ON_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD8_REQ_0_POWER_ON_PARITY_PROTECTION                       _MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DPD8_REQ_0_POWER_ON_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DPD8_REQ_0_POWER_ON_INIT_ENUM                       OFF
#define PMC_IMPL_IO_DPD8_REQ_0_POWER_ON_OFF                     _MK_ENUM_CONST(0)
#define PMC_IMPL_IO_DPD8_REQ_0_POWER_ON_ON                      _MK_ENUM_CONST(1)

#define PMC_IMPL_IO_DPD8_REQ_0_PWR_I2C_SCL_SHIFT                        _MK_SHIFT_CONST(17)
#define PMC_IMPL_IO_DPD8_REQ_0_PWR_I2C_SCL_FIELD                        _MK_FIELD_CONST(0x1, PMC_IMPL_IO_DPD8_REQ_0_PWR_I2C_SCL_SHIFT)
#define PMC_IMPL_IO_DPD8_REQ_0_PWR_I2C_SCL_RANGE                        17:17
#define PMC_IMPL_IO_DPD8_REQ_0_PWR_I2C_SCL_WOFFSET                      0x0
#define PMC_IMPL_IO_DPD8_REQ_0_PWR_I2C_SCL_DEFAULT                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD8_REQ_0_PWR_I2C_SCL_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DPD8_REQ_0_PWR_I2C_SCL_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD8_REQ_0_PWR_I2C_SCL_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD8_REQ_0_PWR_I2C_SCL_PARITY_PROTECTION                    _MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DPD8_REQ_0_PWR_I2C_SCL_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DPD8_REQ_0_PWR_I2C_SCL_INIT_ENUM                    OFF
#define PMC_IMPL_IO_DPD8_REQ_0_PWR_I2C_SCL_OFF                  _MK_ENUM_CONST(0)
#define PMC_IMPL_IO_DPD8_REQ_0_PWR_I2C_SCL_ON                   _MK_ENUM_CONST(1)

#define PMC_IMPL_IO_DPD8_REQ_0_PWR_I2C_SDA_SHIFT                        _MK_SHIFT_CONST(18)
#define PMC_IMPL_IO_DPD8_REQ_0_PWR_I2C_SDA_FIELD                        _MK_FIELD_CONST(0x1, PMC_IMPL_IO_DPD8_REQ_0_PWR_I2C_SDA_SHIFT)
#define PMC_IMPL_IO_DPD8_REQ_0_PWR_I2C_SDA_RANGE                        18:18
#define PMC_IMPL_IO_DPD8_REQ_0_PWR_I2C_SDA_WOFFSET                      0x0
#define PMC_IMPL_IO_DPD8_REQ_0_PWR_I2C_SDA_DEFAULT                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD8_REQ_0_PWR_I2C_SDA_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DPD8_REQ_0_PWR_I2C_SDA_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD8_REQ_0_PWR_I2C_SDA_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD8_REQ_0_PWR_I2C_SDA_PARITY_PROTECTION                    _MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DPD8_REQ_0_PWR_I2C_SDA_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DPD8_REQ_0_PWR_I2C_SDA_INIT_ENUM                    OFF
#define PMC_IMPL_IO_DPD8_REQ_0_PWR_I2C_SDA_OFF                  _MK_ENUM_CONST(0)
#define PMC_IMPL_IO_DPD8_REQ_0_PWR_I2C_SDA_ON                   _MK_ENUM_CONST(1)

#define PMC_IMPL_IO_DPD8_REQ_0_TOUCH_CLK_SHIFT                  _MK_SHIFT_CONST(23)
#define PMC_IMPL_IO_DPD8_REQ_0_TOUCH_CLK_FIELD                  _MK_FIELD_CONST(0x1, PMC_IMPL_IO_DPD8_REQ_0_TOUCH_CLK_SHIFT)
#define PMC_IMPL_IO_DPD8_REQ_0_TOUCH_CLK_RANGE                  23:23
#define PMC_IMPL_IO_DPD8_REQ_0_TOUCH_CLK_WOFFSET                        0x0
#define PMC_IMPL_IO_DPD8_REQ_0_TOUCH_CLK_DEFAULT                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD8_REQ_0_TOUCH_CLK_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DPD8_REQ_0_TOUCH_CLK_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD8_REQ_0_TOUCH_CLK_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD8_REQ_0_TOUCH_CLK_PARITY_PROTECTION                      _MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DPD8_REQ_0_TOUCH_CLK_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DPD8_REQ_0_TOUCH_CLK_INIT_ENUM                      OFF
#define PMC_IMPL_IO_DPD8_REQ_0_TOUCH_CLK_OFF                    _MK_ENUM_CONST(0)
#define PMC_IMPL_IO_DPD8_REQ_0_TOUCH_CLK_ON                     _MK_ENUM_CONST(1)

#define PMC_IMPL_IO_DPD8_REQ_0_VCOMP_ALERT_SHIFT                        _MK_SHIFT_CONST(24)
#define PMC_IMPL_IO_DPD8_REQ_0_VCOMP_ALERT_FIELD                        _MK_FIELD_CONST(0x1, PMC_IMPL_IO_DPD8_REQ_0_VCOMP_ALERT_SHIFT)
#define PMC_IMPL_IO_DPD8_REQ_0_VCOMP_ALERT_RANGE                        24:24
#define PMC_IMPL_IO_DPD8_REQ_0_VCOMP_ALERT_WOFFSET                      0x0
#define PMC_IMPL_IO_DPD8_REQ_0_VCOMP_ALERT_DEFAULT                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD8_REQ_0_VCOMP_ALERT_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DPD8_REQ_0_VCOMP_ALERT_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD8_REQ_0_VCOMP_ALERT_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD8_REQ_0_VCOMP_ALERT_PARITY_PROTECTION                    _MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DPD8_REQ_0_VCOMP_ALERT_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DPD8_REQ_0_VCOMP_ALERT_INIT_ENUM                    OFF
#define PMC_IMPL_IO_DPD8_REQ_0_VCOMP_ALERT_OFF                  _MK_ENUM_CONST(0)
#define PMC_IMPL_IO_DPD8_REQ_0_VCOMP_ALERT_ON                   _MK_ENUM_CONST(1)

#define PMC_IMPL_IO_DPD8_REQ_0_CAN1_WAKE_SHIFT                  _MK_SHIFT_CONST(25)
#define PMC_IMPL_IO_DPD8_REQ_0_CAN1_WAKE_FIELD                  _MK_FIELD_CONST(0x1, PMC_IMPL_IO_DPD8_REQ_0_CAN1_WAKE_SHIFT)
#define PMC_IMPL_IO_DPD8_REQ_0_CAN1_WAKE_RANGE                  25:25
#define PMC_IMPL_IO_DPD8_REQ_0_CAN1_WAKE_WOFFSET                        0x0
#define PMC_IMPL_IO_DPD8_REQ_0_CAN1_WAKE_DEFAULT                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD8_REQ_0_CAN1_WAKE_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DPD8_REQ_0_CAN1_WAKE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD8_REQ_0_CAN1_WAKE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD8_REQ_0_CAN1_WAKE_PARITY_PROTECTION                      _MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DPD8_REQ_0_CAN1_WAKE_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DPD8_REQ_0_CAN1_WAKE_INIT_ENUM                      OFF
#define PMC_IMPL_IO_DPD8_REQ_0_CAN1_WAKE_OFF                    _MK_ENUM_CONST(0)
#define PMC_IMPL_IO_DPD8_REQ_0_CAN1_WAKE_ON                     _MK_ENUM_CONST(1)

#define PMC_IMPL_IO_DPD8_REQ_0_CAN1_ERR_SHIFT                   _MK_SHIFT_CONST(26)
#define PMC_IMPL_IO_DPD8_REQ_0_CAN1_ERR_FIELD                   _MK_FIELD_CONST(0x1, PMC_IMPL_IO_DPD8_REQ_0_CAN1_ERR_SHIFT)
#define PMC_IMPL_IO_DPD8_REQ_0_CAN1_ERR_RANGE                   26:26
#define PMC_IMPL_IO_DPD8_REQ_0_CAN1_ERR_WOFFSET                 0x0
#define PMC_IMPL_IO_DPD8_REQ_0_CAN1_ERR_DEFAULT                 _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD8_REQ_0_CAN1_ERR_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DPD8_REQ_0_CAN1_ERR_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD8_REQ_0_CAN1_ERR_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD8_REQ_0_CAN1_ERR_PARITY_PROTECTION                       _MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DPD8_REQ_0_CAN1_ERR_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DPD8_REQ_0_CAN1_ERR_INIT_ENUM                       OFF
#define PMC_IMPL_IO_DPD8_REQ_0_CAN1_ERR_OFF                     _MK_ENUM_CONST(0)
#define PMC_IMPL_IO_DPD8_REQ_0_CAN1_ERR_ON                      _MK_ENUM_CONST(1)

#define PMC_IMPL_IO_DPD8_REQ_0_CODE_SHIFT                       _MK_SHIFT_CONST(30)
#define PMC_IMPL_IO_DPD8_REQ_0_CODE_FIELD                       _MK_FIELD_CONST(0x3, PMC_IMPL_IO_DPD8_REQ_0_CODE_SHIFT)
#define PMC_IMPL_IO_DPD8_REQ_0_CODE_RANGE                       31:30
#define PMC_IMPL_IO_DPD8_REQ_0_CODE_WOFFSET                     0x0
#define PMC_IMPL_IO_DPD8_REQ_0_CODE_DEFAULT                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD8_REQ_0_CODE_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
#define PMC_IMPL_IO_DPD8_REQ_0_CODE_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD8_REQ_0_CODE_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD8_REQ_0_CODE_PARITY_PROTECTION                   _MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DPD8_REQ_0_CODE_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DPD8_REQ_0_CODE_INIT_ENUM                   IDLE
#define PMC_IMPL_IO_DPD8_REQ_0_CODE_IDLE                        _MK_ENUM_CONST(0)
#define PMC_IMPL_IO_DPD8_REQ_0_CODE_DPD_OFF                     _MK_ENUM_CONST(1)
#define PMC_IMPL_IO_DPD8_REQ_0_CODE_DPD_ON                      _MK_ENUM_CONST(2)


// Register PMC_IMPL_IO_DPD8_STATUS_0
#define PMC_IMPL_IO_DPD8_STATUS_0                       _MK_ADDR_CONST(0xb0)
#define PMC_IMPL_IO_DPD8_STATUS_0_SECURE                        0x0
#define PMC_IMPL_IO_DPD8_STATUS_0_DUAL                  0x0
#define PMC_IMPL_IO_DPD8_STATUS_0_SCR                   IODPD8_SCR_0
#define PMC_IMPL_IO_DPD8_STATUS_0_WORD_COUNT                    0x1
#define PMC_IMPL_IO_DPD8_STATUS_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD8_STATUS_0_RESET_MASK                    _MK_MASK_CONST(0x78700c2)
#define PMC_IMPL_IO_DPD8_STATUS_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD8_STATUS_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD8_STATUS_0_READ_MASK                     _MK_MASK_CONST(0x78700c2)
#define PMC_IMPL_IO_DPD8_STATUS_0_WRITE_MASK                    _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD8_STATUS_0_SAFE_STATE_SHIFT                      _MK_SHIFT_CONST(1)
#define PMC_IMPL_IO_DPD8_STATUS_0_SAFE_STATE_FIELD                      _MK_FIELD_CONST(0x1, PMC_IMPL_IO_DPD8_STATUS_0_SAFE_STATE_SHIFT)
#define PMC_IMPL_IO_DPD8_STATUS_0_SAFE_STATE_RANGE                      1:1
#define PMC_IMPL_IO_DPD8_STATUS_0_SAFE_STATE_WOFFSET                    0x0
#define PMC_IMPL_IO_DPD8_STATUS_0_SAFE_STATE_DEFAULT                    _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD8_STATUS_0_SAFE_STATE_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DPD8_STATUS_0_SAFE_STATE_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD8_STATUS_0_SAFE_STATE_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD8_STATUS_0_SAFE_STATE_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD8_STATUS_0_SAFE_STATE_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DPD8_STATUS_0_SAFE_STATE_INIT_ENUM                  OFF
#define PMC_IMPL_IO_DPD8_STATUS_0_SAFE_STATE_OFF                        _MK_ENUM_CONST(0)
#define PMC_IMPL_IO_DPD8_STATUS_0_SAFE_STATE_ON                 _MK_ENUM_CONST(1)

#define PMC_IMPL_IO_DPD8_STATUS_0_GEN8_I2C_SCL_SHIFT                    _MK_SHIFT_CONST(6)
#define PMC_IMPL_IO_DPD8_STATUS_0_GEN8_I2C_SCL_FIELD                    _MK_FIELD_CONST(0x1, PMC_IMPL_IO_DPD8_STATUS_0_GEN8_I2C_SCL_SHIFT)
#define PMC_IMPL_IO_DPD8_STATUS_0_GEN8_I2C_SCL_RANGE                    6:6
#define PMC_IMPL_IO_DPD8_STATUS_0_GEN8_I2C_SCL_WOFFSET                  0x0
#define PMC_IMPL_IO_DPD8_STATUS_0_GEN8_I2C_SCL_DEFAULT                  _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD8_STATUS_0_GEN8_I2C_SCL_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DPD8_STATUS_0_GEN8_I2C_SCL_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD8_STATUS_0_GEN8_I2C_SCL_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD8_STATUS_0_GEN8_I2C_SCL_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD8_STATUS_0_GEN8_I2C_SCL_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DPD8_STATUS_0_GEN8_I2C_SCL_INIT_ENUM                        OFF
#define PMC_IMPL_IO_DPD8_STATUS_0_GEN8_I2C_SCL_OFF                      _MK_ENUM_CONST(0)
#define PMC_IMPL_IO_DPD8_STATUS_0_GEN8_I2C_SCL_ON                       _MK_ENUM_CONST(1)

#define PMC_IMPL_IO_DPD8_STATUS_0_GEN8_I2C_SDA_SHIFT                    _MK_SHIFT_CONST(7)
#define PMC_IMPL_IO_DPD8_STATUS_0_GEN8_I2C_SDA_FIELD                    _MK_FIELD_CONST(0x1, PMC_IMPL_IO_DPD8_STATUS_0_GEN8_I2C_SDA_SHIFT)
#define PMC_IMPL_IO_DPD8_STATUS_0_GEN8_I2C_SDA_RANGE                    7:7
#define PMC_IMPL_IO_DPD8_STATUS_0_GEN8_I2C_SDA_WOFFSET                  0x0
#define PMC_IMPL_IO_DPD8_STATUS_0_GEN8_I2C_SDA_DEFAULT                  _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD8_STATUS_0_GEN8_I2C_SDA_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DPD8_STATUS_0_GEN8_I2C_SDA_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD8_STATUS_0_GEN8_I2C_SDA_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD8_STATUS_0_GEN8_I2C_SDA_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD8_STATUS_0_GEN8_I2C_SDA_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DPD8_STATUS_0_GEN8_I2C_SDA_INIT_ENUM                        OFF
#define PMC_IMPL_IO_DPD8_STATUS_0_GEN8_I2C_SDA_OFF                      _MK_ENUM_CONST(0)
#define PMC_IMPL_IO_DPD8_STATUS_0_GEN8_I2C_SDA_ON                       _MK_ENUM_CONST(1)

#define PMC_IMPL_IO_DPD8_STATUS_0_POWER_ON_SHIFT                        _MK_SHIFT_CONST(16)
#define PMC_IMPL_IO_DPD8_STATUS_0_POWER_ON_FIELD                        _MK_FIELD_CONST(0x1, PMC_IMPL_IO_DPD8_STATUS_0_POWER_ON_SHIFT)
#define PMC_IMPL_IO_DPD8_STATUS_0_POWER_ON_RANGE                        16:16
#define PMC_IMPL_IO_DPD8_STATUS_0_POWER_ON_WOFFSET                      0x0
#define PMC_IMPL_IO_DPD8_STATUS_0_POWER_ON_DEFAULT                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD8_STATUS_0_POWER_ON_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DPD8_STATUS_0_POWER_ON_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD8_STATUS_0_POWER_ON_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD8_STATUS_0_POWER_ON_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD8_STATUS_0_POWER_ON_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DPD8_STATUS_0_POWER_ON_INIT_ENUM                    OFF
#define PMC_IMPL_IO_DPD8_STATUS_0_POWER_ON_OFF                  _MK_ENUM_CONST(0)
#define PMC_IMPL_IO_DPD8_STATUS_0_POWER_ON_ON                   _MK_ENUM_CONST(1)

#define PMC_IMPL_IO_DPD8_STATUS_0_PWR_I2C_SCL_SHIFT                     _MK_SHIFT_CONST(17)
#define PMC_IMPL_IO_DPD8_STATUS_0_PWR_I2C_SCL_FIELD                     _MK_FIELD_CONST(0x1, PMC_IMPL_IO_DPD8_STATUS_0_PWR_I2C_SCL_SHIFT)
#define PMC_IMPL_IO_DPD8_STATUS_0_PWR_I2C_SCL_RANGE                     17:17
#define PMC_IMPL_IO_DPD8_STATUS_0_PWR_I2C_SCL_WOFFSET                   0x0
#define PMC_IMPL_IO_DPD8_STATUS_0_PWR_I2C_SCL_DEFAULT                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD8_STATUS_0_PWR_I2C_SCL_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DPD8_STATUS_0_PWR_I2C_SCL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD8_STATUS_0_PWR_I2C_SCL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD8_STATUS_0_PWR_I2C_SCL_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD8_STATUS_0_PWR_I2C_SCL_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DPD8_STATUS_0_PWR_I2C_SCL_INIT_ENUM                 OFF
#define PMC_IMPL_IO_DPD8_STATUS_0_PWR_I2C_SCL_OFF                       _MK_ENUM_CONST(0)
#define PMC_IMPL_IO_DPD8_STATUS_0_PWR_I2C_SCL_ON                        _MK_ENUM_CONST(1)

#define PMC_IMPL_IO_DPD8_STATUS_0_PWR_I2C_SDA_SHIFT                     _MK_SHIFT_CONST(18)
#define PMC_IMPL_IO_DPD8_STATUS_0_PWR_I2C_SDA_FIELD                     _MK_FIELD_CONST(0x1, PMC_IMPL_IO_DPD8_STATUS_0_PWR_I2C_SDA_SHIFT)
#define PMC_IMPL_IO_DPD8_STATUS_0_PWR_I2C_SDA_RANGE                     18:18
#define PMC_IMPL_IO_DPD8_STATUS_0_PWR_I2C_SDA_WOFFSET                   0x0
#define PMC_IMPL_IO_DPD8_STATUS_0_PWR_I2C_SDA_DEFAULT                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD8_STATUS_0_PWR_I2C_SDA_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DPD8_STATUS_0_PWR_I2C_SDA_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD8_STATUS_0_PWR_I2C_SDA_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD8_STATUS_0_PWR_I2C_SDA_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD8_STATUS_0_PWR_I2C_SDA_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DPD8_STATUS_0_PWR_I2C_SDA_INIT_ENUM                 OFF
#define PMC_IMPL_IO_DPD8_STATUS_0_PWR_I2C_SDA_OFF                       _MK_ENUM_CONST(0)
#define PMC_IMPL_IO_DPD8_STATUS_0_PWR_I2C_SDA_ON                        _MK_ENUM_CONST(1)

#define PMC_IMPL_IO_DPD8_STATUS_0_TOUCH_CLK_SHIFT                       _MK_SHIFT_CONST(23)
#define PMC_IMPL_IO_DPD8_STATUS_0_TOUCH_CLK_FIELD                       _MK_FIELD_CONST(0x1, PMC_IMPL_IO_DPD8_STATUS_0_TOUCH_CLK_SHIFT)
#define PMC_IMPL_IO_DPD8_STATUS_0_TOUCH_CLK_RANGE                       23:23
#define PMC_IMPL_IO_DPD8_STATUS_0_TOUCH_CLK_WOFFSET                     0x0
#define PMC_IMPL_IO_DPD8_STATUS_0_TOUCH_CLK_DEFAULT                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD8_STATUS_0_TOUCH_CLK_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DPD8_STATUS_0_TOUCH_CLK_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD8_STATUS_0_TOUCH_CLK_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD8_STATUS_0_TOUCH_CLK_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD8_STATUS_0_TOUCH_CLK_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DPD8_STATUS_0_TOUCH_CLK_INIT_ENUM                   OFF
#define PMC_IMPL_IO_DPD8_STATUS_0_TOUCH_CLK_OFF                 _MK_ENUM_CONST(0)
#define PMC_IMPL_IO_DPD8_STATUS_0_TOUCH_CLK_ON                  _MK_ENUM_CONST(1)

#define PMC_IMPL_IO_DPD8_STATUS_0_VCOMP_ALERT_SHIFT                     _MK_SHIFT_CONST(24)
#define PMC_IMPL_IO_DPD8_STATUS_0_VCOMP_ALERT_FIELD                     _MK_FIELD_CONST(0x1, PMC_IMPL_IO_DPD8_STATUS_0_VCOMP_ALERT_SHIFT)
#define PMC_IMPL_IO_DPD8_STATUS_0_VCOMP_ALERT_RANGE                     24:24
#define PMC_IMPL_IO_DPD8_STATUS_0_VCOMP_ALERT_WOFFSET                   0x0
#define PMC_IMPL_IO_DPD8_STATUS_0_VCOMP_ALERT_DEFAULT                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD8_STATUS_0_VCOMP_ALERT_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DPD8_STATUS_0_VCOMP_ALERT_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD8_STATUS_0_VCOMP_ALERT_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD8_STATUS_0_VCOMP_ALERT_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD8_STATUS_0_VCOMP_ALERT_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DPD8_STATUS_0_VCOMP_ALERT_INIT_ENUM                 OFF
#define PMC_IMPL_IO_DPD8_STATUS_0_VCOMP_ALERT_OFF                       _MK_ENUM_CONST(0)
#define PMC_IMPL_IO_DPD8_STATUS_0_VCOMP_ALERT_ON                        _MK_ENUM_CONST(1)

#define PMC_IMPL_IO_DPD8_STATUS_0_CAN1_WAKE_SHIFT                       _MK_SHIFT_CONST(25)
#define PMC_IMPL_IO_DPD8_STATUS_0_CAN1_WAKE_FIELD                       _MK_FIELD_CONST(0x1, PMC_IMPL_IO_DPD8_STATUS_0_CAN1_WAKE_SHIFT)
#define PMC_IMPL_IO_DPD8_STATUS_0_CAN1_WAKE_RANGE                       25:25
#define PMC_IMPL_IO_DPD8_STATUS_0_CAN1_WAKE_WOFFSET                     0x0
#define PMC_IMPL_IO_DPD8_STATUS_0_CAN1_WAKE_DEFAULT                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD8_STATUS_0_CAN1_WAKE_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DPD8_STATUS_0_CAN1_WAKE_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD8_STATUS_0_CAN1_WAKE_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD8_STATUS_0_CAN1_WAKE_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD8_STATUS_0_CAN1_WAKE_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DPD8_STATUS_0_CAN1_WAKE_INIT_ENUM                   OFF
#define PMC_IMPL_IO_DPD8_STATUS_0_CAN1_WAKE_OFF                 _MK_ENUM_CONST(0)
#define PMC_IMPL_IO_DPD8_STATUS_0_CAN1_WAKE_ON                  _MK_ENUM_CONST(1)

#define PMC_IMPL_IO_DPD8_STATUS_0_CAN1_ERR_SHIFT                        _MK_SHIFT_CONST(26)
#define PMC_IMPL_IO_DPD8_STATUS_0_CAN1_ERR_FIELD                        _MK_FIELD_CONST(0x1, PMC_IMPL_IO_DPD8_STATUS_0_CAN1_ERR_SHIFT)
#define PMC_IMPL_IO_DPD8_STATUS_0_CAN1_ERR_RANGE                        26:26
#define PMC_IMPL_IO_DPD8_STATUS_0_CAN1_ERR_WOFFSET                      0x0
#define PMC_IMPL_IO_DPD8_STATUS_0_CAN1_ERR_DEFAULT                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD8_STATUS_0_CAN1_ERR_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DPD8_STATUS_0_CAN1_ERR_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD8_STATUS_0_CAN1_ERR_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD8_STATUS_0_CAN1_ERR_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD8_STATUS_0_CAN1_ERR_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DPD8_STATUS_0_CAN1_ERR_INIT_ENUM                    OFF
#define PMC_IMPL_IO_DPD8_STATUS_0_CAN1_ERR_OFF                  _MK_ENUM_CONST(0)
#define PMC_IMPL_IO_DPD8_STATUS_0_CAN1_ERR_ON                   _MK_ENUM_CONST(1)


// Register PMC_IMPL_IO_DPD7_OFF_MASK_0
#define PMC_IMPL_IO_DPD7_OFF_MASK_0                     _MK_ADDR_CONST(0xb4)
#define PMC_IMPL_IO_DPD7_OFF_MASK_0_SECURE                      0x0
#define PMC_IMPL_IO_DPD7_OFF_MASK_0_DUAL                        0x0
#define PMC_IMPL_IO_DPD7_OFF_MASK_0_SCR                         IODPD7_SCR_0
#define PMC_IMPL_IO_DPD7_OFF_MASK_0_WORD_COUNT                  0x1
#define PMC_IMPL_IO_DPD7_OFF_MASK_0_RESET_VAL                   _MK_MASK_CONST(0x33c03fff)
#define PMC_IMPL_IO_DPD7_OFF_MASK_0_RESET_MASK                  _MK_MASK_CONST(0x33c03fff)
#define PMC_IMPL_IO_DPD7_OFF_MASK_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD7_OFF_MASK_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD7_OFF_MASK_0_READ_MASK                   _MK_MASK_CONST(0x33c03fff)
#define PMC_IMPL_IO_DPD7_OFF_MASK_0_WRITE_MASK                  _MK_MASK_CONST(0x33c03fff)
#define PMC_IMPL_IO_DPD7_OFF_MASK_0_BATT_OC_SHIFT                       _MK_SHIFT_CONST(0)
#define PMC_IMPL_IO_DPD7_OFF_MASK_0_BATT_OC_FIELD                       _MK_FIELD_CONST(0x1, PMC_IMPL_IO_DPD7_OFF_MASK_0_BATT_OC_SHIFT)
#define PMC_IMPL_IO_DPD7_OFF_MASK_0_BATT_OC_RANGE                       0:0
#define PMC_IMPL_IO_DPD7_OFF_MASK_0_BATT_OC_WOFFSET                     0x0
#define PMC_IMPL_IO_DPD7_OFF_MASK_0_BATT_OC_DEFAULT                     _MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DPD7_OFF_MASK_0_BATT_OC_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DPD7_OFF_MASK_0_BATT_OC_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD7_OFF_MASK_0_BATT_OC_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD7_OFF_MASK_0_BATT_OC_PARITY_PROTECTION                   _MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DPD7_OFF_MASK_0_BATT_OC_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DPD7_OFF_MASK_0_BATT_OC_INIT_ENUM                   ON
#define PMC_IMPL_IO_DPD7_OFF_MASK_0_BATT_OC_OFF                 _MK_ENUM_CONST(0)
#define PMC_IMPL_IO_DPD7_OFF_MASK_0_BATT_OC_ON                  _MK_ENUM_CONST(1)

#define PMC_IMPL_IO_DPD7_OFF_MASK_0_AO_RETENTION_SHIFT                  _MK_SHIFT_CONST(1)
#define PMC_IMPL_IO_DPD7_OFF_MASK_0_AO_RETENTION_FIELD                  _MK_FIELD_CONST(0x1, PMC_IMPL_IO_DPD7_OFF_MASK_0_AO_RETENTION_SHIFT)
#define PMC_IMPL_IO_DPD7_OFF_MASK_0_AO_RETENTION_RANGE                  1:1
#define PMC_IMPL_IO_DPD7_OFF_MASK_0_AO_RETENTION_WOFFSET                        0x0
#define PMC_IMPL_IO_DPD7_OFF_MASK_0_AO_RETENTION_DEFAULT                        _MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DPD7_OFF_MASK_0_AO_RETENTION_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DPD7_OFF_MASK_0_AO_RETENTION_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD7_OFF_MASK_0_AO_RETENTION_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD7_OFF_MASK_0_AO_RETENTION_PARITY_PROTECTION                      _MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DPD7_OFF_MASK_0_AO_RETENTION_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DPD7_OFF_MASK_0_AO_RETENTION_INIT_ENUM                      ON
#define PMC_IMPL_IO_DPD7_OFF_MASK_0_AO_RETENTION_OFF                    _MK_ENUM_CONST(0)
#define PMC_IMPL_IO_DPD7_OFF_MASK_0_AO_RETENTION_ON                     _MK_ENUM_CONST(1)

#define PMC_IMPL_IO_DPD7_OFF_MASK_0_CAN0_DIN_SHIFT                      _MK_SHIFT_CONST(2)
#define PMC_IMPL_IO_DPD7_OFF_MASK_0_CAN0_DIN_FIELD                      _MK_FIELD_CONST(0x1, PMC_IMPL_IO_DPD7_OFF_MASK_0_CAN0_DIN_SHIFT)
#define PMC_IMPL_IO_DPD7_OFF_MASK_0_CAN0_DIN_RANGE                      2:2
#define PMC_IMPL_IO_DPD7_OFF_MASK_0_CAN0_DIN_WOFFSET                    0x0
#define PMC_IMPL_IO_DPD7_OFF_MASK_0_CAN0_DIN_DEFAULT                    _MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DPD7_OFF_MASK_0_CAN0_DIN_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DPD7_OFF_MASK_0_CAN0_DIN_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD7_OFF_MASK_0_CAN0_DIN_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD7_OFF_MASK_0_CAN0_DIN_PARITY_PROTECTION                  _MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DPD7_OFF_MASK_0_CAN0_DIN_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DPD7_OFF_MASK_0_CAN0_DIN_INIT_ENUM                  ON
#define PMC_IMPL_IO_DPD7_OFF_MASK_0_CAN0_DIN_OFF                        _MK_ENUM_CONST(0)
#define PMC_IMPL_IO_DPD7_OFF_MASK_0_CAN0_DIN_ON                 _MK_ENUM_CONST(1)

#define PMC_IMPL_IO_DPD7_OFF_MASK_0_CAN0_DOUT_SHIFT                     _MK_SHIFT_CONST(3)
#define PMC_IMPL_IO_DPD7_OFF_MASK_0_CAN0_DOUT_FIELD                     _MK_FIELD_CONST(0x1, PMC_IMPL_IO_DPD7_OFF_MASK_0_CAN0_DOUT_SHIFT)
#define PMC_IMPL_IO_DPD7_OFF_MASK_0_CAN0_DOUT_RANGE                     3:3
#define PMC_IMPL_IO_DPD7_OFF_MASK_0_CAN0_DOUT_WOFFSET                   0x0
#define PMC_IMPL_IO_DPD7_OFF_MASK_0_CAN0_DOUT_DEFAULT                   _MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DPD7_OFF_MASK_0_CAN0_DOUT_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DPD7_OFF_MASK_0_CAN0_DOUT_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD7_OFF_MASK_0_CAN0_DOUT_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD7_OFF_MASK_0_CAN0_DOUT_PARITY_PROTECTION                 _MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DPD7_OFF_MASK_0_CAN0_DOUT_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DPD7_OFF_MASK_0_CAN0_DOUT_INIT_ENUM                 ON
#define PMC_IMPL_IO_DPD7_OFF_MASK_0_CAN0_DOUT_OFF                       _MK_ENUM_CONST(0)
#define PMC_IMPL_IO_DPD7_OFF_MASK_0_CAN0_DOUT_ON                        _MK_ENUM_CONST(1)

#define PMC_IMPL_IO_DPD7_OFF_MASK_0_CAN1_DIN_SHIFT                      _MK_SHIFT_CONST(4)
#define PMC_IMPL_IO_DPD7_OFF_MASK_0_CAN1_DIN_FIELD                      _MK_FIELD_CONST(0x1, PMC_IMPL_IO_DPD7_OFF_MASK_0_CAN1_DIN_SHIFT)
#define PMC_IMPL_IO_DPD7_OFF_MASK_0_CAN1_DIN_RANGE                      4:4
#define PMC_IMPL_IO_DPD7_OFF_MASK_0_CAN1_DIN_WOFFSET                    0x0
#define PMC_IMPL_IO_DPD7_OFF_MASK_0_CAN1_DIN_DEFAULT                    _MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DPD7_OFF_MASK_0_CAN1_DIN_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DPD7_OFF_MASK_0_CAN1_DIN_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD7_OFF_MASK_0_CAN1_DIN_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD7_OFF_MASK_0_CAN1_DIN_PARITY_PROTECTION                  _MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DPD7_OFF_MASK_0_CAN1_DIN_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DPD7_OFF_MASK_0_CAN1_DIN_INIT_ENUM                  ON
#define PMC_IMPL_IO_DPD7_OFF_MASK_0_CAN1_DIN_OFF                        _MK_ENUM_CONST(0)
#define PMC_IMPL_IO_DPD7_OFF_MASK_0_CAN1_DIN_ON                 _MK_ENUM_CONST(1)

#define PMC_IMPL_IO_DPD7_OFF_MASK_0_CAN1_DOUT_SHIFT                     _MK_SHIFT_CONST(5)
#define PMC_IMPL_IO_DPD7_OFF_MASK_0_CAN1_DOUT_FIELD                     _MK_FIELD_CONST(0x1, PMC_IMPL_IO_DPD7_OFF_MASK_0_CAN1_DOUT_SHIFT)
#define PMC_IMPL_IO_DPD7_OFF_MASK_0_CAN1_DOUT_RANGE                     5:5
#define PMC_IMPL_IO_DPD7_OFF_MASK_0_CAN1_DOUT_WOFFSET                   0x0
#define PMC_IMPL_IO_DPD7_OFF_MASK_0_CAN1_DOUT_DEFAULT                   _MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DPD7_OFF_MASK_0_CAN1_DOUT_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DPD7_OFF_MASK_0_CAN1_DOUT_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD7_OFF_MASK_0_CAN1_DOUT_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD7_OFF_MASK_0_CAN1_DOUT_PARITY_PROTECTION                 _MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DPD7_OFF_MASK_0_CAN1_DOUT_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DPD7_OFF_MASK_0_CAN1_DOUT_INIT_ENUM                 ON
#define PMC_IMPL_IO_DPD7_OFF_MASK_0_CAN1_DOUT_OFF                       _MK_ENUM_CONST(0)
#define PMC_IMPL_IO_DPD7_OFF_MASK_0_CAN1_DOUT_ON                        _MK_ENUM_CONST(1)

#define PMC_IMPL_IO_DPD7_OFF_MASK_0_CAN0_STB_SHIFT                      _MK_SHIFT_CONST(6)
#define PMC_IMPL_IO_DPD7_OFF_MASK_0_CAN0_STB_FIELD                      _MK_FIELD_CONST(0x1, PMC_IMPL_IO_DPD7_OFF_MASK_0_CAN0_STB_SHIFT)
#define PMC_IMPL_IO_DPD7_OFF_MASK_0_CAN0_STB_RANGE                      6:6
#define PMC_IMPL_IO_DPD7_OFF_MASK_0_CAN0_STB_WOFFSET                    0x0
#define PMC_IMPL_IO_DPD7_OFF_MASK_0_CAN0_STB_DEFAULT                    _MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DPD7_OFF_MASK_0_CAN0_STB_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DPD7_OFF_MASK_0_CAN0_STB_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD7_OFF_MASK_0_CAN0_STB_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD7_OFF_MASK_0_CAN0_STB_PARITY_PROTECTION                  _MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DPD7_OFF_MASK_0_CAN0_STB_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DPD7_OFF_MASK_0_CAN0_STB_INIT_ENUM                  ON
#define PMC_IMPL_IO_DPD7_OFF_MASK_0_CAN0_STB_OFF                        _MK_ENUM_CONST(0)
#define PMC_IMPL_IO_DPD7_OFF_MASK_0_CAN0_STB_ON                 _MK_ENUM_CONST(1)

#define PMC_IMPL_IO_DPD7_OFF_MASK_0_CAN0_EN_SHIFT                       _MK_SHIFT_CONST(7)
#define PMC_IMPL_IO_DPD7_OFF_MASK_0_CAN0_EN_FIELD                       _MK_FIELD_CONST(0x1, PMC_IMPL_IO_DPD7_OFF_MASK_0_CAN0_EN_SHIFT)
#define PMC_IMPL_IO_DPD7_OFF_MASK_0_CAN0_EN_RANGE                       7:7
#define PMC_IMPL_IO_DPD7_OFF_MASK_0_CAN0_EN_WOFFSET                     0x0
#define PMC_IMPL_IO_DPD7_OFF_MASK_0_CAN0_EN_DEFAULT                     _MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DPD7_OFF_MASK_0_CAN0_EN_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DPD7_OFF_MASK_0_CAN0_EN_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD7_OFF_MASK_0_CAN0_EN_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD7_OFF_MASK_0_CAN0_EN_PARITY_PROTECTION                   _MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DPD7_OFF_MASK_0_CAN0_EN_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DPD7_OFF_MASK_0_CAN0_EN_INIT_ENUM                   ON
#define PMC_IMPL_IO_DPD7_OFF_MASK_0_CAN0_EN_OFF                 _MK_ENUM_CONST(0)
#define PMC_IMPL_IO_DPD7_OFF_MASK_0_CAN0_EN_ON                  _MK_ENUM_CONST(1)

#define PMC_IMPL_IO_DPD7_OFF_MASK_0_GEN2_I2C_SCL_SHIFT                  _MK_SHIFT_CONST(8)
#define PMC_IMPL_IO_DPD7_OFF_MASK_0_GEN2_I2C_SCL_FIELD                  _MK_FIELD_CONST(0x1, PMC_IMPL_IO_DPD7_OFF_MASK_0_GEN2_I2C_SCL_SHIFT)
#define PMC_IMPL_IO_DPD7_OFF_MASK_0_GEN2_I2C_SCL_RANGE                  8:8
#define PMC_IMPL_IO_DPD7_OFF_MASK_0_GEN2_I2C_SCL_WOFFSET                        0x0
#define PMC_IMPL_IO_DPD7_OFF_MASK_0_GEN2_I2C_SCL_DEFAULT                        _MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DPD7_OFF_MASK_0_GEN2_I2C_SCL_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DPD7_OFF_MASK_0_GEN2_I2C_SCL_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD7_OFF_MASK_0_GEN2_I2C_SCL_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD7_OFF_MASK_0_GEN2_I2C_SCL_PARITY_PROTECTION                      _MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DPD7_OFF_MASK_0_GEN2_I2C_SCL_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DPD7_OFF_MASK_0_GEN2_I2C_SCL_INIT_ENUM                      ON
#define PMC_IMPL_IO_DPD7_OFF_MASK_0_GEN2_I2C_SCL_OFF                    _MK_ENUM_CONST(0)
#define PMC_IMPL_IO_DPD7_OFF_MASK_0_GEN2_I2C_SCL_ON                     _MK_ENUM_CONST(1)

#define PMC_IMPL_IO_DPD7_OFF_MASK_0_GEN2_I2C_SDA_SHIFT                  _MK_SHIFT_CONST(9)
#define PMC_IMPL_IO_DPD7_OFF_MASK_0_GEN2_I2C_SDA_FIELD                  _MK_FIELD_CONST(0x1, PMC_IMPL_IO_DPD7_OFF_MASK_0_GEN2_I2C_SDA_SHIFT)
#define PMC_IMPL_IO_DPD7_OFF_MASK_0_GEN2_I2C_SDA_RANGE                  9:9
#define PMC_IMPL_IO_DPD7_OFF_MASK_0_GEN2_I2C_SDA_WOFFSET                        0x0
#define PMC_IMPL_IO_DPD7_OFF_MASK_0_GEN2_I2C_SDA_DEFAULT                        _MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DPD7_OFF_MASK_0_GEN2_I2C_SDA_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DPD7_OFF_MASK_0_GEN2_I2C_SDA_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD7_OFF_MASK_0_GEN2_I2C_SDA_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD7_OFF_MASK_0_GEN2_I2C_SDA_PARITY_PROTECTION                      _MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DPD7_OFF_MASK_0_GEN2_I2C_SDA_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DPD7_OFF_MASK_0_GEN2_I2C_SDA_INIT_ENUM                      ON
#define PMC_IMPL_IO_DPD7_OFF_MASK_0_GEN2_I2C_SDA_OFF                    _MK_ENUM_CONST(0)
#define PMC_IMPL_IO_DPD7_OFF_MASK_0_GEN2_I2C_SDA_ON                     _MK_ENUM_CONST(1)

#define PMC_IMPL_IO_DPD7_OFF_MASK_0_SPI2_CS0_SHIFT                      _MK_SHIFT_CONST(10)
#define PMC_IMPL_IO_DPD7_OFF_MASK_0_SPI2_CS0_FIELD                      _MK_FIELD_CONST(0x1, PMC_IMPL_IO_DPD7_OFF_MASK_0_SPI2_CS0_SHIFT)
#define PMC_IMPL_IO_DPD7_OFF_MASK_0_SPI2_CS0_RANGE                      10:10
#define PMC_IMPL_IO_DPD7_OFF_MASK_0_SPI2_CS0_WOFFSET                    0x0
#define PMC_IMPL_IO_DPD7_OFF_MASK_0_SPI2_CS0_DEFAULT                    _MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DPD7_OFF_MASK_0_SPI2_CS0_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DPD7_OFF_MASK_0_SPI2_CS0_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD7_OFF_MASK_0_SPI2_CS0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD7_OFF_MASK_0_SPI2_CS0_PARITY_PROTECTION                  _MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DPD7_OFF_MASK_0_SPI2_CS0_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DPD7_OFF_MASK_0_SPI2_CS0_INIT_ENUM                  ON
#define PMC_IMPL_IO_DPD7_OFF_MASK_0_SPI2_CS0_OFF                        _MK_ENUM_CONST(0)
#define PMC_IMPL_IO_DPD7_OFF_MASK_0_SPI2_CS0_ON                 _MK_ENUM_CONST(1)

#define PMC_IMPL_IO_DPD7_OFF_MASK_0_SPI2_MISO_SHIFT                     _MK_SHIFT_CONST(11)
#define PMC_IMPL_IO_DPD7_OFF_MASK_0_SPI2_MISO_FIELD                     _MK_FIELD_CONST(0x1, PMC_IMPL_IO_DPD7_OFF_MASK_0_SPI2_MISO_SHIFT)
#define PMC_IMPL_IO_DPD7_OFF_MASK_0_SPI2_MISO_RANGE                     11:11
#define PMC_IMPL_IO_DPD7_OFF_MASK_0_SPI2_MISO_WOFFSET                   0x0
#define PMC_IMPL_IO_DPD7_OFF_MASK_0_SPI2_MISO_DEFAULT                   _MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DPD7_OFF_MASK_0_SPI2_MISO_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DPD7_OFF_MASK_0_SPI2_MISO_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD7_OFF_MASK_0_SPI2_MISO_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD7_OFF_MASK_0_SPI2_MISO_PARITY_PROTECTION                 _MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DPD7_OFF_MASK_0_SPI2_MISO_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DPD7_OFF_MASK_0_SPI2_MISO_INIT_ENUM                 ON
#define PMC_IMPL_IO_DPD7_OFF_MASK_0_SPI2_MISO_OFF                       _MK_ENUM_CONST(0)
#define PMC_IMPL_IO_DPD7_OFF_MASK_0_SPI2_MISO_ON                        _MK_ENUM_CONST(1)

#define PMC_IMPL_IO_DPD7_OFF_MASK_0_SPI2_MOSI_SHIFT                     _MK_SHIFT_CONST(12)
#define PMC_IMPL_IO_DPD7_OFF_MASK_0_SPI2_MOSI_FIELD                     _MK_FIELD_CONST(0x1, PMC_IMPL_IO_DPD7_OFF_MASK_0_SPI2_MOSI_SHIFT)
#define PMC_IMPL_IO_DPD7_OFF_MASK_0_SPI2_MOSI_RANGE                     12:12
#define PMC_IMPL_IO_DPD7_OFF_MASK_0_SPI2_MOSI_WOFFSET                   0x0
#define PMC_IMPL_IO_DPD7_OFF_MASK_0_SPI2_MOSI_DEFAULT                   _MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DPD7_OFF_MASK_0_SPI2_MOSI_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DPD7_OFF_MASK_0_SPI2_MOSI_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD7_OFF_MASK_0_SPI2_MOSI_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD7_OFF_MASK_0_SPI2_MOSI_PARITY_PROTECTION                 _MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DPD7_OFF_MASK_0_SPI2_MOSI_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DPD7_OFF_MASK_0_SPI2_MOSI_INIT_ENUM                 ON
#define PMC_IMPL_IO_DPD7_OFF_MASK_0_SPI2_MOSI_OFF                       _MK_ENUM_CONST(0)
#define PMC_IMPL_IO_DPD7_OFF_MASK_0_SPI2_MOSI_ON                        _MK_ENUM_CONST(1)

#define PMC_IMPL_IO_DPD7_OFF_MASK_0_SPI2_SCK_SHIFT                      _MK_SHIFT_CONST(13)
#define PMC_IMPL_IO_DPD7_OFF_MASK_0_SPI2_SCK_FIELD                      _MK_FIELD_CONST(0x1, PMC_IMPL_IO_DPD7_OFF_MASK_0_SPI2_SCK_SHIFT)
#define PMC_IMPL_IO_DPD7_OFF_MASK_0_SPI2_SCK_RANGE                      13:13
#define PMC_IMPL_IO_DPD7_OFF_MASK_0_SPI2_SCK_WOFFSET                    0x0
#define PMC_IMPL_IO_DPD7_OFF_MASK_0_SPI2_SCK_DEFAULT                    _MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DPD7_OFF_MASK_0_SPI2_SCK_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DPD7_OFF_MASK_0_SPI2_SCK_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD7_OFF_MASK_0_SPI2_SCK_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD7_OFF_MASK_0_SPI2_SCK_PARITY_PROTECTION                  _MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DPD7_OFF_MASK_0_SPI2_SCK_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DPD7_OFF_MASK_0_SPI2_SCK_INIT_ENUM                  ON
#define PMC_IMPL_IO_DPD7_OFF_MASK_0_SPI2_SCK_OFF                        _MK_ENUM_CONST(0)
#define PMC_IMPL_IO_DPD7_OFF_MASK_0_SPI2_SCK_ON                 _MK_ENUM_CONST(1)

#define PMC_IMPL_IO_DPD7_OFF_MASK_0_CAN0_WAKE_SHIFT                     _MK_SHIFT_CONST(22)
#define PMC_IMPL_IO_DPD7_OFF_MASK_0_CAN0_WAKE_FIELD                     _MK_FIELD_CONST(0x1, PMC_IMPL_IO_DPD7_OFF_MASK_0_CAN0_WAKE_SHIFT)
#define PMC_IMPL_IO_DPD7_OFF_MASK_0_CAN0_WAKE_RANGE                     22:22
#define PMC_IMPL_IO_DPD7_OFF_MASK_0_CAN0_WAKE_WOFFSET                   0x0
#define PMC_IMPL_IO_DPD7_OFF_MASK_0_CAN0_WAKE_DEFAULT                   _MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DPD7_OFF_MASK_0_CAN0_WAKE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DPD7_OFF_MASK_0_CAN0_WAKE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD7_OFF_MASK_0_CAN0_WAKE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD7_OFF_MASK_0_CAN0_WAKE_PARITY_PROTECTION                 _MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DPD7_OFF_MASK_0_CAN0_WAKE_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DPD7_OFF_MASK_0_CAN0_WAKE_INIT_ENUM                 ON
#define PMC_IMPL_IO_DPD7_OFF_MASK_0_CAN0_WAKE_OFF                       _MK_ENUM_CONST(0)
#define PMC_IMPL_IO_DPD7_OFF_MASK_0_CAN0_WAKE_ON                        _MK_ENUM_CONST(1)

#define PMC_IMPL_IO_DPD7_OFF_MASK_0_CAN0_ERR_SHIFT                      _MK_SHIFT_CONST(23)
#define PMC_IMPL_IO_DPD7_OFF_MASK_0_CAN0_ERR_FIELD                      _MK_FIELD_CONST(0x1, PMC_IMPL_IO_DPD7_OFF_MASK_0_CAN0_ERR_SHIFT)
#define PMC_IMPL_IO_DPD7_OFF_MASK_0_CAN0_ERR_RANGE                      23:23
#define PMC_IMPL_IO_DPD7_OFF_MASK_0_CAN0_ERR_WOFFSET                    0x0
#define PMC_IMPL_IO_DPD7_OFF_MASK_0_CAN0_ERR_DEFAULT                    _MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DPD7_OFF_MASK_0_CAN0_ERR_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DPD7_OFF_MASK_0_CAN0_ERR_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD7_OFF_MASK_0_CAN0_ERR_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD7_OFF_MASK_0_CAN0_ERR_PARITY_PROTECTION                  _MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DPD7_OFF_MASK_0_CAN0_ERR_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DPD7_OFF_MASK_0_CAN0_ERR_INIT_ENUM                  ON
#define PMC_IMPL_IO_DPD7_OFF_MASK_0_CAN0_ERR_OFF                        _MK_ENUM_CONST(0)
#define PMC_IMPL_IO_DPD7_OFF_MASK_0_CAN0_ERR_ON                 _MK_ENUM_CONST(1)

#define PMC_IMPL_IO_DPD7_OFF_MASK_0_CAN1_STB_SHIFT                      _MK_SHIFT_CONST(24)
#define PMC_IMPL_IO_DPD7_OFF_MASK_0_CAN1_STB_FIELD                      _MK_FIELD_CONST(0x1, PMC_IMPL_IO_DPD7_OFF_MASK_0_CAN1_STB_SHIFT)
#define PMC_IMPL_IO_DPD7_OFF_MASK_0_CAN1_STB_RANGE                      24:24
#define PMC_IMPL_IO_DPD7_OFF_MASK_0_CAN1_STB_WOFFSET                    0x0
#define PMC_IMPL_IO_DPD7_OFF_MASK_0_CAN1_STB_DEFAULT                    _MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DPD7_OFF_MASK_0_CAN1_STB_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DPD7_OFF_MASK_0_CAN1_STB_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD7_OFF_MASK_0_CAN1_STB_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD7_OFF_MASK_0_CAN1_STB_PARITY_PROTECTION                  _MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DPD7_OFF_MASK_0_CAN1_STB_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DPD7_OFF_MASK_0_CAN1_STB_INIT_ENUM                  ON
#define PMC_IMPL_IO_DPD7_OFF_MASK_0_CAN1_STB_OFF                        _MK_ENUM_CONST(0)
#define PMC_IMPL_IO_DPD7_OFF_MASK_0_CAN1_STB_ON                 _MK_ENUM_CONST(1)

#define PMC_IMPL_IO_DPD7_OFF_MASK_0_CAN1_EN_SHIFT                       _MK_SHIFT_CONST(25)
#define PMC_IMPL_IO_DPD7_OFF_MASK_0_CAN1_EN_FIELD                       _MK_FIELD_CONST(0x1, PMC_IMPL_IO_DPD7_OFF_MASK_0_CAN1_EN_SHIFT)
#define PMC_IMPL_IO_DPD7_OFF_MASK_0_CAN1_EN_RANGE                       25:25
#define PMC_IMPL_IO_DPD7_OFF_MASK_0_CAN1_EN_WOFFSET                     0x0
#define PMC_IMPL_IO_DPD7_OFF_MASK_0_CAN1_EN_DEFAULT                     _MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DPD7_OFF_MASK_0_CAN1_EN_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DPD7_OFF_MASK_0_CAN1_EN_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD7_OFF_MASK_0_CAN1_EN_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD7_OFF_MASK_0_CAN1_EN_PARITY_PROTECTION                   _MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DPD7_OFF_MASK_0_CAN1_EN_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DPD7_OFF_MASK_0_CAN1_EN_INIT_ENUM                   ON
#define PMC_IMPL_IO_DPD7_OFF_MASK_0_CAN1_EN_OFF                 _MK_ENUM_CONST(0)
#define PMC_IMPL_IO_DPD7_OFF_MASK_0_CAN1_EN_ON                  _MK_ENUM_CONST(1)

#define PMC_IMPL_IO_DPD7_OFF_MASK_0_UART3_RX_SHIFT                      _MK_SHIFT_CONST(28)
#define PMC_IMPL_IO_DPD7_OFF_MASK_0_UART3_RX_FIELD                      _MK_FIELD_CONST(0x1, PMC_IMPL_IO_DPD7_OFF_MASK_0_UART3_RX_SHIFT)
#define PMC_IMPL_IO_DPD7_OFF_MASK_0_UART3_RX_RANGE                      28:28
#define PMC_IMPL_IO_DPD7_OFF_MASK_0_UART3_RX_WOFFSET                    0x0
#define PMC_IMPL_IO_DPD7_OFF_MASK_0_UART3_RX_DEFAULT                    _MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DPD7_OFF_MASK_0_UART3_RX_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DPD7_OFF_MASK_0_UART3_RX_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD7_OFF_MASK_0_UART3_RX_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD7_OFF_MASK_0_UART3_RX_PARITY_PROTECTION                  _MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DPD7_OFF_MASK_0_UART3_RX_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DPD7_OFF_MASK_0_UART3_RX_INIT_ENUM                  ON
#define PMC_IMPL_IO_DPD7_OFF_MASK_0_UART3_RX_OFF                        _MK_ENUM_CONST(0)
#define PMC_IMPL_IO_DPD7_OFF_MASK_0_UART3_RX_ON                 _MK_ENUM_CONST(1)

#define PMC_IMPL_IO_DPD7_OFF_MASK_0_UART3_TX_SHIFT                      _MK_SHIFT_CONST(29)
#define PMC_IMPL_IO_DPD7_OFF_MASK_0_UART3_TX_FIELD                      _MK_FIELD_CONST(0x1, PMC_IMPL_IO_DPD7_OFF_MASK_0_UART3_TX_SHIFT)
#define PMC_IMPL_IO_DPD7_OFF_MASK_0_UART3_TX_RANGE                      29:29
#define PMC_IMPL_IO_DPD7_OFF_MASK_0_UART3_TX_WOFFSET                    0x0
#define PMC_IMPL_IO_DPD7_OFF_MASK_0_UART3_TX_DEFAULT                    _MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DPD7_OFF_MASK_0_UART3_TX_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DPD7_OFF_MASK_0_UART3_TX_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD7_OFF_MASK_0_UART3_TX_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD7_OFF_MASK_0_UART3_TX_PARITY_PROTECTION                  _MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DPD7_OFF_MASK_0_UART3_TX_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DPD7_OFF_MASK_0_UART3_TX_INIT_ENUM                  ON
#define PMC_IMPL_IO_DPD7_OFF_MASK_0_UART3_TX_OFF                        _MK_ENUM_CONST(0)
#define PMC_IMPL_IO_DPD7_OFF_MASK_0_UART3_TX_ON                 _MK_ENUM_CONST(1)


// Register PMC_IMPL_IO_DPD8_OFF_MASK_0
#define PMC_IMPL_IO_DPD8_OFF_MASK_0                     _MK_ADDR_CONST(0xb8)
#define PMC_IMPL_IO_DPD8_OFF_MASK_0_SECURE                      0x0
#define PMC_IMPL_IO_DPD8_OFF_MASK_0_DUAL                        0x0
#define PMC_IMPL_IO_DPD8_OFF_MASK_0_SCR                         IODPD8_SCR_0
#define PMC_IMPL_IO_DPD8_OFF_MASK_0_WORD_COUNT                  0x1
#define PMC_IMPL_IO_DPD8_OFF_MASK_0_RESET_VAL                   _MK_MASK_CONST(0x78700c2)
#define PMC_IMPL_IO_DPD8_OFF_MASK_0_RESET_MASK                  _MK_MASK_CONST(0x78700c2)
#define PMC_IMPL_IO_DPD8_OFF_MASK_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD8_OFF_MASK_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD8_OFF_MASK_0_READ_MASK                   _MK_MASK_CONST(0x78700c2)
#define PMC_IMPL_IO_DPD8_OFF_MASK_0_WRITE_MASK                  _MK_MASK_CONST(0x78700c2)
#define PMC_IMPL_IO_DPD8_OFF_MASK_0_SAFE_STATE_SHIFT                    _MK_SHIFT_CONST(1)
#define PMC_IMPL_IO_DPD8_OFF_MASK_0_SAFE_STATE_FIELD                    _MK_FIELD_CONST(0x1, PMC_IMPL_IO_DPD8_OFF_MASK_0_SAFE_STATE_SHIFT)
#define PMC_IMPL_IO_DPD8_OFF_MASK_0_SAFE_STATE_RANGE                    1:1
#define PMC_IMPL_IO_DPD8_OFF_MASK_0_SAFE_STATE_WOFFSET                  0x0
#define PMC_IMPL_IO_DPD8_OFF_MASK_0_SAFE_STATE_DEFAULT                  _MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DPD8_OFF_MASK_0_SAFE_STATE_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DPD8_OFF_MASK_0_SAFE_STATE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD8_OFF_MASK_0_SAFE_STATE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD8_OFF_MASK_0_SAFE_STATE_PARITY_PROTECTION                        _MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DPD8_OFF_MASK_0_SAFE_STATE_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DPD8_OFF_MASK_0_SAFE_STATE_INIT_ENUM                        ON
#define PMC_IMPL_IO_DPD8_OFF_MASK_0_SAFE_STATE_OFF                      _MK_ENUM_CONST(0)
#define PMC_IMPL_IO_DPD8_OFF_MASK_0_SAFE_STATE_ON                       _MK_ENUM_CONST(1)

#define PMC_IMPL_IO_DPD8_OFF_MASK_0_GEN8_I2C_SCL_SHIFT                  _MK_SHIFT_CONST(6)
#define PMC_IMPL_IO_DPD8_OFF_MASK_0_GEN8_I2C_SCL_FIELD                  _MK_FIELD_CONST(0x1, PMC_IMPL_IO_DPD8_OFF_MASK_0_GEN8_I2C_SCL_SHIFT)
#define PMC_IMPL_IO_DPD8_OFF_MASK_0_GEN8_I2C_SCL_RANGE                  6:6
#define PMC_IMPL_IO_DPD8_OFF_MASK_0_GEN8_I2C_SCL_WOFFSET                        0x0
#define PMC_IMPL_IO_DPD8_OFF_MASK_0_GEN8_I2C_SCL_DEFAULT                        _MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DPD8_OFF_MASK_0_GEN8_I2C_SCL_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DPD8_OFF_MASK_0_GEN8_I2C_SCL_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD8_OFF_MASK_0_GEN8_I2C_SCL_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD8_OFF_MASK_0_GEN8_I2C_SCL_PARITY_PROTECTION                      _MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DPD8_OFF_MASK_0_GEN8_I2C_SCL_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DPD8_OFF_MASK_0_GEN8_I2C_SCL_INIT_ENUM                      ON
#define PMC_IMPL_IO_DPD8_OFF_MASK_0_GEN8_I2C_SCL_OFF                    _MK_ENUM_CONST(0)
#define PMC_IMPL_IO_DPD8_OFF_MASK_0_GEN8_I2C_SCL_ON                     _MK_ENUM_CONST(1)

#define PMC_IMPL_IO_DPD8_OFF_MASK_0_GEN8_I2C_SDA_SHIFT                  _MK_SHIFT_CONST(7)
#define PMC_IMPL_IO_DPD8_OFF_MASK_0_GEN8_I2C_SDA_FIELD                  _MK_FIELD_CONST(0x1, PMC_IMPL_IO_DPD8_OFF_MASK_0_GEN8_I2C_SDA_SHIFT)
#define PMC_IMPL_IO_DPD8_OFF_MASK_0_GEN8_I2C_SDA_RANGE                  7:7
#define PMC_IMPL_IO_DPD8_OFF_MASK_0_GEN8_I2C_SDA_WOFFSET                        0x0
#define PMC_IMPL_IO_DPD8_OFF_MASK_0_GEN8_I2C_SDA_DEFAULT                        _MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DPD8_OFF_MASK_0_GEN8_I2C_SDA_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DPD8_OFF_MASK_0_GEN8_I2C_SDA_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD8_OFF_MASK_0_GEN8_I2C_SDA_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD8_OFF_MASK_0_GEN8_I2C_SDA_PARITY_PROTECTION                      _MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DPD8_OFF_MASK_0_GEN8_I2C_SDA_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DPD8_OFF_MASK_0_GEN8_I2C_SDA_INIT_ENUM                      ON
#define PMC_IMPL_IO_DPD8_OFF_MASK_0_GEN8_I2C_SDA_OFF                    _MK_ENUM_CONST(0)
#define PMC_IMPL_IO_DPD8_OFF_MASK_0_GEN8_I2C_SDA_ON                     _MK_ENUM_CONST(1)

#define PMC_IMPL_IO_DPD8_OFF_MASK_0_POWER_ON_SHIFT                      _MK_SHIFT_CONST(16)
#define PMC_IMPL_IO_DPD8_OFF_MASK_0_POWER_ON_FIELD                      _MK_FIELD_CONST(0x1, PMC_IMPL_IO_DPD8_OFF_MASK_0_POWER_ON_SHIFT)
#define PMC_IMPL_IO_DPD8_OFF_MASK_0_POWER_ON_RANGE                      16:16
#define PMC_IMPL_IO_DPD8_OFF_MASK_0_POWER_ON_WOFFSET                    0x0
#define PMC_IMPL_IO_DPD8_OFF_MASK_0_POWER_ON_DEFAULT                    _MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DPD8_OFF_MASK_0_POWER_ON_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DPD8_OFF_MASK_0_POWER_ON_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD8_OFF_MASK_0_POWER_ON_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD8_OFF_MASK_0_POWER_ON_PARITY_PROTECTION                  _MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DPD8_OFF_MASK_0_POWER_ON_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DPD8_OFF_MASK_0_POWER_ON_INIT_ENUM                  ON
#define PMC_IMPL_IO_DPD8_OFF_MASK_0_POWER_ON_OFF                        _MK_ENUM_CONST(0)
#define PMC_IMPL_IO_DPD8_OFF_MASK_0_POWER_ON_ON                 _MK_ENUM_CONST(1)

#define PMC_IMPL_IO_DPD8_OFF_MASK_0_PWR_I2C_SCL_SHIFT                   _MK_SHIFT_CONST(17)
#define PMC_IMPL_IO_DPD8_OFF_MASK_0_PWR_I2C_SCL_FIELD                   _MK_FIELD_CONST(0x1, PMC_IMPL_IO_DPD8_OFF_MASK_0_PWR_I2C_SCL_SHIFT)
#define PMC_IMPL_IO_DPD8_OFF_MASK_0_PWR_I2C_SCL_RANGE                   17:17
#define PMC_IMPL_IO_DPD8_OFF_MASK_0_PWR_I2C_SCL_WOFFSET                 0x0
#define PMC_IMPL_IO_DPD8_OFF_MASK_0_PWR_I2C_SCL_DEFAULT                 _MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DPD8_OFF_MASK_0_PWR_I2C_SCL_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DPD8_OFF_MASK_0_PWR_I2C_SCL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD8_OFF_MASK_0_PWR_I2C_SCL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD8_OFF_MASK_0_PWR_I2C_SCL_PARITY_PROTECTION                       _MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DPD8_OFF_MASK_0_PWR_I2C_SCL_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DPD8_OFF_MASK_0_PWR_I2C_SCL_INIT_ENUM                       ON
#define PMC_IMPL_IO_DPD8_OFF_MASK_0_PWR_I2C_SCL_OFF                     _MK_ENUM_CONST(0)
#define PMC_IMPL_IO_DPD8_OFF_MASK_0_PWR_I2C_SCL_ON                      _MK_ENUM_CONST(1)

#define PMC_IMPL_IO_DPD8_OFF_MASK_0_PWR_I2C_SDA_SHIFT                   _MK_SHIFT_CONST(18)
#define PMC_IMPL_IO_DPD8_OFF_MASK_0_PWR_I2C_SDA_FIELD                   _MK_FIELD_CONST(0x1, PMC_IMPL_IO_DPD8_OFF_MASK_0_PWR_I2C_SDA_SHIFT)
#define PMC_IMPL_IO_DPD8_OFF_MASK_0_PWR_I2C_SDA_RANGE                   18:18
#define PMC_IMPL_IO_DPD8_OFF_MASK_0_PWR_I2C_SDA_WOFFSET                 0x0
#define PMC_IMPL_IO_DPD8_OFF_MASK_0_PWR_I2C_SDA_DEFAULT                 _MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DPD8_OFF_MASK_0_PWR_I2C_SDA_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DPD8_OFF_MASK_0_PWR_I2C_SDA_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD8_OFF_MASK_0_PWR_I2C_SDA_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD8_OFF_MASK_0_PWR_I2C_SDA_PARITY_PROTECTION                       _MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DPD8_OFF_MASK_0_PWR_I2C_SDA_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DPD8_OFF_MASK_0_PWR_I2C_SDA_INIT_ENUM                       ON
#define PMC_IMPL_IO_DPD8_OFF_MASK_0_PWR_I2C_SDA_OFF                     _MK_ENUM_CONST(0)
#define PMC_IMPL_IO_DPD8_OFF_MASK_0_PWR_I2C_SDA_ON                      _MK_ENUM_CONST(1)

#define PMC_IMPL_IO_DPD8_OFF_MASK_0_TOUCH_CLK_SHIFT                     _MK_SHIFT_CONST(23)
#define PMC_IMPL_IO_DPD8_OFF_MASK_0_TOUCH_CLK_FIELD                     _MK_FIELD_CONST(0x1, PMC_IMPL_IO_DPD8_OFF_MASK_0_TOUCH_CLK_SHIFT)
#define PMC_IMPL_IO_DPD8_OFF_MASK_0_TOUCH_CLK_RANGE                     23:23
#define PMC_IMPL_IO_DPD8_OFF_MASK_0_TOUCH_CLK_WOFFSET                   0x0
#define PMC_IMPL_IO_DPD8_OFF_MASK_0_TOUCH_CLK_DEFAULT                   _MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DPD8_OFF_MASK_0_TOUCH_CLK_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DPD8_OFF_MASK_0_TOUCH_CLK_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD8_OFF_MASK_0_TOUCH_CLK_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD8_OFF_MASK_0_TOUCH_CLK_PARITY_PROTECTION                 _MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DPD8_OFF_MASK_0_TOUCH_CLK_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DPD8_OFF_MASK_0_TOUCH_CLK_INIT_ENUM                 ON
#define PMC_IMPL_IO_DPD8_OFF_MASK_0_TOUCH_CLK_OFF                       _MK_ENUM_CONST(0)
#define PMC_IMPL_IO_DPD8_OFF_MASK_0_TOUCH_CLK_ON                        _MK_ENUM_CONST(1)

#define PMC_IMPL_IO_DPD8_OFF_MASK_0_VCOMP_ALERT_SHIFT                   _MK_SHIFT_CONST(24)
#define PMC_IMPL_IO_DPD8_OFF_MASK_0_VCOMP_ALERT_FIELD                   _MK_FIELD_CONST(0x1, PMC_IMPL_IO_DPD8_OFF_MASK_0_VCOMP_ALERT_SHIFT)
#define PMC_IMPL_IO_DPD8_OFF_MASK_0_VCOMP_ALERT_RANGE                   24:24
#define PMC_IMPL_IO_DPD8_OFF_MASK_0_VCOMP_ALERT_WOFFSET                 0x0
#define PMC_IMPL_IO_DPD8_OFF_MASK_0_VCOMP_ALERT_DEFAULT                 _MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DPD8_OFF_MASK_0_VCOMP_ALERT_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DPD8_OFF_MASK_0_VCOMP_ALERT_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD8_OFF_MASK_0_VCOMP_ALERT_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD8_OFF_MASK_0_VCOMP_ALERT_PARITY_PROTECTION                       _MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DPD8_OFF_MASK_0_VCOMP_ALERT_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DPD8_OFF_MASK_0_VCOMP_ALERT_INIT_ENUM                       ON
#define PMC_IMPL_IO_DPD8_OFF_MASK_0_VCOMP_ALERT_OFF                     _MK_ENUM_CONST(0)
#define PMC_IMPL_IO_DPD8_OFF_MASK_0_VCOMP_ALERT_ON                      _MK_ENUM_CONST(1)

#define PMC_IMPL_IO_DPD8_OFF_MASK_0_CAN1_WAKE_SHIFT                     _MK_SHIFT_CONST(25)
#define PMC_IMPL_IO_DPD8_OFF_MASK_0_CAN1_WAKE_FIELD                     _MK_FIELD_CONST(0x1, PMC_IMPL_IO_DPD8_OFF_MASK_0_CAN1_WAKE_SHIFT)
#define PMC_IMPL_IO_DPD8_OFF_MASK_0_CAN1_WAKE_RANGE                     25:25
#define PMC_IMPL_IO_DPD8_OFF_MASK_0_CAN1_WAKE_WOFFSET                   0x0
#define PMC_IMPL_IO_DPD8_OFF_MASK_0_CAN1_WAKE_DEFAULT                   _MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DPD8_OFF_MASK_0_CAN1_WAKE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DPD8_OFF_MASK_0_CAN1_WAKE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD8_OFF_MASK_0_CAN1_WAKE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD8_OFF_MASK_0_CAN1_WAKE_PARITY_PROTECTION                 _MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DPD8_OFF_MASK_0_CAN1_WAKE_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DPD8_OFF_MASK_0_CAN1_WAKE_INIT_ENUM                 ON
#define PMC_IMPL_IO_DPD8_OFF_MASK_0_CAN1_WAKE_OFF                       _MK_ENUM_CONST(0)
#define PMC_IMPL_IO_DPD8_OFF_MASK_0_CAN1_WAKE_ON                        _MK_ENUM_CONST(1)

#define PMC_IMPL_IO_DPD8_OFF_MASK_0_CAN1_ERR_SHIFT                      _MK_SHIFT_CONST(26)
#define PMC_IMPL_IO_DPD8_OFF_MASK_0_CAN1_ERR_FIELD                      _MK_FIELD_CONST(0x1, PMC_IMPL_IO_DPD8_OFF_MASK_0_CAN1_ERR_SHIFT)
#define PMC_IMPL_IO_DPD8_OFF_MASK_0_CAN1_ERR_RANGE                      26:26
#define PMC_IMPL_IO_DPD8_OFF_MASK_0_CAN1_ERR_WOFFSET                    0x0
#define PMC_IMPL_IO_DPD8_OFF_MASK_0_CAN1_ERR_DEFAULT                    _MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DPD8_OFF_MASK_0_CAN1_ERR_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DPD8_OFF_MASK_0_CAN1_ERR_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD8_OFF_MASK_0_CAN1_ERR_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define PMC_IMPL_IO_DPD8_OFF_MASK_0_CAN1_ERR_PARITY_PROTECTION                  _MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DPD8_OFF_MASK_0_CAN1_ERR_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define PMC_IMPL_IO_DPD8_OFF_MASK_0_CAN1_ERR_INIT_ENUM                  ON
#define PMC_IMPL_IO_DPD8_OFF_MASK_0_CAN1_ERR_OFF                        _MK_ENUM_CONST(0)
#define PMC_IMPL_IO_DPD8_OFF_MASK_0_CAN1_ERR_ON                 _MK_ENUM_CONST(1)


// Register PMC_IMPL_SEL_DPD_TIM_0
#define PMC_IMPL_SEL_DPD_TIM_0                  _MK_ADDR_CONST(0xbc)
#define PMC_IMPL_SEL_DPD_TIM_0_SECURE                   0x0
#define PMC_IMPL_SEL_DPD_TIM_0_DUAL                     0x0
#define PMC_IMPL_SEL_DPD_TIM_0_SCR                      SEL_DPD_TIM_SCR_0
#define PMC_IMPL_SEL_DPD_TIM_0_WORD_COUNT                       0x1
#define PMC_IMPL_SEL_DPD_TIM_0_RESET_VAL                        _MK_MASK_CONST(0x7f)
#define PMC_IMPL_SEL_DPD_TIM_0_RESET_MASK                       _MK_MASK_CONST(0x7f)
#define PMC_IMPL_SEL_DPD_TIM_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_SEL_DPD_TIM_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define PMC_IMPL_SEL_DPD_TIM_0_READ_MASK                        _MK_MASK_CONST(0x7f)
#define PMC_IMPL_SEL_DPD_TIM_0_WRITE_MASK                       _MK_MASK_CONST(0x7f)
#define PMC_IMPL_SEL_DPD_TIM_0_SEL_DPD_TIM_SHIFT                        _MK_SHIFT_CONST(0)
#define PMC_IMPL_SEL_DPD_TIM_0_SEL_DPD_TIM_FIELD                        _MK_FIELD_CONST(0x7f, PMC_IMPL_SEL_DPD_TIM_0_SEL_DPD_TIM_SHIFT)
#define PMC_IMPL_SEL_DPD_TIM_0_SEL_DPD_TIM_RANGE                        6:0
#define PMC_IMPL_SEL_DPD_TIM_0_SEL_DPD_TIM_WOFFSET                      0x0
#define PMC_IMPL_SEL_DPD_TIM_0_SEL_DPD_TIM_DEFAULT                      _MK_MASK_CONST(0x7f)
#define PMC_IMPL_SEL_DPD_TIM_0_SEL_DPD_TIM_DEFAULT_MASK                 _MK_MASK_CONST(0x7f)
#define PMC_IMPL_SEL_DPD_TIM_0_SEL_DPD_TIM_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_SEL_DPD_TIM_0_SEL_DPD_TIM_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_SEL_DPD_TIM_0_SEL_DPD_TIM_PARITY_PROTECTION                    _MK_MASK_CONST(0x1)
#define PMC_IMPL_SEL_DPD_TIM_0_SEL_DPD_TIM_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)


// Reserved address 0xc0

// Reserved address 0xc4

// Reserved address 0xc8

// Reserved address 0xcc

// Reserved address 0xd0

// Register PMC_IMPL_TSC_MULT_0
#define PMC_IMPL_TSC_MULT_0                     _MK_ADDR_CONST(0xd4)
#define PMC_IMPL_TSC_MULT_0_SECURE                      0x0
#define PMC_IMPL_TSC_MULT_0_DUAL                        0x0
#define PMC_IMPL_TSC_MULT_0_SCR                         0
#define PMC_IMPL_TSC_MULT_0_WORD_COUNT                  0x1
#define PMC_IMPL_TSC_MULT_0_RESET_VAL                   _MK_MASK_CONST(0x16e0)
#define PMC_IMPL_TSC_MULT_0_RESET_MASK                  _MK_MASK_CONST(0xeffff)
#define PMC_IMPL_TSC_MULT_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_TSC_MULT_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_TSC_MULT_0_READ_MASK                   _MK_MASK_CONST(0xfffff)
#define PMC_IMPL_TSC_MULT_0_WRITE_MASK                  _MK_MASK_CONST(0xeffff)
#define PMC_IMPL_TSC_MULT_0_MULT_VAL_SHIFT                      _MK_SHIFT_CONST(0)
#define PMC_IMPL_TSC_MULT_0_MULT_VAL_FIELD                      _MK_FIELD_CONST(0xffff, PMC_IMPL_TSC_MULT_0_MULT_VAL_SHIFT)
#define PMC_IMPL_TSC_MULT_0_MULT_VAL_RANGE                      15:0
#define PMC_IMPL_TSC_MULT_0_MULT_VAL_WOFFSET                    0x0
#define PMC_IMPL_TSC_MULT_0_MULT_VAL_DEFAULT                    _MK_MASK_CONST(0x16e0)
#define PMC_IMPL_TSC_MULT_0_MULT_VAL_DEFAULT_MASK                       _MK_MASK_CONST(0xffff)
#define PMC_IMPL_TSC_MULT_0_MULT_VAL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define PMC_IMPL_TSC_MULT_0_MULT_VAL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define PMC_IMPL_TSC_MULT_0_MULT_VAL_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define PMC_IMPL_TSC_MULT_0_MULT_VAL_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)

#define PMC_IMPL_TSC_MULT_0_FREQ_STS_SHIFT                      _MK_SHIFT_CONST(16)
#define PMC_IMPL_TSC_MULT_0_FREQ_STS_FIELD                      _MK_FIELD_CONST(0x1, PMC_IMPL_TSC_MULT_0_FREQ_STS_SHIFT)
#define PMC_IMPL_TSC_MULT_0_FREQ_STS_RANGE                      16:16
#define PMC_IMPL_TSC_MULT_0_FREQ_STS_WOFFSET                    0x0
#define PMC_IMPL_TSC_MULT_0_FREQ_STS_DEFAULT                    _MK_MASK_CONST(0x0)
#define PMC_IMPL_TSC_MULT_0_FREQ_STS_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define PMC_IMPL_TSC_MULT_0_FREQ_STS_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define PMC_IMPL_TSC_MULT_0_FREQ_STS_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define PMC_IMPL_TSC_MULT_0_FREQ_STS_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define PMC_IMPL_TSC_MULT_0_FREQ_STS_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)

#define PMC_IMPL_TSC_MULT_0_TICK_SEL_SHIFT                      _MK_SHIFT_CONST(17)
#define PMC_IMPL_TSC_MULT_0_TICK_SEL_FIELD                      _MK_FIELD_CONST(0x7, PMC_IMPL_TSC_MULT_0_TICK_SEL_SHIFT)
#define PMC_IMPL_TSC_MULT_0_TICK_SEL_RANGE                      19:17
#define PMC_IMPL_TSC_MULT_0_TICK_SEL_WOFFSET                    0x0
#define PMC_IMPL_TSC_MULT_0_TICK_SEL_DEFAULT                    _MK_MASK_CONST(0x0)
#define PMC_IMPL_TSC_MULT_0_TICK_SEL_DEFAULT_MASK                       _MK_MASK_CONST(0x7)
#define PMC_IMPL_TSC_MULT_0_TICK_SEL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define PMC_IMPL_TSC_MULT_0_TICK_SEL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define PMC_IMPL_TSC_MULT_0_TICK_SEL_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define PMC_IMPL_TSC_MULT_0_TICK_SEL_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define PMC_IMPL_TSC_MULT_0_TICK_SEL_BIT0                       _MK_ENUM_CONST(0)
#define PMC_IMPL_TSC_MULT_0_TICK_SEL_BIT1                       _MK_ENUM_CONST(1)
#define PMC_IMPL_TSC_MULT_0_TICK_SEL_BIT2                       _MK_ENUM_CONST(2)
#define PMC_IMPL_TSC_MULT_0_TICK_SEL_BIT3                       _MK_ENUM_CONST(3)
#define PMC_IMPL_TSC_MULT_0_TICK_SEL_BIT4                       _MK_ENUM_CONST(4)
#define PMC_IMPL_TSC_MULT_0_TICK_SEL_BIT5                       _MK_ENUM_CONST(5)


// Register PMC_IMPL_GLB_AMAP_CFG_0
#define PMC_IMPL_GLB_AMAP_CFG_0                 _MK_ADDR_CONST(0xd8)
#define PMC_IMPL_GLB_AMAP_CFG_0_SECURE                  0x0
#define PMC_IMPL_GLB_AMAP_CFG_0_DUAL                    0x0
#define PMC_IMPL_GLB_AMAP_CFG_0_SCR                     AMAP_SCR_0
#define PMC_IMPL_GLB_AMAP_CFG_0_WORD_COUNT                      0x1
#define PMC_IMPL_GLB_AMAP_CFG_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define PMC_IMPL_GLB_AMAP_CFG_0_RESET_MASK                      _MK_MASK_CONST(0x1e)
#define PMC_IMPL_GLB_AMAP_CFG_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define PMC_IMPL_GLB_AMAP_CFG_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define PMC_IMPL_GLB_AMAP_CFG_0_READ_MASK                       _MK_MASK_CONST(0x1e)
#define PMC_IMPL_GLB_AMAP_CFG_0_WRITE_MASK                      _MK_MASK_CONST(0x1e)
#define PMC_IMPL_GLB_AMAP_CFG_0_PCIE_A1_SHIFT                   _MK_SHIFT_CONST(1)
#define PMC_IMPL_GLB_AMAP_CFG_0_PCIE_A1_FIELD                   _MK_FIELD_CONST(0x1, PMC_IMPL_GLB_AMAP_CFG_0_PCIE_A1_SHIFT)
#define PMC_IMPL_GLB_AMAP_CFG_0_PCIE_A1_RANGE                   1:1
#define PMC_IMPL_GLB_AMAP_CFG_0_PCIE_A1_WOFFSET                 0x0
#define PMC_IMPL_GLB_AMAP_CFG_0_PCIE_A1_DEFAULT                 _MK_MASK_CONST(0x0)
#define PMC_IMPL_GLB_AMAP_CFG_0_PCIE_A1_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define PMC_IMPL_GLB_AMAP_CFG_0_PCIE_A1_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_GLB_AMAP_CFG_0_PCIE_A1_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define PMC_IMPL_GLB_AMAP_CFG_0_PCIE_A1_PARITY_PROTECTION                       _MK_MASK_CONST(0x1)
#define PMC_IMPL_GLB_AMAP_CFG_0_PCIE_A1_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define PMC_IMPL_GLB_AMAP_CFG_0_PCIE_A1_MMIO                    _MK_ENUM_CONST(0)
#define PMC_IMPL_GLB_AMAP_CFG_0_PCIE_A1_DRAM                    _MK_ENUM_CONST(1)

#define PMC_IMPL_GLB_AMAP_CFG_0_PCIE_A2_SHIFT                   _MK_SHIFT_CONST(2)
#define PMC_IMPL_GLB_AMAP_CFG_0_PCIE_A2_FIELD                   _MK_FIELD_CONST(0x1, PMC_IMPL_GLB_AMAP_CFG_0_PCIE_A2_SHIFT)
#define PMC_IMPL_GLB_AMAP_CFG_0_PCIE_A2_RANGE                   2:2
#define PMC_IMPL_GLB_AMAP_CFG_0_PCIE_A2_WOFFSET                 0x0
#define PMC_IMPL_GLB_AMAP_CFG_0_PCIE_A2_DEFAULT                 _MK_MASK_CONST(0x0)
#define PMC_IMPL_GLB_AMAP_CFG_0_PCIE_A2_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define PMC_IMPL_GLB_AMAP_CFG_0_PCIE_A2_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_GLB_AMAP_CFG_0_PCIE_A2_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define PMC_IMPL_GLB_AMAP_CFG_0_PCIE_A2_PARITY_PROTECTION                       _MK_MASK_CONST(0x1)
#define PMC_IMPL_GLB_AMAP_CFG_0_PCIE_A2_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define PMC_IMPL_GLB_AMAP_CFG_0_PCIE_A2_MMIO                    _MK_ENUM_CONST(0)
#define PMC_IMPL_GLB_AMAP_CFG_0_PCIE_A2_DRAM                    _MK_ENUM_CONST(1)

#define PMC_IMPL_GLB_AMAP_CFG_0_PCIE_A3_SHIFT                   _MK_SHIFT_CONST(3)
#define PMC_IMPL_GLB_AMAP_CFG_0_PCIE_A3_FIELD                   _MK_FIELD_CONST(0x1, PMC_IMPL_GLB_AMAP_CFG_0_PCIE_A3_SHIFT)
#define PMC_IMPL_GLB_AMAP_CFG_0_PCIE_A3_RANGE                   3:3
#define PMC_IMPL_GLB_AMAP_CFG_0_PCIE_A3_WOFFSET                 0x0
#define PMC_IMPL_GLB_AMAP_CFG_0_PCIE_A3_DEFAULT                 _MK_MASK_CONST(0x0)
#define PMC_IMPL_GLB_AMAP_CFG_0_PCIE_A3_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define PMC_IMPL_GLB_AMAP_CFG_0_PCIE_A3_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_GLB_AMAP_CFG_0_PCIE_A3_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define PMC_IMPL_GLB_AMAP_CFG_0_PCIE_A3_PARITY_PROTECTION                       _MK_MASK_CONST(0x1)
#define PMC_IMPL_GLB_AMAP_CFG_0_PCIE_A3_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define PMC_IMPL_GLB_AMAP_CFG_0_PCIE_A3_MMIO                    _MK_ENUM_CONST(0)
#define PMC_IMPL_GLB_AMAP_CFG_0_PCIE_A3_DRAM                    _MK_ENUM_CONST(1)

#define PMC_IMPL_GLB_AMAP_CFG_0_PCIE_A4_SHIFT                   _MK_SHIFT_CONST(4)
#define PMC_IMPL_GLB_AMAP_CFG_0_PCIE_A4_FIELD                   _MK_FIELD_CONST(0x1, PMC_IMPL_GLB_AMAP_CFG_0_PCIE_A4_SHIFT)
#define PMC_IMPL_GLB_AMAP_CFG_0_PCIE_A4_RANGE                   4:4
#define PMC_IMPL_GLB_AMAP_CFG_0_PCIE_A4_WOFFSET                 0x0
#define PMC_IMPL_GLB_AMAP_CFG_0_PCIE_A4_DEFAULT                 _MK_MASK_CONST(0x0)
#define PMC_IMPL_GLB_AMAP_CFG_0_PCIE_A4_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define PMC_IMPL_GLB_AMAP_CFG_0_PCIE_A4_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_GLB_AMAP_CFG_0_PCIE_A4_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define PMC_IMPL_GLB_AMAP_CFG_0_PCIE_A4_PARITY_PROTECTION                       _MK_MASK_CONST(0x1)
#define PMC_IMPL_GLB_AMAP_CFG_0_PCIE_A4_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define PMC_IMPL_GLB_AMAP_CFG_0_PCIE_A4_MMIO                    _MK_ENUM_CONST(0)
#define PMC_IMPL_GLB_AMAP_CFG_0_PCIE_A4_DRAM                    _MK_ENUM_CONST(1)


// Reserved address 0xdc

// Reserved address 0xe0

// Reserved address 0xe4

// Register PMC_IMPL_GPU_RG_CNTRL_0
#define PMC_IMPL_GPU_RG_CNTRL_0                 _MK_ADDR_CONST(0xe8)
#define PMC_IMPL_GPU_RG_CNTRL_0_SECURE                  0x0
#define PMC_IMPL_GPU_RG_CNTRL_0_DUAL                    0x0
#define PMC_IMPL_GPU_RG_CNTRL_0_SCR                     GPU_SCR_0
#define PMC_IMPL_GPU_RG_CNTRL_0_WORD_COUNT                      0x1
#define PMC_IMPL_GPU_RG_CNTRL_0_RESET_VAL                       _MK_MASK_CONST(0x1)
#define PMC_IMPL_GPU_RG_CNTRL_0_RESET_MASK                      _MK_MASK_CONST(0x1)
#define PMC_IMPL_GPU_RG_CNTRL_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define PMC_IMPL_GPU_RG_CNTRL_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define PMC_IMPL_GPU_RG_CNTRL_0_READ_MASK                       _MK_MASK_CONST(0x1)
#define PMC_IMPL_GPU_RG_CNTRL_0_WRITE_MASK                      _MK_MASK_CONST(0x1)
#define PMC_IMPL_GPU_RG_CNTRL_0_RAIL_CLAMP_SHIFT                        _MK_SHIFT_CONST(0)
#define PMC_IMPL_GPU_RG_CNTRL_0_RAIL_CLAMP_FIELD                        _MK_FIELD_CONST(0x1, PMC_IMPL_GPU_RG_CNTRL_0_RAIL_CLAMP_SHIFT)
#define PMC_IMPL_GPU_RG_CNTRL_0_RAIL_CLAMP_RANGE                        0:0
#define PMC_IMPL_GPU_RG_CNTRL_0_RAIL_CLAMP_WOFFSET                      0x0
#define PMC_IMPL_GPU_RG_CNTRL_0_RAIL_CLAMP_DEFAULT                      _MK_MASK_CONST(0x1)
#define PMC_IMPL_GPU_RG_CNTRL_0_RAIL_CLAMP_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define PMC_IMPL_GPU_RG_CNTRL_0_RAIL_CLAMP_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_GPU_RG_CNTRL_0_RAIL_CLAMP_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_GPU_RG_CNTRL_0_RAIL_CLAMP_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define PMC_IMPL_GPU_RG_CNTRL_0_RAIL_CLAMP_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)
#define PMC_IMPL_GPU_RG_CNTRL_0_RAIL_CLAMP_DISABLE                      _MK_ENUM_CONST(0)
#define PMC_IMPL_GPU_RG_CNTRL_0_RAIL_CLAMP_ENABLE                       _MK_ENUM_CONST(1)


// Reserved address 0xec

// Reserved address 0xf0

// Register PMC_IMPL_UFSHC_PWR_CNTRL_0
#define PMC_IMPL_UFSHC_PWR_CNTRL_0                      _MK_ADDR_CONST(0xf4)
#define PMC_IMPL_UFSHC_PWR_CNTRL_0_SECURE                       0x0
#define PMC_IMPL_UFSHC_PWR_CNTRL_0_DUAL                         0x0
#define PMC_IMPL_UFSHC_PWR_CNTRL_0_SCR                  CNTRL_SCR_0
#define PMC_IMPL_UFSHC_PWR_CNTRL_0_WORD_COUNT                   0x1
#define PMC_IMPL_UFSHC_PWR_CNTRL_0_RESET_VAL                    _MK_MASK_CONST(0x3)
#define PMC_IMPL_UFSHC_PWR_CNTRL_0_RESET_MASK                   _MK_MASK_CONST(0x3)
#define PMC_IMPL_UFSHC_PWR_CNTRL_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define PMC_IMPL_UFSHC_PWR_CNTRL_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_UFSHC_PWR_CNTRL_0_READ_MASK                    _MK_MASK_CONST(0x3)
#define PMC_IMPL_UFSHC_PWR_CNTRL_0_WRITE_MASK                   _MK_MASK_CONST(0x3)
#define PMC_IMPL_UFSHC_PWR_CNTRL_0_LP_ISOL_EN_SHIFT                     _MK_SHIFT_CONST(0)
#define PMC_IMPL_UFSHC_PWR_CNTRL_0_LP_ISOL_EN_FIELD                     _MK_FIELD_CONST(0x1, PMC_IMPL_UFSHC_PWR_CNTRL_0_LP_ISOL_EN_SHIFT)
#define PMC_IMPL_UFSHC_PWR_CNTRL_0_LP_ISOL_EN_RANGE                     0:0
#define PMC_IMPL_UFSHC_PWR_CNTRL_0_LP_ISOL_EN_WOFFSET                   0x0
#define PMC_IMPL_UFSHC_PWR_CNTRL_0_LP_ISOL_EN_DEFAULT                   _MK_MASK_CONST(0x1)
#define PMC_IMPL_UFSHC_PWR_CNTRL_0_LP_ISOL_EN_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define PMC_IMPL_UFSHC_PWR_CNTRL_0_LP_ISOL_EN_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_UFSHC_PWR_CNTRL_0_LP_ISOL_EN_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_UFSHC_PWR_CNTRL_0_LP_ISOL_EN_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define PMC_IMPL_UFSHC_PWR_CNTRL_0_LP_ISOL_EN_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define PMC_IMPL_UFSHC_PWR_CNTRL_0_LP_ISOL_EN_INIT_ENUM                 ENABLE
#define PMC_IMPL_UFSHC_PWR_CNTRL_0_LP_ISOL_EN_DISABLE                   _MK_ENUM_CONST(0)
#define PMC_IMPL_UFSHC_PWR_CNTRL_0_LP_ISOL_EN_ENABLE                    _MK_ENUM_CONST(1)

#define PMC_IMPL_UFSHC_PWR_CNTRL_0_LP_PWR_READY_SHIFT                   _MK_SHIFT_CONST(1)
#define PMC_IMPL_UFSHC_PWR_CNTRL_0_LP_PWR_READY_FIELD                   _MK_FIELD_CONST(0x1, PMC_IMPL_UFSHC_PWR_CNTRL_0_LP_PWR_READY_SHIFT)
#define PMC_IMPL_UFSHC_PWR_CNTRL_0_LP_PWR_READY_RANGE                   1:1
#define PMC_IMPL_UFSHC_PWR_CNTRL_0_LP_PWR_READY_WOFFSET                 0x0
#define PMC_IMPL_UFSHC_PWR_CNTRL_0_LP_PWR_READY_DEFAULT                 _MK_MASK_CONST(0x1)
#define PMC_IMPL_UFSHC_PWR_CNTRL_0_LP_PWR_READY_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define PMC_IMPL_UFSHC_PWR_CNTRL_0_LP_PWR_READY_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_UFSHC_PWR_CNTRL_0_LP_PWR_READY_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define PMC_IMPL_UFSHC_PWR_CNTRL_0_LP_PWR_READY_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define PMC_IMPL_UFSHC_PWR_CNTRL_0_LP_PWR_READY_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define PMC_IMPL_UFSHC_PWR_CNTRL_0_LP_PWR_READY_INIT_ENUM                       ENABLE
#define PMC_IMPL_UFSHC_PWR_CNTRL_0_LP_PWR_READY_DISABLE                 _MK_ENUM_CONST(0)
#define PMC_IMPL_UFSHC_PWR_CNTRL_0_LP_PWR_READY_ENABLE                  _MK_ENUM_CONST(1)


// Register PMC_IMPL_CNTRL2_0
#define PMC_IMPL_CNTRL2_0                       _MK_ADDR_CONST(0xf8)
#define PMC_IMPL_CNTRL2_0_SECURE                        0x0
#define PMC_IMPL_CNTRL2_0_DUAL                  0x0
#define PMC_IMPL_CNTRL2_0_SCR                   CNTRL_SCR_0
#define PMC_IMPL_CNTRL2_0_WORD_COUNT                    0x1
#define PMC_IMPL_CNTRL2_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_CNTRL2_0_RESET_MASK                    _MK_MASK_CONST(0x1c00)
#define PMC_IMPL_CNTRL2_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_CNTRL2_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define PMC_IMPL_CNTRL2_0_READ_MASK                     _MK_MASK_CONST(0x1dfe)
#define PMC_IMPL_CNTRL2_0_WRITE_MASK                    _MK_MASK_CONST(0x1dfe)
#define PMC_IMPL_CNTRL2_0_HOLD_CKE_LOW_EN_SHIFT                 _MK_SHIFT_CONST(12)
#define PMC_IMPL_CNTRL2_0_HOLD_CKE_LOW_EN_FIELD                 _MK_FIELD_CONST(0x1, PMC_IMPL_CNTRL2_0_HOLD_CKE_LOW_EN_SHIFT)
#define PMC_IMPL_CNTRL2_0_HOLD_CKE_LOW_EN_RANGE                 12:12
#define PMC_IMPL_CNTRL2_0_HOLD_CKE_LOW_EN_WOFFSET                       0x0
#define PMC_IMPL_CNTRL2_0_HOLD_CKE_LOW_EN_DEFAULT                       _MK_MASK_CONST(0x0)
#define PMC_IMPL_CNTRL2_0_HOLD_CKE_LOW_EN_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define PMC_IMPL_CNTRL2_0_HOLD_CKE_LOW_EN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define PMC_IMPL_CNTRL2_0_HOLD_CKE_LOW_EN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define PMC_IMPL_CNTRL2_0_HOLD_CKE_LOW_EN_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_CNTRL2_0_HOLD_CKE_LOW_EN_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)
#define PMC_IMPL_CNTRL2_0_HOLD_CKE_LOW_EN_DISABLE                       _MK_ENUM_CONST(0)
#define PMC_IMPL_CNTRL2_0_HOLD_CKE_LOW_EN_ENABLE                        _MK_ENUM_CONST(1)

#define PMC_IMPL_CNTRL2_0_SYSCLK_DATA_SHIFT                     _MK_SHIFT_CONST(11)
#define PMC_IMPL_CNTRL2_0_SYSCLK_DATA_FIELD                     _MK_FIELD_CONST(0x1, PMC_IMPL_CNTRL2_0_SYSCLK_DATA_SHIFT)
#define PMC_IMPL_CNTRL2_0_SYSCLK_DATA_RANGE                     11:11
#define PMC_IMPL_CNTRL2_0_SYSCLK_DATA_WOFFSET                   0x0
#define PMC_IMPL_CNTRL2_0_SYSCLK_DATA_DEFAULT                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_CNTRL2_0_SYSCLK_DATA_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define PMC_IMPL_CNTRL2_0_SYSCLK_DATA_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_CNTRL2_0_SYSCLK_DATA_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_CNTRL2_0_SYSCLK_DATA_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define PMC_IMPL_CNTRL2_0_SYSCLK_DATA_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)

#define PMC_IMPL_CNTRL2_0_SYSCLK_ORRIDE_SHIFT                   _MK_SHIFT_CONST(10)
#define PMC_IMPL_CNTRL2_0_SYSCLK_ORRIDE_FIELD                   _MK_FIELD_CONST(0x1, PMC_IMPL_CNTRL2_0_SYSCLK_ORRIDE_SHIFT)
#define PMC_IMPL_CNTRL2_0_SYSCLK_ORRIDE_RANGE                   10:10
#define PMC_IMPL_CNTRL2_0_SYSCLK_ORRIDE_WOFFSET                 0x0
#define PMC_IMPL_CNTRL2_0_SYSCLK_ORRIDE_DEFAULT                 _MK_MASK_CONST(0x0)
#define PMC_IMPL_CNTRL2_0_SYSCLK_ORRIDE_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define PMC_IMPL_CNTRL2_0_SYSCLK_ORRIDE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_CNTRL2_0_SYSCLK_ORRIDE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define PMC_IMPL_CNTRL2_0_SYSCLK_ORRIDE_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define PMC_IMPL_CNTRL2_0_SYSCLK_ORRIDE_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define PMC_IMPL_CNTRL2_0_SYSCLK_ORRIDE_DISABLE                 _MK_ENUM_CONST(0)
#define PMC_IMPL_CNTRL2_0_SYSCLK_ORRIDE_ENABLE                  _MK_ENUM_CONST(1)

#define PMC_IMPL_CNTRL2_0_RESERVED_SHIFT                        _MK_SHIFT_CONST(1)
#define PMC_IMPL_CNTRL2_0_RESERVED_FIELD                        _MK_FIELD_CONST(0xff, PMC_IMPL_CNTRL2_0_RESERVED_SHIFT)
#define PMC_IMPL_CNTRL2_0_RESERVED_RANGE                        8:1
#define PMC_IMPL_CNTRL2_0_RESERVED_WOFFSET                      0x0
#define PMC_IMPL_CNTRL2_0_RESERVED_DEFAULT                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_CNTRL2_0_RESERVED_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define PMC_IMPL_CNTRL2_0_RESERVED_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_CNTRL2_0_RESERVED_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_CNTRL2_0_RESERVED_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define PMC_IMPL_CNTRL2_0_RESERVED_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)


// Register PMC_IMPL_EVENT_COUNTER_0
#define PMC_IMPL_EVENT_COUNTER_0                        _MK_ADDR_CONST(0xfc)
#define PMC_IMPL_EVENT_COUNTER_0_SECURE                         0x0
#define PMC_IMPL_EVENT_COUNTER_0_DUAL                   0x0
#define PMC_IMPL_EVENT_COUNTER_0_SCR                    EVENT_COUNTER_SCR_0
#define PMC_IMPL_EVENT_COUNTER_0_WORD_COUNT                     0x1
#define PMC_IMPL_EVENT_COUNTER_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_EVENT_COUNTER_0_RESET_MASK                     _MK_MASK_CONST(0x1fffff)
#define PMC_IMPL_EVENT_COUNTER_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define PMC_IMPL_EVENT_COUNTER_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_EVENT_COUNTER_0_READ_MASK                      _MK_MASK_CONST(0x1fffff)
#define PMC_IMPL_EVENT_COUNTER_0_WRITE_MASK                     _MK_MASK_CONST(0x1fffff)
#define PMC_IMPL_EVENT_COUNTER_0_COUNT_SHIFT                    _MK_SHIFT_CONST(0)
#define PMC_IMPL_EVENT_COUNTER_0_COUNT_FIELD                    _MK_FIELD_CONST(0xffff, PMC_IMPL_EVENT_COUNTER_0_COUNT_SHIFT)
#define PMC_IMPL_EVENT_COUNTER_0_COUNT_RANGE                    15:0
#define PMC_IMPL_EVENT_COUNTER_0_COUNT_WOFFSET                  0x0
#define PMC_IMPL_EVENT_COUNTER_0_COUNT_DEFAULT                  _MK_MASK_CONST(0x0)
#define PMC_IMPL_EVENT_COUNTER_0_COUNT_DEFAULT_MASK                     _MK_MASK_CONST(0xffff)
#define PMC_IMPL_EVENT_COUNTER_0_COUNT_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define PMC_IMPL_EVENT_COUNTER_0_COUNT_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define PMC_IMPL_EVENT_COUNTER_0_COUNT_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_EVENT_COUNTER_0_COUNT_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)

#define PMC_IMPL_EVENT_COUNTER_0_SEL_SHIFT                      _MK_SHIFT_CONST(16)
#define PMC_IMPL_EVENT_COUNTER_0_SEL_FIELD                      _MK_FIELD_CONST(0xf, PMC_IMPL_EVENT_COUNTER_0_SEL_SHIFT)
#define PMC_IMPL_EVENT_COUNTER_0_SEL_RANGE                      19:16
#define PMC_IMPL_EVENT_COUNTER_0_SEL_WOFFSET                    0x0
#define PMC_IMPL_EVENT_COUNTER_0_SEL_DEFAULT                    _MK_MASK_CONST(0x0)
#define PMC_IMPL_EVENT_COUNTER_0_SEL_DEFAULT_MASK                       _MK_MASK_CONST(0xf)
#define PMC_IMPL_EVENT_COUNTER_0_SEL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define PMC_IMPL_EVENT_COUNTER_0_SEL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define PMC_IMPL_EVENT_COUNTER_0_SEL_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define PMC_IMPL_EVENT_COUNTER_0_SEL_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define PMC_IMPL_EVENT_COUNTER_0_SEL_OFF                        _MK_ENUM_CONST(0)
#define PMC_IMPL_EVENT_COUNTER_0_SEL_ON                 _MK_ENUM_CONST(1)

#define PMC_IMPL_EVENT_COUNTER_0_EN_SHIFT                       _MK_SHIFT_CONST(20)
#define PMC_IMPL_EVENT_COUNTER_0_EN_FIELD                       _MK_FIELD_CONST(0x1, PMC_IMPL_EVENT_COUNTER_0_EN_SHIFT)
#define PMC_IMPL_EVENT_COUNTER_0_EN_RANGE                       20:20
#define PMC_IMPL_EVENT_COUNTER_0_EN_WOFFSET                     0x0
#define PMC_IMPL_EVENT_COUNTER_0_EN_DEFAULT                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_EVENT_COUNTER_0_EN_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define PMC_IMPL_EVENT_COUNTER_0_EN_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define PMC_IMPL_EVENT_COUNTER_0_EN_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_EVENT_COUNTER_0_EN_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_EVENT_COUNTER_0_EN_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define PMC_IMPL_EVENT_COUNTER_0_EN_OFF                 _MK_ENUM_CONST(0)
#define PMC_IMPL_EVENT_COUNTER_0_EN_ON                  _MK_ENUM_CONST(1)


// Reserved address 0x100

// Register PMC_IMPL_DIRECT_THERMTRIP_CFG_0
#define PMC_IMPL_DIRECT_THERMTRIP_CFG_0                 _MK_ADDR_CONST(0x104)
#define PMC_IMPL_DIRECT_THERMTRIP_CFG_0_SECURE                  0x0
#define PMC_IMPL_DIRECT_THERMTRIP_CFG_0_DUAL                    0x0
#define PMC_IMPL_DIRECT_THERMTRIP_CFG_0_SCR                     DIRECT_THERMTRIP_CFG_SCR_0
#define PMC_IMPL_DIRECT_THERMTRIP_CFG_0_WORD_COUNT                      0x1
#define PMC_IMPL_DIRECT_THERMTRIP_CFG_0_RESET_VAL                       _MK_MASK_CONST(0x10)
#define PMC_IMPL_DIRECT_THERMTRIP_CFG_0_RESET_MASK                      _MK_MASK_CONST(0x3f)
#define PMC_IMPL_DIRECT_THERMTRIP_CFG_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define PMC_IMPL_DIRECT_THERMTRIP_CFG_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define PMC_IMPL_DIRECT_THERMTRIP_CFG_0_READ_MASK                       _MK_MASK_CONST(0x3f)
#define PMC_IMPL_DIRECT_THERMTRIP_CFG_0_WRITE_MASK                      _MK_MASK_CONST(0x3f)
#define PMC_IMPL_DIRECT_THERMTRIP_CFG_0_THERMTRIP_LOCK_SHIFT                    _MK_SHIFT_CONST(5)
#define PMC_IMPL_DIRECT_THERMTRIP_CFG_0_THERMTRIP_LOCK_FIELD                    _MK_FIELD_CONST(0x1, PMC_IMPL_DIRECT_THERMTRIP_CFG_0_THERMTRIP_LOCK_SHIFT)
#define PMC_IMPL_DIRECT_THERMTRIP_CFG_0_THERMTRIP_LOCK_RANGE                    5:5
#define PMC_IMPL_DIRECT_THERMTRIP_CFG_0_THERMTRIP_LOCK_WOFFSET                  0x0
#define PMC_IMPL_DIRECT_THERMTRIP_CFG_0_THERMTRIP_LOCK_DEFAULT                  _MK_MASK_CONST(0x0)
#define PMC_IMPL_DIRECT_THERMTRIP_CFG_0_THERMTRIP_LOCK_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define PMC_IMPL_DIRECT_THERMTRIP_CFG_0_THERMTRIP_LOCK_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define PMC_IMPL_DIRECT_THERMTRIP_CFG_0_THERMTRIP_LOCK_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define PMC_IMPL_DIRECT_THERMTRIP_CFG_0_THERMTRIP_LOCK_PARITY_PROTECTION                        _MK_MASK_CONST(0x1)
#define PMC_IMPL_DIRECT_THERMTRIP_CFG_0_THERMTRIP_LOCK_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)
#define PMC_IMPL_DIRECT_THERMTRIP_CFG_0_THERMTRIP_LOCK_DISABLE                  _MK_ENUM_CONST(0)
#define PMC_IMPL_DIRECT_THERMTRIP_CFG_0_THERMTRIP_LOCK_ENABLE                   _MK_ENUM_CONST(1)

#define PMC_IMPL_DIRECT_THERMTRIP_CFG_0_THERMTRIP_EN_SHIFT                      _MK_SHIFT_CONST(4)
#define PMC_IMPL_DIRECT_THERMTRIP_CFG_0_THERMTRIP_EN_FIELD                      _MK_FIELD_CONST(0x1, PMC_IMPL_DIRECT_THERMTRIP_CFG_0_THERMTRIP_EN_SHIFT)
#define PMC_IMPL_DIRECT_THERMTRIP_CFG_0_THERMTRIP_EN_RANGE                      4:4
#define PMC_IMPL_DIRECT_THERMTRIP_CFG_0_THERMTRIP_EN_WOFFSET                    0x0
#define PMC_IMPL_DIRECT_THERMTRIP_CFG_0_THERMTRIP_EN_DEFAULT                    _MK_MASK_CONST(0x1)
#define PMC_IMPL_DIRECT_THERMTRIP_CFG_0_THERMTRIP_EN_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define PMC_IMPL_DIRECT_THERMTRIP_CFG_0_THERMTRIP_EN_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define PMC_IMPL_DIRECT_THERMTRIP_CFG_0_THERMTRIP_EN_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define PMC_IMPL_DIRECT_THERMTRIP_CFG_0_THERMTRIP_EN_PARITY_PROTECTION                  _MK_MASK_CONST(0x1)
#define PMC_IMPL_DIRECT_THERMTRIP_CFG_0_THERMTRIP_EN_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define PMC_IMPL_DIRECT_THERMTRIP_CFG_0_THERMTRIP_EN_DISABLE                    _MK_ENUM_CONST(0)
#define PMC_IMPL_DIRECT_THERMTRIP_CFG_0_THERMTRIP_EN_ENABLE                     _MK_ENUM_CONST(1)

#define PMC_IMPL_DIRECT_THERMTRIP_CFG_0_SHDN_ASSERT_PULSE_WIDTH_SHIFT                   _MK_SHIFT_CONST(0)
#define PMC_IMPL_DIRECT_THERMTRIP_CFG_0_SHDN_ASSERT_PULSE_WIDTH_FIELD                   _MK_FIELD_CONST(0xf, PMC_IMPL_DIRECT_THERMTRIP_CFG_0_SHDN_ASSERT_PULSE_WIDTH_SHIFT)
#define PMC_IMPL_DIRECT_THERMTRIP_CFG_0_SHDN_ASSERT_PULSE_WIDTH_RANGE                   3:0
#define PMC_IMPL_DIRECT_THERMTRIP_CFG_0_SHDN_ASSERT_PULSE_WIDTH_WOFFSET                 0x0
#define PMC_IMPL_DIRECT_THERMTRIP_CFG_0_SHDN_ASSERT_PULSE_WIDTH_DEFAULT                 _MK_MASK_CONST(0x0)
#define PMC_IMPL_DIRECT_THERMTRIP_CFG_0_SHDN_ASSERT_PULSE_WIDTH_DEFAULT_MASK                    _MK_MASK_CONST(0xf)
#define PMC_IMPL_DIRECT_THERMTRIP_CFG_0_SHDN_ASSERT_PULSE_WIDTH_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_DIRECT_THERMTRIP_CFG_0_SHDN_ASSERT_PULSE_WIDTH_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define PMC_IMPL_DIRECT_THERMTRIP_CFG_0_SHDN_ASSERT_PULSE_WIDTH_PARITY_PROTECTION                       _MK_MASK_CONST(0x1)
#define PMC_IMPL_DIRECT_THERMTRIP_CFG_0_SHDN_ASSERT_PULSE_WIDTH_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)


// Reserved address 0x108

// Register PMC_IMPL_RAMDUMP_CTL_STATUS_0
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0                   _MK_ADDR_CONST(0x10c)
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_SECURE                    0x0
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_DUAL                      0x0
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_SCR                       RAMDUMP_COM_SCR_0
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_WORD_COUNT                        0x1
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_RESET_VAL                         _MK_MASK_CONST(0x0)
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_RESET_MASK                        _MK_MASK_CONST(0xf1c7e403)
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_READ_MASK                         _MK_MASK_CONST(0xf1c7e4ff)
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_WRITE_MASK                        _MK_MASK_CONST(0x11c7e403)
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_RAMDUMP_CSTATE_SHIFT                      _MK_SHIFT_CONST(29)
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_RAMDUMP_CSTATE_FIELD                      _MK_FIELD_CONST(0x7, PMC_IMPL_RAMDUMP_CTL_STATUS_0_RAMDUMP_CSTATE_SHIFT)
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_RAMDUMP_CSTATE_RANGE                      31:29
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_RAMDUMP_CSTATE_WOFFSET                    0x0
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_RAMDUMP_CSTATE_DEFAULT                    _MK_MASK_CONST(0x0)
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_RAMDUMP_CSTATE_DEFAULT_MASK                       _MK_MASK_CONST(0x7)
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_RAMDUMP_CSTATE_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_RAMDUMP_CSTATE_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_RAMDUMP_CSTATE_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_RAMDUMP_CSTATE_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_RAMDUMP_CSTATE_INIT_ENUM                  IDLE
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_RAMDUMP_CSTATE_IDLE                       _MK_ENUM_CONST(0)
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_RAMDUMP_CSTATE_CACHEFLUSH                 _MK_ENUM_CONST(1)
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_RAMDUMP_CSTATE_WAIT                       _MK_ENUM_CONST(2)
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_RAMDUMP_CSTATE_DRAM_SELF_REFRESH                  _MK_ENUM_CONST(3)
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_RAMDUMP_CSTATE_DEBUG_RESET_ACK                    _MK_ENUM_CONST(4)
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_RAMDUMP_CSTATE_WAIT_FOR_SW_ACK                    _MK_ENUM_CONST(5)

#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_HALT_IN_FIQ_SHIFT                 _MK_SHIFT_CONST(28)
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_HALT_IN_FIQ_FIELD                 _MK_FIELD_CONST(0x1, PMC_IMPL_RAMDUMP_CTL_STATUS_0_HALT_IN_FIQ_SHIFT)
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_HALT_IN_FIQ_RANGE                 28:28
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_HALT_IN_FIQ_WOFFSET                       0x0
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_HALT_IN_FIQ_DEFAULT                       _MK_MASK_CONST(0x0)
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_HALT_IN_FIQ_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_HALT_IN_FIQ_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_HALT_IN_FIQ_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_HALT_IN_FIQ_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_HALT_IN_FIQ_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)

#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_RCE_FIQ_EXITED_GRACEFULLY_SHIFT                   _MK_SHIFT_CONST(24)
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_RCE_FIQ_EXITED_GRACEFULLY_FIELD                   _MK_FIELD_CONST(0x1, PMC_IMPL_RAMDUMP_CTL_STATUS_0_RCE_FIQ_EXITED_GRACEFULLY_SHIFT)
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_RCE_FIQ_EXITED_GRACEFULLY_RANGE                   24:24
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_RCE_FIQ_EXITED_GRACEFULLY_WOFFSET                 0x0
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_RCE_FIQ_EXITED_GRACEFULLY_DEFAULT                 _MK_MASK_CONST(0x0)
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_RCE_FIQ_EXITED_GRACEFULLY_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_RCE_FIQ_EXITED_GRACEFULLY_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_RCE_FIQ_EXITED_GRACEFULLY_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_RCE_FIQ_EXITED_GRACEFULLY_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_RCE_FIQ_EXITED_GRACEFULLY_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_RAMDUMP_2ND_BOOT_COMPLETE_SHIFT                   _MK_SHIFT_CONST(23)
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_RAMDUMP_2ND_BOOT_COMPLETE_FIELD                   _MK_FIELD_CONST(0x1, PMC_IMPL_RAMDUMP_CTL_STATUS_0_RAMDUMP_2ND_BOOT_COMPLETE_SHIFT)
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_RAMDUMP_2ND_BOOT_COMPLETE_RANGE                   23:23
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_RAMDUMP_2ND_BOOT_COMPLETE_WOFFSET                 0x0
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_RAMDUMP_2ND_BOOT_COMPLETE_DEFAULT                 _MK_MASK_CONST(0x0)
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_RAMDUMP_2ND_BOOT_COMPLETE_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_RAMDUMP_2ND_BOOT_COMPLETE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_RAMDUMP_2ND_BOOT_COMPLETE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_RAMDUMP_2ND_BOOT_COMPLETE_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_RAMDUMP_2ND_BOOT_COMPLETE_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_CCPLEX_REMOTE_EXITED_GRACEFULLY_SHIFT                     _MK_SHIFT_CONST(22)
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_CCPLEX_REMOTE_EXITED_GRACEFULLY_FIELD                     _MK_FIELD_CONST(0x1, PMC_IMPL_RAMDUMP_CTL_STATUS_0_CCPLEX_REMOTE_EXITED_GRACEFULLY_SHIFT)
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_CCPLEX_REMOTE_EXITED_GRACEFULLY_RANGE                     22:22
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_CCPLEX_REMOTE_EXITED_GRACEFULLY_WOFFSET                   0x0
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_CCPLEX_REMOTE_EXITED_GRACEFULLY_DEFAULT                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_CCPLEX_REMOTE_EXITED_GRACEFULLY_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_CCPLEX_REMOTE_EXITED_GRACEFULLY_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_CCPLEX_REMOTE_EXITED_GRACEFULLY_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_CCPLEX_REMOTE_EXITED_GRACEFULLY_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_CCPLEX_REMOTE_EXITED_GRACEFULLY_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)

#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_SCE_FIQ_EXITED_GRACEFULLY_SHIFT                   _MK_SHIFT_CONST(18)
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_SCE_FIQ_EXITED_GRACEFULLY_FIELD                   _MK_FIELD_CONST(0x1, PMC_IMPL_RAMDUMP_CTL_STATUS_0_SCE_FIQ_EXITED_GRACEFULLY_SHIFT)
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_SCE_FIQ_EXITED_GRACEFULLY_RANGE                   18:18
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_SCE_FIQ_EXITED_GRACEFULLY_WOFFSET                 0x0
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_SCE_FIQ_EXITED_GRACEFULLY_DEFAULT                 _MK_MASK_CONST(0x0)
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_SCE_FIQ_EXITED_GRACEFULLY_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_SCE_FIQ_EXITED_GRACEFULLY_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_SCE_FIQ_EXITED_GRACEFULLY_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_SCE_FIQ_EXITED_GRACEFULLY_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_SCE_FIQ_EXITED_GRACEFULLY_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_APE_FIQ_EXITED_GRACEFULLY_SHIFT                   _MK_SHIFT_CONST(17)
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_APE_FIQ_EXITED_GRACEFULLY_FIELD                   _MK_FIELD_CONST(0x1, PMC_IMPL_RAMDUMP_CTL_STATUS_0_APE_FIQ_EXITED_GRACEFULLY_SHIFT)
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_APE_FIQ_EXITED_GRACEFULLY_RANGE                   17:17
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_APE_FIQ_EXITED_GRACEFULLY_WOFFSET                 0x0
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_APE_FIQ_EXITED_GRACEFULLY_DEFAULT                 _MK_MASK_CONST(0x0)
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_APE_FIQ_EXITED_GRACEFULLY_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_APE_FIQ_EXITED_GRACEFULLY_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_APE_FIQ_EXITED_GRACEFULLY_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_APE_FIQ_EXITED_GRACEFULLY_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_APE_FIQ_EXITED_GRACEFULLY_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_SPE_FIQ_EXITED_GRACEFULLY_SHIFT                   _MK_SHIFT_CONST(16)
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_SPE_FIQ_EXITED_GRACEFULLY_FIELD                   _MK_FIELD_CONST(0x1, PMC_IMPL_RAMDUMP_CTL_STATUS_0_SPE_FIQ_EXITED_GRACEFULLY_SHIFT)
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_SPE_FIQ_EXITED_GRACEFULLY_RANGE                   16:16
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_SPE_FIQ_EXITED_GRACEFULLY_WOFFSET                 0x0
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_SPE_FIQ_EXITED_GRACEFULLY_DEFAULT                 _MK_MASK_CONST(0x0)
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_SPE_FIQ_EXITED_GRACEFULLY_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_SPE_FIQ_EXITED_GRACEFULLY_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_SPE_FIQ_EXITED_GRACEFULLY_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_SPE_FIQ_EXITED_GRACEFULLY_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_SPE_FIQ_EXITED_GRACEFULLY_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_BPMP_FIQ_EXITED_GRACEFULLY_SHIFT                  _MK_SHIFT_CONST(15)
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_BPMP_FIQ_EXITED_GRACEFULLY_FIELD                  _MK_FIELD_CONST(0x1, PMC_IMPL_RAMDUMP_CTL_STATUS_0_BPMP_FIQ_EXITED_GRACEFULLY_SHIFT)
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_BPMP_FIQ_EXITED_GRACEFULLY_RANGE                  15:15
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_BPMP_FIQ_EXITED_GRACEFULLY_WOFFSET                        0x0
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_BPMP_FIQ_EXITED_GRACEFULLY_DEFAULT                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_BPMP_FIQ_EXITED_GRACEFULLY_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_BPMP_FIQ_EXITED_GRACEFULLY_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_BPMP_FIQ_EXITED_GRACEFULLY_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_BPMP_FIQ_EXITED_GRACEFULLY_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_BPMP_FIQ_EXITED_GRACEFULLY_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)

#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_CCPLEX_CLUSTER1_FIQ_EXITED_GRACEFULLY_SHIFT                       _MK_SHIFT_CONST(14)
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_CCPLEX_CLUSTER1_FIQ_EXITED_GRACEFULLY_FIELD                       _MK_FIELD_CONST(0x1, PMC_IMPL_RAMDUMP_CTL_STATUS_0_CCPLEX_CLUSTER1_FIQ_EXITED_GRACEFULLY_SHIFT)
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_CCPLEX_CLUSTER1_FIQ_EXITED_GRACEFULLY_RANGE                       14:14
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_CCPLEX_CLUSTER1_FIQ_EXITED_GRACEFULLY_WOFFSET                     0x0
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_CCPLEX_CLUSTER1_FIQ_EXITED_GRACEFULLY_DEFAULT                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_CCPLEX_CLUSTER1_FIQ_EXITED_GRACEFULLY_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_CCPLEX_CLUSTER1_FIQ_EXITED_GRACEFULLY_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_CCPLEX_CLUSTER1_FIQ_EXITED_GRACEFULLY_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_CCPLEX_CLUSTER1_FIQ_EXITED_GRACEFULLY_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_CCPLEX_CLUSTER1_FIQ_EXITED_GRACEFULLY_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_CCPLEX_CLUSTER0_FIQ_EXITED_GRACEFULLY_SHIFT                       _MK_SHIFT_CONST(13)
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_CCPLEX_CLUSTER0_FIQ_EXITED_GRACEFULLY_FIELD                       _MK_FIELD_CONST(0x1, PMC_IMPL_RAMDUMP_CTL_STATUS_0_CCPLEX_CLUSTER0_FIQ_EXITED_GRACEFULLY_SHIFT)
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_CCPLEX_CLUSTER0_FIQ_EXITED_GRACEFULLY_RANGE                       13:13
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_CCPLEX_CLUSTER0_FIQ_EXITED_GRACEFULLY_WOFFSET                     0x0
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_CCPLEX_CLUSTER0_FIQ_EXITED_GRACEFULLY_DEFAULT                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_CCPLEX_CLUSTER0_FIQ_EXITED_GRACEFULLY_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_CCPLEX_CLUSTER0_FIQ_EXITED_GRACEFULLY_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_CCPLEX_CLUSTER0_FIQ_EXITED_GRACEFULLY_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_CCPLEX_CLUSTER0_FIQ_EXITED_GRACEFULLY_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_CCPLEX_CLUSTER0_FIQ_EXITED_GRACEFULLY_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_RAMDUMP_STATUS_6_SHIFT                    _MK_SHIFT_CONST(10)
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_RAMDUMP_STATUS_6_FIELD                    _MK_FIELD_CONST(0x1, PMC_IMPL_RAMDUMP_CTL_STATUS_0_RAMDUMP_STATUS_6_SHIFT)
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_RAMDUMP_STATUS_6_RANGE                    10:10
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_RAMDUMP_STATUS_6_WOFFSET                  0x0
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_RAMDUMP_STATUS_6_DEFAULT                  _MK_MASK_CONST(0x0)
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_RAMDUMP_STATUS_6_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_RAMDUMP_STATUS_6_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_RAMDUMP_STATUS_6_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_RAMDUMP_STATUS_6_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_RAMDUMP_STATUS_6_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)

#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_DRAM_SELF_REFRESH_REQUEST_TIMEOUT_SHIFT                   _MK_SHIFT_CONST(7)
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_DRAM_SELF_REFRESH_REQUEST_TIMEOUT_FIELD                   _MK_FIELD_CONST(0x1, PMC_IMPL_RAMDUMP_CTL_STATUS_0_DRAM_SELF_REFRESH_REQUEST_TIMEOUT_SHIFT)
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_DRAM_SELF_REFRESH_REQUEST_TIMEOUT_RANGE                   7:7
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_DRAM_SELF_REFRESH_REQUEST_TIMEOUT_WOFFSET                 0x0
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_DRAM_SELF_REFRESH_REQUEST_TIMEOUT_DEFAULT                 _MK_MASK_CONST(0x0)
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_DRAM_SELF_REFRESH_REQUEST_TIMEOUT_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_DRAM_SELF_REFRESH_REQUEST_TIMEOUT_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_DRAM_SELF_REFRESH_REQUEST_TIMEOUT_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_DRAM_SELF_REFRESH_REQUEST_TIMEOUT_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_DRAM_SELF_REFRESH_REQUEST_TIMEOUT_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_DRAM_IN_SELF_REFRESH_SHIFT                        _MK_SHIFT_CONST(6)
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_DRAM_IN_SELF_REFRESH_FIELD                        _MK_FIELD_CONST(0x1, PMC_IMPL_RAMDUMP_CTL_STATUS_0_DRAM_IN_SELF_REFRESH_SHIFT)
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_DRAM_IN_SELF_REFRESH_RANGE                        6:6
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_DRAM_IN_SELF_REFRESH_WOFFSET                      0x0
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_DRAM_IN_SELF_REFRESH_DEFAULT                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_DRAM_IN_SELF_REFRESH_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_DRAM_IN_SELF_REFRESH_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_DRAM_IN_SELF_REFRESH_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_DRAM_IN_SELF_REFRESH_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_DRAM_IN_SELF_REFRESH_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_CCPLEX_CACHEFLUSH_REQUEST_TIMEOUT_SHIFT                   _MK_SHIFT_CONST(5)
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_CCPLEX_CACHEFLUSH_REQUEST_TIMEOUT_FIELD                   _MK_FIELD_CONST(0x1, PMC_IMPL_RAMDUMP_CTL_STATUS_0_CCPLEX_CACHEFLUSH_REQUEST_TIMEOUT_SHIFT)
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_CCPLEX_CACHEFLUSH_REQUEST_TIMEOUT_RANGE                   5:5
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_CCPLEX_CACHEFLUSH_REQUEST_TIMEOUT_WOFFSET                 0x0
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_CCPLEX_CACHEFLUSH_REQUEST_TIMEOUT_DEFAULT                 _MK_MASK_CONST(0x0)
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_CCPLEX_CACHEFLUSH_REQUEST_TIMEOUT_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_CCPLEX_CACHEFLUSH_REQUEST_TIMEOUT_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_CCPLEX_CACHEFLUSH_REQUEST_TIMEOUT_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_CCPLEX_CACHEFLUSH_REQUEST_TIMEOUT_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_CCPLEX_CACHEFLUSH_REQUEST_TIMEOUT_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_CCPLEX_CACHEFLUSH_DONE_SHIFT                      _MK_SHIFT_CONST(4)
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_CCPLEX_CACHEFLUSH_DONE_FIELD                      _MK_FIELD_CONST(0x1, PMC_IMPL_RAMDUMP_CTL_STATUS_0_CCPLEX_CACHEFLUSH_DONE_SHIFT)
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_CCPLEX_CACHEFLUSH_DONE_RANGE                      4:4
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_CCPLEX_CACHEFLUSH_DONE_WOFFSET                    0x0
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_CCPLEX_CACHEFLUSH_DONE_DEFAULT                    _MK_MASK_CONST(0x0)
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_CCPLEX_CACHEFLUSH_DONE_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_CCPLEX_CACHEFLUSH_DONE_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_CCPLEX_CACHEFLUSH_DONE_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_CCPLEX_CACHEFLUSH_DONE_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_CCPLEX_CACHEFLUSH_DONE_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)

#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_WDT_DFD_RST_ACK_SHIFT                     _MK_SHIFT_CONST(3)
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_WDT_DFD_RST_ACK_FIELD                     _MK_FIELD_CONST(0x1, PMC_IMPL_RAMDUMP_CTL_STATUS_0_WDT_DFD_RST_ACK_SHIFT)
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_WDT_DFD_RST_ACK_RANGE                     3:3
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_WDT_DFD_RST_ACK_WOFFSET                   0x0
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_WDT_DFD_RST_ACK_DEFAULT                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_WDT_DFD_RST_ACK_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_WDT_DFD_RST_ACK_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_WDT_DFD_RST_ACK_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_WDT_DFD_RST_ACK_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_WDT_DFD_RST_ACK_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)

#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_WDT_DFD_RST_REQ_SHIFT                     _MK_SHIFT_CONST(2)
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_WDT_DFD_RST_REQ_FIELD                     _MK_FIELD_CONST(0x1, PMC_IMPL_RAMDUMP_CTL_STATUS_0_WDT_DFD_RST_REQ_SHIFT)
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_WDT_DFD_RST_REQ_RANGE                     2:2
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_WDT_DFD_RST_REQ_WOFFSET                   0x0
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_WDT_DFD_RST_REQ_DEFAULT                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_WDT_DFD_RST_REQ_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_WDT_DFD_RST_REQ_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_WDT_DFD_RST_REQ_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_WDT_DFD_RST_REQ_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_WDT_DFD_RST_REQ_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)

#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_CCPLEX_CACHE_RSTDISABLE_SHIFT                     _MK_SHIFT_CONST(1)
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_CCPLEX_CACHE_RSTDISABLE_FIELD                     _MK_FIELD_CONST(0x1, PMC_IMPL_RAMDUMP_CTL_STATUS_0_CCPLEX_CACHE_RSTDISABLE_SHIFT)
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_CCPLEX_CACHE_RSTDISABLE_RANGE                     1:1
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_CCPLEX_CACHE_RSTDISABLE_WOFFSET                   0x0
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_CCPLEX_CACHE_RSTDISABLE_DEFAULT                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_CCPLEX_CACHE_RSTDISABLE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_CCPLEX_CACHE_RSTDISABLE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_CCPLEX_CACHE_RSTDISABLE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_CCPLEX_CACHE_RSTDISABLE_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_CCPLEX_CACHE_RSTDISABLE_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)

#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_RAMDUMP_EN_SHIFT                  _MK_SHIFT_CONST(0)
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_RAMDUMP_EN_FIELD                  _MK_FIELD_CONST(0x1, PMC_IMPL_RAMDUMP_CTL_STATUS_0_RAMDUMP_EN_SHIFT)
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_RAMDUMP_EN_RANGE                  0:0
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_RAMDUMP_EN_WOFFSET                        0x0
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_RAMDUMP_EN_DEFAULT                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_RAMDUMP_EN_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_RAMDUMP_EN_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_RAMDUMP_EN_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_RAMDUMP_EN_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_RAMDUMP_EN_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)


// Register PMC_IMPL_RAMDUMP_TIMEOUT_0
#define PMC_IMPL_RAMDUMP_TIMEOUT_0                      _MK_ADDR_CONST(0x110)
#define PMC_IMPL_RAMDUMP_TIMEOUT_0_SECURE                       0x0
#define PMC_IMPL_RAMDUMP_TIMEOUT_0_DUAL                         0x0
#define PMC_IMPL_RAMDUMP_TIMEOUT_0_SCR                  RAMDUMP_TIMEOUT_SCR_0
#define PMC_IMPL_RAMDUMP_TIMEOUT_0_WORD_COUNT                   0x1
#define PMC_IMPL_RAMDUMP_TIMEOUT_0_RESET_VAL                    _MK_MASK_CONST(0x7d00)
#define PMC_IMPL_RAMDUMP_TIMEOUT_0_RESET_MASK                   _MK_MASK_CONST(0xffffffff)
#define PMC_IMPL_RAMDUMP_TIMEOUT_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define PMC_IMPL_RAMDUMP_TIMEOUT_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_RAMDUMP_TIMEOUT_0_READ_MASK                    _MK_MASK_CONST(0xffffffff)
#define PMC_IMPL_RAMDUMP_TIMEOUT_0_WRITE_MASK                   _MK_MASK_CONST(0xffffffff)
#define PMC_IMPL_RAMDUMP_TIMEOUT_0_RAMDUMP_TIMEOUT_SHIFT                        _MK_SHIFT_CONST(0)
#define PMC_IMPL_RAMDUMP_TIMEOUT_0_RAMDUMP_TIMEOUT_FIELD                        _MK_FIELD_CONST(0xffffffff, PMC_IMPL_RAMDUMP_TIMEOUT_0_RAMDUMP_TIMEOUT_SHIFT)
#define PMC_IMPL_RAMDUMP_TIMEOUT_0_RAMDUMP_TIMEOUT_RANGE                        31:0
#define PMC_IMPL_RAMDUMP_TIMEOUT_0_RAMDUMP_TIMEOUT_WOFFSET                      0x0
#define PMC_IMPL_RAMDUMP_TIMEOUT_0_RAMDUMP_TIMEOUT_DEFAULT                      _MK_MASK_CONST(0x7d00)
#define PMC_IMPL_RAMDUMP_TIMEOUT_0_RAMDUMP_TIMEOUT_DEFAULT_MASK                 _MK_MASK_CONST(0xffffffff)
#define PMC_IMPL_RAMDUMP_TIMEOUT_0_RAMDUMP_TIMEOUT_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_RAMDUMP_TIMEOUT_0_RAMDUMP_TIMEOUT_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_RAMDUMP_TIMEOUT_0_RAMDUMP_TIMEOUT_PARITY_PROTECTION                    _MK_MASK_CONST(0x1)
#define PMC_IMPL_RAMDUMP_TIMEOUT_0_RAMDUMP_TIMEOUT_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)


// Register PMC_IMPL_RST_REQ_CONFIG_0
#define PMC_IMPL_RST_REQ_CONFIG_0                       _MK_ADDR_CONST(0x114)
#define PMC_IMPL_RST_REQ_CONFIG_0_SECURE                        0x0
#define PMC_IMPL_RST_REQ_CONFIG_0_DUAL                  0x0
#define PMC_IMPL_RST_REQ_CONFIG_0_SCR                   CNTRL_SCR_0
#define PMC_IMPL_RST_REQ_CONFIG_0_WORD_COUNT                    0x1
#define PMC_IMPL_RST_REQ_CONFIG_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_RST_REQ_CONFIG_0_RESET_MASK                    _MK_MASK_CONST(0xb)
#define PMC_IMPL_RST_REQ_CONFIG_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_RST_REQ_CONFIG_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define PMC_IMPL_RST_REQ_CONFIG_0_READ_MASK                     _MK_MASK_CONST(0xb)
#define PMC_IMPL_RST_REQ_CONFIG_0_WRITE_MASK                    _MK_MASK_CONST(0xb)
#define PMC_IMPL_RST_REQ_CONFIG_0_L1BWDTRST_WDT_OUT_RST_EN_SHIFT                        _MK_SHIFT_CONST(0)
#define PMC_IMPL_RST_REQ_CONFIG_0_L1BWDTRST_WDT_OUT_RST_EN_FIELD                        _MK_FIELD_CONST(0x1, PMC_IMPL_RST_REQ_CONFIG_0_L1BWDTRST_WDT_OUT_RST_EN_SHIFT)
#define PMC_IMPL_RST_REQ_CONFIG_0_L1BWDTRST_WDT_OUT_RST_EN_RANGE                        0:0
#define PMC_IMPL_RST_REQ_CONFIG_0_L1BWDTRST_WDT_OUT_RST_EN_WOFFSET                      0x0
#define PMC_IMPL_RST_REQ_CONFIG_0_L1BWDTRST_WDT_OUT_RST_EN_DEFAULT                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_RST_REQ_CONFIG_0_L1BWDTRST_WDT_OUT_RST_EN_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define PMC_IMPL_RST_REQ_CONFIG_0_L1BWDTRST_WDT_OUT_RST_EN_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_RST_REQ_CONFIG_0_L1BWDTRST_WDT_OUT_RST_EN_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_RST_REQ_CONFIG_0_L1BWDTRST_WDT_OUT_RST_EN_PARITY_PROTECTION                    _MK_MASK_CONST(0x1)
#define PMC_IMPL_RST_REQ_CONFIG_0_L1BWDTRST_WDT_OUT_RST_EN_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)
#define PMC_IMPL_RST_REQ_CONFIG_0_L1BWDTRST_WDT_OUT_RST_EN_INIT_ENUM                    DISABLE
#define PMC_IMPL_RST_REQ_CONFIG_0_L1BWDTRST_WDT_OUT_RST_EN_DISABLE                      _MK_ENUM_CONST(0)
#define PMC_IMPL_RST_REQ_CONFIG_0_L1BWDTRST_WDT_OUT_RST_EN_ENABLE                       _MK_ENUM_CONST(1)

#define PMC_IMPL_RST_REQ_CONFIG_0_L1BAOWDTRST_WDT_OUT_RST_EN_SHIFT                      _MK_SHIFT_CONST(1)
#define PMC_IMPL_RST_REQ_CONFIG_0_L1BAOWDTRST_WDT_OUT_RST_EN_FIELD                      _MK_FIELD_CONST(0x1, PMC_IMPL_RST_REQ_CONFIG_0_L1BAOWDTRST_WDT_OUT_RST_EN_SHIFT)
#define PMC_IMPL_RST_REQ_CONFIG_0_L1BAOWDTRST_WDT_OUT_RST_EN_RANGE                      1:1
#define PMC_IMPL_RST_REQ_CONFIG_0_L1BAOWDTRST_WDT_OUT_RST_EN_WOFFSET                    0x0
#define PMC_IMPL_RST_REQ_CONFIG_0_L1BAOWDTRST_WDT_OUT_RST_EN_DEFAULT                    _MK_MASK_CONST(0x0)
#define PMC_IMPL_RST_REQ_CONFIG_0_L1BAOWDTRST_WDT_OUT_RST_EN_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define PMC_IMPL_RST_REQ_CONFIG_0_L1BAOWDTRST_WDT_OUT_RST_EN_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define PMC_IMPL_RST_REQ_CONFIG_0_L1BAOWDTRST_WDT_OUT_RST_EN_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define PMC_IMPL_RST_REQ_CONFIG_0_L1BAOWDTRST_WDT_OUT_RST_EN_PARITY_PROTECTION                  _MK_MASK_CONST(0x1)
#define PMC_IMPL_RST_REQ_CONFIG_0_L1BAOWDTRST_WDT_OUT_RST_EN_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define PMC_IMPL_RST_REQ_CONFIG_0_L1BAOWDTRST_WDT_OUT_RST_EN_INIT_ENUM                  DISABLE
#define PMC_IMPL_RST_REQ_CONFIG_0_L1BAOWDTRST_WDT_OUT_RST_EN_DISABLE                    _MK_ENUM_CONST(0)
#define PMC_IMPL_RST_REQ_CONFIG_0_L1BAOWDTRST_WDT_OUT_RST_EN_ENABLE                     _MK_ENUM_CONST(1)

#define PMC_IMPL_RST_REQ_CONFIG_0_L1CRST_WDT_OUT_RST_EN_SHIFT                   _MK_SHIFT_CONST(3)
#define PMC_IMPL_RST_REQ_CONFIG_0_L1CRST_WDT_OUT_RST_EN_FIELD                   _MK_FIELD_CONST(0x1, PMC_IMPL_RST_REQ_CONFIG_0_L1CRST_WDT_OUT_RST_EN_SHIFT)
#define PMC_IMPL_RST_REQ_CONFIG_0_L1CRST_WDT_OUT_RST_EN_RANGE                   3:3
#define PMC_IMPL_RST_REQ_CONFIG_0_L1CRST_WDT_OUT_RST_EN_WOFFSET                 0x0
#define PMC_IMPL_RST_REQ_CONFIG_0_L1CRST_WDT_OUT_RST_EN_DEFAULT                 _MK_MASK_CONST(0x0)
#define PMC_IMPL_RST_REQ_CONFIG_0_L1CRST_WDT_OUT_RST_EN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define PMC_IMPL_RST_REQ_CONFIG_0_L1CRST_WDT_OUT_RST_EN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_RST_REQ_CONFIG_0_L1CRST_WDT_OUT_RST_EN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define PMC_IMPL_RST_REQ_CONFIG_0_L1CRST_WDT_OUT_RST_EN_PARITY_PROTECTION                       _MK_MASK_CONST(0x1)
#define PMC_IMPL_RST_REQ_CONFIG_0_L1CRST_WDT_OUT_RST_EN_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define PMC_IMPL_RST_REQ_CONFIG_0_L1CRST_WDT_OUT_RST_EN_INIT_ENUM                       DISABLE
#define PMC_IMPL_RST_REQ_CONFIG_0_L1CRST_WDT_OUT_RST_EN_DISABLE                 _MK_ENUM_CONST(0)
#define PMC_IMPL_RST_REQ_CONFIG_0_L1CRST_WDT_OUT_RST_EN_ENABLE                  _MK_ENUM_CONST(1)


// Register PMC_IMPL_RST_REQ_CNTVAL_0
#define PMC_IMPL_RST_REQ_CNTVAL_0                       _MK_ADDR_CONST(0x118)
#define PMC_IMPL_RST_REQ_CNTVAL_0_SECURE                        0x0
#define PMC_IMPL_RST_REQ_CNTVAL_0_DUAL                  0x0
#define PMC_IMPL_RST_REQ_CNTVAL_0_SCR                   CNTRL_SCR_0
#define PMC_IMPL_RST_REQ_CNTVAL_0_WORD_COUNT                    0x1
#define PMC_IMPL_RST_REQ_CNTVAL_0_RESET_VAL                     _MK_MASK_CONST(0x4000000)
#define PMC_IMPL_RST_REQ_CNTVAL_0_RESET_MASK                    _MK_MASK_CONST(0xffffffff)
#define PMC_IMPL_RST_REQ_CNTVAL_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_RST_REQ_CNTVAL_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define PMC_IMPL_RST_REQ_CNTVAL_0_READ_MASK                     _MK_MASK_CONST(0xffffffff)
#define PMC_IMPL_RST_REQ_CNTVAL_0_WRITE_MASK                    _MK_MASK_CONST(0xffffffff)
#define PMC_IMPL_RST_REQ_CNTVAL_0_L1ARST_SHIFT                  _MK_SHIFT_CONST(0)
#define PMC_IMPL_RST_REQ_CNTVAL_0_L1ARST_FIELD                  _MK_FIELD_CONST(0xff, PMC_IMPL_RST_REQ_CNTVAL_0_L1ARST_SHIFT)
#define PMC_IMPL_RST_REQ_CNTVAL_0_L1ARST_RANGE                  7:0
#define PMC_IMPL_RST_REQ_CNTVAL_0_L1ARST_WOFFSET                        0x0
#define PMC_IMPL_RST_REQ_CNTVAL_0_L1ARST_DEFAULT                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_RST_REQ_CNTVAL_0_L1ARST_DEFAULT_MASK                   _MK_MASK_CONST(0xff)
#define PMC_IMPL_RST_REQ_CNTVAL_0_L1ARST_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_RST_REQ_CNTVAL_0_L1ARST_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_RST_REQ_CNTVAL_0_L1ARST_PARITY_PROTECTION                      _MK_MASK_CONST(0x1)
#define PMC_IMPL_RST_REQ_CNTVAL_0_L1ARST_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)

#define PMC_IMPL_RST_REQ_CNTVAL_0_L1BRST_SHIFT                  _MK_SHIFT_CONST(8)
#define PMC_IMPL_RST_REQ_CNTVAL_0_L1BRST_FIELD                  _MK_FIELD_CONST(0xff, PMC_IMPL_RST_REQ_CNTVAL_0_L1BRST_SHIFT)
#define PMC_IMPL_RST_REQ_CNTVAL_0_L1BRST_RANGE                  15:8
#define PMC_IMPL_RST_REQ_CNTVAL_0_L1BRST_WOFFSET                        0x0
#define PMC_IMPL_RST_REQ_CNTVAL_0_L1BRST_DEFAULT                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_RST_REQ_CNTVAL_0_L1BRST_DEFAULT_MASK                   _MK_MASK_CONST(0xff)
#define PMC_IMPL_RST_REQ_CNTVAL_0_L1BRST_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_RST_REQ_CNTVAL_0_L1BRST_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_RST_REQ_CNTVAL_0_L1BRST_PARITY_PROTECTION                      _MK_MASK_CONST(0x1)
#define PMC_IMPL_RST_REQ_CNTVAL_0_L1BRST_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)

#define PMC_IMPL_RST_REQ_CNTVAL_0_L1CRST_SHIFT                  _MK_SHIFT_CONST(16)
#define PMC_IMPL_RST_REQ_CNTVAL_0_L1CRST_FIELD                  _MK_FIELD_CONST(0xff, PMC_IMPL_RST_REQ_CNTVAL_0_L1CRST_SHIFT)
#define PMC_IMPL_RST_REQ_CNTVAL_0_L1CRST_RANGE                  23:16
#define PMC_IMPL_RST_REQ_CNTVAL_0_L1CRST_WOFFSET                        0x0
#define PMC_IMPL_RST_REQ_CNTVAL_0_L1CRST_DEFAULT                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_RST_REQ_CNTVAL_0_L1CRST_DEFAULT_MASK                   _MK_MASK_CONST(0xff)
#define PMC_IMPL_RST_REQ_CNTVAL_0_L1CRST_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_RST_REQ_CNTVAL_0_L1CRST_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_RST_REQ_CNTVAL_0_L1CRST_PARITY_PROTECTION                      _MK_MASK_CONST(0x1)
#define PMC_IMPL_RST_REQ_CNTVAL_0_L1CRST_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)

#define PMC_IMPL_RST_REQ_CNTVAL_0_L2RST_SHIFT                   _MK_SHIFT_CONST(24)
#define PMC_IMPL_RST_REQ_CNTVAL_0_L2RST_FIELD                   _MK_FIELD_CONST(0xff, PMC_IMPL_RST_REQ_CNTVAL_0_L2RST_SHIFT)
#define PMC_IMPL_RST_REQ_CNTVAL_0_L2RST_RANGE                   31:24
#define PMC_IMPL_RST_REQ_CNTVAL_0_L2RST_WOFFSET                 0x0
#define PMC_IMPL_RST_REQ_CNTVAL_0_L2RST_DEFAULT                 _MK_MASK_CONST(0x4)
#define PMC_IMPL_RST_REQ_CNTVAL_0_L2RST_DEFAULT_MASK                    _MK_MASK_CONST(0xff)
#define PMC_IMPL_RST_REQ_CNTVAL_0_L2RST_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_RST_REQ_CNTVAL_0_L2RST_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define PMC_IMPL_RST_REQ_CNTVAL_0_L2RST_PARITY_PROTECTION                       _MK_MASK_CONST(0x1)
#define PMC_IMPL_RST_REQ_CNTVAL_0_L2RST_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)


// Reserved address 0x11c

// Reserved address 0x120

// Reserved address 0x124

// Reserved address 0x128

// Reserved address 0x12c

// Reserved address 0x130

// Reserved address 0x134

// Reserved address 0x138

// Reserved address 0x13c

// Reserved address 0x140

// Reserved address 0x144

// Reserved address 0x148

// Reserved address 0x14c

// Reserved address 0x150

// Reserved address 0x154

// Reserved address 0x158

// Reserved address 0x15c

// Reserved address 0x160

// Reserved address 0x164

// Reserved address 0x168

// Reserved address 0x16c

// Reserved address 0x170

// Reserved address 0x174

// Reserved address 0x178

// Reserved address 0x17c

// Reserved address 0x180

// Reserved address 0x184

// Reserved address 0x188

// Reserved address 0x18c

// Reserved address 0x190

// Reserved address 0x194

// Reserved address 0x198

// Reserved address 0x19c

// Reserved address 0x1a0

// Reserved address 0x1a4

// Reserved address 0x1a8

// Reserved address 0x1ac

// Reserved address 0x1b0

// Reserved address 0x1b4

// Reserved address 0x1b8

// Reserved address 0x1bc

// Reserved address 0x1c0

// Reserved address 0x1c4

// Reserved address 0x1c8

// Reserved address 0x1cc

// Reserved address 0x1d0

// Register PMC_IMPL_VFMON_ACTION_0
#define PMC_IMPL_VFMON_ACTION_0                 _MK_ADDR_CONST(0x1d4)
#define PMC_IMPL_VFMON_ACTION_0_SECURE                  0x0
#define PMC_IMPL_VFMON_ACTION_0_DUAL                    0x0
#define PMC_IMPL_VFMON_ACTION_0_SCR                     VFMON_CTRL_SCR_0
#define PMC_IMPL_VFMON_ACTION_0_WORD_COUNT                      0x1
#define PMC_IMPL_VFMON_ACTION_0_RESET_VAL                       _MK_MASK_CONST(0x80000005)
#define PMC_IMPL_VFMON_ACTION_0_RESET_MASK                      _MK_MASK_CONST(0x8000ffff)
#define PMC_IMPL_VFMON_ACTION_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define PMC_IMPL_VFMON_ACTION_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define PMC_IMPL_VFMON_ACTION_0_READ_MASK                       _MK_MASK_CONST(0x8000ffff)
#define PMC_IMPL_VFMON_ACTION_0_WRITE_MASK                      _MK_MASK_CONST(0x8000ffff)
#define PMC_IMPL_VFMON_ACTION_0_FOSC_FAULT_ACTION_SHIFT                 _MK_SHIFT_CONST(0)
#define PMC_IMPL_VFMON_ACTION_0_FOSC_FAULT_ACTION_FIELD                 _MK_FIELD_CONST(0x3, PMC_IMPL_VFMON_ACTION_0_FOSC_FAULT_ACTION_SHIFT)
#define PMC_IMPL_VFMON_ACTION_0_FOSC_FAULT_ACTION_RANGE                 1:0
#define PMC_IMPL_VFMON_ACTION_0_FOSC_FAULT_ACTION_WOFFSET                       0x0
#define PMC_IMPL_VFMON_ACTION_0_FOSC_FAULT_ACTION_DEFAULT                       _MK_MASK_CONST(0x1)
#define PMC_IMPL_VFMON_ACTION_0_FOSC_FAULT_ACTION_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
#define PMC_IMPL_VFMON_ACTION_0_FOSC_FAULT_ACTION_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define PMC_IMPL_VFMON_ACTION_0_FOSC_FAULT_ACTION_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define PMC_IMPL_VFMON_ACTION_0_FOSC_FAULT_ACTION_PARITY_PROTECTION                     _MK_MASK_CONST(0x1)
#define PMC_IMPL_VFMON_ACTION_0_FOSC_FAULT_ACTION_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)
#define PMC_IMPL_VFMON_ACTION_0_FOSC_FAULT_ACTION_INIT_ENUM                     INTR
#define PMC_IMPL_VFMON_ACTION_0_FOSC_FAULT_ACTION_NONE                  _MK_ENUM_CONST(0)
#define PMC_IMPL_VFMON_ACTION_0_FOSC_FAULT_ACTION_INTR                  _MK_ENUM_CONST(1)

#define PMC_IMPL_VFMON_ACTION_0_F32K_FAULT_ACTION_SHIFT                 _MK_SHIFT_CONST(2)
#define PMC_IMPL_VFMON_ACTION_0_F32K_FAULT_ACTION_FIELD                 _MK_FIELD_CONST(0x3, PMC_IMPL_VFMON_ACTION_0_F32K_FAULT_ACTION_SHIFT)
#define PMC_IMPL_VFMON_ACTION_0_F32K_FAULT_ACTION_RANGE                 3:2
#define PMC_IMPL_VFMON_ACTION_0_F32K_FAULT_ACTION_WOFFSET                       0x0
#define PMC_IMPL_VFMON_ACTION_0_F32K_FAULT_ACTION_DEFAULT                       _MK_MASK_CONST(0x1)
#define PMC_IMPL_VFMON_ACTION_0_F32K_FAULT_ACTION_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
#define PMC_IMPL_VFMON_ACTION_0_F32K_FAULT_ACTION_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define PMC_IMPL_VFMON_ACTION_0_F32K_FAULT_ACTION_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define PMC_IMPL_VFMON_ACTION_0_F32K_FAULT_ACTION_PARITY_PROTECTION                     _MK_MASK_CONST(0x1)
#define PMC_IMPL_VFMON_ACTION_0_F32K_FAULT_ACTION_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)
#define PMC_IMPL_VFMON_ACTION_0_F32K_FAULT_ACTION_INIT_ENUM                     INTR
#define PMC_IMPL_VFMON_ACTION_0_F32K_FAULT_ACTION_NONE                  _MK_ENUM_CONST(0)
#define PMC_IMPL_VFMON_ACTION_0_F32K_FAULT_ACTION_INTR                  _MK_ENUM_CONST(1)

#define PMC_IMPL_VFMON_ACTION_0_VDD_SOC_MIN_FAULT_ACTION_SHIFT                  _MK_SHIFT_CONST(4)
#define PMC_IMPL_VFMON_ACTION_0_VDD_SOC_MIN_FAULT_ACTION_FIELD                  _MK_FIELD_CONST(0x3, PMC_IMPL_VFMON_ACTION_0_VDD_SOC_MIN_FAULT_ACTION_SHIFT)
#define PMC_IMPL_VFMON_ACTION_0_VDD_SOC_MIN_FAULT_ACTION_RANGE                  5:4
#define PMC_IMPL_VFMON_ACTION_0_VDD_SOC_MIN_FAULT_ACTION_WOFFSET                        0x0
#define PMC_IMPL_VFMON_ACTION_0_VDD_SOC_MIN_FAULT_ACTION_DEFAULT                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_VFMON_ACTION_0_VDD_SOC_MIN_FAULT_ACTION_DEFAULT_MASK                   _MK_MASK_CONST(0x3)
#define PMC_IMPL_VFMON_ACTION_0_VDD_SOC_MIN_FAULT_ACTION_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_VFMON_ACTION_0_VDD_SOC_MIN_FAULT_ACTION_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_VFMON_ACTION_0_VDD_SOC_MIN_FAULT_ACTION_PARITY_PROTECTION                      _MK_MASK_CONST(0x1)
#define PMC_IMPL_VFMON_ACTION_0_VDD_SOC_MIN_FAULT_ACTION_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define PMC_IMPL_VFMON_ACTION_0_VDD_SOC_MIN_FAULT_ACTION_INIT_ENUM                      NONE
#define PMC_IMPL_VFMON_ACTION_0_VDD_SOC_MIN_FAULT_ACTION_NONE                   _MK_ENUM_CONST(0)
#define PMC_IMPL_VFMON_ACTION_0_VDD_SOC_MIN_FAULT_ACTION_INTR                   _MK_ENUM_CONST(1)
#define PMC_IMPL_VFMON_ACTION_0_VDD_SOC_MIN_FAULT_ACTION_RST                    _MK_ENUM_CONST(2)

#define PMC_IMPL_VFMON_ACTION_0_VDD_SOC_MAX_FAULT_ACTION_SHIFT                  _MK_SHIFT_CONST(6)
#define PMC_IMPL_VFMON_ACTION_0_VDD_SOC_MAX_FAULT_ACTION_FIELD                  _MK_FIELD_CONST(0x3, PMC_IMPL_VFMON_ACTION_0_VDD_SOC_MAX_FAULT_ACTION_SHIFT)
#define PMC_IMPL_VFMON_ACTION_0_VDD_SOC_MAX_FAULT_ACTION_RANGE                  7:6
#define PMC_IMPL_VFMON_ACTION_0_VDD_SOC_MAX_FAULT_ACTION_WOFFSET                        0x0
#define PMC_IMPL_VFMON_ACTION_0_VDD_SOC_MAX_FAULT_ACTION_DEFAULT                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_VFMON_ACTION_0_VDD_SOC_MAX_FAULT_ACTION_DEFAULT_MASK                   _MK_MASK_CONST(0x3)
#define PMC_IMPL_VFMON_ACTION_0_VDD_SOC_MAX_FAULT_ACTION_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_VFMON_ACTION_0_VDD_SOC_MAX_FAULT_ACTION_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_VFMON_ACTION_0_VDD_SOC_MAX_FAULT_ACTION_PARITY_PROTECTION                      _MK_MASK_CONST(0x1)
#define PMC_IMPL_VFMON_ACTION_0_VDD_SOC_MAX_FAULT_ACTION_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define PMC_IMPL_VFMON_ACTION_0_VDD_SOC_MAX_FAULT_ACTION_INIT_ENUM                      NONE
#define PMC_IMPL_VFMON_ACTION_0_VDD_SOC_MAX_FAULT_ACTION_NONE                   _MK_ENUM_CONST(0)
#define PMC_IMPL_VFMON_ACTION_0_VDD_SOC_MAX_FAULT_ACTION_INTR                   _MK_ENUM_CONST(1)
#define PMC_IMPL_VFMON_ACTION_0_VDD_SOC_MAX_FAULT_ACTION_RST                    _MK_ENUM_CONST(2)

#define PMC_IMPL_VFMON_ACTION_0_VDD_CPU0_MIN_FAULT_ACTION_SHIFT                 _MK_SHIFT_CONST(8)
#define PMC_IMPL_VFMON_ACTION_0_VDD_CPU0_MIN_FAULT_ACTION_FIELD                 _MK_FIELD_CONST(0x3, PMC_IMPL_VFMON_ACTION_0_VDD_CPU0_MIN_FAULT_ACTION_SHIFT)
#define PMC_IMPL_VFMON_ACTION_0_VDD_CPU0_MIN_FAULT_ACTION_RANGE                 9:8
#define PMC_IMPL_VFMON_ACTION_0_VDD_CPU0_MIN_FAULT_ACTION_WOFFSET                       0x0
#define PMC_IMPL_VFMON_ACTION_0_VDD_CPU0_MIN_FAULT_ACTION_DEFAULT                       _MK_MASK_CONST(0x0)
#define PMC_IMPL_VFMON_ACTION_0_VDD_CPU0_MIN_FAULT_ACTION_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
#define PMC_IMPL_VFMON_ACTION_0_VDD_CPU0_MIN_FAULT_ACTION_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define PMC_IMPL_VFMON_ACTION_0_VDD_CPU0_MIN_FAULT_ACTION_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define PMC_IMPL_VFMON_ACTION_0_VDD_CPU0_MIN_FAULT_ACTION_PARITY_PROTECTION                     _MK_MASK_CONST(0x1)
#define PMC_IMPL_VFMON_ACTION_0_VDD_CPU0_MIN_FAULT_ACTION_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)
#define PMC_IMPL_VFMON_ACTION_0_VDD_CPU0_MIN_FAULT_ACTION_INIT_ENUM                     NONE
#define PMC_IMPL_VFMON_ACTION_0_VDD_CPU0_MIN_FAULT_ACTION_NONE                  _MK_ENUM_CONST(0)
#define PMC_IMPL_VFMON_ACTION_0_VDD_CPU0_MIN_FAULT_ACTION_INTR                  _MK_ENUM_CONST(1)
#define PMC_IMPL_VFMON_ACTION_0_VDD_CPU0_MIN_FAULT_ACTION_RST                   _MK_ENUM_CONST(2)

#define PMC_IMPL_VFMON_ACTION_0_VDD_CPU0_MAX_FAULT_ACTION_SHIFT                 _MK_SHIFT_CONST(10)
#define PMC_IMPL_VFMON_ACTION_0_VDD_CPU0_MAX_FAULT_ACTION_FIELD                 _MK_FIELD_CONST(0x3, PMC_IMPL_VFMON_ACTION_0_VDD_CPU0_MAX_FAULT_ACTION_SHIFT)
#define PMC_IMPL_VFMON_ACTION_0_VDD_CPU0_MAX_FAULT_ACTION_RANGE                 11:10
#define PMC_IMPL_VFMON_ACTION_0_VDD_CPU0_MAX_FAULT_ACTION_WOFFSET                       0x0
#define PMC_IMPL_VFMON_ACTION_0_VDD_CPU0_MAX_FAULT_ACTION_DEFAULT                       _MK_MASK_CONST(0x0)
#define PMC_IMPL_VFMON_ACTION_0_VDD_CPU0_MAX_FAULT_ACTION_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
#define PMC_IMPL_VFMON_ACTION_0_VDD_CPU0_MAX_FAULT_ACTION_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define PMC_IMPL_VFMON_ACTION_0_VDD_CPU0_MAX_FAULT_ACTION_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define PMC_IMPL_VFMON_ACTION_0_VDD_CPU0_MAX_FAULT_ACTION_PARITY_PROTECTION                     _MK_MASK_CONST(0x1)
#define PMC_IMPL_VFMON_ACTION_0_VDD_CPU0_MAX_FAULT_ACTION_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)
#define PMC_IMPL_VFMON_ACTION_0_VDD_CPU0_MAX_FAULT_ACTION_INIT_ENUM                     NONE
#define PMC_IMPL_VFMON_ACTION_0_VDD_CPU0_MAX_FAULT_ACTION_NONE                  _MK_ENUM_CONST(0)
#define PMC_IMPL_VFMON_ACTION_0_VDD_CPU0_MAX_FAULT_ACTION_INTR                  _MK_ENUM_CONST(1)
#define PMC_IMPL_VFMON_ACTION_0_VDD_CPU0_MAX_FAULT_ACTION_RST                   _MK_ENUM_CONST(2)

#define PMC_IMPL_VFMON_ACTION_0_VDD_CPU1_MIN_FAULT_ACTION_SHIFT                 _MK_SHIFT_CONST(12)
#define PMC_IMPL_VFMON_ACTION_0_VDD_CPU1_MIN_FAULT_ACTION_FIELD                 _MK_FIELD_CONST(0x3, PMC_IMPL_VFMON_ACTION_0_VDD_CPU1_MIN_FAULT_ACTION_SHIFT)
#define PMC_IMPL_VFMON_ACTION_0_VDD_CPU1_MIN_FAULT_ACTION_RANGE                 13:12
#define PMC_IMPL_VFMON_ACTION_0_VDD_CPU1_MIN_FAULT_ACTION_WOFFSET                       0x0
#define PMC_IMPL_VFMON_ACTION_0_VDD_CPU1_MIN_FAULT_ACTION_DEFAULT                       _MK_MASK_CONST(0x0)
#define PMC_IMPL_VFMON_ACTION_0_VDD_CPU1_MIN_FAULT_ACTION_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
#define PMC_IMPL_VFMON_ACTION_0_VDD_CPU1_MIN_FAULT_ACTION_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define PMC_IMPL_VFMON_ACTION_0_VDD_CPU1_MIN_FAULT_ACTION_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define PMC_IMPL_VFMON_ACTION_0_VDD_CPU1_MIN_FAULT_ACTION_PARITY_PROTECTION                     _MK_MASK_CONST(0x1)
#define PMC_IMPL_VFMON_ACTION_0_VDD_CPU1_MIN_FAULT_ACTION_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)
#define PMC_IMPL_VFMON_ACTION_0_VDD_CPU1_MIN_FAULT_ACTION_INIT_ENUM                     NONE
#define PMC_IMPL_VFMON_ACTION_0_VDD_CPU1_MIN_FAULT_ACTION_NONE                  _MK_ENUM_CONST(0)
#define PMC_IMPL_VFMON_ACTION_0_VDD_CPU1_MIN_FAULT_ACTION_INTR                  _MK_ENUM_CONST(1)
#define PMC_IMPL_VFMON_ACTION_0_VDD_CPU1_MIN_FAULT_ACTION_RST                   _MK_ENUM_CONST(2)

#define PMC_IMPL_VFMON_ACTION_0_VDD_CPU1_MAX_FAULT_ACTION_SHIFT                 _MK_SHIFT_CONST(14)
#define PMC_IMPL_VFMON_ACTION_0_VDD_CPU1_MAX_FAULT_ACTION_FIELD                 _MK_FIELD_CONST(0x3, PMC_IMPL_VFMON_ACTION_0_VDD_CPU1_MAX_FAULT_ACTION_SHIFT)
#define PMC_IMPL_VFMON_ACTION_0_VDD_CPU1_MAX_FAULT_ACTION_RANGE                 15:14
#define PMC_IMPL_VFMON_ACTION_0_VDD_CPU1_MAX_FAULT_ACTION_WOFFSET                       0x0
#define PMC_IMPL_VFMON_ACTION_0_VDD_CPU1_MAX_FAULT_ACTION_DEFAULT                       _MK_MASK_CONST(0x0)
#define PMC_IMPL_VFMON_ACTION_0_VDD_CPU1_MAX_FAULT_ACTION_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
#define PMC_IMPL_VFMON_ACTION_0_VDD_CPU1_MAX_FAULT_ACTION_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define PMC_IMPL_VFMON_ACTION_0_VDD_CPU1_MAX_FAULT_ACTION_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define PMC_IMPL_VFMON_ACTION_0_VDD_CPU1_MAX_FAULT_ACTION_PARITY_PROTECTION                     _MK_MASK_CONST(0x1)
#define PMC_IMPL_VFMON_ACTION_0_VDD_CPU1_MAX_FAULT_ACTION_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)
#define PMC_IMPL_VFMON_ACTION_0_VDD_CPU1_MAX_FAULT_ACTION_INIT_ENUM                     NONE
#define PMC_IMPL_VFMON_ACTION_0_VDD_CPU1_MAX_FAULT_ACTION_NONE                  _MK_ENUM_CONST(0)
#define PMC_IMPL_VFMON_ACTION_0_VDD_CPU1_MAX_FAULT_ACTION_INTR                  _MK_ENUM_CONST(1)
#define PMC_IMPL_VFMON_ACTION_0_VDD_CPU1_MAX_FAULT_ACTION_RST                   _MK_ENUM_CONST(2)

#define PMC_IMPL_VFMON_ACTION_0_VMON_EN_SHIFT                   _MK_SHIFT_CONST(31)
#define PMC_IMPL_VFMON_ACTION_0_VMON_EN_FIELD                   _MK_FIELD_CONST(0x1, PMC_IMPL_VFMON_ACTION_0_VMON_EN_SHIFT)
#define PMC_IMPL_VFMON_ACTION_0_VMON_EN_RANGE                   31:31
#define PMC_IMPL_VFMON_ACTION_0_VMON_EN_WOFFSET                 0x0
#define PMC_IMPL_VFMON_ACTION_0_VMON_EN_DEFAULT                 _MK_MASK_CONST(0x1)
#define PMC_IMPL_VFMON_ACTION_0_VMON_EN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define PMC_IMPL_VFMON_ACTION_0_VMON_EN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_VFMON_ACTION_0_VMON_EN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define PMC_IMPL_VFMON_ACTION_0_VMON_EN_PARITY_PROTECTION                       _MK_MASK_CONST(0x1)
#define PMC_IMPL_VFMON_ACTION_0_VMON_EN_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)


// Register PMC_IMPL_VFMON_INT_STATUS_0
#define PMC_IMPL_VFMON_INT_STATUS_0                     _MK_ADDR_CONST(0x1d8)
#define PMC_IMPL_VFMON_INT_STATUS_0_SECURE                      0x0
#define PMC_IMPL_VFMON_INT_STATUS_0_DUAL                        0x0
#define PMC_IMPL_VFMON_INT_STATUS_0_SCR                         VFMON_ST_SCR_0
#define PMC_IMPL_VFMON_INT_STATUS_0_WORD_COUNT                  0x1
#define PMC_IMPL_VFMON_INT_STATUS_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_VFMON_INT_STATUS_0_RESET_MASK                  _MK_MASK_CONST(0xff)
#define PMC_IMPL_VFMON_INT_STATUS_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_VFMON_INT_STATUS_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_VFMON_INT_STATUS_0_READ_MASK                   _MK_MASK_CONST(0xff)
#define PMC_IMPL_VFMON_INT_STATUS_0_WRITE_MASK                  _MK_MASK_CONST(0xff)
#define PMC_IMPL_VFMON_INT_STATUS_0_FOSC_FAULT_SHIFT                    _MK_SHIFT_CONST(0)
#define PMC_IMPL_VFMON_INT_STATUS_0_FOSC_FAULT_FIELD                    _MK_FIELD_CONST(0x1, PMC_IMPL_VFMON_INT_STATUS_0_FOSC_FAULT_SHIFT)
#define PMC_IMPL_VFMON_INT_STATUS_0_FOSC_FAULT_RANGE                    0:0
#define PMC_IMPL_VFMON_INT_STATUS_0_FOSC_FAULT_WOFFSET                  0x0
#define PMC_IMPL_VFMON_INT_STATUS_0_FOSC_FAULT_DEFAULT                  _MK_MASK_CONST(0x0)
#define PMC_IMPL_VFMON_INT_STATUS_0_FOSC_FAULT_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define PMC_IMPL_VFMON_INT_STATUS_0_FOSC_FAULT_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define PMC_IMPL_VFMON_INT_STATUS_0_FOSC_FAULT_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define PMC_IMPL_VFMON_INT_STATUS_0_FOSC_FAULT_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_VFMON_INT_STATUS_0_FOSC_FAULT_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)
#define PMC_IMPL_VFMON_INT_STATUS_0_FOSC_FAULT_INIT_ENUM                        OFF
#define PMC_IMPL_VFMON_INT_STATUS_0_FOSC_FAULT_OFF                      _MK_ENUM_CONST(0)
#define PMC_IMPL_VFMON_INT_STATUS_0_FOSC_FAULT_ON                       _MK_ENUM_CONST(1)

#define PMC_IMPL_VFMON_INT_STATUS_0_F32K_FAULT_SHIFT                    _MK_SHIFT_CONST(1)
#define PMC_IMPL_VFMON_INT_STATUS_0_F32K_FAULT_FIELD                    _MK_FIELD_CONST(0x1, PMC_IMPL_VFMON_INT_STATUS_0_F32K_FAULT_SHIFT)
#define PMC_IMPL_VFMON_INT_STATUS_0_F32K_FAULT_RANGE                    1:1
#define PMC_IMPL_VFMON_INT_STATUS_0_F32K_FAULT_WOFFSET                  0x0
#define PMC_IMPL_VFMON_INT_STATUS_0_F32K_FAULT_DEFAULT                  _MK_MASK_CONST(0x0)
#define PMC_IMPL_VFMON_INT_STATUS_0_F32K_FAULT_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define PMC_IMPL_VFMON_INT_STATUS_0_F32K_FAULT_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define PMC_IMPL_VFMON_INT_STATUS_0_F32K_FAULT_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define PMC_IMPL_VFMON_INT_STATUS_0_F32K_FAULT_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_VFMON_INT_STATUS_0_F32K_FAULT_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)
#define PMC_IMPL_VFMON_INT_STATUS_0_F32K_FAULT_INIT_ENUM                        OFF
#define PMC_IMPL_VFMON_INT_STATUS_0_F32K_FAULT_OFF                      _MK_ENUM_CONST(0)
#define PMC_IMPL_VFMON_INT_STATUS_0_F32K_FAULT_ON                       _MK_ENUM_CONST(1)

#define PMC_IMPL_VFMON_INT_STATUS_0_VDD_SOC_MIN_FAULT_SHIFT                     _MK_SHIFT_CONST(2)
#define PMC_IMPL_VFMON_INT_STATUS_0_VDD_SOC_MIN_FAULT_FIELD                     _MK_FIELD_CONST(0x1, PMC_IMPL_VFMON_INT_STATUS_0_VDD_SOC_MIN_FAULT_SHIFT)
#define PMC_IMPL_VFMON_INT_STATUS_0_VDD_SOC_MIN_FAULT_RANGE                     2:2
#define PMC_IMPL_VFMON_INT_STATUS_0_VDD_SOC_MIN_FAULT_WOFFSET                   0x0
#define PMC_IMPL_VFMON_INT_STATUS_0_VDD_SOC_MIN_FAULT_DEFAULT                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_VFMON_INT_STATUS_0_VDD_SOC_MIN_FAULT_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define PMC_IMPL_VFMON_INT_STATUS_0_VDD_SOC_MIN_FAULT_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_VFMON_INT_STATUS_0_VDD_SOC_MIN_FAULT_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_VFMON_INT_STATUS_0_VDD_SOC_MIN_FAULT_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define PMC_IMPL_VFMON_INT_STATUS_0_VDD_SOC_MIN_FAULT_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define PMC_IMPL_VFMON_INT_STATUS_0_VDD_SOC_MIN_FAULT_INIT_ENUM                 OFF
#define PMC_IMPL_VFMON_INT_STATUS_0_VDD_SOC_MIN_FAULT_OFF                       _MK_ENUM_CONST(0)
#define PMC_IMPL_VFMON_INT_STATUS_0_VDD_SOC_MIN_FAULT_ON                        _MK_ENUM_CONST(1)

#define PMC_IMPL_VFMON_INT_STATUS_0_VDD_SOC_MAX_FAULT_SHIFT                     _MK_SHIFT_CONST(3)
#define PMC_IMPL_VFMON_INT_STATUS_0_VDD_SOC_MAX_FAULT_FIELD                     _MK_FIELD_CONST(0x1, PMC_IMPL_VFMON_INT_STATUS_0_VDD_SOC_MAX_FAULT_SHIFT)
#define PMC_IMPL_VFMON_INT_STATUS_0_VDD_SOC_MAX_FAULT_RANGE                     3:3
#define PMC_IMPL_VFMON_INT_STATUS_0_VDD_SOC_MAX_FAULT_WOFFSET                   0x0
#define PMC_IMPL_VFMON_INT_STATUS_0_VDD_SOC_MAX_FAULT_DEFAULT                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_VFMON_INT_STATUS_0_VDD_SOC_MAX_FAULT_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define PMC_IMPL_VFMON_INT_STATUS_0_VDD_SOC_MAX_FAULT_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_VFMON_INT_STATUS_0_VDD_SOC_MAX_FAULT_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_VFMON_INT_STATUS_0_VDD_SOC_MAX_FAULT_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define PMC_IMPL_VFMON_INT_STATUS_0_VDD_SOC_MAX_FAULT_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define PMC_IMPL_VFMON_INT_STATUS_0_VDD_SOC_MAX_FAULT_INIT_ENUM                 OFF
#define PMC_IMPL_VFMON_INT_STATUS_0_VDD_SOC_MAX_FAULT_OFF                       _MK_ENUM_CONST(0)
#define PMC_IMPL_VFMON_INT_STATUS_0_VDD_SOC_MAX_FAULT_ON                        _MK_ENUM_CONST(1)

#define PMC_IMPL_VFMON_INT_STATUS_0_VDD_CPU0_MIN_FAULT_SHIFT                    _MK_SHIFT_CONST(4)
#define PMC_IMPL_VFMON_INT_STATUS_0_VDD_CPU0_MIN_FAULT_FIELD                    _MK_FIELD_CONST(0x1, PMC_IMPL_VFMON_INT_STATUS_0_VDD_CPU0_MIN_FAULT_SHIFT)
#define PMC_IMPL_VFMON_INT_STATUS_0_VDD_CPU0_MIN_FAULT_RANGE                    4:4
#define PMC_IMPL_VFMON_INT_STATUS_0_VDD_CPU0_MIN_FAULT_WOFFSET                  0x0
#define PMC_IMPL_VFMON_INT_STATUS_0_VDD_CPU0_MIN_FAULT_DEFAULT                  _MK_MASK_CONST(0x0)
#define PMC_IMPL_VFMON_INT_STATUS_0_VDD_CPU0_MIN_FAULT_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define PMC_IMPL_VFMON_INT_STATUS_0_VDD_CPU0_MIN_FAULT_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define PMC_IMPL_VFMON_INT_STATUS_0_VDD_CPU0_MIN_FAULT_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define PMC_IMPL_VFMON_INT_STATUS_0_VDD_CPU0_MIN_FAULT_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_VFMON_INT_STATUS_0_VDD_CPU0_MIN_FAULT_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)
#define PMC_IMPL_VFMON_INT_STATUS_0_VDD_CPU0_MIN_FAULT_INIT_ENUM                        OFF
#define PMC_IMPL_VFMON_INT_STATUS_0_VDD_CPU0_MIN_FAULT_OFF                      _MK_ENUM_CONST(0)
#define PMC_IMPL_VFMON_INT_STATUS_0_VDD_CPU0_MIN_FAULT_ON                       _MK_ENUM_CONST(1)

#define PMC_IMPL_VFMON_INT_STATUS_0_VDD_CPU0_MAX_FAULT_SHIFT                    _MK_SHIFT_CONST(5)
#define PMC_IMPL_VFMON_INT_STATUS_0_VDD_CPU0_MAX_FAULT_FIELD                    _MK_FIELD_CONST(0x1, PMC_IMPL_VFMON_INT_STATUS_0_VDD_CPU0_MAX_FAULT_SHIFT)
#define PMC_IMPL_VFMON_INT_STATUS_0_VDD_CPU0_MAX_FAULT_RANGE                    5:5
#define PMC_IMPL_VFMON_INT_STATUS_0_VDD_CPU0_MAX_FAULT_WOFFSET                  0x0
#define PMC_IMPL_VFMON_INT_STATUS_0_VDD_CPU0_MAX_FAULT_DEFAULT                  _MK_MASK_CONST(0x0)
#define PMC_IMPL_VFMON_INT_STATUS_0_VDD_CPU0_MAX_FAULT_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define PMC_IMPL_VFMON_INT_STATUS_0_VDD_CPU0_MAX_FAULT_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define PMC_IMPL_VFMON_INT_STATUS_0_VDD_CPU0_MAX_FAULT_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define PMC_IMPL_VFMON_INT_STATUS_0_VDD_CPU0_MAX_FAULT_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_VFMON_INT_STATUS_0_VDD_CPU0_MAX_FAULT_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)
#define PMC_IMPL_VFMON_INT_STATUS_0_VDD_CPU0_MAX_FAULT_INIT_ENUM                        OFF
#define PMC_IMPL_VFMON_INT_STATUS_0_VDD_CPU0_MAX_FAULT_OFF                      _MK_ENUM_CONST(0)
#define PMC_IMPL_VFMON_INT_STATUS_0_VDD_CPU0_MAX_FAULT_ON                       _MK_ENUM_CONST(1)

#define PMC_IMPL_VFMON_INT_STATUS_0_VDD_CPU1_MIN_FAULT_SHIFT                    _MK_SHIFT_CONST(6)
#define PMC_IMPL_VFMON_INT_STATUS_0_VDD_CPU1_MIN_FAULT_FIELD                    _MK_FIELD_CONST(0x1, PMC_IMPL_VFMON_INT_STATUS_0_VDD_CPU1_MIN_FAULT_SHIFT)
#define PMC_IMPL_VFMON_INT_STATUS_0_VDD_CPU1_MIN_FAULT_RANGE                    6:6
#define PMC_IMPL_VFMON_INT_STATUS_0_VDD_CPU1_MIN_FAULT_WOFFSET                  0x0
#define PMC_IMPL_VFMON_INT_STATUS_0_VDD_CPU1_MIN_FAULT_DEFAULT                  _MK_MASK_CONST(0x0)
#define PMC_IMPL_VFMON_INT_STATUS_0_VDD_CPU1_MIN_FAULT_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define PMC_IMPL_VFMON_INT_STATUS_0_VDD_CPU1_MIN_FAULT_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define PMC_IMPL_VFMON_INT_STATUS_0_VDD_CPU1_MIN_FAULT_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define PMC_IMPL_VFMON_INT_STATUS_0_VDD_CPU1_MIN_FAULT_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_VFMON_INT_STATUS_0_VDD_CPU1_MIN_FAULT_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)
#define PMC_IMPL_VFMON_INT_STATUS_0_VDD_CPU1_MIN_FAULT_INIT_ENUM                        OFF
#define PMC_IMPL_VFMON_INT_STATUS_0_VDD_CPU1_MIN_FAULT_OFF                      _MK_ENUM_CONST(0)
#define PMC_IMPL_VFMON_INT_STATUS_0_VDD_CPU1_MIN_FAULT_ON                       _MK_ENUM_CONST(1)

#define PMC_IMPL_VFMON_INT_STATUS_0_VDD_CPU1_MAX_FAULT_SHIFT                    _MK_SHIFT_CONST(7)
#define PMC_IMPL_VFMON_INT_STATUS_0_VDD_CPU1_MAX_FAULT_FIELD                    _MK_FIELD_CONST(0x1, PMC_IMPL_VFMON_INT_STATUS_0_VDD_CPU1_MAX_FAULT_SHIFT)
#define PMC_IMPL_VFMON_INT_STATUS_0_VDD_CPU1_MAX_FAULT_RANGE                    7:7
#define PMC_IMPL_VFMON_INT_STATUS_0_VDD_CPU1_MAX_FAULT_WOFFSET                  0x0
#define PMC_IMPL_VFMON_INT_STATUS_0_VDD_CPU1_MAX_FAULT_DEFAULT                  _MK_MASK_CONST(0x0)
#define PMC_IMPL_VFMON_INT_STATUS_0_VDD_CPU1_MAX_FAULT_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define PMC_IMPL_VFMON_INT_STATUS_0_VDD_CPU1_MAX_FAULT_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define PMC_IMPL_VFMON_INT_STATUS_0_VDD_CPU1_MAX_FAULT_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define PMC_IMPL_VFMON_INT_STATUS_0_VDD_CPU1_MAX_FAULT_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_VFMON_INT_STATUS_0_VDD_CPU1_MAX_FAULT_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)
#define PMC_IMPL_VFMON_INT_STATUS_0_VDD_CPU1_MAX_FAULT_INIT_ENUM                        OFF
#define PMC_IMPL_VFMON_INT_STATUS_0_VDD_CPU1_MAX_FAULT_OFF                      _MK_ENUM_CONST(0)
#define PMC_IMPL_VFMON_INT_STATUS_0_VDD_CPU1_MAX_FAULT_ON                       _MK_ENUM_CONST(1)


// Register PMC_IMPL_VFMON_INT_MASK_0
#define PMC_IMPL_VFMON_INT_MASK_0                       _MK_ADDR_CONST(0x1dc)
#define PMC_IMPL_VFMON_INT_MASK_0_SECURE                        0x0
#define PMC_IMPL_VFMON_INT_MASK_0_DUAL                  0x0
#define PMC_IMPL_VFMON_INT_MASK_0_SCR                   VFMON_ST_SCR_0
#define PMC_IMPL_VFMON_INT_MASK_0_WORD_COUNT                    0x1
#define PMC_IMPL_VFMON_INT_MASK_0_RESET_VAL                     _MK_MASK_CONST(0xff)
#define PMC_IMPL_VFMON_INT_MASK_0_RESET_MASK                    _MK_MASK_CONST(0xff)
#define PMC_IMPL_VFMON_INT_MASK_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_VFMON_INT_MASK_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define PMC_IMPL_VFMON_INT_MASK_0_READ_MASK                     _MK_MASK_CONST(0xff)
#define PMC_IMPL_VFMON_INT_MASK_0_WRITE_MASK                    _MK_MASK_CONST(0xff)
#define PMC_IMPL_VFMON_INT_MASK_0_FOSC_FAULT_SHIFT                      _MK_SHIFT_CONST(0)
#define PMC_IMPL_VFMON_INT_MASK_0_FOSC_FAULT_FIELD                      _MK_FIELD_CONST(0x1, PMC_IMPL_VFMON_INT_MASK_0_FOSC_FAULT_SHIFT)
#define PMC_IMPL_VFMON_INT_MASK_0_FOSC_FAULT_RANGE                      0:0
#define PMC_IMPL_VFMON_INT_MASK_0_FOSC_FAULT_WOFFSET                    0x0
#define PMC_IMPL_VFMON_INT_MASK_0_FOSC_FAULT_DEFAULT                    _MK_MASK_CONST(0x1)
#define PMC_IMPL_VFMON_INT_MASK_0_FOSC_FAULT_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define PMC_IMPL_VFMON_INT_MASK_0_FOSC_FAULT_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define PMC_IMPL_VFMON_INT_MASK_0_FOSC_FAULT_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define PMC_IMPL_VFMON_INT_MASK_0_FOSC_FAULT_PARITY_PROTECTION                  _MK_MASK_CONST(0x1)
#define PMC_IMPL_VFMON_INT_MASK_0_FOSC_FAULT_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define PMC_IMPL_VFMON_INT_MASK_0_FOSC_FAULT_INIT_ENUM                  MASK
#define PMC_IMPL_VFMON_INT_MASK_0_FOSC_FAULT_UNMASK                     _MK_ENUM_CONST(0)
#define PMC_IMPL_VFMON_INT_MASK_0_FOSC_FAULT_MASK                       _MK_ENUM_CONST(1)

#define PMC_IMPL_VFMON_INT_MASK_0_F32K_FAULT_SHIFT                      _MK_SHIFT_CONST(1)
#define PMC_IMPL_VFMON_INT_MASK_0_F32K_FAULT_FIELD                      _MK_FIELD_CONST(0x1, PMC_IMPL_VFMON_INT_MASK_0_F32K_FAULT_SHIFT)
#define PMC_IMPL_VFMON_INT_MASK_0_F32K_FAULT_RANGE                      1:1
#define PMC_IMPL_VFMON_INT_MASK_0_F32K_FAULT_WOFFSET                    0x0
#define PMC_IMPL_VFMON_INT_MASK_0_F32K_FAULT_DEFAULT                    _MK_MASK_CONST(0x1)
#define PMC_IMPL_VFMON_INT_MASK_0_F32K_FAULT_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define PMC_IMPL_VFMON_INT_MASK_0_F32K_FAULT_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define PMC_IMPL_VFMON_INT_MASK_0_F32K_FAULT_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define PMC_IMPL_VFMON_INT_MASK_0_F32K_FAULT_PARITY_PROTECTION                  _MK_MASK_CONST(0x1)
#define PMC_IMPL_VFMON_INT_MASK_0_F32K_FAULT_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define PMC_IMPL_VFMON_INT_MASK_0_F32K_FAULT_INIT_ENUM                  MASK
#define PMC_IMPL_VFMON_INT_MASK_0_F32K_FAULT_UNMASK                     _MK_ENUM_CONST(0)
#define PMC_IMPL_VFMON_INT_MASK_0_F32K_FAULT_MASK                       _MK_ENUM_CONST(1)

#define PMC_IMPL_VFMON_INT_MASK_0_VDD_SOC_MIN_FAULT_SHIFT                       _MK_SHIFT_CONST(2)
#define PMC_IMPL_VFMON_INT_MASK_0_VDD_SOC_MIN_FAULT_FIELD                       _MK_FIELD_CONST(0x1, PMC_IMPL_VFMON_INT_MASK_0_VDD_SOC_MIN_FAULT_SHIFT)
#define PMC_IMPL_VFMON_INT_MASK_0_VDD_SOC_MIN_FAULT_RANGE                       2:2
#define PMC_IMPL_VFMON_INT_MASK_0_VDD_SOC_MIN_FAULT_WOFFSET                     0x0
#define PMC_IMPL_VFMON_INT_MASK_0_VDD_SOC_MIN_FAULT_DEFAULT                     _MK_MASK_CONST(0x1)
#define PMC_IMPL_VFMON_INT_MASK_0_VDD_SOC_MIN_FAULT_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define PMC_IMPL_VFMON_INT_MASK_0_VDD_SOC_MIN_FAULT_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define PMC_IMPL_VFMON_INT_MASK_0_VDD_SOC_MIN_FAULT_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_VFMON_INT_MASK_0_VDD_SOC_MIN_FAULT_PARITY_PROTECTION                   _MK_MASK_CONST(0x1)
#define PMC_IMPL_VFMON_INT_MASK_0_VDD_SOC_MIN_FAULT_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define PMC_IMPL_VFMON_INT_MASK_0_VDD_SOC_MIN_FAULT_INIT_ENUM                   MASK
#define PMC_IMPL_VFMON_INT_MASK_0_VDD_SOC_MIN_FAULT_UNMASK                      _MK_ENUM_CONST(0)
#define PMC_IMPL_VFMON_INT_MASK_0_VDD_SOC_MIN_FAULT_MASK                        _MK_ENUM_CONST(1)

#define PMC_IMPL_VFMON_INT_MASK_0_VDD_SOC_MAX_FAULT_SHIFT                       _MK_SHIFT_CONST(3)
#define PMC_IMPL_VFMON_INT_MASK_0_VDD_SOC_MAX_FAULT_FIELD                       _MK_FIELD_CONST(0x1, PMC_IMPL_VFMON_INT_MASK_0_VDD_SOC_MAX_FAULT_SHIFT)
#define PMC_IMPL_VFMON_INT_MASK_0_VDD_SOC_MAX_FAULT_RANGE                       3:3
#define PMC_IMPL_VFMON_INT_MASK_0_VDD_SOC_MAX_FAULT_WOFFSET                     0x0
#define PMC_IMPL_VFMON_INT_MASK_0_VDD_SOC_MAX_FAULT_DEFAULT                     _MK_MASK_CONST(0x1)
#define PMC_IMPL_VFMON_INT_MASK_0_VDD_SOC_MAX_FAULT_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define PMC_IMPL_VFMON_INT_MASK_0_VDD_SOC_MAX_FAULT_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define PMC_IMPL_VFMON_INT_MASK_0_VDD_SOC_MAX_FAULT_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_VFMON_INT_MASK_0_VDD_SOC_MAX_FAULT_PARITY_PROTECTION                   _MK_MASK_CONST(0x1)
#define PMC_IMPL_VFMON_INT_MASK_0_VDD_SOC_MAX_FAULT_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define PMC_IMPL_VFMON_INT_MASK_0_VDD_SOC_MAX_FAULT_INIT_ENUM                   MASK
#define PMC_IMPL_VFMON_INT_MASK_0_VDD_SOC_MAX_FAULT_UNMASK                      _MK_ENUM_CONST(0)
#define PMC_IMPL_VFMON_INT_MASK_0_VDD_SOC_MAX_FAULT_MASK                        _MK_ENUM_CONST(1)

#define PMC_IMPL_VFMON_INT_MASK_0_VDD_CPU0_MIN_FAULT_SHIFT                      _MK_SHIFT_CONST(4)
#define PMC_IMPL_VFMON_INT_MASK_0_VDD_CPU0_MIN_FAULT_FIELD                      _MK_FIELD_CONST(0x1, PMC_IMPL_VFMON_INT_MASK_0_VDD_CPU0_MIN_FAULT_SHIFT)
#define PMC_IMPL_VFMON_INT_MASK_0_VDD_CPU0_MIN_FAULT_RANGE                      4:4
#define PMC_IMPL_VFMON_INT_MASK_0_VDD_CPU0_MIN_FAULT_WOFFSET                    0x0
#define PMC_IMPL_VFMON_INT_MASK_0_VDD_CPU0_MIN_FAULT_DEFAULT                    _MK_MASK_CONST(0x1)
#define PMC_IMPL_VFMON_INT_MASK_0_VDD_CPU0_MIN_FAULT_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define PMC_IMPL_VFMON_INT_MASK_0_VDD_CPU0_MIN_FAULT_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define PMC_IMPL_VFMON_INT_MASK_0_VDD_CPU0_MIN_FAULT_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define PMC_IMPL_VFMON_INT_MASK_0_VDD_CPU0_MIN_FAULT_PARITY_PROTECTION                  _MK_MASK_CONST(0x1)
#define PMC_IMPL_VFMON_INT_MASK_0_VDD_CPU0_MIN_FAULT_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define PMC_IMPL_VFMON_INT_MASK_0_VDD_CPU0_MIN_FAULT_INIT_ENUM                  MASK
#define PMC_IMPL_VFMON_INT_MASK_0_VDD_CPU0_MIN_FAULT_UNMASK                     _MK_ENUM_CONST(0)
#define PMC_IMPL_VFMON_INT_MASK_0_VDD_CPU0_MIN_FAULT_MASK                       _MK_ENUM_CONST(1)

#define PMC_IMPL_VFMON_INT_MASK_0_VDD_CPU0_MAX_FAULT_SHIFT                      _MK_SHIFT_CONST(5)
#define PMC_IMPL_VFMON_INT_MASK_0_VDD_CPU0_MAX_FAULT_FIELD                      _MK_FIELD_CONST(0x1, PMC_IMPL_VFMON_INT_MASK_0_VDD_CPU0_MAX_FAULT_SHIFT)
#define PMC_IMPL_VFMON_INT_MASK_0_VDD_CPU0_MAX_FAULT_RANGE                      5:5
#define PMC_IMPL_VFMON_INT_MASK_0_VDD_CPU0_MAX_FAULT_WOFFSET                    0x0
#define PMC_IMPL_VFMON_INT_MASK_0_VDD_CPU0_MAX_FAULT_DEFAULT                    _MK_MASK_CONST(0x1)
#define PMC_IMPL_VFMON_INT_MASK_0_VDD_CPU0_MAX_FAULT_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define PMC_IMPL_VFMON_INT_MASK_0_VDD_CPU0_MAX_FAULT_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define PMC_IMPL_VFMON_INT_MASK_0_VDD_CPU0_MAX_FAULT_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define PMC_IMPL_VFMON_INT_MASK_0_VDD_CPU0_MAX_FAULT_PARITY_PROTECTION                  _MK_MASK_CONST(0x1)
#define PMC_IMPL_VFMON_INT_MASK_0_VDD_CPU0_MAX_FAULT_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define PMC_IMPL_VFMON_INT_MASK_0_VDD_CPU0_MAX_FAULT_INIT_ENUM                  MASK
#define PMC_IMPL_VFMON_INT_MASK_0_VDD_CPU0_MAX_FAULT_UNMASK                     _MK_ENUM_CONST(0)
#define PMC_IMPL_VFMON_INT_MASK_0_VDD_CPU0_MAX_FAULT_MASK                       _MK_ENUM_CONST(1)

#define PMC_IMPL_VFMON_INT_MASK_0_VDD_CPU1_MIN_FAULT_SHIFT                      _MK_SHIFT_CONST(6)
#define PMC_IMPL_VFMON_INT_MASK_0_VDD_CPU1_MIN_FAULT_FIELD                      _MK_FIELD_CONST(0x1, PMC_IMPL_VFMON_INT_MASK_0_VDD_CPU1_MIN_FAULT_SHIFT)
#define PMC_IMPL_VFMON_INT_MASK_0_VDD_CPU1_MIN_FAULT_RANGE                      6:6
#define PMC_IMPL_VFMON_INT_MASK_0_VDD_CPU1_MIN_FAULT_WOFFSET                    0x0
#define PMC_IMPL_VFMON_INT_MASK_0_VDD_CPU1_MIN_FAULT_DEFAULT                    _MK_MASK_CONST(0x1)
#define PMC_IMPL_VFMON_INT_MASK_0_VDD_CPU1_MIN_FAULT_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define PMC_IMPL_VFMON_INT_MASK_0_VDD_CPU1_MIN_FAULT_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define PMC_IMPL_VFMON_INT_MASK_0_VDD_CPU1_MIN_FAULT_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define PMC_IMPL_VFMON_INT_MASK_0_VDD_CPU1_MIN_FAULT_PARITY_PROTECTION                  _MK_MASK_CONST(0x1)
#define PMC_IMPL_VFMON_INT_MASK_0_VDD_CPU1_MIN_FAULT_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define PMC_IMPL_VFMON_INT_MASK_0_VDD_CPU1_MIN_FAULT_INIT_ENUM                  MASK
#define PMC_IMPL_VFMON_INT_MASK_0_VDD_CPU1_MIN_FAULT_UNMASK                     _MK_ENUM_CONST(0)
#define PMC_IMPL_VFMON_INT_MASK_0_VDD_CPU1_MIN_FAULT_MASK                       _MK_ENUM_CONST(1)

#define PMC_IMPL_VFMON_INT_MASK_0_VDD_CPU1_MAX_FAULT_SHIFT                      _MK_SHIFT_CONST(7)
#define PMC_IMPL_VFMON_INT_MASK_0_VDD_CPU1_MAX_FAULT_FIELD                      _MK_FIELD_CONST(0x1, PMC_IMPL_VFMON_INT_MASK_0_VDD_CPU1_MAX_FAULT_SHIFT)
#define PMC_IMPL_VFMON_INT_MASK_0_VDD_CPU1_MAX_FAULT_RANGE                      7:7
#define PMC_IMPL_VFMON_INT_MASK_0_VDD_CPU1_MAX_FAULT_WOFFSET                    0x0
#define PMC_IMPL_VFMON_INT_MASK_0_VDD_CPU1_MAX_FAULT_DEFAULT                    _MK_MASK_CONST(0x1)
#define PMC_IMPL_VFMON_INT_MASK_0_VDD_CPU1_MAX_FAULT_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define PMC_IMPL_VFMON_INT_MASK_0_VDD_CPU1_MAX_FAULT_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define PMC_IMPL_VFMON_INT_MASK_0_VDD_CPU1_MAX_FAULT_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define PMC_IMPL_VFMON_INT_MASK_0_VDD_CPU1_MAX_FAULT_PARITY_PROTECTION                  _MK_MASK_CONST(0x1)
#define PMC_IMPL_VFMON_INT_MASK_0_VDD_CPU1_MAX_FAULT_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define PMC_IMPL_VFMON_INT_MASK_0_VDD_CPU1_MAX_FAULT_INIT_ENUM                  MASK
#define PMC_IMPL_VFMON_INT_MASK_0_VDD_CPU1_MAX_FAULT_UNMASK                     _MK_ENUM_CONST(0)
#define PMC_IMPL_VFMON_INT_MASK_0_VDD_CPU1_MAX_FAULT_MASK                       _MK_ENUM_CONST(1)


// Reserved address 0x1e0

// Reserved address 0x1e4

// Reserved address 0x1e8

// Register PMC_IMPL_POWER_GATE_TIMERS_0
#define PMC_IMPL_POWER_GATE_TIMERS_0                    _MK_ADDR_CONST(0x1ec)
#define PMC_IMPL_POWER_GATE_TIMERS_0_SECURE                     0x0
#define PMC_IMPL_POWER_GATE_TIMERS_0_DUAL                       0x0
#define PMC_IMPL_POWER_GATE_TIMERS_0_SCR                        PG_COM_SCR_0
#define PMC_IMPL_POWER_GATE_TIMERS_0_WORD_COUNT                         0x1
#define PMC_IMPL_POWER_GATE_TIMERS_0_RESET_VAL                  _MK_MASK_CONST(0x101)
#define PMC_IMPL_POWER_GATE_TIMERS_0_RESET_MASK                         _MK_MASK_CONST(0xffff)
#define PMC_IMPL_POWER_GATE_TIMERS_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_POWER_GATE_TIMERS_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define PMC_IMPL_POWER_GATE_TIMERS_0_READ_MASK                  _MK_MASK_CONST(0xffff)
#define PMC_IMPL_POWER_GATE_TIMERS_0_WRITE_MASK                         _MK_MASK_CONST(0xffff)
#define PMC_IMPL_POWER_GATE_TIMERS_0_TZONE2FORCE_SHIFT                  _MK_SHIFT_CONST(0)
#define PMC_IMPL_POWER_GATE_TIMERS_0_TZONE2FORCE_FIELD                  _MK_FIELD_CONST(0xff, PMC_IMPL_POWER_GATE_TIMERS_0_TZONE2FORCE_SHIFT)
#define PMC_IMPL_POWER_GATE_TIMERS_0_TZONE2FORCE_RANGE                  7:0
#define PMC_IMPL_POWER_GATE_TIMERS_0_TZONE2FORCE_WOFFSET                        0x0
#define PMC_IMPL_POWER_GATE_TIMERS_0_TZONE2FORCE_DEFAULT                        _MK_MASK_CONST(0x1)
#define PMC_IMPL_POWER_GATE_TIMERS_0_TZONE2FORCE_DEFAULT_MASK                   _MK_MASK_CONST(0xff)
#define PMC_IMPL_POWER_GATE_TIMERS_0_TZONE2FORCE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_POWER_GATE_TIMERS_0_TZONE2FORCE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_POWER_GATE_TIMERS_0_TZONE2FORCE_PARITY_PROTECTION                      _MK_MASK_CONST(0x1)
#define PMC_IMPL_POWER_GATE_TIMERS_0_TZONE2FORCE_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)

#define PMC_IMPL_POWER_GATE_TIMERS_0_TFORCE2ZONE_SHIFT                  _MK_SHIFT_CONST(8)
#define PMC_IMPL_POWER_GATE_TIMERS_0_TFORCE2ZONE_FIELD                  _MK_FIELD_CONST(0xff, PMC_IMPL_POWER_GATE_TIMERS_0_TFORCE2ZONE_SHIFT)
#define PMC_IMPL_POWER_GATE_TIMERS_0_TFORCE2ZONE_RANGE                  15:8
#define PMC_IMPL_POWER_GATE_TIMERS_0_TFORCE2ZONE_WOFFSET                        0x0
#define PMC_IMPL_POWER_GATE_TIMERS_0_TFORCE2ZONE_DEFAULT                        _MK_MASK_CONST(0x1)
#define PMC_IMPL_POWER_GATE_TIMERS_0_TFORCE2ZONE_DEFAULT_MASK                   _MK_MASK_CONST(0xff)
#define PMC_IMPL_POWER_GATE_TIMERS_0_TFORCE2ZONE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_POWER_GATE_TIMERS_0_TFORCE2ZONE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_POWER_GATE_TIMERS_0_TFORCE2ZONE_PARITY_PROTECTION                      _MK_MASK_CONST(0x1)
#define PMC_IMPL_POWER_GATE_TIMERS_0_TFORCE2ZONE_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)


// Register PMC_IMPL_LOGIC_ZONE_DELAY_0
#define PMC_IMPL_LOGIC_ZONE_DELAY_0                     _MK_ADDR_CONST(0x1f0)
#define PMC_IMPL_LOGIC_ZONE_DELAY_0_SECURE                      0x0
#define PMC_IMPL_LOGIC_ZONE_DELAY_0_DUAL                        0x0
#define PMC_IMPL_LOGIC_ZONE_DELAY_0_SCR                         PG_COM_SCR_0
#define PMC_IMPL_LOGIC_ZONE_DELAY_0_WORD_COUNT                  0x1
#define PMC_IMPL_LOGIC_ZONE_DELAY_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_LOGIC_ZONE_DELAY_0_RESET_MASK                  _MK_MASK_CONST(0xffffffff)
#define PMC_IMPL_LOGIC_ZONE_DELAY_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_LOGIC_ZONE_DELAY_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_LOGIC_ZONE_DELAY_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
#define PMC_IMPL_LOGIC_ZONE_DELAY_0_WRITE_MASK                  _MK_MASK_CONST(0xffffffff)
#define PMC_IMPL_LOGIC_ZONE_DELAY_0_LZONE_TIMER0_SHIFT                  _MK_SHIFT_CONST(0)
#define PMC_IMPL_LOGIC_ZONE_DELAY_0_LZONE_TIMER0_FIELD                  _MK_FIELD_CONST(0xf, PMC_IMPL_LOGIC_ZONE_DELAY_0_LZONE_TIMER0_SHIFT)
#define PMC_IMPL_LOGIC_ZONE_DELAY_0_LZONE_TIMER0_RANGE                  3:0
#define PMC_IMPL_LOGIC_ZONE_DELAY_0_LZONE_TIMER0_WOFFSET                        0x0
#define PMC_IMPL_LOGIC_ZONE_DELAY_0_LZONE_TIMER0_DEFAULT                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_LOGIC_ZONE_DELAY_0_LZONE_TIMER0_DEFAULT_MASK                   _MK_MASK_CONST(0xf)
#define PMC_IMPL_LOGIC_ZONE_DELAY_0_LZONE_TIMER0_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_LOGIC_ZONE_DELAY_0_LZONE_TIMER0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_LOGIC_ZONE_DELAY_0_LZONE_TIMER0_PARITY_PROTECTION                      _MK_MASK_CONST(0x1)
#define PMC_IMPL_LOGIC_ZONE_DELAY_0_LZONE_TIMER0_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)

#define PMC_IMPL_LOGIC_ZONE_DELAY_0_LZONE_TIMER1_SHIFT                  _MK_SHIFT_CONST(4)
#define PMC_IMPL_LOGIC_ZONE_DELAY_0_LZONE_TIMER1_FIELD                  _MK_FIELD_CONST(0xf, PMC_IMPL_LOGIC_ZONE_DELAY_0_LZONE_TIMER1_SHIFT)
#define PMC_IMPL_LOGIC_ZONE_DELAY_0_LZONE_TIMER1_RANGE                  7:4
#define PMC_IMPL_LOGIC_ZONE_DELAY_0_LZONE_TIMER1_WOFFSET                        0x0
#define PMC_IMPL_LOGIC_ZONE_DELAY_0_LZONE_TIMER1_DEFAULT                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_LOGIC_ZONE_DELAY_0_LZONE_TIMER1_DEFAULT_MASK                   _MK_MASK_CONST(0xf)
#define PMC_IMPL_LOGIC_ZONE_DELAY_0_LZONE_TIMER1_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_LOGIC_ZONE_DELAY_0_LZONE_TIMER1_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_LOGIC_ZONE_DELAY_0_LZONE_TIMER1_PARITY_PROTECTION                      _MK_MASK_CONST(0x1)
#define PMC_IMPL_LOGIC_ZONE_DELAY_0_LZONE_TIMER1_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)

#define PMC_IMPL_LOGIC_ZONE_DELAY_0_LZONE_TIMER2_SHIFT                  _MK_SHIFT_CONST(8)
#define PMC_IMPL_LOGIC_ZONE_DELAY_0_LZONE_TIMER2_FIELD                  _MK_FIELD_CONST(0xf, PMC_IMPL_LOGIC_ZONE_DELAY_0_LZONE_TIMER2_SHIFT)
#define PMC_IMPL_LOGIC_ZONE_DELAY_0_LZONE_TIMER2_RANGE                  11:8
#define PMC_IMPL_LOGIC_ZONE_DELAY_0_LZONE_TIMER2_WOFFSET                        0x0
#define PMC_IMPL_LOGIC_ZONE_DELAY_0_LZONE_TIMER2_DEFAULT                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_LOGIC_ZONE_DELAY_0_LZONE_TIMER2_DEFAULT_MASK                   _MK_MASK_CONST(0xf)
#define PMC_IMPL_LOGIC_ZONE_DELAY_0_LZONE_TIMER2_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_LOGIC_ZONE_DELAY_0_LZONE_TIMER2_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_LOGIC_ZONE_DELAY_0_LZONE_TIMER2_PARITY_PROTECTION                      _MK_MASK_CONST(0x1)
#define PMC_IMPL_LOGIC_ZONE_DELAY_0_LZONE_TIMER2_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)

#define PMC_IMPL_LOGIC_ZONE_DELAY_0_LZONE_TIMER3_SHIFT                  _MK_SHIFT_CONST(12)
#define PMC_IMPL_LOGIC_ZONE_DELAY_0_LZONE_TIMER3_FIELD                  _MK_FIELD_CONST(0xf, PMC_IMPL_LOGIC_ZONE_DELAY_0_LZONE_TIMER3_SHIFT)
#define PMC_IMPL_LOGIC_ZONE_DELAY_0_LZONE_TIMER3_RANGE                  15:12
#define PMC_IMPL_LOGIC_ZONE_DELAY_0_LZONE_TIMER3_WOFFSET                        0x0
#define PMC_IMPL_LOGIC_ZONE_DELAY_0_LZONE_TIMER3_DEFAULT                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_LOGIC_ZONE_DELAY_0_LZONE_TIMER3_DEFAULT_MASK                   _MK_MASK_CONST(0xf)
#define PMC_IMPL_LOGIC_ZONE_DELAY_0_LZONE_TIMER3_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_LOGIC_ZONE_DELAY_0_LZONE_TIMER3_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_LOGIC_ZONE_DELAY_0_LZONE_TIMER3_PARITY_PROTECTION                      _MK_MASK_CONST(0x1)
#define PMC_IMPL_LOGIC_ZONE_DELAY_0_LZONE_TIMER3_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)

#define PMC_IMPL_LOGIC_ZONE_DELAY_0_LZONE_TIMER4_SHIFT                  _MK_SHIFT_CONST(16)
#define PMC_IMPL_LOGIC_ZONE_DELAY_0_LZONE_TIMER4_FIELD                  _MK_FIELD_CONST(0xf, PMC_IMPL_LOGIC_ZONE_DELAY_0_LZONE_TIMER4_SHIFT)
#define PMC_IMPL_LOGIC_ZONE_DELAY_0_LZONE_TIMER4_RANGE                  19:16
#define PMC_IMPL_LOGIC_ZONE_DELAY_0_LZONE_TIMER4_WOFFSET                        0x0
#define PMC_IMPL_LOGIC_ZONE_DELAY_0_LZONE_TIMER4_DEFAULT                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_LOGIC_ZONE_DELAY_0_LZONE_TIMER4_DEFAULT_MASK                   _MK_MASK_CONST(0xf)
#define PMC_IMPL_LOGIC_ZONE_DELAY_0_LZONE_TIMER4_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_LOGIC_ZONE_DELAY_0_LZONE_TIMER4_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_LOGIC_ZONE_DELAY_0_LZONE_TIMER4_PARITY_PROTECTION                      _MK_MASK_CONST(0x1)
#define PMC_IMPL_LOGIC_ZONE_DELAY_0_LZONE_TIMER4_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)

#define PMC_IMPL_LOGIC_ZONE_DELAY_0_LZONE_TIMER5_SHIFT                  _MK_SHIFT_CONST(20)
#define PMC_IMPL_LOGIC_ZONE_DELAY_0_LZONE_TIMER5_FIELD                  _MK_FIELD_CONST(0xf, PMC_IMPL_LOGIC_ZONE_DELAY_0_LZONE_TIMER5_SHIFT)
#define PMC_IMPL_LOGIC_ZONE_DELAY_0_LZONE_TIMER5_RANGE                  23:20
#define PMC_IMPL_LOGIC_ZONE_DELAY_0_LZONE_TIMER5_WOFFSET                        0x0
#define PMC_IMPL_LOGIC_ZONE_DELAY_0_LZONE_TIMER5_DEFAULT                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_LOGIC_ZONE_DELAY_0_LZONE_TIMER5_DEFAULT_MASK                   _MK_MASK_CONST(0xf)
#define PMC_IMPL_LOGIC_ZONE_DELAY_0_LZONE_TIMER5_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_LOGIC_ZONE_DELAY_0_LZONE_TIMER5_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_LOGIC_ZONE_DELAY_0_LZONE_TIMER5_PARITY_PROTECTION                      _MK_MASK_CONST(0x1)
#define PMC_IMPL_LOGIC_ZONE_DELAY_0_LZONE_TIMER5_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)

#define PMC_IMPL_LOGIC_ZONE_DELAY_0_LZONE_TIMER6_SHIFT                  _MK_SHIFT_CONST(24)
#define PMC_IMPL_LOGIC_ZONE_DELAY_0_LZONE_TIMER6_FIELD                  _MK_FIELD_CONST(0xf, PMC_IMPL_LOGIC_ZONE_DELAY_0_LZONE_TIMER6_SHIFT)
#define PMC_IMPL_LOGIC_ZONE_DELAY_0_LZONE_TIMER6_RANGE                  27:24
#define PMC_IMPL_LOGIC_ZONE_DELAY_0_LZONE_TIMER6_WOFFSET                        0x0
#define PMC_IMPL_LOGIC_ZONE_DELAY_0_LZONE_TIMER6_DEFAULT                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_LOGIC_ZONE_DELAY_0_LZONE_TIMER6_DEFAULT_MASK                   _MK_MASK_CONST(0xf)
#define PMC_IMPL_LOGIC_ZONE_DELAY_0_LZONE_TIMER6_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_LOGIC_ZONE_DELAY_0_LZONE_TIMER6_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_LOGIC_ZONE_DELAY_0_LZONE_TIMER6_PARITY_PROTECTION                      _MK_MASK_CONST(0x1)
#define PMC_IMPL_LOGIC_ZONE_DELAY_0_LZONE_TIMER6_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)

#define PMC_IMPL_LOGIC_ZONE_DELAY_0_LZONE_TIMER7_SHIFT                  _MK_SHIFT_CONST(28)
#define PMC_IMPL_LOGIC_ZONE_DELAY_0_LZONE_TIMER7_FIELD                  _MK_FIELD_CONST(0xf, PMC_IMPL_LOGIC_ZONE_DELAY_0_LZONE_TIMER7_SHIFT)
#define PMC_IMPL_LOGIC_ZONE_DELAY_0_LZONE_TIMER7_RANGE                  31:28
#define PMC_IMPL_LOGIC_ZONE_DELAY_0_LZONE_TIMER7_WOFFSET                        0x0
#define PMC_IMPL_LOGIC_ZONE_DELAY_0_LZONE_TIMER7_DEFAULT                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_LOGIC_ZONE_DELAY_0_LZONE_TIMER7_DEFAULT_MASK                   _MK_MASK_CONST(0xf)
#define PMC_IMPL_LOGIC_ZONE_DELAY_0_LZONE_TIMER7_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_LOGIC_ZONE_DELAY_0_LZONE_TIMER7_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_LOGIC_ZONE_DELAY_0_LZONE_TIMER7_PARITY_PROTECTION                      _MK_MASK_CONST(0x1)
#define PMC_IMPL_LOGIC_ZONE_DELAY_0_LZONE_TIMER7_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)


// Register PMC_IMPL_SRAM_ZONE_DELAY_0
#define PMC_IMPL_SRAM_ZONE_DELAY_0                      _MK_ADDR_CONST(0x1f4)
#define PMC_IMPL_SRAM_ZONE_DELAY_0_SECURE                       0x0
#define PMC_IMPL_SRAM_ZONE_DELAY_0_DUAL                         0x0
#define PMC_IMPL_SRAM_ZONE_DELAY_0_SCR                  PG_COM_SCR_0
#define PMC_IMPL_SRAM_ZONE_DELAY_0_WORD_COUNT                   0x1
#define PMC_IMPL_SRAM_ZONE_DELAY_0_RESET_VAL                    _MK_MASK_CONST(0x0)
#define PMC_IMPL_SRAM_ZONE_DELAY_0_RESET_MASK                   _MK_MASK_CONST(0xffffffff)
#define PMC_IMPL_SRAM_ZONE_DELAY_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define PMC_IMPL_SRAM_ZONE_DELAY_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_SRAM_ZONE_DELAY_0_READ_MASK                    _MK_MASK_CONST(0xffffffff)
#define PMC_IMPL_SRAM_ZONE_DELAY_0_WRITE_MASK                   _MK_MASK_CONST(0xffffffff)
#define PMC_IMPL_SRAM_ZONE_DELAY_0_SZONE_TIMER0_SHIFT                   _MK_SHIFT_CONST(0)
#define PMC_IMPL_SRAM_ZONE_DELAY_0_SZONE_TIMER0_FIELD                   _MK_FIELD_CONST(0xf, PMC_IMPL_SRAM_ZONE_DELAY_0_SZONE_TIMER0_SHIFT)
#define PMC_IMPL_SRAM_ZONE_DELAY_0_SZONE_TIMER0_RANGE                   3:0
#define PMC_IMPL_SRAM_ZONE_DELAY_0_SZONE_TIMER0_WOFFSET                 0x0
#define PMC_IMPL_SRAM_ZONE_DELAY_0_SZONE_TIMER0_DEFAULT                 _MK_MASK_CONST(0x0)
#define PMC_IMPL_SRAM_ZONE_DELAY_0_SZONE_TIMER0_DEFAULT_MASK                    _MK_MASK_CONST(0xf)
#define PMC_IMPL_SRAM_ZONE_DELAY_0_SZONE_TIMER0_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_SRAM_ZONE_DELAY_0_SZONE_TIMER0_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define PMC_IMPL_SRAM_ZONE_DELAY_0_SZONE_TIMER0_PARITY_PROTECTION                       _MK_MASK_CONST(0x1)
#define PMC_IMPL_SRAM_ZONE_DELAY_0_SZONE_TIMER0_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define PMC_IMPL_SRAM_ZONE_DELAY_0_SZONE_TIMER1_SHIFT                   _MK_SHIFT_CONST(4)
#define PMC_IMPL_SRAM_ZONE_DELAY_0_SZONE_TIMER1_FIELD                   _MK_FIELD_CONST(0xf, PMC_IMPL_SRAM_ZONE_DELAY_0_SZONE_TIMER1_SHIFT)
#define PMC_IMPL_SRAM_ZONE_DELAY_0_SZONE_TIMER1_RANGE                   7:4
#define PMC_IMPL_SRAM_ZONE_DELAY_0_SZONE_TIMER1_WOFFSET                 0x0
#define PMC_IMPL_SRAM_ZONE_DELAY_0_SZONE_TIMER1_DEFAULT                 _MK_MASK_CONST(0x0)
#define PMC_IMPL_SRAM_ZONE_DELAY_0_SZONE_TIMER1_DEFAULT_MASK                    _MK_MASK_CONST(0xf)
#define PMC_IMPL_SRAM_ZONE_DELAY_0_SZONE_TIMER1_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_SRAM_ZONE_DELAY_0_SZONE_TIMER1_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define PMC_IMPL_SRAM_ZONE_DELAY_0_SZONE_TIMER1_PARITY_PROTECTION                       _MK_MASK_CONST(0x1)
#define PMC_IMPL_SRAM_ZONE_DELAY_0_SZONE_TIMER1_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define PMC_IMPL_SRAM_ZONE_DELAY_0_SZONE_TIMER2_SHIFT                   _MK_SHIFT_CONST(8)
#define PMC_IMPL_SRAM_ZONE_DELAY_0_SZONE_TIMER2_FIELD                   _MK_FIELD_CONST(0xf, PMC_IMPL_SRAM_ZONE_DELAY_0_SZONE_TIMER2_SHIFT)
#define PMC_IMPL_SRAM_ZONE_DELAY_0_SZONE_TIMER2_RANGE                   11:8
#define PMC_IMPL_SRAM_ZONE_DELAY_0_SZONE_TIMER2_WOFFSET                 0x0
#define PMC_IMPL_SRAM_ZONE_DELAY_0_SZONE_TIMER2_DEFAULT                 _MK_MASK_CONST(0x0)
#define PMC_IMPL_SRAM_ZONE_DELAY_0_SZONE_TIMER2_DEFAULT_MASK                    _MK_MASK_CONST(0xf)
#define PMC_IMPL_SRAM_ZONE_DELAY_0_SZONE_TIMER2_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_SRAM_ZONE_DELAY_0_SZONE_TIMER2_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define PMC_IMPL_SRAM_ZONE_DELAY_0_SZONE_TIMER2_PARITY_PROTECTION                       _MK_MASK_CONST(0x1)
#define PMC_IMPL_SRAM_ZONE_DELAY_0_SZONE_TIMER2_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define PMC_IMPL_SRAM_ZONE_DELAY_0_SZONE_TIMER3_SHIFT                   _MK_SHIFT_CONST(12)
#define PMC_IMPL_SRAM_ZONE_DELAY_0_SZONE_TIMER3_FIELD                   _MK_FIELD_CONST(0xf, PMC_IMPL_SRAM_ZONE_DELAY_0_SZONE_TIMER3_SHIFT)
#define PMC_IMPL_SRAM_ZONE_DELAY_0_SZONE_TIMER3_RANGE                   15:12
#define PMC_IMPL_SRAM_ZONE_DELAY_0_SZONE_TIMER3_WOFFSET                 0x0
#define PMC_IMPL_SRAM_ZONE_DELAY_0_SZONE_TIMER3_DEFAULT                 _MK_MASK_CONST(0x0)
#define PMC_IMPL_SRAM_ZONE_DELAY_0_SZONE_TIMER3_DEFAULT_MASK                    _MK_MASK_CONST(0xf)
#define PMC_IMPL_SRAM_ZONE_DELAY_0_SZONE_TIMER3_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_SRAM_ZONE_DELAY_0_SZONE_TIMER3_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define PMC_IMPL_SRAM_ZONE_DELAY_0_SZONE_TIMER3_PARITY_PROTECTION                       _MK_MASK_CONST(0x1)
#define PMC_IMPL_SRAM_ZONE_DELAY_0_SZONE_TIMER3_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define PMC_IMPL_SRAM_ZONE_DELAY_0_SZONE_TIMER4_SHIFT                   _MK_SHIFT_CONST(16)
#define PMC_IMPL_SRAM_ZONE_DELAY_0_SZONE_TIMER4_FIELD                   _MK_FIELD_CONST(0xf, PMC_IMPL_SRAM_ZONE_DELAY_0_SZONE_TIMER4_SHIFT)
#define PMC_IMPL_SRAM_ZONE_DELAY_0_SZONE_TIMER4_RANGE                   19:16
#define PMC_IMPL_SRAM_ZONE_DELAY_0_SZONE_TIMER4_WOFFSET                 0x0
#define PMC_IMPL_SRAM_ZONE_DELAY_0_SZONE_TIMER4_DEFAULT                 _MK_MASK_CONST(0x0)
#define PMC_IMPL_SRAM_ZONE_DELAY_0_SZONE_TIMER4_DEFAULT_MASK                    _MK_MASK_CONST(0xf)
#define PMC_IMPL_SRAM_ZONE_DELAY_0_SZONE_TIMER4_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_SRAM_ZONE_DELAY_0_SZONE_TIMER4_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define PMC_IMPL_SRAM_ZONE_DELAY_0_SZONE_TIMER4_PARITY_PROTECTION                       _MK_MASK_CONST(0x1)
#define PMC_IMPL_SRAM_ZONE_DELAY_0_SZONE_TIMER4_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define PMC_IMPL_SRAM_ZONE_DELAY_0_SZONE_TIMER5_SHIFT                   _MK_SHIFT_CONST(20)
#define PMC_IMPL_SRAM_ZONE_DELAY_0_SZONE_TIMER5_FIELD                   _MK_FIELD_CONST(0xf, PMC_IMPL_SRAM_ZONE_DELAY_0_SZONE_TIMER5_SHIFT)
#define PMC_IMPL_SRAM_ZONE_DELAY_0_SZONE_TIMER5_RANGE                   23:20
#define PMC_IMPL_SRAM_ZONE_DELAY_0_SZONE_TIMER5_WOFFSET                 0x0
#define PMC_IMPL_SRAM_ZONE_DELAY_0_SZONE_TIMER5_DEFAULT                 _MK_MASK_CONST(0x0)
#define PMC_IMPL_SRAM_ZONE_DELAY_0_SZONE_TIMER5_DEFAULT_MASK                    _MK_MASK_CONST(0xf)
#define PMC_IMPL_SRAM_ZONE_DELAY_0_SZONE_TIMER5_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_SRAM_ZONE_DELAY_0_SZONE_TIMER5_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define PMC_IMPL_SRAM_ZONE_DELAY_0_SZONE_TIMER5_PARITY_PROTECTION                       _MK_MASK_CONST(0x1)
#define PMC_IMPL_SRAM_ZONE_DELAY_0_SZONE_TIMER5_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define PMC_IMPL_SRAM_ZONE_DELAY_0_SZONE_TIMER6_SHIFT                   _MK_SHIFT_CONST(24)
#define PMC_IMPL_SRAM_ZONE_DELAY_0_SZONE_TIMER6_FIELD                   _MK_FIELD_CONST(0xf, PMC_IMPL_SRAM_ZONE_DELAY_0_SZONE_TIMER6_SHIFT)
#define PMC_IMPL_SRAM_ZONE_DELAY_0_SZONE_TIMER6_RANGE                   27:24
#define PMC_IMPL_SRAM_ZONE_DELAY_0_SZONE_TIMER6_WOFFSET                 0x0
#define PMC_IMPL_SRAM_ZONE_DELAY_0_SZONE_TIMER6_DEFAULT                 _MK_MASK_CONST(0x0)
#define PMC_IMPL_SRAM_ZONE_DELAY_0_SZONE_TIMER6_DEFAULT_MASK                    _MK_MASK_CONST(0xf)
#define PMC_IMPL_SRAM_ZONE_DELAY_0_SZONE_TIMER6_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_SRAM_ZONE_DELAY_0_SZONE_TIMER6_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define PMC_IMPL_SRAM_ZONE_DELAY_0_SZONE_TIMER6_PARITY_PROTECTION                       _MK_MASK_CONST(0x1)
#define PMC_IMPL_SRAM_ZONE_DELAY_0_SZONE_TIMER6_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define PMC_IMPL_SRAM_ZONE_DELAY_0_SZONE_TIMER7_SHIFT                   _MK_SHIFT_CONST(28)
#define PMC_IMPL_SRAM_ZONE_DELAY_0_SZONE_TIMER7_FIELD                   _MK_FIELD_CONST(0xf, PMC_IMPL_SRAM_ZONE_DELAY_0_SZONE_TIMER7_SHIFT)
#define PMC_IMPL_SRAM_ZONE_DELAY_0_SZONE_TIMER7_RANGE                   31:28
#define PMC_IMPL_SRAM_ZONE_DELAY_0_SZONE_TIMER7_WOFFSET                 0x0
#define PMC_IMPL_SRAM_ZONE_DELAY_0_SZONE_TIMER7_DEFAULT                 _MK_MASK_CONST(0x0)
#define PMC_IMPL_SRAM_ZONE_DELAY_0_SZONE_TIMER7_DEFAULT_MASK                    _MK_MASK_CONST(0xf)
#define PMC_IMPL_SRAM_ZONE_DELAY_0_SZONE_TIMER7_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_SRAM_ZONE_DELAY_0_SZONE_TIMER7_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define PMC_IMPL_SRAM_ZONE_DELAY_0_SZONE_TIMER7_PARITY_PROTECTION                       _MK_MASK_CONST(0x1)
#define PMC_IMPL_SRAM_ZONE_DELAY_0_SZONE_TIMER7_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)


// Register PMC_IMPL_ZONE_CONFIG_0
#define PMC_IMPL_ZONE_CONFIG_0                  _MK_ADDR_CONST(0x1f8)
#define PMC_IMPL_ZONE_CONFIG_0_SECURE                   0x0
#define PMC_IMPL_ZONE_CONFIG_0_DUAL                     0x0
#define PMC_IMPL_ZONE_CONFIG_0_SCR                      PG_COM_SCR_0
#define PMC_IMPL_ZONE_CONFIG_0_WORD_COUNT                       0x1
#define PMC_IMPL_ZONE_CONFIG_0_RESET_VAL                        _MK_MASK_CONST(0x3)
#define PMC_IMPL_ZONE_CONFIG_0_RESET_MASK                       _MK_MASK_CONST(0xf)
#define PMC_IMPL_ZONE_CONFIG_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_ZONE_CONFIG_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define PMC_IMPL_ZONE_CONFIG_0_READ_MASK                        _MK_MASK_CONST(0xf)
#define PMC_IMPL_ZONE_CONFIG_0_WRITE_MASK                       _MK_MASK_CONST(0xf)
#define PMC_IMPL_ZONE_CONFIG_0_LOGIC_SLEEP_ZONE_EN_SHIFT                        _MK_SHIFT_CONST(0)
#define PMC_IMPL_ZONE_CONFIG_0_LOGIC_SLEEP_ZONE_EN_FIELD                        _MK_FIELD_CONST(0x1, PMC_IMPL_ZONE_CONFIG_0_LOGIC_SLEEP_ZONE_EN_SHIFT)
#define PMC_IMPL_ZONE_CONFIG_0_LOGIC_SLEEP_ZONE_EN_RANGE                        0:0
#define PMC_IMPL_ZONE_CONFIG_0_LOGIC_SLEEP_ZONE_EN_WOFFSET                      0x0
#define PMC_IMPL_ZONE_CONFIG_0_LOGIC_SLEEP_ZONE_EN_DEFAULT                      _MK_MASK_CONST(0x1)
#define PMC_IMPL_ZONE_CONFIG_0_LOGIC_SLEEP_ZONE_EN_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define PMC_IMPL_ZONE_CONFIG_0_LOGIC_SLEEP_ZONE_EN_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_ZONE_CONFIG_0_LOGIC_SLEEP_ZONE_EN_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_ZONE_CONFIG_0_LOGIC_SLEEP_ZONE_EN_PARITY_PROTECTION                    _MK_MASK_CONST(0x1)
#define PMC_IMPL_ZONE_CONFIG_0_LOGIC_SLEEP_ZONE_EN_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)
#define PMC_IMPL_ZONE_CONFIG_0_LOGIC_SLEEP_ZONE_EN_INIT_ENUM                    ENABLE
#define PMC_IMPL_ZONE_CONFIG_0_LOGIC_SLEEP_ZONE_EN_DISABLE                      _MK_ENUM_CONST(0)
#define PMC_IMPL_ZONE_CONFIG_0_LOGIC_SLEEP_ZONE_EN_ENABLE                       _MK_ENUM_CONST(1)

#define PMC_IMPL_ZONE_CONFIG_0_SRAM_SLEEP_ZONE_EN_SHIFT                 _MK_SHIFT_CONST(1)
#define PMC_IMPL_ZONE_CONFIG_0_SRAM_SLEEP_ZONE_EN_FIELD                 _MK_FIELD_CONST(0x1, PMC_IMPL_ZONE_CONFIG_0_SRAM_SLEEP_ZONE_EN_SHIFT)
#define PMC_IMPL_ZONE_CONFIG_0_SRAM_SLEEP_ZONE_EN_RANGE                 1:1
#define PMC_IMPL_ZONE_CONFIG_0_SRAM_SLEEP_ZONE_EN_WOFFSET                       0x0
#define PMC_IMPL_ZONE_CONFIG_0_SRAM_SLEEP_ZONE_EN_DEFAULT                       _MK_MASK_CONST(0x1)
#define PMC_IMPL_ZONE_CONFIG_0_SRAM_SLEEP_ZONE_EN_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define PMC_IMPL_ZONE_CONFIG_0_SRAM_SLEEP_ZONE_EN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define PMC_IMPL_ZONE_CONFIG_0_SRAM_SLEEP_ZONE_EN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define PMC_IMPL_ZONE_CONFIG_0_SRAM_SLEEP_ZONE_EN_PARITY_PROTECTION                     _MK_MASK_CONST(0x1)
#define PMC_IMPL_ZONE_CONFIG_0_SRAM_SLEEP_ZONE_EN_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)
#define PMC_IMPL_ZONE_CONFIG_0_SRAM_SLEEP_ZONE_EN_INIT_ENUM                     ENABLE
#define PMC_IMPL_ZONE_CONFIG_0_SRAM_SLEEP_ZONE_EN_DISABLE                       _MK_ENUM_CONST(0)
#define PMC_IMPL_ZONE_CONFIG_0_SRAM_SLEEP_ZONE_EN_ENABLE                        _MK_ENUM_CONST(1)

#define PMC_IMPL_ZONE_CONFIG_0_SRAM_PWR_UP_ZONE_EN_SHIFT                        _MK_SHIFT_CONST(2)
#define PMC_IMPL_ZONE_CONFIG_0_SRAM_PWR_UP_ZONE_EN_FIELD                        _MK_FIELD_CONST(0x1, PMC_IMPL_ZONE_CONFIG_0_SRAM_PWR_UP_ZONE_EN_SHIFT)
#define PMC_IMPL_ZONE_CONFIG_0_SRAM_PWR_UP_ZONE_EN_RANGE                        2:2
#define PMC_IMPL_ZONE_CONFIG_0_SRAM_PWR_UP_ZONE_EN_WOFFSET                      0x0
#define PMC_IMPL_ZONE_CONFIG_0_SRAM_PWR_UP_ZONE_EN_DEFAULT                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_ZONE_CONFIG_0_SRAM_PWR_UP_ZONE_EN_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define PMC_IMPL_ZONE_CONFIG_0_SRAM_PWR_UP_ZONE_EN_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_ZONE_CONFIG_0_SRAM_PWR_UP_ZONE_EN_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_ZONE_CONFIG_0_SRAM_PWR_UP_ZONE_EN_PARITY_PROTECTION                    _MK_MASK_CONST(0x1)
#define PMC_IMPL_ZONE_CONFIG_0_SRAM_PWR_UP_ZONE_EN_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)
#define PMC_IMPL_ZONE_CONFIG_0_SRAM_PWR_UP_ZONE_EN_INIT_ENUM                    DISABLE
#define PMC_IMPL_ZONE_CONFIG_0_SRAM_PWR_UP_ZONE_EN_DISABLE                      _MK_ENUM_CONST(0)
#define PMC_IMPL_ZONE_CONFIG_0_SRAM_PWR_UP_ZONE_EN_ENABLE                       _MK_ENUM_CONST(1)

#define PMC_IMPL_ZONE_CONFIG_0_SRAM_PWR_DOWN_ZONE_EN_SHIFT                      _MK_SHIFT_CONST(3)
#define PMC_IMPL_ZONE_CONFIG_0_SRAM_PWR_DOWN_ZONE_EN_FIELD                      _MK_FIELD_CONST(0x1, PMC_IMPL_ZONE_CONFIG_0_SRAM_PWR_DOWN_ZONE_EN_SHIFT)
#define PMC_IMPL_ZONE_CONFIG_0_SRAM_PWR_DOWN_ZONE_EN_RANGE                      3:3
#define PMC_IMPL_ZONE_CONFIG_0_SRAM_PWR_DOWN_ZONE_EN_WOFFSET                    0x0
#define PMC_IMPL_ZONE_CONFIG_0_SRAM_PWR_DOWN_ZONE_EN_DEFAULT                    _MK_MASK_CONST(0x0)
#define PMC_IMPL_ZONE_CONFIG_0_SRAM_PWR_DOWN_ZONE_EN_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define PMC_IMPL_ZONE_CONFIG_0_SRAM_PWR_DOWN_ZONE_EN_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define PMC_IMPL_ZONE_CONFIG_0_SRAM_PWR_DOWN_ZONE_EN_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define PMC_IMPL_ZONE_CONFIG_0_SRAM_PWR_DOWN_ZONE_EN_PARITY_PROTECTION                  _MK_MASK_CONST(0x1)
#define PMC_IMPL_ZONE_CONFIG_0_SRAM_PWR_DOWN_ZONE_EN_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define PMC_IMPL_ZONE_CONFIG_0_SRAM_PWR_DOWN_ZONE_EN_INIT_ENUM                  DISABLE
#define PMC_IMPL_ZONE_CONFIG_0_SRAM_PWR_DOWN_ZONE_EN_DISABLE                    _MK_ENUM_CONST(0)
#define PMC_IMPL_ZONE_CONFIG_0_SRAM_PWR_DOWN_ZONE_EN_ENABLE                     _MK_ENUM_CONST(1)


// Register PMC_IMPL_INTER_PARTITION_PG_DELAY_0
#define PMC_IMPL_INTER_PARTITION_PG_DELAY_0                     _MK_ADDR_CONST(0x1fc)
#define PMC_IMPL_INTER_PARTITION_PG_DELAY_0_SECURE                      0x0
#define PMC_IMPL_INTER_PARTITION_PG_DELAY_0_DUAL                        0x0
#define PMC_IMPL_INTER_PARTITION_PG_DELAY_0_SCR                         PG_COM_SCR_0
#define PMC_IMPL_INTER_PARTITION_PG_DELAY_0_WORD_COUNT                  0x1
#define PMC_IMPL_INTER_PARTITION_PG_DELAY_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_INTER_PARTITION_PG_DELAY_0_RESET_MASK                  _MK_MASK_CONST(0xff)
#define PMC_IMPL_INTER_PARTITION_PG_DELAY_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_INTER_PARTITION_PG_DELAY_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_INTER_PARTITION_PG_DELAY_0_READ_MASK                   _MK_MASK_CONST(0xff)
#define PMC_IMPL_INTER_PARTITION_PG_DELAY_0_WRITE_MASK                  _MK_MASK_CONST(0xff)
#define PMC_IMPL_INTER_PARTITION_PG_DELAY_0_INTER_PART_DELAY_SHIFT                      _MK_SHIFT_CONST(0)
#define PMC_IMPL_INTER_PARTITION_PG_DELAY_0_INTER_PART_DELAY_FIELD                      _MK_FIELD_CONST(0xff, PMC_IMPL_INTER_PARTITION_PG_DELAY_0_INTER_PART_DELAY_SHIFT)
#define PMC_IMPL_INTER_PARTITION_PG_DELAY_0_INTER_PART_DELAY_RANGE                      7:0
#define PMC_IMPL_INTER_PARTITION_PG_DELAY_0_INTER_PART_DELAY_WOFFSET                    0x0
#define PMC_IMPL_INTER_PARTITION_PG_DELAY_0_INTER_PART_DELAY_DEFAULT                    _MK_MASK_CONST(0x0)
#define PMC_IMPL_INTER_PARTITION_PG_DELAY_0_INTER_PART_DELAY_DEFAULT_MASK                       _MK_MASK_CONST(0xff)
#define PMC_IMPL_INTER_PARTITION_PG_DELAY_0_INTER_PART_DELAY_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define PMC_IMPL_INTER_PARTITION_PG_DELAY_0_INTER_PART_DELAY_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define PMC_IMPL_INTER_PARTITION_PG_DELAY_0_INTER_PART_DELAY_PARITY_PROTECTION                  _MK_MASK_CONST(0x1)
#define PMC_IMPL_INTER_PARTITION_PG_DELAY_0_INTER_PART_DELAY_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)


// Register PMC_IMPL_AO_PG_TIMERS_0
#define PMC_IMPL_AO_PG_TIMERS_0                 _MK_ADDR_CONST(0x200)
#define PMC_IMPL_AO_PG_TIMERS_0_SECURE                  0x0
#define PMC_IMPL_AO_PG_TIMERS_0_DUAL                    0x0
#define PMC_IMPL_AO_PG_TIMERS_0_SCR                     PG_COM_SCR_0
#define PMC_IMPL_AO_PG_TIMERS_0_WORD_COUNT                      0x1
#define PMC_IMPL_AO_PG_TIMERS_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define PMC_IMPL_AO_PG_TIMERS_0_RESET_MASK                      _MK_MASK_CONST(0xffff)
#define PMC_IMPL_AO_PG_TIMERS_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define PMC_IMPL_AO_PG_TIMERS_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define PMC_IMPL_AO_PG_TIMERS_0_READ_MASK                       _MK_MASK_CONST(0xffff)
#define PMC_IMPL_AO_PG_TIMERS_0_WRITE_MASK                      _MK_MASK_CONST(0xffff)
#define PMC_IMPL_AO_PG_TIMERS_0_CLAMP2LSLEEP_DELAY_SHIFT                        _MK_SHIFT_CONST(0)
#define PMC_IMPL_AO_PG_TIMERS_0_CLAMP2LSLEEP_DELAY_FIELD                        _MK_FIELD_CONST(0xff, PMC_IMPL_AO_PG_TIMERS_0_CLAMP2LSLEEP_DELAY_SHIFT)
#define PMC_IMPL_AO_PG_TIMERS_0_CLAMP2LSLEEP_DELAY_RANGE                        7:0
#define PMC_IMPL_AO_PG_TIMERS_0_CLAMP2LSLEEP_DELAY_WOFFSET                      0x0
#define PMC_IMPL_AO_PG_TIMERS_0_CLAMP2LSLEEP_DELAY_DEFAULT                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_AO_PG_TIMERS_0_CLAMP2LSLEEP_DELAY_DEFAULT_MASK                 _MK_MASK_CONST(0xff)
#define PMC_IMPL_AO_PG_TIMERS_0_CLAMP2LSLEEP_DELAY_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_AO_PG_TIMERS_0_CLAMP2LSLEEP_DELAY_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_AO_PG_TIMERS_0_CLAMP2LSLEEP_DELAY_PARITY_PROTECTION                    _MK_MASK_CONST(0x1)
#define PMC_IMPL_AO_PG_TIMERS_0_CLAMP2LSLEEP_DELAY_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define PMC_IMPL_AO_PG_TIMERS_0_LSLEEP2CLAMP_DELAY_SHIFT                        _MK_SHIFT_CONST(8)
#define PMC_IMPL_AO_PG_TIMERS_0_LSLEEP2CLAMP_DELAY_FIELD                        _MK_FIELD_CONST(0xff, PMC_IMPL_AO_PG_TIMERS_0_LSLEEP2CLAMP_DELAY_SHIFT)
#define PMC_IMPL_AO_PG_TIMERS_0_LSLEEP2CLAMP_DELAY_RANGE                        15:8
#define PMC_IMPL_AO_PG_TIMERS_0_LSLEEP2CLAMP_DELAY_WOFFSET                      0x0
#define PMC_IMPL_AO_PG_TIMERS_0_LSLEEP2CLAMP_DELAY_DEFAULT                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_AO_PG_TIMERS_0_LSLEEP2CLAMP_DELAY_DEFAULT_MASK                 _MK_MASK_CONST(0xff)
#define PMC_IMPL_AO_PG_TIMERS_0_LSLEEP2CLAMP_DELAY_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_AO_PG_TIMERS_0_LSLEEP2CLAMP_DELAY_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_AO_PG_TIMERS_0_LSLEEP2CLAMP_DELAY_PARITY_PROTECTION                    _MK_MASK_CONST(0x1)
#define PMC_IMPL_AO_PG_TIMERS_0_LSLEEP2CLAMP_DELAY_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)


// Register PMC_IMPL_PG_STATUS_0
#define PMC_IMPL_PG_STATUS_0                    _MK_ADDR_CONST(0x204)
#define PMC_IMPL_PG_STATUS_0_SECURE                     0x0
#define PMC_IMPL_PG_STATUS_0_DUAL                       0x0
#define PMC_IMPL_PG_STATUS_0_SCR                        PG_COM_SCR_0
#define PMC_IMPL_PG_STATUS_0_WORD_COUNT                         0x1
#define PMC_IMPL_PG_STATUS_0_RESET_VAL                  _MK_MASK_CONST(0x2)
#define PMC_IMPL_PG_STATUS_0_RESET_MASK                         _MK_MASK_CONST(0x3f)
#define PMC_IMPL_PG_STATUS_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_PG_STATUS_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define PMC_IMPL_PG_STATUS_0_READ_MASK                  _MK_MASK_CONST(0x3f)
#define PMC_IMPL_PG_STATUS_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
#define PMC_IMPL_PG_STATUS_0_PENDING_START_SHIFT                        _MK_SHIFT_CONST(0)
#define PMC_IMPL_PG_STATUS_0_PENDING_START_FIELD                        _MK_FIELD_CONST(0x1, PMC_IMPL_PG_STATUS_0_PENDING_START_SHIFT)
#define PMC_IMPL_PG_STATUS_0_PENDING_START_RANGE                        0:0
#define PMC_IMPL_PG_STATUS_0_PENDING_START_WOFFSET                      0x0
#define PMC_IMPL_PG_STATUS_0_PENDING_START_DEFAULT                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_PG_STATUS_0_PENDING_START_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define PMC_IMPL_PG_STATUS_0_PENDING_START_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_PG_STATUS_0_PENDING_START_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_PG_STATUS_0_PENDING_START_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define PMC_IMPL_PG_STATUS_0_PENDING_START_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)
#define PMC_IMPL_PG_STATUS_0_PENDING_START_INIT_ENUM                    DONE
#define PMC_IMPL_PG_STATUS_0_PENDING_START_DONE                 _MK_ENUM_CONST(0)
#define PMC_IMPL_PG_STATUS_0_PENDING_START_PENDING                      _MK_ENUM_CONST(1)

#define PMC_IMPL_PG_STATUS_0_PENDING_RESET_SLEEP_START_SHIFT                    _MK_SHIFT_CONST(1)
#define PMC_IMPL_PG_STATUS_0_PENDING_RESET_SLEEP_START_FIELD                    _MK_FIELD_CONST(0x1, PMC_IMPL_PG_STATUS_0_PENDING_RESET_SLEEP_START_SHIFT)
#define PMC_IMPL_PG_STATUS_0_PENDING_RESET_SLEEP_START_RANGE                    1:1
#define PMC_IMPL_PG_STATUS_0_PENDING_RESET_SLEEP_START_WOFFSET                  0x0
#define PMC_IMPL_PG_STATUS_0_PENDING_RESET_SLEEP_START_DEFAULT                  _MK_MASK_CONST(0x1)
#define PMC_IMPL_PG_STATUS_0_PENDING_RESET_SLEEP_START_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define PMC_IMPL_PG_STATUS_0_PENDING_RESET_SLEEP_START_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define PMC_IMPL_PG_STATUS_0_PENDING_RESET_SLEEP_START_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define PMC_IMPL_PG_STATUS_0_PENDING_RESET_SLEEP_START_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_PG_STATUS_0_PENDING_RESET_SLEEP_START_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)
#define PMC_IMPL_PG_STATUS_0_PENDING_RESET_SLEEP_START_INIT_ENUM                        PENDING
#define PMC_IMPL_PG_STATUS_0_PENDING_RESET_SLEEP_START_DONE                     _MK_ENUM_CONST(0)
#define PMC_IMPL_PG_STATUS_0_PENDING_RESET_SLEEP_START_PENDING                  _MK_ENUM_CONST(1)

#define PMC_IMPL_PG_STATUS_0_PENDING_SC7_ASSERT_SLEEP_START_SHIFT                       _MK_SHIFT_CONST(2)
#define PMC_IMPL_PG_STATUS_0_PENDING_SC7_ASSERT_SLEEP_START_FIELD                       _MK_FIELD_CONST(0x1, PMC_IMPL_PG_STATUS_0_PENDING_SC7_ASSERT_SLEEP_START_SHIFT)
#define PMC_IMPL_PG_STATUS_0_PENDING_SC7_ASSERT_SLEEP_START_RANGE                       2:2
#define PMC_IMPL_PG_STATUS_0_PENDING_SC7_ASSERT_SLEEP_START_WOFFSET                     0x0
#define PMC_IMPL_PG_STATUS_0_PENDING_SC7_ASSERT_SLEEP_START_DEFAULT                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_PG_STATUS_0_PENDING_SC7_ASSERT_SLEEP_START_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define PMC_IMPL_PG_STATUS_0_PENDING_SC7_ASSERT_SLEEP_START_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define PMC_IMPL_PG_STATUS_0_PENDING_SC7_ASSERT_SLEEP_START_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_PG_STATUS_0_PENDING_SC7_ASSERT_SLEEP_START_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_PG_STATUS_0_PENDING_SC7_ASSERT_SLEEP_START_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define PMC_IMPL_PG_STATUS_0_PENDING_SC7_ASSERT_SLEEP_START_INIT_ENUM                   DONE
#define PMC_IMPL_PG_STATUS_0_PENDING_SC7_ASSERT_SLEEP_START_DONE                        _MK_ENUM_CONST(0)
#define PMC_IMPL_PG_STATUS_0_PENDING_SC7_ASSERT_SLEEP_START_PENDING                     _MK_ENUM_CONST(1)

#define PMC_IMPL_PG_STATUS_0_PENDING_SC7_REMOVE_SLEEP_START_SHIFT                       _MK_SHIFT_CONST(3)
#define PMC_IMPL_PG_STATUS_0_PENDING_SC7_REMOVE_SLEEP_START_FIELD                       _MK_FIELD_CONST(0x1, PMC_IMPL_PG_STATUS_0_PENDING_SC7_REMOVE_SLEEP_START_SHIFT)
#define PMC_IMPL_PG_STATUS_0_PENDING_SC7_REMOVE_SLEEP_START_RANGE                       3:3
#define PMC_IMPL_PG_STATUS_0_PENDING_SC7_REMOVE_SLEEP_START_WOFFSET                     0x0
#define PMC_IMPL_PG_STATUS_0_PENDING_SC7_REMOVE_SLEEP_START_DEFAULT                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_PG_STATUS_0_PENDING_SC7_REMOVE_SLEEP_START_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define PMC_IMPL_PG_STATUS_0_PENDING_SC7_REMOVE_SLEEP_START_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define PMC_IMPL_PG_STATUS_0_PENDING_SC7_REMOVE_SLEEP_START_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_PG_STATUS_0_PENDING_SC7_REMOVE_SLEEP_START_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_PG_STATUS_0_PENDING_SC7_REMOVE_SLEEP_START_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define PMC_IMPL_PG_STATUS_0_PENDING_SC7_REMOVE_SLEEP_START_INIT_ENUM                   DONE
#define PMC_IMPL_PG_STATUS_0_PENDING_SC7_REMOVE_SLEEP_START_DONE                        _MK_ENUM_CONST(0)
#define PMC_IMPL_PG_STATUS_0_PENDING_SC7_REMOVE_SLEEP_START_PENDING                     _MK_ENUM_CONST(1)

#define PMC_IMPL_PG_STATUS_0_PENDING_PM2PMC_RET_REQ_START_SHIFT                 _MK_SHIFT_CONST(4)
#define PMC_IMPL_PG_STATUS_0_PENDING_PM2PMC_RET_REQ_START_FIELD                 _MK_FIELD_CONST(0x1, PMC_IMPL_PG_STATUS_0_PENDING_PM2PMC_RET_REQ_START_SHIFT)
#define PMC_IMPL_PG_STATUS_0_PENDING_PM2PMC_RET_REQ_START_RANGE                 4:4
#define PMC_IMPL_PG_STATUS_0_PENDING_PM2PMC_RET_REQ_START_WOFFSET                       0x0
#define PMC_IMPL_PG_STATUS_0_PENDING_PM2PMC_RET_REQ_START_DEFAULT                       _MK_MASK_CONST(0x0)
#define PMC_IMPL_PG_STATUS_0_PENDING_PM2PMC_RET_REQ_START_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define PMC_IMPL_PG_STATUS_0_PENDING_PM2PMC_RET_REQ_START_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define PMC_IMPL_PG_STATUS_0_PENDING_PM2PMC_RET_REQ_START_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define PMC_IMPL_PG_STATUS_0_PENDING_PM2PMC_RET_REQ_START_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_PG_STATUS_0_PENDING_PM2PMC_RET_REQ_START_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)
#define PMC_IMPL_PG_STATUS_0_PENDING_PM2PMC_RET_REQ_START_INIT_ENUM                     DONE
#define PMC_IMPL_PG_STATUS_0_PENDING_PM2PMC_RET_REQ_START_DONE                  _MK_ENUM_CONST(0)
#define PMC_IMPL_PG_STATUS_0_PENDING_PM2PMC_RET_REQ_START_PENDING                       _MK_ENUM_CONST(1)

#define PMC_IMPL_PG_STATUS_0_PENDING_PM2PMC_UNRET_REQ_START_SHIFT                       _MK_SHIFT_CONST(5)
#define PMC_IMPL_PG_STATUS_0_PENDING_PM2PMC_UNRET_REQ_START_FIELD                       _MK_FIELD_CONST(0x1, PMC_IMPL_PG_STATUS_0_PENDING_PM2PMC_UNRET_REQ_START_SHIFT)
#define PMC_IMPL_PG_STATUS_0_PENDING_PM2PMC_UNRET_REQ_START_RANGE                       5:5
#define PMC_IMPL_PG_STATUS_0_PENDING_PM2PMC_UNRET_REQ_START_WOFFSET                     0x0
#define PMC_IMPL_PG_STATUS_0_PENDING_PM2PMC_UNRET_REQ_START_DEFAULT                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_PG_STATUS_0_PENDING_PM2PMC_UNRET_REQ_START_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define PMC_IMPL_PG_STATUS_0_PENDING_PM2PMC_UNRET_REQ_START_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define PMC_IMPL_PG_STATUS_0_PENDING_PM2PMC_UNRET_REQ_START_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_PG_STATUS_0_PENDING_PM2PMC_UNRET_REQ_START_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_PG_STATUS_0_PENDING_PM2PMC_UNRET_REQ_START_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define PMC_IMPL_PG_STATUS_0_PENDING_PM2PMC_UNRET_REQ_START_INIT_ENUM                   DONE
#define PMC_IMPL_PG_STATUS_0_PENDING_PM2PMC_UNRET_REQ_START_DONE                        _MK_ENUM_CONST(0)
#define PMC_IMPL_PG_STATUS_0_PENDING_PM2PMC_UNRET_REQ_START_PENDING                     _MK_ENUM_CONST(1)


// Register PMC_IMPL_PART_AUD_POWER_GATE_CONTROL_0
#define PMC_IMPL_PART_AUD_POWER_GATE_CONTROL_0                  _MK_ADDR_CONST(0x208)
#define PMC_IMPL_PART_AUD_POWER_GATE_CONTROL_0_SECURE                   0x0
#define PMC_IMPL_PART_AUD_POWER_GATE_CONTROL_0_DUAL                     0x0
#define PMC_IMPL_PART_AUD_POWER_GATE_CONTROL_0_SCR                      PG_AUD_SCR_0
#define PMC_IMPL_PART_AUD_POWER_GATE_CONTROL_0_WORD_COUNT                       0x1
#define PMC_IMPL_PART_AUD_POWER_GATE_CONTROL_0_RESET_VAL                        _MK_MASK_CONST(0x80000000)
#define PMC_IMPL_PART_AUD_POWER_GATE_CONTROL_0_RESET_MASK                       _MK_MASK_CONST(0x80000107)
#define PMC_IMPL_PART_AUD_POWER_GATE_CONTROL_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AUD_POWER_GATE_CONTROL_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AUD_POWER_GATE_CONTROL_0_READ_MASK                        _MK_MASK_CONST(0x80000107)
#define PMC_IMPL_PART_AUD_POWER_GATE_CONTROL_0_WRITE_MASK                       _MK_MASK_CONST(0x80000107)
#define PMC_IMPL_PART_AUD_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SHIFT                        _MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_AUD_POWER_GATE_CONTROL_0_LOGIC_SLEEP_FIELD                        _MK_FIELD_CONST(0x1, PMC_IMPL_PART_AUD_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SHIFT)
#define PMC_IMPL_PART_AUD_POWER_GATE_CONTROL_0_LOGIC_SLEEP_RANGE                        0:0
#define PMC_IMPL_PART_AUD_POWER_GATE_CONTROL_0_LOGIC_SLEEP_WOFFSET                      0x0
#define PMC_IMPL_PART_AUD_POWER_GATE_CONTROL_0_LOGIC_SLEEP_DEFAULT                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AUD_POWER_GATE_CONTROL_0_LOGIC_SLEEP_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AUD_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AUD_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AUD_POWER_GATE_CONTROL_0_LOGIC_SLEEP_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AUD_POWER_GATE_CONTROL_0_LOGIC_SLEEP_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AUD_POWER_GATE_CONTROL_0_LOGIC_SLEEP_INIT_ENUM                    OFF
#define PMC_IMPL_PART_AUD_POWER_GATE_CONTROL_0_LOGIC_SLEEP_OFF                  _MK_ENUM_CONST(0)
#define PMC_IMPL_PART_AUD_POWER_GATE_CONTROL_0_LOGIC_SLEEP_ON                   _MK_ENUM_CONST(1)

#define PMC_IMPL_PART_AUD_POWER_GATE_CONTROL_0_SRAM_RET_EN_SHIFT                        _MK_SHIFT_CONST(1)
#define PMC_IMPL_PART_AUD_POWER_GATE_CONTROL_0_SRAM_RET_EN_FIELD                        _MK_FIELD_CONST(0x1, PMC_IMPL_PART_AUD_POWER_GATE_CONTROL_0_SRAM_RET_EN_SHIFT)
#define PMC_IMPL_PART_AUD_POWER_GATE_CONTROL_0_SRAM_RET_EN_RANGE                        1:1
#define PMC_IMPL_PART_AUD_POWER_GATE_CONTROL_0_SRAM_RET_EN_WOFFSET                      0x0
#define PMC_IMPL_PART_AUD_POWER_GATE_CONTROL_0_SRAM_RET_EN_DEFAULT                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AUD_POWER_GATE_CONTROL_0_SRAM_RET_EN_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AUD_POWER_GATE_CONTROL_0_SRAM_RET_EN_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AUD_POWER_GATE_CONTROL_0_SRAM_RET_EN_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AUD_POWER_GATE_CONTROL_0_SRAM_RET_EN_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AUD_POWER_GATE_CONTROL_0_SRAM_RET_EN_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AUD_POWER_GATE_CONTROL_0_SRAM_RET_EN_INIT_ENUM                    OFF
#define PMC_IMPL_PART_AUD_POWER_GATE_CONTROL_0_SRAM_RET_EN_OFF                  _MK_ENUM_CONST(0)
#define PMC_IMPL_PART_AUD_POWER_GATE_CONTROL_0_SRAM_RET_EN_ON                   _MK_ENUM_CONST(1)

#define PMC_IMPL_PART_AUD_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SHIFT                      _MK_SHIFT_CONST(2)
#define PMC_IMPL_PART_AUD_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_FIELD                      _MK_FIELD_CONST(0x1, PMC_IMPL_PART_AUD_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SHIFT)
#define PMC_IMPL_PART_AUD_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_RANGE                      2:2
#define PMC_IMPL_PART_AUD_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_WOFFSET                    0x0
#define PMC_IMPL_PART_AUD_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_DEFAULT                    _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AUD_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AUD_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AUD_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AUD_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AUD_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AUD_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_INIT_ENUM                  OFF
#define PMC_IMPL_PART_AUD_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_OFF                        _MK_ENUM_CONST(0)
#define PMC_IMPL_PART_AUD_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_ON                 _MK_ENUM_CONST(1)

#define PMC_IMPL_PART_AUD_POWER_GATE_CONTROL_0_START_SHIFT                      _MK_SHIFT_CONST(8)
#define PMC_IMPL_PART_AUD_POWER_GATE_CONTROL_0_START_FIELD                      _MK_FIELD_CONST(0x1, PMC_IMPL_PART_AUD_POWER_GATE_CONTROL_0_START_SHIFT)
#define PMC_IMPL_PART_AUD_POWER_GATE_CONTROL_0_START_RANGE                      8:8
#define PMC_IMPL_PART_AUD_POWER_GATE_CONTROL_0_START_WOFFSET                    0x0
#define PMC_IMPL_PART_AUD_POWER_GATE_CONTROL_0_START_DEFAULT                    _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AUD_POWER_GATE_CONTROL_0_START_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AUD_POWER_GATE_CONTROL_0_START_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AUD_POWER_GATE_CONTROL_0_START_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AUD_POWER_GATE_CONTROL_0_START_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AUD_POWER_GATE_CONTROL_0_START_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AUD_POWER_GATE_CONTROL_0_START_INIT_ENUM                  DONE
#define PMC_IMPL_PART_AUD_POWER_GATE_CONTROL_0_START_DONE                       _MK_ENUM_CONST(0)
#define PMC_IMPL_PART_AUD_POWER_GATE_CONTROL_0_START_PENDING                    _MK_ENUM_CONST(1)

#define PMC_IMPL_PART_AUD_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SHIFT                        _MK_SHIFT_CONST(31)
#define PMC_IMPL_PART_AUD_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_FIELD                        _MK_FIELD_CONST(0x1, PMC_IMPL_PART_AUD_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SHIFT)
#define PMC_IMPL_PART_AUD_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_RANGE                        31:31
#define PMC_IMPL_PART_AUD_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_WOFFSET                      0x0
#define PMC_IMPL_PART_AUD_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_DEFAULT                      _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AUD_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AUD_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AUD_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AUD_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AUD_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AUD_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_INIT_ENUM                    ENABLE
#define PMC_IMPL_PART_AUD_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_DISABLE                      _MK_ENUM_CONST(0)
#define PMC_IMPL_PART_AUD_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_ENABLE                       _MK_ENUM_CONST(1)


// Register PMC_IMPL_PART_AUD_POWER_GATE_STATUS_0
#define PMC_IMPL_PART_AUD_POWER_GATE_STATUS_0                   _MK_ADDR_CONST(0x20c)
#define PMC_IMPL_PART_AUD_POWER_GATE_STATUS_0_SECURE                    0x0
#define PMC_IMPL_PART_AUD_POWER_GATE_STATUS_0_DUAL                      0x0
#define PMC_IMPL_PART_AUD_POWER_GATE_STATUS_0_SCR                       PG_AUD_SCR_0
#define PMC_IMPL_PART_AUD_POWER_GATE_STATUS_0_WORD_COUNT                        0x1
#define PMC_IMPL_PART_AUD_POWER_GATE_STATUS_0_RESET_VAL                         _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AUD_POWER_GATE_STATUS_0_RESET_MASK                        _MK_MASK_CONST(0x7)
#define PMC_IMPL_PART_AUD_POWER_GATE_STATUS_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AUD_POWER_GATE_STATUS_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AUD_POWER_GATE_STATUS_0_READ_MASK                         _MK_MASK_CONST(0x7)
#define PMC_IMPL_PART_AUD_POWER_GATE_STATUS_0_WRITE_MASK                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AUD_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SHIFT                     _MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_AUD_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_FIELD                     _MK_FIELD_CONST(0x1, PMC_IMPL_PART_AUD_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SHIFT)
#define PMC_IMPL_PART_AUD_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_RANGE                     0:0
#define PMC_IMPL_PART_AUD_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_WOFFSET                   0x0
#define PMC_IMPL_PART_AUD_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_DEFAULT                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AUD_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AUD_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AUD_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AUD_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AUD_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AUD_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_INIT_ENUM                 OFF
#define PMC_IMPL_PART_AUD_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_OFF                       _MK_ENUM_CONST(0)
#define PMC_IMPL_PART_AUD_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_ON                        _MK_ENUM_CONST(1)

#define PMC_IMPL_PART_AUD_POWER_GATE_STATUS_0_SRAM_RET_STS_SHIFT                        _MK_SHIFT_CONST(1)
#define PMC_IMPL_PART_AUD_POWER_GATE_STATUS_0_SRAM_RET_STS_FIELD                        _MK_FIELD_CONST(0x1, PMC_IMPL_PART_AUD_POWER_GATE_STATUS_0_SRAM_RET_STS_SHIFT)
#define PMC_IMPL_PART_AUD_POWER_GATE_STATUS_0_SRAM_RET_STS_RANGE                        1:1
#define PMC_IMPL_PART_AUD_POWER_GATE_STATUS_0_SRAM_RET_STS_WOFFSET                      0x0
#define PMC_IMPL_PART_AUD_POWER_GATE_STATUS_0_SRAM_RET_STS_DEFAULT                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AUD_POWER_GATE_STATUS_0_SRAM_RET_STS_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AUD_POWER_GATE_STATUS_0_SRAM_RET_STS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AUD_POWER_GATE_STATUS_0_SRAM_RET_STS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AUD_POWER_GATE_STATUS_0_SRAM_RET_STS_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AUD_POWER_GATE_STATUS_0_SRAM_RET_STS_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AUD_POWER_GATE_STATUS_0_SRAM_RET_STS_INIT_ENUM                    OFF
#define PMC_IMPL_PART_AUD_POWER_GATE_STATUS_0_SRAM_RET_STS_OFF                  _MK_ENUM_CONST(0)
#define PMC_IMPL_PART_AUD_POWER_GATE_STATUS_0_SRAM_RET_STS_ON                   _MK_ENUM_CONST(1)

#define PMC_IMPL_PART_AUD_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SHIFT                      _MK_SHIFT_CONST(2)
#define PMC_IMPL_PART_AUD_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_FIELD                      _MK_FIELD_CONST(0x1, PMC_IMPL_PART_AUD_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SHIFT)
#define PMC_IMPL_PART_AUD_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_RANGE                      2:2
#define PMC_IMPL_PART_AUD_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_WOFFSET                    0x0
#define PMC_IMPL_PART_AUD_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_DEFAULT                    _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AUD_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AUD_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AUD_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AUD_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AUD_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AUD_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_INIT_ENUM                  OFF
#define PMC_IMPL_PART_AUD_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_OFF                        _MK_ENUM_CONST(0)
#define PMC_IMPL_PART_AUD_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_ON                 _MK_ENUM_CONST(1)


// Register PMC_IMPL_PART_AUD_CLAMP_CONTROL_0
#define PMC_IMPL_PART_AUD_CLAMP_CONTROL_0                       _MK_ADDR_CONST(0x210)
#define PMC_IMPL_PART_AUD_CLAMP_CONTROL_0_SECURE                        0x0
#define PMC_IMPL_PART_AUD_CLAMP_CONTROL_0_DUAL                  0x0
#define PMC_IMPL_PART_AUD_CLAMP_CONTROL_0_SCR                   PG_AUD_SCR_0
#define PMC_IMPL_PART_AUD_CLAMP_CONTROL_0_WORD_COUNT                    0x1
#define PMC_IMPL_PART_AUD_CLAMP_CONTROL_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AUD_CLAMP_CONTROL_0_RESET_MASK                    _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AUD_CLAMP_CONTROL_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AUD_CLAMP_CONTROL_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AUD_CLAMP_CONTROL_0_READ_MASK                     _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AUD_CLAMP_CONTROL_0_WRITE_MASK                    _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AUD_CLAMP_CONTROL_0_CLAMP_SHIFT                   _MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_AUD_CLAMP_CONTROL_0_CLAMP_FIELD                   _MK_FIELD_CONST(0x1, PMC_IMPL_PART_AUD_CLAMP_CONTROL_0_CLAMP_SHIFT)
#define PMC_IMPL_PART_AUD_CLAMP_CONTROL_0_CLAMP_RANGE                   0:0
#define PMC_IMPL_PART_AUD_CLAMP_CONTROL_0_CLAMP_WOFFSET                 0x0
#define PMC_IMPL_PART_AUD_CLAMP_CONTROL_0_CLAMP_DEFAULT                 _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AUD_CLAMP_CONTROL_0_CLAMP_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AUD_CLAMP_CONTROL_0_CLAMP_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AUD_CLAMP_CONTROL_0_CLAMP_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AUD_CLAMP_CONTROL_0_CLAMP_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AUD_CLAMP_CONTROL_0_CLAMP_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AUD_CLAMP_CONTROL_0_CLAMP_INIT_ENUM                       OFF
#define PMC_IMPL_PART_AUD_CLAMP_CONTROL_0_CLAMP_OFF                     _MK_ENUM_CONST(0)
#define PMC_IMPL_PART_AUD_CLAMP_CONTROL_0_CLAMP_ON                      _MK_ENUM_CONST(1)


// Reserved address 0x214

// Reserved address 0x218

// Reserved address 0x21c

// Register PMC_IMPL_PART_DISP_POWER_GATE_CONTROL_0
#define PMC_IMPL_PART_DISP_POWER_GATE_CONTROL_0                 _MK_ADDR_CONST(0x220)
#define PMC_IMPL_PART_DISP_POWER_GATE_CONTROL_0_SECURE                  0x0
#define PMC_IMPL_PART_DISP_POWER_GATE_CONTROL_0_DUAL                    0x0
#define PMC_IMPL_PART_DISP_POWER_GATE_CONTROL_0_SCR                     PG_DISP_SCR_0
#define PMC_IMPL_PART_DISP_POWER_GATE_CONTROL_0_WORD_COUNT                      0x1
#define PMC_IMPL_PART_DISP_POWER_GATE_CONTROL_0_RESET_VAL                       _MK_MASK_CONST(0x80000000)
#define PMC_IMPL_PART_DISP_POWER_GATE_CONTROL_0_RESET_MASK                      _MK_MASK_CONST(0x80000107)
#define PMC_IMPL_PART_DISP_POWER_GATE_CONTROL_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_DISP_POWER_GATE_CONTROL_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_DISP_POWER_GATE_CONTROL_0_READ_MASK                       _MK_MASK_CONST(0x80000107)
#define PMC_IMPL_PART_DISP_POWER_GATE_CONTROL_0_WRITE_MASK                      _MK_MASK_CONST(0x80000107)
#define PMC_IMPL_PART_DISP_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SHIFT                       _MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_DISP_POWER_GATE_CONTROL_0_LOGIC_SLEEP_FIELD                       _MK_FIELD_CONST(0x1, PMC_IMPL_PART_DISP_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SHIFT)
#define PMC_IMPL_PART_DISP_POWER_GATE_CONTROL_0_LOGIC_SLEEP_RANGE                       0:0
#define PMC_IMPL_PART_DISP_POWER_GATE_CONTROL_0_LOGIC_SLEEP_WOFFSET                     0x0
#define PMC_IMPL_PART_DISP_POWER_GATE_CONTROL_0_LOGIC_SLEEP_DEFAULT                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_DISP_POWER_GATE_CONTROL_0_LOGIC_SLEEP_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_DISP_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_DISP_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_DISP_POWER_GATE_CONTROL_0_LOGIC_SLEEP_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_DISP_POWER_GATE_CONTROL_0_LOGIC_SLEEP_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_DISP_POWER_GATE_CONTROL_0_LOGIC_SLEEP_INIT_ENUM                   OFF
#define PMC_IMPL_PART_DISP_POWER_GATE_CONTROL_0_LOGIC_SLEEP_OFF                 _MK_ENUM_CONST(0)
#define PMC_IMPL_PART_DISP_POWER_GATE_CONTROL_0_LOGIC_SLEEP_ON                  _MK_ENUM_CONST(1)

#define PMC_IMPL_PART_DISP_POWER_GATE_CONTROL_0_SRAM_RET_EN_SHIFT                       _MK_SHIFT_CONST(1)
#define PMC_IMPL_PART_DISP_POWER_GATE_CONTROL_0_SRAM_RET_EN_FIELD                       _MK_FIELD_CONST(0x1, PMC_IMPL_PART_DISP_POWER_GATE_CONTROL_0_SRAM_RET_EN_SHIFT)
#define PMC_IMPL_PART_DISP_POWER_GATE_CONTROL_0_SRAM_RET_EN_RANGE                       1:1
#define PMC_IMPL_PART_DISP_POWER_GATE_CONTROL_0_SRAM_RET_EN_WOFFSET                     0x0
#define PMC_IMPL_PART_DISP_POWER_GATE_CONTROL_0_SRAM_RET_EN_DEFAULT                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_DISP_POWER_GATE_CONTROL_0_SRAM_RET_EN_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_DISP_POWER_GATE_CONTROL_0_SRAM_RET_EN_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_DISP_POWER_GATE_CONTROL_0_SRAM_RET_EN_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_DISP_POWER_GATE_CONTROL_0_SRAM_RET_EN_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_DISP_POWER_GATE_CONTROL_0_SRAM_RET_EN_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_DISP_POWER_GATE_CONTROL_0_SRAM_RET_EN_INIT_ENUM                   OFF
#define PMC_IMPL_PART_DISP_POWER_GATE_CONTROL_0_SRAM_RET_EN_OFF                 _MK_ENUM_CONST(0)
#define PMC_IMPL_PART_DISP_POWER_GATE_CONTROL_0_SRAM_RET_EN_ON                  _MK_ENUM_CONST(1)

#define PMC_IMPL_PART_DISP_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SHIFT                     _MK_SHIFT_CONST(2)
#define PMC_IMPL_PART_DISP_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_FIELD                     _MK_FIELD_CONST(0x1, PMC_IMPL_PART_DISP_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SHIFT)
#define PMC_IMPL_PART_DISP_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_RANGE                     2:2
#define PMC_IMPL_PART_DISP_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_WOFFSET                   0x0
#define PMC_IMPL_PART_DISP_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_DEFAULT                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_DISP_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_DISP_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_DISP_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_DISP_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_DISP_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_DISP_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_INIT_ENUM                 OFF
#define PMC_IMPL_PART_DISP_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_OFF                       _MK_ENUM_CONST(0)
#define PMC_IMPL_PART_DISP_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_ON                        _MK_ENUM_CONST(1)

#define PMC_IMPL_PART_DISP_POWER_GATE_CONTROL_0_START_SHIFT                     _MK_SHIFT_CONST(8)
#define PMC_IMPL_PART_DISP_POWER_GATE_CONTROL_0_START_FIELD                     _MK_FIELD_CONST(0x1, PMC_IMPL_PART_DISP_POWER_GATE_CONTROL_0_START_SHIFT)
#define PMC_IMPL_PART_DISP_POWER_GATE_CONTROL_0_START_RANGE                     8:8
#define PMC_IMPL_PART_DISP_POWER_GATE_CONTROL_0_START_WOFFSET                   0x0
#define PMC_IMPL_PART_DISP_POWER_GATE_CONTROL_0_START_DEFAULT                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_DISP_POWER_GATE_CONTROL_0_START_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_DISP_POWER_GATE_CONTROL_0_START_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_DISP_POWER_GATE_CONTROL_0_START_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_DISP_POWER_GATE_CONTROL_0_START_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_DISP_POWER_GATE_CONTROL_0_START_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_DISP_POWER_GATE_CONTROL_0_START_INIT_ENUM                 DONE
#define PMC_IMPL_PART_DISP_POWER_GATE_CONTROL_0_START_DONE                      _MK_ENUM_CONST(0)
#define PMC_IMPL_PART_DISP_POWER_GATE_CONTROL_0_START_PENDING                   _MK_ENUM_CONST(1)

#define PMC_IMPL_PART_DISP_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SHIFT                       _MK_SHIFT_CONST(31)
#define PMC_IMPL_PART_DISP_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_FIELD                       _MK_FIELD_CONST(0x1, PMC_IMPL_PART_DISP_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SHIFT)
#define PMC_IMPL_PART_DISP_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_RANGE                       31:31
#define PMC_IMPL_PART_DISP_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_WOFFSET                     0x0
#define PMC_IMPL_PART_DISP_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_DEFAULT                     _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_DISP_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_DISP_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_DISP_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_DISP_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_DISP_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_DISP_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_INIT_ENUM                   ENABLE
#define PMC_IMPL_PART_DISP_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_DISABLE                     _MK_ENUM_CONST(0)
#define PMC_IMPL_PART_DISP_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_ENABLE                      _MK_ENUM_CONST(1)


// Register PMC_IMPL_PART_DISP_POWER_GATE_STATUS_0
#define PMC_IMPL_PART_DISP_POWER_GATE_STATUS_0                  _MK_ADDR_CONST(0x224)
#define PMC_IMPL_PART_DISP_POWER_GATE_STATUS_0_SECURE                   0x0
#define PMC_IMPL_PART_DISP_POWER_GATE_STATUS_0_DUAL                     0x0
#define PMC_IMPL_PART_DISP_POWER_GATE_STATUS_0_SCR                      PG_DISP_SCR_0
#define PMC_IMPL_PART_DISP_POWER_GATE_STATUS_0_WORD_COUNT                       0x1
#define PMC_IMPL_PART_DISP_POWER_GATE_STATUS_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_DISP_POWER_GATE_STATUS_0_RESET_MASK                       _MK_MASK_CONST(0x7)
#define PMC_IMPL_PART_DISP_POWER_GATE_STATUS_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_DISP_POWER_GATE_STATUS_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_DISP_POWER_GATE_STATUS_0_READ_MASK                        _MK_MASK_CONST(0x7)
#define PMC_IMPL_PART_DISP_POWER_GATE_STATUS_0_WRITE_MASK                       _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_DISP_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SHIFT                    _MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_DISP_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_FIELD                    _MK_FIELD_CONST(0x1, PMC_IMPL_PART_DISP_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SHIFT)
#define PMC_IMPL_PART_DISP_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_RANGE                    0:0
#define PMC_IMPL_PART_DISP_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_WOFFSET                  0x0
#define PMC_IMPL_PART_DISP_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_DEFAULT                  _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_DISP_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_DISP_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_DISP_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_DISP_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_DISP_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_DISP_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_INIT_ENUM                        OFF
#define PMC_IMPL_PART_DISP_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_OFF                      _MK_ENUM_CONST(0)
#define PMC_IMPL_PART_DISP_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_ON                       _MK_ENUM_CONST(1)

#define PMC_IMPL_PART_DISP_POWER_GATE_STATUS_0_SRAM_RET_STS_SHIFT                       _MK_SHIFT_CONST(1)
#define PMC_IMPL_PART_DISP_POWER_GATE_STATUS_0_SRAM_RET_STS_FIELD                       _MK_FIELD_CONST(0x1, PMC_IMPL_PART_DISP_POWER_GATE_STATUS_0_SRAM_RET_STS_SHIFT)
#define PMC_IMPL_PART_DISP_POWER_GATE_STATUS_0_SRAM_RET_STS_RANGE                       1:1
#define PMC_IMPL_PART_DISP_POWER_GATE_STATUS_0_SRAM_RET_STS_WOFFSET                     0x0
#define PMC_IMPL_PART_DISP_POWER_GATE_STATUS_0_SRAM_RET_STS_DEFAULT                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_DISP_POWER_GATE_STATUS_0_SRAM_RET_STS_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_DISP_POWER_GATE_STATUS_0_SRAM_RET_STS_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_DISP_POWER_GATE_STATUS_0_SRAM_RET_STS_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_DISP_POWER_GATE_STATUS_0_SRAM_RET_STS_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_DISP_POWER_GATE_STATUS_0_SRAM_RET_STS_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_DISP_POWER_GATE_STATUS_0_SRAM_RET_STS_INIT_ENUM                   OFF
#define PMC_IMPL_PART_DISP_POWER_GATE_STATUS_0_SRAM_RET_STS_OFF                 _MK_ENUM_CONST(0)
#define PMC_IMPL_PART_DISP_POWER_GATE_STATUS_0_SRAM_RET_STS_ON                  _MK_ENUM_CONST(1)

#define PMC_IMPL_PART_DISP_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SHIFT                     _MK_SHIFT_CONST(2)
#define PMC_IMPL_PART_DISP_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_FIELD                     _MK_FIELD_CONST(0x1, PMC_IMPL_PART_DISP_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SHIFT)
#define PMC_IMPL_PART_DISP_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_RANGE                     2:2
#define PMC_IMPL_PART_DISP_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_WOFFSET                   0x0
#define PMC_IMPL_PART_DISP_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_DEFAULT                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_DISP_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_DISP_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_DISP_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_DISP_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_DISP_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_DISP_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_INIT_ENUM                 OFF
#define PMC_IMPL_PART_DISP_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_OFF                       _MK_ENUM_CONST(0)
#define PMC_IMPL_PART_DISP_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_ON                        _MK_ENUM_CONST(1)


// Register PMC_IMPL_PART_DISP_CLAMP_CONTROL_0
#define PMC_IMPL_PART_DISP_CLAMP_CONTROL_0                      _MK_ADDR_CONST(0x228)
#define PMC_IMPL_PART_DISP_CLAMP_CONTROL_0_SECURE                       0x0
#define PMC_IMPL_PART_DISP_CLAMP_CONTROL_0_DUAL                         0x0
#define PMC_IMPL_PART_DISP_CLAMP_CONTROL_0_SCR                  PG_DISP_SCR_0
#define PMC_IMPL_PART_DISP_CLAMP_CONTROL_0_WORD_COUNT                   0x1
#define PMC_IMPL_PART_DISP_CLAMP_CONTROL_0_RESET_VAL                    _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_DISP_CLAMP_CONTROL_0_RESET_MASK                   _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_DISP_CLAMP_CONTROL_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_DISP_CLAMP_CONTROL_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_DISP_CLAMP_CONTROL_0_READ_MASK                    _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_DISP_CLAMP_CONTROL_0_WRITE_MASK                   _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_DISP_CLAMP_CONTROL_0_CLAMP_SHIFT                  _MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_DISP_CLAMP_CONTROL_0_CLAMP_FIELD                  _MK_FIELD_CONST(0x1, PMC_IMPL_PART_DISP_CLAMP_CONTROL_0_CLAMP_SHIFT)
#define PMC_IMPL_PART_DISP_CLAMP_CONTROL_0_CLAMP_RANGE                  0:0
#define PMC_IMPL_PART_DISP_CLAMP_CONTROL_0_CLAMP_WOFFSET                        0x0
#define PMC_IMPL_PART_DISP_CLAMP_CONTROL_0_CLAMP_DEFAULT                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_DISP_CLAMP_CONTROL_0_CLAMP_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_DISP_CLAMP_CONTROL_0_CLAMP_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_DISP_CLAMP_CONTROL_0_CLAMP_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_DISP_CLAMP_CONTROL_0_CLAMP_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_DISP_CLAMP_CONTROL_0_CLAMP_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_DISP_CLAMP_CONTROL_0_CLAMP_INIT_ENUM                      OFF
#define PMC_IMPL_PART_DISP_CLAMP_CONTROL_0_CLAMP_OFF                    _MK_ENUM_CONST(0)
#define PMC_IMPL_PART_DISP_CLAMP_CONTROL_0_CLAMP_ON                     _MK_ENUM_CONST(1)


// Register PMC_IMPL_PART_DISPB_POWER_GATE_CONTROL_0
#define PMC_IMPL_PART_DISPB_POWER_GATE_CONTROL_0                        _MK_ADDR_CONST(0x22c)
#define PMC_IMPL_PART_DISPB_POWER_GATE_CONTROL_0_SECURE                         0x0
#define PMC_IMPL_PART_DISPB_POWER_GATE_CONTROL_0_DUAL                   0x0
#define PMC_IMPL_PART_DISPB_POWER_GATE_CONTROL_0_SCR                    PG_DISPB_SCR_0
#define PMC_IMPL_PART_DISPB_POWER_GATE_CONTROL_0_WORD_COUNT                     0x1
#define PMC_IMPL_PART_DISPB_POWER_GATE_CONTROL_0_RESET_VAL                      _MK_MASK_CONST(0x80000000)
#define PMC_IMPL_PART_DISPB_POWER_GATE_CONTROL_0_RESET_MASK                     _MK_MASK_CONST(0x80000107)
#define PMC_IMPL_PART_DISPB_POWER_GATE_CONTROL_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_DISPB_POWER_GATE_CONTROL_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_DISPB_POWER_GATE_CONTROL_0_READ_MASK                      _MK_MASK_CONST(0x80000107)
#define PMC_IMPL_PART_DISPB_POWER_GATE_CONTROL_0_WRITE_MASK                     _MK_MASK_CONST(0x80000107)
#define PMC_IMPL_PART_DISPB_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SHIFT                      _MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_DISPB_POWER_GATE_CONTROL_0_LOGIC_SLEEP_FIELD                      _MK_FIELD_CONST(0x1, PMC_IMPL_PART_DISPB_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SHIFT)
#define PMC_IMPL_PART_DISPB_POWER_GATE_CONTROL_0_LOGIC_SLEEP_RANGE                      0:0
#define PMC_IMPL_PART_DISPB_POWER_GATE_CONTROL_0_LOGIC_SLEEP_WOFFSET                    0x0
#define PMC_IMPL_PART_DISPB_POWER_GATE_CONTROL_0_LOGIC_SLEEP_DEFAULT                    _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_DISPB_POWER_GATE_CONTROL_0_LOGIC_SLEEP_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_DISPB_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_DISPB_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_DISPB_POWER_GATE_CONTROL_0_LOGIC_SLEEP_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_DISPB_POWER_GATE_CONTROL_0_LOGIC_SLEEP_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_DISPB_POWER_GATE_CONTROL_0_LOGIC_SLEEP_INIT_ENUM                  OFF
#define PMC_IMPL_PART_DISPB_POWER_GATE_CONTROL_0_LOGIC_SLEEP_OFF                        _MK_ENUM_CONST(0)
#define PMC_IMPL_PART_DISPB_POWER_GATE_CONTROL_0_LOGIC_SLEEP_ON                 _MK_ENUM_CONST(1)

#define PMC_IMPL_PART_DISPB_POWER_GATE_CONTROL_0_SRAM_RET_EN_SHIFT                      _MK_SHIFT_CONST(1)
#define PMC_IMPL_PART_DISPB_POWER_GATE_CONTROL_0_SRAM_RET_EN_FIELD                      _MK_FIELD_CONST(0x1, PMC_IMPL_PART_DISPB_POWER_GATE_CONTROL_0_SRAM_RET_EN_SHIFT)
#define PMC_IMPL_PART_DISPB_POWER_GATE_CONTROL_0_SRAM_RET_EN_RANGE                      1:1
#define PMC_IMPL_PART_DISPB_POWER_GATE_CONTROL_0_SRAM_RET_EN_WOFFSET                    0x0
#define PMC_IMPL_PART_DISPB_POWER_GATE_CONTROL_0_SRAM_RET_EN_DEFAULT                    _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_DISPB_POWER_GATE_CONTROL_0_SRAM_RET_EN_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_DISPB_POWER_GATE_CONTROL_0_SRAM_RET_EN_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_DISPB_POWER_GATE_CONTROL_0_SRAM_RET_EN_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_DISPB_POWER_GATE_CONTROL_0_SRAM_RET_EN_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_DISPB_POWER_GATE_CONTROL_0_SRAM_RET_EN_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_DISPB_POWER_GATE_CONTROL_0_SRAM_RET_EN_INIT_ENUM                  OFF
#define PMC_IMPL_PART_DISPB_POWER_GATE_CONTROL_0_SRAM_RET_EN_OFF                        _MK_ENUM_CONST(0)
#define PMC_IMPL_PART_DISPB_POWER_GATE_CONTROL_0_SRAM_RET_EN_ON                 _MK_ENUM_CONST(1)

#define PMC_IMPL_PART_DISPB_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SHIFT                    _MK_SHIFT_CONST(2)
#define PMC_IMPL_PART_DISPB_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_FIELD                    _MK_FIELD_CONST(0x1, PMC_IMPL_PART_DISPB_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SHIFT)
#define PMC_IMPL_PART_DISPB_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_RANGE                    2:2
#define PMC_IMPL_PART_DISPB_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_WOFFSET                  0x0
#define PMC_IMPL_PART_DISPB_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_DEFAULT                  _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_DISPB_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_DISPB_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_DISPB_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_DISPB_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_DISPB_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_DISPB_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_INIT_ENUM                        OFF
#define PMC_IMPL_PART_DISPB_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_OFF                      _MK_ENUM_CONST(0)
#define PMC_IMPL_PART_DISPB_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_ON                       _MK_ENUM_CONST(1)

#define PMC_IMPL_PART_DISPB_POWER_GATE_CONTROL_0_START_SHIFT                    _MK_SHIFT_CONST(8)
#define PMC_IMPL_PART_DISPB_POWER_GATE_CONTROL_0_START_FIELD                    _MK_FIELD_CONST(0x1, PMC_IMPL_PART_DISPB_POWER_GATE_CONTROL_0_START_SHIFT)
#define PMC_IMPL_PART_DISPB_POWER_GATE_CONTROL_0_START_RANGE                    8:8
#define PMC_IMPL_PART_DISPB_POWER_GATE_CONTROL_0_START_WOFFSET                  0x0
#define PMC_IMPL_PART_DISPB_POWER_GATE_CONTROL_0_START_DEFAULT                  _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_DISPB_POWER_GATE_CONTROL_0_START_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_DISPB_POWER_GATE_CONTROL_0_START_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_DISPB_POWER_GATE_CONTROL_0_START_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_DISPB_POWER_GATE_CONTROL_0_START_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_DISPB_POWER_GATE_CONTROL_0_START_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_DISPB_POWER_GATE_CONTROL_0_START_INIT_ENUM                        DONE
#define PMC_IMPL_PART_DISPB_POWER_GATE_CONTROL_0_START_DONE                     _MK_ENUM_CONST(0)
#define PMC_IMPL_PART_DISPB_POWER_GATE_CONTROL_0_START_PENDING                  _MK_ENUM_CONST(1)

#define PMC_IMPL_PART_DISPB_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SHIFT                      _MK_SHIFT_CONST(31)
#define PMC_IMPL_PART_DISPB_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_FIELD                      _MK_FIELD_CONST(0x1, PMC_IMPL_PART_DISPB_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SHIFT)
#define PMC_IMPL_PART_DISPB_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_RANGE                      31:31
#define PMC_IMPL_PART_DISPB_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_WOFFSET                    0x0
#define PMC_IMPL_PART_DISPB_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_DEFAULT                    _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_DISPB_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_DISPB_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_DISPB_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_DISPB_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_DISPB_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_DISPB_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_INIT_ENUM                  ENABLE
#define PMC_IMPL_PART_DISPB_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_DISABLE                    _MK_ENUM_CONST(0)
#define PMC_IMPL_PART_DISPB_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_ENABLE                     _MK_ENUM_CONST(1)


// Register PMC_IMPL_PART_DISPB_POWER_GATE_STATUS_0
#define PMC_IMPL_PART_DISPB_POWER_GATE_STATUS_0                 _MK_ADDR_CONST(0x230)
#define PMC_IMPL_PART_DISPB_POWER_GATE_STATUS_0_SECURE                  0x0
#define PMC_IMPL_PART_DISPB_POWER_GATE_STATUS_0_DUAL                    0x0
#define PMC_IMPL_PART_DISPB_POWER_GATE_STATUS_0_SCR                     PG_DISPB_SCR_0
#define PMC_IMPL_PART_DISPB_POWER_GATE_STATUS_0_WORD_COUNT                      0x1
#define PMC_IMPL_PART_DISPB_POWER_GATE_STATUS_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_DISPB_POWER_GATE_STATUS_0_RESET_MASK                      _MK_MASK_CONST(0x7)
#define PMC_IMPL_PART_DISPB_POWER_GATE_STATUS_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_DISPB_POWER_GATE_STATUS_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_DISPB_POWER_GATE_STATUS_0_READ_MASK                       _MK_MASK_CONST(0x7)
#define PMC_IMPL_PART_DISPB_POWER_GATE_STATUS_0_WRITE_MASK                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_DISPB_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SHIFT                   _MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_DISPB_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_FIELD                   _MK_FIELD_CONST(0x1, PMC_IMPL_PART_DISPB_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SHIFT)
#define PMC_IMPL_PART_DISPB_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_RANGE                   0:0
#define PMC_IMPL_PART_DISPB_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_WOFFSET                 0x0
#define PMC_IMPL_PART_DISPB_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_DEFAULT                 _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_DISPB_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_DISPB_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_DISPB_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_DISPB_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_DISPB_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_DISPB_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_INIT_ENUM                       OFF
#define PMC_IMPL_PART_DISPB_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_OFF                     _MK_ENUM_CONST(0)
#define PMC_IMPL_PART_DISPB_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_ON                      _MK_ENUM_CONST(1)

#define PMC_IMPL_PART_DISPB_POWER_GATE_STATUS_0_SRAM_RET_STS_SHIFT                      _MK_SHIFT_CONST(1)
#define PMC_IMPL_PART_DISPB_POWER_GATE_STATUS_0_SRAM_RET_STS_FIELD                      _MK_FIELD_CONST(0x1, PMC_IMPL_PART_DISPB_POWER_GATE_STATUS_0_SRAM_RET_STS_SHIFT)
#define PMC_IMPL_PART_DISPB_POWER_GATE_STATUS_0_SRAM_RET_STS_RANGE                      1:1
#define PMC_IMPL_PART_DISPB_POWER_GATE_STATUS_0_SRAM_RET_STS_WOFFSET                    0x0
#define PMC_IMPL_PART_DISPB_POWER_GATE_STATUS_0_SRAM_RET_STS_DEFAULT                    _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_DISPB_POWER_GATE_STATUS_0_SRAM_RET_STS_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_DISPB_POWER_GATE_STATUS_0_SRAM_RET_STS_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_DISPB_POWER_GATE_STATUS_0_SRAM_RET_STS_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_DISPB_POWER_GATE_STATUS_0_SRAM_RET_STS_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_DISPB_POWER_GATE_STATUS_0_SRAM_RET_STS_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_DISPB_POWER_GATE_STATUS_0_SRAM_RET_STS_INIT_ENUM                  OFF
#define PMC_IMPL_PART_DISPB_POWER_GATE_STATUS_0_SRAM_RET_STS_OFF                        _MK_ENUM_CONST(0)
#define PMC_IMPL_PART_DISPB_POWER_GATE_STATUS_0_SRAM_RET_STS_ON                 _MK_ENUM_CONST(1)

#define PMC_IMPL_PART_DISPB_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SHIFT                    _MK_SHIFT_CONST(2)
#define PMC_IMPL_PART_DISPB_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_FIELD                    _MK_FIELD_CONST(0x1, PMC_IMPL_PART_DISPB_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SHIFT)
#define PMC_IMPL_PART_DISPB_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_RANGE                    2:2
#define PMC_IMPL_PART_DISPB_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_WOFFSET                  0x0
#define PMC_IMPL_PART_DISPB_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_DEFAULT                  _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_DISPB_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_DISPB_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_DISPB_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_DISPB_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_DISPB_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_DISPB_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_INIT_ENUM                        OFF
#define PMC_IMPL_PART_DISPB_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_OFF                      _MK_ENUM_CONST(0)
#define PMC_IMPL_PART_DISPB_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_ON                       _MK_ENUM_CONST(1)


// Register PMC_IMPL_PART_DISPB_CLAMP_CONTROL_0
#define PMC_IMPL_PART_DISPB_CLAMP_CONTROL_0                     _MK_ADDR_CONST(0x234)
#define PMC_IMPL_PART_DISPB_CLAMP_CONTROL_0_SECURE                      0x0
#define PMC_IMPL_PART_DISPB_CLAMP_CONTROL_0_DUAL                        0x0
#define PMC_IMPL_PART_DISPB_CLAMP_CONTROL_0_SCR                         PG_DISPB_SCR_0
#define PMC_IMPL_PART_DISPB_CLAMP_CONTROL_0_WORD_COUNT                  0x1
#define PMC_IMPL_PART_DISPB_CLAMP_CONTROL_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_DISPB_CLAMP_CONTROL_0_RESET_MASK                  _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_DISPB_CLAMP_CONTROL_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_DISPB_CLAMP_CONTROL_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_DISPB_CLAMP_CONTROL_0_READ_MASK                   _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_DISPB_CLAMP_CONTROL_0_WRITE_MASK                  _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_DISPB_CLAMP_CONTROL_0_CLAMP_SHIFT                 _MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_DISPB_CLAMP_CONTROL_0_CLAMP_FIELD                 _MK_FIELD_CONST(0x1, PMC_IMPL_PART_DISPB_CLAMP_CONTROL_0_CLAMP_SHIFT)
#define PMC_IMPL_PART_DISPB_CLAMP_CONTROL_0_CLAMP_RANGE                 0:0
#define PMC_IMPL_PART_DISPB_CLAMP_CONTROL_0_CLAMP_WOFFSET                       0x0
#define PMC_IMPL_PART_DISPB_CLAMP_CONTROL_0_CLAMP_DEFAULT                       _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_DISPB_CLAMP_CONTROL_0_CLAMP_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_DISPB_CLAMP_CONTROL_0_CLAMP_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_DISPB_CLAMP_CONTROL_0_CLAMP_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_DISPB_CLAMP_CONTROL_0_CLAMP_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_DISPB_CLAMP_CONTROL_0_CLAMP_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_DISPB_CLAMP_CONTROL_0_CLAMP_INIT_ENUM                     OFF
#define PMC_IMPL_PART_DISPB_CLAMP_CONTROL_0_CLAMP_OFF                   _MK_ENUM_CONST(0)
#define PMC_IMPL_PART_DISPB_CLAMP_CONTROL_0_CLAMP_ON                    _MK_ENUM_CONST(1)


// Register PMC_IMPL_PART_DISPC_POWER_GATE_CONTROL_0
#define PMC_IMPL_PART_DISPC_POWER_GATE_CONTROL_0                        _MK_ADDR_CONST(0x238)
#define PMC_IMPL_PART_DISPC_POWER_GATE_CONTROL_0_SECURE                         0x0
#define PMC_IMPL_PART_DISPC_POWER_GATE_CONTROL_0_DUAL                   0x0
#define PMC_IMPL_PART_DISPC_POWER_GATE_CONTROL_0_SCR                    PG_DISPC_SCR_0
#define PMC_IMPL_PART_DISPC_POWER_GATE_CONTROL_0_WORD_COUNT                     0x1
#define PMC_IMPL_PART_DISPC_POWER_GATE_CONTROL_0_RESET_VAL                      _MK_MASK_CONST(0x80000000)
#define PMC_IMPL_PART_DISPC_POWER_GATE_CONTROL_0_RESET_MASK                     _MK_MASK_CONST(0x80000107)
#define PMC_IMPL_PART_DISPC_POWER_GATE_CONTROL_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_DISPC_POWER_GATE_CONTROL_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_DISPC_POWER_GATE_CONTROL_0_READ_MASK                      _MK_MASK_CONST(0x80000107)
#define PMC_IMPL_PART_DISPC_POWER_GATE_CONTROL_0_WRITE_MASK                     _MK_MASK_CONST(0x80000107)
#define PMC_IMPL_PART_DISPC_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SHIFT                      _MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_DISPC_POWER_GATE_CONTROL_0_LOGIC_SLEEP_FIELD                      _MK_FIELD_CONST(0x1, PMC_IMPL_PART_DISPC_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SHIFT)
#define PMC_IMPL_PART_DISPC_POWER_GATE_CONTROL_0_LOGIC_SLEEP_RANGE                      0:0
#define PMC_IMPL_PART_DISPC_POWER_GATE_CONTROL_0_LOGIC_SLEEP_WOFFSET                    0x0
#define PMC_IMPL_PART_DISPC_POWER_GATE_CONTROL_0_LOGIC_SLEEP_DEFAULT                    _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_DISPC_POWER_GATE_CONTROL_0_LOGIC_SLEEP_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_DISPC_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_DISPC_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_DISPC_POWER_GATE_CONTROL_0_LOGIC_SLEEP_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_DISPC_POWER_GATE_CONTROL_0_LOGIC_SLEEP_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_DISPC_POWER_GATE_CONTROL_0_LOGIC_SLEEP_INIT_ENUM                  OFF
#define PMC_IMPL_PART_DISPC_POWER_GATE_CONTROL_0_LOGIC_SLEEP_OFF                        _MK_ENUM_CONST(0)
#define PMC_IMPL_PART_DISPC_POWER_GATE_CONTROL_0_LOGIC_SLEEP_ON                 _MK_ENUM_CONST(1)

#define PMC_IMPL_PART_DISPC_POWER_GATE_CONTROL_0_SRAM_RET_EN_SHIFT                      _MK_SHIFT_CONST(1)
#define PMC_IMPL_PART_DISPC_POWER_GATE_CONTROL_0_SRAM_RET_EN_FIELD                      _MK_FIELD_CONST(0x1, PMC_IMPL_PART_DISPC_POWER_GATE_CONTROL_0_SRAM_RET_EN_SHIFT)
#define PMC_IMPL_PART_DISPC_POWER_GATE_CONTROL_0_SRAM_RET_EN_RANGE                      1:1
#define PMC_IMPL_PART_DISPC_POWER_GATE_CONTROL_0_SRAM_RET_EN_WOFFSET                    0x0
#define PMC_IMPL_PART_DISPC_POWER_GATE_CONTROL_0_SRAM_RET_EN_DEFAULT                    _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_DISPC_POWER_GATE_CONTROL_0_SRAM_RET_EN_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_DISPC_POWER_GATE_CONTROL_0_SRAM_RET_EN_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_DISPC_POWER_GATE_CONTROL_0_SRAM_RET_EN_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_DISPC_POWER_GATE_CONTROL_0_SRAM_RET_EN_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_DISPC_POWER_GATE_CONTROL_0_SRAM_RET_EN_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_DISPC_POWER_GATE_CONTROL_0_SRAM_RET_EN_INIT_ENUM                  OFF
#define PMC_IMPL_PART_DISPC_POWER_GATE_CONTROL_0_SRAM_RET_EN_OFF                        _MK_ENUM_CONST(0)
#define PMC_IMPL_PART_DISPC_POWER_GATE_CONTROL_0_SRAM_RET_EN_ON                 _MK_ENUM_CONST(1)

#define PMC_IMPL_PART_DISPC_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SHIFT                    _MK_SHIFT_CONST(2)
#define PMC_IMPL_PART_DISPC_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_FIELD                    _MK_FIELD_CONST(0x1, PMC_IMPL_PART_DISPC_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SHIFT)
#define PMC_IMPL_PART_DISPC_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_RANGE                    2:2
#define PMC_IMPL_PART_DISPC_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_WOFFSET                  0x0
#define PMC_IMPL_PART_DISPC_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_DEFAULT                  _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_DISPC_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_DISPC_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_DISPC_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_DISPC_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_DISPC_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_DISPC_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_INIT_ENUM                        OFF
#define PMC_IMPL_PART_DISPC_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_OFF                      _MK_ENUM_CONST(0)
#define PMC_IMPL_PART_DISPC_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_ON                       _MK_ENUM_CONST(1)

#define PMC_IMPL_PART_DISPC_POWER_GATE_CONTROL_0_START_SHIFT                    _MK_SHIFT_CONST(8)
#define PMC_IMPL_PART_DISPC_POWER_GATE_CONTROL_0_START_FIELD                    _MK_FIELD_CONST(0x1, PMC_IMPL_PART_DISPC_POWER_GATE_CONTROL_0_START_SHIFT)
#define PMC_IMPL_PART_DISPC_POWER_GATE_CONTROL_0_START_RANGE                    8:8
#define PMC_IMPL_PART_DISPC_POWER_GATE_CONTROL_0_START_WOFFSET                  0x0
#define PMC_IMPL_PART_DISPC_POWER_GATE_CONTROL_0_START_DEFAULT                  _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_DISPC_POWER_GATE_CONTROL_0_START_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_DISPC_POWER_GATE_CONTROL_0_START_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_DISPC_POWER_GATE_CONTROL_0_START_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_DISPC_POWER_GATE_CONTROL_0_START_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_DISPC_POWER_GATE_CONTROL_0_START_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_DISPC_POWER_GATE_CONTROL_0_START_INIT_ENUM                        DONE
#define PMC_IMPL_PART_DISPC_POWER_GATE_CONTROL_0_START_DONE                     _MK_ENUM_CONST(0)
#define PMC_IMPL_PART_DISPC_POWER_GATE_CONTROL_0_START_PENDING                  _MK_ENUM_CONST(1)

#define PMC_IMPL_PART_DISPC_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SHIFT                      _MK_SHIFT_CONST(31)
#define PMC_IMPL_PART_DISPC_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_FIELD                      _MK_FIELD_CONST(0x1, PMC_IMPL_PART_DISPC_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SHIFT)
#define PMC_IMPL_PART_DISPC_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_RANGE                      31:31
#define PMC_IMPL_PART_DISPC_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_WOFFSET                    0x0
#define PMC_IMPL_PART_DISPC_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_DEFAULT                    _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_DISPC_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_DISPC_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_DISPC_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_DISPC_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_DISPC_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_DISPC_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_INIT_ENUM                  ENABLE
#define PMC_IMPL_PART_DISPC_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_DISABLE                    _MK_ENUM_CONST(0)
#define PMC_IMPL_PART_DISPC_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_ENABLE                     _MK_ENUM_CONST(1)


// Register PMC_IMPL_PART_DISPC_POWER_GATE_STATUS_0
#define PMC_IMPL_PART_DISPC_POWER_GATE_STATUS_0                 _MK_ADDR_CONST(0x23c)
#define PMC_IMPL_PART_DISPC_POWER_GATE_STATUS_0_SECURE                  0x0
#define PMC_IMPL_PART_DISPC_POWER_GATE_STATUS_0_DUAL                    0x0
#define PMC_IMPL_PART_DISPC_POWER_GATE_STATUS_0_SCR                     PG_DISPC_SCR_0
#define PMC_IMPL_PART_DISPC_POWER_GATE_STATUS_0_WORD_COUNT                      0x1
#define PMC_IMPL_PART_DISPC_POWER_GATE_STATUS_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_DISPC_POWER_GATE_STATUS_0_RESET_MASK                      _MK_MASK_CONST(0x7)
#define PMC_IMPL_PART_DISPC_POWER_GATE_STATUS_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_DISPC_POWER_GATE_STATUS_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_DISPC_POWER_GATE_STATUS_0_READ_MASK                       _MK_MASK_CONST(0x7)
#define PMC_IMPL_PART_DISPC_POWER_GATE_STATUS_0_WRITE_MASK                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_DISPC_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SHIFT                   _MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_DISPC_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_FIELD                   _MK_FIELD_CONST(0x1, PMC_IMPL_PART_DISPC_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SHIFT)
#define PMC_IMPL_PART_DISPC_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_RANGE                   0:0
#define PMC_IMPL_PART_DISPC_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_WOFFSET                 0x0
#define PMC_IMPL_PART_DISPC_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_DEFAULT                 _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_DISPC_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_DISPC_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_DISPC_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_DISPC_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_DISPC_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_DISPC_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_INIT_ENUM                       OFF
#define PMC_IMPL_PART_DISPC_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_OFF                     _MK_ENUM_CONST(0)
#define PMC_IMPL_PART_DISPC_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_ON                      _MK_ENUM_CONST(1)

#define PMC_IMPL_PART_DISPC_POWER_GATE_STATUS_0_SRAM_RET_STS_SHIFT                      _MK_SHIFT_CONST(1)
#define PMC_IMPL_PART_DISPC_POWER_GATE_STATUS_0_SRAM_RET_STS_FIELD                      _MK_FIELD_CONST(0x1, PMC_IMPL_PART_DISPC_POWER_GATE_STATUS_0_SRAM_RET_STS_SHIFT)
#define PMC_IMPL_PART_DISPC_POWER_GATE_STATUS_0_SRAM_RET_STS_RANGE                      1:1
#define PMC_IMPL_PART_DISPC_POWER_GATE_STATUS_0_SRAM_RET_STS_WOFFSET                    0x0
#define PMC_IMPL_PART_DISPC_POWER_GATE_STATUS_0_SRAM_RET_STS_DEFAULT                    _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_DISPC_POWER_GATE_STATUS_0_SRAM_RET_STS_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_DISPC_POWER_GATE_STATUS_0_SRAM_RET_STS_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_DISPC_POWER_GATE_STATUS_0_SRAM_RET_STS_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_DISPC_POWER_GATE_STATUS_0_SRAM_RET_STS_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_DISPC_POWER_GATE_STATUS_0_SRAM_RET_STS_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_DISPC_POWER_GATE_STATUS_0_SRAM_RET_STS_INIT_ENUM                  OFF
#define PMC_IMPL_PART_DISPC_POWER_GATE_STATUS_0_SRAM_RET_STS_OFF                        _MK_ENUM_CONST(0)
#define PMC_IMPL_PART_DISPC_POWER_GATE_STATUS_0_SRAM_RET_STS_ON                 _MK_ENUM_CONST(1)

#define PMC_IMPL_PART_DISPC_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SHIFT                    _MK_SHIFT_CONST(2)
#define PMC_IMPL_PART_DISPC_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_FIELD                    _MK_FIELD_CONST(0x1, PMC_IMPL_PART_DISPC_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SHIFT)
#define PMC_IMPL_PART_DISPC_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_RANGE                    2:2
#define PMC_IMPL_PART_DISPC_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_WOFFSET                  0x0
#define PMC_IMPL_PART_DISPC_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_DEFAULT                  _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_DISPC_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_DISPC_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_DISPC_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_DISPC_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_DISPC_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_DISPC_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_INIT_ENUM                        OFF
#define PMC_IMPL_PART_DISPC_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_OFF                      _MK_ENUM_CONST(0)
#define PMC_IMPL_PART_DISPC_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_ON                       _MK_ENUM_CONST(1)


// Register PMC_IMPL_PART_DISPC_CLAMP_CONTROL_0
#define PMC_IMPL_PART_DISPC_CLAMP_CONTROL_0                     _MK_ADDR_CONST(0x240)
#define PMC_IMPL_PART_DISPC_CLAMP_CONTROL_0_SECURE                      0x0
#define PMC_IMPL_PART_DISPC_CLAMP_CONTROL_0_DUAL                        0x0
#define PMC_IMPL_PART_DISPC_CLAMP_CONTROL_0_SCR                         PG_DISPC_SCR_0
#define PMC_IMPL_PART_DISPC_CLAMP_CONTROL_0_WORD_COUNT                  0x1
#define PMC_IMPL_PART_DISPC_CLAMP_CONTROL_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_DISPC_CLAMP_CONTROL_0_RESET_MASK                  _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_DISPC_CLAMP_CONTROL_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_DISPC_CLAMP_CONTROL_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_DISPC_CLAMP_CONTROL_0_READ_MASK                   _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_DISPC_CLAMP_CONTROL_0_WRITE_MASK                  _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_DISPC_CLAMP_CONTROL_0_CLAMP_SHIFT                 _MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_DISPC_CLAMP_CONTROL_0_CLAMP_FIELD                 _MK_FIELD_CONST(0x1, PMC_IMPL_PART_DISPC_CLAMP_CONTROL_0_CLAMP_SHIFT)
#define PMC_IMPL_PART_DISPC_CLAMP_CONTROL_0_CLAMP_RANGE                 0:0
#define PMC_IMPL_PART_DISPC_CLAMP_CONTROL_0_CLAMP_WOFFSET                       0x0
#define PMC_IMPL_PART_DISPC_CLAMP_CONTROL_0_CLAMP_DEFAULT                       _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_DISPC_CLAMP_CONTROL_0_CLAMP_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_DISPC_CLAMP_CONTROL_0_CLAMP_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_DISPC_CLAMP_CONTROL_0_CLAMP_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_DISPC_CLAMP_CONTROL_0_CLAMP_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_DISPC_CLAMP_CONTROL_0_CLAMP_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_DISPC_CLAMP_CONTROL_0_CLAMP_INIT_ENUM                     OFF
#define PMC_IMPL_PART_DISPC_CLAMP_CONTROL_0_CLAMP_OFF                   _MK_ENUM_CONST(0)
#define PMC_IMPL_PART_DISPC_CLAMP_CONTROL_0_CLAMP_ON                    _MK_ENUM_CONST(1)


// Register PMC_IMPL_PART_ISPA_POWER_GATE_CONTROL_0
#define PMC_IMPL_PART_ISPA_POWER_GATE_CONTROL_0                 _MK_ADDR_CONST(0x244)
#define PMC_IMPL_PART_ISPA_POWER_GATE_CONTROL_0_SECURE                  0x0
#define PMC_IMPL_PART_ISPA_POWER_GATE_CONTROL_0_DUAL                    0x0
#define PMC_IMPL_PART_ISPA_POWER_GATE_CONTROL_0_SCR                     PG_ISPA_SCR_0
#define PMC_IMPL_PART_ISPA_POWER_GATE_CONTROL_0_WORD_COUNT                      0x1
#define PMC_IMPL_PART_ISPA_POWER_GATE_CONTROL_0_RESET_VAL                       _MK_MASK_CONST(0x80000000)
#define PMC_IMPL_PART_ISPA_POWER_GATE_CONTROL_0_RESET_MASK                      _MK_MASK_CONST(0x80000107)
#define PMC_IMPL_PART_ISPA_POWER_GATE_CONTROL_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_ISPA_POWER_GATE_CONTROL_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_ISPA_POWER_GATE_CONTROL_0_READ_MASK                       _MK_MASK_CONST(0x80000107)
#define PMC_IMPL_PART_ISPA_POWER_GATE_CONTROL_0_WRITE_MASK                      _MK_MASK_CONST(0x80000107)
#define PMC_IMPL_PART_ISPA_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SHIFT                       _MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_ISPA_POWER_GATE_CONTROL_0_LOGIC_SLEEP_FIELD                       _MK_FIELD_CONST(0x1, PMC_IMPL_PART_ISPA_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SHIFT)
#define PMC_IMPL_PART_ISPA_POWER_GATE_CONTROL_0_LOGIC_SLEEP_RANGE                       0:0
#define PMC_IMPL_PART_ISPA_POWER_GATE_CONTROL_0_LOGIC_SLEEP_WOFFSET                     0x0
#define PMC_IMPL_PART_ISPA_POWER_GATE_CONTROL_0_LOGIC_SLEEP_DEFAULT                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_ISPA_POWER_GATE_CONTROL_0_LOGIC_SLEEP_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_ISPA_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_ISPA_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_ISPA_POWER_GATE_CONTROL_0_LOGIC_SLEEP_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_ISPA_POWER_GATE_CONTROL_0_LOGIC_SLEEP_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_ISPA_POWER_GATE_CONTROL_0_LOGIC_SLEEP_INIT_ENUM                   OFF
#define PMC_IMPL_PART_ISPA_POWER_GATE_CONTROL_0_LOGIC_SLEEP_OFF                 _MK_ENUM_CONST(0)
#define PMC_IMPL_PART_ISPA_POWER_GATE_CONTROL_0_LOGIC_SLEEP_ON                  _MK_ENUM_CONST(1)

#define PMC_IMPL_PART_ISPA_POWER_GATE_CONTROL_0_SRAM_RET_EN_SHIFT                       _MK_SHIFT_CONST(1)
#define PMC_IMPL_PART_ISPA_POWER_GATE_CONTROL_0_SRAM_RET_EN_FIELD                       _MK_FIELD_CONST(0x1, PMC_IMPL_PART_ISPA_POWER_GATE_CONTROL_0_SRAM_RET_EN_SHIFT)
#define PMC_IMPL_PART_ISPA_POWER_GATE_CONTROL_0_SRAM_RET_EN_RANGE                       1:1
#define PMC_IMPL_PART_ISPA_POWER_GATE_CONTROL_0_SRAM_RET_EN_WOFFSET                     0x0
#define PMC_IMPL_PART_ISPA_POWER_GATE_CONTROL_0_SRAM_RET_EN_DEFAULT                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_ISPA_POWER_GATE_CONTROL_0_SRAM_RET_EN_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_ISPA_POWER_GATE_CONTROL_0_SRAM_RET_EN_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_ISPA_POWER_GATE_CONTROL_0_SRAM_RET_EN_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_ISPA_POWER_GATE_CONTROL_0_SRAM_RET_EN_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_ISPA_POWER_GATE_CONTROL_0_SRAM_RET_EN_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_ISPA_POWER_GATE_CONTROL_0_SRAM_RET_EN_INIT_ENUM                   OFF
#define PMC_IMPL_PART_ISPA_POWER_GATE_CONTROL_0_SRAM_RET_EN_OFF                 _MK_ENUM_CONST(0)
#define PMC_IMPL_PART_ISPA_POWER_GATE_CONTROL_0_SRAM_RET_EN_ON                  _MK_ENUM_CONST(1)

#define PMC_IMPL_PART_ISPA_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SHIFT                     _MK_SHIFT_CONST(2)
#define PMC_IMPL_PART_ISPA_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_FIELD                     _MK_FIELD_CONST(0x1, PMC_IMPL_PART_ISPA_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SHIFT)
#define PMC_IMPL_PART_ISPA_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_RANGE                     2:2
#define PMC_IMPL_PART_ISPA_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_WOFFSET                   0x0
#define PMC_IMPL_PART_ISPA_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_DEFAULT                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_ISPA_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_ISPA_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_ISPA_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_ISPA_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_ISPA_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_ISPA_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_INIT_ENUM                 OFF
#define PMC_IMPL_PART_ISPA_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_OFF                       _MK_ENUM_CONST(0)
#define PMC_IMPL_PART_ISPA_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_ON                        _MK_ENUM_CONST(1)

#define PMC_IMPL_PART_ISPA_POWER_GATE_CONTROL_0_START_SHIFT                     _MK_SHIFT_CONST(8)
#define PMC_IMPL_PART_ISPA_POWER_GATE_CONTROL_0_START_FIELD                     _MK_FIELD_CONST(0x1, PMC_IMPL_PART_ISPA_POWER_GATE_CONTROL_0_START_SHIFT)
#define PMC_IMPL_PART_ISPA_POWER_GATE_CONTROL_0_START_RANGE                     8:8
#define PMC_IMPL_PART_ISPA_POWER_GATE_CONTROL_0_START_WOFFSET                   0x0
#define PMC_IMPL_PART_ISPA_POWER_GATE_CONTROL_0_START_DEFAULT                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_ISPA_POWER_GATE_CONTROL_0_START_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_ISPA_POWER_GATE_CONTROL_0_START_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_ISPA_POWER_GATE_CONTROL_0_START_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_ISPA_POWER_GATE_CONTROL_0_START_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_ISPA_POWER_GATE_CONTROL_0_START_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_ISPA_POWER_GATE_CONTROL_0_START_INIT_ENUM                 DONE
#define PMC_IMPL_PART_ISPA_POWER_GATE_CONTROL_0_START_DONE                      _MK_ENUM_CONST(0)
#define PMC_IMPL_PART_ISPA_POWER_GATE_CONTROL_0_START_PENDING                   _MK_ENUM_CONST(1)

#define PMC_IMPL_PART_ISPA_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SHIFT                       _MK_SHIFT_CONST(31)
#define PMC_IMPL_PART_ISPA_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_FIELD                       _MK_FIELD_CONST(0x1, PMC_IMPL_PART_ISPA_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SHIFT)
#define PMC_IMPL_PART_ISPA_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_RANGE                       31:31
#define PMC_IMPL_PART_ISPA_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_WOFFSET                     0x0
#define PMC_IMPL_PART_ISPA_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_DEFAULT                     _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_ISPA_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_ISPA_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_ISPA_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_ISPA_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_ISPA_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_ISPA_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_INIT_ENUM                   ENABLE
#define PMC_IMPL_PART_ISPA_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_DISABLE                     _MK_ENUM_CONST(0)
#define PMC_IMPL_PART_ISPA_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_ENABLE                      _MK_ENUM_CONST(1)


// Register PMC_IMPL_PART_ISPA_POWER_GATE_STATUS_0
#define PMC_IMPL_PART_ISPA_POWER_GATE_STATUS_0                  _MK_ADDR_CONST(0x248)
#define PMC_IMPL_PART_ISPA_POWER_GATE_STATUS_0_SECURE                   0x0
#define PMC_IMPL_PART_ISPA_POWER_GATE_STATUS_0_DUAL                     0x0
#define PMC_IMPL_PART_ISPA_POWER_GATE_STATUS_0_SCR                      PG_ISPA_SCR_0
#define PMC_IMPL_PART_ISPA_POWER_GATE_STATUS_0_WORD_COUNT                       0x1
#define PMC_IMPL_PART_ISPA_POWER_GATE_STATUS_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_ISPA_POWER_GATE_STATUS_0_RESET_MASK                       _MK_MASK_CONST(0x7)
#define PMC_IMPL_PART_ISPA_POWER_GATE_STATUS_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_ISPA_POWER_GATE_STATUS_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_ISPA_POWER_GATE_STATUS_0_READ_MASK                        _MK_MASK_CONST(0x7)
#define PMC_IMPL_PART_ISPA_POWER_GATE_STATUS_0_WRITE_MASK                       _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_ISPA_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SHIFT                    _MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_ISPA_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_FIELD                    _MK_FIELD_CONST(0x1, PMC_IMPL_PART_ISPA_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SHIFT)
#define PMC_IMPL_PART_ISPA_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_RANGE                    0:0
#define PMC_IMPL_PART_ISPA_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_WOFFSET                  0x0
#define PMC_IMPL_PART_ISPA_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_DEFAULT                  _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_ISPA_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_ISPA_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_ISPA_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_ISPA_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_ISPA_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_ISPA_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_INIT_ENUM                        OFF
#define PMC_IMPL_PART_ISPA_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_OFF                      _MK_ENUM_CONST(0)
#define PMC_IMPL_PART_ISPA_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_ON                       _MK_ENUM_CONST(1)

#define PMC_IMPL_PART_ISPA_POWER_GATE_STATUS_0_SRAM_RET_STS_SHIFT                       _MK_SHIFT_CONST(1)
#define PMC_IMPL_PART_ISPA_POWER_GATE_STATUS_0_SRAM_RET_STS_FIELD                       _MK_FIELD_CONST(0x1, PMC_IMPL_PART_ISPA_POWER_GATE_STATUS_0_SRAM_RET_STS_SHIFT)
#define PMC_IMPL_PART_ISPA_POWER_GATE_STATUS_0_SRAM_RET_STS_RANGE                       1:1
#define PMC_IMPL_PART_ISPA_POWER_GATE_STATUS_0_SRAM_RET_STS_WOFFSET                     0x0
#define PMC_IMPL_PART_ISPA_POWER_GATE_STATUS_0_SRAM_RET_STS_DEFAULT                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_ISPA_POWER_GATE_STATUS_0_SRAM_RET_STS_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_ISPA_POWER_GATE_STATUS_0_SRAM_RET_STS_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_ISPA_POWER_GATE_STATUS_0_SRAM_RET_STS_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_ISPA_POWER_GATE_STATUS_0_SRAM_RET_STS_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_ISPA_POWER_GATE_STATUS_0_SRAM_RET_STS_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_ISPA_POWER_GATE_STATUS_0_SRAM_RET_STS_INIT_ENUM                   OFF
#define PMC_IMPL_PART_ISPA_POWER_GATE_STATUS_0_SRAM_RET_STS_OFF                 _MK_ENUM_CONST(0)
#define PMC_IMPL_PART_ISPA_POWER_GATE_STATUS_0_SRAM_RET_STS_ON                  _MK_ENUM_CONST(1)

#define PMC_IMPL_PART_ISPA_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SHIFT                     _MK_SHIFT_CONST(2)
#define PMC_IMPL_PART_ISPA_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_FIELD                     _MK_FIELD_CONST(0x1, PMC_IMPL_PART_ISPA_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SHIFT)
#define PMC_IMPL_PART_ISPA_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_RANGE                     2:2
#define PMC_IMPL_PART_ISPA_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_WOFFSET                   0x0
#define PMC_IMPL_PART_ISPA_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_DEFAULT                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_ISPA_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_ISPA_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_ISPA_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_ISPA_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_ISPA_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_ISPA_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_INIT_ENUM                 OFF
#define PMC_IMPL_PART_ISPA_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_OFF                       _MK_ENUM_CONST(0)
#define PMC_IMPL_PART_ISPA_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_ON                        _MK_ENUM_CONST(1)


// Register PMC_IMPL_PART_ISPA_CLAMP_CONTROL_0
#define PMC_IMPL_PART_ISPA_CLAMP_CONTROL_0                      _MK_ADDR_CONST(0x24c)
#define PMC_IMPL_PART_ISPA_CLAMP_CONTROL_0_SECURE                       0x0
#define PMC_IMPL_PART_ISPA_CLAMP_CONTROL_0_DUAL                         0x0
#define PMC_IMPL_PART_ISPA_CLAMP_CONTROL_0_SCR                  PG_ISPA_SCR_0
#define PMC_IMPL_PART_ISPA_CLAMP_CONTROL_0_WORD_COUNT                   0x1
#define PMC_IMPL_PART_ISPA_CLAMP_CONTROL_0_RESET_VAL                    _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_ISPA_CLAMP_CONTROL_0_RESET_MASK                   _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_ISPA_CLAMP_CONTROL_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_ISPA_CLAMP_CONTROL_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_ISPA_CLAMP_CONTROL_0_READ_MASK                    _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_ISPA_CLAMP_CONTROL_0_WRITE_MASK                   _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_ISPA_CLAMP_CONTROL_0_CLAMP_SHIFT                  _MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_ISPA_CLAMP_CONTROL_0_CLAMP_FIELD                  _MK_FIELD_CONST(0x1, PMC_IMPL_PART_ISPA_CLAMP_CONTROL_0_CLAMP_SHIFT)
#define PMC_IMPL_PART_ISPA_CLAMP_CONTROL_0_CLAMP_RANGE                  0:0
#define PMC_IMPL_PART_ISPA_CLAMP_CONTROL_0_CLAMP_WOFFSET                        0x0
#define PMC_IMPL_PART_ISPA_CLAMP_CONTROL_0_CLAMP_DEFAULT                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_ISPA_CLAMP_CONTROL_0_CLAMP_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_ISPA_CLAMP_CONTROL_0_CLAMP_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_ISPA_CLAMP_CONTROL_0_CLAMP_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_ISPA_CLAMP_CONTROL_0_CLAMP_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_ISPA_CLAMP_CONTROL_0_CLAMP_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_ISPA_CLAMP_CONTROL_0_CLAMP_INIT_ENUM                      OFF
#define PMC_IMPL_PART_ISPA_CLAMP_CONTROL_0_CLAMP_OFF                    _MK_ENUM_CONST(0)
#define PMC_IMPL_PART_ISPA_CLAMP_CONTROL_0_CLAMP_ON                     _MK_ENUM_CONST(1)


// Register PMC_IMPL_PART_NVDECA_POWER_GATE_CONTROL_0
#define PMC_IMPL_PART_NVDECA_POWER_GATE_CONTROL_0                       _MK_ADDR_CONST(0x250)
#define PMC_IMPL_PART_NVDECA_POWER_GATE_CONTROL_0_SECURE                        0x0
#define PMC_IMPL_PART_NVDECA_POWER_GATE_CONTROL_0_DUAL                  0x0
#define PMC_IMPL_PART_NVDECA_POWER_GATE_CONTROL_0_SCR                   PG_NVDECA_SCR_0
#define PMC_IMPL_PART_NVDECA_POWER_GATE_CONTROL_0_WORD_COUNT                    0x1
#define PMC_IMPL_PART_NVDECA_POWER_GATE_CONTROL_0_RESET_VAL                     _MK_MASK_CONST(0x80000000)
#define PMC_IMPL_PART_NVDECA_POWER_GATE_CONTROL_0_RESET_MASK                    _MK_MASK_CONST(0x80000107)
#define PMC_IMPL_PART_NVDECA_POWER_GATE_CONTROL_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_NVDECA_POWER_GATE_CONTROL_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_NVDECA_POWER_GATE_CONTROL_0_READ_MASK                     _MK_MASK_CONST(0x80000107)
#define PMC_IMPL_PART_NVDECA_POWER_GATE_CONTROL_0_WRITE_MASK                    _MK_MASK_CONST(0x80000107)
#define PMC_IMPL_PART_NVDECA_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SHIFT                     _MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_NVDECA_POWER_GATE_CONTROL_0_LOGIC_SLEEP_FIELD                     _MK_FIELD_CONST(0x1, PMC_IMPL_PART_NVDECA_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SHIFT)
#define PMC_IMPL_PART_NVDECA_POWER_GATE_CONTROL_0_LOGIC_SLEEP_RANGE                     0:0
#define PMC_IMPL_PART_NVDECA_POWER_GATE_CONTROL_0_LOGIC_SLEEP_WOFFSET                   0x0
#define PMC_IMPL_PART_NVDECA_POWER_GATE_CONTROL_0_LOGIC_SLEEP_DEFAULT                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_NVDECA_POWER_GATE_CONTROL_0_LOGIC_SLEEP_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_NVDECA_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_NVDECA_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_NVDECA_POWER_GATE_CONTROL_0_LOGIC_SLEEP_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_NVDECA_POWER_GATE_CONTROL_0_LOGIC_SLEEP_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_NVDECA_POWER_GATE_CONTROL_0_LOGIC_SLEEP_INIT_ENUM                 OFF
#define PMC_IMPL_PART_NVDECA_POWER_GATE_CONTROL_0_LOGIC_SLEEP_OFF                       _MK_ENUM_CONST(0)
#define PMC_IMPL_PART_NVDECA_POWER_GATE_CONTROL_0_LOGIC_SLEEP_ON                        _MK_ENUM_CONST(1)

#define PMC_IMPL_PART_NVDECA_POWER_GATE_CONTROL_0_SRAM_RET_EN_SHIFT                     _MK_SHIFT_CONST(1)
#define PMC_IMPL_PART_NVDECA_POWER_GATE_CONTROL_0_SRAM_RET_EN_FIELD                     _MK_FIELD_CONST(0x1, PMC_IMPL_PART_NVDECA_POWER_GATE_CONTROL_0_SRAM_RET_EN_SHIFT)
#define PMC_IMPL_PART_NVDECA_POWER_GATE_CONTROL_0_SRAM_RET_EN_RANGE                     1:1
#define PMC_IMPL_PART_NVDECA_POWER_GATE_CONTROL_0_SRAM_RET_EN_WOFFSET                   0x0
#define PMC_IMPL_PART_NVDECA_POWER_GATE_CONTROL_0_SRAM_RET_EN_DEFAULT                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_NVDECA_POWER_GATE_CONTROL_0_SRAM_RET_EN_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_NVDECA_POWER_GATE_CONTROL_0_SRAM_RET_EN_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_NVDECA_POWER_GATE_CONTROL_0_SRAM_RET_EN_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_NVDECA_POWER_GATE_CONTROL_0_SRAM_RET_EN_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_NVDECA_POWER_GATE_CONTROL_0_SRAM_RET_EN_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_NVDECA_POWER_GATE_CONTROL_0_SRAM_RET_EN_INIT_ENUM                 OFF
#define PMC_IMPL_PART_NVDECA_POWER_GATE_CONTROL_0_SRAM_RET_EN_OFF                       _MK_ENUM_CONST(0)
#define PMC_IMPL_PART_NVDECA_POWER_GATE_CONTROL_0_SRAM_RET_EN_ON                        _MK_ENUM_CONST(1)

#define PMC_IMPL_PART_NVDECA_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SHIFT                   _MK_SHIFT_CONST(2)
#define PMC_IMPL_PART_NVDECA_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_FIELD                   _MK_FIELD_CONST(0x1, PMC_IMPL_PART_NVDECA_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SHIFT)
#define PMC_IMPL_PART_NVDECA_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_RANGE                   2:2
#define PMC_IMPL_PART_NVDECA_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_WOFFSET                 0x0
#define PMC_IMPL_PART_NVDECA_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_DEFAULT                 _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_NVDECA_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_NVDECA_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_NVDECA_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_NVDECA_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_NVDECA_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_NVDECA_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_INIT_ENUM                       OFF
#define PMC_IMPL_PART_NVDECA_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_OFF                     _MK_ENUM_CONST(0)
#define PMC_IMPL_PART_NVDECA_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_ON                      _MK_ENUM_CONST(1)

#define PMC_IMPL_PART_NVDECA_POWER_GATE_CONTROL_0_START_SHIFT                   _MK_SHIFT_CONST(8)
#define PMC_IMPL_PART_NVDECA_POWER_GATE_CONTROL_0_START_FIELD                   _MK_FIELD_CONST(0x1, PMC_IMPL_PART_NVDECA_POWER_GATE_CONTROL_0_START_SHIFT)
#define PMC_IMPL_PART_NVDECA_POWER_GATE_CONTROL_0_START_RANGE                   8:8
#define PMC_IMPL_PART_NVDECA_POWER_GATE_CONTROL_0_START_WOFFSET                 0x0
#define PMC_IMPL_PART_NVDECA_POWER_GATE_CONTROL_0_START_DEFAULT                 _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_NVDECA_POWER_GATE_CONTROL_0_START_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_NVDECA_POWER_GATE_CONTROL_0_START_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_NVDECA_POWER_GATE_CONTROL_0_START_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_NVDECA_POWER_GATE_CONTROL_0_START_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_NVDECA_POWER_GATE_CONTROL_0_START_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_NVDECA_POWER_GATE_CONTROL_0_START_INIT_ENUM                       DONE
#define PMC_IMPL_PART_NVDECA_POWER_GATE_CONTROL_0_START_DONE                    _MK_ENUM_CONST(0)
#define PMC_IMPL_PART_NVDECA_POWER_GATE_CONTROL_0_START_PENDING                 _MK_ENUM_CONST(1)

#define PMC_IMPL_PART_NVDECA_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SHIFT                     _MK_SHIFT_CONST(31)
#define PMC_IMPL_PART_NVDECA_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_FIELD                     _MK_FIELD_CONST(0x1, PMC_IMPL_PART_NVDECA_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SHIFT)
#define PMC_IMPL_PART_NVDECA_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_RANGE                     31:31
#define PMC_IMPL_PART_NVDECA_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_WOFFSET                   0x0
#define PMC_IMPL_PART_NVDECA_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_DEFAULT                   _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_NVDECA_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_NVDECA_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_NVDECA_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_NVDECA_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_NVDECA_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_NVDECA_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_INIT_ENUM                 ENABLE
#define PMC_IMPL_PART_NVDECA_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_DISABLE                   _MK_ENUM_CONST(0)
#define PMC_IMPL_PART_NVDECA_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_ENABLE                    _MK_ENUM_CONST(1)


// Register PMC_IMPL_PART_NVDECA_POWER_GATE_STATUS_0
#define PMC_IMPL_PART_NVDECA_POWER_GATE_STATUS_0                        _MK_ADDR_CONST(0x254)
#define PMC_IMPL_PART_NVDECA_POWER_GATE_STATUS_0_SECURE                         0x0
#define PMC_IMPL_PART_NVDECA_POWER_GATE_STATUS_0_DUAL                   0x0
#define PMC_IMPL_PART_NVDECA_POWER_GATE_STATUS_0_SCR                    PG_NVDECA_SCR_0
#define PMC_IMPL_PART_NVDECA_POWER_GATE_STATUS_0_WORD_COUNT                     0x1
#define PMC_IMPL_PART_NVDECA_POWER_GATE_STATUS_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_NVDECA_POWER_GATE_STATUS_0_RESET_MASK                     _MK_MASK_CONST(0x7)
#define PMC_IMPL_PART_NVDECA_POWER_GATE_STATUS_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_NVDECA_POWER_GATE_STATUS_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_NVDECA_POWER_GATE_STATUS_0_READ_MASK                      _MK_MASK_CONST(0x7)
#define PMC_IMPL_PART_NVDECA_POWER_GATE_STATUS_0_WRITE_MASK                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_NVDECA_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SHIFT                  _MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_NVDECA_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_FIELD                  _MK_FIELD_CONST(0x1, PMC_IMPL_PART_NVDECA_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SHIFT)
#define PMC_IMPL_PART_NVDECA_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_RANGE                  0:0
#define PMC_IMPL_PART_NVDECA_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_WOFFSET                        0x0
#define PMC_IMPL_PART_NVDECA_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_DEFAULT                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_NVDECA_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_NVDECA_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_NVDECA_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_NVDECA_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_NVDECA_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_NVDECA_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_INIT_ENUM                      OFF
#define PMC_IMPL_PART_NVDECA_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_OFF                    _MK_ENUM_CONST(0)
#define PMC_IMPL_PART_NVDECA_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_ON                     _MK_ENUM_CONST(1)

#define PMC_IMPL_PART_NVDECA_POWER_GATE_STATUS_0_SRAM_RET_STS_SHIFT                     _MK_SHIFT_CONST(1)
#define PMC_IMPL_PART_NVDECA_POWER_GATE_STATUS_0_SRAM_RET_STS_FIELD                     _MK_FIELD_CONST(0x1, PMC_IMPL_PART_NVDECA_POWER_GATE_STATUS_0_SRAM_RET_STS_SHIFT)
#define PMC_IMPL_PART_NVDECA_POWER_GATE_STATUS_0_SRAM_RET_STS_RANGE                     1:1
#define PMC_IMPL_PART_NVDECA_POWER_GATE_STATUS_0_SRAM_RET_STS_WOFFSET                   0x0
#define PMC_IMPL_PART_NVDECA_POWER_GATE_STATUS_0_SRAM_RET_STS_DEFAULT                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_NVDECA_POWER_GATE_STATUS_0_SRAM_RET_STS_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_NVDECA_POWER_GATE_STATUS_0_SRAM_RET_STS_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_NVDECA_POWER_GATE_STATUS_0_SRAM_RET_STS_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_NVDECA_POWER_GATE_STATUS_0_SRAM_RET_STS_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_NVDECA_POWER_GATE_STATUS_0_SRAM_RET_STS_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_NVDECA_POWER_GATE_STATUS_0_SRAM_RET_STS_INIT_ENUM                 OFF
#define PMC_IMPL_PART_NVDECA_POWER_GATE_STATUS_0_SRAM_RET_STS_OFF                       _MK_ENUM_CONST(0)
#define PMC_IMPL_PART_NVDECA_POWER_GATE_STATUS_0_SRAM_RET_STS_ON                        _MK_ENUM_CONST(1)

#define PMC_IMPL_PART_NVDECA_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SHIFT                   _MK_SHIFT_CONST(2)
#define PMC_IMPL_PART_NVDECA_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_FIELD                   _MK_FIELD_CONST(0x1, PMC_IMPL_PART_NVDECA_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SHIFT)
#define PMC_IMPL_PART_NVDECA_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_RANGE                   2:2
#define PMC_IMPL_PART_NVDECA_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_WOFFSET                 0x0
#define PMC_IMPL_PART_NVDECA_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_DEFAULT                 _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_NVDECA_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_NVDECA_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_NVDECA_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_NVDECA_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_NVDECA_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_NVDECA_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_INIT_ENUM                       OFF
#define PMC_IMPL_PART_NVDECA_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_OFF                     _MK_ENUM_CONST(0)
#define PMC_IMPL_PART_NVDECA_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_ON                      _MK_ENUM_CONST(1)


// Register PMC_IMPL_PART_NVDECA_CLAMP_CONTROL_0
#define PMC_IMPL_PART_NVDECA_CLAMP_CONTROL_0                    _MK_ADDR_CONST(0x258)
#define PMC_IMPL_PART_NVDECA_CLAMP_CONTROL_0_SECURE                     0x0
#define PMC_IMPL_PART_NVDECA_CLAMP_CONTROL_0_DUAL                       0x0
#define PMC_IMPL_PART_NVDECA_CLAMP_CONTROL_0_SCR                        PG_NVDECA_SCR_0
#define PMC_IMPL_PART_NVDECA_CLAMP_CONTROL_0_WORD_COUNT                         0x1
#define PMC_IMPL_PART_NVDECA_CLAMP_CONTROL_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_NVDECA_CLAMP_CONTROL_0_RESET_MASK                         _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_NVDECA_CLAMP_CONTROL_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_NVDECA_CLAMP_CONTROL_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_NVDECA_CLAMP_CONTROL_0_READ_MASK                  _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_NVDECA_CLAMP_CONTROL_0_WRITE_MASK                         _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_NVDECA_CLAMP_CONTROL_0_CLAMP_SHIFT                        _MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_NVDECA_CLAMP_CONTROL_0_CLAMP_FIELD                        _MK_FIELD_CONST(0x1, PMC_IMPL_PART_NVDECA_CLAMP_CONTROL_0_CLAMP_SHIFT)
#define PMC_IMPL_PART_NVDECA_CLAMP_CONTROL_0_CLAMP_RANGE                        0:0
#define PMC_IMPL_PART_NVDECA_CLAMP_CONTROL_0_CLAMP_WOFFSET                      0x0
#define PMC_IMPL_PART_NVDECA_CLAMP_CONTROL_0_CLAMP_DEFAULT                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_NVDECA_CLAMP_CONTROL_0_CLAMP_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_NVDECA_CLAMP_CONTROL_0_CLAMP_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_NVDECA_CLAMP_CONTROL_0_CLAMP_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_NVDECA_CLAMP_CONTROL_0_CLAMP_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_NVDECA_CLAMP_CONTROL_0_CLAMP_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_NVDECA_CLAMP_CONTROL_0_CLAMP_INIT_ENUM                    OFF
#define PMC_IMPL_PART_NVDECA_CLAMP_CONTROL_0_CLAMP_OFF                  _MK_ENUM_CONST(0)
#define PMC_IMPL_PART_NVDECA_CLAMP_CONTROL_0_CLAMP_ON                   _MK_ENUM_CONST(1)


// Register PMC_IMPL_PART_NVJPG_POWER_GATE_CONTROL_0
#define PMC_IMPL_PART_NVJPG_POWER_GATE_CONTROL_0                        _MK_ADDR_CONST(0x25c)
#define PMC_IMPL_PART_NVJPG_POWER_GATE_CONTROL_0_SECURE                         0x0
#define PMC_IMPL_PART_NVJPG_POWER_GATE_CONTROL_0_DUAL                   0x0
#define PMC_IMPL_PART_NVJPG_POWER_GATE_CONTROL_0_SCR                    PG_NVJPG_SCR_0
#define PMC_IMPL_PART_NVJPG_POWER_GATE_CONTROL_0_WORD_COUNT                     0x1
#define PMC_IMPL_PART_NVJPG_POWER_GATE_CONTROL_0_RESET_VAL                      _MK_MASK_CONST(0x80000000)
#define PMC_IMPL_PART_NVJPG_POWER_GATE_CONTROL_0_RESET_MASK                     _MK_MASK_CONST(0x80000107)
#define PMC_IMPL_PART_NVJPG_POWER_GATE_CONTROL_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_NVJPG_POWER_GATE_CONTROL_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_NVJPG_POWER_GATE_CONTROL_0_READ_MASK                      _MK_MASK_CONST(0x80000107)
#define PMC_IMPL_PART_NVJPG_POWER_GATE_CONTROL_0_WRITE_MASK                     _MK_MASK_CONST(0x80000107)
#define PMC_IMPL_PART_NVJPG_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SHIFT                      _MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_NVJPG_POWER_GATE_CONTROL_0_LOGIC_SLEEP_FIELD                      _MK_FIELD_CONST(0x1, PMC_IMPL_PART_NVJPG_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SHIFT)
#define PMC_IMPL_PART_NVJPG_POWER_GATE_CONTROL_0_LOGIC_SLEEP_RANGE                      0:0
#define PMC_IMPL_PART_NVJPG_POWER_GATE_CONTROL_0_LOGIC_SLEEP_WOFFSET                    0x0
#define PMC_IMPL_PART_NVJPG_POWER_GATE_CONTROL_0_LOGIC_SLEEP_DEFAULT                    _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_NVJPG_POWER_GATE_CONTROL_0_LOGIC_SLEEP_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_NVJPG_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_NVJPG_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_NVJPG_POWER_GATE_CONTROL_0_LOGIC_SLEEP_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_NVJPG_POWER_GATE_CONTROL_0_LOGIC_SLEEP_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_NVJPG_POWER_GATE_CONTROL_0_LOGIC_SLEEP_INIT_ENUM                  OFF
#define PMC_IMPL_PART_NVJPG_POWER_GATE_CONTROL_0_LOGIC_SLEEP_OFF                        _MK_ENUM_CONST(0)
#define PMC_IMPL_PART_NVJPG_POWER_GATE_CONTROL_0_LOGIC_SLEEP_ON                 _MK_ENUM_CONST(1)

#define PMC_IMPL_PART_NVJPG_POWER_GATE_CONTROL_0_SRAM_RET_EN_SHIFT                      _MK_SHIFT_CONST(1)
#define PMC_IMPL_PART_NVJPG_POWER_GATE_CONTROL_0_SRAM_RET_EN_FIELD                      _MK_FIELD_CONST(0x1, PMC_IMPL_PART_NVJPG_POWER_GATE_CONTROL_0_SRAM_RET_EN_SHIFT)
#define PMC_IMPL_PART_NVJPG_POWER_GATE_CONTROL_0_SRAM_RET_EN_RANGE                      1:1
#define PMC_IMPL_PART_NVJPG_POWER_GATE_CONTROL_0_SRAM_RET_EN_WOFFSET                    0x0
#define PMC_IMPL_PART_NVJPG_POWER_GATE_CONTROL_0_SRAM_RET_EN_DEFAULT                    _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_NVJPG_POWER_GATE_CONTROL_0_SRAM_RET_EN_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_NVJPG_POWER_GATE_CONTROL_0_SRAM_RET_EN_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_NVJPG_POWER_GATE_CONTROL_0_SRAM_RET_EN_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_NVJPG_POWER_GATE_CONTROL_0_SRAM_RET_EN_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_NVJPG_POWER_GATE_CONTROL_0_SRAM_RET_EN_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_NVJPG_POWER_GATE_CONTROL_0_SRAM_RET_EN_INIT_ENUM                  OFF
#define PMC_IMPL_PART_NVJPG_POWER_GATE_CONTROL_0_SRAM_RET_EN_OFF                        _MK_ENUM_CONST(0)
#define PMC_IMPL_PART_NVJPG_POWER_GATE_CONTROL_0_SRAM_RET_EN_ON                 _MK_ENUM_CONST(1)

#define PMC_IMPL_PART_NVJPG_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SHIFT                    _MK_SHIFT_CONST(2)
#define PMC_IMPL_PART_NVJPG_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_FIELD                    _MK_FIELD_CONST(0x1, PMC_IMPL_PART_NVJPG_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SHIFT)
#define PMC_IMPL_PART_NVJPG_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_RANGE                    2:2
#define PMC_IMPL_PART_NVJPG_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_WOFFSET                  0x0
#define PMC_IMPL_PART_NVJPG_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_DEFAULT                  _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_NVJPG_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_NVJPG_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_NVJPG_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_NVJPG_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_NVJPG_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_NVJPG_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_INIT_ENUM                        OFF
#define PMC_IMPL_PART_NVJPG_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_OFF                      _MK_ENUM_CONST(0)
#define PMC_IMPL_PART_NVJPG_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_ON                       _MK_ENUM_CONST(1)

#define PMC_IMPL_PART_NVJPG_POWER_GATE_CONTROL_0_START_SHIFT                    _MK_SHIFT_CONST(8)
#define PMC_IMPL_PART_NVJPG_POWER_GATE_CONTROL_0_START_FIELD                    _MK_FIELD_CONST(0x1, PMC_IMPL_PART_NVJPG_POWER_GATE_CONTROL_0_START_SHIFT)
#define PMC_IMPL_PART_NVJPG_POWER_GATE_CONTROL_0_START_RANGE                    8:8
#define PMC_IMPL_PART_NVJPG_POWER_GATE_CONTROL_0_START_WOFFSET                  0x0
#define PMC_IMPL_PART_NVJPG_POWER_GATE_CONTROL_0_START_DEFAULT                  _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_NVJPG_POWER_GATE_CONTROL_0_START_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_NVJPG_POWER_GATE_CONTROL_0_START_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_NVJPG_POWER_GATE_CONTROL_0_START_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_NVJPG_POWER_GATE_CONTROL_0_START_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_NVJPG_POWER_GATE_CONTROL_0_START_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_NVJPG_POWER_GATE_CONTROL_0_START_INIT_ENUM                        DONE
#define PMC_IMPL_PART_NVJPG_POWER_GATE_CONTROL_0_START_DONE                     _MK_ENUM_CONST(0)
#define PMC_IMPL_PART_NVJPG_POWER_GATE_CONTROL_0_START_PENDING                  _MK_ENUM_CONST(1)

#define PMC_IMPL_PART_NVJPG_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SHIFT                      _MK_SHIFT_CONST(31)
#define PMC_IMPL_PART_NVJPG_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_FIELD                      _MK_FIELD_CONST(0x1, PMC_IMPL_PART_NVJPG_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SHIFT)
#define PMC_IMPL_PART_NVJPG_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_RANGE                      31:31
#define PMC_IMPL_PART_NVJPG_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_WOFFSET                    0x0
#define PMC_IMPL_PART_NVJPG_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_DEFAULT                    _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_NVJPG_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_NVJPG_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_NVJPG_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_NVJPG_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_NVJPG_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_NVJPG_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_INIT_ENUM                  ENABLE
#define PMC_IMPL_PART_NVJPG_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_DISABLE                    _MK_ENUM_CONST(0)
#define PMC_IMPL_PART_NVJPG_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_ENABLE                     _MK_ENUM_CONST(1)


// Register PMC_IMPL_PART_NVJPG_POWER_GATE_STATUS_0
#define PMC_IMPL_PART_NVJPG_POWER_GATE_STATUS_0                 _MK_ADDR_CONST(0x260)
#define PMC_IMPL_PART_NVJPG_POWER_GATE_STATUS_0_SECURE                  0x0
#define PMC_IMPL_PART_NVJPG_POWER_GATE_STATUS_0_DUAL                    0x0
#define PMC_IMPL_PART_NVJPG_POWER_GATE_STATUS_0_SCR                     PG_NVJPG_SCR_0
#define PMC_IMPL_PART_NVJPG_POWER_GATE_STATUS_0_WORD_COUNT                      0x1
#define PMC_IMPL_PART_NVJPG_POWER_GATE_STATUS_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_NVJPG_POWER_GATE_STATUS_0_RESET_MASK                      _MK_MASK_CONST(0x7)
#define PMC_IMPL_PART_NVJPG_POWER_GATE_STATUS_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_NVJPG_POWER_GATE_STATUS_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_NVJPG_POWER_GATE_STATUS_0_READ_MASK                       _MK_MASK_CONST(0x7)
#define PMC_IMPL_PART_NVJPG_POWER_GATE_STATUS_0_WRITE_MASK                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_NVJPG_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SHIFT                   _MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_NVJPG_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_FIELD                   _MK_FIELD_CONST(0x1, PMC_IMPL_PART_NVJPG_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SHIFT)
#define PMC_IMPL_PART_NVJPG_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_RANGE                   0:0
#define PMC_IMPL_PART_NVJPG_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_WOFFSET                 0x0
#define PMC_IMPL_PART_NVJPG_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_DEFAULT                 _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_NVJPG_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_NVJPG_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_NVJPG_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_NVJPG_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_NVJPG_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_NVJPG_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_INIT_ENUM                       OFF
#define PMC_IMPL_PART_NVJPG_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_OFF                     _MK_ENUM_CONST(0)
#define PMC_IMPL_PART_NVJPG_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_ON                      _MK_ENUM_CONST(1)

#define PMC_IMPL_PART_NVJPG_POWER_GATE_STATUS_0_SRAM_RET_STS_SHIFT                      _MK_SHIFT_CONST(1)
#define PMC_IMPL_PART_NVJPG_POWER_GATE_STATUS_0_SRAM_RET_STS_FIELD                      _MK_FIELD_CONST(0x1, PMC_IMPL_PART_NVJPG_POWER_GATE_STATUS_0_SRAM_RET_STS_SHIFT)
#define PMC_IMPL_PART_NVJPG_POWER_GATE_STATUS_0_SRAM_RET_STS_RANGE                      1:1
#define PMC_IMPL_PART_NVJPG_POWER_GATE_STATUS_0_SRAM_RET_STS_WOFFSET                    0x0
#define PMC_IMPL_PART_NVJPG_POWER_GATE_STATUS_0_SRAM_RET_STS_DEFAULT                    _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_NVJPG_POWER_GATE_STATUS_0_SRAM_RET_STS_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_NVJPG_POWER_GATE_STATUS_0_SRAM_RET_STS_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_NVJPG_POWER_GATE_STATUS_0_SRAM_RET_STS_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_NVJPG_POWER_GATE_STATUS_0_SRAM_RET_STS_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_NVJPG_POWER_GATE_STATUS_0_SRAM_RET_STS_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_NVJPG_POWER_GATE_STATUS_0_SRAM_RET_STS_INIT_ENUM                  OFF
#define PMC_IMPL_PART_NVJPG_POWER_GATE_STATUS_0_SRAM_RET_STS_OFF                        _MK_ENUM_CONST(0)
#define PMC_IMPL_PART_NVJPG_POWER_GATE_STATUS_0_SRAM_RET_STS_ON                 _MK_ENUM_CONST(1)

#define PMC_IMPL_PART_NVJPG_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SHIFT                    _MK_SHIFT_CONST(2)
#define PMC_IMPL_PART_NVJPG_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_FIELD                    _MK_FIELD_CONST(0x1, PMC_IMPL_PART_NVJPG_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SHIFT)
#define PMC_IMPL_PART_NVJPG_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_RANGE                    2:2
#define PMC_IMPL_PART_NVJPG_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_WOFFSET                  0x0
#define PMC_IMPL_PART_NVJPG_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_DEFAULT                  _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_NVJPG_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_NVJPG_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_NVJPG_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_NVJPG_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_NVJPG_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_NVJPG_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_INIT_ENUM                        OFF
#define PMC_IMPL_PART_NVJPG_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_OFF                      _MK_ENUM_CONST(0)
#define PMC_IMPL_PART_NVJPG_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_ON                       _MK_ENUM_CONST(1)


// Register PMC_IMPL_PART_NVJPG_CLAMP_CONTROL_0
#define PMC_IMPL_PART_NVJPG_CLAMP_CONTROL_0                     _MK_ADDR_CONST(0x264)
#define PMC_IMPL_PART_NVJPG_CLAMP_CONTROL_0_SECURE                      0x0
#define PMC_IMPL_PART_NVJPG_CLAMP_CONTROL_0_DUAL                        0x0
#define PMC_IMPL_PART_NVJPG_CLAMP_CONTROL_0_SCR                         PG_NVJPG_SCR_0
#define PMC_IMPL_PART_NVJPG_CLAMP_CONTROL_0_WORD_COUNT                  0x1
#define PMC_IMPL_PART_NVJPG_CLAMP_CONTROL_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_NVJPG_CLAMP_CONTROL_0_RESET_MASK                  _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_NVJPG_CLAMP_CONTROL_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_NVJPG_CLAMP_CONTROL_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_NVJPG_CLAMP_CONTROL_0_READ_MASK                   _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_NVJPG_CLAMP_CONTROL_0_WRITE_MASK                  _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_NVJPG_CLAMP_CONTROL_0_CLAMP_SHIFT                 _MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_NVJPG_CLAMP_CONTROL_0_CLAMP_FIELD                 _MK_FIELD_CONST(0x1, PMC_IMPL_PART_NVJPG_CLAMP_CONTROL_0_CLAMP_SHIFT)
#define PMC_IMPL_PART_NVJPG_CLAMP_CONTROL_0_CLAMP_RANGE                 0:0
#define PMC_IMPL_PART_NVJPG_CLAMP_CONTROL_0_CLAMP_WOFFSET                       0x0
#define PMC_IMPL_PART_NVJPG_CLAMP_CONTROL_0_CLAMP_DEFAULT                       _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_NVJPG_CLAMP_CONTROL_0_CLAMP_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_NVJPG_CLAMP_CONTROL_0_CLAMP_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_NVJPG_CLAMP_CONTROL_0_CLAMP_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_NVJPG_CLAMP_CONTROL_0_CLAMP_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_NVJPG_CLAMP_CONTROL_0_CLAMP_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_NVJPG_CLAMP_CONTROL_0_CLAMP_INIT_ENUM                     OFF
#define PMC_IMPL_PART_NVJPG_CLAMP_CONTROL_0_CLAMP_OFF                   _MK_ENUM_CONST(0)
#define PMC_IMPL_PART_NVJPG_CLAMP_CONTROL_0_CLAMP_ON                    _MK_ENUM_CONST(1)


// Reserved address 0x268

// Reserved address 0x26c

// Reserved address 0x270

// Reserved address 0x274

// Reserved address 0x278

// Reserved address 0x27c

// Register PMC_IMPL_PART_SAX_POWER_GATE_CONTROL_0
#define PMC_IMPL_PART_SAX_POWER_GATE_CONTROL_0                  _MK_ADDR_CONST(0x280)
#define PMC_IMPL_PART_SAX_POWER_GATE_CONTROL_0_SECURE                   0x0
#define PMC_IMPL_PART_SAX_POWER_GATE_CONTROL_0_DUAL                     0x0
#define PMC_IMPL_PART_SAX_POWER_GATE_CONTROL_0_SCR                      PG_SAX_SCR_0
#define PMC_IMPL_PART_SAX_POWER_GATE_CONTROL_0_WORD_COUNT                       0x1
#define PMC_IMPL_PART_SAX_POWER_GATE_CONTROL_0_RESET_VAL                        _MK_MASK_CONST(0x80000000)
#define PMC_IMPL_PART_SAX_POWER_GATE_CONTROL_0_RESET_MASK                       _MK_MASK_CONST(0x80000107)
#define PMC_IMPL_PART_SAX_POWER_GATE_CONTROL_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_SAX_POWER_GATE_CONTROL_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_SAX_POWER_GATE_CONTROL_0_READ_MASK                        _MK_MASK_CONST(0x80000107)
#define PMC_IMPL_PART_SAX_POWER_GATE_CONTROL_0_WRITE_MASK                       _MK_MASK_CONST(0x80000107)
#define PMC_IMPL_PART_SAX_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SHIFT                        _MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_SAX_POWER_GATE_CONTROL_0_LOGIC_SLEEP_FIELD                        _MK_FIELD_CONST(0x1, PMC_IMPL_PART_SAX_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SHIFT)
#define PMC_IMPL_PART_SAX_POWER_GATE_CONTROL_0_LOGIC_SLEEP_RANGE                        0:0
#define PMC_IMPL_PART_SAX_POWER_GATE_CONTROL_0_LOGIC_SLEEP_WOFFSET                      0x0
#define PMC_IMPL_PART_SAX_POWER_GATE_CONTROL_0_LOGIC_SLEEP_DEFAULT                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_SAX_POWER_GATE_CONTROL_0_LOGIC_SLEEP_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_SAX_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_SAX_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_SAX_POWER_GATE_CONTROL_0_LOGIC_SLEEP_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_SAX_POWER_GATE_CONTROL_0_LOGIC_SLEEP_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_SAX_POWER_GATE_CONTROL_0_LOGIC_SLEEP_INIT_ENUM                    OFF
#define PMC_IMPL_PART_SAX_POWER_GATE_CONTROL_0_LOGIC_SLEEP_OFF                  _MK_ENUM_CONST(0)
#define PMC_IMPL_PART_SAX_POWER_GATE_CONTROL_0_LOGIC_SLEEP_ON                   _MK_ENUM_CONST(1)

#define PMC_IMPL_PART_SAX_POWER_GATE_CONTROL_0_SRAM_RET_EN_SHIFT                        _MK_SHIFT_CONST(1)
#define PMC_IMPL_PART_SAX_POWER_GATE_CONTROL_0_SRAM_RET_EN_FIELD                        _MK_FIELD_CONST(0x1, PMC_IMPL_PART_SAX_POWER_GATE_CONTROL_0_SRAM_RET_EN_SHIFT)
#define PMC_IMPL_PART_SAX_POWER_GATE_CONTROL_0_SRAM_RET_EN_RANGE                        1:1
#define PMC_IMPL_PART_SAX_POWER_GATE_CONTROL_0_SRAM_RET_EN_WOFFSET                      0x0
#define PMC_IMPL_PART_SAX_POWER_GATE_CONTROL_0_SRAM_RET_EN_DEFAULT                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_SAX_POWER_GATE_CONTROL_0_SRAM_RET_EN_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_SAX_POWER_GATE_CONTROL_0_SRAM_RET_EN_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_SAX_POWER_GATE_CONTROL_0_SRAM_RET_EN_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_SAX_POWER_GATE_CONTROL_0_SRAM_RET_EN_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_SAX_POWER_GATE_CONTROL_0_SRAM_RET_EN_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_SAX_POWER_GATE_CONTROL_0_SRAM_RET_EN_INIT_ENUM                    OFF
#define PMC_IMPL_PART_SAX_POWER_GATE_CONTROL_0_SRAM_RET_EN_OFF                  _MK_ENUM_CONST(0)
#define PMC_IMPL_PART_SAX_POWER_GATE_CONTROL_0_SRAM_RET_EN_ON                   _MK_ENUM_CONST(1)

#define PMC_IMPL_PART_SAX_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SHIFT                      _MK_SHIFT_CONST(2)
#define PMC_IMPL_PART_SAX_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_FIELD                      _MK_FIELD_CONST(0x1, PMC_IMPL_PART_SAX_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SHIFT)
#define PMC_IMPL_PART_SAX_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_RANGE                      2:2
#define PMC_IMPL_PART_SAX_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_WOFFSET                    0x0
#define PMC_IMPL_PART_SAX_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_DEFAULT                    _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_SAX_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_SAX_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_SAX_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_SAX_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_SAX_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_SAX_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_INIT_ENUM                  OFF
#define PMC_IMPL_PART_SAX_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_OFF                        _MK_ENUM_CONST(0)
#define PMC_IMPL_PART_SAX_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_ON                 _MK_ENUM_CONST(1)

#define PMC_IMPL_PART_SAX_POWER_GATE_CONTROL_0_START_SHIFT                      _MK_SHIFT_CONST(8)
#define PMC_IMPL_PART_SAX_POWER_GATE_CONTROL_0_START_FIELD                      _MK_FIELD_CONST(0x1, PMC_IMPL_PART_SAX_POWER_GATE_CONTROL_0_START_SHIFT)
#define PMC_IMPL_PART_SAX_POWER_GATE_CONTROL_0_START_RANGE                      8:8
#define PMC_IMPL_PART_SAX_POWER_GATE_CONTROL_0_START_WOFFSET                    0x0
#define PMC_IMPL_PART_SAX_POWER_GATE_CONTROL_0_START_DEFAULT                    _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_SAX_POWER_GATE_CONTROL_0_START_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_SAX_POWER_GATE_CONTROL_0_START_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_SAX_POWER_GATE_CONTROL_0_START_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_SAX_POWER_GATE_CONTROL_0_START_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_SAX_POWER_GATE_CONTROL_0_START_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_SAX_POWER_GATE_CONTROL_0_START_INIT_ENUM                  DONE
#define PMC_IMPL_PART_SAX_POWER_GATE_CONTROL_0_START_DONE                       _MK_ENUM_CONST(0)
#define PMC_IMPL_PART_SAX_POWER_GATE_CONTROL_0_START_PENDING                    _MK_ENUM_CONST(1)

#define PMC_IMPL_PART_SAX_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SHIFT                        _MK_SHIFT_CONST(31)
#define PMC_IMPL_PART_SAX_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_FIELD                        _MK_FIELD_CONST(0x1, PMC_IMPL_PART_SAX_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SHIFT)
#define PMC_IMPL_PART_SAX_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_RANGE                        31:31
#define PMC_IMPL_PART_SAX_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_WOFFSET                      0x0
#define PMC_IMPL_PART_SAX_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_DEFAULT                      _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_SAX_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_SAX_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_SAX_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_SAX_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_SAX_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_SAX_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_INIT_ENUM                    ENABLE
#define PMC_IMPL_PART_SAX_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_DISABLE                      _MK_ENUM_CONST(0)
#define PMC_IMPL_PART_SAX_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_ENABLE                       _MK_ENUM_CONST(1)


// Register PMC_IMPL_PART_SAX_POWER_GATE_STATUS_0
#define PMC_IMPL_PART_SAX_POWER_GATE_STATUS_0                   _MK_ADDR_CONST(0x284)
#define PMC_IMPL_PART_SAX_POWER_GATE_STATUS_0_SECURE                    0x0
#define PMC_IMPL_PART_SAX_POWER_GATE_STATUS_0_DUAL                      0x0
#define PMC_IMPL_PART_SAX_POWER_GATE_STATUS_0_SCR                       PG_SAX_SCR_0
#define PMC_IMPL_PART_SAX_POWER_GATE_STATUS_0_WORD_COUNT                        0x1
#define PMC_IMPL_PART_SAX_POWER_GATE_STATUS_0_RESET_VAL                         _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_SAX_POWER_GATE_STATUS_0_RESET_MASK                        _MK_MASK_CONST(0x7)
#define PMC_IMPL_PART_SAX_POWER_GATE_STATUS_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_SAX_POWER_GATE_STATUS_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_SAX_POWER_GATE_STATUS_0_READ_MASK                         _MK_MASK_CONST(0x7)
#define PMC_IMPL_PART_SAX_POWER_GATE_STATUS_0_WRITE_MASK                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_SAX_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SHIFT                     _MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_SAX_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_FIELD                     _MK_FIELD_CONST(0x1, PMC_IMPL_PART_SAX_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SHIFT)
#define PMC_IMPL_PART_SAX_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_RANGE                     0:0
#define PMC_IMPL_PART_SAX_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_WOFFSET                   0x0
#define PMC_IMPL_PART_SAX_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_DEFAULT                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_SAX_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_SAX_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_SAX_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_SAX_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_SAX_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_SAX_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_INIT_ENUM                 OFF
#define PMC_IMPL_PART_SAX_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_OFF                       _MK_ENUM_CONST(0)
#define PMC_IMPL_PART_SAX_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_ON                        _MK_ENUM_CONST(1)

#define PMC_IMPL_PART_SAX_POWER_GATE_STATUS_0_SRAM_RET_STS_SHIFT                        _MK_SHIFT_CONST(1)
#define PMC_IMPL_PART_SAX_POWER_GATE_STATUS_0_SRAM_RET_STS_FIELD                        _MK_FIELD_CONST(0x1, PMC_IMPL_PART_SAX_POWER_GATE_STATUS_0_SRAM_RET_STS_SHIFT)
#define PMC_IMPL_PART_SAX_POWER_GATE_STATUS_0_SRAM_RET_STS_RANGE                        1:1
#define PMC_IMPL_PART_SAX_POWER_GATE_STATUS_0_SRAM_RET_STS_WOFFSET                      0x0
#define PMC_IMPL_PART_SAX_POWER_GATE_STATUS_0_SRAM_RET_STS_DEFAULT                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_SAX_POWER_GATE_STATUS_0_SRAM_RET_STS_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_SAX_POWER_GATE_STATUS_0_SRAM_RET_STS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_SAX_POWER_GATE_STATUS_0_SRAM_RET_STS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_SAX_POWER_GATE_STATUS_0_SRAM_RET_STS_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_SAX_POWER_GATE_STATUS_0_SRAM_RET_STS_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_SAX_POWER_GATE_STATUS_0_SRAM_RET_STS_INIT_ENUM                    OFF
#define PMC_IMPL_PART_SAX_POWER_GATE_STATUS_0_SRAM_RET_STS_OFF                  _MK_ENUM_CONST(0)
#define PMC_IMPL_PART_SAX_POWER_GATE_STATUS_0_SRAM_RET_STS_ON                   _MK_ENUM_CONST(1)

#define PMC_IMPL_PART_SAX_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SHIFT                      _MK_SHIFT_CONST(2)
#define PMC_IMPL_PART_SAX_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_FIELD                      _MK_FIELD_CONST(0x1, PMC_IMPL_PART_SAX_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SHIFT)
#define PMC_IMPL_PART_SAX_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_RANGE                      2:2
#define PMC_IMPL_PART_SAX_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_WOFFSET                    0x0
#define PMC_IMPL_PART_SAX_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_DEFAULT                    _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_SAX_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_SAX_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_SAX_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_SAX_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_SAX_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_SAX_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_INIT_ENUM                  OFF
#define PMC_IMPL_PART_SAX_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_OFF                        _MK_ENUM_CONST(0)
#define PMC_IMPL_PART_SAX_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_ON                 _MK_ENUM_CONST(1)


// Register PMC_IMPL_PART_SAX_CLAMP_CONTROL_0
#define PMC_IMPL_PART_SAX_CLAMP_CONTROL_0                       _MK_ADDR_CONST(0x288)
#define PMC_IMPL_PART_SAX_CLAMP_CONTROL_0_SECURE                        0x0
#define PMC_IMPL_PART_SAX_CLAMP_CONTROL_0_DUAL                  0x0
#define PMC_IMPL_PART_SAX_CLAMP_CONTROL_0_SCR                   PG_SAX_SCR_0
#define PMC_IMPL_PART_SAX_CLAMP_CONTROL_0_WORD_COUNT                    0x1
#define PMC_IMPL_PART_SAX_CLAMP_CONTROL_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_SAX_CLAMP_CONTROL_0_RESET_MASK                    _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_SAX_CLAMP_CONTROL_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_SAX_CLAMP_CONTROL_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_SAX_CLAMP_CONTROL_0_READ_MASK                     _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_SAX_CLAMP_CONTROL_0_WRITE_MASK                    _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_SAX_CLAMP_CONTROL_0_CLAMP_SHIFT                   _MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_SAX_CLAMP_CONTROL_0_CLAMP_FIELD                   _MK_FIELD_CONST(0x1, PMC_IMPL_PART_SAX_CLAMP_CONTROL_0_CLAMP_SHIFT)
#define PMC_IMPL_PART_SAX_CLAMP_CONTROL_0_CLAMP_RANGE                   0:0
#define PMC_IMPL_PART_SAX_CLAMP_CONTROL_0_CLAMP_WOFFSET                 0x0
#define PMC_IMPL_PART_SAX_CLAMP_CONTROL_0_CLAMP_DEFAULT                 _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_SAX_CLAMP_CONTROL_0_CLAMP_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_SAX_CLAMP_CONTROL_0_CLAMP_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_SAX_CLAMP_CONTROL_0_CLAMP_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_SAX_CLAMP_CONTROL_0_CLAMP_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_SAX_CLAMP_CONTROL_0_CLAMP_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_SAX_CLAMP_CONTROL_0_CLAMP_INIT_ENUM                       OFF
#define PMC_IMPL_PART_SAX_CLAMP_CONTROL_0_CLAMP_OFF                     _MK_ENUM_CONST(0)
#define PMC_IMPL_PART_SAX_CLAMP_CONTROL_0_CLAMP_ON                      _MK_ENUM_CONST(1)


// Register PMC_IMPL_PART_VE_POWER_GATE_CONTROL_0
#define PMC_IMPL_PART_VE_POWER_GATE_CONTROL_0                   _MK_ADDR_CONST(0x28c)
#define PMC_IMPL_PART_VE_POWER_GATE_CONTROL_0_SECURE                    0x0
#define PMC_IMPL_PART_VE_POWER_GATE_CONTROL_0_DUAL                      0x0
#define PMC_IMPL_PART_VE_POWER_GATE_CONTROL_0_SCR                       PG_VE_SCR_0
#define PMC_IMPL_PART_VE_POWER_GATE_CONTROL_0_WORD_COUNT                        0x1
#define PMC_IMPL_PART_VE_POWER_GATE_CONTROL_0_RESET_VAL                         _MK_MASK_CONST(0x80000000)
#define PMC_IMPL_PART_VE_POWER_GATE_CONTROL_0_RESET_MASK                        _MK_MASK_CONST(0x80000107)
#define PMC_IMPL_PART_VE_POWER_GATE_CONTROL_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_VE_POWER_GATE_CONTROL_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_VE_POWER_GATE_CONTROL_0_READ_MASK                         _MK_MASK_CONST(0x80000107)
#define PMC_IMPL_PART_VE_POWER_GATE_CONTROL_0_WRITE_MASK                        _MK_MASK_CONST(0x80000107)
#define PMC_IMPL_PART_VE_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SHIFT                 _MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_VE_POWER_GATE_CONTROL_0_LOGIC_SLEEP_FIELD                 _MK_FIELD_CONST(0x1, PMC_IMPL_PART_VE_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SHIFT)
#define PMC_IMPL_PART_VE_POWER_GATE_CONTROL_0_LOGIC_SLEEP_RANGE                 0:0
#define PMC_IMPL_PART_VE_POWER_GATE_CONTROL_0_LOGIC_SLEEP_WOFFSET                       0x0
#define PMC_IMPL_PART_VE_POWER_GATE_CONTROL_0_LOGIC_SLEEP_DEFAULT                       _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_VE_POWER_GATE_CONTROL_0_LOGIC_SLEEP_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_VE_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_VE_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_VE_POWER_GATE_CONTROL_0_LOGIC_SLEEP_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_VE_POWER_GATE_CONTROL_0_LOGIC_SLEEP_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_VE_POWER_GATE_CONTROL_0_LOGIC_SLEEP_INIT_ENUM                     OFF
#define PMC_IMPL_PART_VE_POWER_GATE_CONTROL_0_LOGIC_SLEEP_OFF                   _MK_ENUM_CONST(0)
#define PMC_IMPL_PART_VE_POWER_GATE_CONTROL_0_LOGIC_SLEEP_ON                    _MK_ENUM_CONST(1)

#define PMC_IMPL_PART_VE_POWER_GATE_CONTROL_0_SRAM_RET_EN_SHIFT                 _MK_SHIFT_CONST(1)
#define PMC_IMPL_PART_VE_POWER_GATE_CONTROL_0_SRAM_RET_EN_FIELD                 _MK_FIELD_CONST(0x1, PMC_IMPL_PART_VE_POWER_GATE_CONTROL_0_SRAM_RET_EN_SHIFT)
#define PMC_IMPL_PART_VE_POWER_GATE_CONTROL_0_SRAM_RET_EN_RANGE                 1:1
#define PMC_IMPL_PART_VE_POWER_GATE_CONTROL_0_SRAM_RET_EN_WOFFSET                       0x0
#define PMC_IMPL_PART_VE_POWER_GATE_CONTROL_0_SRAM_RET_EN_DEFAULT                       _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_VE_POWER_GATE_CONTROL_0_SRAM_RET_EN_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_VE_POWER_GATE_CONTROL_0_SRAM_RET_EN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_VE_POWER_GATE_CONTROL_0_SRAM_RET_EN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_VE_POWER_GATE_CONTROL_0_SRAM_RET_EN_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_VE_POWER_GATE_CONTROL_0_SRAM_RET_EN_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_VE_POWER_GATE_CONTROL_0_SRAM_RET_EN_INIT_ENUM                     OFF
#define PMC_IMPL_PART_VE_POWER_GATE_CONTROL_0_SRAM_RET_EN_OFF                   _MK_ENUM_CONST(0)
#define PMC_IMPL_PART_VE_POWER_GATE_CONTROL_0_SRAM_RET_EN_ON                    _MK_ENUM_CONST(1)

#define PMC_IMPL_PART_VE_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SHIFT                       _MK_SHIFT_CONST(2)
#define PMC_IMPL_PART_VE_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_FIELD                       _MK_FIELD_CONST(0x1, PMC_IMPL_PART_VE_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SHIFT)
#define PMC_IMPL_PART_VE_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_RANGE                       2:2
#define PMC_IMPL_PART_VE_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_WOFFSET                     0x0
#define PMC_IMPL_PART_VE_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_DEFAULT                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_VE_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_VE_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_VE_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_VE_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_VE_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_VE_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_INIT_ENUM                   OFF
#define PMC_IMPL_PART_VE_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_OFF                 _MK_ENUM_CONST(0)
#define PMC_IMPL_PART_VE_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_ON                  _MK_ENUM_CONST(1)

#define PMC_IMPL_PART_VE_POWER_GATE_CONTROL_0_START_SHIFT                       _MK_SHIFT_CONST(8)
#define PMC_IMPL_PART_VE_POWER_GATE_CONTROL_0_START_FIELD                       _MK_FIELD_CONST(0x1, PMC_IMPL_PART_VE_POWER_GATE_CONTROL_0_START_SHIFT)
#define PMC_IMPL_PART_VE_POWER_GATE_CONTROL_0_START_RANGE                       8:8
#define PMC_IMPL_PART_VE_POWER_GATE_CONTROL_0_START_WOFFSET                     0x0
#define PMC_IMPL_PART_VE_POWER_GATE_CONTROL_0_START_DEFAULT                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_VE_POWER_GATE_CONTROL_0_START_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_VE_POWER_GATE_CONTROL_0_START_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_VE_POWER_GATE_CONTROL_0_START_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_VE_POWER_GATE_CONTROL_0_START_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_VE_POWER_GATE_CONTROL_0_START_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_VE_POWER_GATE_CONTROL_0_START_INIT_ENUM                   DONE
#define PMC_IMPL_PART_VE_POWER_GATE_CONTROL_0_START_DONE                        _MK_ENUM_CONST(0)
#define PMC_IMPL_PART_VE_POWER_GATE_CONTROL_0_START_PENDING                     _MK_ENUM_CONST(1)

#define PMC_IMPL_PART_VE_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SHIFT                 _MK_SHIFT_CONST(31)
#define PMC_IMPL_PART_VE_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_FIELD                 _MK_FIELD_CONST(0x1, PMC_IMPL_PART_VE_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SHIFT)
#define PMC_IMPL_PART_VE_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_RANGE                 31:31
#define PMC_IMPL_PART_VE_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_WOFFSET                       0x0
#define PMC_IMPL_PART_VE_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_DEFAULT                       _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_VE_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_VE_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_VE_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_VE_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_VE_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_VE_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_INIT_ENUM                     ENABLE
#define PMC_IMPL_PART_VE_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_DISABLE                       _MK_ENUM_CONST(0)
#define PMC_IMPL_PART_VE_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_ENABLE                        _MK_ENUM_CONST(1)


// Register PMC_IMPL_PART_VE_POWER_GATE_STATUS_0
#define PMC_IMPL_PART_VE_POWER_GATE_STATUS_0                    _MK_ADDR_CONST(0x290)
#define PMC_IMPL_PART_VE_POWER_GATE_STATUS_0_SECURE                     0x0
#define PMC_IMPL_PART_VE_POWER_GATE_STATUS_0_DUAL                       0x0
#define PMC_IMPL_PART_VE_POWER_GATE_STATUS_0_SCR                        PG_VE_SCR_0
#define PMC_IMPL_PART_VE_POWER_GATE_STATUS_0_WORD_COUNT                         0x1
#define PMC_IMPL_PART_VE_POWER_GATE_STATUS_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_VE_POWER_GATE_STATUS_0_RESET_MASK                         _MK_MASK_CONST(0x7)
#define PMC_IMPL_PART_VE_POWER_GATE_STATUS_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_VE_POWER_GATE_STATUS_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_VE_POWER_GATE_STATUS_0_READ_MASK                  _MK_MASK_CONST(0x7)
#define PMC_IMPL_PART_VE_POWER_GATE_STATUS_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_VE_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SHIFT                      _MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_VE_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_FIELD                      _MK_FIELD_CONST(0x1, PMC_IMPL_PART_VE_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SHIFT)
#define PMC_IMPL_PART_VE_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_RANGE                      0:0
#define PMC_IMPL_PART_VE_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_WOFFSET                    0x0
#define PMC_IMPL_PART_VE_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_DEFAULT                    _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_VE_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_VE_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_VE_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_VE_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_VE_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_VE_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_INIT_ENUM                  OFF
#define PMC_IMPL_PART_VE_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_OFF                        _MK_ENUM_CONST(0)
#define PMC_IMPL_PART_VE_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_ON                 _MK_ENUM_CONST(1)

#define PMC_IMPL_PART_VE_POWER_GATE_STATUS_0_SRAM_RET_STS_SHIFT                 _MK_SHIFT_CONST(1)
#define PMC_IMPL_PART_VE_POWER_GATE_STATUS_0_SRAM_RET_STS_FIELD                 _MK_FIELD_CONST(0x1, PMC_IMPL_PART_VE_POWER_GATE_STATUS_0_SRAM_RET_STS_SHIFT)
#define PMC_IMPL_PART_VE_POWER_GATE_STATUS_0_SRAM_RET_STS_RANGE                 1:1
#define PMC_IMPL_PART_VE_POWER_GATE_STATUS_0_SRAM_RET_STS_WOFFSET                       0x0
#define PMC_IMPL_PART_VE_POWER_GATE_STATUS_0_SRAM_RET_STS_DEFAULT                       _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_VE_POWER_GATE_STATUS_0_SRAM_RET_STS_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_VE_POWER_GATE_STATUS_0_SRAM_RET_STS_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_VE_POWER_GATE_STATUS_0_SRAM_RET_STS_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_VE_POWER_GATE_STATUS_0_SRAM_RET_STS_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_VE_POWER_GATE_STATUS_0_SRAM_RET_STS_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_VE_POWER_GATE_STATUS_0_SRAM_RET_STS_INIT_ENUM                     OFF
#define PMC_IMPL_PART_VE_POWER_GATE_STATUS_0_SRAM_RET_STS_OFF                   _MK_ENUM_CONST(0)
#define PMC_IMPL_PART_VE_POWER_GATE_STATUS_0_SRAM_RET_STS_ON                    _MK_ENUM_CONST(1)

#define PMC_IMPL_PART_VE_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SHIFT                       _MK_SHIFT_CONST(2)
#define PMC_IMPL_PART_VE_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_FIELD                       _MK_FIELD_CONST(0x1, PMC_IMPL_PART_VE_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SHIFT)
#define PMC_IMPL_PART_VE_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_RANGE                       2:2
#define PMC_IMPL_PART_VE_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_WOFFSET                     0x0
#define PMC_IMPL_PART_VE_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_DEFAULT                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_VE_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_VE_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_VE_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_VE_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_VE_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_VE_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_INIT_ENUM                   OFF
#define PMC_IMPL_PART_VE_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_OFF                 _MK_ENUM_CONST(0)
#define PMC_IMPL_PART_VE_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_ON                  _MK_ENUM_CONST(1)


// Register PMC_IMPL_PART_VE_CLAMP_CONTROL_0
#define PMC_IMPL_PART_VE_CLAMP_CONTROL_0                        _MK_ADDR_CONST(0x294)
#define PMC_IMPL_PART_VE_CLAMP_CONTROL_0_SECURE                         0x0
#define PMC_IMPL_PART_VE_CLAMP_CONTROL_0_DUAL                   0x0
#define PMC_IMPL_PART_VE_CLAMP_CONTROL_0_SCR                    PG_VE_SCR_0
#define PMC_IMPL_PART_VE_CLAMP_CONTROL_0_WORD_COUNT                     0x1
#define PMC_IMPL_PART_VE_CLAMP_CONTROL_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_VE_CLAMP_CONTROL_0_RESET_MASK                     _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_VE_CLAMP_CONTROL_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_VE_CLAMP_CONTROL_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_VE_CLAMP_CONTROL_0_READ_MASK                      _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_VE_CLAMP_CONTROL_0_WRITE_MASK                     _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_VE_CLAMP_CONTROL_0_CLAMP_SHIFT                    _MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_VE_CLAMP_CONTROL_0_CLAMP_FIELD                    _MK_FIELD_CONST(0x1, PMC_IMPL_PART_VE_CLAMP_CONTROL_0_CLAMP_SHIFT)
#define PMC_IMPL_PART_VE_CLAMP_CONTROL_0_CLAMP_RANGE                    0:0
#define PMC_IMPL_PART_VE_CLAMP_CONTROL_0_CLAMP_WOFFSET                  0x0
#define PMC_IMPL_PART_VE_CLAMP_CONTROL_0_CLAMP_DEFAULT                  _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_VE_CLAMP_CONTROL_0_CLAMP_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_VE_CLAMP_CONTROL_0_CLAMP_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_VE_CLAMP_CONTROL_0_CLAMP_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_VE_CLAMP_CONTROL_0_CLAMP_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_VE_CLAMP_CONTROL_0_CLAMP_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_VE_CLAMP_CONTROL_0_CLAMP_INIT_ENUM                        OFF
#define PMC_IMPL_PART_VE_CLAMP_CONTROL_0_CLAMP_OFF                      _MK_ENUM_CONST(0)
#define PMC_IMPL_PART_VE_CLAMP_CONTROL_0_CLAMP_ON                       _MK_ENUM_CONST(1)


// Register PMC_IMPL_PART_VIC_POWER_GATE_CONTROL_0
#define PMC_IMPL_PART_VIC_POWER_GATE_CONTROL_0                  _MK_ADDR_CONST(0x298)
#define PMC_IMPL_PART_VIC_POWER_GATE_CONTROL_0_SECURE                   0x0
#define PMC_IMPL_PART_VIC_POWER_GATE_CONTROL_0_DUAL                     0x0
#define PMC_IMPL_PART_VIC_POWER_GATE_CONTROL_0_SCR                      PG_VIC_SCR_0
#define PMC_IMPL_PART_VIC_POWER_GATE_CONTROL_0_WORD_COUNT                       0x1
#define PMC_IMPL_PART_VIC_POWER_GATE_CONTROL_0_RESET_VAL                        _MK_MASK_CONST(0x80000000)
#define PMC_IMPL_PART_VIC_POWER_GATE_CONTROL_0_RESET_MASK                       _MK_MASK_CONST(0x80000107)
#define PMC_IMPL_PART_VIC_POWER_GATE_CONTROL_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_VIC_POWER_GATE_CONTROL_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_VIC_POWER_GATE_CONTROL_0_READ_MASK                        _MK_MASK_CONST(0x80000107)
#define PMC_IMPL_PART_VIC_POWER_GATE_CONTROL_0_WRITE_MASK                       _MK_MASK_CONST(0x80000107)
#define PMC_IMPL_PART_VIC_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SHIFT                        _MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_VIC_POWER_GATE_CONTROL_0_LOGIC_SLEEP_FIELD                        _MK_FIELD_CONST(0x1, PMC_IMPL_PART_VIC_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SHIFT)
#define PMC_IMPL_PART_VIC_POWER_GATE_CONTROL_0_LOGIC_SLEEP_RANGE                        0:0
#define PMC_IMPL_PART_VIC_POWER_GATE_CONTROL_0_LOGIC_SLEEP_WOFFSET                      0x0
#define PMC_IMPL_PART_VIC_POWER_GATE_CONTROL_0_LOGIC_SLEEP_DEFAULT                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_VIC_POWER_GATE_CONTROL_0_LOGIC_SLEEP_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_VIC_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_VIC_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_VIC_POWER_GATE_CONTROL_0_LOGIC_SLEEP_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_VIC_POWER_GATE_CONTROL_0_LOGIC_SLEEP_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_VIC_POWER_GATE_CONTROL_0_LOGIC_SLEEP_INIT_ENUM                    OFF
#define PMC_IMPL_PART_VIC_POWER_GATE_CONTROL_0_LOGIC_SLEEP_OFF                  _MK_ENUM_CONST(0)
#define PMC_IMPL_PART_VIC_POWER_GATE_CONTROL_0_LOGIC_SLEEP_ON                   _MK_ENUM_CONST(1)

#define PMC_IMPL_PART_VIC_POWER_GATE_CONTROL_0_SRAM_RET_EN_SHIFT                        _MK_SHIFT_CONST(1)
#define PMC_IMPL_PART_VIC_POWER_GATE_CONTROL_0_SRAM_RET_EN_FIELD                        _MK_FIELD_CONST(0x1, PMC_IMPL_PART_VIC_POWER_GATE_CONTROL_0_SRAM_RET_EN_SHIFT)
#define PMC_IMPL_PART_VIC_POWER_GATE_CONTROL_0_SRAM_RET_EN_RANGE                        1:1
#define PMC_IMPL_PART_VIC_POWER_GATE_CONTROL_0_SRAM_RET_EN_WOFFSET                      0x0
#define PMC_IMPL_PART_VIC_POWER_GATE_CONTROL_0_SRAM_RET_EN_DEFAULT                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_VIC_POWER_GATE_CONTROL_0_SRAM_RET_EN_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_VIC_POWER_GATE_CONTROL_0_SRAM_RET_EN_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_VIC_POWER_GATE_CONTROL_0_SRAM_RET_EN_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_VIC_POWER_GATE_CONTROL_0_SRAM_RET_EN_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_VIC_POWER_GATE_CONTROL_0_SRAM_RET_EN_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_VIC_POWER_GATE_CONTROL_0_SRAM_RET_EN_INIT_ENUM                    OFF
#define PMC_IMPL_PART_VIC_POWER_GATE_CONTROL_0_SRAM_RET_EN_OFF                  _MK_ENUM_CONST(0)
#define PMC_IMPL_PART_VIC_POWER_GATE_CONTROL_0_SRAM_RET_EN_ON                   _MK_ENUM_CONST(1)

#define PMC_IMPL_PART_VIC_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SHIFT                      _MK_SHIFT_CONST(2)
#define PMC_IMPL_PART_VIC_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_FIELD                      _MK_FIELD_CONST(0x1, PMC_IMPL_PART_VIC_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SHIFT)
#define PMC_IMPL_PART_VIC_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_RANGE                      2:2
#define PMC_IMPL_PART_VIC_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_WOFFSET                    0x0
#define PMC_IMPL_PART_VIC_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_DEFAULT                    _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_VIC_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_VIC_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_VIC_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_VIC_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_VIC_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_VIC_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_INIT_ENUM                  OFF
#define PMC_IMPL_PART_VIC_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_OFF                        _MK_ENUM_CONST(0)
#define PMC_IMPL_PART_VIC_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_ON                 _MK_ENUM_CONST(1)

#define PMC_IMPL_PART_VIC_POWER_GATE_CONTROL_0_START_SHIFT                      _MK_SHIFT_CONST(8)
#define PMC_IMPL_PART_VIC_POWER_GATE_CONTROL_0_START_FIELD                      _MK_FIELD_CONST(0x1, PMC_IMPL_PART_VIC_POWER_GATE_CONTROL_0_START_SHIFT)
#define PMC_IMPL_PART_VIC_POWER_GATE_CONTROL_0_START_RANGE                      8:8
#define PMC_IMPL_PART_VIC_POWER_GATE_CONTROL_0_START_WOFFSET                    0x0
#define PMC_IMPL_PART_VIC_POWER_GATE_CONTROL_0_START_DEFAULT                    _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_VIC_POWER_GATE_CONTROL_0_START_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_VIC_POWER_GATE_CONTROL_0_START_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_VIC_POWER_GATE_CONTROL_0_START_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_VIC_POWER_GATE_CONTROL_0_START_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_VIC_POWER_GATE_CONTROL_0_START_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_VIC_POWER_GATE_CONTROL_0_START_INIT_ENUM                  DONE
#define PMC_IMPL_PART_VIC_POWER_GATE_CONTROL_0_START_DONE                       _MK_ENUM_CONST(0)
#define PMC_IMPL_PART_VIC_POWER_GATE_CONTROL_0_START_PENDING                    _MK_ENUM_CONST(1)

#define PMC_IMPL_PART_VIC_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SHIFT                        _MK_SHIFT_CONST(31)
#define PMC_IMPL_PART_VIC_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_FIELD                        _MK_FIELD_CONST(0x1, PMC_IMPL_PART_VIC_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SHIFT)
#define PMC_IMPL_PART_VIC_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_RANGE                        31:31
#define PMC_IMPL_PART_VIC_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_WOFFSET                      0x0
#define PMC_IMPL_PART_VIC_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_DEFAULT                      _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_VIC_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_VIC_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_VIC_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_VIC_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_VIC_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_VIC_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_INIT_ENUM                    ENABLE
#define PMC_IMPL_PART_VIC_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_DISABLE                      _MK_ENUM_CONST(0)
#define PMC_IMPL_PART_VIC_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_ENABLE                       _MK_ENUM_CONST(1)


// Register PMC_IMPL_PART_VIC_POWER_GATE_STATUS_0
#define PMC_IMPL_PART_VIC_POWER_GATE_STATUS_0                   _MK_ADDR_CONST(0x29c)
#define PMC_IMPL_PART_VIC_POWER_GATE_STATUS_0_SECURE                    0x0
#define PMC_IMPL_PART_VIC_POWER_GATE_STATUS_0_DUAL                      0x0
#define PMC_IMPL_PART_VIC_POWER_GATE_STATUS_0_SCR                       PG_VIC_SCR_0
#define PMC_IMPL_PART_VIC_POWER_GATE_STATUS_0_WORD_COUNT                        0x1
#define PMC_IMPL_PART_VIC_POWER_GATE_STATUS_0_RESET_VAL                         _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_VIC_POWER_GATE_STATUS_0_RESET_MASK                        _MK_MASK_CONST(0x7)
#define PMC_IMPL_PART_VIC_POWER_GATE_STATUS_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_VIC_POWER_GATE_STATUS_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_VIC_POWER_GATE_STATUS_0_READ_MASK                         _MK_MASK_CONST(0x7)
#define PMC_IMPL_PART_VIC_POWER_GATE_STATUS_0_WRITE_MASK                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_VIC_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SHIFT                     _MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_VIC_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_FIELD                     _MK_FIELD_CONST(0x1, PMC_IMPL_PART_VIC_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SHIFT)
#define PMC_IMPL_PART_VIC_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_RANGE                     0:0
#define PMC_IMPL_PART_VIC_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_WOFFSET                   0x0
#define PMC_IMPL_PART_VIC_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_DEFAULT                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_VIC_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_VIC_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_VIC_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_VIC_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_VIC_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_VIC_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_INIT_ENUM                 OFF
#define PMC_IMPL_PART_VIC_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_OFF                       _MK_ENUM_CONST(0)
#define PMC_IMPL_PART_VIC_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_ON                        _MK_ENUM_CONST(1)

#define PMC_IMPL_PART_VIC_POWER_GATE_STATUS_0_SRAM_RET_STS_SHIFT                        _MK_SHIFT_CONST(1)
#define PMC_IMPL_PART_VIC_POWER_GATE_STATUS_0_SRAM_RET_STS_FIELD                        _MK_FIELD_CONST(0x1, PMC_IMPL_PART_VIC_POWER_GATE_STATUS_0_SRAM_RET_STS_SHIFT)
#define PMC_IMPL_PART_VIC_POWER_GATE_STATUS_0_SRAM_RET_STS_RANGE                        1:1
#define PMC_IMPL_PART_VIC_POWER_GATE_STATUS_0_SRAM_RET_STS_WOFFSET                      0x0
#define PMC_IMPL_PART_VIC_POWER_GATE_STATUS_0_SRAM_RET_STS_DEFAULT                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_VIC_POWER_GATE_STATUS_0_SRAM_RET_STS_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_VIC_POWER_GATE_STATUS_0_SRAM_RET_STS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_VIC_POWER_GATE_STATUS_0_SRAM_RET_STS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_VIC_POWER_GATE_STATUS_0_SRAM_RET_STS_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_VIC_POWER_GATE_STATUS_0_SRAM_RET_STS_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_VIC_POWER_GATE_STATUS_0_SRAM_RET_STS_INIT_ENUM                    OFF
#define PMC_IMPL_PART_VIC_POWER_GATE_STATUS_0_SRAM_RET_STS_OFF                  _MK_ENUM_CONST(0)
#define PMC_IMPL_PART_VIC_POWER_GATE_STATUS_0_SRAM_RET_STS_ON                   _MK_ENUM_CONST(1)

#define PMC_IMPL_PART_VIC_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SHIFT                      _MK_SHIFT_CONST(2)
#define PMC_IMPL_PART_VIC_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_FIELD                      _MK_FIELD_CONST(0x1, PMC_IMPL_PART_VIC_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SHIFT)
#define PMC_IMPL_PART_VIC_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_RANGE                      2:2
#define PMC_IMPL_PART_VIC_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_WOFFSET                    0x0
#define PMC_IMPL_PART_VIC_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_DEFAULT                    _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_VIC_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_VIC_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_VIC_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_VIC_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_VIC_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_VIC_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_INIT_ENUM                  OFF
#define PMC_IMPL_PART_VIC_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_OFF                        _MK_ENUM_CONST(0)
#define PMC_IMPL_PART_VIC_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_ON                 _MK_ENUM_CONST(1)


// Register PMC_IMPL_PART_VIC_CLAMP_CONTROL_0
#define PMC_IMPL_PART_VIC_CLAMP_CONTROL_0                       _MK_ADDR_CONST(0x2a0)
#define PMC_IMPL_PART_VIC_CLAMP_CONTROL_0_SECURE                        0x0
#define PMC_IMPL_PART_VIC_CLAMP_CONTROL_0_DUAL                  0x0
#define PMC_IMPL_PART_VIC_CLAMP_CONTROL_0_SCR                   PG_VIC_SCR_0
#define PMC_IMPL_PART_VIC_CLAMP_CONTROL_0_WORD_COUNT                    0x1
#define PMC_IMPL_PART_VIC_CLAMP_CONTROL_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_VIC_CLAMP_CONTROL_0_RESET_MASK                    _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_VIC_CLAMP_CONTROL_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_VIC_CLAMP_CONTROL_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_VIC_CLAMP_CONTROL_0_READ_MASK                     _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_VIC_CLAMP_CONTROL_0_WRITE_MASK                    _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_VIC_CLAMP_CONTROL_0_CLAMP_SHIFT                   _MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_VIC_CLAMP_CONTROL_0_CLAMP_FIELD                   _MK_FIELD_CONST(0x1, PMC_IMPL_PART_VIC_CLAMP_CONTROL_0_CLAMP_SHIFT)
#define PMC_IMPL_PART_VIC_CLAMP_CONTROL_0_CLAMP_RANGE                   0:0
#define PMC_IMPL_PART_VIC_CLAMP_CONTROL_0_CLAMP_WOFFSET                 0x0
#define PMC_IMPL_PART_VIC_CLAMP_CONTROL_0_CLAMP_DEFAULT                 _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_VIC_CLAMP_CONTROL_0_CLAMP_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_VIC_CLAMP_CONTROL_0_CLAMP_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_VIC_CLAMP_CONTROL_0_CLAMP_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_VIC_CLAMP_CONTROL_0_CLAMP_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_VIC_CLAMP_CONTROL_0_CLAMP_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_VIC_CLAMP_CONTROL_0_CLAMP_INIT_ENUM                       OFF
#define PMC_IMPL_PART_VIC_CLAMP_CONTROL_0_CLAMP_OFF                     _MK_ENUM_CONST(0)
#define PMC_IMPL_PART_VIC_CLAMP_CONTROL_0_CLAMP_ON                      _MK_ENUM_CONST(1)


// Register PMC_IMPL_PART_XUSBA_POWER_GATE_CONTROL_0
#define PMC_IMPL_PART_XUSBA_POWER_GATE_CONTROL_0                        _MK_ADDR_CONST(0x2a4)
#define PMC_IMPL_PART_XUSBA_POWER_GATE_CONTROL_0_SECURE                         0x0
#define PMC_IMPL_PART_XUSBA_POWER_GATE_CONTROL_0_DUAL                   0x0
#define PMC_IMPL_PART_XUSBA_POWER_GATE_CONTROL_0_SCR                    PG_XUSBA_SCR_0
#define PMC_IMPL_PART_XUSBA_POWER_GATE_CONTROL_0_WORD_COUNT                     0x1
#define PMC_IMPL_PART_XUSBA_POWER_GATE_CONTROL_0_RESET_VAL                      _MK_MASK_CONST(0x80000000)
#define PMC_IMPL_PART_XUSBA_POWER_GATE_CONTROL_0_RESET_MASK                     _MK_MASK_CONST(0x80000107)
#define PMC_IMPL_PART_XUSBA_POWER_GATE_CONTROL_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_XUSBA_POWER_GATE_CONTROL_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_XUSBA_POWER_GATE_CONTROL_0_READ_MASK                      _MK_MASK_CONST(0x80000107)
#define PMC_IMPL_PART_XUSBA_POWER_GATE_CONTROL_0_WRITE_MASK                     _MK_MASK_CONST(0x80000107)
#define PMC_IMPL_PART_XUSBA_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SHIFT                      _MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_XUSBA_POWER_GATE_CONTROL_0_LOGIC_SLEEP_FIELD                      _MK_FIELD_CONST(0x1, PMC_IMPL_PART_XUSBA_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SHIFT)
#define PMC_IMPL_PART_XUSBA_POWER_GATE_CONTROL_0_LOGIC_SLEEP_RANGE                      0:0
#define PMC_IMPL_PART_XUSBA_POWER_GATE_CONTROL_0_LOGIC_SLEEP_WOFFSET                    0x0
#define PMC_IMPL_PART_XUSBA_POWER_GATE_CONTROL_0_LOGIC_SLEEP_DEFAULT                    _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_XUSBA_POWER_GATE_CONTROL_0_LOGIC_SLEEP_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_XUSBA_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_XUSBA_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_XUSBA_POWER_GATE_CONTROL_0_LOGIC_SLEEP_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_XUSBA_POWER_GATE_CONTROL_0_LOGIC_SLEEP_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_XUSBA_POWER_GATE_CONTROL_0_LOGIC_SLEEP_INIT_ENUM                  OFF
#define PMC_IMPL_PART_XUSBA_POWER_GATE_CONTROL_0_LOGIC_SLEEP_OFF                        _MK_ENUM_CONST(0)
#define PMC_IMPL_PART_XUSBA_POWER_GATE_CONTROL_0_LOGIC_SLEEP_ON                 _MK_ENUM_CONST(1)

#define PMC_IMPL_PART_XUSBA_POWER_GATE_CONTROL_0_SRAM_RET_EN_SHIFT                      _MK_SHIFT_CONST(1)
#define PMC_IMPL_PART_XUSBA_POWER_GATE_CONTROL_0_SRAM_RET_EN_FIELD                      _MK_FIELD_CONST(0x1, PMC_IMPL_PART_XUSBA_POWER_GATE_CONTROL_0_SRAM_RET_EN_SHIFT)
#define PMC_IMPL_PART_XUSBA_POWER_GATE_CONTROL_0_SRAM_RET_EN_RANGE                      1:1
#define PMC_IMPL_PART_XUSBA_POWER_GATE_CONTROL_0_SRAM_RET_EN_WOFFSET                    0x0
#define PMC_IMPL_PART_XUSBA_POWER_GATE_CONTROL_0_SRAM_RET_EN_DEFAULT                    _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_XUSBA_POWER_GATE_CONTROL_0_SRAM_RET_EN_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_XUSBA_POWER_GATE_CONTROL_0_SRAM_RET_EN_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_XUSBA_POWER_GATE_CONTROL_0_SRAM_RET_EN_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_XUSBA_POWER_GATE_CONTROL_0_SRAM_RET_EN_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_XUSBA_POWER_GATE_CONTROL_0_SRAM_RET_EN_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_XUSBA_POWER_GATE_CONTROL_0_SRAM_RET_EN_INIT_ENUM                  OFF
#define PMC_IMPL_PART_XUSBA_POWER_GATE_CONTROL_0_SRAM_RET_EN_OFF                        _MK_ENUM_CONST(0)
#define PMC_IMPL_PART_XUSBA_POWER_GATE_CONTROL_0_SRAM_RET_EN_ON                 _MK_ENUM_CONST(1)

#define PMC_IMPL_PART_XUSBA_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SHIFT                    _MK_SHIFT_CONST(2)
#define PMC_IMPL_PART_XUSBA_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_FIELD                    _MK_FIELD_CONST(0x1, PMC_IMPL_PART_XUSBA_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SHIFT)
#define PMC_IMPL_PART_XUSBA_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_RANGE                    2:2
#define PMC_IMPL_PART_XUSBA_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_WOFFSET                  0x0
#define PMC_IMPL_PART_XUSBA_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_DEFAULT                  _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_XUSBA_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_XUSBA_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_XUSBA_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_XUSBA_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_XUSBA_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_XUSBA_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_INIT_ENUM                        OFF
#define PMC_IMPL_PART_XUSBA_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_OFF                      _MK_ENUM_CONST(0)
#define PMC_IMPL_PART_XUSBA_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_ON                       _MK_ENUM_CONST(1)

#define PMC_IMPL_PART_XUSBA_POWER_GATE_CONTROL_0_START_SHIFT                    _MK_SHIFT_CONST(8)
#define PMC_IMPL_PART_XUSBA_POWER_GATE_CONTROL_0_START_FIELD                    _MK_FIELD_CONST(0x1, PMC_IMPL_PART_XUSBA_POWER_GATE_CONTROL_0_START_SHIFT)
#define PMC_IMPL_PART_XUSBA_POWER_GATE_CONTROL_0_START_RANGE                    8:8
#define PMC_IMPL_PART_XUSBA_POWER_GATE_CONTROL_0_START_WOFFSET                  0x0
#define PMC_IMPL_PART_XUSBA_POWER_GATE_CONTROL_0_START_DEFAULT                  _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_XUSBA_POWER_GATE_CONTROL_0_START_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_XUSBA_POWER_GATE_CONTROL_0_START_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_XUSBA_POWER_GATE_CONTROL_0_START_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_XUSBA_POWER_GATE_CONTROL_0_START_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_XUSBA_POWER_GATE_CONTROL_0_START_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_XUSBA_POWER_GATE_CONTROL_0_START_INIT_ENUM                        DONE
#define PMC_IMPL_PART_XUSBA_POWER_GATE_CONTROL_0_START_DONE                     _MK_ENUM_CONST(0)
#define PMC_IMPL_PART_XUSBA_POWER_GATE_CONTROL_0_START_PENDING                  _MK_ENUM_CONST(1)

#define PMC_IMPL_PART_XUSBA_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SHIFT                      _MK_SHIFT_CONST(31)
#define PMC_IMPL_PART_XUSBA_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_FIELD                      _MK_FIELD_CONST(0x1, PMC_IMPL_PART_XUSBA_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SHIFT)
#define PMC_IMPL_PART_XUSBA_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_RANGE                      31:31
#define PMC_IMPL_PART_XUSBA_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_WOFFSET                    0x0
#define PMC_IMPL_PART_XUSBA_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_DEFAULT                    _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_XUSBA_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_XUSBA_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_XUSBA_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_XUSBA_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_XUSBA_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_XUSBA_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_INIT_ENUM                  ENABLE
#define PMC_IMPL_PART_XUSBA_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_DISABLE                    _MK_ENUM_CONST(0)
#define PMC_IMPL_PART_XUSBA_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_ENABLE                     _MK_ENUM_CONST(1)


// Register PMC_IMPL_PART_XUSBA_POWER_GATE_STATUS_0
#define PMC_IMPL_PART_XUSBA_POWER_GATE_STATUS_0                 _MK_ADDR_CONST(0x2a8)
#define PMC_IMPL_PART_XUSBA_POWER_GATE_STATUS_0_SECURE                  0x0
#define PMC_IMPL_PART_XUSBA_POWER_GATE_STATUS_0_DUAL                    0x0
#define PMC_IMPL_PART_XUSBA_POWER_GATE_STATUS_0_SCR                     PG_XUSBA_SCR_0
#define PMC_IMPL_PART_XUSBA_POWER_GATE_STATUS_0_WORD_COUNT                      0x1
#define PMC_IMPL_PART_XUSBA_POWER_GATE_STATUS_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_XUSBA_POWER_GATE_STATUS_0_RESET_MASK                      _MK_MASK_CONST(0x7)
#define PMC_IMPL_PART_XUSBA_POWER_GATE_STATUS_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_XUSBA_POWER_GATE_STATUS_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_XUSBA_POWER_GATE_STATUS_0_READ_MASK                       _MK_MASK_CONST(0x7)
#define PMC_IMPL_PART_XUSBA_POWER_GATE_STATUS_0_WRITE_MASK                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_XUSBA_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SHIFT                   _MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_XUSBA_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_FIELD                   _MK_FIELD_CONST(0x1, PMC_IMPL_PART_XUSBA_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SHIFT)
#define PMC_IMPL_PART_XUSBA_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_RANGE                   0:0
#define PMC_IMPL_PART_XUSBA_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_WOFFSET                 0x0
#define PMC_IMPL_PART_XUSBA_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_DEFAULT                 _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_XUSBA_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_XUSBA_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_XUSBA_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_XUSBA_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_XUSBA_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_XUSBA_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_INIT_ENUM                       OFF
#define PMC_IMPL_PART_XUSBA_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_OFF                     _MK_ENUM_CONST(0)
#define PMC_IMPL_PART_XUSBA_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_ON                      _MK_ENUM_CONST(1)

#define PMC_IMPL_PART_XUSBA_POWER_GATE_STATUS_0_SRAM_RET_STS_SHIFT                      _MK_SHIFT_CONST(1)
#define PMC_IMPL_PART_XUSBA_POWER_GATE_STATUS_0_SRAM_RET_STS_FIELD                      _MK_FIELD_CONST(0x1, PMC_IMPL_PART_XUSBA_POWER_GATE_STATUS_0_SRAM_RET_STS_SHIFT)
#define PMC_IMPL_PART_XUSBA_POWER_GATE_STATUS_0_SRAM_RET_STS_RANGE                      1:1
#define PMC_IMPL_PART_XUSBA_POWER_GATE_STATUS_0_SRAM_RET_STS_WOFFSET                    0x0
#define PMC_IMPL_PART_XUSBA_POWER_GATE_STATUS_0_SRAM_RET_STS_DEFAULT                    _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_XUSBA_POWER_GATE_STATUS_0_SRAM_RET_STS_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_XUSBA_POWER_GATE_STATUS_0_SRAM_RET_STS_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_XUSBA_POWER_GATE_STATUS_0_SRAM_RET_STS_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_XUSBA_POWER_GATE_STATUS_0_SRAM_RET_STS_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_XUSBA_POWER_GATE_STATUS_0_SRAM_RET_STS_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_XUSBA_POWER_GATE_STATUS_0_SRAM_RET_STS_INIT_ENUM                  OFF
#define PMC_IMPL_PART_XUSBA_POWER_GATE_STATUS_0_SRAM_RET_STS_OFF                        _MK_ENUM_CONST(0)
#define PMC_IMPL_PART_XUSBA_POWER_GATE_STATUS_0_SRAM_RET_STS_ON                 _MK_ENUM_CONST(1)

#define PMC_IMPL_PART_XUSBA_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SHIFT                    _MK_SHIFT_CONST(2)
#define PMC_IMPL_PART_XUSBA_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_FIELD                    _MK_FIELD_CONST(0x1, PMC_IMPL_PART_XUSBA_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SHIFT)
#define PMC_IMPL_PART_XUSBA_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_RANGE                    2:2
#define PMC_IMPL_PART_XUSBA_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_WOFFSET                  0x0
#define PMC_IMPL_PART_XUSBA_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_DEFAULT                  _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_XUSBA_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_XUSBA_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_XUSBA_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_XUSBA_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_XUSBA_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_XUSBA_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_INIT_ENUM                        OFF
#define PMC_IMPL_PART_XUSBA_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_OFF                      _MK_ENUM_CONST(0)
#define PMC_IMPL_PART_XUSBA_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_ON                       _MK_ENUM_CONST(1)


// Register PMC_IMPL_PART_XUSBA_CLAMP_CONTROL_0
#define PMC_IMPL_PART_XUSBA_CLAMP_CONTROL_0                     _MK_ADDR_CONST(0x2ac)
#define PMC_IMPL_PART_XUSBA_CLAMP_CONTROL_0_SECURE                      0x0
#define PMC_IMPL_PART_XUSBA_CLAMP_CONTROL_0_DUAL                        0x0
#define PMC_IMPL_PART_XUSBA_CLAMP_CONTROL_0_SCR                         PG_XUSBA_SCR_0
#define PMC_IMPL_PART_XUSBA_CLAMP_CONTROL_0_WORD_COUNT                  0x1
#define PMC_IMPL_PART_XUSBA_CLAMP_CONTROL_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_XUSBA_CLAMP_CONTROL_0_RESET_MASK                  _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_XUSBA_CLAMP_CONTROL_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_XUSBA_CLAMP_CONTROL_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_XUSBA_CLAMP_CONTROL_0_READ_MASK                   _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_XUSBA_CLAMP_CONTROL_0_WRITE_MASK                  _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_XUSBA_CLAMP_CONTROL_0_CLAMP_SHIFT                 _MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_XUSBA_CLAMP_CONTROL_0_CLAMP_FIELD                 _MK_FIELD_CONST(0x1, PMC_IMPL_PART_XUSBA_CLAMP_CONTROL_0_CLAMP_SHIFT)
#define PMC_IMPL_PART_XUSBA_CLAMP_CONTROL_0_CLAMP_RANGE                 0:0
#define PMC_IMPL_PART_XUSBA_CLAMP_CONTROL_0_CLAMP_WOFFSET                       0x0
#define PMC_IMPL_PART_XUSBA_CLAMP_CONTROL_0_CLAMP_DEFAULT                       _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_XUSBA_CLAMP_CONTROL_0_CLAMP_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_XUSBA_CLAMP_CONTROL_0_CLAMP_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_XUSBA_CLAMP_CONTROL_0_CLAMP_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_XUSBA_CLAMP_CONTROL_0_CLAMP_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_XUSBA_CLAMP_CONTROL_0_CLAMP_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_XUSBA_CLAMP_CONTROL_0_CLAMP_INIT_ENUM                     OFF
#define PMC_IMPL_PART_XUSBA_CLAMP_CONTROL_0_CLAMP_OFF                   _MK_ENUM_CONST(0)
#define PMC_IMPL_PART_XUSBA_CLAMP_CONTROL_0_CLAMP_ON                    _MK_ENUM_CONST(1)


// Register PMC_IMPL_PART_XUSBB_POWER_GATE_CONTROL_0
#define PMC_IMPL_PART_XUSBB_POWER_GATE_CONTROL_0                        _MK_ADDR_CONST(0x2b0)
#define PMC_IMPL_PART_XUSBB_POWER_GATE_CONTROL_0_SECURE                         0x0
#define PMC_IMPL_PART_XUSBB_POWER_GATE_CONTROL_0_DUAL                   0x0
#define PMC_IMPL_PART_XUSBB_POWER_GATE_CONTROL_0_SCR                    PG_XUSBB_SCR_0
#define PMC_IMPL_PART_XUSBB_POWER_GATE_CONTROL_0_WORD_COUNT                     0x1
#define PMC_IMPL_PART_XUSBB_POWER_GATE_CONTROL_0_RESET_VAL                      _MK_MASK_CONST(0x80000000)
#define PMC_IMPL_PART_XUSBB_POWER_GATE_CONTROL_0_RESET_MASK                     _MK_MASK_CONST(0x80000107)
#define PMC_IMPL_PART_XUSBB_POWER_GATE_CONTROL_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_XUSBB_POWER_GATE_CONTROL_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_XUSBB_POWER_GATE_CONTROL_0_READ_MASK                      _MK_MASK_CONST(0x80000107)
#define PMC_IMPL_PART_XUSBB_POWER_GATE_CONTROL_0_WRITE_MASK                     _MK_MASK_CONST(0x80000107)
#define PMC_IMPL_PART_XUSBB_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SHIFT                      _MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_XUSBB_POWER_GATE_CONTROL_0_LOGIC_SLEEP_FIELD                      _MK_FIELD_CONST(0x1, PMC_IMPL_PART_XUSBB_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SHIFT)
#define PMC_IMPL_PART_XUSBB_POWER_GATE_CONTROL_0_LOGIC_SLEEP_RANGE                      0:0
#define PMC_IMPL_PART_XUSBB_POWER_GATE_CONTROL_0_LOGIC_SLEEP_WOFFSET                    0x0
#define PMC_IMPL_PART_XUSBB_POWER_GATE_CONTROL_0_LOGIC_SLEEP_DEFAULT                    _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_XUSBB_POWER_GATE_CONTROL_0_LOGIC_SLEEP_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_XUSBB_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_XUSBB_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_XUSBB_POWER_GATE_CONTROL_0_LOGIC_SLEEP_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_XUSBB_POWER_GATE_CONTROL_0_LOGIC_SLEEP_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_XUSBB_POWER_GATE_CONTROL_0_LOGIC_SLEEP_INIT_ENUM                  OFF
#define PMC_IMPL_PART_XUSBB_POWER_GATE_CONTROL_0_LOGIC_SLEEP_OFF                        _MK_ENUM_CONST(0)
#define PMC_IMPL_PART_XUSBB_POWER_GATE_CONTROL_0_LOGIC_SLEEP_ON                 _MK_ENUM_CONST(1)

#define PMC_IMPL_PART_XUSBB_POWER_GATE_CONTROL_0_SRAM_RET_EN_SHIFT                      _MK_SHIFT_CONST(1)
#define PMC_IMPL_PART_XUSBB_POWER_GATE_CONTROL_0_SRAM_RET_EN_FIELD                      _MK_FIELD_CONST(0x1, PMC_IMPL_PART_XUSBB_POWER_GATE_CONTROL_0_SRAM_RET_EN_SHIFT)
#define PMC_IMPL_PART_XUSBB_POWER_GATE_CONTROL_0_SRAM_RET_EN_RANGE                      1:1
#define PMC_IMPL_PART_XUSBB_POWER_GATE_CONTROL_0_SRAM_RET_EN_WOFFSET                    0x0
#define PMC_IMPL_PART_XUSBB_POWER_GATE_CONTROL_0_SRAM_RET_EN_DEFAULT                    _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_XUSBB_POWER_GATE_CONTROL_0_SRAM_RET_EN_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_XUSBB_POWER_GATE_CONTROL_0_SRAM_RET_EN_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_XUSBB_POWER_GATE_CONTROL_0_SRAM_RET_EN_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_XUSBB_POWER_GATE_CONTROL_0_SRAM_RET_EN_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_XUSBB_POWER_GATE_CONTROL_0_SRAM_RET_EN_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_XUSBB_POWER_GATE_CONTROL_0_SRAM_RET_EN_INIT_ENUM                  OFF
#define PMC_IMPL_PART_XUSBB_POWER_GATE_CONTROL_0_SRAM_RET_EN_OFF                        _MK_ENUM_CONST(0)
#define PMC_IMPL_PART_XUSBB_POWER_GATE_CONTROL_0_SRAM_RET_EN_ON                 _MK_ENUM_CONST(1)

#define PMC_IMPL_PART_XUSBB_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SHIFT                    _MK_SHIFT_CONST(2)
#define PMC_IMPL_PART_XUSBB_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_FIELD                    _MK_FIELD_CONST(0x1, PMC_IMPL_PART_XUSBB_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SHIFT)
#define PMC_IMPL_PART_XUSBB_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_RANGE                    2:2
#define PMC_IMPL_PART_XUSBB_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_WOFFSET                  0x0
#define PMC_IMPL_PART_XUSBB_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_DEFAULT                  _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_XUSBB_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_XUSBB_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_XUSBB_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_XUSBB_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_XUSBB_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_XUSBB_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_INIT_ENUM                        OFF
#define PMC_IMPL_PART_XUSBB_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_OFF                      _MK_ENUM_CONST(0)
#define PMC_IMPL_PART_XUSBB_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_ON                       _MK_ENUM_CONST(1)

#define PMC_IMPL_PART_XUSBB_POWER_GATE_CONTROL_0_START_SHIFT                    _MK_SHIFT_CONST(8)
#define PMC_IMPL_PART_XUSBB_POWER_GATE_CONTROL_0_START_FIELD                    _MK_FIELD_CONST(0x1, PMC_IMPL_PART_XUSBB_POWER_GATE_CONTROL_0_START_SHIFT)
#define PMC_IMPL_PART_XUSBB_POWER_GATE_CONTROL_0_START_RANGE                    8:8
#define PMC_IMPL_PART_XUSBB_POWER_GATE_CONTROL_0_START_WOFFSET                  0x0
#define PMC_IMPL_PART_XUSBB_POWER_GATE_CONTROL_0_START_DEFAULT                  _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_XUSBB_POWER_GATE_CONTROL_0_START_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_XUSBB_POWER_GATE_CONTROL_0_START_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_XUSBB_POWER_GATE_CONTROL_0_START_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_XUSBB_POWER_GATE_CONTROL_0_START_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_XUSBB_POWER_GATE_CONTROL_0_START_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_XUSBB_POWER_GATE_CONTROL_0_START_INIT_ENUM                        DONE
#define PMC_IMPL_PART_XUSBB_POWER_GATE_CONTROL_0_START_DONE                     _MK_ENUM_CONST(0)
#define PMC_IMPL_PART_XUSBB_POWER_GATE_CONTROL_0_START_PENDING                  _MK_ENUM_CONST(1)

#define PMC_IMPL_PART_XUSBB_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SHIFT                      _MK_SHIFT_CONST(31)
#define PMC_IMPL_PART_XUSBB_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_FIELD                      _MK_FIELD_CONST(0x1, PMC_IMPL_PART_XUSBB_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SHIFT)
#define PMC_IMPL_PART_XUSBB_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_RANGE                      31:31
#define PMC_IMPL_PART_XUSBB_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_WOFFSET                    0x0
#define PMC_IMPL_PART_XUSBB_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_DEFAULT                    _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_XUSBB_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_XUSBB_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_XUSBB_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_XUSBB_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_XUSBB_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_XUSBB_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_INIT_ENUM                  ENABLE
#define PMC_IMPL_PART_XUSBB_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_DISABLE                    _MK_ENUM_CONST(0)
#define PMC_IMPL_PART_XUSBB_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_ENABLE                     _MK_ENUM_CONST(1)


// Register PMC_IMPL_PART_XUSBB_POWER_GATE_STATUS_0
#define PMC_IMPL_PART_XUSBB_POWER_GATE_STATUS_0                 _MK_ADDR_CONST(0x2b4)
#define PMC_IMPL_PART_XUSBB_POWER_GATE_STATUS_0_SECURE                  0x0
#define PMC_IMPL_PART_XUSBB_POWER_GATE_STATUS_0_DUAL                    0x0
#define PMC_IMPL_PART_XUSBB_POWER_GATE_STATUS_0_SCR                     PG_XUSBB_SCR_0
#define PMC_IMPL_PART_XUSBB_POWER_GATE_STATUS_0_WORD_COUNT                      0x1
#define PMC_IMPL_PART_XUSBB_POWER_GATE_STATUS_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_XUSBB_POWER_GATE_STATUS_0_RESET_MASK                      _MK_MASK_CONST(0x7)
#define PMC_IMPL_PART_XUSBB_POWER_GATE_STATUS_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_XUSBB_POWER_GATE_STATUS_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_XUSBB_POWER_GATE_STATUS_0_READ_MASK                       _MK_MASK_CONST(0x7)
#define PMC_IMPL_PART_XUSBB_POWER_GATE_STATUS_0_WRITE_MASK                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_XUSBB_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SHIFT                   _MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_XUSBB_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_FIELD                   _MK_FIELD_CONST(0x1, PMC_IMPL_PART_XUSBB_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SHIFT)
#define PMC_IMPL_PART_XUSBB_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_RANGE                   0:0
#define PMC_IMPL_PART_XUSBB_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_WOFFSET                 0x0
#define PMC_IMPL_PART_XUSBB_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_DEFAULT                 _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_XUSBB_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_XUSBB_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_XUSBB_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_XUSBB_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_XUSBB_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_XUSBB_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_INIT_ENUM                       OFF
#define PMC_IMPL_PART_XUSBB_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_OFF                     _MK_ENUM_CONST(0)
#define PMC_IMPL_PART_XUSBB_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_ON                      _MK_ENUM_CONST(1)

#define PMC_IMPL_PART_XUSBB_POWER_GATE_STATUS_0_SRAM_RET_STS_SHIFT                      _MK_SHIFT_CONST(1)
#define PMC_IMPL_PART_XUSBB_POWER_GATE_STATUS_0_SRAM_RET_STS_FIELD                      _MK_FIELD_CONST(0x1, PMC_IMPL_PART_XUSBB_POWER_GATE_STATUS_0_SRAM_RET_STS_SHIFT)
#define PMC_IMPL_PART_XUSBB_POWER_GATE_STATUS_0_SRAM_RET_STS_RANGE                      1:1
#define PMC_IMPL_PART_XUSBB_POWER_GATE_STATUS_0_SRAM_RET_STS_WOFFSET                    0x0
#define PMC_IMPL_PART_XUSBB_POWER_GATE_STATUS_0_SRAM_RET_STS_DEFAULT                    _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_XUSBB_POWER_GATE_STATUS_0_SRAM_RET_STS_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_XUSBB_POWER_GATE_STATUS_0_SRAM_RET_STS_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_XUSBB_POWER_GATE_STATUS_0_SRAM_RET_STS_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_XUSBB_POWER_GATE_STATUS_0_SRAM_RET_STS_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_XUSBB_POWER_GATE_STATUS_0_SRAM_RET_STS_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_XUSBB_POWER_GATE_STATUS_0_SRAM_RET_STS_INIT_ENUM                  OFF
#define PMC_IMPL_PART_XUSBB_POWER_GATE_STATUS_0_SRAM_RET_STS_OFF                        _MK_ENUM_CONST(0)
#define PMC_IMPL_PART_XUSBB_POWER_GATE_STATUS_0_SRAM_RET_STS_ON                 _MK_ENUM_CONST(1)

#define PMC_IMPL_PART_XUSBB_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SHIFT                    _MK_SHIFT_CONST(2)
#define PMC_IMPL_PART_XUSBB_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_FIELD                    _MK_FIELD_CONST(0x1, PMC_IMPL_PART_XUSBB_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SHIFT)
#define PMC_IMPL_PART_XUSBB_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_RANGE                    2:2
#define PMC_IMPL_PART_XUSBB_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_WOFFSET                  0x0
#define PMC_IMPL_PART_XUSBB_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_DEFAULT                  _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_XUSBB_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_XUSBB_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_XUSBB_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_XUSBB_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_XUSBB_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_XUSBB_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_INIT_ENUM                        OFF
#define PMC_IMPL_PART_XUSBB_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_OFF                      _MK_ENUM_CONST(0)
#define PMC_IMPL_PART_XUSBB_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_ON                       _MK_ENUM_CONST(1)


// Register PMC_IMPL_PART_XUSBB_CLAMP_CONTROL_0
#define PMC_IMPL_PART_XUSBB_CLAMP_CONTROL_0                     _MK_ADDR_CONST(0x2b8)
#define PMC_IMPL_PART_XUSBB_CLAMP_CONTROL_0_SECURE                      0x0
#define PMC_IMPL_PART_XUSBB_CLAMP_CONTROL_0_DUAL                        0x0
#define PMC_IMPL_PART_XUSBB_CLAMP_CONTROL_0_SCR                         PG_XUSBB_SCR_0
#define PMC_IMPL_PART_XUSBB_CLAMP_CONTROL_0_WORD_COUNT                  0x1
#define PMC_IMPL_PART_XUSBB_CLAMP_CONTROL_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_XUSBB_CLAMP_CONTROL_0_RESET_MASK                  _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_XUSBB_CLAMP_CONTROL_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_XUSBB_CLAMP_CONTROL_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_XUSBB_CLAMP_CONTROL_0_READ_MASK                   _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_XUSBB_CLAMP_CONTROL_0_WRITE_MASK                  _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_XUSBB_CLAMP_CONTROL_0_CLAMP_SHIFT                 _MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_XUSBB_CLAMP_CONTROL_0_CLAMP_FIELD                 _MK_FIELD_CONST(0x1, PMC_IMPL_PART_XUSBB_CLAMP_CONTROL_0_CLAMP_SHIFT)
#define PMC_IMPL_PART_XUSBB_CLAMP_CONTROL_0_CLAMP_RANGE                 0:0
#define PMC_IMPL_PART_XUSBB_CLAMP_CONTROL_0_CLAMP_WOFFSET                       0x0
#define PMC_IMPL_PART_XUSBB_CLAMP_CONTROL_0_CLAMP_DEFAULT                       _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_XUSBB_CLAMP_CONTROL_0_CLAMP_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_XUSBB_CLAMP_CONTROL_0_CLAMP_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_XUSBB_CLAMP_CONTROL_0_CLAMP_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_XUSBB_CLAMP_CONTROL_0_CLAMP_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_XUSBB_CLAMP_CONTROL_0_CLAMP_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_XUSBB_CLAMP_CONTROL_0_CLAMP_INIT_ENUM                     OFF
#define PMC_IMPL_PART_XUSBB_CLAMP_CONTROL_0_CLAMP_OFF                   _MK_ENUM_CONST(0)
#define PMC_IMPL_PART_XUSBB_CLAMP_CONTROL_0_CLAMP_ON                    _MK_ENUM_CONST(1)


// Register PMC_IMPL_PART_XUSBC_POWER_GATE_CONTROL_0
#define PMC_IMPL_PART_XUSBC_POWER_GATE_CONTROL_0                        _MK_ADDR_CONST(0x2bc)
#define PMC_IMPL_PART_XUSBC_POWER_GATE_CONTROL_0_SECURE                         0x0
#define PMC_IMPL_PART_XUSBC_POWER_GATE_CONTROL_0_DUAL                   0x0
#define PMC_IMPL_PART_XUSBC_POWER_GATE_CONTROL_0_SCR                    PG_XUSBC_SCR_0
#define PMC_IMPL_PART_XUSBC_POWER_GATE_CONTROL_0_WORD_COUNT                     0x1
#define PMC_IMPL_PART_XUSBC_POWER_GATE_CONTROL_0_RESET_VAL                      _MK_MASK_CONST(0x80000000)
#define PMC_IMPL_PART_XUSBC_POWER_GATE_CONTROL_0_RESET_MASK                     _MK_MASK_CONST(0x80000107)
#define PMC_IMPL_PART_XUSBC_POWER_GATE_CONTROL_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_XUSBC_POWER_GATE_CONTROL_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_XUSBC_POWER_GATE_CONTROL_0_READ_MASK                      _MK_MASK_CONST(0x80000107)
#define PMC_IMPL_PART_XUSBC_POWER_GATE_CONTROL_0_WRITE_MASK                     _MK_MASK_CONST(0x80000107)
#define PMC_IMPL_PART_XUSBC_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SHIFT                      _MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_XUSBC_POWER_GATE_CONTROL_0_LOGIC_SLEEP_FIELD                      _MK_FIELD_CONST(0x1, PMC_IMPL_PART_XUSBC_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SHIFT)
#define PMC_IMPL_PART_XUSBC_POWER_GATE_CONTROL_0_LOGIC_SLEEP_RANGE                      0:0
#define PMC_IMPL_PART_XUSBC_POWER_GATE_CONTROL_0_LOGIC_SLEEP_WOFFSET                    0x0
#define PMC_IMPL_PART_XUSBC_POWER_GATE_CONTROL_0_LOGIC_SLEEP_DEFAULT                    _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_XUSBC_POWER_GATE_CONTROL_0_LOGIC_SLEEP_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_XUSBC_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_XUSBC_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_XUSBC_POWER_GATE_CONTROL_0_LOGIC_SLEEP_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_XUSBC_POWER_GATE_CONTROL_0_LOGIC_SLEEP_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_XUSBC_POWER_GATE_CONTROL_0_LOGIC_SLEEP_INIT_ENUM                  OFF
#define PMC_IMPL_PART_XUSBC_POWER_GATE_CONTROL_0_LOGIC_SLEEP_OFF                        _MK_ENUM_CONST(0)
#define PMC_IMPL_PART_XUSBC_POWER_GATE_CONTROL_0_LOGIC_SLEEP_ON                 _MK_ENUM_CONST(1)

#define PMC_IMPL_PART_XUSBC_POWER_GATE_CONTROL_0_SRAM_RET_EN_SHIFT                      _MK_SHIFT_CONST(1)
#define PMC_IMPL_PART_XUSBC_POWER_GATE_CONTROL_0_SRAM_RET_EN_FIELD                      _MK_FIELD_CONST(0x1, PMC_IMPL_PART_XUSBC_POWER_GATE_CONTROL_0_SRAM_RET_EN_SHIFT)
#define PMC_IMPL_PART_XUSBC_POWER_GATE_CONTROL_0_SRAM_RET_EN_RANGE                      1:1
#define PMC_IMPL_PART_XUSBC_POWER_GATE_CONTROL_0_SRAM_RET_EN_WOFFSET                    0x0
#define PMC_IMPL_PART_XUSBC_POWER_GATE_CONTROL_0_SRAM_RET_EN_DEFAULT                    _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_XUSBC_POWER_GATE_CONTROL_0_SRAM_RET_EN_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_XUSBC_POWER_GATE_CONTROL_0_SRAM_RET_EN_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_XUSBC_POWER_GATE_CONTROL_0_SRAM_RET_EN_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_XUSBC_POWER_GATE_CONTROL_0_SRAM_RET_EN_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_XUSBC_POWER_GATE_CONTROL_0_SRAM_RET_EN_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_XUSBC_POWER_GATE_CONTROL_0_SRAM_RET_EN_INIT_ENUM                  OFF
#define PMC_IMPL_PART_XUSBC_POWER_GATE_CONTROL_0_SRAM_RET_EN_OFF                        _MK_ENUM_CONST(0)
#define PMC_IMPL_PART_XUSBC_POWER_GATE_CONTROL_0_SRAM_RET_EN_ON                 _MK_ENUM_CONST(1)

#define PMC_IMPL_PART_XUSBC_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SHIFT                    _MK_SHIFT_CONST(2)
#define PMC_IMPL_PART_XUSBC_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_FIELD                    _MK_FIELD_CONST(0x1, PMC_IMPL_PART_XUSBC_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SHIFT)
#define PMC_IMPL_PART_XUSBC_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_RANGE                    2:2
#define PMC_IMPL_PART_XUSBC_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_WOFFSET                  0x0
#define PMC_IMPL_PART_XUSBC_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_DEFAULT                  _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_XUSBC_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_XUSBC_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_XUSBC_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_XUSBC_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_XUSBC_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_XUSBC_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_INIT_ENUM                        OFF
#define PMC_IMPL_PART_XUSBC_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_OFF                      _MK_ENUM_CONST(0)
#define PMC_IMPL_PART_XUSBC_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_ON                       _MK_ENUM_CONST(1)

#define PMC_IMPL_PART_XUSBC_POWER_GATE_CONTROL_0_START_SHIFT                    _MK_SHIFT_CONST(8)
#define PMC_IMPL_PART_XUSBC_POWER_GATE_CONTROL_0_START_FIELD                    _MK_FIELD_CONST(0x1, PMC_IMPL_PART_XUSBC_POWER_GATE_CONTROL_0_START_SHIFT)
#define PMC_IMPL_PART_XUSBC_POWER_GATE_CONTROL_0_START_RANGE                    8:8
#define PMC_IMPL_PART_XUSBC_POWER_GATE_CONTROL_0_START_WOFFSET                  0x0
#define PMC_IMPL_PART_XUSBC_POWER_GATE_CONTROL_0_START_DEFAULT                  _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_XUSBC_POWER_GATE_CONTROL_0_START_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_XUSBC_POWER_GATE_CONTROL_0_START_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_XUSBC_POWER_GATE_CONTROL_0_START_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_XUSBC_POWER_GATE_CONTROL_0_START_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_XUSBC_POWER_GATE_CONTROL_0_START_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_XUSBC_POWER_GATE_CONTROL_0_START_INIT_ENUM                        DONE
#define PMC_IMPL_PART_XUSBC_POWER_GATE_CONTROL_0_START_DONE                     _MK_ENUM_CONST(0)
#define PMC_IMPL_PART_XUSBC_POWER_GATE_CONTROL_0_START_PENDING                  _MK_ENUM_CONST(1)

#define PMC_IMPL_PART_XUSBC_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SHIFT                      _MK_SHIFT_CONST(31)
#define PMC_IMPL_PART_XUSBC_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_FIELD                      _MK_FIELD_CONST(0x1, PMC_IMPL_PART_XUSBC_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SHIFT)
#define PMC_IMPL_PART_XUSBC_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_RANGE                      31:31
#define PMC_IMPL_PART_XUSBC_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_WOFFSET                    0x0
#define PMC_IMPL_PART_XUSBC_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_DEFAULT                    _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_XUSBC_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_XUSBC_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_XUSBC_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_XUSBC_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_XUSBC_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_XUSBC_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_INIT_ENUM                  ENABLE
#define PMC_IMPL_PART_XUSBC_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_DISABLE                    _MK_ENUM_CONST(0)
#define PMC_IMPL_PART_XUSBC_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_ENABLE                     _MK_ENUM_CONST(1)


// Register PMC_IMPL_PART_XUSBC_POWER_GATE_STATUS_0
#define PMC_IMPL_PART_XUSBC_POWER_GATE_STATUS_0                 _MK_ADDR_CONST(0x2c0)
#define PMC_IMPL_PART_XUSBC_POWER_GATE_STATUS_0_SECURE                  0x0
#define PMC_IMPL_PART_XUSBC_POWER_GATE_STATUS_0_DUAL                    0x0
#define PMC_IMPL_PART_XUSBC_POWER_GATE_STATUS_0_SCR                     PG_XUSBC_SCR_0
#define PMC_IMPL_PART_XUSBC_POWER_GATE_STATUS_0_WORD_COUNT                      0x1
#define PMC_IMPL_PART_XUSBC_POWER_GATE_STATUS_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_XUSBC_POWER_GATE_STATUS_0_RESET_MASK                      _MK_MASK_CONST(0x7)
#define PMC_IMPL_PART_XUSBC_POWER_GATE_STATUS_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_XUSBC_POWER_GATE_STATUS_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_XUSBC_POWER_GATE_STATUS_0_READ_MASK                       _MK_MASK_CONST(0x7)
#define PMC_IMPL_PART_XUSBC_POWER_GATE_STATUS_0_WRITE_MASK                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_XUSBC_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SHIFT                   _MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_XUSBC_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_FIELD                   _MK_FIELD_CONST(0x1, PMC_IMPL_PART_XUSBC_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SHIFT)
#define PMC_IMPL_PART_XUSBC_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_RANGE                   0:0
#define PMC_IMPL_PART_XUSBC_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_WOFFSET                 0x0
#define PMC_IMPL_PART_XUSBC_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_DEFAULT                 _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_XUSBC_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_XUSBC_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_XUSBC_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_XUSBC_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_XUSBC_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_XUSBC_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_INIT_ENUM                       OFF
#define PMC_IMPL_PART_XUSBC_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_OFF                     _MK_ENUM_CONST(0)
#define PMC_IMPL_PART_XUSBC_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_ON                      _MK_ENUM_CONST(1)

#define PMC_IMPL_PART_XUSBC_POWER_GATE_STATUS_0_SRAM_RET_STS_SHIFT                      _MK_SHIFT_CONST(1)
#define PMC_IMPL_PART_XUSBC_POWER_GATE_STATUS_0_SRAM_RET_STS_FIELD                      _MK_FIELD_CONST(0x1, PMC_IMPL_PART_XUSBC_POWER_GATE_STATUS_0_SRAM_RET_STS_SHIFT)
#define PMC_IMPL_PART_XUSBC_POWER_GATE_STATUS_0_SRAM_RET_STS_RANGE                      1:1
#define PMC_IMPL_PART_XUSBC_POWER_GATE_STATUS_0_SRAM_RET_STS_WOFFSET                    0x0
#define PMC_IMPL_PART_XUSBC_POWER_GATE_STATUS_0_SRAM_RET_STS_DEFAULT                    _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_XUSBC_POWER_GATE_STATUS_0_SRAM_RET_STS_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_XUSBC_POWER_GATE_STATUS_0_SRAM_RET_STS_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_XUSBC_POWER_GATE_STATUS_0_SRAM_RET_STS_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_XUSBC_POWER_GATE_STATUS_0_SRAM_RET_STS_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_XUSBC_POWER_GATE_STATUS_0_SRAM_RET_STS_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_XUSBC_POWER_GATE_STATUS_0_SRAM_RET_STS_INIT_ENUM                  OFF
#define PMC_IMPL_PART_XUSBC_POWER_GATE_STATUS_0_SRAM_RET_STS_OFF                        _MK_ENUM_CONST(0)
#define PMC_IMPL_PART_XUSBC_POWER_GATE_STATUS_0_SRAM_RET_STS_ON                 _MK_ENUM_CONST(1)

#define PMC_IMPL_PART_XUSBC_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SHIFT                    _MK_SHIFT_CONST(2)
#define PMC_IMPL_PART_XUSBC_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_FIELD                    _MK_FIELD_CONST(0x1, PMC_IMPL_PART_XUSBC_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SHIFT)
#define PMC_IMPL_PART_XUSBC_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_RANGE                    2:2
#define PMC_IMPL_PART_XUSBC_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_WOFFSET                  0x0
#define PMC_IMPL_PART_XUSBC_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_DEFAULT                  _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_XUSBC_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_XUSBC_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_XUSBC_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_XUSBC_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_XUSBC_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_XUSBC_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_INIT_ENUM                        OFF
#define PMC_IMPL_PART_XUSBC_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_OFF                      _MK_ENUM_CONST(0)
#define PMC_IMPL_PART_XUSBC_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_ON                       _MK_ENUM_CONST(1)


// Register PMC_IMPL_PART_XUSBC_CLAMP_CONTROL_0
#define PMC_IMPL_PART_XUSBC_CLAMP_CONTROL_0                     _MK_ADDR_CONST(0x2c4)
#define PMC_IMPL_PART_XUSBC_CLAMP_CONTROL_0_SECURE                      0x0
#define PMC_IMPL_PART_XUSBC_CLAMP_CONTROL_0_DUAL                        0x0
#define PMC_IMPL_PART_XUSBC_CLAMP_CONTROL_0_SCR                         PG_XUSBC_SCR_0
#define PMC_IMPL_PART_XUSBC_CLAMP_CONTROL_0_WORD_COUNT                  0x1
#define PMC_IMPL_PART_XUSBC_CLAMP_CONTROL_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_XUSBC_CLAMP_CONTROL_0_RESET_MASK                  _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_XUSBC_CLAMP_CONTROL_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_XUSBC_CLAMP_CONTROL_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_XUSBC_CLAMP_CONTROL_0_READ_MASK                   _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_XUSBC_CLAMP_CONTROL_0_WRITE_MASK                  _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_XUSBC_CLAMP_CONTROL_0_CLAMP_SHIFT                 _MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_XUSBC_CLAMP_CONTROL_0_CLAMP_FIELD                 _MK_FIELD_CONST(0x1, PMC_IMPL_PART_XUSBC_CLAMP_CONTROL_0_CLAMP_SHIFT)
#define PMC_IMPL_PART_XUSBC_CLAMP_CONTROL_0_CLAMP_RANGE                 0:0
#define PMC_IMPL_PART_XUSBC_CLAMP_CONTROL_0_CLAMP_WOFFSET                       0x0
#define PMC_IMPL_PART_XUSBC_CLAMP_CONTROL_0_CLAMP_DEFAULT                       _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_XUSBC_CLAMP_CONTROL_0_CLAMP_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_XUSBC_CLAMP_CONTROL_0_CLAMP_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_XUSBC_CLAMP_CONTROL_0_CLAMP_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_XUSBC_CLAMP_CONTROL_0_CLAMP_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_XUSBC_CLAMP_CONTROL_0_CLAMP_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_XUSBC_CLAMP_CONTROL_0_CLAMP_INIT_ENUM                     OFF
#define PMC_IMPL_PART_XUSBC_CLAMP_CONTROL_0_CLAMP_OFF                   _MK_ENUM_CONST(0)
#define PMC_IMPL_PART_XUSBC_CLAMP_CONTROL_0_CLAMP_ON                    _MK_ENUM_CONST(1)


// Register PMC_IMPL_PART_SCRATCH_POWER_GATE_CONTROL_0
#define PMC_IMPL_PART_SCRATCH_POWER_GATE_CONTROL_0                      _MK_ADDR_CONST(0x2c8)
#define PMC_IMPL_PART_SCRATCH_POWER_GATE_CONTROL_0_SECURE                       0x0
#define PMC_IMPL_PART_SCRATCH_POWER_GATE_CONTROL_0_DUAL                         0x0
#define PMC_IMPL_PART_SCRATCH_POWER_GATE_CONTROL_0_SCR                  PG_SCRATCH_SCR_0
#define PMC_IMPL_PART_SCRATCH_POWER_GATE_CONTROL_0_WORD_COUNT                   0x1
#define PMC_IMPL_PART_SCRATCH_POWER_GATE_CONTROL_0_RESET_VAL                    _MK_MASK_CONST(0x80000000)
#define PMC_IMPL_PART_SCRATCH_POWER_GATE_CONTROL_0_RESET_MASK                   _MK_MASK_CONST(0x80000107)
#define PMC_IMPL_PART_SCRATCH_POWER_GATE_CONTROL_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_SCRATCH_POWER_GATE_CONTROL_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_SCRATCH_POWER_GATE_CONTROL_0_READ_MASK                    _MK_MASK_CONST(0x80000107)
#define PMC_IMPL_PART_SCRATCH_POWER_GATE_CONTROL_0_WRITE_MASK                   _MK_MASK_CONST(0x80000107)
#define PMC_IMPL_PART_SCRATCH_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SHIFT                    _MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_SCRATCH_POWER_GATE_CONTROL_0_LOGIC_SLEEP_FIELD                    _MK_FIELD_CONST(0x1, PMC_IMPL_PART_SCRATCH_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SHIFT)
#define PMC_IMPL_PART_SCRATCH_POWER_GATE_CONTROL_0_LOGIC_SLEEP_RANGE                    0:0
#define PMC_IMPL_PART_SCRATCH_POWER_GATE_CONTROL_0_LOGIC_SLEEP_WOFFSET                  0x0
#define PMC_IMPL_PART_SCRATCH_POWER_GATE_CONTROL_0_LOGIC_SLEEP_DEFAULT                  _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_SCRATCH_POWER_GATE_CONTROL_0_LOGIC_SLEEP_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_SCRATCH_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_SCRATCH_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_SCRATCH_POWER_GATE_CONTROL_0_LOGIC_SLEEP_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_SCRATCH_POWER_GATE_CONTROL_0_LOGIC_SLEEP_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_SCRATCH_POWER_GATE_CONTROL_0_LOGIC_SLEEP_INIT_ENUM                        OFF
#define PMC_IMPL_PART_SCRATCH_POWER_GATE_CONTROL_0_LOGIC_SLEEP_OFF                      _MK_ENUM_CONST(0)
#define PMC_IMPL_PART_SCRATCH_POWER_GATE_CONTROL_0_LOGIC_SLEEP_ON                       _MK_ENUM_CONST(1)

#define PMC_IMPL_PART_SCRATCH_POWER_GATE_CONTROL_0_SRAM_RET_EN_SHIFT                    _MK_SHIFT_CONST(1)
#define PMC_IMPL_PART_SCRATCH_POWER_GATE_CONTROL_0_SRAM_RET_EN_FIELD                    _MK_FIELD_CONST(0x1, PMC_IMPL_PART_SCRATCH_POWER_GATE_CONTROL_0_SRAM_RET_EN_SHIFT)
#define PMC_IMPL_PART_SCRATCH_POWER_GATE_CONTROL_0_SRAM_RET_EN_RANGE                    1:1
#define PMC_IMPL_PART_SCRATCH_POWER_GATE_CONTROL_0_SRAM_RET_EN_WOFFSET                  0x0
#define PMC_IMPL_PART_SCRATCH_POWER_GATE_CONTROL_0_SRAM_RET_EN_DEFAULT                  _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_SCRATCH_POWER_GATE_CONTROL_0_SRAM_RET_EN_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_SCRATCH_POWER_GATE_CONTROL_0_SRAM_RET_EN_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_SCRATCH_POWER_GATE_CONTROL_0_SRAM_RET_EN_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_SCRATCH_POWER_GATE_CONTROL_0_SRAM_RET_EN_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_SCRATCH_POWER_GATE_CONTROL_0_SRAM_RET_EN_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_SCRATCH_POWER_GATE_CONTROL_0_SRAM_RET_EN_INIT_ENUM                        OFF
#define PMC_IMPL_PART_SCRATCH_POWER_GATE_CONTROL_0_SRAM_RET_EN_OFF                      _MK_ENUM_CONST(0)
#define PMC_IMPL_PART_SCRATCH_POWER_GATE_CONTROL_0_SRAM_RET_EN_ON                       _MK_ENUM_CONST(1)

#define PMC_IMPL_PART_SCRATCH_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SHIFT                  _MK_SHIFT_CONST(2)
#define PMC_IMPL_PART_SCRATCH_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_FIELD                  _MK_FIELD_CONST(0x1, PMC_IMPL_PART_SCRATCH_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SHIFT)
#define PMC_IMPL_PART_SCRATCH_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_RANGE                  2:2
#define PMC_IMPL_PART_SCRATCH_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_WOFFSET                        0x0
#define PMC_IMPL_PART_SCRATCH_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_DEFAULT                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_SCRATCH_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_SCRATCH_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_SCRATCH_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_SCRATCH_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_SCRATCH_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_SCRATCH_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_INIT_ENUM                      OFF
#define PMC_IMPL_PART_SCRATCH_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_OFF                    _MK_ENUM_CONST(0)
#define PMC_IMPL_PART_SCRATCH_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_ON                     _MK_ENUM_CONST(1)

#define PMC_IMPL_PART_SCRATCH_POWER_GATE_CONTROL_0_START_SHIFT                  _MK_SHIFT_CONST(8)
#define PMC_IMPL_PART_SCRATCH_POWER_GATE_CONTROL_0_START_FIELD                  _MK_FIELD_CONST(0x1, PMC_IMPL_PART_SCRATCH_POWER_GATE_CONTROL_0_START_SHIFT)
#define PMC_IMPL_PART_SCRATCH_POWER_GATE_CONTROL_0_START_RANGE                  8:8
#define PMC_IMPL_PART_SCRATCH_POWER_GATE_CONTROL_0_START_WOFFSET                        0x0
#define PMC_IMPL_PART_SCRATCH_POWER_GATE_CONTROL_0_START_DEFAULT                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_SCRATCH_POWER_GATE_CONTROL_0_START_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_SCRATCH_POWER_GATE_CONTROL_0_START_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_SCRATCH_POWER_GATE_CONTROL_0_START_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_SCRATCH_POWER_GATE_CONTROL_0_START_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_SCRATCH_POWER_GATE_CONTROL_0_START_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_SCRATCH_POWER_GATE_CONTROL_0_START_INIT_ENUM                      DONE
#define PMC_IMPL_PART_SCRATCH_POWER_GATE_CONTROL_0_START_DONE                   _MK_ENUM_CONST(0)
#define PMC_IMPL_PART_SCRATCH_POWER_GATE_CONTROL_0_START_PENDING                        _MK_ENUM_CONST(1)

#define PMC_IMPL_PART_SCRATCH_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SHIFT                    _MK_SHIFT_CONST(31)
#define PMC_IMPL_PART_SCRATCH_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_FIELD                    _MK_FIELD_CONST(0x1, PMC_IMPL_PART_SCRATCH_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SHIFT)
#define PMC_IMPL_PART_SCRATCH_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_RANGE                    31:31
#define PMC_IMPL_PART_SCRATCH_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_WOFFSET                  0x0
#define PMC_IMPL_PART_SCRATCH_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_DEFAULT                  _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_SCRATCH_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_SCRATCH_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_SCRATCH_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_SCRATCH_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_SCRATCH_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_SCRATCH_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_INIT_ENUM                        ENABLE
#define PMC_IMPL_PART_SCRATCH_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_DISABLE                  _MK_ENUM_CONST(0)
#define PMC_IMPL_PART_SCRATCH_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_ENABLE                   _MK_ENUM_CONST(1)


// Register PMC_IMPL_PART_SCRATCH_POWER_GATE_STATUS_0
#define PMC_IMPL_PART_SCRATCH_POWER_GATE_STATUS_0                       _MK_ADDR_CONST(0x2cc)
#define PMC_IMPL_PART_SCRATCH_POWER_GATE_STATUS_0_SECURE                        0x0
#define PMC_IMPL_PART_SCRATCH_POWER_GATE_STATUS_0_DUAL                  0x0
#define PMC_IMPL_PART_SCRATCH_POWER_GATE_STATUS_0_SCR                   PG_SCRATCH_SCR_0
#define PMC_IMPL_PART_SCRATCH_POWER_GATE_STATUS_0_WORD_COUNT                    0x1
#define PMC_IMPL_PART_SCRATCH_POWER_GATE_STATUS_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_SCRATCH_POWER_GATE_STATUS_0_RESET_MASK                    _MK_MASK_CONST(0x7)
#define PMC_IMPL_PART_SCRATCH_POWER_GATE_STATUS_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_SCRATCH_POWER_GATE_STATUS_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_SCRATCH_POWER_GATE_STATUS_0_READ_MASK                     _MK_MASK_CONST(0x7)
#define PMC_IMPL_PART_SCRATCH_POWER_GATE_STATUS_0_WRITE_MASK                    _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_SCRATCH_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SHIFT                 _MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_SCRATCH_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_FIELD                 _MK_FIELD_CONST(0x1, PMC_IMPL_PART_SCRATCH_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SHIFT)
#define PMC_IMPL_PART_SCRATCH_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_RANGE                 0:0
#define PMC_IMPL_PART_SCRATCH_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_WOFFSET                       0x0
#define PMC_IMPL_PART_SCRATCH_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_DEFAULT                       _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_SCRATCH_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_SCRATCH_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_SCRATCH_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_SCRATCH_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_SCRATCH_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_SCRATCH_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_INIT_ENUM                     OFF
#define PMC_IMPL_PART_SCRATCH_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_OFF                   _MK_ENUM_CONST(0)
#define PMC_IMPL_PART_SCRATCH_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_ON                    _MK_ENUM_CONST(1)

#define PMC_IMPL_PART_SCRATCH_POWER_GATE_STATUS_0_SRAM_RET_STS_SHIFT                    _MK_SHIFT_CONST(1)
#define PMC_IMPL_PART_SCRATCH_POWER_GATE_STATUS_0_SRAM_RET_STS_FIELD                    _MK_FIELD_CONST(0x1, PMC_IMPL_PART_SCRATCH_POWER_GATE_STATUS_0_SRAM_RET_STS_SHIFT)
#define PMC_IMPL_PART_SCRATCH_POWER_GATE_STATUS_0_SRAM_RET_STS_RANGE                    1:1
#define PMC_IMPL_PART_SCRATCH_POWER_GATE_STATUS_0_SRAM_RET_STS_WOFFSET                  0x0
#define PMC_IMPL_PART_SCRATCH_POWER_GATE_STATUS_0_SRAM_RET_STS_DEFAULT                  _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_SCRATCH_POWER_GATE_STATUS_0_SRAM_RET_STS_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_SCRATCH_POWER_GATE_STATUS_0_SRAM_RET_STS_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_SCRATCH_POWER_GATE_STATUS_0_SRAM_RET_STS_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_SCRATCH_POWER_GATE_STATUS_0_SRAM_RET_STS_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_SCRATCH_POWER_GATE_STATUS_0_SRAM_RET_STS_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_SCRATCH_POWER_GATE_STATUS_0_SRAM_RET_STS_INIT_ENUM                        OFF
#define PMC_IMPL_PART_SCRATCH_POWER_GATE_STATUS_0_SRAM_RET_STS_OFF                      _MK_ENUM_CONST(0)
#define PMC_IMPL_PART_SCRATCH_POWER_GATE_STATUS_0_SRAM_RET_STS_ON                       _MK_ENUM_CONST(1)

#define PMC_IMPL_PART_SCRATCH_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SHIFT                  _MK_SHIFT_CONST(2)
#define PMC_IMPL_PART_SCRATCH_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_FIELD                  _MK_FIELD_CONST(0x1, PMC_IMPL_PART_SCRATCH_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SHIFT)
#define PMC_IMPL_PART_SCRATCH_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_RANGE                  2:2
#define PMC_IMPL_PART_SCRATCH_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_WOFFSET                        0x0
#define PMC_IMPL_PART_SCRATCH_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_DEFAULT                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_SCRATCH_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_SCRATCH_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_SCRATCH_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_SCRATCH_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_SCRATCH_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_SCRATCH_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_INIT_ENUM                      OFF
#define PMC_IMPL_PART_SCRATCH_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_OFF                    _MK_ENUM_CONST(0)
#define PMC_IMPL_PART_SCRATCH_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_ON                     _MK_ENUM_CONST(1)


// Register PMC_IMPL_PART_SCRATCH_CLAMP_CONTROL_0
#define PMC_IMPL_PART_SCRATCH_CLAMP_CONTROL_0                   _MK_ADDR_CONST(0x2d0)
#define PMC_IMPL_PART_SCRATCH_CLAMP_CONTROL_0_SECURE                    0x0
#define PMC_IMPL_PART_SCRATCH_CLAMP_CONTROL_0_DUAL                      0x0
#define PMC_IMPL_PART_SCRATCH_CLAMP_CONTROL_0_SCR                       PG_SCRATCH_SCR_0
#define PMC_IMPL_PART_SCRATCH_CLAMP_CONTROL_0_WORD_COUNT                        0x1
#define PMC_IMPL_PART_SCRATCH_CLAMP_CONTROL_0_RESET_VAL                         _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_SCRATCH_CLAMP_CONTROL_0_RESET_MASK                        _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_SCRATCH_CLAMP_CONTROL_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_SCRATCH_CLAMP_CONTROL_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_SCRATCH_CLAMP_CONTROL_0_READ_MASK                         _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_SCRATCH_CLAMP_CONTROL_0_WRITE_MASK                        _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_SCRATCH_CLAMP_CONTROL_0_CLAMP_SHIFT                       _MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_SCRATCH_CLAMP_CONTROL_0_CLAMP_FIELD                       _MK_FIELD_CONST(0x1, PMC_IMPL_PART_SCRATCH_CLAMP_CONTROL_0_CLAMP_SHIFT)
#define PMC_IMPL_PART_SCRATCH_CLAMP_CONTROL_0_CLAMP_RANGE                       0:0
#define PMC_IMPL_PART_SCRATCH_CLAMP_CONTROL_0_CLAMP_WOFFSET                     0x0
#define PMC_IMPL_PART_SCRATCH_CLAMP_CONTROL_0_CLAMP_DEFAULT                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_SCRATCH_CLAMP_CONTROL_0_CLAMP_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_SCRATCH_CLAMP_CONTROL_0_CLAMP_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_SCRATCH_CLAMP_CONTROL_0_CLAMP_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_SCRATCH_CLAMP_CONTROL_0_CLAMP_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_SCRATCH_CLAMP_CONTROL_0_CLAMP_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_SCRATCH_CLAMP_CONTROL_0_CLAMP_INIT_ENUM                   OFF
#define PMC_IMPL_PART_SCRATCH_CLAMP_CONTROL_0_CLAMP_OFF                 _MK_ENUM_CONST(0)
#define PMC_IMPL_PART_SCRATCH_CLAMP_CONTROL_0_CLAMP_ON                  _MK_ENUM_CONST(1)


// Register PMC_IMPL_PART_AONPG_POWER_GATE_CONTROL_0
#define PMC_IMPL_PART_AONPG_POWER_GATE_CONTROL_0                        _MK_ADDR_CONST(0x2d4)
#define PMC_IMPL_PART_AONPG_POWER_GATE_CONTROL_0_SECURE                         0x0
#define PMC_IMPL_PART_AONPG_POWER_GATE_CONTROL_0_DUAL                   0x0
#define PMC_IMPL_PART_AONPG_POWER_GATE_CONTROL_0_SCR                    PG_AONPG_SCR_0
#define PMC_IMPL_PART_AONPG_POWER_GATE_CONTROL_0_WORD_COUNT                     0x1
#define PMC_IMPL_PART_AONPG_POWER_GATE_CONTROL_0_RESET_VAL                      _MK_MASK_CONST(0x80000000)
#define PMC_IMPL_PART_AONPG_POWER_GATE_CONTROL_0_RESET_MASK                     _MK_MASK_CONST(0x80000107)
#define PMC_IMPL_PART_AONPG_POWER_GATE_CONTROL_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AONPG_POWER_GATE_CONTROL_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AONPG_POWER_GATE_CONTROL_0_READ_MASK                      _MK_MASK_CONST(0x80000107)
#define PMC_IMPL_PART_AONPG_POWER_GATE_CONTROL_0_WRITE_MASK                     _MK_MASK_CONST(0x80000107)
#define PMC_IMPL_PART_AONPG_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SHIFT                      _MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_AONPG_POWER_GATE_CONTROL_0_LOGIC_SLEEP_FIELD                      _MK_FIELD_CONST(0x1, PMC_IMPL_PART_AONPG_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SHIFT)
#define PMC_IMPL_PART_AONPG_POWER_GATE_CONTROL_0_LOGIC_SLEEP_RANGE                      0:0
#define PMC_IMPL_PART_AONPG_POWER_GATE_CONTROL_0_LOGIC_SLEEP_WOFFSET                    0x0
#define PMC_IMPL_PART_AONPG_POWER_GATE_CONTROL_0_LOGIC_SLEEP_DEFAULT                    _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AONPG_POWER_GATE_CONTROL_0_LOGIC_SLEEP_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AONPG_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AONPG_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AONPG_POWER_GATE_CONTROL_0_LOGIC_SLEEP_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AONPG_POWER_GATE_CONTROL_0_LOGIC_SLEEP_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AONPG_POWER_GATE_CONTROL_0_LOGIC_SLEEP_INIT_ENUM                  OFF
#define PMC_IMPL_PART_AONPG_POWER_GATE_CONTROL_0_LOGIC_SLEEP_OFF                        _MK_ENUM_CONST(0)
#define PMC_IMPL_PART_AONPG_POWER_GATE_CONTROL_0_LOGIC_SLEEP_ON                 _MK_ENUM_CONST(1)

#define PMC_IMPL_PART_AONPG_POWER_GATE_CONTROL_0_SRAM_RET_EN_SHIFT                      _MK_SHIFT_CONST(1)
#define PMC_IMPL_PART_AONPG_POWER_GATE_CONTROL_0_SRAM_RET_EN_FIELD                      _MK_FIELD_CONST(0x1, PMC_IMPL_PART_AONPG_POWER_GATE_CONTROL_0_SRAM_RET_EN_SHIFT)
#define PMC_IMPL_PART_AONPG_POWER_GATE_CONTROL_0_SRAM_RET_EN_RANGE                      1:1
#define PMC_IMPL_PART_AONPG_POWER_GATE_CONTROL_0_SRAM_RET_EN_WOFFSET                    0x0
#define PMC_IMPL_PART_AONPG_POWER_GATE_CONTROL_0_SRAM_RET_EN_DEFAULT                    _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AONPG_POWER_GATE_CONTROL_0_SRAM_RET_EN_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AONPG_POWER_GATE_CONTROL_0_SRAM_RET_EN_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AONPG_POWER_GATE_CONTROL_0_SRAM_RET_EN_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AONPG_POWER_GATE_CONTROL_0_SRAM_RET_EN_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AONPG_POWER_GATE_CONTROL_0_SRAM_RET_EN_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AONPG_POWER_GATE_CONTROL_0_SRAM_RET_EN_INIT_ENUM                  OFF
#define PMC_IMPL_PART_AONPG_POWER_GATE_CONTROL_0_SRAM_RET_EN_OFF                        _MK_ENUM_CONST(0)
#define PMC_IMPL_PART_AONPG_POWER_GATE_CONTROL_0_SRAM_RET_EN_ON                 _MK_ENUM_CONST(1)

#define PMC_IMPL_PART_AONPG_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SHIFT                    _MK_SHIFT_CONST(2)
#define PMC_IMPL_PART_AONPG_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_FIELD                    _MK_FIELD_CONST(0x1, PMC_IMPL_PART_AONPG_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SHIFT)
#define PMC_IMPL_PART_AONPG_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_RANGE                    2:2
#define PMC_IMPL_PART_AONPG_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_WOFFSET                  0x0
#define PMC_IMPL_PART_AONPG_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_DEFAULT                  _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AONPG_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AONPG_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AONPG_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AONPG_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AONPG_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AONPG_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_INIT_ENUM                        OFF
#define PMC_IMPL_PART_AONPG_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_OFF                      _MK_ENUM_CONST(0)
#define PMC_IMPL_PART_AONPG_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_ON                       _MK_ENUM_CONST(1)

#define PMC_IMPL_PART_AONPG_POWER_GATE_CONTROL_0_START_SHIFT                    _MK_SHIFT_CONST(8)
#define PMC_IMPL_PART_AONPG_POWER_GATE_CONTROL_0_START_FIELD                    _MK_FIELD_CONST(0x1, PMC_IMPL_PART_AONPG_POWER_GATE_CONTROL_0_START_SHIFT)
#define PMC_IMPL_PART_AONPG_POWER_GATE_CONTROL_0_START_RANGE                    8:8
#define PMC_IMPL_PART_AONPG_POWER_GATE_CONTROL_0_START_WOFFSET                  0x0
#define PMC_IMPL_PART_AONPG_POWER_GATE_CONTROL_0_START_DEFAULT                  _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AONPG_POWER_GATE_CONTROL_0_START_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AONPG_POWER_GATE_CONTROL_0_START_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AONPG_POWER_GATE_CONTROL_0_START_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AONPG_POWER_GATE_CONTROL_0_START_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AONPG_POWER_GATE_CONTROL_0_START_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AONPG_POWER_GATE_CONTROL_0_START_INIT_ENUM                        DONE
#define PMC_IMPL_PART_AONPG_POWER_GATE_CONTROL_0_START_DONE                     _MK_ENUM_CONST(0)
#define PMC_IMPL_PART_AONPG_POWER_GATE_CONTROL_0_START_PENDING                  _MK_ENUM_CONST(1)

#define PMC_IMPL_PART_AONPG_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SHIFT                      _MK_SHIFT_CONST(31)
#define PMC_IMPL_PART_AONPG_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_FIELD                      _MK_FIELD_CONST(0x1, PMC_IMPL_PART_AONPG_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SHIFT)
#define PMC_IMPL_PART_AONPG_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_RANGE                      31:31
#define PMC_IMPL_PART_AONPG_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_WOFFSET                    0x0
#define PMC_IMPL_PART_AONPG_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_DEFAULT                    _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AONPG_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AONPG_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AONPG_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AONPG_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AONPG_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AONPG_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_INIT_ENUM                  ENABLE
#define PMC_IMPL_PART_AONPG_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_DISABLE                    _MK_ENUM_CONST(0)
#define PMC_IMPL_PART_AONPG_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_ENABLE                     _MK_ENUM_CONST(1)


// Register PMC_IMPL_PART_AONPG_POWER_GATE_STATUS_0
#define PMC_IMPL_PART_AONPG_POWER_GATE_STATUS_0                 _MK_ADDR_CONST(0x2d8)
#define PMC_IMPL_PART_AONPG_POWER_GATE_STATUS_0_SECURE                  0x0
#define PMC_IMPL_PART_AONPG_POWER_GATE_STATUS_0_DUAL                    0x0
#define PMC_IMPL_PART_AONPG_POWER_GATE_STATUS_0_SCR                     PG_AONPG_SCR_0
#define PMC_IMPL_PART_AONPG_POWER_GATE_STATUS_0_WORD_COUNT                      0x1
#define PMC_IMPL_PART_AONPG_POWER_GATE_STATUS_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AONPG_POWER_GATE_STATUS_0_RESET_MASK                      _MK_MASK_CONST(0x7)
#define PMC_IMPL_PART_AONPG_POWER_GATE_STATUS_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AONPG_POWER_GATE_STATUS_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AONPG_POWER_GATE_STATUS_0_READ_MASK                       _MK_MASK_CONST(0x7)
#define PMC_IMPL_PART_AONPG_POWER_GATE_STATUS_0_WRITE_MASK                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AONPG_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SHIFT                   _MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_AONPG_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_FIELD                   _MK_FIELD_CONST(0x1, PMC_IMPL_PART_AONPG_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SHIFT)
#define PMC_IMPL_PART_AONPG_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_RANGE                   0:0
#define PMC_IMPL_PART_AONPG_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_WOFFSET                 0x0
#define PMC_IMPL_PART_AONPG_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_DEFAULT                 _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AONPG_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AONPG_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AONPG_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AONPG_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AONPG_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AONPG_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_INIT_ENUM                       OFF
#define PMC_IMPL_PART_AONPG_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_OFF                     _MK_ENUM_CONST(0)
#define PMC_IMPL_PART_AONPG_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_ON                      _MK_ENUM_CONST(1)

#define PMC_IMPL_PART_AONPG_POWER_GATE_STATUS_0_SRAM_RET_STS_SHIFT                      _MK_SHIFT_CONST(1)
#define PMC_IMPL_PART_AONPG_POWER_GATE_STATUS_0_SRAM_RET_STS_FIELD                      _MK_FIELD_CONST(0x1, PMC_IMPL_PART_AONPG_POWER_GATE_STATUS_0_SRAM_RET_STS_SHIFT)
#define PMC_IMPL_PART_AONPG_POWER_GATE_STATUS_0_SRAM_RET_STS_RANGE                      1:1
#define PMC_IMPL_PART_AONPG_POWER_GATE_STATUS_0_SRAM_RET_STS_WOFFSET                    0x0
#define PMC_IMPL_PART_AONPG_POWER_GATE_STATUS_0_SRAM_RET_STS_DEFAULT                    _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AONPG_POWER_GATE_STATUS_0_SRAM_RET_STS_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AONPG_POWER_GATE_STATUS_0_SRAM_RET_STS_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AONPG_POWER_GATE_STATUS_0_SRAM_RET_STS_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AONPG_POWER_GATE_STATUS_0_SRAM_RET_STS_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AONPG_POWER_GATE_STATUS_0_SRAM_RET_STS_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AONPG_POWER_GATE_STATUS_0_SRAM_RET_STS_INIT_ENUM                  OFF
#define PMC_IMPL_PART_AONPG_POWER_GATE_STATUS_0_SRAM_RET_STS_OFF                        _MK_ENUM_CONST(0)
#define PMC_IMPL_PART_AONPG_POWER_GATE_STATUS_0_SRAM_RET_STS_ON                 _MK_ENUM_CONST(1)

#define PMC_IMPL_PART_AONPG_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SHIFT                    _MK_SHIFT_CONST(2)
#define PMC_IMPL_PART_AONPG_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_FIELD                    _MK_FIELD_CONST(0x1, PMC_IMPL_PART_AONPG_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SHIFT)
#define PMC_IMPL_PART_AONPG_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_RANGE                    2:2
#define PMC_IMPL_PART_AONPG_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_WOFFSET                  0x0
#define PMC_IMPL_PART_AONPG_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_DEFAULT                  _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AONPG_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AONPG_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AONPG_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AONPG_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AONPG_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AONPG_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_INIT_ENUM                        OFF
#define PMC_IMPL_PART_AONPG_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_OFF                      _MK_ENUM_CONST(0)
#define PMC_IMPL_PART_AONPG_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_ON                       _MK_ENUM_CONST(1)


// Register PMC_IMPL_PART_AONPG_CLAMP_CONTROL_0
#define PMC_IMPL_PART_AONPG_CLAMP_CONTROL_0                     _MK_ADDR_CONST(0x2dc)
#define PMC_IMPL_PART_AONPG_CLAMP_CONTROL_0_SECURE                      0x0
#define PMC_IMPL_PART_AONPG_CLAMP_CONTROL_0_DUAL                        0x0
#define PMC_IMPL_PART_AONPG_CLAMP_CONTROL_0_SCR                         PG_AONPG_SCR_0
#define PMC_IMPL_PART_AONPG_CLAMP_CONTROL_0_WORD_COUNT                  0x1
#define PMC_IMPL_PART_AONPG_CLAMP_CONTROL_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AONPG_CLAMP_CONTROL_0_RESET_MASK                  _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AONPG_CLAMP_CONTROL_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AONPG_CLAMP_CONTROL_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AONPG_CLAMP_CONTROL_0_READ_MASK                   _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AONPG_CLAMP_CONTROL_0_WRITE_MASK                  _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AONPG_CLAMP_CONTROL_0_CLAMP_SHIFT                 _MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_AONPG_CLAMP_CONTROL_0_CLAMP_FIELD                 _MK_FIELD_CONST(0x1, PMC_IMPL_PART_AONPG_CLAMP_CONTROL_0_CLAMP_SHIFT)
#define PMC_IMPL_PART_AONPG_CLAMP_CONTROL_0_CLAMP_RANGE                 0:0
#define PMC_IMPL_PART_AONPG_CLAMP_CONTROL_0_CLAMP_WOFFSET                       0x0
#define PMC_IMPL_PART_AONPG_CLAMP_CONTROL_0_CLAMP_DEFAULT                       _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AONPG_CLAMP_CONTROL_0_CLAMP_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AONPG_CLAMP_CONTROL_0_CLAMP_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AONPG_CLAMP_CONTROL_0_CLAMP_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AONPG_CLAMP_CONTROL_0_CLAMP_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AONPG_CLAMP_CONTROL_0_CLAMP_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AONPG_CLAMP_CONTROL_0_CLAMP_INIT_ENUM                     OFF
#define PMC_IMPL_PART_AONPG_CLAMP_CONTROL_0_CLAMP_OFF                   _MK_ENUM_CONST(0)
#define PMC_IMPL_PART_AONPG_CLAMP_CONTROL_0_CLAMP_ON                    _MK_ENUM_CONST(1)


// Reserved address 0x2e0

// Reserved address 0x2e4

// Reserved address 0x2e8

// Reserved address 0x2ec

// Reserved address 0x2f0

// Reserved address 0x2f4

// Reserved address 0x2f8

// Reserved address 0x2fc

// Reserved address 0x300

// Reserved address 0x304

// Reserved address 0x308

// Reserved address 0x30c

// Reserved address 0x310

// Reserved address 0x314

// Reserved address 0x318

// Reserved address 0x31c

// Reserved address 0x320

// Reserved address 0x324

// Reserved address 0x328

// Reserved address 0x32c

// Reserved address 0x330

// Reserved address 0x334

// Reserved address 0x338

// Reserved address 0x33c

// Reserved address 0x340

// Reserved address 0x344

// Reserved address 0x348

// Reserved address 0x34c

// Reserved address 0x350

// Reserved address 0x354

// Reserved address 0x358

// Reserved address 0x35c

// Reserved address 0x360

// Reserved address 0x364

// Reserved address 0x368

// Reserved address 0x36c

// Register PMC_IMPL_PART_BPMP_POWER_GATE_CONTROL_0
#define PMC_IMPL_PART_BPMP_POWER_GATE_CONTROL_0                 _MK_ADDR_CONST(0x370)
#define PMC_IMPL_PART_BPMP_POWER_GATE_CONTROL_0_SECURE                  0x0
#define PMC_IMPL_PART_BPMP_POWER_GATE_CONTROL_0_DUAL                    0x0
#define PMC_IMPL_PART_BPMP_POWER_GATE_CONTROL_0_SCR                     PG_BPMP_SCR_0
#define PMC_IMPL_PART_BPMP_POWER_GATE_CONTROL_0_WORD_COUNT                      0x1
#define PMC_IMPL_PART_BPMP_POWER_GATE_CONTROL_0_RESET_VAL                       _MK_MASK_CONST(0x80000000)
#define PMC_IMPL_PART_BPMP_POWER_GATE_CONTROL_0_RESET_MASK                      _MK_MASK_CONST(0x80000107)
#define PMC_IMPL_PART_BPMP_POWER_GATE_CONTROL_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_BPMP_POWER_GATE_CONTROL_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_BPMP_POWER_GATE_CONTROL_0_READ_MASK                       _MK_MASK_CONST(0x80000107)
#define PMC_IMPL_PART_BPMP_POWER_GATE_CONTROL_0_WRITE_MASK                      _MK_MASK_CONST(0x80000107)
#define PMC_IMPL_PART_BPMP_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SHIFT                       _MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_BPMP_POWER_GATE_CONTROL_0_LOGIC_SLEEP_FIELD                       _MK_FIELD_CONST(0x1, PMC_IMPL_PART_BPMP_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SHIFT)
#define PMC_IMPL_PART_BPMP_POWER_GATE_CONTROL_0_LOGIC_SLEEP_RANGE                       0:0
#define PMC_IMPL_PART_BPMP_POWER_GATE_CONTROL_0_LOGIC_SLEEP_WOFFSET                     0x0
#define PMC_IMPL_PART_BPMP_POWER_GATE_CONTROL_0_LOGIC_SLEEP_DEFAULT                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_BPMP_POWER_GATE_CONTROL_0_LOGIC_SLEEP_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_BPMP_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_BPMP_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_BPMP_POWER_GATE_CONTROL_0_LOGIC_SLEEP_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_BPMP_POWER_GATE_CONTROL_0_LOGIC_SLEEP_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_BPMP_POWER_GATE_CONTROL_0_LOGIC_SLEEP_INIT_ENUM                   OFF
#define PMC_IMPL_PART_BPMP_POWER_GATE_CONTROL_0_LOGIC_SLEEP_OFF                 _MK_ENUM_CONST(0)
#define PMC_IMPL_PART_BPMP_POWER_GATE_CONTROL_0_LOGIC_SLEEP_ON                  _MK_ENUM_CONST(1)

#define PMC_IMPL_PART_BPMP_POWER_GATE_CONTROL_0_SRAM_RET_EN_SHIFT                       _MK_SHIFT_CONST(1)
#define PMC_IMPL_PART_BPMP_POWER_GATE_CONTROL_0_SRAM_RET_EN_FIELD                       _MK_FIELD_CONST(0x1, PMC_IMPL_PART_BPMP_POWER_GATE_CONTROL_0_SRAM_RET_EN_SHIFT)
#define PMC_IMPL_PART_BPMP_POWER_GATE_CONTROL_0_SRAM_RET_EN_RANGE                       1:1
#define PMC_IMPL_PART_BPMP_POWER_GATE_CONTROL_0_SRAM_RET_EN_WOFFSET                     0x0
#define PMC_IMPL_PART_BPMP_POWER_GATE_CONTROL_0_SRAM_RET_EN_DEFAULT                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_BPMP_POWER_GATE_CONTROL_0_SRAM_RET_EN_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_BPMP_POWER_GATE_CONTROL_0_SRAM_RET_EN_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_BPMP_POWER_GATE_CONTROL_0_SRAM_RET_EN_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_BPMP_POWER_GATE_CONTROL_0_SRAM_RET_EN_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_BPMP_POWER_GATE_CONTROL_0_SRAM_RET_EN_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_BPMP_POWER_GATE_CONTROL_0_SRAM_RET_EN_INIT_ENUM                   OFF
#define PMC_IMPL_PART_BPMP_POWER_GATE_CONTROL_0_SRAM_RET_EN_OFF                 _MK_ENUM_CONST(0)
#define PMC_IMPL_PART_BPMP_POWER_GATE_CONTROL_0_SRAM_RET_EN_ON                  _MK_ENUM_CONST(1)

#define PMC_IMPL_PART_BPMP_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SHIFT                     _MK_SHIFT_CONST(2)
#define PMC_IMPL_PART_BPMP_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_FIELD                     _MK_FIELD_CONST(0x1, PMC_IMPL_PART_BPMP_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SHIFT)
#define PMC_IMPL_PART_BPMP_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_RANGE                     2:2
#define PMC_IMPL_PART_BPMP_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_WOFFSET                   0x0
#define PMC_IMPL_PART_BPMP_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_DEFAULT                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_BPMP_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_BPMP_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_BPMP_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_BPMP_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_BPMP_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_BPMP_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_INIT_ENUM                 OFF
#define PMC_IMPL_PART_BPMP_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_OFF                       _MK_ENUM_CONST(0)
#define PMC_IMPL_PART_BPMP_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_ON                        _MK_ENUM_CONST(1)

#define PMC_IMPL_PART_BPMP_POWER_GATE_CONTROL_0_START_SHIFT                     _MK_SHIFT_CONST(8)
#define PMC_IMPL_PART_BPMP_POWER_GATE_CONTROL_0_START_FIELD                     _MK_FIELD_CONST(0x1, PMC_IMPL_PART_BPMP_POWER_GATE_CONTROL_0_START_SHIFT)
#define PMC_IMPL_PART_BPMP_POWER_GATE_CONTROL_0_START_RANGE                     8:8
#define PMC_IMPL_PART_BPMP_POWER_GATE_CONTROL_0_START_WOFFSET                   0x0
#define PMC_IMPL_PART_BPMP_POWER_GATE_CONTROL_0_START_DEFAULT                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_BPMP_POWER_GATE_CONTROL_0_START_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_BPMP_POWER_GATE_CONTROL_0_START_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_BPMP_POWER_GATE_CONTROL_0_START_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_BPMP_POWER_GATE_CONTROL_0_START_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_BPMP_POWER_GATE_CONTROL_0_START_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_BPMP_POWER_GATE_CONTROL_0_START_INIT_ENUM                 DONE
#define PMC_IMPL_PART_BPMP_POWER_GATE_CONTROL_0_START_DONE                      _MK_ENUM_CONST(0)
#define PMC_IMPL_PART_BPMP_POWER_GATE_CONTROL_0_START_PENDING                   _MK_ENUM_CONST(1)

#define PMC_IMPL_PART_BPMP_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SHIFT                       _MK_SHIFT_CONST(31)
#define PMC_IMPL_PART_BPMP_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_FIELD                       _MK_FIELD_CONST(0x1, PMC_IMPL_PART_BPMP_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SHIFT)
#define PMC_IMPL_PART_BPMP_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_RANGE                       31:31
#define PMC_IMPL_PART_BPMP_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_WOFFSET                     0x0
#define PMC_IMPL_PART_BPMP_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_DEFAULT                     _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_BPMP_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_BPMP_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_BPMP_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_BPMP_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_BPMP_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_BPMP_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_INIT_ENUM                   ENABLE
#define PMC_IMPL_PART_BPMP_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_DISABLE                     _MK_ENUM_CONST(0)
#define PMC_IMPL_PART_BPMP_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_ENABLE                      _MK_ENUM_CONST(1)


// Register PMC_IMPL_PART_BPMP_POWER_GATE_STATUS_0
#define PMC_IMPL_PART_BPMP_POWER_GATE_STATUS_0                  _MK_ADDR_CONST(0x374)
#define PMC_IMPL_PART_BPMP_POWER_GATE_STATUS_0_SECURE                   0x0
#define PMC_IMPL_PART_BPMP_POWER_GATE_STATUS_0_DUAL                     0x0
#define PMC_IMPL_PART_BPMP_POWER_GATE_STATUS_0_SCR                      PG_BPMP_SCR_0
#define PMC_IMPL_PART_BPMP_POWER_GATE_STATUS_0_WORD_COUNT                       0x1
#define PMC_IMPL_PART_BPMP_POWER_GATE_STATUS_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_BPMP_POWER_GATE_STATUS_0_RESET_MASK                       _MK_MASK_CONST(0x7)
#define PMC_IMPL_PART_BPMP_POWER_GATE_STATUS_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_BPMP_POWER_GATE_STATUS_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_BPMP_POWER_GATE_STATUS_0_READ_MASK                        _MK_MASK_CONST(0x7)
#define PMC_IMPL_PART_BPMP_POWER_GATE_STATUS_0_WRITE_MASK                       _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_BPMP_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SHIFT                    _MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_BPMP_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_FIELD                    _MK_FIELD_CONST(0x1, PMC_IMPL_PART_BPMP_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SHIFT)
#define PMC_IMPL_PART_BPMP_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_RANGE                    0:0
#define PMC_IMPL_PART_BPMP_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_WOFFSET                  0x0
#define PMC_IMPL_PART_BPMP_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_DEFAULT                  _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_BPMP_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_BPMP_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_BPMP_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_BPMP_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_BPMP_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_BPMP_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_INIT_ENUM                        OFF
#define PMC_IMPL_PART_BPMP_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_OFF                      _MK_ENUM_CONST(0)
#define PMC_IMPL_PART_BPMP_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_ON                       _MK_ENUM_CONST(1)

#define PMC_IMPL_PART_BPMP_POWER_GATE_STATUS_0_SRAM_RET_STS_SHIFT                       _MK_SHIFT_CONST(1)
#define PMC_IMPL_PART_BPMP_POWER_GATE_STATUS_0_SRAM_RET_STS_FIELD                       _MK_FIELD_CONST(0x1, PMC_IMPL_PART_BPMP_POWER_GATE_STATUS_0_SRAM_RET_STS_SHIFT)
#define PMC_IMPL_PART_BPMP_POWER_GATE_STATUS_0_SRAM_RET_STS_RANGE                       1:1
#define PMC_IMPL_PART_BPMP_POWER_GATE_STATUS_0_SRAM_RET_STS_WOFFSET                     0x0
#define PMC_IMPL_PART_BPMP_POWER_GATE_STATUS_0_SRAM_RET_STS_DEFAULT                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_BPMP_POWER_GATE_STATUS_0_SRAM_RET_STS_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_BPMP_POWER_GATE_STATUS_0_SRAM_RET_STS_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_BPMP_POWER_GATE_STATUS_0_SRAM_RET_STS_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_BPMP_POWER_GATE_STATUS_0_SRAM_RET_STS_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_BPMP_POWER_GATE_STATUS_0_SRAM_RET_STS_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_BPMP_POWER_GATE_STATUS_0_SRAM_RET_STS_INIT_ENUM                   OFF
#define PMC_IMPL_PART_BPMP_POWER_GATE_STATUS_0_SRAM_RET_STS_OFF                 _MK_ENUM_CONST(0)
#define PMC_IMPL_PART_BPMP_POWER_GATE_STATUS_0_SRAM_RET_STS_ON                  _MK_ENUM_CONST(1)

#define PMC_IMPL_PART_BPMP_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SHIFT                     _MK_SHIFT_CONST(2)
#define PMC_IMPL_PART_BPMP_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_FIELD                     _MK_FIELD_CONST(0x1, PMC_IMPL_PART_BPMP_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SHIFT)
#define PMC_IMPL_PART_BPMP_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_RANGE                     2:2
#define PMC_IMPL_PART_BPMP_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_WOFFSET                   0x0
#define PMC_IMPL_PART_BPMP_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_DEFAULT                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_BPMP_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_BPMP_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_BPMP_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_BPMP_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_BPMP_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_BPMP_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_INIT_ENUM                 OFF
#define PMC_IMPL_PART_BPMP_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_OFF                       _MK_ENUM_CONST(0)
#define PMC_IMPL_PART_BPMP_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_ON                        _MK_ENUM_CONST(1)


// Register PMC_IMPL_PART_BPMP_CLAMP_CONTROL_0
#define PMC_IMPL_PART_BPMP_CLAMP_CONTROL_0                      _MK_ADDR_CONST(0x378)
#define PMC_IMPL_PART_BPMP_CLAMP_CONTROL_0_SECURE                       0x0
#define PMC_IMPL_PART_BPMP_CLAMP_CONTROL_0_DUAL                         0x0
#define PMC_IMPL_PART_BPMP_CLAMP_CONTROL_0_SCR                  PG_BPMP_SCR_0
#define PMC_IMPL_PART_BPMP_CLAMP_CONTROL_0_WORD_COUNT                   0x1
#define PMC_IMPL_PART_BPMP_CLAMP_CONTROL_0_RESET_VAL                    _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_BPMP_CLAMP_CONTROL_0_RESET_MASK                   _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_BPMP_CLAMP_CONTROL_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_BPMP_CLAMP_CONTROL_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_BPMP_CLAMP_CONTROL_0_READ_MASK                    _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_BPMP_CLAMP_CONTROL_0_WRITE_MASK                   _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_BPMP_CLAMP_CONTROL_0_CLAMP_SHIFT                  _MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_BPMP_CLAMP_CONTROL_0_CLAMP_FIELD                  _MK_FIELD_CONST(0x1, PMC_IMPL_PART_BPMP_CLAMP_CONTROL_0_CLAMP_SHIFT)
#define PMC_IMPL_PART_BPMP_CLAMP_CONTROL_0_CLAMP_RANGE                  0:0
#define PMC_IMPL_PART_BPMP_CLAMP_CONTROL_0_CLAMP_WOFFSET                        0x0
#define PMC_IMPL_PART_BPMP_CLAMP_CONTROL_0_CLAMP_DEFAULT                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_BPMP_CLAMP_CONTROL_0_CLAMP_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_BPMP_CLAMP_CONTROL_0_CLAMP_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_BPMP_CLAMP_CONTROL_0_CLAMP_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_BPMP_CLAMP_CONTROL_0_CLAMP_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_BPMP_CLAMP_CONTROL_0_CLAMP_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_BPMP_CLAMP_CONTROL_0_CLAMP_INIT_ENUM                      OFF
#define PMC_IMPL_PART_BPMP_CLAMP_CONTROL_0_CLAMP_OFF                    _MK_ENUM_CONST(0)
#define PMC_IMPL_PART_BPMP_CLAMP_CONTROL_0_CLAMP_ON                     _MK_ENUM_CONST(1)


// Register PMC_IMPL_PART_SCE_POWER_GATE_CONTROL_0
#define PMC_IMPL_PART_SCE_POWER_GATE_CONTROL_0                  _MK_ADDR_CONST(0x37c)
#define PMC_IMPL_PART_SCE_POWER_GATE_CONTROL_0_SECURE                   0x0
#define PMC_IMPL_PART_SCE_POWER_GATE_CONTROL_0_DUAL                     0x0
#define PMC_IMPL_PART_SCE_POWER_GATE_CONTROL_0_SCR                      PG_SCE_SCR_0
#define PMC_IMPL_PART_SCE_POWER_GATE_CONTROL_0_WORD_COUNT                       0x1
#define PMC_IMPL_PART_SCE_POWER_GATE_CONTROL_0_RESET_VAL                        _MK_MASK_CONST(0x80000000)
#define PMC_IMPL_PART_SCE_POWER_GATE_CONTROL_0_RESET_MASK                       _MK_MASK_CONST(0x80000107)
#define PMC_IMPL_PART_SCE_POWER_GATE_CONTROL_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_SCE_POWER_GATE_CONTROL_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_SCE_POWER_GATE_CONTROL_0_READ_MASK                        _MK_MASK_CONST(0x80000107)
#define PMC_IMPL_PART_SCE_POWER_GATE_CONTROL_0_WRITE_MASK                       _MK_MASK_CONST(0x80000107)
#define PMC_IMPL_PART_SCE_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SHIFT                        _MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_SCE_POWER_GATE_CONTROL_0_LOGIC_SLEEP_FIELD                        _MK_FIELD_CONST(0x1, PMC_IMPL_PART_SCE_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SHIFT)
#define PMC_IMPL_PART_SCE_POWER_GATE_CONTROL_0_LOGIC_SLEEP_RANGE                        0:0
#define PMC_IMPL_PART_SCE_POWER_GATE_CONTROL_0_LOGIC_SLEEP_WOFFSET                      0x0
#define PMC_IMPL_PART_SCE_POWER_GATE_CONTROL_0_LOGIC_SLEEP_DEFAULT                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_SCE_POWER_GATE_CONTROL_0_LOGIC_SLEEP_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_SCE_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_SCE_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_SCE_POWER_GATE_CONTROL_0_LOGIC_SLEEP_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_SCE_POWER_GATE_CONTROL_0_LOGIC_SLEEP_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_SCE_POWER_GATE_CONTROL_0_LOGIC_SLEEP_INIT_ENUM                    OFF
#define PMC_IMPL_PART_SCE_POWER_GATE_CONTROL_0_LOGIC_SLEEP_OFF                  _MK_ENUM_CONST(0)
#define PMC_IMPL_PART_SCE_POWER_GATE_CONTROL_0_LOGIC_SLEEP_ON                   _MK_ENUM_CONST(1)

#define PMC_IMPL_PART_SCE_POWER_GATE_CONTROL_0_SRAM_RET_EN_SHIFT                        _MK_SHIFT_CONST(1)
#define PMC_IMPL_PART_SCE_POWER_GATE_CONTROL_0_SRAM_RET_EN_FIELD                        _MK_FIELD_CONST(0x1, PMC_IMPL_PART_SCE_POWER_GATE_CONTROL_0_SRAM_RET_EN_SHIFT)
#define PMC_IMPL_PART_SCE_POWER_GATE_CONTROL_0_SRAM_RET_EN_RANGE                        1:1
#define PMC_IMPL_PART_SCE_POWER_GATE_CONTROL_0_SRAM_RET_EN_WOFFSET                      0x0
#define PMC_IMPL_PART_SCE_POWER_GATE_CONTROL_0_SRAM_RET_EN_DEFAULT                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_SCE_POWER_GATE_CONTROL_0_SRAM_RET_EN_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_SCE_POWER_GATE_CONTROL_0_SRAM_RET_EN_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_SCE_POWER_GATE_CONTROL_0_SRAM_RET_EN_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_SCE_POWER_GATE_CONTROL_0_SRAM_RET_EN_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_SCE_POWER_GATE_CONTROL_0_SRAM_RET_EN_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_SCE_POWER_GATE_CONTROL_0_SRAM_RET_EN_INIT_ENUM                    OFF
#define PMC_IMPL_PART_SCE_POWER_GATE_CONTROL_0_SRAM_RET_EN_OFF                  _MK_ENUM_CONST(0)
#define PMC_IMPL_PART_SCE_POWER_GATE_CONTROL_0_SRAM_RET_EN_ON                   _MK_ENUM_CONST(1)

#define PMC_IMPL_PART_SCE_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SHIFT                      _MK_SHIFT_CONST(2)
#define PMC_IMPL_PART_SCE_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_FIELD                      _MK_FIELD_CONST(0x1, PMC_IMPL_PART_SCE_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SHIFT)
#define PMC_IMPL_PART_SCE_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_RANGE                      2:2
#define PMC_IMPL_PART_SCE_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_WOFFSET                    0x0
#define PMC_IMPL_PART_SCE_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_DEFAULT                    _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_SCE_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_SCE_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_SCE_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_SCE_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_SCE_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_SCE_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_INIT_ENUM                  OFF
#define PMC_IMPL_PART_SCE_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_OFF                        _MK_ENUM_CONST(0)
#define PMC_IMPL_PART_SCE_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_ON                 _MK_ENUM_CONST(1)

#define PMC_IMPL_PART_SCE_POWER_GATE_CONTROL_0_START_SHIFT                      _MK_SHIFT_CONST(8)
#define PMC_IMPL_PART_SCE_POWER_GATE_CONTROL_0_START_FIELD                      _MK_FIELD_CONST(0x1, PMC_IMPL_PART_SCE_POWER_GATE_CONTROL_0_START_SHIFT)
#define PMC_IMPL_PART_SCE_POWER_GATE_CONTROL_0_START_RANGE                      8:8
#define PMC_IMPL_PART_SCE_POWER_GATE_CONTROL_0_START_WOFFSET                    0x0
#define PMC_IMPL_PART_SCE_POWER_GATE_CONTROL_0_START_DEFAULT                    _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_SCE_POWER_GATE_CONTROL_0_START_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_SCE_POWER_GATE_CONTROL_0_START_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_SCE_POWER_GATE_CONTROL_0_START_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_SCE_POWER_GATE_CONTROL_0_START_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_SCE_POWER_GATE_CONTROL_0_START_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_SCE_POWER_GATE_CONTROL_0_START_INIT_ENUM                  DONE
#define PMC_IMPL_PART_SCE_POWER_GATE_CONTROL_0_START_DONE                       _MK_ENUM_CONST(0)
#define PMC_IMPL_PART_SCE_POWER_GATE_CONTROL_0_START_PENDING                    _MK_ENUM_CONST(1)

#define PMC_IMPL_PART_SCE_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SHIFT                        _MK_SHIFT_CONST(31)
#define PMC_IMPL_PART_SCE_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_FIELD                        _MK_FIELD_CONST(0x1, PMC_IMPL_PART_SCE_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SHIFT)
#define PMC_IMPL_PART_SCE_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_RANGE                        31:31
#define PMC_IMPL_PART_SCE_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_WOFFSET                      0x0
#define PMC_IMPL_PART_SCE_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_DEFAULT                      _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_SCE_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_SCE_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_SCE_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_SCE_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_SCE_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_SCE_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_INIT_ENUM                    ENABLE
#define PMC_IMPL_PART_SCE_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_DISABLE                      _MK_ENUM_CONST(0)
#define PMC_IMPL_PART_SCE_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_ENABLE                       _MK_ENUM_CONST(1)


// Register PMC_IMPL_PART_SCE_POWER_GATE_STATUS_0
#define PMC_IMPL_PART_SCE_POWER_GATE_STATUS_0                   _MK_ADDR_CONST(0x380)
#define PMC_IMPL_PART_SCE_POWER_GATE_STATUS_0_SECURE                    0x0
#define PMC_IMPL_PART_SCE_POWER_GATE_STATUS_0_DUAL                      0x0
#define PMC_IMPL_PART_SCE_POWER_GATE_STATUS_0_SCR                       PG_SCE_SCR_0
#define PMC_IMPL_PART_SCE_POWER_GATE_STATUS_0_WORD_COUNT                        0x1
#define PMC_IMPL_PART_SCE_POWER_GATE_STATUS_0_RESET_VAL                         _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_SCE_POWER_GATE_STATUS_0_RESET_MASK                        _MK_MASK_CONST(0x7)
#define PMC_IMPL_PART_SCE_POWER_GATE_STATUS_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_SCE_POWER_GATE_STATUS_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_SCE_POWER_GATE_STATUS_0_READ_MASK                         _MK_MASK_CONST(0x7)
#define PMC_IMPL_PART_SCE_POWER_GATE_STATUS_0_WRITE_MASK                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_SCE_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SHIFT                     _MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_SCE_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_FIELD                     _MK_FIELD_CONST(0x1, PMC_IMPL_PART_SCE_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SHIFT)
#define PMC_IMPL_PART_SCE_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_RANGE                     0:0
#define PMC_IMPL_PART_SCE_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_WOFFSET                   0x0
#define PMC_IMPL_PART_SCE_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_DEFAULT                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_SCE_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_SCE_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_SCE_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_SCE_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_SCE_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_SCE_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_INIT_ENUM                 OFF
#define PMC_IMPL_PART_SCE_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_OFF                       _MK_ENUM_CONST(0)
#define PMC_IMPL_PART_SCE_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_ON                        _MK_ENUM_CONST(1)

#define PMC_IMPL_PART_SCE_POWER_GATE_STATUS_0_SRAM_RET_STS_SHIFT                        _MK_SHIFT_CONST(1)
#define PMC_IMPL_PART_SCE_POWER_GATE_STATUS_0_SRAM_RET_STS_FIELD                        _MK_FIELD_CONST(0x1, PMC_IMPL_PART_SCE_POWER_GATE_STATUS_0_SRAM_RET_STS_SHIFT)
#define PMC_IMPL_PART_SCE_POWER_GATE_STATUS_0_SRAM_RET_STS_RANGE                        1:1
#define PMC_IMPL_PART_SCE_POWER_GATE_STATUS_0_SRAM_RET_STS_WOFFSET                      0x0
#define PMC_IMPL_PART_SCE_POWER_GATE_STATUS_0_SRAM_RET_STS_DEFAULT                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_SCE_POWER_GATE_STATUS_0_SRAM_RET_STS_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_SCE_POWER_GATE_STATUS_0_SRAM_RET_STS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_SCE_POWER_GATE_STATUS_0_SRAM_RET_STS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_SCE_POWER_GATE_STATUS_0_SRAM_RET_STS_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_SCE_POWER_GATE_STATUS_0_SRAM_RET_STS_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_SCE_POWER_GATE_STATUS_0_SRAM_RET_STS_INIT_ENUM                    OFF
#define PMC_IMPL_PART_SCE_POWER_GATE_STATUS_0_SRAM_RET_STS_OFF                  _MK_ENUM_CONST(0)
#define PMC_IMPL_PART_SCE_POWER_GATE_STATUS_0_SRAM_RET_STS_ON                   _MK_ENUM_CONST(1)

#define PMC_IMPL_PART_SCE_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SHIFT                      _MK_SHIFT_CONST(2)
#define PMC_IMPL_PART_SCE_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_FIELD                      _MK_FIELD_CONST(0x1, PMC_IMPL_PART_SCE_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SHIFT)
#define PMC_IMPL_PART_SCE_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_RANGE                      2:2
#define PMC_IMPL_PART_SCE_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_WOFFSET                    0x0
#define PMC_IMPL_PART_SCE_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_DEFAULT                    _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_SCE_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_SCE_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_SCE_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_SCE_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_SCE_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_SCE_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_INIT_ENUM                  OFF
#define PMC_IMPL_PART_SCE_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_OFF                        _MK_ENUM_CONST(0)
#define PMC_IMPL_PART_SCE_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_ON                 _MK_ENUM_CONST(1)


// Register PMC_IMPL_PART_SCE_CLAMP_CONTROL_0
#define PMC_IMPL_PART_SCE_CLAMP_CONTROL_0                       _MK_ADDR_CONST(0x384)
#define PMC_IMPL_PART_SCE_CLAMP_CONTROL_0_SECURE                        0x0
#define PMC_IMPL_PART_SCE_CLAMP_CONTROL_0_DUAL                  0x0
#define PMC_IMPL_PART_SCE_CLAMP_CONTROL_0_SCR                   PG_SCE_SCR_0
#define PMC_IMPL_PART_SCE_CLAMP_CONTROL_0_WORD_COUNT                    0x1
#define PMC_IMPL_PART_SCE_CLAMP_CONTROL_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_SCE_CLAMP_CONTROL_0_RESET_MASK                    _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_SCE_CLAMP_CONTROL_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_SCE_CLAMP_CONTROL_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_SCE_CLAMP_CONTROL_0_READ_MASK                     _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_SCE_CLAMP_CONTROL_0_WRITE_MASK                    _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_SCE_CLAMP_CONTROL_0_CLAMP_SHIFT                   _MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_SCE_CLAMP_CONTROL_0_CLAMP_FIELD                   _MK_FIELD_CONST(0x1, PMC_IMPL_PART_SCE_CLAMP_CONTROL_0_CLAMP_SHIFT)
#define PMC_IMPL_PART_SCE_CLAMP_CONTROL_0_CLAMP_RANGE                   0:0
#define PMC_IMPL_PART_SCE_CLAMP_CONTROL_0_CLAMP_WOFFSET                 0x0
#define PMC_IMPL_PART_SCE_CLAMP_CONTROL_0_CLAMP_DEFAULT                 _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_SCE_CLAMP_CONTROL_0_CLAMP_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_SCE_CLAMP_CONTROL_0_CLAMP_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_SCE_CLAMP_CONTROL_0_CLAMP_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_SCE_CLAMP_CONTROL_0_CLAMP_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_SCE_CLAMP_CONTROL_0_CLAMP_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_SCE_CLAMP_CONTROL_0_CLAMP_INIT_ENUM                       OFF
#define PMC_IMPL_PART_SCE_CLAMP_CONTROL_0_CLAMP_OFF                     _MK_ENUM_CONST(0)
#define PMC_IMPL_PART_SCE_CLAMP_CONTROL_0_CLAMP_ON                      _MK_ENUM_CONST(1)


// Register PMC_IMPL_PART_AOPG_TCM0_POWER_GATE_CONTROL_0
#define PMC_IMPL_PART_AOPG_TCM0_POWER_GATE_CONTROL_0                    _MK_ADDR_CONST(0x388)
#define PMC_IMPL_PART_AOPG_TCM0_POWER_GATE_CONTROL_0_SECURE                     0x0
#define PMC_IMPL_PART_AOPG_TCM0_POWER_GATE_CONTROL_0_DUAL                       0x0
#define PMC_IMPL_PART_AOPG_TCM0_POWER_GATE_CONTROL_0_SCR                        PG_AOPG_TCM0_SCR_0
#define PMC_IMPL_PART_AOPG_TCM0_POWER_GATE_CONTROL_0_WORD_COUNT                         0x1
#define PMC_IMPL_PART_AOPG_TCM0_POWER_GATE_CONTROL_0_RESET_VAL                  _MK_MASK_CONST(0x80000000)
#define PMC_IMPL_PART_AOPG_TCM0_POWER_GATE_CONTROL_0_RESET_MASK                         _MK_MASK_CONST(0x80000107)
#define PMC_IMPL_PART_AOPG_TCM0_POWER_GATE_CONTROL_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM0_POWER_GATE_CONTROL_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM0_POWER_GATE_CONTROL_0_READ_MASK                  _MK_MASK_CONST(0x80000107)
#define PMC_IMPL_PART_AOPG_TCM0_POWER_GATE_CONTROL_0_WRITE_MASK                         _MK_MASK_CONST(0x80000107)
#define PMC_IMPL_PART_AOPG_TCM0_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SHIFT                  _MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_AOPG_TCM0_POWER_GATE_CONTROL_0_LOGIC_SLEEP_FIELD                  _MK_FIELD_CONST(0x1, PMC_IMPL_PART_AOPG_TCM0_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SHIFT)
#define PMC_IMPL_PART_AOPG_TCM0_POWER_GATE_CONTROL_0_LOGIC_SLEEP_RANGE                  0:0
#define PMC_IMPL_PART_AOPG_TCM0_POWER_GATE_CONTROL_0_LOGIC_SLEEP_WOFFSET                        0x0
#define PMC_IMPL_PART_AOPG_TCM0_POWER_GATE_CONTROL_0_LOGIC_SLEEP_DEFAULT                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM0_POWER_GATE_CONTROL_0_LOGIC_SLEEP_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AOPG_TCM0_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM0_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM0_POWER_GATE_CONTROL_0_LOGIC_SLEEP_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM0_POWER_GATE_CONTROL_0_LOGIC_SLEEP_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AOPG_TCM0_POWER_GATE_CONTROL_0_LOGIC_SLEEP_INIT_ENUM                      OFF
#define PMC_IMPL_PART_AOPG_TCM0_POWER_GATE_CONTROL_0_LOGIC_SLEEP_OFF                    _MK_ENUM_CONST(0)
#define PMC_IMPL_PART_AOPG_TCM0_POWER_GATE_CONTROL_0_LOGIC_SLEEP_ON                     _MK_ENUM_CONST(1)

#define PMC_IMPL_PART_AOPG_TCM0_POWER_GATE_CONTROL_0_SRAM_RET_EN_SHIFT                  _MK_SHIFT_CONST(1)
#define PMC_IMPL_PART_AOPG_TCM0_POWER_GATE_CONTROL_0_SRAM_RET_EN_FIELD                  _MK_FIELD_CONST(0x1, PMC_IMPL_PART_AOPG_TCM0_POWER_GATE_CONTROL_0_SRAM_RET_EN_SHIFT)
#define PMC_IMPL_PART_AOPG_TCM0_POWER_GATE_CONTROL_0_SRAM_RET_EN_RANGE                  1:1
#define PMC_IMPL_PART_AOPG_TCM0_POWER_GATE_CONTROL_0_SRAM_RET_EN_WOFFSET                        0x0
#define PMC_IMPL_PART_AOPG_TCM0_POWER_GATE_CONTROL_0_SRAM_RET_EN_DEFAULT                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM0_POWER_GATE_CONTROL_0_SRAM_RET_EN_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AOPG_TCM0_POWER_GATE_CONTROL_0_SRAM_RET_EN_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM0_POWER_GATE_CONTROL_0_SRAM_RET_EN_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM0_POWER_GATE_CONTROL_0_SRAM_RET_EN_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM0_POWER_GATE_CONTROL_0_SRAM_RET_EN_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AOPG_TCM0_POWER_GATE_CONTROL_0_SRAM_RET_EN_INIT_ENUM                      OFF
#define PMC_IMPL_PART_AOPG_TCM0_POWER_GATE_CONTROL_0_SRAM_RET_EN_OFF                    _MK_ENUM_CONST(0)
#define PMC_IMPL_PART_AOPG_TCM0_POWER_GATE_CONTROL_0_SRAM_RET_EN_ON                     _MK_ENUM_CONST(1)

#define PMC_IMPL_PART_AOPG_TCM0_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SHIFT                        _MK_SHIFT_CONST(2)
#define PMC_IMPL_PART_AOPG_TCM0_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_FIELD                        _MK_FIELD_CONST(0x1, PMC_IMPL_PART_AOPG_TCM0_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SHIFT)
#define PMC_IMPL_PART_AOPG_TCM0_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_RANGE                        2:2
#define PMC_IMPL_PART_AOPG_TCM0_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_WOFFSET                      0x0
#define PMC_IMPL_PART_AOPG_TCM0_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_DEFAULT                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM0_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AOPG_TCM0_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM0_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM0_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM0_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AOPG_TCM0_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_INIT_ENUM                    OFF
#define PMC_IMPL_PART_AOPG_TCM0_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_OFF                  _MK_ENUM_CONST(0)
#define PMC_IMPL_PART_AOPG_TCM0_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_ON                   _MK_ENUM_CONST(1)

#define PMC_IMPL_PART_AOPG_TCM0_POWER_GATE_CONTROL_0_START_SHIFT                        _MK_SHIFT_CONST(8)
#define PMC_IMPL_PART_AOPG_TCM0_POWER_GATE_CONTROL_0_START_FIELD                        _MK_FIELD_CONST(0x1, PMC_IMPL_PART_AOPG_TCM0_POWER_GATE_CONTROL_0_START_SHIFT)
#define PMC_IMPL_PART_AOPG_TCM0_POWER_GATE_CONTROL_0_START_RANGE                        8:8
#define PMC_IMPL_PART_AOPG_TCM0_POWER_GATE_CONTROL_0_START_WOFFSET                      0x0
#define PMC_IMPL_PART_AOPG_TCM0_POWER_GATE_CONTROL_0_START_DEFAULT                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM0_POWER_GATE_CONTROL_0_START_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AOPG_TCM0_POWER_GATE_CONTROL_0_START_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM0_POWER_GATE_CONTROL_0_START_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM0_POWER_GATE_CONTROL_0_START_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM0_POWER_GATE_CONTROL_0_START_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AOPG_TCM0_POWER_GATE_CONTROL_0_START_INIT_ENUM                    DONE
#define PMC_IMPL_PART_AOPG_TCM0_POWER_GATE_CONTROL_0_START_DONE                 _MK_ENUM_CONST(0)
#define PMC_IMPL_PART_AOPG_TCM0_POWER_GATE_CONTROL_0_START_PENDING                      _MK_ENUM_CONST(1)

#define PMC_IMPL_PART_AOPG_TCM0_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SHIFT                  _MK_SHIFT_CONST(31)
#define PMC_IMPL_PART_AOPG_TCM0_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_FIELD                  _MK_FIELD_CONST(0x1, PMC_IMPL_PART_AOPG_TCM0_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SHIFT)
#define PMC_IMPL_PART_AOPG_TCM0_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_RANGE                  31:31
#define PMC_IMPL_PART_AOPG_TCM0_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_WOFFSET                        0x0
#define PMC_IMPL_PART_AOPG_TCM0_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_DEFAULT                        _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AOPG_TCM0_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AOPG_TCM0_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM0_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM0_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM0_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AOPG_TCM0_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_INIT_ENUM                      ENABLE
#define PMC_IMPL_PART_AOPG_TCM0_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_DISABLE                        _MK_ENUM_CONST(0)
#define PMC_IMPL_PART_AOPG_TCM0_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_ENABLE                 _MK_ENUM_CONST(1)


// Register PMC_IMPL_PART_AOPG_TCM0_POWER_GATE_STATUS_0
#define PMC_IMPL_PART_AOPG_TCM0_POWER_GATE_STATUS_0                     _MK_ADDR_CONST(0x38c)
#define PMC_IMPL_PART_AOPG_TCM0_POWER_GATE_STATUS_0_SECURE                      0x0
#define PMC_IMPL_PART_AOPG_TCM0_POWER_GATE_STATUS_0_DUAL                        0x0
#define PMC_IMPL_PART_AOPG_TCM0_POWER_GATE_STATUS_0_SCR                         PG_AOPG_TCM0_SCR_0
#define PMC_IMPL_PART_AOPG_TCM0_POWER_GATE_STATUS_0_WORD_COUNT                  0x1
#define PMC_IMPL_PART_AOPG_TCM0_POWER_GATE_STATUS_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM0_POWER_GATE_STATUS_0_RESET_MASK                  _MK_MASK_CONST(0x7)
#define PMC_IMPL_PART_AOPG_TCM0_POWER_GATE_STATUS_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM0_POWER_GATE_STATUS_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM0_POWER_GATE_STATUS_0_READ_MASK                   _MK_MASK_CONST(0x7)
#define PMC_IMPL_PART_AOPG_TCM0_POWER_GATE_STATUS_0_WRITE_MASK                  _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM0_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SHIFT                       _MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_AOPG_TCM0_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_FIELD                       _MK_FIELD_CONST(0x1, PMC_IMPL_PART_AOPG_TCM0_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SHIFT)
#define PMC_IMPL_PART_AOPG_TCM0_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_RANGE                       0:0
#define PMC_IMPL_PART_AOPG_TCM0_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_WOFFSET                     0x0
#define PMC_IMPL_PART_AOPG_TCM0_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_DEFAULT                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM0_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AOPG_TCM0_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM0_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM0_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM0_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AOPG_TCM0_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_INIT_ENUM                   OFF
#define PMC_IMPL_PART_AOPG_TCM0_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_OFF                 _MK_ENUM_CONST(0)
#define PMC_IMPL_PART_AOPG_TCM0_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_ON                  _MK_ENUM_CONST(1)

#define PMC_IMPL_PART_AOPG_TCM0_POWER_GATE_STATUS_0_SRAM_RET_STS_SHIFT                  _MK_SHIFT_CONST(1)
#define PMC_IMPL_PART_AOPG_TCM0_POWER_GATE_STATUS_0_SRAM_RET_STS_FIELD                  _MK_FIELD_CONST(0x1, PMC_IMPL_PART_AOPG_TCM0_POWER_GATE_STATUS_0_SRAM_RET_STS_SHIFT)
#define PMC_IMPL_PART_AOPG_TCM0_POWER_GATE_STATUS_0_SRAM_RET_STS_RANGE                  1:1
#define PMC_IMPL_PART_AOPG_TCM0_POWER_GATE_STATUS_0_SRAM_RET_STS_WOFFSET                        0x0
#define PMC_IMPL_PART_AOPG_TCM0_POWER_GATE_STATUS_0_SRAM_RET_STS_DEFAULT                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM0_POWER_GATE_STATUS_0_SRAM_RET_STS_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AOPG_TCM0_POWER_GATE_STATUS_0_SRAM_RET_STS_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM0_POWER_GATE_STATUS_0_SRAM_RET_STS_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM0_POWER_GATE_STATUS_0_SRAM_RET_STS_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM0_POWER_GATE_STATUS_0_SRAM_RET_STS_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AOPG_TCM0_POWER_GATE_STATUS_0_SRAM_RET_STS_INIT_ENUM                      OFF
#define PMC_IMPL_PART_AOPG_TCM0_POWER_GATE_STATUS_0_SRAM_RET_STS_OFF                    _MK_ENUM_CONST(0)
#define PMC_IMPL_PART_AOPG_TCM0_POWER_GATE_STATUS_0_SRAM_RET_STS_ON                     _MK_ENUM_CONST(1)

#define PMC_IMPL_PART_AOPG_TCM0_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SHIFT                        _MK_SHIFT_CONST(2)
#define PMC_IMPL_PART_AOPG_TCM0_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_FIELD                        _MK_FIELD_CONST(0x1, PMC_IMPL_PART_AOPG_TCM0_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SHIFT)
#define PMC_IMPL_PART_AOPG_TCM0_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_RANGE                        2:2
#define PMC_IMPL_PART_AOPG_TCM0_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_WOFFSET                      0x0
#define PMC_IMPL_PART_AOPG_TCM0_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_DEFAULT                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM0_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AOPG_TCM0_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM0_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM0_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM0_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AOPG_TCM0_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_INIT_ENUM                    OFF
#define PMC_IMPL_PART_AOPG_TCM0_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_OFF                  _MK_ENUM_CONST(0)
#define PMC_IMPL_PART_AOPG_TCM0_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_ON                   _MK_ENUM_CONST(1)


// Register PMC_IMPL_PART_AOPG_TCM0_CLAMP_CONTROL_0
#define PMC_IMPL_PART_AOPG_TCM0_CLAMP_CONTROL_0                 _MK_ADDR_CONST(0x390)
#define PMC_IMPL_PART_AOPG_TCM0_CLAMP_CONTROL_0_SECURE                  0x0
#define PMC_IMPL_PART_AOPG_TCM0_CLAMP_CONTROL_0_DUAL                    0x0
#define PMC_IMPL_PART_AOPG_TCM0_CLAMP_CONTROL_0_SCR                     PG_AOPG_TCM0_SCR_0
#define PMC_IMPL_PART_AOPG_TCM0_CLAMP_CONTROL_0_WORD_COUNT                      0x1
#define PMC_IMPL_PART_AOPG_TCM0_CLAMP_CONTROL_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM0_CLAMP_CONTROL_0_RESET_MASK                      _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AOPG_TCM0_CLAMP_CONTROL_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM0_CLAMP_CONTROL_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM0_CLAMP_CONTROL_0_READ_MASK                       _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AOPG_TCM0_CLAMP_CONTROL_0_WRITE_MASK                      _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AOPG_TCM0_CLAMP_CONTROL_0_CLAMP_SHIFT                     _MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_AOPG_TCM0_CLAMP_CONTROL_0_CLAMP_FIELD                     _MK_FIELD_CONST(0x1, PMC_IMPL_PART_AOPG_TCM0_CLAMP_CONTROL_0_CLAMP_SHIFT)
#define PMC_IMPL_PART_AOPG_TCM0_CLAMP_CONTROL_0_CLAMP_RANGE                     0:0
#define PMC_IMPL_PART_AOPG_TCM0_CLAMP_CONTROL_0_CLAMP_WOFFSET                   0x0
#define PMC_IMPL_PART_AOPG_TCM0_CLAMP_CONTROL_0_CLAMP_DEFAULT                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM0_CLAMP_CONTROL_0_CLAMP_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AOPG_TCM0_CLAMP_CONTROL_0_CLAMP_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM0_CLAMP_CONTROL_0_CLAMP_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM0_CLAMP_CONTROL_0_CLAMP_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM0_CLAMP_CONTROL_0_CLAMP_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AOPG_TCM0_CLAMP_CONTROL_0_CLAMP_INIT_ENUM                 OFF
#define PMC_IMPL_PART_AOPG_TCM0_CLAMP_CONTROL_0_CLAMP_OFF                       _MK_ENUM_CONST(0)
#define PMC_IMPL_PART_AOPG_TCM0_CLAMP_CONTROL_0_CLAMP_ON                        _MK_ENUM_CONST(1)


// Register PMC_IMPL_PART_AOPG_TCM1_POWER_GATE_CONTROL_0
#define PMC_IMPL_PART_AOPG_TCM1_POWER_GATE_CONTROL_0                    _MK_ADDR_CONST(0x394)
#define PMC_IMPL_PART_AOPG_TCM1_POWER_GATE_CONTROL_0_SECURE                     0x0
#define PMC_IMPL_PART_AOPG_TCM1_POWER_GATE_CONTROL_0_DUAL                       0x0
#define PMC_IMPL_PART_AOPG_TCM1_POWER_GATE_CONTROL_0_SCR                        PG_AOPG_TCM1_SCR_0
#define PMC_IMPL_PART_AOPG_TCM1_POWER_GATE_CONTROL_0_WORD_COUNT                         0x1
#define PMC_IMPL_PART_AOPG_TCM1_POWER_GATE_CONTROL_0_RESET_VAL                  _MK_MASK_CONST(0x80000000)
#define PMC_IMPL_PART_AOPG_TCM1_POWER_GATE_CONTROL_0_RESET_MASK                         _MK_MASK_CONST(0x80000107)
#define PMC_IMPL_PART_AOPG_TCM1_POWER_GATE_CONTROL_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM1_POWER_GATE_CONTROL_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM1_POWER_GATE_CONTROL_0_READ_MASK                  _MK_MASK_CONST(0x80000107)
#define PMC_IMPL_PART_AOPG_TCM1_POWER_GATE_CONTROL_0_WRITE_MASK                         _MK_MASK_CONST(0x80000107)
#define PMC_IMPL_PART_AOPG_TCM1_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SHIFT                  _MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_AOPG_TCM1_POWER_GATE_CONTROL_0_LOGIC_SLEEP_FIELD                  _MK_FIELD_CONST(0x1, PMC_IMPL_PART_AOPG_TCM1_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SHIFT)
#define PMC_IMPL_PART_AOPG_TCM1_POWER_GATE_CONTROL_0_LOGIC_SLEEP_RANGE                  0:0
#define PMC_IMPL_PART_AOPG_TCM1_POWER_GATE_CONTROL_0_LOGIC_SLEEP_WOFFSET                        0x0
#define PMC_IMPL_PART_AOPG_TCM1_POWER_GATE_CONTROL_0_LOGIC_SLEEP_DEFAULT                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM1_POWER_GATE_CONTROL_0_LOGIC_SLEEP_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AOPG_TCM1_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM1_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM1_POWER_GATE_CONTROL_0_LOGIC_SLEEP_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM1_POWER_GATE_CONTROL_0_LOGIC_SLEEP_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AOPG_TCM1_POWER_GATE_CONTROL_0_LOGIC_SLEEP_INIT_ENUM                      OFF
#define PMC_IMPL_PART_AOPG_TCM1_POWER_GATE_CONTROL_0_LOGIC_SLEEP_OFF                    _MK_ENUM_CONST(0)
#define PMC_IMPL_PART_AOPG_TCM1_POWER_GATE_CONTROL_0_LOGIC_SLEEP_ON                     _MK_ENUM_CONST(1)

#define PMC_IMPL_PART_AOPG_TCM1_POWER_GATE_CONTROL_0_SRAM_RET_EN_SHIFT                  _MK_SHIFT_CONST(1)
#define PMC_IMPL_PART_AOPG_TCM1_POWER_GATE_CONTROL_0_SRAM_RET_EN_FIELD                  _MK_FIELD_CONST(0x1, PMC_IMPL_PART_AOPG_TCM1_POWER_GATE_CONTROL_0_SRAM_RET_EN_SHIFT)
#define PMC_IMPL_PART_AOPG_TCM1_POWER_GATE_CONTROL_0_SRAM_RET_EN_RANGE                  1:1
#define PMC_IMPL_PART_AOPG_TCM1_POWER_GATE_CONTROL_0_SRAM_RET_EN_WOFFSET                        0x0
#define PMC_IMPL_PART_AOPG_TCM1_POWER_GATE_CONTROL_0_SRAM_RET_EN_DEFAULT                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM1_POWER_GATE_CONTROL_0_SRAM_RET_EN_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AOPG_TCM1_POWER_GATE_CONTROL_0_SRAM_RET_EN_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM1_POWER_GATE_CONTROL_0_SRAM_RET_EN_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM1_POWER_GATE_CONTROL_0_SRAM_RET_EN_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM1_POWER_GATE_CONTROL_0_SRAM_RET_EN_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AOPG_TCM1_POWER_GATE_CONTROL_0_SRAM_RET_EN_INIT_ENUM                      OFF
#define PMC_IMPL_PART_AOPG_TCM1_POWER_GATE_CONTROL_0_SRAM_RET_EN_OFF                    _MK_ENUM_CONST(0)
#define PMC_IMPL_PART_AOPG_TCM1_POWER_GATE_CONTROL_0_SRAM_RET_EN_ON                     _MK_ENUM_CONST(1)

#define PMC_IMPL_PART_AOPG_TCM1_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SHIFT                        _MK_SHIFT_CONST(2)
#define PMC_IMPL_PART_AOPG_TCM1_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_FIELD                        _MK_FIELD_CONST(0x1, PMC_IMPL_PART_AOPG_TCM1_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SHIFT)
#define PMC_IMPL_PART_AOPG_TCM1_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_RANGE                        2:2
#define PMC_IMPL_PART_AOPG_TCM1_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_WOFFSET                      0x0
#define PMC_IMPL_PART_AOPG_TCM1_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_DEFAULT                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM1_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AOPG_TCM1_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM1_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM1_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM1_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AOPG_TCM1_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_INIT_ENUM                    OFF
#define PMC_IMPL_PART_AOPG_TCM1_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_OFF                  _MK_ENUM_CONST(0)
#define PMC_IMPL_PART_AOPG_TCM1_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_ON                   _MK_ENUM_CONST(1)

#define PMC_IMPL_PART_AOPG_TCM1_POWER_GATE_CONTROL_0_START_SHIFT                        _MK_SHIFT_CONST(8)
#define PMC_IMPL_PART_AOPG_TCM1_POWER_GATE_CONTROL_0_START_FIELD                        _MK_FIELD_CONST(0x1, PMC_IMPL_PART_AOPG_TCM1_POWER_GATE_CONTROL_0_START_SHIFT)
#define PMC_IMPL_PART_AOPG_TCM1_POWER_GATE_CONTROL_0_START_RANGE                        8:8
#define PMC_IMPL_PART_AOPG_TCM1_POWER_GATE_CONTROL_0_START_WOFFSET                      0x0
#define PMC_IMPL_PART_AOPG_TCM1_POWER_GATE_CONTROL_0_START_DEFAULT                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM1_POWER_GATE_CONTROL_0_START_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AOPG_TCM1_POWER_GATE_CONTROL_0_START_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM1_POWER_GATE_CONTROL_0_START_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM1_POWER_GATE_CONTROL_0_START_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM1_POWER_GATE_CONTROL_0_START_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AOPG_TCM1_POWER_GATE_CONTROL_0_START_INIT_ENUM                    DONE
#define PMC_IMPL_PART_AOPG_TCM1_POWER_GATE_CONTROL_0_START_DONE                 _MK_ENUM_CONST(0)
#define PMC_IMPL_PART_AOPG_TCM1_POWER_GATE_CONTROL_0_START_PENDING                      _MK_ENUM_CONST(1)

#define PMC_IMPL_PART_AOPG_TCM1_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SHIFT                  _MK_SHIFT_CONST(31)
#define PMC_IMPL_PART_AOPG_TCM1_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_FIELD                  _MK_FIELD_CONST(0x1, PMC_IMPL_PART_AOPG_TCM1_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SHIFT)
#define PMC_IMPL_PART_AOPG_TCM1_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_RANGE                  31:31
#define PMC_IMPL_PART_AOPG_TCM1_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_WOFFSET                        0x0
#define PMC_IMPL_PART_AOPG_TCM1_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_DEFAULT                        _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AOPG_TCM1_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AOPG_TCM1_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM1_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM1_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM1_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AOPG_TCM1_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_INIT_ENUM                      ENABLE
#define PMC_IMPL_PART_AOPG_TCM1_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_DISABLE                        _MK_ENUM_CONST(0)
#define PMC_IMPL_PART_AOPG_TCM1_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_ENABLE                 _MK_ENUM_CONST(1)


// Register PMC_IMPL_PART_AOPG_TCM1_POWER_GATE_STATUS_0
#define PMC_IMPL_PART_AOPG_TCM1_POWER_GATE_STATUS_0                     _MK_ADDR_CONST(0x398)
#define PMC_IMPL_PART_AOPG_TCM1_POWER_GATE_STATUS_0_SECURE                      0x0
#define PMC_IMPL_PART_AOPG_TCM1_POWER_GATE_STATUS_0_DUAL                        0x0
#define PMC_IMPL_PART_AOPG_TCM1_POWER_GATE_STATUS_0_SCR                         PG_AOPG_TCM1_SCR_0
#define PMC_IMPL_PART_AOPG_TCM1_POWER_GATE_STATUS_0_WORD_COUNT                  0x1
#define PMC_IMPL_PART_AOPG_TCM1_POWER_GATE_STATUS_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM1_POWER_GATE_STATUS_0_RESET_MASK                  _MK_MASK_CONST(0x7)
#define PMC_IMPL_PART_AOPG_TCM1_POWER_GATE_STATUS_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM1_POWER_GATE_STATUS_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM1_POWER_GATE_STATUS_0_READ_MASK                   _MK_MASK_CONST(0x7)
#define PMC_IMPL_PART_AOPG_TCM1_POWER_GATE_STATUS_0_WRITE_MASK                  _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM1_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SHIFT                       _MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_AOPG_TCM1_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_FIELD                       _MK_FIELD_CONST(0x1, PMC_IMPL_PART_AOPG_TCM1_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SHIFT)
#define PMC_IMPL_PART_AOPG_TCM1_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_RANGE                       0:0
#define PMC_IMPL_PART_AOPG_TCM1_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_WOFFSET                     0x0
#define PMC_IMPL_PART_AOPG_TCM1_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_DEFAULT                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM1_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AOPG_TCM1_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM1_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM1_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM1_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AOPG_TCM1_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_INIT_ENUM                   OFF
#define PMC_IMPL_PART_AOPG_TCM1_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_OFF                 _MK_ENUM_CONST(0)
#define PMC_IMPL_PART_AOPG_TCM1_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_ON                  _MK_ENUM_CONST(1)

#define PMC_IMPL_PART_AOPG_TCM1_POWER_GATE_STATUS_0_SRAM_RET_STS_SHIFT                  _MK_SHIFT_CONST(1)
#define PMC_IMPL_PART_AOPG_TCM1_POWER_GATE_STATUS_0_SRAM_RET_STS_FIELD                  _MK_FIELD_CONST(0x1, PMC_IMPL_PART_AOPG_TCM1_POWER_GATE_STATUS_0_SRAM_RET_STS_SHIFT)
#define PMC_IMPL_PART_AOPG_TCM1_POWER_GATE_STATUS_0_SRAM_RET_STS_RANGE                  1:1
#define PMC_IMPL_PART_AOPG_TCM1_POWER_GATE_STATUS_0_SRAM_RET_STS_WOFFSET                        0x0
#define PMC_IMPL_PART_AOPG_TCM1_POWER_GATE_STATUS_0_SRAM_RET_STS_DEFAULT                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM1_POWER_GATE_STATUS_0_SRAM_RET_STS_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AOPG_TCM1_POWER_GATE_STATUS_0_SRAM_RET_STS_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM1_POWER_GATE_STATUS_0_SRAM_RET_STS_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM1_POWER_GATE_STATUS_0_SRAM_RET_STS_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM1_POWER_GATE_STATUS_0_SRAM_RET_STS_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AOPG_TCM1_POWER_GATE_STATUS_0_SRAM_RET_STS_INIT_ENUM                      OFF
#define PMC_IMPL_PART_AOPG_TCM1_POWER_GATE_STATUS_0_SRAM_RET_STS_OFF                    _MK_ENUM_CONST(0)
#define PMC_IMPL_PART_AOPG_TCM1_POWER_GATE_STATUS_0_SRAM_RET_STS_ON                     _MK_ENUM_CONST(1)

#define PMC_IMPL_PART_AOPG_TCM1_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SHIFT                        _MK_SHIFT_CONST(2)
#define PMC_IMPL_PART_AOPG_TCM1_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_FIELD                        _MK_FIELD_CONST(0x1, PMC_IMPL_PART_AOPG_TCM1_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SHIFT)
#define PMC_IMPL_PART_AOPG_TCM1_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_RANGE                        2:2
#define PMC_IMPL_PART_AOPG_TCM1_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_WOFFSET                      0x0
#define PMC_IMPL_PART_AOPG_TCM1_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_DEFAULT                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM1_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AOPG_TCM1_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM1_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM1_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM1_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AOPG_TCM1_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_INIT_ENUM                    OFF
#define PMC_IMPL_PART_AOPG_TCM1_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_OFF                  _MK_ENUM_CONST(0)
#define PMC_IMPL_PART_AOPG_TCM1_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_ON                   _MK_ENUM_CONST(1)


// Register PMC_IMPL_PART_AOPG_TCM1_CLAMP_CONTROL_0
#define PMC_IMPL_PART_AOPG_TCM1_CLAMP_CONTROL_0                 _MK_ADDR_CONST(0x39c)
#define PMC_IMPL_PART_AOPG_TCM1_CLAMP_CONTROL_0_SECURE                  0x0
#define PMC_IMPL_PART_AOPG_TCM1_CLAMP_CONTROL_0_DUAL                    0x0
#define PMC_IMPL_PART_AOPG_TCM1_CLAMP_CONTROL_0_SCR                     PG_AOPG_TCM1_SCR_0
#define PMC_IMPL_PART_AOPG_TCM1_CLAMP_CONTROL_0_WORD_COUNT                      0x1
#define PMC_IMPL_PART_AOPG_TCM1_CLAMP_CONTROL_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM1_CLAMP_CONTROL_0_RESET_MASK                      _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AOPG_TCM1_CLAMP_CONTROL_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM1_CLAMP_CONTROL_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM1_CLAMP_CONTROL_0_READ_MASK                       _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AOPG_TCM1_CLAMP_CONTROL_0_WRITE_MASK                      _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AOPG_TCM1_CLAMP_CONTROL_0_CLAMP_SHIFT                     _MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_AOPG_TCM1_CLAMP_CONTROL_0_CLAMP_FIELD                     _MK_FIELD_CONST(0x1, PMC_IMPL_PART_AOPG_TCM1_CLAMP_CONTROL_0_CLAMP_SHIFT)
#define PMC_IMPL_PART_AOPG_TCM1_CLAMP_CONTROL_0_CLAMP_RANGE                     0:0
#define PMC_IMPL_PART_AOPG_TCM1_CLAMP_CONTROL_0_CLAMP_WOFFSET                   0x0
#define PMC_IMPL_PART_AOPG_TCM1_CLAMP_CONTROL_0_CLAMP_DEFAULT                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM1_CLAMP_CONTROL_0_CLAMP_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AOPG_TCM1_CLAMP_CONTROL_0_CLAMP_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM1_CLAMP_CONTROL_0_CLAMP_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM1_CLAMP_CONTROL_0_CLAMP_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM1_CLAMP_CONTROL_0_CLAMP_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AOPG_TCM1_CLAMP_CONTROL_0_CLAMP_INIT_ENUM                 OFF
#define PMC_IMPL_PART_AOPG_TCM1_CLAMP_CONTROL_0_CLAMP_OFF                       _MK_ENUM_CONST(0)
#define PMC_IMPL_PART_AOPG_TCM1_CLAMP_CONTROL_0_CLAMP_ON                        _MK_ENUM_CONST(1)


// Register PMC_IMPL_PART_AOPG_TCM2_POWER_GATE_CONTROL_0
#define PMC_IMPL_PART_AOPG_TCM2_POWER_GATE_CONTROL_0                    _MK_ADDR_CONST(0x3a0)
#define PMC_IMPL_PART_AOPG_TCM2_POWER_GATE_CONTROL_0_SECURE                     0x0
#define PMC_IMPL_PART_AOPG_TCM2_POWER_GATE_CONTROL_0_DUAL                       0x0
#define PMC_IMPL_PART_AOPG_TCM2_POWER_GATE_CONTROL_0_SCR                        PG_AOPG_TCM2_SCR_0
#define PMC_IMPL_PART_AOPG_TCM2_POWER_GATE_CONTROL_0_WORD_COUNT                         0x1
#define PMC_IMPL_PART_AOPG_TCM2_POWER_GATE_CONTROL_0_RESET_VAL                  _MK_MASK_CONST(0x80000000)
#define PMC_IMPL_PART_AOPG_TCM2_POWER_GATE_CONTROL_0_RESET_MASK                         _MK_MASK_CONST(0x80000107)
#define PMC_IMPL_PART_AOPG_TCM2_POWER_GATE_CONTROL_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM2_POWER_GATE_CONTROL_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM2_POWER_GATE_CONTROL_0_READ_MASK                  _MK_MASK_CONST(0x80000107)
#define PMC_IMPL_PART_AOPG_TCM2_POWER_GATE_CONTROL_0_WRITE_MASK                         _MK_MASK_CONST(0x80000107)
#define PMC_IMPL_PART_AOPG_TCM2_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SHIFT                  _MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_AOPG_TCM2_POWER_GATE_CONTROL_0_LOGIC_SLEEP_FIELD                  _MK_FIELD_CONST(0x1, PMC_IMPL_PART_AOPG_TCM2_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SHIFT)
#define PMC_IMPL_PART_AOPG_TCM2_POWER_GATE_CONTROL_0_LOGIC_SLEEP_RANGE                  0:0
#define PMC_IMPL_PART_AOPG_TCM2_POWER_GATE_CONTROL_0_LOGIC_SLEEP_WOFFSET                        0x0
#define PMC_IMPL_PART_AOPG_TCM2_POWER_GATE_CONTROL_0_LOGIC_SLEEP_DEFAULT                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM2_POWER_GATE_CONTROL_0_LOGIC_SLEEP_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AOPG_TCM2_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM2_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM2_POWER_GATE_CONTROL_0_LOGIC_SLEEP_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM2_POWER_GATE_CONTROL_0_LOGIC_SLEEP_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AOPG_TCM2_POWER_GATE_CONTROL_0_LOGIC_SLEEP_INIT_ENUM                      OFF
#define PMC_IMPL_PART_AOPG_TCM2_POWER_GATE_CONTROL_0_LOGIC_SLEEP_OFF                    _MK_ENUM_CONST(0)
#define PMC_IMPL_PART_AOPG_TCM2_POWER_GATE_CONTROL_0_LOGIC_SLEEP_ON                     _MK_ENUM_CONST(1)

#define PMC_IMPL_PART_AOPG_TCM2_POWER_GATE_CONTROL_0_SRAM_RET_EN_SHIFT                  _MK_SHIFT_CONST(1)
#define PMC_IMPL_PART_AOPG_TCM2_POWER_GATE_CONTROL_0_SRAM_RET_EN_FIELD                  _MK_FIELD_CONST(0x1, PMC_IMPL_PART_AOPG_TCM2_POWER_GATE_CONTROL_0_SRAM_RET_EN_SHIFT)
#define PMC_IMPL_PART_AOPG_TCM2_POWER_GATE_CONTROL_0_SRAM_RET_EN_RANGE                  1:1
#define PMC_IMPL_PART_AOPG_TCM2_POWER_GATE_CONTROL_0_SRAM_RET_EN_WOFFSET                        0x0
#define PMC_IMPL_PART_AOPG_TCM2_POWER_GATE_CONTROL_0_SRAM_RET_EN_DEFAULT                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM2_POWER_GATE_CONTROL_0_SRAM_RET_EN_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AOPG_TCM2_POWER_GATE_CONTROL_0_SRAM_RET_EN_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM2_POWER_GATE_CONTROL_0_SRAM_RET_EN_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM2_POWER_GATE_CONTROL_0_SRAM_RET_EN_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM2_POWER_GATE_CONTROL_0_SRAM_RET_EN_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AOPG_TCM2_POWER_GATE_CONTROL_0_SRAM_RET_EN_INIT_ENUM                      OFF
#define PMC_IMPL_PART_AOPG_TCM2_POWER_GATE_CONTROL_0_SRAM_RET_EN_OFF                    _MK_ENUM_CONST(0)
#define PMC_IMPL_PART_AOPG_TCM2_POWER_GATE_CONTROL_0_SRAM_RET_EN_ON                     _MK_ENUM_CONST(1)

#define PMC_IMPL_PART_AOPG_TCM2_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SHIFT                        _MK_SHIFT_CONST(2)
#define PMC_IMPL_PART_AOPG_TCM2_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_FIELD                        _MK_FIELD_CONST(0x1, PMC_IMPL_PART_AOPG_TCM2_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SHIFT)
#define PMC_IMPL_PART_AOPG_TCM2_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_RANGE                        2:2
#define PMC_IMPL_PART_AOPG_TCM2_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_WOFFSET                      0x0
#define PMC_IMPL_PART_AOPG_TCM2_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_DEFAULT                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM2_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AOPG_TCM2_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM2_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM2_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM2_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AOPG_TCM2_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_INIT_ENUM                    OFF
#define PMC_IMPL_PART_AOPG_TCM2_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_OFF                  _MK_ENUM_CONST(0)
#define PMC_IMPL_PART_AOPG_TCM2_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_ON                   _MK_ENUM_CONST(1)

#define PMC_IMPL_PART_AOPG_TCM2_POWER_GATE_CONTROL_0_START_SHIFT                        _MK_SHIFT_CONST(8)
#define PMC_IMPL_PART_AOPG_TCM2_POWER_GATE_CONTROL_0_START_FIELD                        _MK_FIELD_CONST(0x1, PMC_IMPL_PART_AOPG_TCM2_POWER_GATE_CONTROL_0_START_SHIFT)
#define PMC_IMPL_PART_AOPG_TCM2_POWER_GATE_CONTROL_0_START_RANGE                        8:8
#define PMC_IMPL_PART_AOPG_TCM2_POWER_GATE_CONTROL_0_START_WOFFSET                      0x0
#define PMC_IMPL_PART_AOPG_TCM2_POWER_GATE_CONTROL_0_START_DEFAULT                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM2_POWER_GATE_CONTROL_0_START_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AOPG_TCM2_POWER_GATE_CONTROL_0_START_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM2_POWER_GATE_CONTROL_0_START_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM2_POWER_GATE_CONTROL_0_START_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM2_POWER_GATE_CONTROL_0_START_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AOPG_TCM2_POWER_GATE_CONTROL_0_START_INIT_ENUM                    DONE
#define PMC_IMPL_PART_AOPG_TCM2_POWER_GATE_CONTROL_0_START_DONE                 _MK_ENUM_CONST(0)
#define PMC_IMPL_PART_AOPG_TCM2_POWER_GATE_CONTROL_0_START_PENDING                      _MK_ENUM_CONST(1)

#define PMC_IMPL_PART_AOPG_TCM2_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SHIFT                  _MK_SHIFT_CONST(31)
#define PMC_IMPL_PART_AOPG_TCM2_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_FIELD                  _MK_FIELD_CONST(0x1, PMC_IMPL_PART_AOPG_TCM2_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SHIFT)
#define PMC_IMPL_PART_AOPG_TCM2_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_RANGE                  31:31
#define PMC_IMPL_PART_AOPG_TCM2_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_WOFFSET                        0x0
#define PMC_IMPL_PART_AOPG_TCM2_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_DEFAULT                        _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AOPG_TCM2_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AOPG_TCM2_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM2_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM2_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM2_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AOPG_TCM2_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_INIT_ENUM                      ENABLE
#define PMC_IMPL_PART_AOPG_TCM2_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_DISABLE                        _MK_ENUM_CONST(0)
#define PMC_IMPL_PART_AOPG_TCM2_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_ENABLE                 _MK_ENUM_CONST(1)


// Register PMC_IMPL_PART_AOPG_TCM2_POWER_GATE_STATUS_0
#define PMC_IMPL_PART_AOPG_TCM2_POWER_GATE_STATUS_0                     _MK_ADDR_CONST(0x3a4)
#define PMC_IMPL_PART_AOPG_TCM2_POWER_GATE_STATUS_0_SECURE                      0x0
#define PMC_IMPL_PART_AOPG_TCM2_POWER_GATE_STATUS_0_DUAL                        0x0
#define PMC_IMPL_PART_AOPG_TCM2_POWER_GATE_STATUS_0_SCR                         PG_AOPG_TCM2_SCR_0
#define PMC_IMPL_PART_AOPG_TCM2_POWER_GATE_STATUS_0_WORD_COUNT                  0x1
#define PMC_IMPL_PART_AOPG_TCM2_POWER_GATE_STATUS_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM2_POWER_GATE_STATUS_0_RESET_MASK                  _MK_MASK_CONST(0x7)
#define PMC_IMPL_PART_AOPG_TCM2_POWER_GATE_STATUS_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM2_POWER_GATE_STATUS_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM2_POWER_GATE_STATUS_0_READ_MASK                   _MK_MASK_CONST(0x7)
#define PMC_IMPL_PART_AOPG_TCM2_POWER_GATE_STATUS_0_WRITE_MASK                  _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM2_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SHIFT                       _MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_AOPG_TCM2_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_FIELD                       _MK_FIELD_CONST(0x1, PMC_IMPL_PART_AOPG_TCM2_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SHIFT)
#define PMC_IMPL_PART_AOPG_TCM2_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_RANGE                       0:0
#define PMC_IMPL_PART_AOPG_TCM2_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_WOFFSET                     0x0
#define PMC_IMPL_PART_AOPG_TCM2_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_DEFAULT                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM2_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AOPG_TCM2_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM2_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM2_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM2_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AOPG_TCM2_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_INIT_ENUM                   OFF
#define PMC_IMPL_PART_AOPG_TCM2_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_OFF                 _MK_ENUM_CONST(0)
#define PMC_IMPL_PART_AOPG_TCM2_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_ON                  _MK_ENUM_CONST(1)

#define PMC_IMPL_PART_AOPG_TCM2_POWER_GATE_STATUS_0_SRAM_RET_STS_SHIFT                  _MK_SHIFT_CONST(1)
#define PMC_IMPL_PART_AOPG_TCM2_POWER_GATE_STATUS_0_SRAM_RET_STS_FIELD                  _MK_FIELD_CONST(0x1, PMC_IMPL_PART_AOPG_TCM2_POWER_GATE_STATUS_0_SRAM_RET_STS_SHIFT)
#define PMC_IMPL_PART_AOPG_TCM2_POWER_GATE_STATUS_0_SRAM_RET_STS_RANGE                  1:1
#define PMC_IMPL_PART_AOPG_TCM2_POWER_GATE_STATUS_0_SRAM_RET_STS_WOFFSET                        0x0
#define PMC_IMPL_PART_AOPG_TCM2_POWER_GATE_STATUS_0_SRAM_RET_STS_DEFAULT                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM2_POWER_GATE_STATUS_0_SRAM_RET_STS_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AOPG_TCM2_POWER_GATE_STATUS_0_SRAM_RET_STS_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM2_POWER_GATE_STATUS_0_SRAM_RET_STS_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM2_POWER_GATE_STATUS_0_SRAM_RET_STS_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM2_POWER_GATE_STATUS_0_SRAM_RET_STS_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AOPG_TCM2_POWER_GATE_STATUS_0_SRAM_RET_STS_INIT_ENUM                      OFF
#define PMC_IMPL_PART_AOPG_TCM2_POWER_GATE_STATUS_0_SRAM_RET_STS_OFF                    _MK_ENUM_CONST(0)
#define PMC_IMPL_PART_AOPG_TCM2_POWER_GATE_STATUS_0_SRAM_RET_STS_ON                     _MK_ENUM_CONST(1)

#define PMC_IMPL_PART_AOPG_TCM2_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SHIFT                        _MK_SHIFT_CONST(2)
#define PMC_IMPL_PART_AOPG_TCM2_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_FIELD                        _MK_FIELD_CONST(0x1, PMC_IMPL_PART_AOPG_TCM2_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SHIFT)
#define PMC_IMPL_PART_AOPG_TCM2_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_RANGE                        2:2
#define PMC_IMPL_PART_AOPG_TCM2_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_WOFFSET                      0x0
#define PMC_IMPL_PART_AOPG_TCM2_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_DEFAULT                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM2_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AOPG_TCM2_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM2_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM2_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM2_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AOPG_TCM2_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_INIT_ENUM                    OFF
#define PMC_IMPL_PART_AOPG_TCM2_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_OFF                  _MK_ENUM_CONST(0)
#define PMC_IMPL_PART_AOPG_TCM2_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_ON                   _MK_ENUM_CONST(1)


// Register PMC_IMPL_PART_AOPG_TCM2_CLAMP_CONTROL_0
#define PMC_IMPL_PART_AOPG_TCM2_CLAMP_CONTROL_0                 _MK_ADDR_CONST(0x3a8)
#define PMC_IMPL_PART_AOPG_TCM2_CLAMP_CONTROL_0_SECURE                  0x0
#define PMC_IMPL_PART_AOPG_TCM2_CLAMP_CONTROL_0_DUAL                    0x0
#define PMC_IMPL_PART_AOPG_TCM2_CLAMP_CONTROL_0_SCR                     PG_AOPG_TCM2_SCR_0
#define PMC_IMPL_PART_AOPG_TCM2_CLAMP_CONTROL_0_WORD_COUNT                      0x1
#define PMC_IMPL_PART_AOPG_TCM2_CLAMP_CONTROL_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM2_CLAMP_CONTROL_0_RESET_MASK                      _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AOPG_TCM2_CLAMP_CONTROL_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM2_CLAMP_CONTROL_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM2_CLAMP_CONTROL_0_READ_MASK                       _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AOPG_TCM2_CLAMP_CONTROL_0_WRITE_MASK                      _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AOPG_TCM2_CLAMP_CONTROL_0_CLAMP_SHIFT                     _MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_AOPG_TCM2_CLAMP_CONTROL_0_CLAMP_FIELD                     _MK_FIELD_CONST(0x1, PMC_IMPL_PART_AOPG_TCM2_CLAMP_CONTROL_0_CLAMP_SHIFT)
#define PMC_IMPL_PART_AOPG_TCM2_CLAMP_CONTROL_0_CLAMP_RANGE                     0:0
#define PMC_IMPL_PART_AOPG_TCM2_CLAMP_CONTROL_0_CLAMP_WOFFSET                   0x0
#define PMC_IMPL_PART_AOPG_TCM2_CLAMP_CONTROL_0_CLAMP_DEFAULT                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM2_CLAMP_CONTROL_0_CLAMP_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AOPG_TCM2_CLAMP_CONTROL_0_CLAMP_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM2_CLAMP_CONTROL_0_CLAMP_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM2_CLAMP_CONTROL_0_CLAMP_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM2_CLAMP_CONTROL_0_CLAMP_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AOPG_TCM2_CLAMP_CONTROL_0_CLAMP_INIT_ENUM                 OFF
#define PMC_IMPL_PART_AOPG_TCM2_CLAMP_CONTROL_0_CLAMP_OFF                       _MK_ENUM_CONST(0)
#define PMC_IMPL_PART_AOPG_TCM2_CLAMP_CONTROL_0_CLAMP_ON                        _MK_ENUM_CONST(1)


// Register PMC_IMPL_PART_AOPG_TCM3_POWER_GATE_CONTROL_0
#define PMC_IMPL_PART_AOPG_TCM3_POWER_GATE_CONTROL_0                    _MK_ADDR_CONST(0x3ac)
#define PMC_IMPL_PART_AOPG_TCM3_POWER_GATE_CONTROL_0_SECURE                     0x0
#define PMC_IMPL_PART_AOPG_TCM3_POWER_GATE_CONTROL_0_DUAL                       0x0
#define PMC_IMPL_PART_AOPG_TCM3_POWER_GATE_CONTROL_0_SCR                        PG_AOPG_TCM3_SCR_0
#define PMC_IMPL_PART_AOPG_TCM3_POWER_GATE_CONTROL_0_WORD_COUNT                         0x1
#define PMC_IMPL_PART_AOPG_TCM3_POWER_GATE_CONTROL_0_RESET_VAL                  _MK_MASK_CONST(0x80000000)
#define PMC_IMPL_PART_AOPG_TCM3_POWER_GATE_CONTROL_0_RESET_MASK                         _MK_MASK_CONST(0x80000107)
#define PMC_IMPL_PART_AOPG_TCM3_POWER_GATE_CONTROL_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM3_POWER_GATE_CONTROL_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM3_POWER_GATE_CONTROL_0_READ_MASK                  _MK_MASK_CONST(0x80000107)
#define PMC_IMPL_PART_AOPG_TCM3_POWER_GATE_CONTROL_0_WRITE_MASK                         _MK_MASK_CONST(0x80000107)
#define PMC_IMPL_PART_AOPG_TCM3_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SHIFT                  _MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_AOPG_TCM3_POWER_GATE_CONTROL_0_LOGIC_SLEEP_FIELD                  _MK_FIELD_CONST(0x1, PMC_IMPL_PART_AOPG_TCM3_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SHIFT)
#define PMC_IMPL_PART_AOPG_TCM3_POWER_GATE_CONTROL_0_LOGIC_SLEEP_RANGE                  0:0
#define PMC_IMPL_PART_AOPG_TCM3_POWER_GATE_CONTROL_0_LOGIC_SLEEP_WOFFSET                        0x0
#define PMC_IMPL_PART_AOPG_TCM3_POWER_GATE_CONTROL_0_LOGIC_SLEEP_DEFAULT                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM3_POWER_GATE_CONTROL_0_LOGIC_SLEEP_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AOPG_TCM3_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM3_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM3_POWER_GATE_CONTROL_0_LOGIC_SLEEP_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM3_POWER_GATE_CONTROL_0_LOGIC_SLEEP_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AOPG_TCM3_POWER_GATE_CONTROL_0_LOGIC_SLEEP_INIT_ENUM                      OFF
#define PMC_IMPL_PART_AOPG_TCM3_POWER_GATE_CONTROL_0_LOGIC_SLEEP_OFF                    _MK_ENUM_CONST(0)
#define PMC_IMPL_PART_AOPG_TCM3_POWER_GATE_CONTROL_0_LOGIC_SLEEP_ON                     _MK_ENUM_CONST(1)

#define PMC_IMPL_PART_AOPG_TCM3_POWER_GATE_CONTROL_0_SRAM_RET_EN_SHIFT                  _MK_SHIFT_CONST(1)
#define PMC_IMPL_PART_AOPG_TCM3_POWER_GATE_CONTROL_0_SRAM_RET_EN_FIELD                  _MK_FIELD_CONST(0x1, PMC_IMPL_PART_AOPG_TCM3_POWER_GATE_CONTROL_0_SRAM_RET_EN_SHIFT)
#define PMC_IMPL_PART_AOPG_TCM3_POWER_GATE_CONTROL_0_SRAM_RET_EN_RANGE                  1:1
#define PMC_IMPL_PART_AOPG_TCM3_POWER_GATE_CONTROL_0_SRAM_RET_EN_WOFFSET                        0x0
#define PMC_IMPL_PART_AOPG_TCM3_POWER_GATE_CONTROL_0_SRAM_RET_EN_DEFAULT                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM3_POWER_GATE_CONTROL_0_SRAM_RET_EN_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AOPG_TCM3_POWER_GATE_CONTROL_0_SRAM_RET_EN_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM3_POWER_GATE_CONTROL_0_SRAM_RET_EN_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM3_POWER_GATE_CONTROL_0_SRAM_RET_EN_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM3_POWER_GATE_CONTROL_0_SRAM_RET_EN_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AOPG_TCM3_POWER_GATE_CONTROL_0_SRAM_RET_EN_INIT_ENUM                      OFF
#define PMC_IMPL_PART_AOPG_TCM3_POWER_GATE_CONTROL_0_SRAM_RET_EN_OFF                    _MK_ENUM_CONST(0)
#define PMC_IMPL_PART_AOPG_TCM3_POWER_GATE_CONTROL_0_SRAM_RET_EN_ON                     _MK_ENUM_CONST(1)

#define PMC_IMPL_PART_AOPG_TCM3_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SHIFT                        _MK_SHIFT_CONST(2)
#define PMC_IMPL_PART_AOPG_TCM3_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_FIELD                        _MK_FIELD_CONST(0x1, PMC_IMPL_PART_AOPG_TCM3_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SHIFT)
#define PMC_IMPL_PART_AOPG_TCM3_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_RANGE                        2:2
#define PMC_IMPL_PART_AOPG_TCM3_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_WOFFSET                      0x0
#define PMC_IMPL_PART_AOPG_TCM3_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_DEFAULT                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM3_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AOPG_TCM3_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM3_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM3_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM3_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AOPG_TCM3_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_INIT_ENUM                    OFF
#define PMC_IMPL_PART_AOPG_TCM3_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_OFF                  _MK_ENUM_CONST(0)
#define PMC_IMPL_PART_AOPG_TCM3_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_ON                   _MK_ENUM_CONST(1)

#define PMC_IMPL_PART_AOPG_TCM3_POWER_GATE_CONTROL_0_START_SHIFT                        _MK_SHIFT_CONST(8)
#define PMC_IMPL_PART_AOPG_TCM3_POWER_GATE_CONTROL_0_START_FIELD                        _MK_FIELD_CONST(0x1, PMC_IMPL_PART_AOPG_TCM3_POWER_GATE_CONTROL_0_START_SHIFT)
#define PMC_IMPL_PART_AOPG_TCM3_POWER_GATE_CONTROL_0_START_RANGE                        8:8
#define PMC_IMPL_PART_AOPG_TCM3_POWER_GATE_CONTROL_0_START_WOFFSET                      0x0
#define PMC_IMPL_PART_AOPG_TCM3_POWER_GATE_CONTROL_0_START_DEFAULT                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM3_POWER_GATE_CONTROL_0_START_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AOPG_TCM3_POWER_GATE_CONTROL_0_START_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM3_POWER_GATE_CONTROL_0_START_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM3_POWER_GATE_CONTROL_0_START_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM3_POWER_GATE_CONTROL_0_START_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AOPG_TCM3_POWER_GATE_CONTROL_0_START_INIT_ENUM                    DONE
#define PMC_IMPL_PART_AOPG_TCM3_POWER_GATE_CONTROL_0_START_DONE                 _MK_ENUM_CONST(0)
#define PMC_IMPL_PART_AOPG_TCM3_POWER_GATE_CONTROL_0_START_PENDING                      _MK_ENUM_CONST(1)

#define PMC_IMPL_PART_AOPG_TCM3_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SHIFT                  _MK_SHIFT_CONST(31)
#define PMC_IMPL_PART_AOPG_TCM3_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_FIELD                  _MK_FIELD_CONST(0x1, PMC_IMPL_PART_AOPG_TCM3_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SHIFT)
#define PMC_IMPL_PART_AOPG_TCM3_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_RANGE                  31:31
#define PMC_IMPL_PART_AOPG_TCM3_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_WOFFSET                        0x0
#define PMC_IMPL_PART_AOPG_TCM3_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_DEFAULT                        _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AOPG_TCM3_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AOPG_TCM3_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM3_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM3_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM3_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AOPG_TCM3_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_INIT_ENUM                      ENABLE
#define PMC_IMPL_PART_AOPG_TCM3_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_DISABLE                        _MK_ENUM_CONST(0)
#define PMC_IMPL_PART_AOPG_TCM3_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_ENABLE                 _MK_ENUM_CONST(1)


// Register PMC_IMPL_PART_AOPG_TCM3_POWER_GATE_STATUS_0
#define PMC_IMPL_PART_AOPG_TCM3_POWER_GATE_STATUS_0                     _MK_ADDR_CONST(0x3b0)
#define PMC_IMPL_PART_AOPG_TCM3_POWER_GATE_STATUS_0_SECURE                      0x0
#define PMC_IMPL_PART_AOPG_TCM3_POWER_GATE_STATUS_0_DUAL                        0x0
#define PMC_IMPL_PART_AOPG_TCM3_POWER_GATE_STATUS_0_SCR                         PG_AOPG_TCM3_SCR_0
#define PMC_IMPL_PART_AOPG_TCM3_POWER_GATE_STATUS_0_WORD_COUNT                  0x1
#define PMC_IMPL_PART_AOPG_TCM3_POWER_GATE_STATUS_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM3_POWER_GATE_STATUS_0_RESET_MASK                  _MK_MASK_CONST(0x7)
#define PMC_IMPL_PART_AOPG_TCM3_POWER_GATE_STATUS_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM3_POWER_GATE_STATUS_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM3_POWER_GATE_STATUS_0_READ_MASK                   _MK_MASK_CONST(0x7)
#define PMC_IMPL_PART_AOPG_TCM3_POWER_GATE_STATUS_0_WRITE_MASK                  _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM3_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SHIFT                       _MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_AOPG_TCM3_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_FIELD                       _MK_FIELD_CONST(0x1, PMC_IMPL_PART_AOPG_TCM3_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SHIFT)
#define PMC_IMPL_PART_AOPG_TCM3_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_RANGE                       0:0
#define PMC_IMPL_PART_AOPG_TCM3_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_WOFFSET                     0x0
#define PMC_IMPL_PART_AOPG_TCM3_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_DEFAULT                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM3_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AOPG_TCM3_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM3_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM3_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM3_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AOPG_TCM3_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_INIT_ENUM                   OFF
#define PMC_IMPL_PART_AOPG_TCM3_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_OFF                 _MK_ENUM_CONST(0)
#define PMC_IMPL_PART_AOPG_TCM3_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_ON                  _MK_ENUM_CONST(1)

#define PMC_IMPL_PART_AOPG_TCM3_POWER_GATE_STATUS_0_SRAM_RET_STS_SHIFT                  _MK_SHIFT_CONST(1)
#define PMC_IMPL_PART_AOPG_TCM3_POWER_GATE_STATUS_0_SRAM_RET_STS_FIELD                  _MK_FIELD_CONST(0x1, PMC_IMPL_PART_AOPG_TCM3_POWER_GATE_STATUS_0_SRAM_RET_STS_SHIFT)
#define PMC_IMPL_PART_AOPG_TCM3_POWER_GATE_STATUS_0_SRAM_RET_STS_RANGE                  1:1
#define PMC_IMPL_PART_AOPG_TCM3_POWER_GATE_STATUS_0_SRAM_RET_STS_WOFFSET                        0x0
#define PMC_IMPL_PART_AOPG_TCM3_POWER_GATE_STATUS_0_SRAM_RET_STS_DEFAULT                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM3_POWER_GATE_STATUS_0_SRAM_RET_STS_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AOPG_TCM3_POWER_GATE_STATUS_0_SRAM_RET_STS_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM3_POWER_GATE_STATUS_0_SRAM_RET_STS_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM3_POWER_GATE_STATUS_0_SRAM_RET_STS_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM3_POWER_GATE_STATUS_0_SRAM_RET_STS_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AOPG_TCM3_POWER_GATE_STATUS_0_SRAM_RET_STS_INIT_ENUM                      OFF
#define PMC_IMPL_PART_AOPG_TCM3_POWER_GATE_STATUS_0_SRAM_RET_STS_OFF                    _MK_ENUM_CONST(0)
#define PMC_IMPL_PART_AOPG_TCM3_POWER_GATE_STATUS_0_SRAM_RET_STS_ON                     _MK_ENUM_CONST(1)

#define PMC_IMPL_PART_AOPG_TCM3_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SHIFT                        _MK_SHIFT_CONST(2)
#define PMC_IMPL_PART_AOPG_TCM3_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_FIELD                        _MK_FIELD_CONST(0x1, PMC_IMPL_PART_AOPG_TCM3_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SHIFT)
#define PMC_IMPL_PART_AOPG_TCM3_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_RANGE                        2:2
#define PMC_IMPL_PART_AOPG_TCM3_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_WOFFSET                      0x0
#define PMC_IMPL_PART_AOPG_TCM3_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_DEFAULT                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM3_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AOPG_TCM3_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM3_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM3_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM3_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AOPG_TCM3_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_INIT_ENUM                    OFF
#define PMC_IMPL_PART_AOPG_TCM3_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_OFF                  _MK_ENUM_CONST(0)
#define PMC_IMPL_PART_AOPG_TCM3_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_ON                   _MK_ENUM_CONST(1)


// Register PMC_IMPL_PART_AOPG_TCM3_CLAMP_CONTROL_0
#define PMC_IMPL_PART_AOPG_TCM3_CLAMP_CONTROL_0                 _MK_ADDR_CONST(0x3b4)
#define PMC_IMPL_PART_AOPG_TCM3_CLAMP_CONTROL_0_SECURE                  0x0
#define PMC_IMPL_PART_AOPG_TCM3_CLAMP_CONTROL_0_DUAL                    0x0
#define PMC_IMPL_PART_AOPG_TCM3_CLAMP_CONTROL_0_SCR                     PG_AOPG_TCM3_SCR_0
#define PMC_IMPL_PART_AOPG_TCM3_CLAMP_CONTROL_0_WORD_COUNT                      0x1
#define PMC_IMPL_PART_AOPG_TCM3_CLAMP_CONTROL_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM3_CLAMP_CONTROL_0_RESET_MASK                      _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AOPG_TCM3_CLAMP_CONTROL_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM3_CLAMP_CONTROL_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM3_CLAMP_CONTROL_0_READ_MASK                       _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AOPG_TCM3_CLAMP_CONTROL_0_WRITE_MASK                      _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AOPG_TCM3_CLAMP_CONTROL_0_CLAMP_SHIFT                     _MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_AOPG_TCM3_CLAMP_CONTROL_0_CLAMP_FIELD                     _MK_FIELD_CONST(0x1, PMC_IMPL_PART_AOPG_TCM3_CLAMP_CONTROL_0_CLAMP_SHIFT)
#define PMC_IMPL_PART_AOPG_TCM3_CLAMP_CONTROL_0_CLAMP_RANGE                     0:0
#define PMC_IMPL_PART_AOPG_TCM3_CLAMP_CONTROL_0_CLAMP_WOFFSET                   0x0
#define PMC_IMPL_PART_AOPG_TCM3_CLAMP_CONTROL_0_CLAMP_DEFAULT                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM3_CLAMP_CONTROL_0_CLAMP_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AOPG_TCM3_CLAMP_CONTROL_0_CLAMP_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM3_CLAMP_CONTROL_0_CLAMP_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM3_CLAMP_CONTROL_0_CLAMP_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM3_CLAMP_CONTROL_0_CLAMP_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AOPG_TCM3_CLAMP_CONTROL_0_CLAMP_INIT_ENUM                 OFF
#define PMC_IMPL_PART_AOPG_TCM3_CLAMP_CONTROL_0_CLAMP_OFF                       _MK_ENUM_CONST(0)
#define PMC_IMPL_PART_AOPG_TCM3_CLAMP_CONTROL_0_CLAMP_ON                        _MK_ENUM_CONST(1)


// Register PMC_IMPL_PART_AOPG_TCM4_POWER_GATE_CONTROL_0
#define PMC_IMPL_PART_AOPG_TCM4_POWER_GATE_CONTROL_0                    _MK_ADDR_CONST(0x3b8)
#define PMC_IMPL_PART_AOPG_TCM4_POWER_GATE_CONTROL_0_SECURE                     0x0
#define PMC_IMPL_PART_AOPG_TCM4_POWER_GATE_CONTROL_0_DUAL                       0x0
#define PMC_IMPL_PART_AOPG_TCM4_POWER_GATE_CONTROL_0_SCR                        PG_AOPG_TCM4_SCR_0
#define PMC_IMPL_PART_AOPG_TCM4_POWER_GATE_CONTROL_0_WORD_COUNT                         0x1
#define PMC_IMPL_PART_AOPG_TCM4_POWER_GATE_CONTROL_0_RESET_VAL                  _MK_MASK_CONST(0x80000000)
#define PMC_IMPL_PART_AOPG_TCM4_POWER_GATE_CONTROL_0_RESET_MASK                         _MK_MASK_CONST(0x80000107)
#define PMC_IMPL_PART_AOPG_TCM4_POWER_GATE_CONTROL_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM4_POWER_GATE_CONTROL_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM4_POWER_GATE_CONTROL_0_READ_MASK                  _MK_MASK_CONST(0x80000107)
#define PMC_IMPL_PART_AOPG_TCM4_POWER_GATE_CONTROL_0_WRITE_MASK                         _MK_MASK_CONST(0x80000107)
#define PMC_IMPL_PART_AOPG_TCM4_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SHIFT                  _MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_AOPG_TCM4_POWER_GATE_CONTROL_0_LOGIC_SLEEP_FIELD                  _MK_FIELD_CONST(0x1, PMC_IMPL_PART_AOPG_TCM4_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SHIFT)
#define PMC_IMPL_PART_AOPG_TCM4_POWER_GATE_CONTROL_0_LOGIC_SLEEP_RANGE                  0:0
#define PMC_IMPL_PART_AOPG_TCM4_POWER_GATE_CONTROL_0_LOGIC_SLEEP_WOFFSET                        0x0
#define PMC_IMPL_PART_AOPG_TCM4_POWER_GATE_CONTROL_0_LOGIC_SLEEP_DEFAULT                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM4_POWER_GATE_CONTROL_0_LOGIC_SLEEP_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AOPG_TCM4_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM4_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM4_POWER_GATE_CONTROL_0_LOGIC_SLEEP_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM4_POWER_GATE_CONTROL_0_LOGIC_SLEEP_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AOPG_TCM4_POWER_GATE_CONTROL_0_LOGIC_SLEEP_INIT_ENUM                      OFF
#define PMC_IMPL_PART_AOPG_TCM4_POWER_GATE_CONTROL_0_LOGIC_SLEEP_OFF                    _MK_ENUM_CONST(0)
#define PMC_IMPL_PART_AOPG_TCM4_POWER_GATE_CONTROL_0_LOGIC_SLEEP_ON                     _MK_ENUM_CONST(1)

#define PMC_IMPL_PART_AOPG_TCM4_POWER_GATE_CONTROL_0_SRAM_RET_EN_SHIFT                  _MK_SHIFT_CONST(1)
#define PMC_IMPL_PART_AOPG_TCM4_POWER_GATE_CONTROL_0_SRAM_RET_EN_FIELD                  _MK_FIELD_CONST(0x1, PMC_IMPL_PART_AOPG_TCM4_POWER_GATE_CONTROL_0_SRAM_RET_EN_SHIFT)
#define PMC_IMPL_PART_AOPG_TCM4_POWER_GATE_CONTROL_0_SRAM_RET_EN_RANGE                  1:1
#define PMC_IMPL_PART_AOPG_TCM4_POWER_GATE_CONTROL_0_SRAM_RET_EN_WOFFSET                        0x0
#define PMC_IMPL_PART_AOPG_TCM4_POWER_GATE_CONTROL_0_SRAM_RET_EN_DEFAULT                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM4_POWER_GATE_CONTROL_0_SRAM_RET_EN_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AOPG_TCM4_POWER_GATE_CONTROL_0_SRAM_RET_EN_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM4_POWER_GATE_CONTROL_0_SRAM_RET_EN_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM4_POWER_GATE_CONTROL_0_SRAM_RET_EN_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM4_POWER_GATE_CONTROL_0_SRAM_RET_EN_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AOPG_TCM4_POWER_GATE_CONTROL_0_SRAM_RET_EN_INIT_ENUM                      OFF
#define PMC_IMPL_PART_AOPG_TCM4_POWER_GATE_CONTROL_0_SRAM_RET_EN_OFF                    _MK_ENUM_CONST(0)
#define PMC_IMPL_PART_AOPG_TCM4_POWER_GATE_CONTROL_0_SRAM_RET_EN_ON                     _MK_ENUM_CONST(1)

#define PMC_IMPL_PART_AOPG_TCM4_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SHIFT                        _MK_SHIFT_CONST(2)
#define PMC_IMPL_PART_AOPG_TCM4_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_FIELD                        _MK_FIELD_CONST(0x1, PMC_IMPL_PART_AOPG_TCM4_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SHIFT)
#define PMC_IMPL_PART_AOPG_TCM4_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_RANGE                        2:2
#define PMC_IMPL_PART_AOPG_TCM4_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_WOFFSET                      0x0
#define PMC_IMPL_PART_AOPG_TCM4_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_DEFAULT                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM4_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AOPG_TCM4_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM4_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM4_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM4_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AOPG_TCM4_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_INIT_ENUM                    OFF
#define PMC_IMPL_PART_AOPG_TCM4_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_OFF                  _MK_ENUM_CONST(0)
#define PMC_IMPL_PART_AOPG_TCM4_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_ON                   _MK_ENUM_CONST(1)

#define PMC_IMPL_PART_AOPG_TCM4_POWER_GATE_CONTROL_0_START_SHIFT                        _MK_SHIFT_CONST(8)
#define PMC_IMPL_PART_AOPG_TCM4_POWER_GATE_CONTROL_0_START_FIELD                        _MK_FIELD_CONST(0x1, PMC_IMPL_PART_AOPG_TCM4_POWER_GATE_CONTROL_0_START_SHIFT)
#define PMC_IMPL_PART_AOPG_TCM4_POWER_GATE_CONTROL_0_START_RANGE                        8:8
#define PMC_IMPL_PART_AOPG_TCM4_POWER_GATE_CONTROL_0_START_WOFFSET                      0x0
#define PMC_IMPL_PART_AOPG_TCM4_POWER_GATE_CONTROL_0_START_DEFAULT                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM4_POWER_GATE_CONTROL_0_START_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AOPG_TCM4_POWER_GATE_CONTROL_0_START_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM4_POWER_GATE_CONTROL_0_START_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM4_POWER_GATE_CONTROL_0_START_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM4_POWER_GATE_CONTROL_0_START_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AOPG_TCM4_POWER_GATE_CONTROL_0_START_INIT_ENUM                    DONE
#define PMC_IMPL_PART_AOPG_TCM4_POWER_GATE_CONTROL_0_START_DONE                 _MK_ENUM_CONST(0)
#define PMC_IMPL_PART_AOPG_TCM4_POWER_GATE_CONTROL_0_START_PENDING                      _MK_ENUM_CONST(1)

#define PMC_IMPL_PART_AOPG_TCM4_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SHIFT                  _MK_SHIFT_CONST(31)
#define PMC_IMPL_PART_AOPG_TCM4_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_FIELD                  _MK_FIELD_CONST(0x1, PMC_IMPL_PART_AOPG_TCM4_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SHIFT)
#define PMC_IMPL_PART_AOPG_TCM4_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_RANGE                  31:31
#define PMC_IMPL_PART_AOPG_TCM4_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_WOFFSET                        0x0
#define PMC_IMPL_PART_AOPG_TCM4_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_DEFAULT                        _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AOPG_TCM4_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AOPG_TCM4_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM4_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM4_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM4_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AOPG_TCM4_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_INIT_ENUM                      ENABLE
#define PMC_IMPL_PART_AOPG_TCM4_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_DISABLE                        _MK_ENUM_CONST(0)
#define PMC_IMPL_PART_AOPG_TCM4_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_ENABLE                 _MK_ENUM_CONST(1)


// Register PMC_IMPL_PART_AOPG_TCM4_POWER_GATE_STATUS_0
#define PMC_IMPL_PART_AOPG_TCM4_POWER_GATE_STATUS_0                     _MK_ADDR_CONST(0x3bc)
#define PMC_IMPL_PART_AOPG_TCM4_POWER_GATE_STATUS_0_SECURE                      0x0
#define PMC_IMPL_PART_AOPG_TCM4_POWER_GATE_STATUS_0_DUAL                        0x0
#define PMC_IMPL_PART_AOPG_TCM4_POWER_GATE_STATUS_0_SCR                         PG_AOPG_TCM4_SCR_0
#define PMC_IMPL_PART_AOPG_TCM4_POWER_GATE_STATUS_0_WORD_COUNT                  0x1
#define PMC_IMPL_PART_AOPG_TCM4_POWER_GATE_STATUS_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM4_POWER_GATE_STATUS_0_RESET_MASK                  _MK_MASK_CONST(0x7)
#define PMC_IMPL_PART_AOPG_TCM4_POWER_GATE_STATUS_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM4_POWER_GATE_STATUS_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM4_POWER_GATE_STATUS_0_READ_MASK                   _MK_MASK_CONST(0x7)
#define PMC_IMPL_PART_AOPG_TCM4_POWER_GATE_STATUS_0_WRITE_MASK                  _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM4_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SHIFT                       _MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_AOPG_TCM4_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_FIELD                       _MK_FIELD_CONST(0x1, PMC_IMPL_PART_AOPG_TCM4_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SHIFT)
#define PMC_IMPL_PART_AOPG_TCM4_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_RANGE                       0:0
#define PMC_IMPL_PART_AOPG_TCM4_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_WOFFSET                     0x0
#define PMC_IMPL_PART_AOPG_TCM4_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_DEFAULT                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM4_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AOPG_TCM4_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM4_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM4_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM4_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AOPG_TCM4_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_INIT_ENUM                   OFF
#define PMC_IMPL_PART_AOPG_TCM4_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_OFF                 _MK_ENUM_CONST(0)
#define PMC_IMPL_PART_AOPG_TCM4_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_ON                  _MK_ENUM_CONST(1)

#define PMC_IMPL_PART_AOPG_TCM4_POWER_GATE_STATUS_0_SRAM_RET_STS_SHIFT                  _MK_SHIFT_CONST(1)
#define PMC_IMPL_PART_AOPG_TCM4_POWER_GATE_STATUS_0_SRAM_RET_STS_FIELD                  _MK_FIELD_CONST(0x1, PMC_IMPL_PART_AOPG_TCM4_POWER_GATE_STATUS_0_SRAM_RET_STS_SHIFT)
#define PMC_IMPL_PART_AOPG_TCM4_POWER_GATE_STATUS_0_SRAM_RET_STS_RANGE                  1:1
#define PMC_IMPL_PART_AOPG_TCM4_POWER_GATE_STATUS_0_SRAM_RET_STS_WOFFSET                        0x0
#define PMC_IMPL_PART_AOPG_TCM4_POWER_GATE_STATUS_0_SRAM_RET_STS_DEFAULT                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM4_POWER_GATE_STATUS_0_SRAM_RET_STS_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AOPG_TCM4_POWER_GATE_STATUS_0_SRAM_RET_STS_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM4_POWER_GATE_STATUS_0_SRAM_RET_STS_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM4_POWER_GATE_STATUS_0_SRAM_RET_STS_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM4_POWER_GATE_STATUS_0_SRAM_RET_STS_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AOPG_TCM4_POWER_GATE_STATUS_0_SRAM_RET_STS_INIT_ENUM                      OFF
#define PMC_IMPL_PART_AOPG_TCM4_POWER_GATE_STATUS_0_SRAM_RET_STS_OFF                    _MK_ENUM_CONST(0)
#define PMC_IMPL_PART_AOPG_TCM4_POWER_GATE_STATUS_0_SRAM_RET_STS_ON                     _MK_ENUM_CONST(1)

#define PMC_IMPL_PART_AOPG_TCM4_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SHIFT                        _MK_SHIFT_CONST(2)
#define PMC_IMPL_PART_AOPG_TCM4_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_FIELD                        _MK_FIELD_CONST(0x1, PMC_IMPL_PART_AOPG_TCM4_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SHIFT)
#define PMC_IMPL_PART_AOPG_TCM4_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_RANGE                        2:2
#define PMC_IMPL_PART_AOPG_TCM4_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_WOFFSET                      0x0
#define PMC_IMPL_PART_AOPG_TCM4_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_DEFAULT                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM4_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AOPG_TCM4_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM4_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM4_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM4_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AOPG_TCM4_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_INIT_ENUM                    OFF
#define PMC_IMPL_PART_AOPG_TCM4_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_OFF                  _MK_ENUM_CONST(0)
#define PMC_IMPL_PART_AOPG_TCM4_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_ON                   _MK_ENUM_CONST(1)


// Register PMC_IMPL_PART_AOPG_TCM4_CLAMP_CONTROL_0
#define PMC_IMPL_PART_AOPG_TCM4_CLAMP_CONTROL_0                 _MK_ADDR_CONST(0x3c0)
#define PMC_IMPL_PART_AOPG_TCM4_CLAMP_CONTROL_0_SECURE                  0x0
#define PMC_IMPL_PART_AOPG_TCM4_CLAMP_CONTROL_0_DUAL                    0x0
#define PMC_IMPL_PART_AOPG_TCM4_CLAMP_CONTROL_0_SCR                     PG_AOPG_TCM4_SCR_0
#define PMC_IMPL_PART_AOPG_TCM4_CLAMP_CONTROL_0_WORD_COUNT                      0x1
#define PMC_IMPL_PART_AOPG_TCM4_CLAMP_CONTROL_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM4_CLAMP_CONTROL_0_RESET_MASK                      _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AOPG_TCM4_CLAMP_CONTROL_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM4_CLAMP_CONTROL_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM4_CLAMP_CONTROL_0_READ_MASK                       _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AOPG_TCM4_CLAMP_CONTROL_0_WRITE_MASK                      _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AOPG_TCM4_CLAMP_CONTROL_0_CLAMP_SHIFT                     _MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_AOPG_TCM4_CLAMP_CONTROL_0_CLAMP_FIELD                     _MK_FIELD_CONST(0x1, PMC_IMPL_PART_AOPG_TCM4_CLAMP_CONTROL_0_CLAMP_SHIFT)
#define PMC_IMPL_PART_AOPG_TCM4_CLAMP_CONTROL_0_CLAMP_RANGE                     0:0
#define PMC_IMPL_PART_AOPG_TCM4_CLAMP_CONTROL_0_CLAMP_WOFFSET                   0x0
#define PMC_IMPL_PART_AOPG_TCM4_CLAMP_CONTROL_0_CLAMP_DEFAULT                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM4_CLAMP_CONTROL_0_CLAMP_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AOPG_TCM4_CLAMP_CONTROL_0_CLAMP_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM4_CLAMP_CONTROL_0_CLAMP_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM4_CLAMP_CONTROL_0_CLAMP_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM4_CLAMP_CONTROL_0_CLAMP_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AOPG_TCM4_CLAMP_CONTROL_0_CLAMP_INIT_ENUM                 OFF
#define PMC_IMPL_PART_AOPG_TCM4_CLAMP_CONTROL_0_CLAMP_OFF                       _MK_ENUM_CONST(0)
#define PMC_IMPL_PART_AOPG_TCM4_CLAMP_CONTROL_0_CLAMP_ON                        _MK_ENUM_CONST(1)


// Register PMC_IMPL_PART_AOPG_TCM5_POWER_GATE_CONTROL_0
#define PMC_IMPL_PART_AOPG_TCM5_POWER_GATE_CONTROL_0                    _MK_ADDR_CONST(0x3c4)
#define PMC_IMPL_PART_AOPG_TCM5_POWER_GATE_CONTROL_0_SECURE                     0x0
#define PMC_IMPL_PART_AOPG_TCM5_POWER_GATE_CONTROL_0_DUAL                       0x0
#define PMC_IMPL_PART_AOPG_TCM5_POWER_GATE_CONTROL_0_SCR                        PG_AOPG_TCM5_SCR_0
#define PMC_IMPL_PART_AOPG_TCM5_POWER_GATE_CONTROL_0_WORD_COUNT                         0x1
#define PMC_IMPL_PART_AOPG_TCM5_POWER_GATE_CONTROL_0_RESET_VAL                  _MK_MASK_CONST(0x80000000)
#define PMC_IMPL_PART_AOPG_TCM5_POWER_GATE_CONTROL_0_RESET_MASK                         _MK_MASK_CONST(0x80000107)
#define PMC_IMPL_PART_AOPG_TCM5_POWER_GATE_CONTROL_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM5_POWER_GATE_CONTROL_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM5_POWER_GATE_CONTROL_0_READ_MASK                  _MK_MASK_CONST(0x80000107)
#define PMC_IMPL_PART_AOPG_TCM5_POWER_GATE_CONTROL_0_WRITE_MASK                         _MK_MASK_CONST(0x80000107)
#define PMC_IMPL_PART_AOPG_TCM5_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SHIFT                  _MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_AOPG_TCM5_POWER_GATE_CONTROL_0_LOGIC_SLEEP_FIELD                  _MK_FIELD_CONST(0x1, PMC_IMPL_PART_AOPG_TCM5_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SHIFT)
#define PMC_IMPL_PART_AOPG_TCM5_POWER_GATE_CONTROL_0_LOGIC_SLEEP_RANGE                  0:0
#define PMC_IMPL_PART_AOPG_TCM5_POWER_GATE_CONTROL_0_LOGIC_SLEEP_WOFFSET                        0x0
#define PMC_IMPL_PART_AOPG_TCM5_POWER_GATE_CONTROL_0_LOGIC_SLEEP_DEFAULT                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM5_POWER_GATE_CONTROL_0_LOGIC_SLEEP_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AOPG_TCM5_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM5_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM5_POWER_GATE_CONTROL_0_LOGIC_SLEEP_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM5_POWER_GATE_CONTROL_0_LOGIC_SLEEP_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AOPG_TCM5_POWER_GATE_CONTROL_0_LOGIC_SLEEP_INIT_ENUM                      OFF
#define PMC_IMPL_PART_AOPG_TCM5_POWER_GATE_CONTROL_0_LOGIC_SLEEP_OFF                    _MK_ENUM_CONST(0)
#define PMC_IMPL_PART_AOPG_TCM5_POWER_GATE_CONTROL_0_LOGIC_SLEEP_ON                     _MK_ENUM_CONST(1)

#define PMC_IMPL_PART_AOPG_TCM5_POWER_GATE_CONTROL_0_SRAM_RET_EN_SHIFT                  _MK_SHIFT_CONST(1)
#define PMC_IMPL_PART_AOPG_TCM5_POWER_GATE_CONTROL_0_SRAM_RET_EN_FIELD                  _MK_FIELD_CONST(0x1, PMC_IMPL_PART_AOPG_TCM5_POWER_GATE_CONTROL_0_SRAM_RET_EN_SHIFT)
#define PMC_IMPL_PART_AOPG_TCM5_POWER_GATE_CONTROL_0_SRAM_RET_EN_RANGE                  1:1
#define PMC_IMPL_PART_AOPG_TCM5_POWER_GATE_CONTROL_0_SRAM_RET_EN_WOFFSET                        0x0
#define PMC_IMPL_PART_AOPG_TCM5_POWER_GATE_CONTROL_0_SRAM_RET_EN_DEFAULT                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM5_POWER_GATE_CONTROL_0_SRAM_RET_EN_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AOPG_TCM5_POWER_GATE_CONTROL_0_SRAM_RET_EN_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM5_POWER_GATE_CONTROL_0_SRAM_RET_EN_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM5_POWER_GATE_CONTROL_0_SRAM_RET_EN_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM5_POWER_GATE_CONTROL_0_SRAM_RET_EN_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AOPG_TCM5_POWER_GATE_CONTROL_0_SRAM_RET_EN_INIT_ENUM                      OFF
#define PMC_IMPL_PART_AOPG_TCM5_POWER_GATE_CONTROL_0_SRAM_RET_EN_OFF                    _MK_ENUM_CONST(0)
#define PMC_IMPL_PART_AOPG_TCM5_POWER_GATE_CONTROL_0_SRAM_RET_EN_ON                     _MK_ENUM_CONST(1)

#define PMC_IMPL_PART_AOPG_TCM5_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SHIFT                        _MK_SHIFT_CONST(2)
#define PMC_IMPL_PART_AOPG_TCM5_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_FIELD                        _MK_FIELD_CONST(0x1, PMC_IMPL_PART_AOPG_TCM5_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SHIFT)
#define PMC_IMPL_PART_AOPG_TCM5_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_RANGE                        2:2
#define PMC_IMPL_PART_AOPG_TCM5_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_WOFFSET                      0x0
#define PMC_IMPL_PART_AOPG_TCM5_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_DEFAULT                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM5_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AOPG_TCM5_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM5_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM5_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM5_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AOPG_TCM5_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_INIT_ENUM                    OFF
#define PMC_IMPL_PART_AOPG_TCM5_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_OFF                  _MK_ENUM_CONST(0)
#define PMC_IMPL_PART_AOPG_TCM5_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_ON                   _MK_ENUM_CONST(1)

#define PMC_IMPL_PART_AOPG_TCM5_POWER_GATE_CONTROL_0_START_SHIFT                        _MK_SHIFT_CONST(8)
#define PMC_IMPL_PART_AOPG_TCM5_POWER_GATE_CONTROL_0_START_FIELD                        _MK_FIELD_CONST(0x1, PMC_IMPL_PART_AOPG_TCM5_POWER_GATE_CONTROL_0_START_SHIFT)
#define PMC_IMPL_PART_AOPG_TCM5_POWER_GATE_CONTROL_0_START_RANGE                        8:8
#define PMC_IMPL_PART_AOPG_TCM5_POWER_GATE_CONTROL_0_START_WOFFSET                      0x0
#define PMC_IMPL_PART_AOPG_TCM5_POWER_GATE_CONTROL_0_START_DEFAULT                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM5_POWER_GATE_CONTROL_0_START_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AOPG_TCM5_POWER_GATE_CONTROL_0_START_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM5_POWER_GATE_CONTROL_0_START_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM5_POWER_GATE_CONTROL_0_START_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM5_POWER_GATE_CONTROL_0_START_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AOPG_TCM5_POWER_GATE_CONTROL_0_START_INIT_ENUM                    DONE
#define PMC_IMPL_PART_AOPG_TCM5_POWER_GATE_CONTROL_0_START_DONE                 _MK_ENUM_CONST(0)
#define PMC_IMPL_PART_AOPG_TCM5_POWER_GATE_CONTROL_0_START_PENDING                      _MK_ENUM_CONST(1)

#define PMC_IMPL_PART_AOPG_TCM5_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SHIFT                  _MK_SHIFT_CONST(31)
#define PMC_IMPL_PART_AOPG_TCM5_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_FIELD                  _MK_FIELD_CONST(0x1, PMC_IMPL_PART_AOPG_TCM5_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SHIFT)
#define PMC_IMPL_PART_AOPG_TCM5_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_RANGE                  31:31
#define PMC_IMPL_PART_AOPG_TCM5_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_WOFFSET                        0x0
#define PMC_IMPL_PART_AOPG_TCM5_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_DEFAULT                        _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AOPG_TCM5_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AOPG_TCM5_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM5_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM5_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM5_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AOPG_TCM5_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_INIT_ENUM                      ENABLE
#define PMC_IMPL_PART_AOPG_TCM5_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_DISABLE                        _MK_ENUM_CONST(0)
#define PMC_IMPL_PART_AOPG_TCM5_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_ENABLE                 _MK_ENUM_CONST(1)


// Register PMC_IMPL_PART_AOPG_TCM5_POWER_GATE_STATUS_0
#define PMC_IMPL_PART_AOPG_TCM5_POWER_GATE_STATUS_0                     _MK_ADDR_CONST(0x3c8)
#define PMC_IMPL_PART_AOPG_TCM5_POWER_GATE_STATUS_0_SECURE                      0x0
#define PMC_IMPL_PART_AOPG_TCM5_POWER_GATE_STATUS_0_DUAL                        0x0
#define PMC_IMPL_PART_AOPG_TCM5_POWER_GATE_STATUS_0_SCR                         PG_AOPG_TCM5_SCR_0
#define PMC_IMPL_PART_AOPG_TCM5_POWER_GATE_STATUS_0_WORD_COUNT                  0x1
#define PMC_IMPL_PART_AOPG_TCM5_POWER_GATE_STATUS_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM5_POWER_GATE_STATUS_0_RESET_MASK                  _MK_MASK_CONST(0x7)
#define PMC_IMPL_PART_AOPG_TCM5_POWER_GATE_STATUS_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM5_POWER_GATE_STATUS_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM5_POWER_GATE_STATUS_0_READ_MASK                   _MK_MASK_CONST(0x7)
#define PMC_IMPL_PART_AOPG_TCM5_POWER_GATE_STATUS_0_WRITE_MASK                  _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM5_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SHIFT                       _MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_AOPG_TCM5_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_FIELD                       _MK_FIELD_CONST(0x1, PMC_IMPL_PART_AOPG_TCM5_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SHIFT)
#define PMC_IMPL_PART_AOPG_TCM5_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_RANGE                       0:0
#define PMC_IMPL_PART_AOPG_TCM5_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_WOFFSET                     0x0
#define PMC_IMPL_PART_AOPG_TCM5_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_DEFAULT                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM5_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AOPG_TCM5_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM5_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM5_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM5_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AOPG_TCM5_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_INIT_ENUM                   OFF
#define PMC_IMPL_PART_AOPG_TCM5_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_OFF                 _MK_ENUM_CONST(0)
#define PMC_IMPL_PART_AOPG_TCM5_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_ON                  _MK_ENUM_CONST(1)

#define PMC_IMPL_PART_AOPG_TCM5_POWER_GATE_STATUS_0_SRAM_RET_STS_SHIFT                  _MK_SHIFT_CONST(1)
#define PMC_IMPL_PART_AOPG_TCM5_POWER_GATE_STATUS_0_SRAM_RET_STS_FIELD                  _MK_FIELD_CONST(0x1, PMC_IMPL_PART_AOPG_TCM5_POWER_GATE_STATUS_0_SRAM_RET_STS_SHIFT)
#define PMC_IMPL_PART_AOPG_TCM5_POWER_GATE_STATUS_0_SRAM_RET_STS_RANGE                  1:1
#define PMC_IMPL_PART_AOPG_TCM5_POWER_GATE_STATUS_0_SRAM_RET_STS_WOFFSET                        0x0
#define PMC_IMPL_PART_AOPG_TCM5_POWER_GATE_STATUS_0_SRAM_RET_STS_DEFAULT                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM5_POWER_GATE_STATUS_0_SRAM_RET_STS_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AOPG_TCM5_POWER_GATE_STATUS_0_SRAM_RET_STS_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM5_POWER_GATE_STATUS_0_SRAM_RET_STS_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM5_POWER_GATE_STATUS_0_SRAM_RET_STS_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM5_POWER_GATE_STATUS_0_SRAM_RET_STS_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AOPG_TCM5_POWER_GATE_STATUS_0_SRAM_RET_STS_INIT_ENUM                      OFF
#define PMC_IMPL_PART_AOPG_TCM5_POWER_GATE_STATUS_0_SRAM_RET_STS_OFF                    _MK_ENUM_CONST(0)
#define PMC_IMPL_PART_AOPG_TCM5_POWER_GATE_STATUS_0_SRAM_RET_STS_ON                     _MK_ENUM_CONST(1)

#define PMC_IMPL_PART_AOPG_TCM5_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SHIFT                        _MK_SHIFT_CONST(2)
#define PMC_IMPL_PART_AOPG_TCM5_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_FIELD                        _MK_FIELD_CONST(0x1, PMC_IMPL_PART_AOPG_TCM5_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SHIFT)
#define PMC_IMPL_PART_AOPG_TCM5_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_RANGE                        2:2
#define PMC_IMPL_PART_AOPG_TCM5_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_WOFFSET                      0x0
#define PMC_IMPL_PART_AOPG_TCM5_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_DEFAULT                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM5_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AOPG_TCM5_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM5_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM5_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM5_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AOPG_TCM5_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_INIT_ENUM                    OFF
#define PMC_IMPL_PART_AOPG_TCM5_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_OFF                  _MK_ENUM_CONST(0)
#define PMC_IMPL_PART_AOPG_TCM5_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_ON                   _MK_ENUM_CONST(1)


// Register PMC_IMPL_PART_AOPG_TCM5_CLAMP_CONTROL_0
#define PMC_IMPL_PART_AOPG_TCM5_CLAMP_CONTROL_0                 _MK_ADDR_CONST(0x3cc)
#define PMC_IMPL_PART_AOPG_TCM5_CLAMP_CONTROL_0_SECURE                  0x0
#define PMC_IMPL_PART_AOPG_TCM5_CLAMP_CONTROL_0_DUAL                    0x0
#define PMC_IMPL_PART_AOPG_TCM5_CLAMP_CONTROL_0_SCR                     PG_AOPG_TCM5_SCR_0
#define PMC_IMPL_PART_AOPG_TCM5_CLAMP_CONTROL_0_WORD_COUNT                      0x1
#define PMC_IMPL_PART_AOPG_TCM5_CLAMP_CONTROL_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM5_CLAMP_CONTROL_0_RESET_MASK                      _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AOPG_TCM5_CLAMP_CONTROL_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM5_CLAMP_CONTROL_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM5_CLAMP_CONTROL_0_READ_MASK                       _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AOPG_TCM5_CLAMP_CONTROL_0_WRITE_MASK                      _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AOPG_TCM5_CLAMP_CONTROL_0_CLAMP_SHIFT                     _MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_AOPG_TCM5_CLAMP_CONTROL_0_CLAMP_FIELD                     _MK_FIELD_CONST(0x1, PMC_IMPL_PART_AOPG_TCM5_CLAMP_CONTROL_0_CLAMP_SHIFT)
#define PMC_IMPL_PART_AOPG_TCM5_CLAMP_CONTROL_0_CLAMP_RANGE                     0:0
#define PMC_IMPL_PART_AOPG_TCM5_CLAMP_CONTROL_0_CLAMP_WOFFSET                   0x0
#define PMC_IMPL_PART_AOPG_TCM5_CLAMP_CONTROL_0_CLAMP_DEFAULT                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM5_CLAMP_CONTROL_0_CLAMP_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AOPG_TCM5_CLAMP_CONTROL_0_CLAMP_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM5_CLAMP_CONTROL_0_CLAMP_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM5_CLAMP_CONTROL_0_CLAMP_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM5_CLAMP_CONTROL_0_CLAMP_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AOPG_TCM5_CLAMP_CONTROL_0_CLAMP_INIT_ENUM                 OFF
#define PMC_IMPL_PART_AOPG_TCM5_CLAMP_CONTROL_0_CLAMP_OFF                       _MK_ENUM_CONST(0)
#define PMC_IMPL_PART_AOPG_TCM5_CLAMP_CONTROL_0_CLAMP_ON                        _MK_ENUM_CONST(1)


// Register PMC_IMPL_PART_AOPG_TCM6_POWER_GATE_CONTROL_0
#define PMC_IMPL_PART_AOPG_TCM6_POWER_GATE_CONTROL_0                    _MK_ADDR_CONST(0x3d0)
#define PMC_IMPL_PART_AOPG_TCM6_POWER_GATE_CONTROL_0_SECURE                     0x0
#define PMC_IMPL_PART_AOPG_TCM6_POWER_GATE_CONTROL_0_DUAL                       0x0
#define PMC_IMPL_PART_AOPG_TCM6_POWER_GATE_CONTROL_0_SCR                        PG_AOPG_TCM6_SCR_0
#define PMC_IMPL_PART_AOPG_TCM6_POWER_GATE_CONTROL_0_WORD_COUNT                         0x1
#define PMC_IMPL_PART_AOPG_TCM6_POWER_GATE_CONTROL_0_RESET_VAL                  _MK_MASK_CONST(0x80000000)
#define PMC_IMPL_PART_AOPG_TCM6_POWER_GATE_CONTROL_0_RESET_MASK                         _MK_MASK_CONST(0x80000107)
#define PMC_IMPL_PART_AOPG_TCM6_POWER_GATE_CONTROL_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM6_POWER_GATE_CONTROL_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM6_POWER_GATE_CONTROL_0_READ_MASK                  _MK_MASK_CONST(0x80000107)
#define PMC_IMPL_PART_AOPG_TCM6_POWER_GATE_CONTROL_0_WRITE_MASK                         _MK_MASK_CONST(0x80000107)
#define PMC_IMPL_PART_AOPG_TCM6_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SHIFT                  _MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_AOPG_TCM6_POWER_GATE_CONTROL_0_LOGIC_SLEEP_FIELD                  _MK_FIELD_CONST(0x1, PMC_IMPL_PART_AOPG_TCM6_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SHIFT)
#define PMC_IMPL_PART_AOPG_TCM6_POWER_GATE_CONTROL_0_LOGIC_SLEEP_RANGE                  0:0
#define PMC_IMPL_PART_AOPG_TCM6_POWER_GATE_CONTROL_0_LOGIC_SLEEP_WOFFSET                        0x0
#define PMC_IMPL_PART_AOPG_TCM6_POWER_GATE_CONTROL_0_LOGIC_SLEEP_DEFAULT                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM6_POWER_GATE_CONTROL_0_LOGIC_SLEEP_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AOPG_TCM6_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM6_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM6_POWER_GATE_CONTROL_0_LOGIC_SLEEP_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM6_POWER_GATE_CONTROL_0_LOGIC_SLEEP_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AOPG_TCM6_POWER_GATE_CONTROL_0_LOGIC_SLEEP_INIT_ENUM                      OFF
#define PMC_IMPL_PART_AOPG_TCM6_POWER_GATE_CONTROL_0_LOGIC_SLEEP_OFF                    _MK_ENUM_CONST(0)
#define PMC_IMPL_PART_AOPG_TCM6_POWER_GATE_CONTROL_0_LOGIC_SLEEP_ON                     _MK_ENUM_CONST(1)

#define PMC_IMPL_PART_AOPG_TCM6_POWER_GATE_CONTROL_0_SRAM_RET_EN_SHIFT                  _MK_SHIFT_CONST(1)
#define PMC_IMPL_PART_AOPG_TCM6_POWER_GATE_CONTROL_0_SRAM_RET_EN_FIELD                  _MK_FIELD_CONST(0x1, PMC_IMPL_PART_AOPG_TCM6_POWER_GATE_CONTROL_0_SRAM_RET_EN_SHIFT)
#define PMC_IMPL_PART_AOPG_TCM6_POWER_GATE_CONTROL_0_SRAM_RET_EN_RANGE                  1:1
#define PMC_IMPL_PART_AOPG_TCM6_POWER_GATE_CONTROL_0_SRAM_RET_EN_WOFFSET                        0x0
#define PMC_IMPL_PART_AOPG_TCM6_POWER_GATE_CONTROL_0_SRAM_RET_EN_DEFAULT                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM6_POWER_GATE_CONTROL_0_SRAM_RET_EN_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AOPG_TCM6_POWER_GATE_CONTROL_0_SRAM_RET_EN_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM6_POWER_GATE_CONTROL_0_SRAM_RET_EN_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM6_POWER_GATE_CONTROL_0_SRAM_RET_EN_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM6_POWER_GATE_CONTROL_0_SRAM_RET_EN_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AOPG_TCM6_POWER_GATE_CONTROL_0_SRAM_RET_EN_INIT_ENUM                      OFF
#define PMC_IMPL_PART_AOPG_TCM6_POWER_GATE_CONTROL_0_SRAM_RET_EN_OFF                    _MK_ENUM_CONST(0)
#define PMC_IMPL_PART_AOPG_TCM6_POWER_GATE_CONTROL_0_SRAM_RET_EN_ON                     _MK_ENUM_CONST(1)

#define PMC_IMPL_PART_AOPG_TCM6_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SHIFT                        _MK_SHIFT_CONST(2)
#define PMC_IMPL_PART_AOPG_TCM6_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_FIELD                        _MK_FIELD_CONST(0x1, PMC_IMPL_PART_AOPG_TCM6_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SHIFT)
#define PMC_IMPL_PART_AOPG_TCM6_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_RANGE                        2:2
#define PMC_IMPL_PART_AOPG_TCM6_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_WOFFSET                      0x0
#define PMC_IMPL_PART_AOPG_TCM6_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_DEFAULT                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM6_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AOPG_TCM6_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM6_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM6_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM6_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AOPG_TCM6_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_INIT_ENUM                    OFF
#define PMC_IMPL_PART_AOPG_TCM6_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_OFF                  _MK_ENUM_CONST(0)
#define PMC_IMPL_PART_AOPG_TCM6_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_ON                   _MK_ENUM_CONST(1)

#define PMC_IMPL_PART_AOPG_TCM6_POWER_GATE_CONTROL_0_START_SHIFT                        _MK_SHIFT_CONST(8)
#define PMC_IMPL_PART_AOPG_TCM6_POWER_GATE_CONTROL_0_START_FIELD                        _MK_FIELD_CONST(0x1, PMC_IMPL_PART_AOPG_TCM6_POWER_GATE_CONTROL_0_START_SHIFT)
#define PMC_IMPL_PART_AOPG_TCM6_POWER_GATE_CONTROL_0_START_RANGE                        8:8
#define PMC_IMPL_PART_AOPG_TCM6_POWER_GATE_CONTROL_0_START_WOFFSET                      0x0
#define PMC_IMPL_PART_AOPG_TCM6_POWER_GATE_CONTROL_0_START_DEFAULT                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM6_POWER_GATE_CONTROL_0_START_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AOPG_TCM6_POWER_GATE_CONTROL_0_START_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM6_POWER_GATE_CONTROL_0_START_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM6_POWER_GATE_CONTROL_0_START_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM6_POWER_GATE_CONTROL_0_START_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AOPG_TCM6_POWER_GATE_CONTROL_0_START_INIT_ENUM                    DONE
#define PMC_IMPL_PART_AOPG_TCM6_POWER_GATE_CONTROL_0_START_DONE                 _MK_ENUM_CONST(0)
#define PMC_IMPL_PART_AOPG_TCM6_POWER_GATE_CONTROL_0_START_PENDING                      _MK_ENUM_CONST(1)

#define PMC_IMPL_PART_AOPG_TCM6_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SHIFT                  _MK_SHIFT_CONST(31)
#define PMC_IMPL_PART_AOPG_TCM6_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_FIELD                  _MK_FIELD_CONST(0x1, PMC_IMPL_PART_AOPG_TCM6_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SHIFT)
#define PMC_IMPL_PART_AOPG_TCM6_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_RANGE                  31:31
#define PMC_IMPL_PART_AOPG_TCM6_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_WOFFSET                        0x0
#define PMC_IMPL_PART_AOPG_TCM6_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_DEFAULT                        _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AOPG_TCM6_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AOPG_TCM6_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM6_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM6_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM6_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AOPG_TCM6_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_INIT_ENUM                      ENABLE
#define PMC_IMPL_PART_AOPG_TCM6_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_DISABLE                        _MK_ENUM_CONST(0)
#define PMC_IMPL_PART_AOPG_TCM6_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_ENABLE                 _MK_ENUM_CONST(1)


// Register PMC_IMPL_PART_AOPG_TCM6_POWER_GATE_STATUS_0
#define PMC_IMPL_PART_AOPG_TCM6_POWER_GATE_STATUS_0                     _MK_ADDR_CONST(0x3d4)
#define PMC_IMPL_PART_AOPG_TCM6_POWER_GATE_STATUS_0_SECURE                      0x0
#define PMC_IMPL_PART_AOPG_TCM6_POWER_GATE_STATUS_0_DUAL                        0x0
#define PMC_IMPL_PART_AOPG_TCM6_POWER_GATE_STATUS_0_SCR                         PG_AOPG_TCM6_SCR_0
#define PMC_IMPL_PART_AOPG_TCM6_POWER_GATE_STATUS_0_WORD_COUNT                  0x1
#define PMC_IMPL_PART_AOPG_TCM6_POWER_GATE_STATUS_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM6_POWER_GATE_STATUS_0_RESET_MASK                  _MK_MASK_CONST(0x7)
#define PMC_IMPL_PART_AOPG_TCM6_POWER_GATE_STATUS_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM6_POWER_GATE_STATUS_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM6_POWER_GATE_STATUS_0_READ_MASK                   _MK_MASK_CONST(0x7)
#define PMC_IMPL_PART_AOPG_TCM6_POWER_GATE_STATUS_0_WRITE_MASK                  _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM6_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SHIFT                       _MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_AOPG_TCM6_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_FIELD                       _MK_FIELD_CONST(0x1, PMC_IMPL_PART_AOPG_TCM6_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SHIFT)
#define PMC_IMPL_PART_AOPG_TCM6_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_RANGE                       0:0
#define PMC_IMPL_PART_AOPG_TCM6_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_WOFFSET                     0x0
#define PMC_IMPL_PART_AOPG_TCM6_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_DEFAULT                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM6_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AOPG_TCM6_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM6_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM6_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM6_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AOPG_TCM6_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_INIT_ENUM                   OFF
#define PMC_IMPL_PART_AOPG_TCM6_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_OFF                 _MK_ENUM_CONST(0)
#define PMC_IMPL_PART_AOPG_TCM6_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_ON                  _MK_ENUM_CONST(1)

#define PMC_IMPL_PART_AOPG_TCM6_POWER_GATE_STATUS_0_SRAM_RET_STS_SHIFT                  _MK_SHIFT_CONST(1)
#define PMC_IMPL_PART_AOPG_TCM6_POWER_GATE_STATUS_0_SRAM_RET_STS_FIELD                  _MK_FIELD_CONST(0x1, PMC_IMPL_PART_AOPG_TCM6_POWER_GATE_STATUS_0_SRAM_RET_STS_SHIFT)
#define PMC_IMPL_PART_AOPG_TCM6_POWER_GATE_STATUS_0_SRAM_RET_STS_RANGE                  1:1
#define PMC_IMPL_PART_AOPG_TCM6_POWER_GATE_STATUS_0_SRAM_RET_STS_WOFFSET                        0x0
#define PMC_IMPL_PART_AOPG_TCM6_POWER_GATE_STATUS_0_SRAM_RET_STS_DEFAULT                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM6_POWER_GATE_STATUS_0_SRAM_RET_STS_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AOPG_TCM6_POWER_GATE_STATUS_0_SRAM_RET_STS_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM6_POWER_GATE_STATUS_0_SRAM_RET_STS_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM6_POWER_GATE_STATUS_0_SRAM_RET_STS_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM6_POWER_GATE_STATUS_0_SRAM_RET_STS_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AOPG_TCM6_POWER_GATE_STATUS_0_SRAM_RET_STS_INIT_ENUM                      OFF
#define PMC_IMPL_PART_AOPG_TCM6_POWER_GATE_STATUS_0_SRAM_RET_STS_OFF                    _MK_ENUM_CONST(0)
#define PMC_IMPL_PART_AOPG_TCM6_POWER_GATE_STATUS_0_SRAM_RET_STS_ON                     _MK_ENUM_CONST(1)

#define PMC_IMPL_PART_AOPG_TCM6_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SHIFT                        _MK_SHIFT_CONST(2)
#define PMC_IMPL_PART_AOPG_TCM6_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_FIELD                        _MK_FIELD_CONST(0x1, PMC_IMPL_PART_AOPG_TCM6_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SHIFT)
#define PMC_IMPL_PART_AOPG_TCM6_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_RANGE                        2:2
#define PMC_IMPL_PART_AOPG_TCM6_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_WOFFSET                      0x0
#define PMC_IMPL_PART_AOPG_TCM6_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_DEFAULT                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM6_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AOPG_TCM6_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM6_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM6_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM6_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AOPG_TCM6_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_INIT_ENUM                    OFF
#define PMC_IMPL_PART_AOPG_TCM6_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_OFF                  _MK_ENUM_CONST(0)
#define PMC_IMPL_PART_AOPG_TCM6_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_ON                   _MK_ENUM_CONST(1)


// Register PMC_IMPL_PART_AOPG_TCM6_CLAMP_CONTROL_0
#define PMC_IMPL_PART_AOPG_TCM6_CLAMP_CONTROL_0                 _MK_ADDR_CONST(0x3d8)
#define PMC_IMPL_PART_AOPG_TCM6_CLAMP_CONTROL_0_SECURE                  0x0
#define PMC_IMPL_PART_AOPG_TCM6_CLAMP_CONTROL_0_DUAL                    0x0
#define PMC_IMPL_PART_AOPG_TCM6_CLAMP_CONTROL_0_SCR                     PG_AOPG_TCM6_SCR_0
#define PMC_IMPL_PART_AOPG_TCM6_CLAMP_CONTROL_0_WORD_COUNT                      0x1
#define PMC_IMPL_PART_AOPG_TCM6_CLAMP_CONTROL_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM6_CLAMP_CONTROL_0_RESET_MASK                      _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AOPG_TCM6_CLAMP_CONTROL_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM6_CLAMP_CONTROL_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM6_CLAMP_CONTROL_0_READ_MASK                       _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AOPG_TCM6_CLAMP_CONTROL_0_WRITE_MASK                      _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AOPG_TCM6_CLAMP_CONTROL_0_CLAMP_SHIFT                     _MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_AOPG_TCM6_CLAMP_CONTROL_0_CLAMP_FIELD                     _MK_FIELD_CONST(0x1, PMC_IMPL_PART_AOPG_TCM6_CLAMP_CONTROL_0_CLAMP_SHIFT)
#define PMC_IMPL_PART_AOPG_TCM6_CLAMP_CONTROL_0_CLAMP_RANGE                     0:0
#define PMC_IMPL_PART_AOPG_TCM6_CLAMP_CONTROL_0_CLAMP_WOFFSET                   0x0
#define PMC_IMPL_PART_AOPG_TCM6_CLAMP_CONTROL_0_CLAMP_DEFAULT                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM6_CLAMP_CONTROL_0_CLAMP_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AOPG_TCM6_CLAMP_CONTROL_0_CLAMP_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM6_CLAMP_CONTROL_0_CLAMP_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM6_CLAMP_CONTROL_0_CLAMP_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM6_CLAMP_CONTROL_0_CLAMP_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AOPG_TCM6_CLAMP_CONTROL_0_CLAMP_INIT_ENUM                 OFF
#define PMC_IMPL_PART_AOPG_TCM6_CLAMP_CONTROL_0_CLAMP_OFF                       _MK_ENUM_CONST(0)
#define PMC_IMPL_PART_AOPG_TCM6_CLAMP_CONTROL_0_CLAMP_ON                        _MK_ENUM_CONST(1)


// Register PMC_IMPL_PART_AOPG_TCM7_POWER_GATE_CONTROL_0
#define PMC_IMPL_PART_AOPG_TCM7_POWER_GATE_CONTROL_0                    _MK_ADDR_CONST(0x3dc)
#define PMC_IMPL_PART_AOPG_TCM7_POWER_GATE_CONTROL_0_SECURE                     0x0
#define PMC_IMPL_PART_AOPG_TCM7_POWER_GATE_CONTROL_0_DUAL                       0x0
#define PMC_IMPL_PART_AOPG_TCM7_POWER_GATE_CONTROL_0_SCR                        PG_AOPG_TCM7_SCR_0
#define PMC_IMPL_PART_AOPG_TCM7_POWER_GATE_CONTROL_0_WORD_COUNT                         0x1
#define PMC_IMPL_PART_AOPG_TCM7_POWER_GATE_CONTROL_0_RESET_VAL                  _MK_MASK_CONST(0x80000000)
#define PMC_IMPL_PART_AOPG_TCM7_POWER_GATE_CONTROL_0_RESET_MASK                         _MK_MASK_CONST(0x80000107)
#define PMC_IMPL_PART_AOPG_TCM7_POWER_GATE_CONTROL_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM7_POWER_GATE_CONTROL_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM7_POWER_GATE_CONTROL_0_READ_MASK                  _MK_MASK_CONST(0x80000107)
#define PMC_IMPL_PART_AOPG_TCM7_POWER_GATE_CONTROL_0_WRITE_MASK                         _MK_MASK_CONST(0x80000107)
#define PMC_IMPL_PART_AOPG_TCM7_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SHIFT                  _MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_AOPG_TCM7_POWER_GATE_CONTROL_0_LOGIC_SLEEP_FIELD                  _MK_FIELD_CONST(0x1, PMC_IMPL_PART_AOPG_TCM7_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SHIFT)
#define PMC_IMPL_PART_AOPG_TCM7_POWER_GATE_CONTROL_0_LOGIC_SLEEP_RANGE                  0:0
#define PMC_IMPL_PART_AOPG_TCM7_POWER_GATE_CONTROL_0_LOGIC_SLEEP_WOFFSET                        0x0
#define PMC_IMPL_PART_AOPG_TCM7_POWER_GATE_CONTROL_0_LOGIC_SLEEP_DEFAULT                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM7_POWER_GATE_CONTROL_0_LOGIC_SLEEP_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AOPG_TCM7_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM7_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM7_POWER_GATE_CONTROL_0_LOGIC_SLEEP_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM7_POWER_GATE_CONTROL_0_LOGIC_SLEEP_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AOPG_TCM7_POWER_GATE_CONTROL_0_LOGIC_SLEEP_INIT_ENUM                      OFF
#define PMC_IMPL_PART_AOPG_TCM7_POWER_GATE_CONTROL_0_LOGIC_SLEEP_OFF                    _MK_ENUM_CONST(0)
#define PMC_IMPL_PART_AOPG_TCM7_POWER_GATE_CONTROL_0_LOGIC_SLEEP_ON                     _MK_ENUM_CONST(1)

#define PMC_IMPL_PART_AOPG_TCM7_POWER_GATE_CONTROL_0_SRAM_RET_EN_SHIFT                  _MK_SHIFT_CONST(1)
#define PMC_IMPL_PART_AOPG_TCM7_POWER_GATE_CONTROL_0_SRAM_RET_EN_FIELD                  _MK_FIELD_CONST(0x1, PMC_IMPL_PART_AOPG_TCM7_POWER_GATE_CONTROL_0_SRAM_RET_EN_SHIFT)
#define PMC_IMPL_PART_AOPG_TCM7_POWER_GATE_CONTROL_0_SRAM_RET_EN_RANGE                  1:1
#define PMC_IMPL_PART_AOPG_TCM7_POWER_GATE_CONTROL_0_SRAM_RET_EN_WOFFSET                        0x0
#define PMC_IMPL_PART_AOPG_TCM7_POWER_GATE_CONTROL_0_SRAM_RET_EN_DEFAULT                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM7_POWER_GATE_CONTROL_0_SRAM_RET_EN_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AOPG_TCM7_POWER_GATE_CONTROL_0_SRAM_RET_EN_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM7_POWER_GATE_CONTROL_0_SRAM_RET_EN_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM7_POWER_GATE_CONTROL_0_SRAM_RET_EN_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM7_POWER_GATE_CONTROL_0_SRAM_RET_EN_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AOPG_TCM7_POWER_GATE_CONTROL_0_SRAM_RET_EN_INIT_ENUM                      OFF
#define PMC_IMPL_PART_AOPG_TCM7_POWER_GATE_CONTROL_0_SRAM_RET_EN_OFF                    _MK_ENUM_CONST(0)
#define PMC_IMPL_PART_AOPG_TCM7_POWER_GATE_CONTROL_0_SRAM_RET_EN_ON                     _MK_ENUM_CONST(1)

#define PMC_IMPL_PART_AOPG_TCM7_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SHIFT                        _MK_SHIFT_CONST(2)
#define PMC_IMPL_PART_AOPG_TCM7_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_FIELD                        _MK_FIELD_CONST(0x1, PMC_IMPL_PART_AOPG_TCM7_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SHIFT)
#define PMC_IMPL_PART_AOPG_TCM7_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_RANGE                        2:2
#define PMC_IMPL_PART_AOPG_TCM7_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_WOFFSET                      0x0
#define PMC_IMPL_PART_AOPG_TCM7_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_DEFAULT                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM7_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AOPG_TCM7_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM7_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM7_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM7_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AOPG_TCM7_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_INIT_ENUM                    OFF
#define PMC_IMPL_PART_AOPG_TCM7_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_OFF                  _MK_ENUM_CONST(0)
#define PMC_IMPL_PART_AOPG_TCM7_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_ON                   _MK_ENUM_CONST(1)

#define PMC_IMPL_PART_AOPG_TCM7_POWER_GATE_CONTROL_0_START_SHIFT                        _MK_SHIFT_CONST(8)
#define PMC_IMPL_PART_AOPG_TCM7_POWER_GATE_CONTROL_0_START_FIELD                        _MK_FIELD_CONST(0x1, PMC_IMPL_PART_AOPG_TCM7_POWER_GATE_CONTROL_0_START_SHIFT)
#define PMC_IMPL_PART_AOPG_TCM7_POWER_GATE_CONTROL_0_START_RANGE                        8:8
#define PMC_IMPL_PART_AOPG_TCM7_POWER_GATE_CONTROL_0_START_WOFFSET                      0x0
#define PMC_IMPL_PART_AOPG_TCM7_POWER_GATE_CONTROL_0_START_DEFAULT                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM7_POWER_GATE_CONTROL_0_START_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AOPG_TCM7_POWER_GATE_CONTROL_0_START_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM7_POWER_GATE_CONTROL_0_START_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM7_POWER_GATE_CONTROL_0_START_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM7_POWER_GATE_CONTROL_0_START_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AOPG_TCM7_POWER_GATE_CONTROL_0_START_INIT_ENUM                    DONE
#define PMC_IMPL_PART_AOPG_TCM7_POWER_GATE_CONTROL_0_START_DONE                 _MK_ENUM_CONST(0)
#define PMC_IMPL_PART_AOPG_TCM7_POWER_GATE_CONTROL_0_START_PENDING                      _MK_ENUM_CONST(1)

#define PMC_IMPL_PART_AOPG_TCM7_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SHIFT                  _MK_SHIFT_CONST(31)
#define PMC_IMPL_PART_AOPG_TCM7_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_FIELD                  _MK_FIELD_CONST(0x1, PMC_IMPL_PART_AOPG_TCM7_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SHIFT)
#define PMC_IMPL_PART_AOPG_TCM7_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_RANGE                  31:31
#define PMC_IMPL_PART_AOPG_TCM7_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_WOFFSET                        0x0
#define PMC_IMPL_PART_AOPG_TCM7_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_DEFAULT                        _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AOPG_TCM7_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AOPG_TCM7_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM7_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM7_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM7_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AOPG_TCM7_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_INIT_ENUM                      ENABLE
#define PMC_IMPL_PART_AOPG_TCM7_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_DISABLE                        _MK_ENUM_CONST(0)
#define PMC_IMPL_PART_AOPG_TCM7_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_ENABLE                 _MK_ENUM_CONST(1)


// Register PMC_IMPL_PART_AOPG_TCM7_POWER_GATE_STATUS_0
#define PMC_IMPL_PART_AOPG_TCM7_POWER_GATE_STATUS_0                     _MK_ADDR_CONST(0x3e0)
#define PMC_IMPL_PART_AOPG_TCM7_POWER_GATE_STATUS_0_SECURE                      0x0
#define PMC_IMPL_PART_AOPG_TCM7_POWER_GATE_STATUS_0_DUAL                        0x0
#define PMC_IMPL_PART_AOPG_TCM7_POWER_GATE_STATUS_0_SCR                         PG_AOPG_TCM7_SCR_0
#define PMC_IMPL_PART_AOPG_TCM7_POWER_GATE_STATUS_0_WORD_COUNT                  0x1
#define PMC_IMPL_PART_AOPG_TCM7_POWER_GATE_STATUS_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM7_POWER_GATE_STATUS_0_RESET_MASK                  _MK_MASK_CONST(0x7)
#define PMC_IMPL_PART_AOPG_TCM7_POWER_GATE_STATUS_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM7_POWER_GATE_STATUS_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM7_POWER_GATE_STATUS_0_READ_MASK                   _MK_MASK_CONST(0x7)
#define PMC_IMPL_PART_AOPG_TCM7_POWER_GATE_STATUS_0_WRITE_MASK                  _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM7_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SHIFT                       _MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_AOPG_TCM7_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_FIELD                       _MK_FIELD_CONST(0x1, PMC_IMPL_PART_AOPG_TCM7_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SHIFT)
#define PMC_IMPL_PART_AOPG_TCM7_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_RANGE                       0:0
#define PMC_IMPL_PART_AOPG_TCM7_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_WOFFSET                     0x0
#define PMC_IMPL_PART_AOPG_TCM7_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_DEFAULT                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM7_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AOPG_TCM7_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM7_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM7_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM7_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AOPG_TCM7_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_INIT_ENUM                   OFF
#define PMC_IMPL_PART_AOPG_TCM7_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_OFF                 _MK_ENUM_CONST(0)
#define PMC_IMPL_PART_AOPG_TCM7_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_ON                  _MK_ENUM_CONST(1)

#define PMC_IMPL_PART_AOPG_TCM7_POWER_GATE_STATUS_0_SRAM_RET_STS_SHIFT                  _MK_SHIFT_CONST(1)
#define PMC_IMPL_PART_AOPG_TCM7_POWER_GATE_STATUS_0_SRAM_RET_STS_FIELD                  _MK_FIELD_CONST(0x1, PMC_IMPL_PART_AOPG_TCM7_POWER_GATE_STATUS_0_SRAM_RET_STS_SHIFT)
#define PMC_IMPL_PART_AOPG_TCM7_POWER_GATE_STATUS_0_SRAM_RET_STS_RANGE                  1:1
#define PMC_IMPL_PART_AOPG_TCM7_POWER_GATE_STATUS_0_SRAM_RET_STS_WOFFSET                        0x0
#define PMC_IMPL_PART_AOPG_TCM7_POWER_GATE_STATUS_0_SRAM_RET_STS_DEFAULT                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM7_POWER_GATE_STATUS_0_SRAM_RET_STS_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AOPG_TCM7_POWER_GATE_STATUS_0_SRAM_RET_STS_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM7_POWER_GATE_STATUS_0_SRAM_RET_STS_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM7_POWER_GATE_STATUS_0_SRAM_RET_STS_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM7_POWER_GATE_STATUS_0_SRAM_RET_STS_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AOPG_TCM7_POWER_GATE_STATUS_0_SRAM_RET_STS_INIT_ENUM                      OFF
#define PMC_IMPL_PART_AOPG_TCM7_POWER_GATE_STATUS_0_SRAM_RET_STS_OFF                    _MK_ENUM_CONST(0)
#define PMC_IMPL_PART_AOPG_TCM7_POWER_GATE_STATUS_0_SRAM_RET_STS_ON                     _MK_ENUM_CONST(1)

#define PMC_IMPL_PART_AOPG_TCM7_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SHIFT                        _MK_SHIFT_CONST(2)
#define PMC_IMPL_PART_AOPG_TCM7_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_FIELD                        _MK_FIELD_CONST(0x1, PMC_IMPL_PART_AOPG_TCM7_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SHIFT)
#define PMC_IMPL_PART_AOPG_TCM7_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_RANGE                        2:2
#define PMC_IMPL_PART_AOPG_TCM7_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_WOFFSET                      0x0
#define PMC_IMPL_PART_AOPG_TCM7_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_DEFAULT                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM7_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AOPG_TCM7_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM7_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM7_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM7_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AOPG_TCM7_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_INIT_ENUM                    OFF
#define PMC_IMPL_PART_AOPG_TCM7_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_OFF                  _MK_ENUM_CONST(0)
#define PMC_IMPL_PART_AOPG_TCM7_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_ON                   _MK_ENUM_CONST(1)


// Register PMC_IMPL_PART_AOPG_TCM7_CLAMP_CONTROL_0
#define PMC_IMPL_PART_AOPG_TCM7_CLAMP_CONTROL_0                 _MK_ADDR_CONST(0x3e4)
#define PMC_IMPL_PART_AOPG_TCM7_CLAMP_CONTROL_0_SECURE                  0x0
#define PMC_IMPL_PART_AOPG_TCM7_CLAMP_CONTROL_0_DUAL                    0x0
#define PMC_IMPL_PART_AOPG_TCM7_CLAMP_CONTROL_0_SCR                     PG_AOPG_TCM7_SCR_0
#define PMC_IMPL_PART_AOPG_TCM7_CLAMP_CONTROL_0_WORD_COUNT                      0x1
#define PMC_IMPL_PART_AOPG_TCM7_CLAMP_CONTROL_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM7_CLAMP_CONTROL_0_RESET_MASK                      _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AOPG_TCM7_CLAMP_CONTROL_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM7_CLAMP_CONTROL_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM7_CLAMP_CONTROL_0_READ_MASK                       _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AOPG_TCM7_CLAMP_CONTROL_0_WRITE_MASK                      _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AOPG_TCM7_CLAMP_CONTROL_0_CLAMP_SHIFT                     _MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_AOPG_TCM7_CLAMP_CONTROL_0_CLAMP_FIELD                     _MK_FIELD_CONST(0x1, PMC_IMPL_PART_AOPG_TCM7_CLAMP_CONTROL_0_CLAMP_SHIFT)
#define PMC_IMPL_PART_AOPG_TCM7_CLAMP_CONTROL_0_CLAMP_RANGE                     0:0
#define PMC_IMPL_PART_AOPG_TCM7_CLAMP_CONTROL_0_CLAMP_WOFFSET                   0x0
#define PMC_IMPL_PART_AOPG_TCM7_CLAMP_CONTROL_0_CLAMP_DEFAULT                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM7_CLAMP_CONTROL_0_CLAMP_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AOPG_TCM7_CLAMP_CONTROL_0_CLAMP_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM7_CLAMP_CONTROL_0_CLAMP_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM7_CLAMP_CONTROL_0_CLAMP_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_TCM7_CLAMP_CONTROL_0_CLAMP_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AOPG_TCM7_CLAMP_CONTROL_0_CLAMP_INIT_ENUM                 OFF
#define PMC_IMPL_PART_AOPG_TCM7_CLAMP_CONTROL_0_CLAMP_OFF                       _MK_ENUM_CONST(0)
#define PMC_IMPL_PART_AOPG_TCM7_CLAMP_CONTROL_0_CLAMP_ON                        _MK_ENUM_CONST(1)


// Register PMC_IMPL_PART_AOPG_CACHE_POWER_GATE_CONTROL_0
#define PMC_IMPL_PART_AOPG_CACHE_POWER_GATE_CONTROL_0                   _MK_ADDR_CONST(0x3e8)
#define PMC_IMPL_PART_AOPG_CACHE_POWER_GATE_CONTROL_0_SECURE                    0x0
#define PMC_IMPL_PART_AOPG_CACHE_POWER_GATE_CONTROL_0_DUAL                      0x0
#define PMC_IMPL_PART_AOPG_CACHE_POWER_GATE_CONTROL_0_SCR                       PG_AOPG_CACHE_SCR_0
#define PMC_IMPL_PART_AOPG_CACHE_POWER_GATE_CONTROL_0_WORD_COUNT                        0x1
#define PMC_IMPL_PART_AOPG_CACHE_POWER_GATE_CONTROL_0_RESET_VAL                         _MK_MASK_CONST(0x80000000)
#define PMC_IMPL_PART_AOPG_CACHE_POWER_GATE_CONTROL_0_RESET_MASK                        _MK_MASK_CONST(0x80000107)
#define PMC_IMPL_PART_AOPG_CACHE_POWER_GATE_CONTROL_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_CACHE_POWER_GATE_CONTROL_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_CACHE_POWER_GATE_CONTROL_0_READ_MASK                         _MK_MASK_CONST(0x80000107)
#define PMC_IMPL_PART_AOPG_CACHE_POWER_GATE_CONTROL_0_WRITE_MASK                        _MK_MASK_CONST(0x80000107)
#define PMC_IMPL_PART_AOPG_CACHE_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SHIFT                 _MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_AOPG_CACHE_POWER_GATE_CONTROL_0_LOGIC_SLEEP_FIELD                 _MK_FIELD_CONST(0x1, PMC_IMPL_PART_AOPG_CACHE_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SHIFT)
#define PMC_IMPL_PART_AOPG_CACHE_POWER_GATE_CONTROL_0_LOGIC_SLEEP_RANGE                 0:0
#define PMC_IMPL_PART_AOPG_CACHE_POWER_GATE_CONTROL_0_LOGIC_SLEEP_WOFFSET                       0x0
#define PMC_IMPL_PART_AOPG_CACHE_POWER_GATE_CONTROL_0_LOGIC_SLEEP_DEFAULT                       _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_CACHE_POWER_GATE_CONTROL_0_LOGIC_SLEEP_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AOPG_CACHE_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_CACHE_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_CACHE_POWER_GATE_CONTROL_0_LOGIC_SLEEP_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_CACHE_POWER_GATE_CONTROL_0_LOGIC_SLEEP_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AOPG_CACHE_POWER_GATE_CONTROL_0_LOGIC_SLEEP_INIT_ENUM                     OFF
#define PMC_IMPL_PART_AOPG_CACHE_POWER_GATE_CONTROL_0_LOGIC_SLEEP_OFF                   _MK_ENUM_CONST(0)
#define PMC_IMPL_PART_AOPG_CACHE_POWER_GATE_CONTROL_0_LOGIC_SLEEP_ON                    _MK_ENUM_CONST(1)

#define PMC_IMPL_PART_AOPG_CACHE_POWER_GATE_CONTROL_0_SRAM_RET_EN_SHIFT                 _MK_SHIFT_CONST(1)
#define PMC_IMPL_PART_AOPG_CACHE_POWER_GATE_CONTROL_0_SRAM_RET_EN_FIELD                 _MK_FIELD_CONST(0x1, PMC_IMPL_PART_AOPG_CACHE_POWER_GATE_CONTROL_0_SRAM_RET_EN_SHIFT)
#define PMC_IMPL_PART_AOPG_CACHE_POWER_GATE_CONTROL_0_SRAM_RET_EN_RANGE                 1:1
#define PMC_IMPL_PART_AOPG_CACHE_POWER_GATE_CONTROL_0_SRAM_RET_EN_WOFFSET                       0x0
#define PMC_IMPL_PART_AOPG_CACHE_POWER_GATE_CONTROL_0_SRAM_RET_EN_DEFAULT                       _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_CACHE_POWER_GATE_CONTROL_0_SRAM_RET_EN_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AOPG_CACHE_POWER_GATE_CONTROL_0_SRAM_RET_EN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_CACHE_POWER_GATE_CONTROL_0_SRAM_RET_EN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_CACHE_POWER_GATE_CONTROL_0_SRAM_RET_EN_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_CACHE_POWER_GATE_CONTROL_0_SRAM_RET_EN_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AOPG_CACHE_POWER_GATE_CONTROL_0_SRAM_RET_EN_INIT_ENUM                     OFF
#define PMC_IMPL_PART_AOPG_CACHE_POWER_GATE_CONTROL_0_SRAM_RET_EN_OFF                   _MK_ENUM_CONST(0)
#define PMC_IMPL_PART_AOPG_CACHE_POWER_GATE_CONTROL_0_SRAM_RET_EN_ON                    _MK_ENUM_CONST(1)

#define PMC_IMPL_PART_AOPG_CACHE_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SHIFT                       _MK_SHIFT_CONST(2)
#define PMC_IMPL_PART_AOPG_CACHE_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_FIELD                       _MK_FIELD_CONST(0x1, PMC_IMPL_PART_AOPG_CACHE_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SHIFT)
#define PMC_IMPL_PART_AOPG_CACHE_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_RANGE                       2:2
#define PMC_IMPL_PART_AOPG_CACHE_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_WOFFSET                     0x0
#define PMC_IMPL_PART_AOPG_CACHE_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_DEFAULT                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_CACHE_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AOPG_CACHE_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_CACHE_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_CACHE_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_CACHE_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AOPG_CACHE_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_INIT_ENUM                   OFF
#define PMC_IMPL_PART_AOPG_CACHE_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_OFF                 _MK_ENUM_CONST(0)
#define PMC_IMPL_PART_AOPG_CACHE_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_ON                  _MK_ENUM_CONST(1)

#define PMC_IMPL_PART_AOPG_CACHE_POWER_GATE_CONTROL_0_START_SHIFT                       _MK_SHIFT_CONST(8)
#define PMC_IMPL_PART_AOPG_CACHE_POWER_GATE_CONTROL_0_START_FIELD                       _MK_FIELD_CONST(0x1, PMC_IMPL_PART_AOPG_CACHE_POWER_GATE_CONTROL_0_START_SHIFT)
#define PMC_IMPL_PART_AOPG_CACHE_POWER_GATE_CONTROL_0_START_RANGE                       8:8
#define PMC_IMPL_PART_AOPG_CACHE_POWER_GATE_CONTROL_0_START_WOFFSET                     0x0
#define PMC_IMPL_PART_AOPG_CACHE_POWER_GATE_CONTROL_0_START_DEFAULT                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_CACHE_POWER_GATE_CONTROL_0_START_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AOPG_CACHE_POWER_GATE_CONTROL_0_START_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_CACHE_POWER_GATE_CONTROL_0_START_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_CACHE_POWER_GATE_CONTROL_0_START_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_CACHE_POWER_GATE_CONTROL_0_START_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AOPG_CACHE_POWER_GATE_CONTROL_0_START_INIT_ENUM                   DONE
#define PMC_IMPL_PART_AOPG_CACHE_POWER_GATE_CONTROL_0_START_DONE                        _MK_ENUM_CONST(0)
#define PMC_IMPL_PART_AOPG_CACHE_POWER_GATE_CONTROL_0_START_PENDING                     _MK_ENUM_CONST(1)

#define PMC_IMPL_PART_AOPG_CACHE_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SHIFT                 _MK_SHIFT_CONST(31)
#define PMC_IMPL_PART_AOPG_CACHE_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_FIELD                 _MK_FIELD_CONST(0x1, PMC_IMPL_PART_AOPG_CACHE_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SHIFT)
#define PMC_IMPL_PART_AOPG_CACHE_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_RANGE                 31:31
#define PMC_IMPL_PART_AOPG_CACHE_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_WOFFSET                       0x0
#define PMC_IMPL_PART_AOPG_CACHE_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_DEFAULT                       _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AOPG_CACHE_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AOPG_CACHE_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_CACHE_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_CACHE_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_CACHE_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AOPG_CACHE_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_INIT_ENUM                     ENABLE
#define PMC_IMPL_PART_AOPG_CACHE_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_DISABLE                       _MK_ENUM_CONST(0)
#define PMC_IMPL_PART_AOPG_CACHE_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_ENABLE                        _MK_ENUM_CONST(1)


// Register PMC_IMPL_PART_AOPG_CACHE_POWER_GATE_STATUS_0
#define PMC_IMPL_PART_AOPG_CACHE_POWER_GATE_STATUS_0                    _MK_ADDR_CONST(0x3ec)
#define PMC_IMPL_PART_AOPG_CACHE_POWER_GATE_STATUS_0_SECURE                     0x0
#define PMC_IMPL_PART_AOPG_CACHE_POWER_GATE_STATUS_0_DUAL                       0x0
#define PMC_IMPL_PART_AOPG_CACHE_POWER_GATE_STATUS_0_SCR                        PG_AOPG_CACHE_SCR_0
#define PMC_IMPL_PART_AOPG_CACHE_POWER_GATE_STATUS_0_WORD_COUNT                         0x1
#define PMC_IMPL_PART_AOPG_CACHE_POWER_GATE_STATUS_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_CACHE_POWER_GATE_STATUS_0_RESET_MASK                         _MK_MASK_CONST(0x7)
#define PMC_IMPL_PART_AOPG_CACHE_POWER_GATE_STATUS_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_CACHE_POWER_GATE_STATUS_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_CACHE_POWER_GATE_STATUS_0_READ_MASK                  _MK_MASK_CONST(0x7)
#define PMC_IMPL_PART_AOPG_CACHE_POWER_GATE_STATUS_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_CACHE_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SHIFT                      _MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_AOPG_CACHE_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_FIELD                      _MK_FIELD_CONST(0x1, PMC_IMPL_PART_AOPG_CACHE_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SHIFT)
#define PMC_IMPL_PART_AOPG_CACHE_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_RANGE                      0:0
#define PMC_IMPL_PART_AOPG_CACHE_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_WOFFSET                    0x0
#define PMC_IMPL_PART_AOPG_CACHE_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_DEFAULT                    _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_CACHE_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AOPG_CACHE_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_CACHE_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_CACHE_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_CACHE_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AOPG_CACHE_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_INIT_ENUM                  OFF
#define PMC_IMPL_PART_AOPG_CACHE_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_OFF                        _MK_ENUM_CONST(0)
#define PMC_IMPL_PART_AOPG_CACHE_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_ON                 _MK_ENUM_CONST(1)

#define PMC_IMPL_PART_AOPG_CACHE_POWER_GATE_STATUS_0_SRAM_RET_STS_SHIFT                 _MK_SHIFT_CONST(1)
#define PMC_IMPL_PART_AOPG_CACHE_POWER_GATE_STATUS_0_SRAM_RET_STS_FIELD                 _MK_FIELD_CONST(0x1, PMC_IMPL_PART_AOPG_CACHE_POWER_GATE_STATUS_0_SRAM_RET_STS_SHIFT)
#define PMC_IMPL_PART_AOPG_CACHE_POWER_GATE_STATUS_0_SRAM_RET_STS_RANGE                 1:1
#define PMC_IMPL_PART_AOPG_CACHE_POWER_GATE_STATUS_0_SRAM_RET_STS_WOFFSET                       0x0
#define PMC_IMPL_PART_AOPG_CACHE_POWER_GATE_STATUS_0_SRAM_RET_STS_DEFAULT                       _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_CACHE_POWER_GATE_STATUS_0_SRAM_RET_STS_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AOPG_CACHE_POWER_GATE_STATUS_0_SRAM_RET_STS_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_CACHE_POWER_GATE_STATUS_0_SRAM_RET_STS_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_CACHE_POWER_GATE_STATUS_0_SRAM_RET_STS_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_CACHE_POWER_GATE_STATUS_0_SRAM_RET_STS_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AOPG_CACHE_POWER_GATE_STATUS_0_SRAM_RET_STS_INIT_ENUM                     OFF
#define PMC_IMPL_PART_AOPG_CACHE_POWER_GATE_STATUS_0_SRAM_RET_STS_OFF                   _MK_ENUM_CONST(0)
#define PMC_IMPL_PART_AOPG_CACHE_POWER_GATE_STATUS_0_SRAM_RET_STS_ON                    _MK_ENUM_CONST(1)

#define PMC_IMPL_PART_AOPG_CACHE_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SHIFT                       _MK_SHIFT_CONST(2)
#define PMC_IMPL_PART_AOPG_CACHE_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_FIELD                       _MK_FIELD_CONST(0x1, PMC_IMPL_PART_AOPG_CACHE_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SHIFT)
#define PMC_IMPL_PART_AOPG_CACHE_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_RANGE                       2:2
#define PMC_IMPL_PART_AOPG_CACHE_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_WOFFSET                     0x0
#define PMC_IMPL_PART_AOPG_CACHE_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_DEFAULT                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_CACHE_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AOPG_CACHE_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_CACHE_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_CACHE_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_CACHE_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AOPG_CACHE_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_INIT_ENUM                   OFF
#define PMC_IMPL_PART_AOPG_CACHE_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_OFF                 _MK_ENUM_CONST(0)
#define PMC_IMPL_PART_AOPG_CACHE_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_ON                  _MK_ENUM_CONST(1)


// Register PMC_IMPL_PART_AOPG_CACHE_CLAMP_CONTROL_0
#define PMC_IMPL_PART_AOPG_CACHE_CLAMP_CONTROL_0                        _MK_ADDR_CONST(0x3f0)
#define PMC_IMPL_PART_AOPG_CACHE_CLAMP_CONTROL_0_SECURE                         0x0
#define PMC_IMPL_PART_AOPG_CACHE_CLAMP_CONTROL_0_DUAL                   0x0
#define PMC_IMPL_PART_AOPG_CACHE_CLAMP_CONTROL_0_SCR                    PG_AOPG_CACHE_SCR_0
#define PMC_IMPL_PART_AOPG_CACHE_CLAMP_CONTROL_0_WORD_COUNT                     0x1
#define PMC_IMPL_PART_AOPG_CACHE_CLAMP_CONTROL_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_CACHE_CLAMP_CONTROL_0_RESET_MASK                     _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AOPG_CACHE_CLAMP_CONTROL_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_CACHE_CLAMP_CONTROL_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_CACHE_CLAMP_CONTROL_0_READ_MASK                      _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AOPG_CACHE_CLAMP_CONTROL_0_WRITE_MASK                     _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AOPG_CACHE_CLAMP_CONTROL_0_CLAMP_SHIFT                    _MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_AOPG_CACHE_CLAMP_CONTROL_0_CLAMP_FIELD                    _MK_FIELD_CONST(0x1, PMC_IMPL_PART_AOPG_CACHE_CLAMP_CONTROL_0_CLAMP_SHIFT)
#define PMC_IMPL_PART_AOPG_CACHE_CLAMP_CONTROL_0_CLAMP_RANGE                    0:0
#define PMC_IMPL_PART_AOPG_CACHE_CLAMP_CONTROL_0_CLAMP_WOFFSET                  0x0
#define PMC_IMPL_PART_AOPG_CACHE_CLAMP_CONTROL_0_CLAMP_DEFAULT                  _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_CACHE_CLAMP_CONTROL_0_CLAMP_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AOPG_CACHE_CLAMP_CONTROL_0_CLAMP_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_CACHE_CLAMP_CONTROL_0_CLAMP_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_CACHE_CLAMP_CONTROL_0_CLAMP_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_CACHE_CLAMP_CONTROL_0_CLAMP_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AOPG_CACHE_CLAMP_CONTROL_0_CLAMP_INIT_ENUM                        OFF
#define PMC_IMPL_PART_AOPG_CACHE_CLAMP_CONTROL_0_CLAMP_OFF                      _MK_ENUM_CONST(0)
#define PMC_IMPL_PART_AOPG_CACHE_CLAMP_CONTROL_0_CLAMP_ON                       _MK_ENUM_CONST(1)


// Register PMC_IMPL_PART_AOPG_CAN0_POWER_GATE_CONTROL_0
#define PMC_IMPL_PART_AOPG_CAN0_POWER_GATE_CONTROL_0                    _MK_ADDR_CONST(0x3f4)
#define PMC_IMPL_PART_AOPG_CAN0_POWER_GATE_CONTROL_0_SECURE                     0x0
#define PMC_IMPL_PART_AOPG_CAN0_POWER_GATE_CONTROL_0_DUAL                       0x0
#define PMC_IMPL_PART_AOPG_CAN0_POWER_GATE_CONTROL_0_SCR                        PG_AOPG_CAN0_SCR_0
#define PMC_IMPL_PART_AOPG_CAN0_POWER_GATE_CONTROL_0_WORD_COUNT                         0x1
#define PMC_IMPL_PART_AOPG_CAN0_POWER_GATE_CONTROL_0_RESET_VAL                  _MK_MASK_CONST(0x80000000)
#define PMC_IMPL_PART_AOPG_CAN0_POWER_GATE_CONTROL_0_RESET_MASK                         _MK_MASK_CONST(0x80000107)
#define PMC_IMPL_PART_AOPG_CAN0_POWER_GATE_CONTROL_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_CAN0_POWER_GATE_CONTROL_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_CAN0_POWER_GATE_CONTROL_0_READ_MASK                  _MK_MASK_CONST(0x80000107)
#define PMC_IMPL_PART_AOPG_CAN0_POWER_GATE_CONTROL_0_WRITE_MASK                         _MK_MASK_CONST(0x80000107)
#define PMC_IMPL_PART_AOPG_CAN0_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SHIFT                  _MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_AOPG_CAN0_POWER_GATE_CONTROL_0_LOGIC_SLEEP_FIELD                  _MK_FIELD_CONST(0x1, PMC_IMPL_PART_AOPG_CAN0_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SHIFT)
#define PMC_IMPL_PART_AOPG_CAN0_POWER_GATE_CONTROL_0_LOGIC_SLEEP_RANGE                  0:0
#define PMC_IMPL_PART_AOPG_CAN0_POWER_GATE_CONTROL_0_LOGIC_SLEEP_WOFFSET                        0x0
#define PMC_IMPL_PART_AOPG_CAN0_POWER_GATE_CONTROL_0_LOGIC_SLEEP_DEFAULT                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_CAN0_POWER_GATE_CONTROL_0_LOGIC_SLEEP_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AOPG_CAN0_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_CAN0_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_CAN0_POWER_GATE_CONTROL_0_LOGIC_SLEEP_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_CAN0_POWER_GATE_CONTROL_0_LOGIC_SLEEP_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AOPG_CAN0_POWER_GATE_CONTROL_0_LOGIC_SLEEP_INIT_ENUM                      OFF
#define PMC_IMPL_PART_AOPG_CAN0_POWER_GATE_CONTROL_0_LOGIC_SLEEP_OFF                    _MK_ENUM_CONST(0)
#define PMC_IMPL_PART_AOPG_CAN0_POWER_GATE_CONTROL_0_LOGIC_SLEEP_ON                     _MK_ENUM_CONST(1)

#define PMC_IMPL_PART_AOPG_CAN0_POWER_GATE_CONTROL_0_SRAM_RET_EN_SHIFT                  _MK_SHIFT_CONST(1)
#define PMC_IMPL_PART_AOPG_CAN0_POWER_GATE_CONTROL_0_SRAM_RET_EN_FIELD                  _MK_FIELD_CONST(0x1, PMC_IMPL_PART_AOPG_CAN0_POWER_GATE_CONTROL_0_SRAM_RET_EN_SHIFT)
#define PMC_IMPL_PART_AOPG_CAN0_POWER_GATE_CONTROL_0_SRAM_RET_EN_RANGE                  1:1
#define PMC_IMPL_PART_AOPG_CAN0_POWER_GATE_CONTROL_0_SRAM_RET_EN_WOFFSET                        0x0
#define PMC_IMPL_PART_AOPG_CAN0_POWER_GATE_CONTROL_0_SRAM_RET_EN_DEFAULT                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_CAN0_POWER_GATE_CONTROL_0_SRAM_RET_EN_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AOPG_CAN0_POWER_GATE_CONTROL_0_SRAM_RET_EN_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_CAN0_POWER_GATE_CONTROL_0_SRAM_RET_EN_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_CAN0_POWER_GATE_CONTROL_0_SRAM_RET_EN_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_CAN0_POWER_GATE_CONTROL_0_SRAM_RET_EN_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AOPG_CAN0_POWER_GATE_CONTROL_0_SRAM_RET_EN_INIT_ENUM                      OFF
#define PMC_IMPL_PART_AOPG_CAN0_POWER_GATE_CONTROL_0_SRAM_RET_EN_OFF                    _MK_ENUM_CONST(0)
#define PMC_IMPL_PART_AOPG_CAN0_POWER_GATE_CONTROL_0_SRAM_RET_EN_ON                     _MK_ENUM_CONST(1)

#define PMC_IMPL_PART_AOPG_CAN0_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SHIFT                        _MK_SHIFT_CONST(2)
#define PMC_IMPL_PART_AOPG_CAN0_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_FIELD                        _MK_FIELD_CONST(0x1, PMC_IMPL_PART_AOPG_CAN0_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SHIFT)
#define PMC_IMPL_PART_AOPG_CAN0_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_RANGE                        2:2
#define PMC_IMPL_PART_AOPG_CAN0_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_WOFFSET                      0x0
#define PMC_IMPL_PART_AOPG_CAN0_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_DEFAULT                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_CAN0_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AOPG_CAN0_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_CAN0_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_CAN0_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_CAN0_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AOPG_CAN0_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_INIT_ENUM                    OFF
#define PMC_IMPL_PART_AOPG_CAN0_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_OFF                  _MK_ENUM_CONST(0)
#define PMC_IMPL_PART_AOPG_CAN0_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_ON                   _MK_ENUM_CONST(1)

#define PMC_IMPL_PART_AOPG_CAN0_POWER_GATE_CONTROL_0_START_SHIFT                        _MK_SHIFT_CONST(8)
#define PMC_IMPL_PART_AOPG_CAN0_POWER_GATE_CONTROL_0_START_FIELD                        _MK_FIELD_CONST(0x1, PMC_IMPL_PART_AOPG_CAN0_POWER_GATE_CONTROL_0_START_SHIFT)
#define PMC_IMPL_PART_AOPG_CAN0_POWER_GATE_CONTROL_0_START_RANGE                        8:8
#define PMC_IMPL_PART_AOPG_CAN0_POWER_GATE_CONTROL_0_START_WOFFSET                      0x0
#define PMC_IMPL_PART_AOPG_CAN0_POWER_GATE_CONTROL_0_START_DEFAULT                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_CAN0_POWER_GATE_CONTROL_0_START_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AOPG_CAN0_POWER_GATE_CONTROL_0_START_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_CAN0_POWER_GATE_CONTROL_0_START_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_CAN0_POWER_GATE_CONTROL_0_START_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_CAN0_POWER_GATE_CONTROL_0_START_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AOPG_CAN0_POWER_GATE_CONTROL_0_START_INIT_ENUM                    DONE
#define PMC_IMPL_PART_AOPG_CAN0_POWER_GATE_CONTROL_0_START_DONE                 _MK_ENUM_CONST(0)
#define PMC_IMPL_PART_AOPG_CAN0_POWER_GATE_CONTROL_0_START_PENDING                      _MK_ENUM_CONST(1)

#define PMC_IMPL_PART_AOPG_CAN0_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SHIFT                  _MK_SHIFT_CONST(31)
#define PMC_IMPL_PART_AOPG_CAN0_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_FIELD                  _MK_FIELD_CONST(0x1, PMC_IMPL_PART_AOPG_CAN0_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SHIFT)
#define PMC_IMPL_PART_AOPG_CAN0_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_RANGE                  31:31
#define PMC_IMPL_PART_AOPG_CAN0_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_WOFFSET                        0x0
#define PMC_IMPL_PART_AOPG_CAN0_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_DEFAULT                        _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AOPG_CAN0_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AOPG_CAN0_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_CAN0_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_CAN0_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_CAN0_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AOPG_CAN0_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_INIT_ENUM                      ENABLE
#define PMC_IMPL_PART_AOPG_CAN0_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_DISABLE                        _MK_ENUM_CONST(0)
#define PMC_IMPL_PART_AOPG_CAN0_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_ENABLE                 _MK_ENUM_CONST(1)


// Register PMC_IMPL_PART_AOPG_CAN0_POWER_GATE_STATUS_0
#define PMC_IMPL_PART_AOPG_CAN0_POWER_GATE_STATUS_0                     _MK_ADDR_CONST(0x3f8)
#define PMC_IMPL_PART_AOPG_CAN0_POWER_GATE_STATUS_0_SECURE                      0x0
#define PMC_IMPL_PART_AOPG_CAN0_POWER_GATE_STATUS_0_DUAL                        0x0
#define PMC_IMPL_PART_AOPG_CAN0_POWER_GATE_STATUS_0_SCR                         PG_AOPG_CAN0_SCR_0
#define PMC_IMPL_PART_AOPG_CAN0_POWER_GATE_STATUS_0_WORD_COUNT                  0x1
#define PMC_IMPL_PART_AOPG_CAN0_POWER_GATE_STATUS_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_CAN0_POWER_GATE_STATUS_0_RESET_MASK                  _MK_MASK_CONST(0x7)
#define PMC_IMPL_PART_AOPG_CAN0_POWER_GATE_STATUS_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_CAN0_POWER_GATE_STATUS_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_CAN0_POWER_GATE_STATUS_0_READ_MASK                   _MK_MASK_CONST(0x7)
#define PMC_IMPL_PART_AOPG_CAN0_POWER_GATE_STATUS_0_WRITE_MASK                  _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_CAN0_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SHIFT                       _MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_AOPG_CAN0_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_FIELD                       _MK_FIELD_CONST(0x1, PMC_IMPL_PART_AOPG_CAN0_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SHIFT)
#define PMC_IMPL_PART_AOPG_CAN0_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_RANGE                       0:0
#define PMC_IMPL_PART_AOPG_CAN0_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_WOFFSET                     0x0
#define PMC_IMPL_PART_AOPG_CAN0_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_DEFAULT                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_CAN0_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AOPG_CAN0_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_CAN0_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_CAN0_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_CAN0_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AOPG_CAN0_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_INIT_ENUM                   OFF
#define PMC_IMPL_PART_AOPG_CAN0_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_OFF                 _MK_ENUM_CONST(0)
#define PMC_IMPL_PART_AOPG_CAN0_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_ON                  _MK_ENUM_CONST(1)

#define PMC_IMPL_PART_AOPG_CAN0_POWER_GATE_STATUS_0_SRAM_RET_STS_SHIFT                  _MK_SHIFT_CONST(1)
#define PMC_IMPL_PART_AOPG_CAN0_POWER_GATE_STATUS_0_SRAM_RET_STS_FIELD                  _MK_FIELD_CONST(0x1, PMC_IMPL_PART_AOPG_CAN0_POWER_GATE_STATUS_0_SRAM_RET_STS_SHIFT)
#define PMC_IMPL_PART_AOPG_CAN0_POWER_GATE_STATUS_0_SRAM_RET_STS_RANGE                  1:1
#define PMC_IMPL_PART_AOPG_CAN0_POWER_GATE_STATUS_0_SRAM_RET_STS_WOFFSET                        0x0
#define PMC_IMPL_PART_AOPG_CAN0_POWER_GATE_STATUS_0_SRAM_RET_STS_DEFAULT                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_CAN0_POWER_GATE_STATUS_0_SRAM_RET_STS_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AOPG_CAN0_POWER_GATE_STATUS_0_SRAM_RET_STS_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_CAN0_POWER_GATE_STATUS_0_SRAM_RET_STS_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_CAN0_POWER_GATE_STATUS_0_SRAM_RET_STS_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_CAN0_POWER_GATE_STATUS_0_SRAM_RET_STS_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AOPG_CAN0_POWER_GATE_STATUS_0_SRAM_RET_STS_INIT_ENUM                      OFF
#define PMC_IMPL_PART_AOPG_CAN0_POWER_GATE_STATUS_0_SRAM_RET_STS_OFF                    _MK_ENUM_CONST(0)
#define PMC_IMPL_PART_AOPG_CAN0_POWER_GATE_STATUS_0_SRAM_RET_STS_ON                     _MK_ENUM_CONST(1)

#define PMC_IMPL_PART_AOPG_CAN0_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SHIFT                        _MK_SHIFT_CONST(2)
#define PMC_IMPL_PART_AOPG_CAN0_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_FIELD                        _MK_FIELD_CONST(0x1, PMC_IMPL_PART_AOPG_CAN0_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SHIFT)
#define PMC_IMPL_PART_AOPG_CAN0_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_RANGE                        2:2
#define PMC_IMPL_PART_AOPG_CAN0_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_WOFFSET                      0x0
#define PMC_IMPL_PART_AOPG_CAN0_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_DEFAULT                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_CAN0_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AOPG_CAN0_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_CAN0_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_CAN0_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_CAN0_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AOPG_CAN0_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_INIT_ENUM                    OFF
#define PMC_IMPL_PART_AOPG_CAN0_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_OFF                  _MK_ENUM_CONST(0)
#define PMC_IMPL_PART_AOPG_CAN0_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_ON                   _MK_ENUM_CONST(1)


// Register PMC_IMPL_PART_AOPG_CAN0_CLAMP_CONTROL_0
#define PMC_IMPL_PART_AOPG_CAN0_CLAMP_CONTROL_0                 _MK_ADDR_CONST(0x3fc)
#define PMC_IMPL_PART_AOPG_CAN0_CLAMP_CONTROL_0_SECURE                  0x0
#define PMC_IMPL_PART_AOPG_CAN0_CLAMP_CONTROL_0_DUAL                    0x0
#define PMC_IMPL_PART_AOPG_CAN0_CLAMP_CONTROL_0_SCR                     PG_AOPG_CAN0_SCR_0
#define PMC_IMPL_PART_AOPG_CAN0_CLAMP_CONTROL_0_WORD_COUNT                      0x1
#define PMC_IMPL_PART_AOPG_CAN0_CLAMP_CONTROL_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_CAN0_CLAMP_CONTROL_0_RESET_MASK                      _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AOPG_CAN0_CLAMP_CONTROL_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_CAN0_CLAMP_CONTROL_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_CAN0_CLAMP_CONTROL_0_READ_MASK                       _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AOPG_CAN0_CLAMP_CONTROL_0_WRITE_MASK                      _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AOPG_CAN0_CLAMP_CONTROL_0_CLAMP_SHIFT                     _MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_AOPG_CAN0_CLAMP_CONTROL_0_CLAMP_FIELD                     _MK_FIELD_CONST(0x1, PMC_IMPL_PART_AOPG_CAN0_CLAMP_CONTROL_0_CLAMP_SHIFT)
#define PMC_IMPL_PART_AOPG_CAN0_CLAMP_CONTROL_0_CLAMP_RANGE                     0:0
#define PMC_IMPL_PART_AOPG_CAN0_CLAMP_CONTROL_0_CLAMP_WOFFSET                   0x0
#define PMC_IMPL_PART_AOPG_CAN0_CLAMP_CONTROL_0_CLAMP_DEFAULT                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_CAN0_CLAMP_CONTROL_0_CLAMP_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AOPG_CAN0_CLAMP_CONTROL_0_CLAMP_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_CAN0_CLAMP_CONTROL_0_CLAMP_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_CAN0_CLAMP_CONTROL_0_CLAMP_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_CAN0_CLAMP_CONTROL_0_CLAMP_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AOPG_CAN0_CLAMP_CONTROL_0_CLAMP_INIT_ENUM                 OFF
#define PMC_IMPL_PART_AOPG_CAN0_CLAMP_CONTROL_0_CLAMP_OFF                       _MK_ENUM_CONST(0)
#define PMC_IMPL_PART_AOPG_CAN0_CLAMP_CONTROL_0_CLAMP_ON                        _MK_ENUM_CONST(1)


// Register PMC_IMPL_PART_AOPG_CAN1_POWER_GATE_CONTROL_0
#define PMC_IMPL_PART_AOPG_CAN1_POWER_GATE_CONTROL_0                    _MK_ADDR_CONST(0x400)
#define PMC_IMPL_PART_AOPG_CAN1_POWER_GATE_CONTROL_0_SECURE                     0x0
#define PMC_IMPL_PART_AOPG_CAN1_POWER_GATE_CONTROL_0_DUAL                       0x0
#define PMC_IMPL_PART_AOPG_CAN1_POWER_GATE_CONTROL_0_SCR                        PG_AOPG_CAN1_SCR_0
#define PMC_IMPL_PART_AOPG_CAN1_POWER_GATE_CONTROL_0_WORD_COUNT                         0x1
#define PMC_IMPL_PART_AOPG_CAN1_POWER_GATE_CONTROL_0_RESET_VAL                  _MK_MASK_CONST(0x80000000)
#define PMC_IMPL_PART_AOPG_CAN1_POWER_GATE_CONTROL_0_RESET_MASK                         _MK_MASK_CONST(0x80000107)
#define PMC_IMPL_PART_AOPG_CAN1_POWER_GATE_CONTROL_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_CAN1_POWER_GATE_CONTROL_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_CAN1_POWER_GATE_CONTROL_0_READ_MASK                  _MK_MASK_CONST(0x80000107)
#define PMC_IMPL_PART_AOPG_CAN1_POWER_GATE_CONTROL_0_WRITE_MASK                         _MK_MASK_CONST(0x80000107)
#define PMC_IMPL_PART_AOPG_CAN1_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SHIFT                  _MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_AOPG_CAN1_POWER_GATE_CONTROL_0_LOGIC_SLEEP_FIELD                  _MK_FIELD_CONST(0x1, PMC_IMPL_PART_AOPG_CAN1_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SHIFT)
#define PMC_IMPL_PART_AOPG_CAN1_POWER_GATE_CONTROL_0_LOGIC_SLEEP_RANGE                  0:0
#define PMC_IMPL_PART_AOPG_CAN1_POWER_GATE_CONTROL_0_LOGIC_SLEEP_WOFFSET                        0x0
#define PMC_IMPL_PART_AOPG_CAN1_POWER_GATE_CONTROL_0_LOGIC_SLEEP_DEFAULT                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_CAN1_POWER_GATE_CONTROL_0_LOGIC_SLEEP_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AOPG_CAN1_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_CAN1_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_CAN1_POWER_GATE_CONTROL_0_LOGIC_SLEEP_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_CAN1_POWER_GATE_CONTROL_0_LOGIC_SLEEP_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AOPG_CAN1_POWER_GATE_CONTROL_0_LOGIC_SLEEP_INIT_ENUM                      OFF
#define PMC_IMPL_PART_AOPG_CAN1_POWER_GATE_CONTROL_0_LOGIC_SLEEP_OFF                    _MK_ENUM_CONST(0)
#define PMC_IMPL_PART_AOPG_CAN1_POWER_GATE_CONTROL_0_LOGIC_SLEEP_ON                     _MK_ENUM_CONST(1)

#define PMC_IMPL_PART_AOPG_CAN1_POWER_GATE_CONTROL_0_SRAM_RET_EN_SHIFT                  _MK_SHIFT_CONST(1)
#define PMC_IMPL_PART_AOPG_CAN1_POWER_GATE_CONTROL_0_SRAM_RET_EN_FIELD                  _MK_FIELD_CONST(0x1, PMC_IMPL_PART_AOPG_CAN1_POWER_GATE_CONTROL_0_SRAM_RET_EN_SHIFT)
#define PMC_IMPL_PART_AOPG_CAN1_POWER_GATE_CONTROL_0_SRAM_RET_EN_RANGE                  1:1
#define PMC_IMPL_PART_AOPG_CAN1_POWER_GATE_CONTROL_0_SRAM_RET_EN_WOFFSET                        0x0
#define PMC_IMPL_PART_AOPG_CAN1_POWER_GATE_CONTROL_0_SRAM_RET_EN_DEFAULT                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_CAN1_POWER_GATE_CONTROL_0_SRAM_RET_EN_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AOPG_CAN1_POWER_GATE_CONTROL_0_SRAM_RET_EN_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_CAN1_POWER_GATE_CONTROL_0_SRAM_RET_EN_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_CAN1_POWER_GATE_CONTROL_0_SRAM_RET_EN_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_CAN1_POWER_GATE_CONTROL_0_SRAM_RET_EN_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AOPG_CAN1_POWER_GATE_CONTROL_0_SRAM_RET_EN_INIT_ENUM                      OFF
#define PMC_IMPL_PART_AOPG_CAN1_POWER_GATE_CONTROL_0_SRAM_RET_EN_OFF                    _MK_ENUM_CONST(0)
#define PMC_IMPL_PART_AOPG_CAN1_POWER_GATE_CONTROL_0_SRAM_RET_EN_ON                     _MK_ENUM_CONST(1)

#define PMC_IMPL_PART_AOPG_CAN1_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SHIFT                        _MK_SHIFT_CONST(2)
#define PMC_IMPL_PART_AOPG_CAN1_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_FIELD                        _MK_FIELD_CONST(0x1, PMC_IMPL_PART_AOPG_CAN1_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SHIFT)
#define PMC_IMPL_PART_AOPG_CAN1_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_RANGE                        2:2
#define PMC_IMPL_PART_AOPG_CAN1_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_WOFFSET                      0x0
#define PMC_IMPL_PART_AOPG_CAN1_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_DEFAULT                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_CAN1_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AOPG_CAN1_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_CAN1_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_CAN1_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_CAN1_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AOPG_CAN1_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_INIT_ENUM                    OFF
#define PMC_IMPL_PART_AOPG_CAN1_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_OFF                  _MK_ENUM_CONST(0)
#define PMC_IMPL_PART_AOPG_CAN1_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_ON                   _MK_ENUM_CONST(1)

#define PMC_IMPL_PART_AOPG_CAN1_POWER_GATE_CONTROL_0_START_SHIFT                        _MK_SHIFT_CONST(8)
#define PMC_IMPL_PART_AOPG_CAN1_POWER_GATE_CONTROL_0_START_FIELD                        _MK_FIELD_CONST(0x1, PMC_IMPL_PART_AOPG_CAN1_POWER_GATE_CONTROL_0_START_SHIFT)
#define PMC_IMPL_PART_AOPG_CAN1_POWER_GATE_CONTROL_0_START_RANGE                        8:8
#define PMC_IMPL_PART_AOPG_CAN1_POWER_GATE_CONTROL_0_START_WOFFSET                      0x0
#define PMC_IMPL_PART_AOPG_CAN1_POWER_GATE_CONTROL_0_START_DEFAULT                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_CAN1_POWER_GATE_CONTROL_0_START_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AOPG_CAN1_POWER_GATE_CONTROL_0_START_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_CAN1_POWER_GATE_CONTROL_0_START_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_CAN1_POWER_GATE_CONTROL_0_START_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_CAN1_POWER_GATE_CONTROL_0_START_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AOPG_CAN1_POWER_GATE_CONTROL_0_START_INIT_ENUM                    DONE
#define PMC_IMPL_PART_AOPG_CAN1_POWER_GATE_CONTROL_0_START_DONE                 _MK_ENUM_CONST(0)
#define PMC_IMPL_PART_AOPG_CAN1_POWER_GATE_CONTROL_0_START_PENDING                      _MK_ENUM_CONST(1)

#define PMC_IMPL_PART_AOPG_CAN1_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SHIFT                  _MK_SHIFT_CONST(31)
#define PMC_IMPL_PART_AOPG_CAN1_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_FIELD                  _MK_FIELD_CONST(0x1, PMC_IMPL_PART_AOPG_CAN1_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SHIFT)
#define PMC_IMPL_PART_AOPG_CAN1_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_RANGE                  31:31
#define PMC_IMPL_PART_AOPG_CAN1_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_WOFFSET                        0x0
#define PMC_IMPL_PART_AOPG_CAN1_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_DEFAULT                        _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AOPG_CAN1_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AOPG_CAN1_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_CAN1_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_CAN1_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_CAN1_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AOPG_CAN1_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_INIT_ENUM                      ENABLE
#define PMC_IMPL_PART_AOPG_CAN1_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_DISABLE                        _MK_ENUM_CONST(0)
#define PMC_IMPL_PART_AOPG_CAN1_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_ENABLE                 _MK_ENUM_CONST(1)


// Register PMC_IMPL_PART_AOPG_CAN1_POWER_GATE_STATUS_0
#define PMC_IMPL_PART_AOPG_CAN1_POWER_GATE_STATUS_0                     _MK_ADDR_CONST(0x404)
#define PMC_IMPL_PART_AOPG_CAN1_POWER_GATE_STATUS_0_SECURE                      0x0
#define PMC_IMPL_PART_AOPG_CAN1_POWER_GATE_STATUS_0_DUAL                        0x0
#define PMC_IMPL_PART_AOPG_CAN1_POWER_GATE_STATUS_0_SCR                         PG_AOPG_CAN1_SCR_0
#define PMC_IMPL_PART_AOPG_CAN1_POWER_GATE_STATUS_0_WORD_COUNT                  0x1
#define PMC_IMPL_PART_AOPG_CAN1_POWER_GATE_STATUS_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_CAN1_POWER_GATE_STATUS_0_RESET_MASK                  _MK_MASK_CONST(0x7)
#define PMC_IMPL_PART_AOPG_CAN1_POWER_GATE_STATUS_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_CAN1_POWER_GATE_STATUS_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_CAN1_POWER_GATE_STATUS_0_READ_MASK                   _MK_MASK_CONST(0x7)
#define PMC_IMPL_PART_AOPG_CAN1_POWER_GATE_STATUS_0_WRITE_MASK                  _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_CAN1_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SHIFT                       _MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_AOPG_CAN1_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_FIELD                       _MK_FIELD_CONST(0x1, PMC_IMPL_PART_AOPG_CAN1_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SHIFT)
#define PMC_IMPL_PART_AOPG_CAN1_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_RANGE                       0:0
#define PMC_IMPL_PART_AOPG_CAN1_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_WOFFSET                     0x0
#define PMC_IMPL_PART_AOPG_CAN1_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_DEFAULT                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_CAN1_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AOPG_CAN1_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_CAN1_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_CAN1_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_CAN1_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AOPG_CAN1_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_INIT_ENUM                   OFF
#define PMC_IMPL_PART_AOPG_CAN1_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_OFF                 _MK_ENUM_CONST(0)
#define PMC_IMPL_PART_AOPG_CAN1_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_ON                  _MK_ENUM_CONST(1)

#define PMC_IMPL_PART_AOPG_CAN1_POWER_GATE_STATUS_0_SRAM_RET_STS_SHIFT                  _MK_SHIFT_CONST(1)
#define PMC_IMPL_PART_AOPG_CAN1_POWER_GATE_STATUS_0_SRAM_RET_STS_FIELD                  _MK_FIELD_CONST(0x1, PMC_IMPL_PART_AOPG_CAN1_POWER_GATE_STATUS_0_SRAM_RET_STS_SHIFT)
#define PMC_IMPL_PART_AOPG_CAN1_POWER_GATE_STATUS_0_SRAM_RET_STS_RANGE                  1:1
#define PMC_IMPL_PART_AOPG_CAN1_POWER_GATE_STATUS_0_SRAM_RET_STS_WOFFSET                        0x0
#define PMC_IMPL_PART_AOPG_CAN1_POWER_GATE_STATUS_0_SRAM_RET_STS_DEFAULT                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_CAN1_POWER_GATE_STATUS_0_SRAM_RET_STS_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AOPG_CAN1_POWER_GATE_STATUS_0_SRAM_RET_STS_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_CAN1_POWER_GATE_STATUS_0_SRAM_RET_STS_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_CAN1_POWER_GATE_STATUS_0_SRAM_RET_STS_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_CAN1_POWER_GATE_STATUS_0_SRAM_RET_STS_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AOPG_CAN1_POWER_GATE_STATUS_0_SRAM_RET_STS_INIT_ENUM                      OFF
#define PMC_IMPL_PART_AOPG_CAN1_POWER_GATE_STATUS_0_SRAM_RET_STS_OFF                    _MK_ENUM_CONST(0)
#define PMC_IMPL_PART_AOPG_CAN1_POWER_GATE_STATUS_0_SRAM_RET_STS_ON                     _MK_ENUM_CONST(1)

#define PMC_IMPL_PART_AOPG_CAN1_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SHIFT                        _MK_SHIFT_CONST(2)
#define PMC_IMPL_PART_AOPG_CAN1_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_FIELD                        _MK_FIELD_CONST(0x1, PMC_IMPL_PART_AOPG_CAN1_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SHIFT)
#define PMC_IMPL_PART_AOPG_CAN1_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_RANGE                        2:2
#define PMC_IMPL_PART_AOPG_CAN1_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_WOFFSET                      0x0
#define PMC_IMPL_PART_AOPG_CAN1_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_DEFAULT                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_CAN1_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AOPG_CAN1_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_CAN1_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_CAN1_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_CAN1_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AOPG_CAN1_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_INIT_ENUM                    OFF
#define PMC_IMPL_PART_AOPG_CAN1_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_OFF                  _MK_ENUM_CONST(0)
#define PMC_IMPL_PART_AOPG_CAN1_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_ON                   _MK_ENUM_CONST(1)


// Register PMC_IMPL_PART_AOPG_CAN1_CLAMP_CONTROL_0
#define PMC_IMPL_PART_AOPG_CAN1_CLAMP_CONTROL_0                 _MK_ADDR_CONST(0x408)
#define PMC_IMPL_PART_AOPG_CAN1_CLAMP_CONTROL_0_SECURE                  0x0
#define PMC_IMPL_PART_AOPG_CAN1_CLAMP_CONTROL_0_DUAL                    0x0
#define PMC_IMPL_PART_AOPG_CAN1_CLAMP_CONTROL_0_SCR                     PG_AOPG_CAN1_SCR_0
#define PMC_IMPL_PART_AOPG_CAN1_CLAMP_CONTROL_0_WORD_COUNT                      0x1
#define PMC_IMPL_PART_AOPG_CAN1_CLAMP_CONTROL_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_CAN1_CLAMP_CONTROL_0_RESET_MASK                      _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AOPG_CAN1_CLAMP_CONTROL_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_CAN1_CLAMP_CONTROL_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_CAN1_CLAMP_CONTROL_0_READ_MASK                       _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AOPG_CAN1_CLAMP_CONTROL_0_WRITE_MASK                      _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AOPG_CAN1_CLAMP_CONTROL_0_CLAMP_SHIFT                     _MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_AOPG_CAN1_CLAMP_CONTROL_0_CLAMP_FIELD                     _MK_FIELD_CONST(0x1, PMC_IMPL_PART_AOPG_CAN1_CLAMP_CONTROL_0_CLAMP_SHIFT)
#define PMC_IMPL_PART_AOPG_CAN1_CLAMP_CONTROL_0_CLAMP_RANGE                     0:0
#define PMC_IMPL_PART_AOPG_CAN1_CLAMP_CONTROL_0_CLAMP_WOFFSET                   0x0
#define PMC_IMPL_PART_AOPG_CAN1_CLAMP_CONTROL_0_CLAMP_DEFAULT                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_CAN1_CLAMP_CONTROL_0_CLAMP_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AOPG_CAN1_CLAMP_CONTROL_0_CLAMP_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_CAN1_CLAMP_CONTROL_0_CLAMP_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_CAN1_CLAMP_CONTROL_0_CLAMP_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_AOPG_CAN1_CLAMP_CONTROL_0_CLAMP_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_AOPG_CAN1_CLAMP_CONTROL_0_CLAMP_INIT_ENUM                 OFF
#define PMC_IMPL_PART_AOPG_CAN1_CLAMP_CONTROL_0_CLAMP_OFF                       _MK_ENUM_CONST(0)
#define PMC_IMPL_PART_AOPG_CAN1_CLAMP_CONTROL_0_CLAMP_ON                        _MK_ENUM_CONST(1)


// Reserved address 0x40c

// Reserved address 0x410

// Reserved address 0x414

// Register PMC_IMPL_PART_MSS_SCRATCH_POWER_GATE_CONTROL_0
#define PMC_IMPL_PART_MSS_SCRATCH_POWER_GATE_CONTROL_0                  _MK_ADDR_CONST(0x418)
#define PMC_IMPL_PART_MSS_SCRATCH_POWER_GATE_CONTROL_0_SECURE                   0x0
#define PMC_IMPL_PART_MSS_SCRATCH_POWER_GATE_CONTROL_0_DUAL                     0x0
#define PMC_IMPL_PART_MSS_SCRATCH_POWER_GATE_CONTROL_0_SCR                      PG_MSS_SCRATCH_SCR_0
#define PMC_IMPL_PART_MSS_SCRATCH_POWER_GATE_CONTROL_0_WORD_COUNT                       0x1
#define PMC_IMPL_PART_MSS_SCRATCH_POWER_GATE_CONTROL_0_RESET_VAL                        _MK_MASK_CONST(0x80000000)
#define PMC_IMPL_PART_MSS_SCRATCH_POWER_GATE_CONTROL_0_RESET_MASK                       _MK_MASK_CONST(0x80000107)
#define PMC_IMPL_PART_MSS_SCRATCH_POWER_GATE_CONTROL_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_MSS_SCRATCH_POWER_GATE_CONTROL_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_MSS_SCRATCH_POWER_GATE_CONTROL_0_READ_MASK                        _MK_MASK_CONST(0x80000107)
#define PMC_IMPL_PART_MSS_SCRATCH_POWER_GATE_CONTROL_0_WRITE_MASK                       _MK_MASK_CONST(0x80000107)
#define PMC_IMPL_PART_MSS_SCRATCH_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SHIFT                        _MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_MSS_SCRATCH_POWER_GATE_CONTROL_0_LOGIC_SLEEP_FIELD                        _MK_FIELD_CONST(0x1, PMC_IMPL_PART_MSS_SCRATCH_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SHIFT)
#define PMC_IMPL_PART_MSS_SCRATCH_POWER_GATE_CONTROL_0_LOGIC_SLEEP_RANGE                        0:0
#define PMC_IMPL_PART_MSS_SCRATCH_POWER_GATE_CONTROL_0_LOGIC_SLEEP_WOFFSET                      0x0
#define PMC_IMPL_PART_MSS_SCRATCH_POWER_GATE_CONTROL_0_LOGIC_SLEEP_DEFAULT                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_MSS_SCRATCH_POWER_GATE_CONTROL_0_LOGIC_SLEEP_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_MSS_SCRATCH_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_MSS_SCRATCH_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_MSS_SCRATCH_POWER_GATE_CONTROL_0_LOGIC_SLEEP_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_MSS_SCRATCH_POWER_GATE_CONTROL_0_LOGIC_SLEEP_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_MSS_SCRATCH_POWER_GATE_CONTROL_0_LOGIC_SLEEP_INIT_ENUM                    OFF
#define PMC_IMPL_PART_MSS_SCRATCH_POWER_GATE_CONTROL_0_LOGIC_SLEEP_OFF                  _MK_ENUM_CONST(0)
#define PMC_IMPL_PART_MSS_SCRATCH_POWER_GATE_CONTROL_0_LOGIC_SLEEP_ON                   _MK_ENUM_CONST(1)

#define PMC_IMPL_PART_MSS_SCRATCH_POWER_GATE_CONTROL_0_SRAM_RET_EN_SHIFT                        _MK_SHIFT_CONST(1)
#define PMC_IMPL_PART_MSS_SCRATCH_POWER_GATE_CONTROL_0_SRAM_RET_EN_FIELD                        _MK_FIELD_CONST(0x1, PMC_IMPL_PART_MSS_SCRATCH_POWER_GATE_CONTROL_0_SRAM_RET_EN_SHIFT)
#define PMC_IMPL_PART_MSS_SCRATCH_POWER_GATE_CONTROL_0_SRAM_RET_EN_RANGE                        1:1
#define PMC_IMPL_PART_MSS_SCRATCH_POWER_GATE_CONTROL_0_SRAM_RET_EN_WOFFSET                      0x0
#define PMC_IMPL_PART_MSS_SCRATCH_POWER_GATE_CONTROL_0_SRAM_RET_EN_DEFAULT                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_MSS_SCRATCH_POWER_GATE_CONTROL_0_SRAM_RET_EN_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_MSS_SCRATCH_POWER_GATE_CONTROL_0_SRAM_RET_EN_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_MSS_SCRATCH_POWER_GATE_CONTROL_0_SRAM_RET_EN_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_MSS_SCRATCH_POWER_GATE_CONTROL_0_SRAM_RET_EN_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_MSS_SCRATCH_POWER_GATE_CONTROL_0_SRAM_RET_EN_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_MSS_SCRATCH_POWER_GATE_CONTROL_0_SRAM_RET_EN_INIT_ENUM                    OFF
#define PMC_IMPL_PART_MSS_SCRATCH_POWER_GATE_CONTROL_0_SRAM_RET_EN_OFF                  _MK_ENUM_CONST(0)
#define PMC_IMPL_PART_MSS_SCRATCH_POWER_GATE_CONTROL_0_SRAM_RET_EN_ON                   _MK_ENUM_CONST(1)

#define PMC_IMPL_PART_MSS_SCRATCH_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SHIFT                      _MK_SHIFT_CONST(2)
#define PMC_IMPL_PART_MSS_SCRATCH_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_FIELD                      _MK_FIELD_CONST(0x1, PMC_IMPL_PART_MSS_SCRATCH_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SHIFT)
#define PMC_IMPL_PART_MSS_SCRATCH_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_RANGE                      2:2
#define PMC_IMPL_PART_MSS_SCRATCH_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_WOFFSET                    0x0
#define PMC_IMPL_PART_MSS_SCRATCH_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_DEFAULT                    _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_MSS_SCRATCH_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_MSS_SCRATCH_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_MSS_SCRATCH_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_MSS_SCRATCH_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_MSS_SCRATCH_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_MSS_SCRATCH_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_INIT_ENUM                  OFF
#define PMC_IMPL_PART_MSS_SCRATCH_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_OFF                        _MK_ENUM_CONST(0)
#define PMC_IMPL_PART_MSS_SCRATCH_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_ON                 _MK_ENUM_CONST(1)

#define PMC_IMPL_PART_MSS_SCRATCH_POWER_GATE_CONTROL_0_START_SHIFT                      _MK_SHIFT_CONST(8)
#define PMC_IMPL_PART_MSS_SCRATCH_POWER_GATE_CONTROL_0_START_FIELD                      _MK_FIELD_CONST(0x1, PMC_IMPL_PART_MSS_SCRATCH_POWER_GATE_CONTROL_0_START_SHIFT)
#define PMC_IMPL_PART_MSS_SCRATCH_POWER_GATE_CONTROL_0_START_RANGE                      8:8
#define PMC_IMPL_PART_MSS_SCRATCH_POWER_GATE_CONTROL_0_START_WOFFSET                    0x0
#define PMC_IMPL_PART_MSS_SCRATCH_POWER_GATE_CONTROL_0_START_DEFAULT                    _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_MSS_SCRATCH_POWER_GATE_CONTROL_0_START_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_MSS_SCRATCH_POWER_GATE_CONTROL_0_START_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_MSS_SCRATCH_POWER_GATE_CONTROL_0_START_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_MSS_SCRATCH_POWER_GATE_CONTROL_0_START_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_MSS_SCRATCH_POWER_GATE_CONTROL_0_START_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_MSS_SCRATCH_POWER_GATE_CONTROL_0_START_INIT_ENUM                  DONE
#define PMC_IMPL_PART_MSS_SCRATCH_POWER_GATE_CONTROL_0_START_DONE                       _MK_ENUM_CONST(0)
#define PMC_IMPL_PART_MSS_SCRATCH_POWER_GATE_CONTROL_0_START_PENDING                    _MK_ENUM_CONST(1)

#define PMC_IMPL_PART_MSS_SCRATCH_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SHIFT                        _MK_SHIFT_CONST(31)
#define PMC_IMPL_PART_MSS_SCRATCH_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_FIELD                        _MK_FIELD_CONST(0x1, PMC_IMPL_PART_MSS_SCRATCH_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SHIFT)
#define PMC_IMPL_PART_MSS_SCRATCH_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_RANGE                        31:31
#define PMC_IMPL_PART_MSS_SCRATCH_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_WOFFSET                      0x0
#define PMC_IMPL_PART_MSS_SCRATCH_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_DEFAULT                      _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_MSS_SCRATCH_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_MSS_SCRATCH_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_MSS_SCRATCH_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_MSS_SCRATCH_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_MSS_SCRATCH_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_MSS_SCRATCH_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_INIT_ENUM                    ENABLE
#define PMC_IMPL_PART_MSS_SCRATCH_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_DISABLE                      _MK_ENUM_CONST(0)
#define PMC_IMPL_PART_MSS_SCRATCH_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_ENABLE                       _MK_ENUM_CONST(1)


// Register PMC_IMPL_PART_MSS_SCRATCH_POWER_GATE_STATUS_0
#define PMC_IMPL_PART_MSS_SCRATCH_POWER_GATE_STATUS_0                   _MK_ADDR_CONST(0x41c)
#define PMC_IMPL_PART_MSS_SCRATCH_POWER_GATE_STATUS_0_SECURE                    0x0
#define PMC_IMPL_PART_MSS_SCRATCH_POWER_GATE_STATUS_0_DUAL                      0x0
#define PMC_IMPL_PART_MSS_SCRATCH_POWER_GATE_STATUS_0_SCR                       PG_MSS_SCRATCH_SCR_0
#define PMC_IMPL_PART_MSS_SCRATCH_POWER_GATE_STATUS_0_WORD_COUNT                        0x1
#define PMC_IMPL_PART_MSS_SCRATCH_POWER_GATE_STATUS_0_RESET_VAL                         _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_MSS_SCRATCH_POWER_GATE_STATUS_0_RESET_MASK                        _MK_MASK_CONST(0x7)
#define PMC_IMPL_PART_MSS_SCRATCH_POWER_GATE_STATUS_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_MSS_SCRATCH_POWER_GATE_STATUS_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_MSS_SCRATCH_POWER_GATE_STATUS_0_READ_MASK                         _MK_MASK_CONST(0x7)
#define PMC_IMPL_PART_MSS_SCRATCH_POWER_GATE_STATUS_0_WRITE_MASK                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_MSS_SCRATCH_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SHIFT                     _MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_MSS_SCRATCH_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_FIELD                     _MK_FIELD_CONST(0x1, PMC_IMPL_PART_MSS_SCRATCH_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SHIFT)
#define PMC_IMPL_PART_MSS_SCRATCH_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_RANGE                     0:0
#define PMC_IMPL_PART_MSS_SCRATCH_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_WOFFSET                   0x0
#define PMC_IMPL_PART_MSS_SCRATCH_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_DEFAULT                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_MSS_SCRATCH_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_MSS_SCRATCH_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_MSS_SCRATCH_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_MSS_SCRATCH_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_MSS_SCRATCH_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_MSS_SCRATCH_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_INIT_ENUM                 OFF
#define PMC_IMPL_PART_MSS_SCRATCH_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_OFF                       _MK_ENUM_CONST(0)
#define PMC_IMPL_PART_MSS_SCRATCH_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_ON                        _MK_ENUM_CONST(1)

#define PMC_IMPL_PART_MSS_SCRATCH_POWER_GATE_STATUS_0_SRAM_RET_STS_SHIFT                        _MK_SHIFT_CONST(1)
#define PMC_IMPL_PART_MSS_SCRATCH_POWER_GATE_STATUS_0_SRAM_RET_STS_FIELD                        _MK_FIELD_CONST(0x1, PMC_IMPL_PART_MSS_SCRATCH_POWER_GATE_STATUS_0_SRAM_RET_STS_SHIFT)
#define PMC_IMPL_PART_MSS_SCRATCH_POWER_GATE_STATUS_0_SRAM_RET_STS_RANGE                        1:1
#define PMC_IMPL_PART_MSS_SCRATCH_POWER_GATE_STATUS_0_SRAM_RET_STS_WOFFSET                      0x0
#define PMC_IMPL_PART_MSS_SCRATCH_POWER_GATE_STATUS_0_SRAM_RET_STS_DEFAULT                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_MSS_SCRATCH_POWER_GATE_STATUS_0_SRAM_RET_STS_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_MSS_SCRATCH_POWER_GATE_STATUS_0_SRAM_RET_STS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_MSS_SCRATCH_POWER_GATE_STATUS_0_SRAM_RET_STS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_MSS_SCRATCH_POWER_GATE_STATUS_0_SRAM_RET_STS_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_MSS_SCRATCH_POWER_GATE_STATUS_0_SRAM_RET_STS_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_MSS_SCRATCH_POWER_GATE_STATUS_0_SRAM_RET_STS_INIT_ENUM                    OFF
#define PMC_IMPL_PART_MSS_SCRATCH_POWER_GATE_STATUS_0_SRAM_RET_STS_OFF                  _MK_ENUM_CONST(0)
#define PMC_IMPL_PART_MSS_SCRATCH_POWER_GATE_STATUS_0_SRAM_RET_STS_ON                   _MK_ENUM_CONST(1)

#define PMC_IMPL_PART_MSS_SCRATCH_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SHIFT                      _MK_SHIFT_CONST(2)
#define PMC_IMPL_PART_MSS_SCRATCH_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_FIELD                      _MK_FIELD_CONST(0x1, PMC_IMPL_PART_MSS_SCRATCH_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SHIFT)
#define PMC_IMPL_PART_MSS_SCRATCH_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_RANGE                      2:2
#define PMC_IMPL_PART_MSS_SCRATCH_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_WOFFSET                    0x0
#define PMC_IMPL_PART_MSS_SCRATCH_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_DEFAULT                    _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_MSS_SCRATCH_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_MSS_SCRATCH_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_MSS_SCRATCH_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_MSS_SCRATCH_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_MSS_SCRATCH_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_MSS_SCRATCH_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_INIT_ENUM                  OFF
#define PMC_IMPL_PART_MSS_SCRATCH_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_OFF                        _MK_ENUM_CONST(0)
#define PMC_IMPL_PART_MSS_SCRATCH_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_ON                 _MK_ENUM_CONST(1)


// Register PMC_IMPL_PART_MSS_SCRATCH_CLAMP_CONTROL_0
#define PMC_IMPL_PART_MSS_SCRATCH_CLAMP_CONTROL_0                       _MK_ADDR_CONST(0x420)
#define PMC_IMPL_PART_MSS_SCRATCH_CLAMP_CONTROL_0_SECURE                        0x0
#define PMC_IMPL_PART_MSS_SCRATCH_CLAMP_CONTROL_0_DUAL                  0x0
#define PMC_IMPL_PART_MSS_SCRATCH_CLAMP_CONTROL_0_SCR                   PG_MSS_SCRATCH_SCR_0
#define PMC_IMPL_PART_MSS_SCRATCH_CLAMP_CONTROL_0_WORD_COUNT                    0x1
#define PMC_IMPL_PART_MSS_SCRATCH_CLAMP_CONTROL_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_MSS_SCRATCH_CLAMP_CONTROL_0_RESET_MASK                    _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_MSS_SCRATCH_CLAMP_CONTROL_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_MSS_SCRATCH_CLAMP_CONTROL_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_MSS_SCRATCH_CLAMP_CONTROL_0_READ_MASK                     _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_MSS_SCRATCH_CLAMP_CONTROL_0_WRITE_MASK                    _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_MSS_SCRATCH_CLAMP_CONTROL_0_CLAMP_SHIFT                   _MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_MSS_SCRATCH_CLAMP_CONTROL_0_CLAMP_FIELD                   _MK_FIELD_CONST(0x1, PMC_IMPL_PART_MSS_SCRATCH_CLAMP_CONTROL_0_CLAMP_SHIFT)
#define PMC_IMPL_PART_MSS_SCRATCH_CLAMP_CONTROL_0_CLAMP_RANGE                   0:0
#define PMC_IMPL_PART_MSS_SCRATCH_CLAMP_CONTROL_0_CLAMP_WOFFSET                 0x0
#define PMC_IMPL_PART_MSS_SCRATCH_CLAMP_CONTROL_0_CLAMP_DEFAULT                 _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_MSS_SCRATCH_CLAMP_CONTROL_0_CLAMP_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_MSS_SCRATCH_CLAMP_CONTROL_0_CLAMP_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_MSS_SCRATCH_CLAMP_CONTROL_0_CLAMP_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_MSS_SCRATCH_CLAMP_CONTROL_0_CLAMP_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_MSS_SCRATCH_CLAMP_CONTROL_0_CLAMP_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_MSS_SCRATCH_CLAMP_CONTROL_0_CLAMP_INIT_ENUM                       OFF
#define PMC_IMPL_PART_MSS_SCRATCH_CLAMP_CONTROL_0_CLAMP_OFF                     _MK_ENUM_CONST(0)
#define PMC_IMPL_PART_MSS_SCRATCH_CLAMP_CONTROL_0_CLAMP_ON                      _MK_ENUM_CONST(1)


// Register PMC_IMPL_PART_PCIEX8A_POWER_GATE_CONTROL_0
#define PMC_IMPL_PART_PCIEX8A_POWER_GATE_CONTROL_0                      _MK_ADDR_CONST(0x424)
#define PMC_IMPL_PART_PCIEX8A_POWER_GATE_CONTROL_0_SECURE                       0x0
#define PMC_IMPL_PART_PCIEX8A_POWER_GATE_CONTROL_0_DUAL                         0x0
#define PMC_IMPL_PART_PCIEX8A_POWER_GATE_CONTROL_0_SCR                  PG_PCIEX8A_SCR_0
#define PMC_IMPL_PART_PCIEX8A_POWER_GATE_CONTROL_0_WORD_COUNT                   0x1
#define PMC_IMPL_PART_PCIEX8A_POWER_GATE_CONTROL_0_RESET_VAL                    _MK_MASK_CONST(0x80000000)
#define PMC_IMPL_PART_PCIEX8A_POWER_GATE_CONTROL_0_RESET_MASK                   _MK_MASK_CONST(0x80000107)
#define PMC_IMPL_PART_PCIEX8A_POWER_GATE_CONTROL_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX8A_POWER_GATE_CONTROL_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX8A_POWER_GATE_CONTROL_0_READ_MASK                    _MK_MASK_CONST(0x80000107)
#define PMC_IMPL_PART_PCIEX8A_POWER_GATE_CONTROL_0_WRITE_MASK                   _MK_MASK_CONST(0x80000107)
#define PMC_IMPL_PART_PCIEX8A_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SHIFT                    _MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_PCIEX8A_POWER_GATE_CONTROL_0_LOGIC_SLEEP_FIELD                    _MK_FIELD_CONST(0x1, PMC_IMPL_PART_PCIEX8A_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SHIFT)
#define PMC_IMPL_PART_PCIEX8A_POWER_GATE_CONTROL_0_LOGIC_SLEEP_RANGE                    0:0
#define PMC_IMPL_PART_PCIEX8A_POWER_GATE_CONTROL_0_LOGIC_SLEEP_WOFFSET                  0x0
#define PMC_IMPL_PART_PCIEX8A_POWER_GATE_CONTROL_0_LOGIC_SLEEP_DEFAULT                  _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX8A_POWER_GATE_CONTROL_0_LOGIC_SLEEP_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PCIEX8A_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX8A_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX8A_POWER_GATE_CONTROL_0_LOGIC_SLEEP_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX8A_POWER_GATE_CONTROL_0_LOGIC_SLEEP_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PCIEX8A_POWER_GATE_CONTROL_0_LOGIC_SLEEP_INIT_ENUM                        OFF
#define PMC_IMPL_PART_PCIEX8A_POWER_GATE_CONTROL_0_LOGIC_SLEEP_OFF                      _MK_ENUM_CONST(0)
#define PMC_IMPL_PART_PCIEX8A_POWER_GATE_CONTROL_0_LOGIC_SLEEP_ON                       _MK_ENUM_CONST(1)

#define PMC_IMPL_PART_PCIEX8A_POWER_GATE_CONTROL_0_SRAM_RET_EN_SHIFT                    _MK_SHIFT_CONST(1)
#define PMC_IMPL_PART_PCIEX8A_POWER_GATE_CONTROL_0_SRAM_RET_EN_FIELD                    _MK_FIELD_CONST(0x1, PMC_IMPL_PART_PCIEX8A_POWER_GATE_CONTROL_0_SRAM_RET_EN_SHIFT)
#define PMC_IMPL_PART_PCIEX8A_POWER_GATE_CONTROL_0_SRAM_RET_EN_RANGE                    1:1
#define PMC_IMPL_PART_PCIEX8A_POWER_GATE_CONTROL_0_SRAM_RET_EN_WOFFSET                  0x0
#define PMC_IMPL_PART_PCIEX8A_POWER_GATE_CONTROL_0_SRAM_RET_EN_DEFAULT                  _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX8A_POWER_GATE_CONTROL_0_SRAM_RET_EN_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PCIEX8A_POWER_GATE_CONTROL_0_SRAM_RET_EN_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX8A_POWER_GATE_CONTROL_0_SRAM_RET_EN_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX8A_POWER_GATE_CONTROL_0_SRAM_RET_EN_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX8A_POWER_GATE_CONTROL_0_SRAM_RET_EN_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PCIEX8A_POWER_GATE_CONTROL_0_SRAM_RET_EN_INIT_ENUM                        OFF
#define PMC_IMPL_PART_PCIEX8A_POWER_GATE_CONTROL_0_SRAM_RET_EN_OFF                      _MK_ENUM_CONST(0)
#define PMC_IMPL_PART_PCIEX8A_POWER_GATE_CONTROL_0_SRAM_RET_EN_ON                       _MK_ENUM_CONST(1)

#define PMC_IMPL_PART_PCIEX8A_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SHIFT                  _MK_SHIFT_CONST(2)
#define PMC_IMPL_PART_PCIEX8A_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_FIELD                  _MK_FIELD_CONST(0x1, PMC_IMPL_PART_PCIEX8A_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SHIFT)
#define PMC_IMPL_PART_PCIEX8A_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_RANGE                  2:2
#define PMC_IMPL_PART_PCIEX8A_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_WOFFSET                        0x0
#define PMC_IMPL_PART_PCIEX8A_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_DEFAULT                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX8A_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PCIEX8A_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX8A_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX8A_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX8A_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PCIEX8A_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_INIT_ENUM                      OFF
#define PMC_IMPL_PART_PCIEX8A_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_OFF                    _MK_ENUM_CONST(0)
#define PMC_IMPL_PART_PCIEX8A_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_ON                     _MK_ENUM_CONST(1)

#define PMC_IMPL_PART_PCIEX8A_POWER_GATE_CONTROL_0_START_SHIFT                  _MK_SHIFT_CONST(8)
#define PMC_IMPL_PART_PCIEX8A_POWER_GATE_CONTROL_0_START_FIELD                  _MK_FIELD_CONST(0x1, PMC_IMPL_PART_PCIEX8A_POWER_GATE_CONTROL_0_START_SHIFT)
#define PMC_IMPL_PART_PCIEX8A_POWER_GATE_CONTROL_0_START_RANGE                  8:8
#define PMC_IMPL_PART_PCIEX8A_POWER_GATE_CONTROL_0_START_WOFFSET                        0x0
#define PMC_IMPL_PART_PCIEX8A_POWER_GATE_CONTROL_0_START_DEFAULT                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX8A_POWER_GATE_CONTROL_0_START_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PCIEX8A_POWER_GATE_CONTROL_0_START_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX8A_POWER_GATE_CONTROL_0_START_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX8A_POWER_GATE_CONTROL_0_START_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX8A_POWER_GATE_CONTROL_0_START_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PCIEX8A_POWER_GATE_CONTROL_0_START_INIT_ENUM                      DONE
#define PMC_IMPL_PART_PCIEX8A_POWER_GATE_CONTROL_0_START_DONE                   _MK_ENUM_CONST(0)
#define PMC_IMPL_PART_PCIEX8A_POWER_GATE_CONTROL_0_START_PENDING                        _MK_ENUM_CONST(1)

#define PMC_IMPL_PART_PCIEX8A_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SHIFT                    _MK_SHIFT_CONST(31)
#define PMC_IMPL_PART_PCIEX8A_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_FIELD                    _MK_FIELD_CONST(0x1, PMC_IMPL_PART_PCIEX8A_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SHIFT)
#define PMC_IMPL_PART_PCIEX8A_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_RANGE                    31:31
#define PMC_IMPL_PART_PCIEX8A_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_WOFFSET                  0x0
#define PMC_IMPL_PART_PCIEX8A_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_DEFAULT                  _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PCIEX8A_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PCIEX8A_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX8A_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX8A_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX8A_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PCIEX8A_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_INIT_ENUM                        ENABLE
#define PMC_IMPL_PART_PCIEX8A_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_DISABLE                  _MK_ENUM_CONST(0)
#define PMC_IMPL_PART_PCIEX8A_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_ENABLE                   _MK_ENUM_CONST(1)


// Register PMC_IMPL_PART_PCIEX8A_POWER_GATE_STATUS_0
#define PMC_IMPL_PART_PCIEX8A_POWER_GATE_STATUS_0                       _MK_ADDR_CONST(0x428)
#define PMC_IMPL_PART_PCIEX8A_POWER_GATE_STATUS_0_SECURE                        0x0
#define PMC_IMPL_PART_PCIEX8A_POWER_GATE_STATUS_0_DUAL                  0x0
#define PMC_IMPL_PART_PCIEX8A_POWER_GATE_STATUS_0_SCR                   PG_PCIEX8A_SCR_0
#define PMC_IMPL_PART_PCIEX8A_POWER_GATE_STATUS_0_WORD_COUNT                    0x1
#define PMC_IMPL_PART_PCIEX8A_POWER_GATE_STATUS_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX8A_POWER_GATE_STATUS_0_RESET_MASK                    _MK_MASK_CONST(0x7)
#define PMC_IMPL_PART_PCIEX8A_POWER_GATE_STATUS_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX8A_POWER_GATE_STATUS_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX8A_POWER_GATE_STATUS_0_READ_MASK                     _MK_MASK_CONST(0x7)
#define PMC_IMPL_PART_PCIEX8A_POWER_GATE_STATUS_0_WRITE_MASK                    _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX8A_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SHIFT                 _MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_PCIEX8A_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_FIELD                 _MK_FIELD_CONST(0x1, PMC_IMPL_PART_PCIEX8A_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SHIFT)
#define PMC_IMPL_PART_PCIEX8A_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_RANGE                 0:0
#define PMC_IMPL_PART_PCIEX8A_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_WOFFSET                       0x0
#define PMC_IMPL_PART_PCIEX8A_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_DEFAULT                       _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX8A_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PCIEX8A_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX8A_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX8A_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX8A_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PCIEX8A_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_INIT_ENUM                     OFF
#define PMC_IMPL_PART_PCIEX8A_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_OFF                   _MK_ENUM_CONST(0)
#define PMC_IMPL_PART_PCIEX8A_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_ON                    _MK_ENUM_CONST(1)

#define PMC_IMPL_PART_PCIEX8A_POWER_GATE_STATUS_0_SRAM_RET_STS_SHIFT                    _MK_SHIFT_CONST(1)
#define PMC_IMPL_PART_PCIEX8A_POWER_GATE_STATUS_0_SRAM_RET_STS_FIELD                    _MK_FIELD_CONST(0x1, PMC_IMPL_PART_PCIEX8A_POWER_GATE_STATUS_0_SRAM_RET_STS_SHIFT)
#define PMC_IMPL_PART_PCIEX8A_POWER_GATE_STATUS_0_SRAM_RET_STS_RANGE                    1:1
#define PMC_IMPL_PART_PCIEX8A_POWER_GATE_STATUS_0_SRAM_RET_STS_WOFFSET                  0x0
#define PMC_IMPL_PART_PCIEX8A_POWER_GATE_STATUS_0_SRAM_RET_STS_DEFAULT                  _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX8A_POWER_GATE_STATUS_0_SRAM_RET_STS_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PCIEX8A_POWER_GATE_STATUS_0_SRAM_RET_STS_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX8A_POWER_GATE_STATUS_0_SRAM_RET_STS_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX8A_POWER_GATE_STATUS_0_SRAM_RET_STS_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX8A_POWER_GATE_STATUS_0_SRAM_RET_STS_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PCIEX8A_POWER_GATE_STATUS_0_SRAM_RET_STS_INIT_ENUM                        OFF
#define PMC_IMPL_PART_PCIEX8A_POWER_GATE_STATUS_0_SRAM_RET_STS_OFF                      _MK_ENUM_CONST(0)
#define PMC_IMPL_PART_PCIEX8A_POWER_GATE_STATUS_0_SRAM_RET_STS_ON                       _MK_ENUM_CONST(1)

#define PMC_IMPL_PART_PCIEX8A_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SHIFT                  _MK_SHIFT_CONST(2)
#define PMC_IMPL_PART_PCIEX8A_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_FIELD                  _MK_FIELD_CONST(0x1, PMC_IMPL_PART_PCIEX8A_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SHIFT)
#define PMC_IMPL_PART_PCIEX8A_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_RANGE                  2:2
#define PMC_IMPL_PART_PCIEX8A_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_WOFFSET                        0x0
#define PMC_IMPL_PART_PCIEX8A_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_DEFAULT                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX8A_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PCIEX8A_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX8A_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX8A_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX8A_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PCIEX8A_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_INIT_ENUM                      OFF
#define PMC_IMPL_PART_PCIEX8A_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_OFF                    _MK_ENUM_CONST(0)
#define PMC_IMPL_PART_PCIEX8A_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_ON                     _MK_ENUM_CONST(1)


// Register PMC_IMPL_PART_PCIEX8A_CLAMP_CONTROL_0
#define PMC_IMPL_PART_PCIEX8A_CLAMP_CONTROL_0                   _MK_ADDR_CONST(0x42c)
#define PMC_IMPL_PART_PCIEX8A_CLAMP_CONTROL_0_SECURE                    0x0
#define PMC_IMPL_PART_PCIEX8A_CLAMP_CONTROL_0_DUAL                      0x0
#define PMC_IMPL_PART_PCIEX8A_CLAMP_CONTROL_0_SCR                       PG_PCIEX8A_SCR_0
#define PMC_IMPL_PART_PCIEX8A_CLAMP_CONTROL_0_WORD_COUNT                        0x1
#define PMC_IMPL_PART_PCIEX8A_CLAMP_CONTROL_0_RESET_VAL                         _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX8A_CLAMP_CONTROL_0_RESET_MASK                        _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PCIEX8A_CLAMP_CONTROL_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX8A_CLAMP_CONTROL_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX8A_CLAMP_CONTROL_0_READ_MASK                         _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PCIEX8A_CLAMP_CONTROL_0_WRITE_MASK                        _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PCIEX8A_CLAMP_CONTROL_0_CLAMP_SHIFT                       _MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_PCIEX8A_CLAMP_CONTROL_0_CLAMP_FIELD                       _MK_FIELD_CONST(0x1, PMC_IMPL_PART_PCIEX8A_CLAMP_CONTROL_0_CLAMP_SHIFT)
#define PMC_IMPL_PART_PCIEX8A_CLAMP_CONTROL_0_CLAMP_RANGE                       0:0
#define PMC_IMPL_PART_PCIEX8A_CLAMP_CONTROL_0_CLAMP_WOFFSET                     0x0
#define PMC_IMPL_PART_PCIEX8A_CLAMP_CONTROL_0_CLAMP_DEFAULT                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX8A_CLAMP_CONTROL_0_CLAMP_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PCIEX8A_CLAMP_CONTROL_0_CLAMP_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX8A_CLAMP_CONTROL_0_CLAMP_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX8A_CLAMP_CONTROL_0_CLAMP_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX8A_CLAMP_CONTROL_0_CLAMP_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PCIEX8A_CLAMP_CONTROL_0_CLAMP_INIT_ENUM                   OFF
#define PMC_IMPL_PART_PCIEX8A_CLAMP_CONTROL_0_CLAMP_OFF                 _MK_ENUM_CONST(0)
#define PMC_IMPL_PART_PCIEX8A_CLAMP_CONTROL_0_CLAMP_ON                  _MK_ENUM_CONST(1)


// Register PMC_IMPL_PART_PCIEX4A_POWER_GATE_CONTROL_0
#define PMC_IMPL_PART_PCIEX4A_POWER_GATE_CONTROL_0                      _MK_ADDR_CONST(0x430)
#define PMC_IMPL_PART_PCIEX4A_POWER_GATE_CONTROL_0_SECURE                       0x0
#define PMC_IMPL_PART_PCIEX4A_POWER_GATE_CONTROL_0_DUAL                         0x0
#define PMC_IMPL_PART_PCIEX4A_POWER_GATE_CONTROL_0_SCR                  PG_PCIEX4A_SCR_0
#define PMC_IMPL_PART_PCIEX4A_POWER_GATE_CONTROL_0_WORD_COUNT                   0x1
#define PMC_IMPL_PART_PCIEX4A_POWER_GATE_CONTROL_0_RESET_VAL                    _MK_MASK_CONST(0x80000000)
#define PMC_IMPL_PART_PCIEX4A_POWER_GATE_CONTROL_0_RESET_MASK                   _MK_MASK_CONST(0x80000107)
#define PMC_IMPL_PART_PCIEX4A_POWER_GATE_CONTROL_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX4A_POWER_GATE_CONTROL_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX4A_POWER_GATE_CONTROL_0_READ_MASK                    _MK_MASK_CONST(0x80000107)
#define PMC_IMPL_PART_PCIEX4A_POWER_GATE_CONTROL_0_WRITE_MASK                   _MK_MASK_CONST(0x80000107)
#define PMC_IMPL_PART_PCIEX4A_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SHIFT                    _MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_PCIEX4A_POWER_GATE_CONTROL_0_LOGIC_SLEEP_FIELD                    _MK_FIELD_CONST(0x1, PMC_IMPL_PART_PCIEX4A_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SHIFT)
#define PMC_IMPL_PART_PCIEX4A_POWER_GATE_CONTROL_0_LOGIC_SLEEP_RANGE                    0:0
#define PMC_IMPL_PART_PCIEX4A_POWER_GATE_CONTROL_0_LOGIC_SLEEP_WOFFSET                  0x0
#define PMC_IMPL_PART_PCIEX4A_POWER_GATE_CONTROL_0_LOGIC_SLEEP_DEFAULT                  _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX4A_POWER_GATE_CONTROL_0_LOGIC_SLEEP_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PCIEX4A_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX4A_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX4A_POWER_GATE_CONTROL_0_LOGIC_SLEEP_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX4A_POWER_GATE_CONTROL_0_LOGIC_SLEEP_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PCIEX4A_POWER_GATE_CONTROL_0_LOGIC_SLEEP_INIT_ENUM                        OFF
#define PMC_IMPL_PART_PCIEX4A_POWER_GATE_CONTROL_0_LOGIC_SLEEP_OFF                      _MK_ENUM_CONST(0)
#define PMC_IMPL_PART_PCIEX4A_POWER_GATE_CONTROL_0_LOGIC_SLEEP_ON                       _MK_ENUM_CONST(1)

#define PMC_IMPL_PART_PCIEX4A_POWER_GATE_CONTROL_0_SRAM_RET_EN_SHIFT                    _MK_SHIFT_CONST(1)
#define PMC_IMPL_PART_PCIEX4A_POWER_GATE_CONTROL_0_SRAM_RET_EN_FIELD                    _MK_FIELD_CONST(0x1, PMC_IMPL_PART_PCIEX4A_POWER_GATE_CONTROL_0_SRAM_RET_EN_SHIFT)
#define PMC_IMPL_PART_PCIEX4A_POWER_GATE_CONTROL_0_SRAM_RET_EN_RANGE                    1:1
#define PMC_IMPL_PART_PCIEX4A_POWER_GATE_CONTROL_0_SRAM_RET_EN_WOFFSET                  0x0
#define PMC_IMPL_PART_PCIEX4A_POWER_GATE_CONTROL_0_SRAM_RET_EN_DEFAULT                  _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX4A_POWER_GATE_CONTROL_0_SRAM_RET_EN_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PCIEX4A_POWER_GATE_CONTROL_0_SRAM_RET_EN_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX4A_POWER_GATE_CONTROL_0_SRAM_RET_EN_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX4A_POWER_GATE_CONTROL_0_SRAM_RET_EN_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX4A_POWER_GATE_CONTROL_0_SRAM_RET_EN_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PCIEX4A_POWER_GATE_CONTROL_0_SRAM_RET_EN_INIT_ENUM                        OFF
#define PMC_IMPL_PART_PCIEX4A_POWER_GATE_CONTROL_0_SRAM_RET_EN_OFF                      _MK_ENUM_CONST(0)
#define PMC_IMPL_PART_PCIEX4A_POWER_GATE_CONTROL_0_SRAM_RET_EN_ON                       _MK_ENUM_CONST(1)

#define PMC_IMPL_PART_PCIEX4A_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SHIFT                  _MK_SHIFT_CONST(2)
#define PMC_IMPL_PART_PCIEX4A_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_FIELD                  _MK_FIELD_CONST(0x1, PMC_IMPL_PART_PCIEX4A_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SHIFT)
#define PMC_IMPL_PART_PCIEX4A_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_RANGE                  2:2
#define PMC_IMPL_PART_PCIEX4A_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_WOFFSET                        0x0
#define PMC_IMPL_PART_PCIEX4A_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_DEFAULT                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX4A_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PCIEX4A_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX4A_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX4A_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX4A_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PCIEX4A_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_INIT_ENUM                      OFF
#define PMC_IMPL_PART_PCIEX4A_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_OFF                    _MK_ENUM_CONST(0)
#define PMC_IMPL_PART_PCIEX4A_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_ON                     _MK_ENUM_CONST(1)

#define PMC_IMPL_PART_PCIEX4A_POWER_GATE_CONTROL_0_START_SHIFT                  _MK_SHIFT_CONST(8)
#define PMC_IMPL_PART_PCIEX4A_POWER_GATE_CONTROL_0_START_FIELD                  _MK_FIELD_CONST(0x1, PMC_IMPL_PART_PCIEX4A_POWER_GATE_CONTROL_0_START_SHIFT)
#define PMC_IMPL_PART_PCIEX4A_POWER_GATE_CONTROL_0_START_RANGE                  8:8
#define PMC_IMPL_PART_PCIEX4A_POWER_GATE_CONTROL_0_START_WOFFSET                        0x0
#define PMC_IMPL_PART_PCIEX4A_POWER_GATE_CONTROL_0_START_DEFAULT                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX4A_POWER_GATE_CONTROL_0_START_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PCIEX4A_POWER_GATE_CONTROL_0_START_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX4A_POWER_GATE_CONTROL_0_START_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX4A_POWER_GATE_CONTROL_0_START_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX4A_POWER_GATE_CONTROL_0_START_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PCIEX4A_POWER_GATE_CONTROL_0_START_INIT_ENUM                      DONE
#define PMC_IMPL_PART_PCIEX4A_POWER_GATE_CONTROL_0_START_DONE                   _MK_ENUM_CONST(0)
#define PMC_IMPL_PART_PCIEX4A_POWER_GATE_CONTROL_0_START_PENDING                        _MK_ENUM_CONST(1)

#define PMC_IMPL_PART_PCIEX4A_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SHIFT                    _MK_SHIFT_CONST(31)
#define PMC_IMPL_PART_PCIEX4A_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_FIELD                    _MK_FIELD_CONST(0x1, PMC_IMPL_PART_PCIEX4A_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SHIFT)
#define PMC_IMPL_PART_PCIEX4A_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_RANGE                    31:31
#define PMC_IMPL_PART_PCIEX4A_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_WOFFSET                  0x0
#define PMC_IMPL_PART_PCIEX4A_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_DEFAULT                  _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PCIEX4A_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PCIEX4A_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX4A_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX4A_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX4A_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PCIEX4A_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_INIT_ENUM                        ENABLE
#define PMC_IMPL_PART_PCIEX4A_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_DISABLE                  _MK_ENUM_CONST(0)
#define PMC_IMPL_PART_PCIEX4A_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_ENABLE                   _MK_ENUM_CONST(1)


// Register PMC_IMPL_PART_PCIEX4A_POWER_GATE_STATUS_0
#define PMC_IMPL_PART_PCIEX4A_POWER_GATE_STATUS_0                       _MK_ADDR_CONST(0x434)
#define PMC_IMPL_PART_PCIEX4A_POWER_GATE_STATUS_0_SECURE                        0x0
#define PMC_IMPL_PART_PCIEX4A_POWER_GATE_STATUS_0_DUAL                  0x0
#define PMC_IMPL_PART_PCIEX4A_POWER_GATE_STATUS_0_SCR                   PG_PCIEX4A_SCR_0
#define PMC_IMPL_PART_PCIEX4A_POWER_GATE_STATUS_0_WORD_COUNT                    0x1
#define PMC_IMPL_PART_PCIEX4A_POWER_GATE_STATUS_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX4A_POWER_GATE_STATUS_0_RESET_MASK                    _MK_MASK_CONST(0x7)
#define PMC_IMPL_PART_PCIEX4A_POWER_GATE_STATUS_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX4A_POWER_GATE_STATUS_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX4A_POWER_GATE_STATUS_0_READ_MASK                     _MK_MASK_CONST(0x7)
#define PMC_IMPL_PART_PCIEX4A_POWER_GATE_STATUS_0_WRITE_MASK                    _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX4A_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SHIFT                 _MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_PCIEX4A_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_FIELD                 _MK_FIELD_CONST(0x1, PMC_IMPL_PART_PCIEX4A_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SHIFT)
#define PMC_IMPL_PART_PCIEX4A_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_RANGE                 0:0
#define PMC_IMPL_PART_PCIEX4A_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_WOFFSET                       0x0
#define PMC_IMPL_PART_PCIEX4A_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_DEFAULT                       _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX4A_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PCIEX4A_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX4A_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX4A_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX4A_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PCIEX4A_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_INIT_ENUM                     OFF
#define PMC_IMPL_PART_PCIEX4A_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_OFF                   _MK_ENUM_CONST(0)
#define PMC_IMPL_PART_PCIEX4A_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_ON                    _MK_ENUM_CONST(1)

#define PMC_IMPL_PART_PCIEX4A_POWER_GATE_STATUS_0_SRAM_RET_STS_SHIFT                    _MK_SHIFT_CONST(1)
#define PMC_IMPL_PART_PCIEX4A_POWER_GATE_STATUS_0_SRAM_RET_STS_FIELD                    _MK_FIELD_CONST(0x1, PMC_IMPL_PART_PCIEX4A_POWER_GATE_STATUS_0_SRAM_RET_STS_SHIFT)
#define PMC_IMPL_PART_PCIEX4A_POWER_GATE_STATUS_0_SRAM_RET_STS_RANGE                    1:1
#define PMC_IMPL_PART_PCIEX4A_POWER_GATE_STATUS_0_SRAM_RET_STS_WOFFSET                  0x0
#define PMC_IMPL_PART_PCIEX4A_POWER_GATE_STATUS_0_SRAM_RET_STS_DEFAULT                  _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX4A_POWER_GATE_STATUS_0_SRAM_RET_STS_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PCIEX4A_POWER_GATE_STATUS_0_SRAM_RET_STS_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX4A_POWER_GATE_STATUS_0_SRAM_RET_STS_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX4A_POWER_GATE_STATUS_0_SRAM_RET_STS_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX4A_POWER_GATE_STATUS_0_SRAM_RET_STS_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PCIEX4A_POWER_GATE_STATUS_0_SRAM_RET_STS_INIT_ENUM                        OFF
#define PMC_IMPL_PART_PCIEX4A_POWER_GATE_STATUS_0_SRAM_RET_STS_OFF                      _MK_ENUM_CONST(0)
#define PMC_IMPL_PART_PCIEX4A_POWER_GATE_STATUS_0_SRAM_RET_STS_ON                       _MK_ENUM_CONST(1)

#define PMC_IMPL_PART_PCIEX4A_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SHIFT                  _MK_SHIFT_CONST(2)
#define PMC_IMPL_PART_PCIEX4A_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_FIELD                  _MK_FIELD_CONST(0x1, PMC_IMPL_PART_PCIEX4A_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SHIFT)
#define PMC_IMPL_PART_PCIEX4A_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_RANGE                  2:2
#define PMC_IMPL_PART_PCIEX4A_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_WOFFSET                        0x0
#define PMC_IMPL_PART_PCIEX4A_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_DEFAULT                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX4A_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PCIEX4A_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX4A_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX4A_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX4A_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PCIEX4A_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_INIT_ENUM                      OFF
#define PMC_IMPL_PART_PCIEX4A_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_OFF                    _MK_ENUM_CONST(0)
#define PMC_IMPL_PART_PCIEX4A_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_ON                     _MK_ENUM_CONST(1)


// Register PMC_IMPL_PART_PCIEX4A_CLAMP_CONTROL_0
#define PMC_IMPL_PART_PCIEX4A_CLAMP_CONTROL_0                   _MK_ADDR_CONST(0x438)
#define PMC_IMPL_PART_PCIEX4A_CLAMP_CONTROL_0_SECURE                    0x0
#define PMC_IMPL_PART_PCIEX4A_CLAMP_CONTROL_0_DUAL                      0x0
#define PMC_IMPL_PART_PCIEX4A_CLAMP_CONTROL_0_SCR                       PG_PCIEX4A_SCR_0
#define PMC_IMPL_PART_PCIEX4A_CLAMP_CONTROL_0_WORD_COUNT                        0x1
#define PMC_IMPL_PART_PCIEX4A_CLAMP_CONTROL_0_RESET_VAL                         _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX4A_CLAMP_CONTROL_0_RESET_MASK                        _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PCIEX4A_CLAMP_CONTROL_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX4A_CLAMP_CONTROL_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX4A_CLAMP_CONTROL_0_READ_MASK                         _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PCIEX4A_CLAMP_CONTROL_0_WRITE_MASK                        _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PCIEX4A_CLAMP_CONTROL_0_CLAMP_SHIFT                       _MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_PCIEX4A_CLAMP_CONTROL_0_CLAMP_FIELD                       _MK_FIELD_CONST(0x1, PMC_IMPL_PART_PCIEX4A_CLAMP_CONTROL_0_CLAMP_SHIFT)
#define PMC_IMPL_PART_PCIEX4A_CLAMP_CONTROL_0_CLAMP_RANGE                       0:0
#define PMC_IMPL_PART_PCIEX4A_CLAMP_CONTROL_0_CLAMP_WOFFSET                     0x0
#define PMC_IMPL_PART_PCIEX4A_CLAMP_CONTROL_0_CLAMP_DEFAULT                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX4A_CLAMP_CONTROL_0_CLAMP_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PCIEX4A_CLAMP_CONTROL_0_CLAMP_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX4A_CLAMP_CONTROL_0_CLAMP_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX4A_CLAMP_CONTROL_0_CLAMP_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX4A_CLAMP_CONTROL_0_CLAMP_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PCIEX4A_CLAMP_CONTROL_0_CLAMP_INIT_ENUM                   OFF
#define PMC_IMPL_PART_PCIEX4A_CLAMP_CONTROL_0_CLAMP_OFF                 _MK_ENUM_CONST(0)
#define PMC_IMPL_PART_PCIEX4A_CLAMP_CONTROL_0_CLAMP_ON                  _MK_ENUM_CONST(1)


// Register PMC_IMPL_PART_PCIEX1A_POWER_GATE_CONTROL_0
#define PMC_IMPL_PART_PCIEX1A_POWER_GATE_CONTROL_0                      _MK_ADDR_CONST(0x43c)
#define PMC_IMPL_PART_PCIEX1A_POWER_GATE_CONTROL_0_SECURE                       0x0
#define PMC_IMPL_PART_PCIEX1A_POWER_GATE_CONTROL_0_DUAL                         0x0
#define PMC_IMPL_PART_PCIEX1A_POWER_GATE_CONTROL_0_SCR                  PG_PCIEX1A_SCR_0
#define PMC_IMPL_PART_PCIEX1A_POWER_GATE_CONTROL_0_WORD_COUNT                   0x1
#define PMC_IMPL_PART_PCIEX1A_POWER_GATE_CONTROL_0_RESET_VAL                    _MK_MASK_CONST(0x80000000)
#define PMC_IMPL_PART_PCIEX1A_POWER_GATE_CONTROL_0_RESET_MASK                   _MK_MASK_CONST(0x80000107)
#define PMC_IMPL_PART_PCIEX1A_POWER_GATE_CONTROL_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX1A_POWER_GATE_CONTROL_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX1A_POWER_GATE_CONTROL_0_READ_MASK                    _MK_MASK_CONST(0x80000107)
#define PMC_IMPL_PART_PCIEX1A_POWER_GATE_CONTROL_0_WRITE_MASK                   _MK_MASK_CONST(0x80000107)
#define PMC_IMPL_PART_PCIEX1A_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SHIFT                    _MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_PCIEX1A_POWER_GATE_CONTROL_0_LOGIC_SLEEP_FIELD                    _MK_FIELD_CONST(0x1, PMC_IMPL_PART_PCIEX1A_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SHIFT)
#define PMC_IMPL_PART_PCIEX1A_POWER_GATE_CONTROL_0_LOGIC_SLEEP_RANGE                    0:0
#define PMC_IMPL_PART_PCIEX1A_POWER_GATE_CONTROL_0_LOGIC_SLEEP_WOFFSET                  0x0
#define PMC_IMPL_PART_PCIEX1A_POWER_GATE_CONTROL_0_LOGIC_SLEEP_DEFAULT                  _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX1A_POWER_GATE_CONTROL_0_LOGIC_SLEEP_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PCIEX1A_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX1A_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX1A_POWER_GATE_CONTROL_0_LOGIC_SLEEP_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX1A_POWER_GATE_CONTROL_0_LOGIC_SLEEP_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PCIEX1A_POWER_GATE_CONTROL_0_LOGIC_SLEEP_INIT_ENUM                        OFF
#define PMC_IMPL_PART_PCIEX1A_POWER_GATE_CONTROL_0_LOGIC_SLEEP_OFF                      _MK_ENUM_CONST(0)
#define PMC_IMPL_PART_PCIEX1A_POWER_GATE_CONTROL_0_LOGIC_SLEEP_ON                       _MK_ENUM_CONST(1)

#define PMC_IMPL_PART_PCIEX1A_POWER_GATE_CONTROL_0_SRAM_RET_EN_SHIFT                    _MK_SHIFT_CONST(1)
#define PMC_IMPL_PART_PCIEX1A_POWER_GATE_CONTROL_0_SRAM_RET_EN_FIELD                    _MK_FIELD_CONST(0x1, PMC_IMPL_PART_PCIEX1A_POWER_GATE_CONTROL_0_SRAM_RET_EN_SHIFT)
#define PMC_IMPL_PART_PCIEX1A_POWER_GATE_CONTROL_0_SRAM_RET_EN_RANGE                    1:1
#define PMC_IMPL_PART_PCIEX1A_POWER_GATE_CONTROL_0_SRAM_RET_EN_WOFFSET                  0x0
#define PMC_IMPL_PART_PCIEX1A_POWER_GATE_CONTROL_0_SRAM_RET_EN_DEFAULT                  _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX1A_POWER_GATE_CONTROL_0_SRAM_RET_EN_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PCIEX1A_POWER_GATE_CONTROL_0_SRAM_RET_EN_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX1A_POWER_GATE_CONTROL_0_SRAM_RET_EN_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX1A_POWER_GATE_CONTROL_0_SRAM_RET_EN_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX1A_POWER_GATE_CONTROL_0_SRAM_RET_EN_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PCIEX1A_POWER_GATE_CONTROL_0_SRAM_RET_EN_INIT_ENUM                        OFF
#define PMC_IMPL_PART_PCIEX1A_POWER_GATE_CONTROL_0_SRAM_RET_EN_OFF                      _MK_ENUM_CONST(0)
#define PMC_IMPL_PART_PCIEX1A_POWER_GATE_CONTROL_0_SRAM_RET_EN_ON                       _MK_ENUM_CONST(1)

#define PMC_IMPL_PART_PCIEX1A_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SHIFT                  _MK_SHIFT_CONST(2)
#define PMC_IMPL_PART_PCIEX1A_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_FIELD                  _MK_FIELD_CONST(0x1, PMC_IMPL_PART_PCIEX1A_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SHIFT)
#define PMC_IMPL_PART_PCIEX1A_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_RANGE                  2:2
#define PMC_IMPL_PART_PCIEX1A_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_WOFFSET                        0x0
#define PMC_IMPL_PART_PCIEX1A_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_DEFAULT                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX1A_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PCIEX1A_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX1A_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX1A_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX1A_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PCIEX1A_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_INIT_ENUM                      OFF
#define PMC_IMPL_PART_PCIEX1A_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_OFF                    _MK_ENUM_CONST(0)
#define PMC_IMPL_PART_PCIEX1A_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_ON                     _MK_ENUM_CONST(1)

#define PMC_IMPL_PART_PCIEX1A_POWER_GATE_CONTROL_0_START_SHIFT                  _MK_SHIFT_CONST(8)
#define PMC_IMPL_PART_PCIEX1A_POWER_GATE_CONTROL_0_START_FIELD                  _MK_FIELD_CONST(0x1, PMC_IMPL_PART_PCIEX1A_POWER_GATE_CONTROL_0_START_SHIFT)
#define PMC_IMPL_PART_PCIEX1A_POWER_GATE_CONTROL_0_START_RANGE                  8:8
#define PMC_IMPL_PART_PCIEX1A_POWER_GATE_CONTROL_0_START_WOFFSET                        0x0
#define PMC_IMPL_PART_PCIEX1A_POWER_GATE_CONTROL_0_START_DEFAULT                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX1A_POWER_GATE_CONTROL_0_START_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PCIEX1A_POWER_GATE_CONTROL_0_START_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX1A_POWER_GATE_CONTROL_0_START_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX1A_POWER_GATE_CONTROL_0_START_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX1A_POWER_GATE_CONTROL_0_START_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PCIEX1A_POWER_GATE_CONTROL_0_START_INIT_ENUM                      DONE
#define PMC_IMPL_PART_PCIEX1A_POWER_GATE_CONTROL_0_START_DONE                   _MK_ENUM_CONST(0)
#define PMC_IMPL_PART_PCIEX1A_POWER_GATE_CONTROL_0_START_PENDING                        _MK_ENUM_CONST(1)

#define PMC_IMPL_PART_PCIEX1A_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SHIFT                    _MK_SHIFT_CONST(31)
#define PMC_IMPL_PART_PCIEX1A_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_FIELD                    _MK_FIELD_CONST(0x1, PMC_IMPL_PART_PCIEX1A_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SHIFT)
#define PMC_IMPL_PART_PCIEX1A_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_RANGE                    31:31
#define PMC_IMPL_PART_PCIEX1A_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_WOFFSET                  0x0
#define PMC_IMPL_PART_PCIEX1A_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_DEFAULT                  _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PCIEX1A_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PCIEX1A_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX1A_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX1A_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX1A_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PCIEX1A_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_INIT_ENUM                        ENABLE
#define PMC_IMPL_PART_PCIEX1A_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_DISABLE                  _MK_ENUM_CONST(0)
#define PMC_IMPL_PART_PCIEX1A_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_ENABLE                   _MK_ENUM_CONST(1)


// Register PMC_IMPL_PART_PCIEX1A_POWER_GATE_STATUS_0
#define PMC_IMPL_PART_PCIEX1A_POWER_GATE_STATUS_0                       _MK_ADDR_CONST(0x440)
#define PMC_IMPL_PART_PCIEX1A_POWER_GATE_STATUS_0_SECURE                        0x0
#define PMC_IMPL_PART_PCIEX1A_POWER_GATE_STATUS_0_DUAL                  0x0
#define PMC_IMPL_PART_PCIEX1A_POWER_GATE_STATUS_0_SCR                   PG_PCIEX1A_SCR_0
#define PMC_IMPL_PART_PCIEX1A_POWER_GATE_STATUS_0_WORD_COUNT                    0x1
#define PMC_IMPL_PART_PCIEX1A_POWER_GATE_STATUS_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX1A_POWER_GATE_STATUS_0_RESET_MASK                    _MK_MASK_CONST(0x7)
#define PMC_IMPL_PART_PCIEX1A_POWER_GATE_STATUS_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX1A_POWER_GATE_STATUS_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX1A_POWER_GATE_STATUS_0_READ_MASK                     _MK_MASK_CONST(0x7)
#define PMC_IMPL_PART_PCIEX1A_POWER_GATE_STATUS_0_WRITE_MASK                    _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX1A_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SHIFT                 _MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_PCIEX1A_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_FIELD                 _MK_FIELD_CONST(0x1, PMC_IMPL_PART_PCIEX1A_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SHIFT)
#define PMC_IMPL_PART_PCIEX1A_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_RANGE                 0:0
#define PMC_IMPL_PART_PCIEX1A_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_WOFFSET                       0x0
#define PMC_IMPL_PART_PCIEX1A_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_DEFAULT                       _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX1A_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PCIEX1A_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX1A_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX1A_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX1A_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PCIEX1A_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_INIT_ENUM                     OFF
#define PMC_IMPL_PART_PCIEX1A_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_OFF                   _MK_ENUM_CONST(0)
#define PMC_IMPL_PART_PCIEX1A_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_ON                    _MK_ENUM_CONST(1)

#define PMC_IMPL_PART_PCIEX1A_POWER_GATE_STATUS_0_SRAM_RET_STS_SHIFT                    _MK_SHIFT_CONST(1)
#define PMC_IMPL_PART_PCIEX1A_POWER_GATE_STATUS_0_SRAM_RET_STS_FIELD                    _MK_FIELD_CONST(0x1, PMC_IMPL_PART_PCIEX1A_POWER_GATE_STATUS_0_SRAM_RET_STS_SHIFT)
#define PMC_IMPL_PART_PCIEX1A_POWER_GATE_STATUS_0_SRAM_RET_STS_RANGE                    1:1
#define PMC_IMPL_PART_PCIEX1A_POWER_GATE_STATUS_0_SRAM_RET_STS_WOFFSET                  0x0
#define PMC_IMPL_PART_PCIEX1A_POWER_GATE_STATUS_0_SRAM_RET_STS_DEFAULT                  _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX1A_POWER_GATE_STATUS_0_SRAM_RET_STS_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PCIEX1A_POWER_GATE_STATUS_0_SRAM_RET_STS_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX1A_POWER_GATE_STATUS_0_SRAM_RET_STS_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX1A_POWER_GATE_STATUS_0_SRAM_RET_STS_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX1A_POWER_GATE_STATUS_0_SRAM_RET_STS_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PCIEX1A_POWER_GATE_STATUS_0_SRAM_RET_STS_INIT_ENUM                        OFF
#define PMC_IMPL_PART_PCIEX1A_POWER_GATE_STATUS_0_SRAM_RET_STS_OFF                      _MK_ENUM_CONST(0)
#define PMC_IMPL_PART_PCIEX1A_POWER_GATE_STATUS_0_SRAM_RET_STS_ON                       _MK_ENUM_CONST(1)

#define PMC_IMPL_PART_PCIEX1A_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SHIFT                  _MK_SHIFT_CONST(2)
#define PMC_IMPL_PART_PCIEX1A_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_FIELD                  _MK_FIELD_CONST(0x1, PMC_IMPL_PART_PCIEX1A_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SHIFT)
#define PMC_IMPL_PART_PCIEX1A_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_RANGE                  2:2
#define PMC_IMPL_PART_PCIEX1A_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_WOFFSET                        0x0
#define PMC_IMPL_PART_PCIEX1A_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_DEFAULT                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX1A_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PCIEX1A_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX1A_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX1A_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX1A_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PCIEX1A_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_INIT_ENUM                      OFF
#define PMC_IMPL_PART_PCIEX1A_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_OFF                    _MK_ENUM_CONST(0)
#define PMC_IMPL_PART_PCIEX1A_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_ON                     _MK_ENUM_CONST(1)


// Register PMC_IMPL_PART_PCIEX1A_CLAMP_CONTROL_0
#define PMC_IMPL_PART_PCIEX1A_CLAMP_CONTROL_0                   _MK_ADDR_CONST(0x444)
#define PMC_IMPL_PART_PCIEX1A_CLAMP_CONTROL_0_SECURE                    0x0
#define PMC_IMPL_PART_PCIEX1A_CLAMP_CONTROL_0_DUAL                      0x0
#define PMC_IMPL_PART_PCIEX1A_CLAMP_CONTROL_0_SCR                       PG_PCIEX1A_SCR_0
#define PMC_IMPL_PART_PCIEX1A_CLAMP_CONTROL_0_WORD_COUNT                        0x1
#define PMC_IMPL_PART_PCIEX1A_CLAMP_CONTROL_0_RESET_VAL                         _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX1A_CLAMP_CONTROL_0_RESET_MASK                        _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PCIEX1A_CLAMP_CONTROL_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX1A_CLAMP_CONTROL_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX1A_CLAMP_CONTROL_0_READ_MASK                         _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PCIEX1A_CLAMP_CONTROL_0_WRITE_MASK                        _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PCIEX1A_CLAMP_CONTROL_0_CLAMP_SHIFT                       _MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_PCIEX1A_CLAMP_CONTROL_0_CLAMP_FIELD                       _MK_FIELD_CONST(0x1, PMC_IMPL_PART_PCIEX1A_CLAMP_CONTROL_0_CLAMP_SHIFT)
#define PMC_IMPL_PART_PCIEX1A_CLAMP_CONTROL_0_CLAMP_RANGE                       0:0
#define PMC_IMPL_PART_PCIEX1A_CLAMP_CONTROL_0_CLAMP_WOFFSET                     0x0
#define PMC_IMPL_PART_PCIEX1A_CLAMP_CONTROL_0_CLAMP_DEFAULT                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX1A_CLAMP_CONTROL_0_CLAMP_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PCIEX1A_CLAMP_CONTROL_0_CLAMP_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX1A_CLAMP_CONTROL_0_CLAMP_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX1A_CLAMP_CONTROL_0_CLAMP_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX1A_CLAMP_CONTROL_0_CLAMP_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PCIEX1A_CLAMP_CONTROL_0_CLAMP_INIT_ENUM                   OFF
#define PMC_IMPL_PART_PCIEX1A_CLAMP_CONTROL_0_CLAMP_OFF                 _MK_ENUM_CONST(0)
#define PMC_IMPL_PART_PCIEX1A_CLAMP_CONTROL_0_CLAMP_ON                  _MK_ENUM_CONST(1)


// Register PMC_IMPL_PART_NVL_POWER_GATE_CONTROL_0
#define PMC_IMPL_PART_NVL_POWER_GATE_CONTROL_0                  _MK_ADDR_CONST(0x448)
#define PMC_IMPL_PART_NVL_POWER_GATE_CONTROL_0_SECURE                   0x0
#define PMC_IMPL_PART_NVL_POWER_GATE_CONTROL_0_DUAL                     0x0
#define PMC_IMPL_PART_NVL_POWER_GATE_CONTROL_0_SCR                      PG_NVL_SCR_0
#define PMC_IMPL_PART_NVL_POWER_GATE_CONTROL_0_WORD_COUNT                       0x1
#define PMC_IMPL_PART_NVL_POWER_GATE_CONTROL_0_RESET_VAL                        _MK_MASK_CONST(0x80000000)
#define PMC_IMPL_PART_NVL_POWER_GATE_CONTROL_0_RESET_MASK                       _MK_MASK_CONST(0x80000107)
#define PMC_IMPL_PART_NVL_POWER_GATE_CONTROL_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_NVL_POWER_GATE_CONTROL_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_NVL_POWER_GATE_CONTROL_0_READ_MASK                        _MK_MASK_CONST(0x80000107)
#define PMC_IMPL_PART_NVL_POWER_GATE_CONTROL_0_WRITE_MASK                       _MK_MASK_CONST(0x80000107)
#define PMC_IMPL_PART_NVL_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SHIFT                        _MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_NVL_POWER_GATE_CONTROL_0_LOGIC_SLEEP_FIELD                        _MK_FIELD_CONST(0x1, PMC_IMPL_PART_NVL_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SHIFT)
#define PMC_IMPL_PART_NVL_POWER_GATE_CONTROL_0_LOGIC_SLEEP_RANGE                        0:0
#define PMC_IMPL_PART_NVL_POWER_GATE_CONTROL_0_LOGIC_SLEEP_WOFFSET                      0x0
#define PMC_IMPL_PART_NVL_POWER_GATE_CONTROL_0_LOGIC_SLEEP_DEFAULT                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_NVL_POWER_GATE_CONTROL_0_LOGIC_SLEEP_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_NVL_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_NVL_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_NVL_POWER_GATE_CONTROL_0_LOGIC_SLEEP_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_NVL_POWER_GATE_CONTROL_0_LOGIC_SLEEP_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_NVL_POWER_GATE_CONTROL_0_LOGIC_SLEEP_INIT_ENUM                    OFF
#define PMC_IMPL_PART_NVL_POWER_GATE_CONTROL_0_LOGIC_SLEEP_OFF                  _MK_ENUM_CONST(0)
#define PMC_IMPL_PART_NVL_POWER_GATE_CONTROL_0_LOGIC_SLEEP_ON                   _MK_ENUM_CONST(1)

#define PMC_IMPL_PART_NVL_POWER_GATE_CONTROL_0_SRAM_RET_EN_SHIFT                        _MK_SHIFT_CONST(1)
#define PMC_IMPL_PART_NVL_POWER_GATE_CONTROL_0_SRAM_RET_EN_FIELD                        _MK_FIELD_CONST(0x1, PMC_IMPL_PART_NVL_POWER_GATE_CONTROL_0_SRAM_RET_EN_SHIFT)
#define PMC_IMPL_PART_NVL_POWER_GATE_CONTROL_0_SRAM_RET_EN_RANGE                        1:1
#define PMC_IMPL_PART_NVL_POWER_GATE_CONTROL_0_SRAM_RET_EN_WOFFSET                      0x0
#define PMC_IMPL_PART_NVL_POWER_GATE_CONTROL_0_SRAM_RET_EN_DEFAULT                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_NVL_POWER_GATE_CONTROL_0_SRAM_RET_EN_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_NVL_POWER_GATE_CONTROL_0_SRAM_RET_EN_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_NVL_POWER_GATE_CONTROL_0_SRAM_RET_EN_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_NVL_POWER_GATE_CONTROL_0_SRAM_RET_EN_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_NVL_POWER_GATE_CONTROL_0_SRAM_RET_EN_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_NVL_POWER_GATE_CONTROL_0_SRAM_RET_EN_INIT_ENUM                    OFF
#define PMC_IMPL_PART_NVL_POWER_GATE_CONTROL_0_SRAM_RET_EN_OFF                  _MK_ENUM_CONST(0)
#define PMC_IMPL_PART_NVL_POWER_GATE_CONTROL_0_SRAM_RET_EN_ON                   _MK_ENUM_CONST(1)

#define PMC_IMPL_PART_NVL_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SHIFT                      _MK_SHIFT_CONST(2)
#define PMC_IMPL_PART_NVL_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_FIELD                      _MK_FIELD_CONST(0x1, PMC_IMPL_PART_NVL_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SHIFT)
#define PMC_IMPL_PART_NVL_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_RANGE                      2:2
#define PMC_IMPL_PART_NVL_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_WOFFSET                    0x0
#define PMC_IMPL_PART_NVL_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_DEFAULT                    _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_NVL_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_NVL_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_NVL_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_NVL_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_NVL_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_NVL_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_INIT_ENUM                  OFF
#define PMC_IMPL_PART_NVL_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_OFF                        _MK_ENUM_CONST(0)
#define PMC_IMPL_PART_NVL_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_ON                 _MK_ENUM_CONST(1)

#define PMC_IMPL_PART_NVL_POWER_GATE_CONTROL_0_START_SHIFT                      _MK_SHIFT_CONST(8)
#define PMC_IMPL_PART_NVL_POWER_GATE_CONTROL_0_START_FIELD                      _MK_FIELD_CONST(0x1, PMC_IMPL_PART_NVL_POWER_GATE_CONTROL_0_START_SHIFT)
#define PMC_IMPL_PART_NVL_POWER_GATE_CONTROL_0_START_RANGE                      8:8
#define PMC_IMPL_PART_NVL_POWER_GATE_CONTROL_0_START_WOFFSET                    0x0
#define PMC_IMPL_PART_NVL_POWER_GATE_CONTROL_0_START_DEFAULT                    _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_NVL_POWER_GATE_CONTROL_0_START_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_NVL_POWER_GATE_CONTROL_0_START_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_NVL_POWER_GATE_CONTROL_0_START_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_NVL_POWER_GATE_CONTROL_0_START_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_NVL_POWER_GATE_CONTROL_0_START_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_NVL_POWER_GATE_CONTROL_0_START_INIT_ENUM                  DONE
#define PMC_IMPL_PART_NVL_POWER_GATE_CONTROL_0_START_DONE                       _MK_ENUM_CONST(0)
#define PMC_IMPL_PART_NVL_POWER_GATE_CONTROL_0_START_PENDING                    _MK_ENUM_CONST(1)

#define PMC_IMPL_PART_NVL_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SHIFT                        _MK_SHIFT_CONST(31)
#define PMC_IMPL_PART_NVL_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_FIELD                        _MK_FIELD_CONST(0x1, PMC_IMPL_PART_NVL_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SHIFT)
#define PMC_IMPL_PART_NVL_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_RANGE                        31:31
#define PMC_IMPL_PART_NVL_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_WOFFSET                      0x0
#define PMC_IMPL_PART_NVL_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_DEFAULT                      _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_NVL_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_NVL_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_NVL_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_NVL_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_NVL_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_NVL_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_INIT_ENUM                    ENABLE
#define PMC_IMPL_PART_NVL_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_DISABLE                      _MK_ENUM_CONST(0)
#define PMC_IMPL_PART_NVL_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_ENABLE                       _MK_ENUM_CONST(1)


// Register PMC_IMPL_PART_NVL_POWER_GATE_STATUS_0
#define PMC_IMPL_PART_NVL_POWER_GATE_STATUS_0                   _MK_ADDR_CONST(0x44c)
#define PMC_IMPL_PART_NVL_POWER_GATE_STATUS_0_SECURE                    0x0
#define PMC_IMPL_PART_NVL_POWER_GATE_STATUS_0_DUAL                      0x0
#define PMC_IMPL_PART_NVL_POWER_GATE_STATUS_0_SCR                       PG_NVL_SCR_0
#define PMC_IMPL_PART_NVL_POWER_GATE_STATUS_0_WORD_COUNT                        0x1
#define PMC_IMPL_PART_NVL_POWER_GATE_STATUS_0_RESET_VAL                         _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_NVL_POWER_GATE_STATUS_0_RESET_MASK                        _MK_MASK_CONST(0x7)
#define PMC_IMPL_PART_NVL_POWER_GATE_STATUS_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_NVL_POWER_GATE_STATUS_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_NVL_POWER_GATE_STATUS_0_READ_MASK                         _MK_MASK_CONST(0x7)
#define PMC_IMPL_PART_NVL_POWER_GATE_STATUS_0_WRITE_MASK                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_NVL_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SHIFT                     _MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_NVL_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_FIELD                     _MK_FIELD_CONST(0x1, PMC_IMPL_PART_NVL_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SHIFT)
#define PMC_IMPL_PART_NVL_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_RANGE                     0:0
#define PMC_IMPL_PART_NVL_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_WOFFSET                   0x0
#define PMC_IMPL_PART_NVL_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_DEFAULT                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_NVL_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_NVL_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_NVL_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_NVL_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_NVL_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_NVL_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_INIT_ENUM                 OFF
#define PMC_IMPL_PART_NVL_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_OFF                       _MK_ENUM_CONST(0)
#define PMC_IMPL_PART_NVL_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_ON                        _MK_ENUM_CONST(1)

#define PMC_IMPL_PART_NVL_POWER_GATE_STATUS_0_SRAM_RET_STS_SHIFT                        _MK_SHIFT_CONST(1)
#define PMC_IMPL_PART_NVL_POWER_GATE_STATUS_0_SRAM_RET_STS_FIELD                        _MK_FIELD_CONST(0x1, PMC_IMPL_PART_NVL_POWER_GATE_STATUS_0_SRAM_RET_STS_SHIFT)
#define PMC_IMPL_PART_NVL_POWER_GATE_STATUS_0_SRAM_RET_STS_RANGE                        1:1
#define PMC_IMPL_PART_NVL_POWER_GATE_STATUS_0_SRAM_RET_STS_WOFFSET                      0x0
#define PMC_IMPL_PART_NVL_POWER_GATE_STATUS_0_SRAM_RET_STS_DEFAULT                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_NVL_POWER_GATE_STATUS_0_SRAM_RET_STS_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_NVL_POWER_GATE_STATUS_0_SRAM_RET_STS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_NVL_POWER_GATE_STATUS_0_SRAM_RET_STS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_NVL_POWER_GATE_STATUS_0_SRAM_RET_STS_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_NVL_POWER_GATE_STATUS_0_SRAM_RET_STS_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_NVL_POWER_GATE_STATUS_0_SRAM_RET_STS_INIT_ENUM                    OFF
#define PMC_IMPL_PART_NVL_POWER_GATE_STATUS_0_SRAM_RET_STS_OFF                  _MK_ENUM_CONST(0)
#define PMC_IMPL_PART_NVL_POWER_GATE_STATUS_0_SRAM_RET_STS_ON                   _MK_ENUM_CONST(1)

#define PMC_IMPL_PART_NVL_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SHIFT                      _MK_SHIFT_CONST(2)
#define PMC_IMPL_PART_NVL_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_FIELD                      _MK_FIELD_CONST(0x1, PMC_IMPL_PART_NVL_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SHIFT)
#define PMC_IMPL_PART_NVL_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_RANGE                      2:2
#define PMC_IMPL_PART_NVL_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_WOFFSET                    0x0
#define PMC_IMPL_PART_NVL_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_DEFAULT                    _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_NVL_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_NVL_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_NVL_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_NVL_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_NVL_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_NVL_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_INIT_ENUM                  OFF
#define PMC_IMPL_PART_NVL_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_OFF                        _MK_ENUM_CONST(0)
#define PMC_IMPL_PART_NVL_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_ON                 _MK_ENUM_CONST(1)


// Register PMC_IMPL_PART_NVL_CLAMP_CONTROL_0
#define PMC_IMPL_PART_NVL_CLAMP_CONTROL_0                       _MK_ADDR_CONST(0x450)
#define PMC_IMPL_PART_NVL_CLAMP_CONTROL_0_SECURE                        0x0
#define PMC_IMPL_PART_NVL_CLAMP_CONTROL_0_DUAL                  0x0
#define PMC_IMPL_PART_NVL_CLAMP_CONTROL_0_SCR                   PG_NVL_SCR_0
#define PMC_IMPL_PART_NVL_CLAMP_CONTROL_0_WORD_COUNT                    0x1
#define PMC_IMPL_PART_NVL_CLAMP_CONTROL_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_NVL_CLAMP_CONTROL_0_RESET_MASK                    _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_NVL_CLAMP_CONTROL_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_NVL_CLAMP_CONTROL_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_NVL_CLAMP_CONTROL_0_READ_MASK                     _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_NVL_CLAMP_CONTROL_0_WRITE_MASK                    _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_NVL_CLAMP_CONTROL_0_CLAMP_SHIFT                   _MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_NVL_CLAMP_CONTROL_0_CLAMP_FIELD                   _MK_FIELD_CONST(0x1, PMC_IMPL_PART_NVL_CLAMP_CONTROL_0_CLAMP_SHIFT)
#define PMC_IMPL_PART_NVL_CLAMP_CONTROL_0_CLAMP_RANGE                   0:0
#define PMC_IMPL_PART_NVL_CLAMP_CONTROL_0_CLAMP_WOFFSET                 0x0
#define PMC_IMPL_PART_NVL_CLAMP_CONTROL_0_CLAMP_DEFAULT                 _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_NVL_CLAMP_CONTROL_0_CLAMP_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_NVL_CLAMP_CONTROL_0_CLAMP_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_NVL_CLAMP_CONTROL_0_CLAMP_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_NVL_CLAMP_CONTROL_0_CLAMP_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_NVL_CLAMP_CONTROL_0_CLAMP_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_NVL_CLAMP_CONTROL_0_CLAMP_INIT_ENUM                       OFF
#define PMC_IMPL_PART_NVL_CLAMP_CONTROL_0_CLAMP_OFF                     _MK_ENUM_CONST(0)
#define PMC_IMPL_PART_NVL_CLAMP_CONTROL_0_CLAMP_ON                      _MK_ENUM_CONST(1)


// Register PMC_IMPL_PART_PCIEX8B_POWER_GATE_CONTROL_0
#define PMC_IMPL_PART_PCIEX8B_POWER_GATE_CONTROL_0                      _MK_ADDR_CONST(0x454)
#define PMC_IMPL_PART_PCIEX8B_POWER_GATE_CONTROL_0_SECURE                       0x0
#define PMC_IMPL_PART_PCIEX8B_POWER_GATE_CONTROL_0_DUAL                         0x0
#define PMC_IMPL_PART_PCIEX8B_POWER_GATE_CONTROL_0_SCR                  PG_PCIEX8B_SCR_0
#define PMC_IMPL_PART_PCIEX8B_POWER_GATE_CONTROL_0_WORD_COUNT                   0x1
#define PMC_IMPL_PART_PCIEX8B_POWER_GATE_CONTROL_0_RESET_VAL                    _MK_MASK_CONST(0x80000000)
#define PMC_IMPL_PART_PCIEX8B_POWER_GATE_CONTROL_0_RESET_MASK                   _MK_MASK_CONST(0x80000107)
#define PMC_IMPL_PART_PCIEX8B_POWER_GATE_CONTROL_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX8B_POWER_GATE_CONTROL_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX8B_POWER_GATE_CONTROL_0_READ_MASK                    _MK_MASK_CONST(0x80000107)
#define PMC_IMPL_PART_PCIEX8B_POWER_GATE_CONTROL_0_WRITE_MASK                   _MK_MASK_CONST(0x80000107)
#define PMC_IMPL_PART_PCIEX8B_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SHIFT                    _MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_PCIEX8B_POWER_GATE_CONTROL_0_LOGIC_SLEEP_FIELD                    _MK_FIELD_CONST(0x1, PMC_IMPL_PART_PCIEX8B_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SHIFT)
#define PMC_IMPL_PART_PCIEX8B_POWER_GATE_CONTROL_0_LOGIC_SLEEP_RANGE                    0:0
#define PMC_IMPL_PART_PCIEX8B_POWER_GATE_CONTROL_0_LOGIC_SLEEP_WOFFSET                  0x0
#define PMC_IMPL_PART_PCIEX8B_POWER_GATE_CONTROL_0_LOGIC_SLEEP_DEFAULT                  _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX8B_POWER_GATE_CONTROL_0_LOGIC_SLEEP_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PCIEX8B_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX8B_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX8B_POWER_GATE_CONTROL_0_LOGIC_SLEEP_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX8B_POWER_GATE_CONTROL_0_LOGIC_SLEEP_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PCIEX8B_POWER_GATE_CONTROL_0_LOGIC_SLEEP_INIT_ENUM                        OFF
#define PMC_IMPL_PART_PCIEX8B_POWER_GATE_CONTROL_0_LOGIC_SLEEP_OFF                      _MK_ENUM_CONST(0)
#define PMC_IMPL_PART_PCIEX8B_POWER_GATE_CONTROL_0_LOGIC_SLEEP_ON                       _MK_ENUM_CONST(1)

#define PMC_IMPL_PART_PCIEX8B_POWER_GATE_CONTROL_0_SRAM_RET_EN_SHIFT                    _MK_SHIFT_CONST(1)
#define PMC_IMPL_PART_PCIEX8B_POWER_GATE_CONTROL_0_SRAM_RET_EN_FIELD                    _MK_FIELD_CONST(0x1, PMC_IMPL_PART_PCIEX8B_POWER_GATE_CONTROL_0_SRAM_RET_EN_SHIFT)
#define PMC_IMPL_PART_PCIEX8B_POWER_GATE_CONTROL_0_SRAM_RET_EN_RANGE                    1:1
#define PMC_IMPL_PART_PCIEX8B_POWER_GATE_CONTROL_0_SRAM_RET_EN_WOFFSET                  0x0
#define PMC_IMPL_PART_PCIEX8B_POWER_GATE_CONTROL_0_SRAM_RET_EN_DEFAULT                  _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX8B_POWER_GATE_CONTROL_0_SRAM_RET_EN_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PCIEX8B_POWER_GATE_CONTROL_0_SRAM_RET_EN_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX8B_POWER_GATE_CONTROL_0_SRAM_RET_EN_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX8B_POWER_GATE_CONTROL_0_SRAM_RET_EN_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX8B_POWER_GATE_CONTROL_0_SRAM_RET_EN_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PCIEX8B_POWER_GATE_CONTROL_0_SRAM_RET_EN_INIT_ENUM                        OFF
#define PMC_IMPL_PART_PCIEX8B_POWER_GATE_CONTROL_0_SRAM_RET_EN_OFF                      _MK_ENUM_CONST(0)
#define PMC_IMPL_PART_PCIEX8B_POWER_GATE_CONTROL_0_SRAM_RET_EN_ON                       _MK_ENUM_CONST(1)

#define PMC_IMPL_PART_PCIEX8B_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SHIFT                  _MK_SHIFT_CONST(2)
#define PMC_IMPL_PART_PCIEX8B_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_FIELD                  _MK_FIELD_CONST(0x1, PMC_IMPL_PART_PCIEX8B_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SHIFT)
#define PMC_IMPL_PART_PCIEX8B_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_RANGE                  2:2
#define PMC_IMPL_PART_PCIEX8B_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_WOFFSET                        0x0
#define PMC_IMPL_PART_PCIEX8B_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_DEFAULT                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX8B_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PCIEX8B_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX8B_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX8B_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX8B_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PCIEX8B_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_INIT_ENUM                      OFF
#define PMC_IMPL_PART_PCIEX8B_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_OFF                    _MK_ENUM_CONST(0)
#define PMC_IMPL_PART_PCIEX8B_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_ON                     _MK_ENUM_CONST(1)

#define PMC_IMPL_PART_PCIEX8B_POWER_GATE_CONTROL_0_START_SHIFT                  _MK_SHIFT_CONST(8)
#define PMC_IMPL_PART_PCIEX8B_POWER_GATE_CONTROL_0_START_FIELD                  _MK_FIELD_CONST(0x1, PMC_IMPL_PART_PCIEX8B_POWER_GATE_CONTROL_0_START_SHIFT)
#define PMC_IMPL_PART_PCIEX8B_POWER_GATE_CONTROL_0_START_RANGE                  8:8
#define PMC_IMPL_PART_PCIEX8B_POWER_GATE_CONTROL_0_START_WOFFSET                        0x0
#define PMC_IMPL_PART_PCIEX8B_POWER_GATE_CONTROL_0_START_DEFAULT                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX8B_POWER_GATE_CONTROL_0_START_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PCIEX8B_POWER_GATE_CONTROL_0_START_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX8B_POWER_GATE_CONTROL_0_START_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX8B_POWER_GATE_CONTROL_0_START_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX8B_POWER_GATE_CONTROL_0_START_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PCIEX8B_POWER_GATE_CONTROL_0_START_INIT_ENUM                      DONE
#define PMC_IMPL_PART_PCIEX8B_POWER_GATE_CONTROL_0_START_DONE                   _MK_ENUM_CONST(0)
#define PMC_IMPL_PART_PCIEX8B_POWER_GATE_CONTROL_0_START_PENDING                        _MK_ENUM_CONST(1)

#define PMC_IMPL_PART_PCIEX8B_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SHIFT                    _MK_SHIFT_CONST(31)
#define PMC_IMPL_PART_PCIEX8B_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_FIELD                    _MK_FIELD_CONST(0x1, PMC_IMPL_PART_PCIEX8B_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SHIFT)
#define PMC_IMPL_PART_PCIEX8B_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_RANGE                    31:31
#define PMC_IMPL_PART_PCIEX8B_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_WOFFSET                  0x0
#define PMC_IMPL_PART_PCIEX8B_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_DEFAULT                  _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PCIEX8B_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PCIEX8B_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX8B_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX8B_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX8B_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PCIEX8B_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_INIT_ENUM                        ENABLE
#define PMC_IMPL_PART_PCIEX8B_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_DISABLE                  _MK_ENUM_CONST(0)
#define PMC_IMPL_PART_PCIEX8B_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_ENABLE                   _MK_ENUM_CONST(1)


// Register PMC_IMPL_PART_PCIEX8B_POWER_GATE_STATUS_0
#define PMC_IMPL_PART_PCIEX8B_POWER_GATE_STATUS_0                       _MK_ADDR_CONST(0x458)
#define PMC_IMPL_PART_PCIEX8B_POWER_GATE_STATUS_0_SECURE                        0x0
#define PMC_IMPL_PART_PCIEX8B_POWER_GATE_STATUS_0_DUAL                  0x0
#define PMC_IMPL_PART_PCIEX8B_POWER_GATE_STATUS_0_SCR                   PG_PCIEX8B_SCR_0
#define PMC_IMPL_PART_PCIEX8B_POWER_GATE_STATUS_0_WORD_COUNT                    0x1
#define PMC_IMPL_PART_PCIEX8B_POWER_GATE_STATUS_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX8B_POWER_GATE_STATUS_0_RESET_MASK                    _MK_MASK_CONST(0x7)
#define PMC_IMPL_PART_PCIEX8B_POWER_GATE_STATUS_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX8B_POWER_GATE_STATUS_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX8B_POWER_GATE_STATUS_0_READ_MASK                     _MK_MASK_CONST(0x7)
#define PMC_IMPL_PART_PCIEX8B_POWER_GATE_STATUS_0_WRITE_MASK                    _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX8B_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SHIFT                 _MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_PCIEX8B_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_FIELD                 _MK_FIELD_CONST(0x1, PMC_IMPL_PART_PCIEX8B_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SHIFT)
#define PMC_IMPL_PART_PCIEX8B_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_RANGE                 0:0
#define PMC_IMPL_PART_PCIEX8B_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_WOFFSET                       0x0
#define PMC_IMPL_PART_PCIEX8B_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_DEFAULT                       _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX8B_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PCIEX8B_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX8B_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX8B_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX8B_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PCIEX8B_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_INIT_ENUM                     OFF
#define PMC_IMPL_PART_PCIEX8B_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_OFF                   _MK_ENUM_CONST(0)
#define PMC_IMPL_PART_PCIEX8B_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_ON                    _MK_ENUM_CONST(1)

#define PMC_IMPL_PART_PCIEX8B_POWER_GATE_STATUS_0_SRAM_RET_STS_SHIFT                    _MK_SHIFT_CONST(1)
#define PMC_IMPL_PART_PCIEX8B_POWER_GATE_STATUS_0_SRAM_RET_STS_FIELD                    _MK_FIELD_CONST(0x1, PMC_IMPL_PART_PCIEX8B_POWER_GATE_STATUS_0_SRAM_RET_STS_SHIFT)
#define PMC_IMPL_PART_PCIEX8B_POWER_GATE_STATUS_0_SRAM_RET_STS_RANGE                    1:1
#define PMC_IMPL_PART_PCIEX8B_POWER_GATE_STATUS_0_SRAM_RET_STS_WOFFSET                  0x0
#define PMC_IMPL_PART_PCIEX8B_POWER_GATE_STATUS_0_SRAM_RET_STS_DEFAULT                  _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX8B_POWER_GATE_STATUS_0_SRAM_RET_STS_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PCIEX8B_POWER_GATE_STATUS_0_SRAM_RET_STS_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX8B_POWER_GATE_STATUS_0_SRAM_RET_STS_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX8B_POWER_GATE_STATUS_0_SRAM_RET_STS_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX8B_POWER_GATE_STATUS_0_SRAM_RET_STS_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PCIEX8B_POWER_GATE_STATUS_0_SRAM_RET_STS_INIT_ENUM                        OFF
#define PMC_IMPL_PART_PCIEX8B_POWER_GATE_STATUS_0_SRAM_RET_STS_OFF                      _MK_ENUM_CONST(0)
#define PMC_IMPL_PART_PCIEX8B_POWER_GATE_STATUS_0_SRAM_RET_STS_ON                       _MK_ENUM_CONST(1)

#define PMC_IMPL_PART_PCIEX8B_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SHIFT                  _MK_SHIFT_CONST(2)
#define PMC_IMPL_PART_PCIEX8B_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_FIELD                  _MK_FIELD_CONST(0x1, PMC_IMPL_PART_PCIEX8B_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SHIFT)
#define PMC_IMPL_PART_PCIEX8B_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_RANGE                  2:2
#define PMC_IMPL_PART_PCIEX8B_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_WOFFSET                        0x0
#define PMC_IMPL_PART_PCIEX8B_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_DEFAULT                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX8B_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PCIEX8B_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX8B_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX8B_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX8B_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PCIEX8B_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_INIT_ENUM                      OFF
#define PMC_IMPL_PART_PCIEX8B_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_OFF                    _MK_ENUM_CONST(0)
#define PMC_IMPL_PART_PCIEX8B_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_ON                     _MK_ENUM_CONST(1)


// Register PMC_IMPL_PART_PCIEX8B_CLAMP_CONTROL_0
#define PMC_IMPL_PART_PCIEX8B_CLAMP_CONTROL_0                   _MK_ADDR_CONST(0x45c)
#define PMC_IMPL_PART_PCIEX8B_CLAMP_CONTROL_0_SECURE                    0x0
#define PMC_IMPL_PART_PCIEX8B_CLAMP_CONTROL_0_DUAL                      0x0
#define PMC_IMPL_PART_PCIEX8B_CLAMP_CONTROL_0_SCR                       PG_PCIEX8B_SCR_0
#define PMC_IMPL_PART_PCIEX8B_CLAMP_CONTROL_0_WORD_COUNT                        0x1
#define PMC_IMPL_PART_PCIEX8B_CLAMP_CONTROL_0_RESET_VAL                         _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX8B_CLAMP_CONTROL_0_RESET_MASK                        _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PCIEX8B_CLAMP_CONTROL_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX8B_CLAMP_CONTROL_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX8B_CLAMP_CONTROL_0_READ_MASK                         _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PCIEX8B_CLAMP_CONTROL_0_WRITE_MASK                        _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PCIEX8B_CLAMP_CONTROL_0_CLAMP_SHIFT                       _MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_PCIEX8B_CLAMP_CONTROL_0_CLAMP_FIELD                       _MK_FIELD_CONST(0x1, PMC_IMPL_PART_PCIEX8B_CLAMP_CONTROL_0_CLAMP_SHIFT)
#define PMC_IMPL_PART_PCIEX8B_CLAMP_CONTROL_0_CLAMP_RANGE                       0:0
#define PMC_IMPL_PART_PCIEX8B_CLAMP_CONTROL_0_CLAMP_WOFFSET                     0x0
#define PMC_IMPL_PART_PCIEX8B_CLAMP_CONTROL_0_CLAMP_DEFAULT                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX8B_CLAMP_CONTROL_0_CLAMP_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PCIEX8B_CLAMP_CONTROL_0_CLAMP_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX8B_CLAMP_CONTROL_0_CLAMP_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX8B_CLAMP_CONTROL_0_CLAMP_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PCIEX8B_CLAMP_CONTROL_0_CLAMP_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PCIEX8B_CLAMP_CONTROL_0_CLAMP_INIT_ENUM                   OFF
#define PMC_IMPL_PART_PCIEX8B_CLAMP_CONTROL_0_CLAMP_OFF                 _MK_ENUM_CONST(0)
#define PMC_IMPL_PART_PCIEX8B_CLAMP_CONTROL_0_CLAMP_ON                  _MK_ENUM_CONST(1)


// Register PMC_IMPL_PART_PVAA_POWER_GATE_CONTROL_0
#define PMC_IMPL_PART_PVAA_POWER_GATE_CONTROL_0                 _MK_ADDR_CONST(0x460)
#define PMC_IMPL_PART_PVAA_POWER_GATE_CONTROL_0_SECURE                  0x0
#define PMC_IMPL_PART_PVAA_POWER_GATE_CONTROL_0_DUAL                    0x0
#define PMC_IMPL_PART_PVAA_POWER_GATE_CONTROL_0_SCR                     PG_PVAA_SCR_0
#define PMC_IMPL_PART_PVAA_POWER_GATE_CONTROL_0_WORD_COUNT                      0x1
#define PMC_IMPL_PART_PVAA_POWER_GATE_CONTROL_0_RESET_VAL                       _MK_MASK_CONST(0x80000005)
#define PMC_IMPL_PART_PVAA_POWER_GATE_CONTROL_0_RESET_MASK                      _MK_MASK_CONST(0x80000107)
#define PMC_IMPL_PART_PVAA_POWER_GATE_CONTROL_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PVAA_POWER_GATE_CONTROL_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PVAA_POWER_GATE_CONTROL_0_READ_MASK                       _MK_MASK_CONST(0x80000107)
#define PMC_IMPL_PART_PVAA_POWER_GATE_CONTROL_0_WRITE_MASK                      _MK_MASK_CONST(0x80000107)
#define PMC_IMPL_PART_PVAA_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SHIFT                       _MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_PVAA_POWER_GATE_CONTROL_0_LOGIC_SLEEP_FIELD                       _MK_FIELD_CONST(0x1, PMC_IMPL_PART_PVAA_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SHIFT)
#define PMC_IMPL_PART_PVAA_POWER_GATE_CONTROL_0_LOGIC_SLEEP_RANGE                       0:0
#define PMC_IMPL_PART_PVAA_POWER_GATE_CONTROL_0_LOGIC_SLEEP_WOFFSET                     0x0
#define PMC_IMPL_PART_PVAA_POWER_GATE_CONTROL_0_LOGIC_SLEEP_DEFAULT                     _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PVAA_POWER_GATE_CONTROL_0_LOGIC_SLEEP_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PVAA_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PVAA_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PVAA_POWER_GATE_CONTROL_0_LOGIC_SLEEP_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PVAA_POWER_GATE_CONTROL_0_LOGIC_SLEEP_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PVAA_POWER_GATE_CONTROL_0_LOGIC_SLEEP_INIT_ENUM                   ON
#define PMC_IMPL_PART_PVAA_POWER_GATE_CONTROL_0_LOGIC_SLEEP_OFF                 _MK_ENUM_CONST(0)
#define PMC_IMPL_PART_PVAA_POWER_GATE_CONTROL_0_LOGIC_SLEEP_ON                  _MK_ENUM_CONST(1)

#define PMC_IMPL_PART_PVAA_POWER_GATE_CONTROL_0_SRAM_RET_EN_SHIFT                       _MK_SHIFT_CONST(1)
#define PMC_IMPL_PART_PVAA_POWER_GATE_CONTROL_0_SRAM_RET_EN_FIELD                       _MK_FIELD_CONST(0x1, PMC_IMPL_PART_PVAA_POWER_GATE_CONTROL_0_SRAM_RET_EN_SHIFT)
#define PMC_IMPL_PART_PVAA_POWER_GATE_CONTROL_0_SRAM_RET_EN_RANGE                       1:1
#define PMC_IMPL_PART_PVAA_POWER_GATE_CONTROL_0_SRAM_RET_EN_WOFFSET                     0x0
#define PMC_IMPL_PART_PVAA_POWER_GATE_CONTROL_0_SRAM_RET_EN_DEFAULT                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PVAA_POWER_GATE_CONTROL_0_SRAM_RET_EN_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PVAA_POWER_GATE_CONTROL_0_SRAM_RET_EN_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PVAA_POWER_GATE_CONTROL_0_SRAM_RET_EN_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PVAA_POWER_GATE_CONTROL_0_SRAM_RET_EN_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PVAA_POWER_GATE_CONTROL_0_SRAM_RET_EN_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PVAA_POWER_GATE_CONTROL_0_SRAM_RET_EN_INIT_ENUM                   OFF
#define PMC_IMPL_PART_PVAA_POWER_GATE_CONTROL_0_SRAM_RET_EN_OFF                 _MK_ENUM_CONST(0)
#define PMC_IMPL_PART_PVAA_POWER_GATE_CONTROL_0_SRAM_RET_EN_ON                  _MK_ENUM_CONST(1)

#define PMC_IMPL_PART_PVAA_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SHIFT                     _MK_SHIFT_CONST(2)
#define PMC_IMPL_PART_PVAA_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_FIELD                     _MK_FIELD_CONST(0x1, PMC_IMPL_PART_PVAA_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SHIFT)
#define PMC_IMPL_PART_PVAA_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_RANGE                     2:2
#define PMC_IMPL_PART_PVAA_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_WOFFSET                   0x0
#define PMC_IMPL_PART_PVAA_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_DEFAULT                   _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PVAA_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PVAA_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PVAA_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PVAA_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PVAA_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PVAA_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_INIT_ENUM                 ON
#define PMC_IMPL_PART_PVAA_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_OFF                       _MK_ENUM_CONST(0)
#define PMC_IMPL_PART_PVAA_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_ON                        _MK_ENUM_CONST(1)

#define PMC_IMPL_PART_PVAA_POWER_GATE_CONTROL_0_START_SHIFT                     _MK_SHIFT_CONST(8)
#define PMC_IMPL_PART_PVAA_POWER_GATE_CONTROL_0_START_FIELD                     _MK_FIELD_CONST(0x1, PMC_IMPL_PART_PVAA_POWER_GATE_CONTROL_0_START_SHIFT)
#define PMC_IMPL_PART_PVAA_POWER_GATE_CONTROL_0_START_RANGE                     8:8
#define PMC_IMPL_PART_PVAA_POWER_GATE_CONTROL_0_START_WOFFSET                   0x0
#define PMC_IMPL_PART_PVAA_POWER_GATE_CONTROL_0_START_DEFAULT                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PVAA_POWER_GATE_CONTROL_0_START_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PVAA_POWER_GATE_CONTROL_0_START_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PVAA_POWER_GATE_CONTROL_0_START_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PVAA_POWER_GATE_CONTROL_0_START_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PVAA_POWER_GATE_CONTROL_0_START_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PVAA_POWER_GATE_CONTROL_0_START_INIT_ENUM                 DONE
#define PMC_IMPL_PART_PVAA_POWER_GATE_CONTROL_0_START_DONE                      _MK_ENUM_CONST(0)
#define PMC_IMPL_PART_PVAA_POWER_GATE_CONTROL_0_START_PENDING                   _MK_ENUM_CONST(1)

#define PMC_IMPL_PART_PVAA_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SHIFT                       _MK_SHIFT_CONST(31)
#define PMC_IMPL_PART_PVAA_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_FIELD                       _MK_FIELD_CONST(0x1, PMC_IMPL_PART_PVAA_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SHIFT)
#define PMC_IMPL_PART_PVAA_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_RANGE                       31:31
#define PMC_IMPL_PART_PVAA_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_WOFFSET                     0x0
#define PMC_IMPL_PART_PVAA_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_DEFAULT                     _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PVAA_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PVAA_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PVAA_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PVAA_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PVAA_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PVAA_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_INIT_ENUM                   ENABLE
#define PMC_IMPL_PART_PVAA_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_DISABLE                     _MK_ENUM_CONST(0)
#define PMC_IMPL_PART_PVAA_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_ENABLE                      _MK_ENUM_CONST(1)


// Register PMC_IMPL_PART_PVAA_POWER_GATE_STATUS_0
#define PMC_IMPL_PART_PVAA_POWER_GATE_STATUS_0                  _MK_ADDR_CONST(0x464)
#define PMC_IMPL_PART_PVAA_POWER_GATE_STATUS_0_SECURE                   0x0
#define PMC_IMPL_PART_PVAA_POWER_GATE_STATUS_0_DUAL                     0x0
#define PMC_IMPL_PART_PVAA_POWER_GATE_STATUS_0_SCR                      PG_PVAA_SCR_0
#define PMC_IMPL_PART_PVAA_POWER_GATE_STATUS_0_WORD_COUNT                       0x1
#define PMC_IMPL_PART_PVAA_POWER_GATE_STATUS_0_RESET_VAL                        _MK_MASK_CONST(0x5)
#define PMC_IMPL_PART_PVAA_POWER_GATE_STATUS_0_RESET_MASK                       _MK_MASK_CONST(0x7)
#define PMC_IMPL_PART_PVAA_POWER_GATE_STATUS_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PVAA_POWER_GATE_STATUS_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PVAA_POWER_GATE_STATUS_0_READ_MASK                        _MK_MASK_CONST(0x7)
#define PMC_IMPL_PART_PVAA_POWER_GATE_STATUS_0_WRITE_MASK                       _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PVAA_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SHIFT                    _MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_PVAA_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_FIELD                    _MK_FIELD_CONST(0x1, PMC_IMPL_PART_PVAA_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SHIFT)
#define PMC_IMPL_PART_PVAA_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_RANGE                    0:0
#define PMC_IMPL_PART_PVAA_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_WOFFSET                  0x0
#define PMC_IMPL_PART_PVAA_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_DEFAULT                  _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PVAA_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PVAA_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PVAA_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PVAA_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PVAA_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PVAA_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_INIT_ENUM                        ON
#define PMC_IMPL_PART_PVAA_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_OFF                      _MK_ENUM_CONST(0)
#define PMC_IMPL_PART_PVAA_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_ON                       _MK_ENUM_CONST(1)

#define PMC_IMPL_PART_PVAA_POWER_GATE_STATUS_0_SRAM_RET_STS_SHIFT                       _MK_SHIFT_CONST(1)
#define PMC_IMPL_PART_PVAA_POWER_GATE_STATUS_0_SRAM_RET_STS_FIELD                       _MK_FIELD_CONST(0x1, PMC_IMPL_PART_PVAA_POWER_GATE_STATUS_0_SRAM_RET_STS_SHIFT)
#define PMC_IMPL_PART_PVAA_POWER_GATE_STATUS_0_SRAM_RET_STS_RANGE                       1:1
#define PMC_IMPL_PART_PVAA_POWER_GATE_STATUS_0_SRAM_RET_STS_WOFFSET                     0x0
#define PMC_IMPL_PART_PVAA_POWER_GATE_STATUS_0_SRAM_RET_STS_DEFAULT                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PVAA_POWER_GATE_STATUS_0_SRAM_RET_STS_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PVAA_POWER_GATE_STATUS_0_SRAM_RET_STS_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PVAA_POWER_GATE_STATUS_0_SRAM_RET_STS_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PVAA_POWER_GATE_STATUS_0_SRAM_RET_STS_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PVAA_POWER_GATE_STATUS_0_SRAM_RET_STS_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PVAA_POWER_GATE_STATUS_0_SRAM_RET_STS_INIT_ENUM                   OFF
#define PMC_IMPL_PART_PVAA_POWER_GATE_STATUS_0_SRAM_RET_STS_OFF                 _MK_ENUM_CONST(0)
#define PMC_IMPL_PART_PVAA_POWER_GATE_STATUS_0_SRAM_RET_STS_ON                  _MK_ENUM_CONST(1)

#define PMC_IMPL_PART_PVAA_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SHIFT                     _MK_SHIFT_CONST(2)
#define PMC_IMPL_PART_PVAA_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_FIELD                     _MK_FIELD_CONST(0x1, PMC_IMPL_PART_PVAA_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SHIFT)
#define PMC_IMPL_PART_PVAA_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_RANGE                     2:2
#define PMC_IMPL_PART_PVAA_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_WOFFSET                   0x0
#define PMC_IMPL_PART_PVAA_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_DEFAULT                   _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PVAA_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PVAA_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PVAA_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PVAA_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PVAA_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PVAA_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_INIT_ENUM                 ON
#define PMC_IMPL_PART_PVAA_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_OFF                       _MK_ENUM_CONST(0)
#define PMC_IMPL_PART_PVAA_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_ON                        _MK_ENUM_CONST(1)


// Register PMC_IMPL_PART_PVAA_CLAMP_CONTROL_0
#define PMC_IMPL_PART_PVAA_CLAMP_CONTROL_0                      _MK_ADDR_CONST(0x468)
#define PMC_IMPL_PART_PVAA_CLAMP_CONTROL_0_SECURE                       0x0
#define PMC_IMPL_PART_PVAA_CLAMP_CONTROL_0_DUAL                         0x0
#define PMC_IMPL_PART_PVAA_CLAMP_CONTROL_0_SCR                  PG_PVAA_SCR_0
#define PMC_IMPL_PART_PVAA_CLAMP_CONTROL_0_WORD_COUNT                   0x1
#define PMC_IMPL_PART_PVAA_CLAMP_CONTROL_0_RESET_VAL                    _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PVAA_CLAMP_CONTROL_0_RESET_MASK                   _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PVAA_CLAMP_CONTROL_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PVAA_CLAMP_CONTROL_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PVAA_CLAMP_CONTROL_0_READ_MASK                    _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PVAA_CLAMP_CONTROL_0_WRITE_MASK                   _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PVAA_CLAMP_CONTROL_0_CLAMP_SHIFT                  _MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_PVAA_CLAMP_CONTROL_0_CLAMP_FIELD                  _MK_FIELD_CONST(0x1, PMC_IMPL_PART_PVAA_CLAMP_CONTROL_0_CLAMP_SHIFT)
#define PMC_IMPL_PART_PVAA_CLAMP_CONTROL_0_CLAMP_RANGE                  0:0
#define PMC_IMPL_PART_PVAA_CLAMP_CONTROL_0_CLAMP_WOFFSET                        0x0
#define PMC_IMPL_PART_PVAA_CLAMP_CONTROL_0_CLAMP_DEFAULT                        _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PVAA_CLAMP_CONTROL_0_CLAMP_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PVAA_CLAMP_CONTROL_0_CLAMP_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PVAA_CLAMP_CONTROL_0_CLAMP_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PVAA_CLAMP_CONTROL_0_CLAMP_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PVAA_CLAMP_CONTROL_0_CLAMP_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PVAA_CLAMP_CONTROL_0_CLAMP_INIT_ENUM                      ON
#define PMC_IMPL_PART_PVAA_CLAMP_CONTROL_0_CLAMP_OFF                    _MK_ENUM_CONST(0)
#define PMC_IMPL_PART_PVAA_CLAMP_CONTROL_0_CLAMP_ON                     _MK_ENUM_CONST(1)


// Register PMC_IMPL_PART_PVAB_POWER_GATE_CONTROL_0
#define PMC_IMPL_PART_PVAB_POWER_GATE_CONTROL_0                 _MK_ADDR_CONST(0x46c)
#define PMC_IMPL_PART_PVAB_POWER_GATE_CONTROL_0_SECURE                  0x0
#define PMC_IMPL_PART_PVAB_POWER_GATE_CONTROL_0_DUAL                    0x0
#define PMC_IMPL_PART_PVAB_POWER_GATE_CONTROL_0_SCR                     PG_PVAB_SCR_0
#define PMC_IMPL_PART_PVAB_POWER_GATE_CONTROL_0_WORD_COUNT                      0x1
#define PMC_IMPL_PART_PVAB_POWER_GATE_CONTROL_0_RESET_VAL                       _MK_MASK_CONST(0x80000005)
#define PMC_IMPL_PART_PVAB_POWER_GATE_CONTROL_0_RESET_MASK                      _MK_MASK_CONST(0x80000107)
#define PMC_IMPL_PART_PVAB_POWER_GATE_CONTROL_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PVAB_POWER_GATE_CONTROL_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PVAB_POWER_GATE_CONTROL_0_READ_MASK                       _MK_MASK_CONST(0x80000107)
#define PMC_IMPL_PART_PVAB_POWER_GATE_CONTROL_0_WRITE_MASK                      _MK_MASK_CONST(0x80000107)
#define PMC_IMPL_PART_PVAB_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SHIFT                       _MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_PVAB_POWER_GATE_CONTROL_0_LOGIC_SLEEP_FIELD                       _MK_FIELD_CONST(0x1, PMC_IMPL_PART_PVAB_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SHIFT)
#define PMC_IMPL_PART_PVAB_POWER_GATE_CONTROL_0_LOGIC_SLEEP_RANGE                       0:0
#define PMC_IMPL_PART_PVAB_POWER_GATE_CONTROL_0_LOGIC_SLEEP_WOFFSET                     0x0
#define PMC_IMPL_PART_PVAB_POWER_GATE_CONTROL_0_LOGIC_SLEEP_DEFAULT                     _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PVAB_POWER_GATE_CONTROL_0_LOGIC_SLEEP_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PVAB_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PVAB_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PVAB_POWER_GATE_CONTROL_0_LOGIC_SLEEP_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PVAB_POWER_GATE_CONTROL_0_LOGIC_SLEEP_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PVAB_POWER_GATE_CONTROL_0_LOGIC_SLEEP_INIT_ENUM                   ON
#define PMC_IMPL_PART_PVAB_POWER_GATE_CONTROL_0_LOGIC_SLEEP_OFF                 _MK_ENUM_CONST(0)
#define PMC_IMPL_PART_PVAB_POWER_GATE_CONTROL_0_LOGIC_SLEEP_ON                  _MK_ENUM_CONST(1)

#define PMC_IMPL_PART_PVAB_POWER_GATE_CONTROL_0_SRAM_RET_EN_SHIFT                       _MK_SHIFT_CONST(1)
#define PMC_IMPL_PART_PVAB_POWER_GATE_CONTROL_0_SRAM_RET_EN_FIELD                       _MK_FIELD_CONST(0x1, PMC_IMPL_PART_PVAB_POWER_GATE_CONTROL_0_SRAM_RET_EN_SHIFT)
#define PMC_IMPL_PART_PVAB_POWER_GATE_CONTROL_0_SRAM_RET_EN_RANGE                       1:1
#define PMC_IMPL_PART_PVAB_POWER_GATE_CONTROL_0_SRAM_RET_EN_WOFFSET                     0x0
#define PMC_IMPL_PART_PVAB_POWER_GATE_CONTROL_0_SRAM_RET_EN_DEFAULT                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PVAB_POWER_GATE_CONTROL_0_SRAM_RET_EN_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PVAB_POWER_GATE_CONTROL_0_SRAM_RET_EN_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PVAB_POWER_GATE_CONTROL_0_SRAM_RET_EN_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PVAB_POWER_GATE_CONTROL_0_SRAM_RET_EN_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PVAB_POWER_GATE_CONTROL_0_SRAM_RET_EN_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PVAB_POWER_GATE_CONTROL_0_SRAM_RET_EN_INIT_ENUM                   OFF
#define PMC_IMPL_PART_PVAB_POWER_GATE_CONTROL_0_SRAM_RET_EN_OFF                 _MK_ENUM_CONST(0)
#define PMC_IMPL_PART_PVAB_POWER_GATE_CONTROL_0_SRAM_RET_EN_ON                  _MK_ENUM_CONST(1)

#define PMC_IMPL_PART_PVAB_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SHIFT                     _MK_SHIFT_CONST(2)
#define PMC_IMPL_PART_PVAB_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_FIELD                     _MK_FIELD_CONST(0x1, PMC_IMPL_PART_PVAB_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SHIFT)
#define PMC_IMPL_PART_PVAB_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_RANGE                     2:2
#define PMC_IMPL_PART_PVAB_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_WOFFSET                   0x0
#define PMC_IMPL_PART_PVAB_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_DEFAULT                   _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PVAB_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PVAB_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PVAB_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PVAB_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PVAB_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PVAB_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_INIT_ENUM                 ON
#define PMC_IMPL_PART_PVAB_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_OFF                       _MK_ENUM_CONST(0)
#define PMC_IMPL_PART_PVAB_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_ON                        _MK_ENUM_CONST(1)

#define PMC_IMPL_PART_PVAB_POWER_GATE_CONTROL_0_START_SHIFT                     _MK_SHIFT_CONST(8)
#define PMC_IMPL_PART_PVAB_POWER_GATE_CONTROL_0_START_FIELD                     _MK_FIELD_CONST(0x1, PMC_IMPL_PART_PVAB_POWER_GATE_CONTROL_0_START_SHIFT)
#define PMC_IMPL_PART_PVAB_POWER_GATE_CONTROL_0_START_RANGE                     8:8
#define PMC_IMPL_PART_PVAB_POWER_GATE_CONTROL_0_START_WOFFSET                   0x0
#define PMC_IMPL_PART_PVAB_POWER_GATE_CONTROL_0_START_DEFAULT                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PVAB_POWER_GATE_CONTROL_0_START_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PVAB_POWER_GATE_CONTROL_0_START_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PVAB_POWER_GATE_CONTROL_0_START_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PVAB_POWER_GATE_CONTROL_0_START_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PVAB_POWER_GATE_CONTROL_0_START_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PVAB_POWER_GATE_CONTROL_0_START_INIT_ENUM                 DONE
#define PMC_IMPL_PART_PVAB_POWER_GATE_CONTROL_0_START_DONE                      _MK_ENUM_CONST(0)
#define PMC_IMPL_PART_PVAB_POWER_GATE_CONTROL_0_START_PENDING                   _MK_ENUM_CONST(1)

#define PMC_IMPL_PART_PVAB_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SHIFT                       _MK_SHIFT_CONST(31)
#define PMC_IMPL_PART_PVAB_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_FIELD                       _MK_FIELD_CONST(0x1, PMC_IMPL_PART_PVAB_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SHIFT)
#define PMC_IMPL_PART_PVAB_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_RANGE                       31:31
#define PMC_IMPL_PART_PVAB_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_WOFFSET                     0x0
#define PMC_IMPL_PART_PVAB_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_DEFAULT                     _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PVAB_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PVAB_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PVAB_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PVAB_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PVAB_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PVAB_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_INIT_ENUM                   ENABLE
#define PMC_IMPL_PART_PVAB_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_DISABLE                     _MK_ENUM_CONST(0)
#define PMC_IMPL_PART_PVAB_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_ENABLE                      _MK_ENUM_CONST(1)


// Register PMC_IMPL_PART_PVAB_POWER_GATE_STATUS_0
#define PMC_IMPL_PART_PVAB_POWER_GATE_STATUS_0                  _MK_ADDR_CONST(0x470)
#define PMC_IMPL_PART_PVAB_POWER_GATE_STATUS_0_SECURE                   0x0
#define PMC_IMPL_PART_PVAB_POWER_GATE_STATUS_0_DUAL                     0x0
#define PMC_IMPL_PART_PVAB_POWER_GATE_STATUS_0_SCR                      PG_PVAB_SCR_0
#define PMC_IMPL_PART_PVAB_POWER_GATE_STATUS_0_WORD_COUNT                       0x1
#define PMC_IMPL_PART_PVAB_POWER_GATE_STATUS_0_RESET_VAL                        _MK_MASK_CONST(0x5)
#define PMC_IMPL_PART_PVAB_POWER_GATE_STATUS_0_RESET_MASK                       _MK_MASK_CONST(0x7)
#define PMC_IMPL_PART_PVAB_POWER_GATE_STATUS_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PVAB_POWER_GATE_STATUS_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PVAB_POWER_GATE_STATUS_0_READ_MASK                        _MK_MASK_CONST(0x7)
#define PMC_IMPL_PART_PVAB_POWER_GATE_STATUS_0_WRITE_MASK                       _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PVAB_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SHIFT                    _MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_PVAB_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_FIELD                    _MK_FIELD_CONST(0x1, PMC_IMPL_PART_PVAB_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SHIFT)
#define PMC_IMPL_PART_PVAB_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_RANGE                    0:0
#define PMC_IMPL_PART_PVAB_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_WOFFSET                  0x0
#define PMC_IMPL_PART_PVAB_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_DEFAULT                  _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PVAB_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PVAB_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PVAB_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PVAB_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PVAB_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PVAB_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_INIT_ENUM                        ON
#define PMC_IMPL_PART_PVAB_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_OFF                      _MK_ENUM_CONST(0)
#define PMC_IMPL_PART_PVAB_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_ON                       _MK_ENUM_CONST(1)

#define PMC_IMPL_PART_PVAB_POWER_GATE_STATUS_0_SRAM_RET_STS_SHIFT                       _MK_SHIFT_CONST(1)
#define PMC_IMPL_PART_PVAB_POWER_GATE_STATUS_0_SRAM_RET_STS_FIELD                       _MK_FIELD_CONST(0x1, PMC_IMPL_PART_PVAB_POWER_GATE_STATUS_0_SRAM_RET_STS_SHIFT)
#define PMC_IMPL_PART_PVAB_POWER_GATE_STATUS_0_SRAM_RET_STS_RANGE                       1:1
#define PMC_IMPL_PART_PVAB_POWER_GATE_STATUS_0_SRAM_RET_STS_WOFFSET                     0x0
#define PMC_IMPL_PART_PVAB_POWER_GATE_STATUS_0_SRAM_RET_STS_DEFAULT                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PVAB_POWER_GATE_STATUS_0_SRAM_RET_STS_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PVAB_POWER_GATE_STATUS_0_SRAM_RET_STS_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PVAB_POWER_GATE_STATUS_0_SRAM_RET_STS_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PVAB_POWER_GATE_STATUS_0_SRAM_RET_STS_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PVAB_POWER_GATE_STATUS_0_SRAM_RET_STS_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PVAB_POWER_GATE_STATUS_0_SRAM_RET_STS_INIT_ENUM                   OFF
#define PMC_IMPL_PART_PVAB_POWER_GATE_STATUS_0_SRAM_RET_STS_OFF                 _MK_ENUM_CONST(0)
#define PMC_IMPL_PART_PVAB_POWER_GATE_STATUS_0_SRAM_RET_STS_ON                  _MK_ENUM_CONST(1)

#define PMC_IMPL_PART_PVAB_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SHIFT                     _MK_SHIFT_CONST(2)
#define PMC_IMPL_PART_PVAB_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_FIELD                     _MK_FIELD_CONST(0x1, PMC_IMPL_PART_PVAB_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SHIFT)
#define PMC_IMPL_PART_PVAB_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_RANGE                     2:2
#define PMC_IMPL_PART_PVAB_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_WOFFSET                   0x0
#define PMC_IMPL_PART_PVAB_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_DEFAULT                   _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PVAB_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PVAB_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PVAB_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PVAB_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PVAB_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PVAB_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_INIT_ENUM                 ON
#define PMC_IMPL_PART_PVAB_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_OFF                       _MK_ENUM_CONST(0)
#define PMC_IMPL_PART_PVAB_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_ON                        _MK_ENUM_CONST(1)


// Register PMC_IMPL_PART_PVAB_CLAMP_CONTROL_0
#define PMC_IMPL_PART_PVAB_CLAMP_CONTROL_0                      _MK_ADDR_CONST(0x474)
#define PMC_IMPL_PART_PVAB_CLAMP_CONTROL_0_SECURE                       0x0
#define PMC_IMPL_PART_PVAB_CLAMP_CONTROL_0_DUAL                         0x0
#define PMC_IMPL_PART_PVAB_CLAMP_CONTROL_0_SCR                  PG_PVAB_SCR_0
#define PMC_IMPL_PART_PVAB_CLAMP_CONTROL_0_WORD_COUNT                   0x1
#define PMC_IMPL_PART_PVAB_CLAMP_CONTROL_0_RESET_VAL                    _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PVAB_CLAMP_CONTROL_0_RESET_MASK                   _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PVAB_CLAMP_CONTROL_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PVAB_CLAMP_CONTROL_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PVAB_CLAMP_CONTROL_0_READ_MASK                    _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PVAB_CLAMP_CONTROL_0_WRITE_MASK                   _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PVAB_CLAMP_CONTROL_0_CLAMP_SHIFT                  _MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_PVAB_CLAMP_CONTROL_0_CLAMP_FIELD                  _MK_FIELD_CONST(0x1, PMC_IMPL_PART_PVAB_CLAMP_CONTROL_0_CLAMP_SHIFT)
#define PMC_IMPL_PART_PVAB_CLAMP_CONTROL_0_CLAMP_RANGE                  0:0
#define PMC_IMPL_PART_PVAB_CLAMP_CONTROL_0_CLAMP_WOFFSET                        0x0
#define PMC_IMPL_PART_PVAB_CLAMP_CONTROL_0_CLAMP_DEFAULT                        _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PVAB_CLAMP_CONTROL_0_CLAMP_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PVAB_CLAMP_CONTROL_0_CLAMP_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PVAB_CLAMP_CONTROL_0_CLAMP_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PVAB_CLAMP_CONTROL_0_CLAMP_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_PVAB_CLAMP_CONTROL_0_CLAMP_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_PVAB_CLAMP_CONTROL_0_CLAMP_INIT_ENUM                      ON
#define PMC_IMPL_PART_PVAB_CLAMP_CONTROL_0_CLAMP_OFF                    _MK_ENUM_CONST(0)
#define PMC_IMPL_PART_PVAB_CLAMP_CONTROL_0_CLAMP_ON                     _MK_ENUM_CONST(1)


// Register PMC_IMPL_PART_DLAA_POWER_GATE_CONTROL_0
#define PMC_IMPL_PART_DLAA_POWER_GATE_CONTROL_0                 _MK_ADDR_CONST(0x478)
#define PMC_IMPL_PART_DLAA_POWER_GATE_CONTROL_0_SECURE                  0x0
#define PMC_IMPL_PART_DLAA_POWER_GATE_CONTROL_0_DUAL                    0x0
#define PMC_IMPL_PART_DLAA_POWER_GATE_CONTROL_0_SCR                     PG_DLAA_SCR_0
#define PMC_IMPL_PART_DLAA_POWER_GATE_CONTROL_0_WORD_COUNT                      0x1
#define PMC_IMPL_PART_DLAA_POWER_GATE_CONTROL_0_RESET_VAL                       _MK_MASK_CONST(0x80000005)
#define PMC_IMPL_PART_DLAA_POWER_GATE_CONTROL_0_RESET_MASK                      _MK_MASK_CONST(0x80000107)
#define PMC_IMPL_PART_DLAA_POWER_GATE_CONTROL_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_DLAA_POWER_GATE_CONTROL_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_DLAA_POWER_GATE_CONTROL_0_READ_MASK                       _MK_MASK_CONST(0x80000107)
#define PMC_IMPL_PART_DLAA_POWER_GATE_CONTROL_0_WRITE_MASK                      _MK_MASK_CONST(0x80000107)
#define PMC_IMPL_PART_DLAA_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SHIFT                       _MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_DLAA_POWER_GATE_CONTROL_0_LOGIC_SLEEP_FIELD                       _MK_FIELD_CONST(0x1, PMC_IMPL_PART_DLAA_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SHIFT)
#define PMC_IMPL_PART_DLAA_POWER_GATE_CONTROL_0_LOGIC_SLEEP_RANGE                       0:0
#define PMC_IMPL_PART_DLAA_POWER_GATE_CONTROL_0_LOGIC_SLEEP_WOFFSET                     0x0
#define PMC_IMPL_PART_DLAA_POWER_GATE_CONTROL_0_LOGIC_SLEEP_DEFAULT                     _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_DLAA_POWER_GATE_CONTROL_0_LOGIC_SLEEP_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_DLAA_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_DLAA_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_DLAA_POWER_GATE_CONTROL_0_LOGIC_SLEEP_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_DLAA_POWER_GATE_CONTROL_0_LOGIC_SLEEP_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_DLAA_POWER_GATE_CONTROL_0_LOGIC_SLEEP_INIT_ENUM                   ON
#define PMC_IMPL_PART_DLAA_POWER_GATE_CONTROL_0_LOGIC_SLEEP_OFF                 _MK_ENUM_CONST(0)
#define PMC_IMPL_PART_DLAA_POWER_GATE_CONTROL_0_LOGIC_SLEEP_ON                  _MK_ENUM_CONST(1)

#define PMC_IMPL_PART_DLAA_POWER_GATE_CONTROL_0_SRAM_RET_EN_SHIFT                       _MK_SHIFT_CONST(1)
#define PMC_IMPL_PART_DLAA_POWER_GATE_CONTROL_0_SRAM_RET_EN_FIELD                       _MK_FIELD_CONST(0x1, PMC_IMPL_PART_DLAA_POWER_GATE_CONTROL_0_SRAM_RET_EN_SHIFT)
#define PMC_IMPL_PART_DLAA_POWER_GATE_CONTROL_0_SRAM_RET_EN_RANGE                       1:1
#define PMC_IMPL_PART_DLAA_POWER_GATE_CONTROL_0_SRAM_RET_EN_WOFFSET                     0x0
#define PMC_IMPL_PART_DLAA_POWER_GATE_CONTROL_0_SRAM_RET_EN_DEFAULT                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_DLAA_POWER_GATE_CONTROL_0_SRAM_RET_EN_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_DLAA_POWER_GATE_CONTROL_0_SRAM_RET_EN_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_DLAA_POWER_GATE_CONTROL_0_SRAM_RET_EN_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_DLAA_POWER_GATE_CONTROL_0_SRAM_RET_EN_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_DLAA_POWER_GATE_CONTROL_0_SRAM_RET_EN_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_DLAA_POWER_GATE_CONTROL_0_SRAM_RET_EN_INIT_ENUM                   OFF
#define PMC_IMPL_PART_DLAA_POWER_GATE_CONTROL_0_SRAM_RET_EN_OFF                 _MK_ENUM_CONST(0)
#define PMC_IMPL_PART_DLAA_POWER_GATE_CONTROL_0_SRAM_RET_EN_ON                  _MK_ENUM_CONST(1)

#define PMC_IMPL_PART_DLAA_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SHIFT                     _MK_SHIFT_CONST(2)
#define PMC_IMPL_PART_DLAA_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_FIELD                     _MK_FIELD_CONST(0x1, PMC_IMPL_PART_DLAA_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SHIFT)
#define PMC_IMPL_PART_DLAA_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_RANGE                     2:2
#define PMC_IMPL_PART_DLAA_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_WOFFSET                   0x0
#define PMC_IMPL_PART_DLAA_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_DEFAULT                   _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_DLAA_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_DLAA_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_DLAA_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_DLAA_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_DLAA_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_DLAA_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_INIT_ENUM                 ON
#define PMC_IMPL_PART_DLAA_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_OFF                       _MK_ENUM_CONST(0)
#define PMC_IMPL_PART_DLAA_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_ON                        _MK_ENUM_CONST(1)

#define PMC_IMPL_PART_DLAA_POWER_GATE_CONTROL_0_START_SHIFT                     _MK_SHIFT_CONST(8)
#define PMC_IMPL_PART_DLAA_POWER_GATE_CONTROL_0_START_FIELD                     _MK_FIELD_CONST(0x1, PMC_IMPL_PART_DLAA_POWER_GATE_CONTROL_0_START_SHIFT)
#define PMC_IMPL_PART_DLAA_POWER_GATE_CONTROL_0_START_RANGE                     8:8
#define PMC_IMPL_PART_DLAA_POWER_GATE_CONTROL_0_START_WOFFSET                   0x0
#define PMC_IMPL_PART_DLAA_POWER_GATE_CONTROL_0_START_DEFAULT                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_DLAA_POWER_GATE_CONTROL_0_START_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_DLAA_POWER_GATE_CONTROL_0_START_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_DLAA_POWER_GATE_CONTROL_0_START_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_DLAA_POWER_GATE_CONTROL_0_START_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_DLAA_POWER_GATE_CONTROL_0_START_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_DLAA_POWER_GATE_CONTROL_0_START_INIT_ENUM                 DONE
#define PMC_IMPL_PART_DLAA_POWER_GATE_CONTROL_0_START_DONE                      _MK_ENUM_CONST(0)
#define PMC_IMPL_PART_DLAA_POWER_GATE_CONTROL_0_START_PENDING                   _MK_ENUM_CONST(1)

#define PMC_IMPL_PART_DLAA_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SHIFT                       _MK_SHIFT_CONST(31)
#define PMC_IMPL_PART_DLAA_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_FIELD                       _MK_FIELD_CONST(0x1, PMC_IMPL_PART_DLAA_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SHIFT)
#define PMC_IMPL_PART_DLAA_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_RANGE                       31:31
#define PMC_IMPL_PART_DLAA_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_WOFFSET                     0x0
#define PMC_IMPL_PART_DLAA_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_DEFAULT                     _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_DLAA_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_DLAA_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_DLAA_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_DLAA_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_DLAA_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_DLAA_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_INIT_ENUM                   ENABLE
#define PMC_IMPL_PART_DLAA_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_DISABLE                     _MK_ENUM_CONST(0)
#define PMC_IMPL_PART_DLAA_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_ENABLE                      _MK_ENUM_CONST(1)


// Register PMC_IMPL_PART_DLAA_POWER_GATE_STATUS_0
#define PMC_IMPL_PART_DLAA_POWER_GATE_STATUS_0                  _MK_ADDR_CONST(0x47c)
#define PMC_IMPL_PART_DLAA_POWER_GATE_STATUS_0_SECURE                   0x0
#define PMC_IMPL_PART_DLAA_POWER_GATE_STATUS_0_DUAL                     0x0
#define PMC_IMPL_PART_DLAA_POWER_GATE_STATUS_0_SCR                      PG_DLAA_SCR_0
#define PMC_IMPL_PART_DLAA_POWER_GATE_STATUS_0_WORD_COUNT                       0x1
#define PMC_IMPL_PART_DLAA_POWER_GATE_STATUS_0_RESET_VAL                        _MK_MASK_CONST(0x5)
#define PMC_IMPL_PART_DLAA_POWER_GATE_STATUS_0_RESET_MASK                       _MK_MASK_CONST(0x7)
#define PMC_IMPL_PART_DLAA_POWER_GATE_STATUS_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_DLAA_POWER_GATE_STATUS_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_DLAA_POWER_GATE_STATUS_0_READ_MASK                        _MK_MASK_CONST(0x7)
#define PMC_IMPL_PART_DLAA_POWER_GATE_STATUS_0_WRITE_MASK                       _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_DLAA_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SHIFT                    _MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_DLAA_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_FIELD                    _MK_FIELD_CONST(0x1, PMC_IMPL_PART_DLAA_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SHIFT)
#define PMC_IMPL_PART_DLAA_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_RANGE                    0:0
#define PMC_IMPL_PART_DLAA_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_WOFFSET                  0x0
#define PMC_IMPL_PART_DLAA_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_DEFAULT                  _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_DLAA_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_DLAA_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_DLAA_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_DLAA_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_DLAA_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_DLAA_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_INIT_ENUM                        ON
#define PMC_IMPL_PART_DLAA_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_OFF                      _MK_ENUM_CONST(0)
#define PMC_IMPL_PART_DLAA_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_ON                       _MK_ENUM_CONST(1)

#define PMC_IMPL_PART_DLAA_POWER_GATE_STATUS_0_SRAM_RET_STS_SHIFT                       _MK_SHIFT_CONST(1)
#define PMC_IMPL_PART_DLAA_POWER_GATE_STATUS_0_SRAM_RET_STS_FIELD                       _MK_FIELD_CONST(0x1, PMC_IMPL_PART_DLAA_POWER_GATE_STATUS_0_SRAM_RET_STS_SHIFT)
#define PMC_IMPL_PART_DLAA_POWER_GATE_STATUS_0_SRAM_RET_STS_RANGE                       1:1
#define PMC_IMPL_PART_DLAA_POWER_GATE_STATUS_0_SRAM_RET_STS_WOFFSET                     0x0
#define PMC_IMPL_PART_DLAA_POWER_GATE_STATUS_0_SRAM_RET_STS_DEFAULT                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_DLAA_POWER_GATE_STATUS_0_SRAM_RET_STS_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_DLAA_POWER_GATE_STATUS_0_SRAM_RET_STS_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_DLAA_POWER_GATE_STATUS_0_SRAM_RET_STS_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_DLAA_POWER_GATE_STATUS_0_SRAM_RET_STS_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_DLAA_POWER_GATE_STATUS_0_SRAM_RET_STS_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_DLAA_POWER_GATE_STATUS_0_SRAM_RET_STS_INIT_ENUM                   OFF
#define PMC_IMPL_PART_DLAA_POWER_GATE_STATUS_0_SRAM_RET_STS_OFF                 _MK_ENUM_CONST(0)
#define PMC_IMPL_PART_DLAA_POWER_GATE_STATUS_0_SRAM_RET_STS_ON                  _MK_ENUM_CONST(1)

#define PMC_IMPL_PART_DLAA_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SHIFT                     _MK_SHIFT_CONST(2)
#define PMC_IMPL_PART_DLAA_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_FIELD                     _MK_FIELD_CONST(0x1, PMC_IMPL_PART_DLAA_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SHIFT)
#define PMC_IMPL_PART_DLAA_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_RANGE                     2:2
#define PMC_IMPL_PART_DLAA_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_WOFFSET                   0x0
#define PMC_IMPL_PART_DLAA_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_DEFAULT                   _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_DLAA_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_DLAA_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_DLAA_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_DLAA_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_DLAA_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_DLAA_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_INIT_ENUM                 ON
#define PMC_IMPL_PART_DLAA_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_OFF                       _MK_ENUM_CONST(0)
#define PMC_IMPL_PART_DLAA_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_ON                        _MK_ENUM_CONST(1)


// Register PMC_IMPL_PART_DLAA_CLAMP_CONTROL_0
#define PMC_IMPL_PART_DLAA_CLAMP_CONTROL_0                      _MK_ADDR_CONST(0x480)
#define PMC_IMPL_PART_DLAA_CLAMP_CONTROL_0_SECURE                       0x0
#define PMC_IMPL_PART_DLAA_CLAMP_CONTROL_0_DUAL                         0x0
#define PMC_IMPL_PART_DLAA_CLAMP_CONTROL_0_SCR                  PG_DLAA_SCR_0
#define PMC_IMPL_PART_DLAA_CLAMP_CONTROL_0_WORD_COUNT                   0x1
#define PMC_IMPL_PART_DLAA_CLAMP_CONTROL_0_RESET_VAL                    _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_DLAA_CLAMP_CONTROL_0_RESET_MASK                   _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_DLAA_CLAMP_CONTROL_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_DLAA_CLAMP_CONTROL_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_DLAA_CLAMP_CONTROL_0_READ_MASK                    _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_DLAA_CLAMP_CONTROL_0_WRITE_MASK                   _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_DLAA_CLAMP_CONTROL_0_CLAMP_SHIFT                  _MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_DLAA_CLAMP_CONTROL_0_CLAMP_FIELD                  _MK_FIELD_CONST(0x1, PMC_IMPL_PART_DLAA_CLAMP_CONTROL_0_CLAMP_SHIFT)
#define PMC_IMPL_PART_DLAA_CLAMP_CONTROL_0_CLAMP_RANGE                  0:0
#define PMC_IMPL_PART_DLAA_CLAMP_CONTROL_0_CLAMP_WOFFSET                        0x0
#define PMC_IMPL_PART_DLAA_CLAMP_CONTROL_0_CLAMP_DEFAULT                        _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_DLAA_CLAMP_CONTROL_0_CLAMP_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_DLAA_CLAMP_CONTROL_0_CLAMP_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_DLAA_CLAMP_CONTROL_0_CLAMP_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_DLAA_CLAMP_CONTROL_0_CLAMP_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_DLAA_CLAMP_CONTROL_0_CLAMP_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_DLAA_CLAMP_CONTROL_0_CLAMP_INIT_ENUM                      ON
#define PMC_IMPL_PART_DLAA_CLAMP_CONTROL_0_CLAMP_OFF                    _MK_ENUM_CONST(0)
#define PMC_IMPL_PART_DLAA_CLAMP_CONTROL_0_CLAMP_ON                     _MK_ENUM_CONST(1)


// Register PMC_IMPL_PART_DLAB_POWER_GATE_CONTROL_0
#define PMC_IMPL_PART_DLAB_POWER_GATE_CONTROL_0                 _MK_ADDR_CONST(0x484)
#define PMC_IMPL_PART_DLAB_POWER_GATE_CONTROL_0_SECURE                  0x0
#define PMC_IMPL_PART_DLAB_POWER_GATE_CONTROL_0_DUAL                    0x0
#define PMC_IMPL_PART_DLAB_POWER_GATE_CONTROL_0_SCR                     PG_DLAB_SCR_0
#define PMC_IMPL_PART_DLAB_POWER_GATE_CONTROL_0_WORD_COUNT                      0x1
#define PMC_IMPL_PART_DLAB_POWER_GATE_CONTROL_0_RESET_VAL                       _MK_MASK_CONST(0x80000005)
#define PMC_IMPL_PART_DLAB_POWER_GATE_CONTROL_0_RESET_MASK                      _MK_MASK_CONST(0x80000107)
#define PMC_IMPL_PART_DLAB_POWER_GATE_CONTROL_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_DLAB_POWER_GATE_CONTROL_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_DLAB_POWER_GATE_CONTROL_0_READ_MASK                       _MK_MASK_CONST(0x80000107)
#define PMC_IMPL_PART_DLAB_POWER_GATE_CONTROL_0_WRITE_MASK                      _MK_MASK_CONST(0x80000107)
#define PMC_IMPL_PART_DLAB_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SHIFT                       _MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_DLAB_POWER_GATE_CONTROL_0_LOGIC_SLEEP_FIELD                       _MK_FIELD_CONST(0x1, PMC_IMPL_PART_DLAB_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SHIFT)
#define PMC_IMPL_PART_DLAB_POWER_GATE_CONTROL_0_LOGIC_SLEEP_RANGE                       0:0
#define PMC_IMPL_PART_DLAB_POWER_GATE_CONTROL_0_LOGIC_SLEEP_WOFFSET                     0x0
#define PMC_IMPL_PART_DLAB_POWER_GATE_CONTROL_0_LOGIC_SLEEP_DEFAULT                     _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_DLAB_POWER_GATE_CONTROL_0_LOGIC_SLEEP_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_DLAB_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_DLAB_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_DLAB_POWER_GATE_CONTROL_0_LOGIC_SLEEP_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_DLAB_POWER_GATE_CONTROL_0_LOGIC_SLEEP_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_DLAB_POWER_GATE_CONTROL_0_LOGIC_SLEEP_INIT_ENUM                   ON
#define PMC_IMPL_PART_DLAB_POWER_GATE_CONTROL_0_LOGIC_SLEEP_OFF                 _MK_ENUM_CONST(0)
#define PMC_IMPL_PART_DLAB_POWER_GATE_CONTROL_0_LOGIC_SLEEP_ON                  _MK_ENUM_CONST(1)

#define PMC_IMPL_PART_DLAB_POWER_GATE_CONTROL_0_SRAM_RET_EN_SHIFT                       _MK_SHIFT_CONST(1)
#define PMC_IMPL_PART_DLAB_POWER_GATE_CONTROL_0_SRAM_RET_EN_FIELD                       _MK_FIELD_CONST(0x1, PMC_IMPL_PART_DLAB_POWER_GATE_CONTROL_0_SRAM_RET_EN_SHIFT)
#define PMC_IMPL_PART_DLAB_POWER_GATE_CONTROL_0_SRAM_RET_EN_RANGE                       1:1
#define PMC_IMPL_PART_DLAB_POWER_GATE_CONTROL_0_SRAM_RET_EN_WOFFSET                     0x0
#define PMC_IMPL_PART_DLAB_POWER_GATE_CONTROL_0_SRAM_RET_EN_DEFAULT                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_DLAB_POWER_GATE_CONTROL_0_SRAM_RET_EN_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_DLAB_POWER_GATE_CONTROL_0_SRAM_RET_EN_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_DLAB_POWER_GATE_CONTROL_0_SRAM_RET_EN_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_DLAB_POWER_GATE_CONTROL_0_SRAM_RET_EN_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_DLAB_POWER_GATE_CONTROL_0_SRAM_RET_EN_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_DLAB_POWER_GATE_CONTROL_0_SRAM_RET_EN_INIT_ENUM                   OFF
#define PMC_IMPL_PART_DLAB_POWER_GATE_CONTROL_0_SRAM_RET_EN_OFF                 _MK_ENUM_CONST(0)
#define PMC_IMPL_PART_DLAB_POWER_GATE_CONTROL_0_SRAM_RET_EN_ON                  _MK_ENUM_CONST(1)

#define PMC_IMPL_PART_DLAB_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SHIFT                     _MK_SHIFT_CONST(2)
#define PMC_IMPL_PART_DLAB_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_FIELD                     _MK_FIELD_CONST(0x1, PMC_IMPL_PART_DLAB_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SHIFT)
#define PMC_IMPL_PART_DLAB_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_RANGE                     2:2
#define PMC_IMPL_PART_DLAB_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_WOFFSET                   0x0
#define PMC_IMPL_PART_DLAB_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_DEFAULT                   _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_DLAB_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_DLAB_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_DLAB_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_DLAB_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_DLAB_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_DLAB_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_INIT_ENUM                 ON
#define PMC_IMPL_PART_DLAB_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_OFF                       _MK_ENUM_CONST(0)
#define PMC_IMPL_PART_DLAB_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_ON                        _MK_ENUM_CONST(1)

#define PMC_IMPL_PART_DLAB_POWER_GATE_CONTROL_0_START_SHIFT                     _MK_SHIFT_CONST(8)
#define PMC_IMPL_PART_DLAB_POWER_GATE_CONTROL_0_START_FIELD                     _MK_FIELD_CONST(0x1, PMC_IMPL_PART_DLAB_POWER_GATE_CONTROL_0_START_SHIFT)
#define PMC_IMPL_PART_DLAB_POWER_GATE_CONTROL_0_START_RANGE                     8:8
#define PMC_IMPL_PART_DLAB_POWER_GATE_CONTROL_0_START_WOFFSET                   0x0
#define PMC_IMPL_PART_DLAB_POWER_GATE_CONTROL_0_START_DEFAULT                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_DLAB_POWER_GATE_CONTROL_0_START_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_DLAB_POWER_GATE_CONTROL_0_START_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_DLAB_POWER_GATE_CONTROL_0_START_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_DLAB_POWER_GATE_CONTROL_0_START_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_DLAB_POWER_GATE_CONTROL_0_START_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_DLAB_POWER_GATE_CONTROL_0_START_INIT_ENUM                 DONE
#define PMC_IMPL_PART_DLAB_POWER_GATE_CONTROL_0_START_DONE                      _MK_ENUM_CONST(0)
#define PMC_IMPL_PART_DLAB_POWER_GATE_CONTROL_0_START_PENDING                   _MK_ENUM_CONST(1)

#define PMC_IMPL_PART_DLAB_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SHIFT                       _MK_SHIFT_CONST(31)
#define PMC_IMPL_PART_DLAB_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_FIELD                       _MK_FIELD_CONST(0x1, PMC_IMPL_PART_DLAB_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SHIFT)
#define PMC_IMPL_PART_DLAB_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_RANGE                       31:31
#define PMC_IMPL_PART_DLAB_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_WOFFSET                     0x0
#define PMC_IMPL_PART_DLAB_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_DEFAULT                     _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_DLAB_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_DLAB_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_DLAB_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_DLAB_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_DLAB_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_DLAB_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_INIT_ENUM                   ENABLE
#define PMC_IMPL_PART_DLAB_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_DISABLE                     _MK_ENUM_CONST(0)
#define PMC_IMPL_PART_DLAB_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_ENABLE                      _MK_ENUM_CONST(1)


// Register PMC_IMPL_PART_DLAB_POWER_GATE_STATUS_0
#define PMC_IMPL_PART_DLAB_POWER_GATE_STATUS_0                  _MK_ADDR_CONST(0x488)
#define PMC_IMPL_PART_DLAB_POWER_GATE_STATUS_0_SECURE                   0x0
#define PMC_IMPL_PART_DLAB_POWER_GATE_STATUS_0_DUAL                     0x0
#define PMC_IMPL_PART_DLAB_POWER_GATE_STATUS_0_SCR                      PG_DLAB_SCR_0
#define PMC_IMPL_PART_DLAB_POWER_GATE_STATUS_0_WORD_COUNT                       0x1
#define PMC_IMPL_PART_DLAB_POWER_GATE_STATUS_0_RESET_VAL                        _MK_MASK_CONST(0x5)
#define PMC_IMPL_PART_DLAB_POWER_GATE_STATUS_0_RESET_MASK                       _MK_MASK_CONST(0x7)
#define PMC_IMPL_PART_DLAB_POWER_GATE_STATUS_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_DLAB_POWER_GATE_STATUS_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_DLAB_POWER_GATE_STATUS_0_READ_MASK                        _MK_MASK_CONST(0x7)
#define PMC_IMPL_PART_DLAB_POWER_GATE_STATUS_0_WRITE_MASK                       _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_DLAB_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SHIFT                    _MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_DLAB_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_FIELD                    _MK_FIELD_CONST(0x1, PMC_IMPL_PART_DLAB_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SHIFT)
#define PMC_IMPL_PART_DLAB_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_RANGE                    0:0
#define PMC_IMPL_PART_DLAB_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_WOFFSET                  0x0
#define PMC_IMPL_PART_DLAB_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_DEFAULT                  _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_DLAB_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_DLAB_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_DLAB_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_DLAB_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_DLAB_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_DLAB_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_INIT_ENUM                        ON
#define PMC_IMPL_PART_DLAB_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_OFF                      _MK_ENUM_CONST(0)
#define PMC_IMPL_PART_DLAB_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_ON                       _MK_ENUM_CONST(1)

#define PMC_IMPL_PART_DLAB_POWER_GATE_STATUS_0_SRAM_RET_STS_SHIFT                       _MK_SHIFT_CONST(1)
#define PMC_IMPL_PART_DLAB_POWER_GATE_STATUS_0_SRAM_RET_STS_FIELD                       _MK_FIELD_CONST(0x1, PMC_IMPL_PART_DLAB_POWER_GATE_STATUS_0_SRAM_RET_STS_SHIFT)
#define PMC_IMPL_PART_DLAB_POWER_GATE_STATUS_0_SRAM_RET_STS_RANGE                       1:1
#define PMC_IMPL_PART_DLAB_POWER_GATE_STATUS_0_SRAM_RET_STS_WOFFSET                     0x0
#define PMC_IMPL_PART_DLAB_POWER_GATE_STATUS_0_SRAM_RET_STS_DEFAULT                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_DLAB_POWER_GATE_STATUS_0_SRAM_RET_STS_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_DLAB_POWER_GATE_STATUS_0_SRAM_RET_STS_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_DLAB_POWER_GATE_STATUS_0_SRAM_RET_STS_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_DLAB_POWER_GATE_STATUS_0_SRAM_RET_STS_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_DLAB_POWER_GATE_STATUS_0_SRAM_RET_STS_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_DLAB_POWER_GATE_STATUS_0_SRAM_RET_STS_INIT_ENUM                   OFF
#define PMC_IMPL_PART_DLAB_POWER_GATE_STATUS_0_SRAM_RET_STS_OFF                 _MK_ENUM_CONST(0)
#define PMC_IMPL_PART_DLAB_POWER_GATE_STATUS_0_SRAM_RET_STS_ON                  _MK_ENUM_CONST(1)

#define PMC_IMPL_PART_DLAB_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SHIFT                     _MK_SHIFT_CONST(2)
#define PMC_IMPL_PART_DLAB_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_FIELD                     _MK_FIELD_CONST(0x1, PMC_IMPL_PART_DLAB_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SHIFT)
#define PMC_IMPL_PART_DLAB_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_RANGE                     2:2
#define PMC_IMPL_PART_DLAB_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_WOFFSET                   0x0
#define PMC_IMPL_PART_DLAB_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_DEFAULT                   _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_DLAB_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_DLAB_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_DLAB_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_DLAB_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_DLAB_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_DLAB_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_INIT_ENUM                 ON
#define PMC_IMPL_PART_DLAB_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_OFF                       _MK_ENUM_CONST(0)
#define PMC_IMPL_PART_DLAB_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_ON                        _MK_ENUM_CONST(1)


// Register PMC_IMPL_PART_DLAB_CLAMP_CONTROL_0
#define PMC_IMPL_PART_DLAB_CLAMP_CONTROL_0                      _MK_ADDR_CONST(0x48c)
#define PMC_IMPL_PART_DLAB_CLAMP_CONTROL_0_SECURE                       0x0
#define PMC_IMPL_PART_DLAB_CLAMP_CONTROL_0_DUAL                         0x0
#define PMC_IMPL_PART_DLAB_CLAMP_CONTROL_0_SCR                  PG_DLAB_SCR_0
#define PMC_IMPL_PART_DLAB_CLAMP_CONTROL_0_WORD_COUNT                   0x1
#define PMC_IMPL_PART_DLAB_CLAMP_CONTROL_0_RESET_VAL                    _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_DLAB_CLAMP_CONTROL_0_RESET_MASK                   _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_DLAB_CLAMP_CONTROL_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_DLAB_CLAMP_CONTROL_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_DLAB_CLAMP_CONTROL_0_READ_MASK                    _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_DLAB_CLAMP_CONTROL_0_WRITE_MASK                   _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_DLAB_CLAMP_CONTROL_0_CLAMP_SHIFT                  _MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_DLAB_CLAMP_CONTROL_0_CLAMP_FIELD                  _MK_FIELD_CONST(0x1, PMC_IMPL_PART_DLAB_CLAMP_CONTROL_0_CLAMP_SHIFT)
#define PMC_IMPL_PART_DLAB_CLAMP_CONTROL_0_CLAMP_RANGE                  0:0
#define PMC_IMPL_PART_DLAB_CLAMP_CONTROL_0_CLAMP_WOFFSET                        0x0
#define PMC_IMPL_PART_DLAB_CLAMP_CONTROL_0_CLAMP_DEFAULT                        _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_DLAB_CLAMP_CONTROL_0_CLAMP_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_DLAB_CLAMP_CONTROL_0_CLAMP_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_DLAB_CLAMP_CONTROL_0_CLAMP_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_DLAB_CLAMP_CONTROL_0_CLAMP_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_DLAB_CLAMP_CONTROL_0_CLAMP_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_DLAB_CLAMP_CONTROL_0_CLAMP_INIT_ENUM                      ON
#define PMC_IMPL_PART_DLAB_CLAMP_CONTROL_0_CLAMP_OFF                    _MK_ENUM_CONST(0)
#define PMC_IMPL_PART_DLAB_CLAMP_CONTROL_0_CLAMP_ON                     _MK_ENUM_CONST(1)


// Register PMC_IMPL_PART_NVENCA_POWER_GATE_CONTROL_0
#define PMC_IMPL_PART_NVENCA_POWER_GATE_CONTROL_0                       _MK_ADDR_CONST(0x490)
#define PMC_IMPL_PART_NVENCA_POWER_GATE_CONTROL_0_SECURE                        0x0
#define PMC_IMPL_PART_NVENCA_POWER_GATE_CONTROL_0_DUAL                  0x0
#define PMC_IMPL_PART_NVENCA_POWER_GATE_CONTROL_0_SCR                   PG_NVENCA_SCR_0
#define PMC_IMPL_PART_NVENCA_POWER_GATE_CONTROL_0_WORD_COUNT                    0x1
#define PMC_IMPL_PART_NVENCA_POWER_GATE_CONTROL_0_RESET_VAL                     _MK_MASK_CONST(0x80000000)
#define PMC_IMPL_PART_NVENCA_POWER_GATE_CONTROL_0_RESET_MASK                    _MK_MASK_CONST(0x80000107)
#define PMC_IMPL_PART_NVENCA_POWER_GATE_CONTROL_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_NVENCA_POWER_GATE_CONTROL_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_NVENCA_POWER_GATE_CONTROL_0_READ_MASK                     _MK_MASK_CONST(0x80000107)
#define PMC_IMPL_PART_NVENCA_POWER_GATE_CONTROL_0_WRITE_MASK                    _MK_MASK_CONST(0x80000107)
#define PMC_IMPL_PART_NVENCA_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SHIFT                     _MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_NVENCA_POWER_GATE_CONTROL_0_LOGIC_SLEEP_FIELD                     _MK_FIELD_CONST(0x1, PMC_IMPL_PART_NVENCA_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SHIFT)
#define PMC_IMPL_PART_NVENCA_POWER_GATE_CONTROL_0_LOGIC_SLEEP_RANGE                     0:0
#define PMC_IMPL_PART_NVENCA_POWER_GATE_CONTROL_0_LOGIC_SLEEP_WOFFSET                   0x0
#define PMC_IMPL_PART_NVENCA_POWER_GATE_CONTROL_0_LOGIC_SLEEP_DEFAULT                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_NVENCA_POWER_GATE_CONTROL_0_LOGIC_SLEEP_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_NVENCA_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_NVENCA_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_NVENCA_POWER_GATE_CONTROL_0_LOGIC_SLEEP_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_NVENCA_POWER_GATE_CONTROL_0_LOGIC_SLEEP_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_NVENCA_POWER_GATE_CONTROL_0_LOGIC_SLEEP_INIT_ENUM                 OFF
#define PMC_IMPL_PART_NVENCA_POWER_GATE_CONTROL_0_LOGIC_SLEEP_OFF                       _MK_ENUM_CONST(0)
#define PMC_IMPL_PART_NVENCA_POWER_GATE_CONTROL_0_LOGIC_SLEEP_ON                        _MK_ENUM_CONST(1)

#define PMC_IMPL_PART_NVENCA_POWER_GATE_CONTROL_0_SRAM_RET_EN_SHIFT                     _MK_SHIFT_CONST(1)
#define PMC_IMPL_PART_NVENCA_POWER_GATE_CONTROL_0_SRAM_RET_EN_FIELD                     _MK_FIELD_CONST(0x1, PMC_IMPL_PART_NVENCA_POWER_GATE_CONTROL_0_SRAM_RET_EN_SHIFT)
#define PMC_IMPL_PART_NVENCA_POWER_GATE_CONTROL_0_SRAM_RET_EN_RANGE                     1:1
#define PMC_IMPL_PART_NVENCA_POWER_GATE_CONTROL_0_SRAM_RET_EN_WOFFSET                   0x0
#define PMC_IMPL_PART_NVENCA_POWER_GATE_CONTROL_0_SRAM_RET_EN_DEFAULT                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_NVENCA_POWER_GATE_CONTROL_0_SRAM_RET_EN_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_NVENCA_POWER_GATE_CONTROL_0_SRAM_RET_EN_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_NVENCA_POWER_GATE_CONTROL_0_SRAM_RET_EN_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_NVENCA_POWER_GATE_CONTROL_0_SRAM_RET_EN_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_NVENCA_POWER_GATE_CONTROL_0_SRAM_RET_EN_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_NVENCA_POWER_GATE_CONTROL_0_SRAM_RET_EN_INIT_ENUM                 OFF
#define PMC_IMPL_PART_NVENCA_POWER_GATE_CONTROL_0_SRAM_RET_EN_OFF                       _MK_ENUM_CONST(0)
#define PMC_IMPL_PART_NVENCA_POWER_GATE_CONTROL_0_SRAM_RET_EN_ON                        _MK_ENUM_CONST(1)

#define PMC_IMPL_PART_NVENCA_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SHIFT                   _MK_SHIFT_CONST(2)
#define PMC_IMPL_PART_NVENCA_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_FIELD                   _MK_FIELD_CONST(0x1, PMC_IMPL_PART_NVENCA_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SHIFT)
#define PMC_IMPL_PART_NVENCA_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_RANGE                   2:2
#define PMC_IMPL_PART_NVENCA_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_WOFFSET                 0x0
#define PMC_IMPL_PART_NVENCA_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_DEFAULT                 _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_NVENCA_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_NVENCA_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_NVENCA_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_NVENCA_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_NVENCA_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_NVENCA_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_INIT_ENUM                       OFF
#define PMC_IMPL_PART_NVENCA_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_OFF                     _MK_ENUM_CONST(0)
#define PMC_IMPL_PART_NVENCA_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_ON                      _MK_ENUM_CONST(1)

#define PMC_IMPL_PART_NVENCA_POWER_GATE_CONTROL_0_START_SHIFT                   _MK_SHIFT_CONST(8)
#define PMC_IMPL_PART_NVENCA_POWER_GATE_CONTROL_0_START_FIELD                   _MK_FIELD_CONST(0x1, PMC_IMPL_PART_NVENCA_POWER_GATE_CONTROL_0_START_SHIFT)
#define PMC_IMPL_PART_NVENCA_POWER_GATE_CONTROL_0_START_RANGE                   8:8
#define PMC_IMPL_PART_NVENCA_POWER_GATE_CONTROL_0_START_WOFFSET                 0x0
#define PMC_IMPL_PART_NVENCA_POWER_GATE_CONTROL_0_START_DEFAULT                 _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_NVENCA_POWER_GATE_CONTROL_0_START_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_NVENCA_POWER_GATE_CONTROL_0_START_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_NVENCA_POWER_GATE_CONTROL_0_START_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_NVENCA_POWER_GATE_CONTROL_0_START_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_NVENCA_POWER_GATE_CONTROL_0_START_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_NVENCA_POWER_GATE_CONTROL_0_START_INIT_ENUM                       DONE
#define PMC_IMPL_PART_NVENCA_POWER_GATE_CONTROL_0_START_DONE                    _MK_ENUM_CONST(0)
#define PMC_IMPL_PART_NVENCA_POWER_GATE_CONTROL_0_START_PENDING                 _MK_ENUM_CONST(1)

#define PMC_IMPL_PART_NVENCA_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SHIFT                     _MK_SHIFT_CONST(31)
#define PMC_IMPL_PART_NVENCA_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_FIELD                     _MK_FIELD_CONST(0x1, PMC_IMPL_PART_NVENCA_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SHIFT)
#define PMC_IMPL_PART_NVENCA_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_RANGE                     31:31
#define PMC_IMPL_PART_NVENCA_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_WOFFSET                   0x0
#define PMC_IMPL_PART_NVENCA_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_DEFAULT                   _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_NVENCA_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_NVENCA_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_NVENCA_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_NVENCA_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_NVENCA_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_NVENCA_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_INIT_ENUM                 ENABLE
#define PMC_IMPL_PART_NVENCA_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_DISABLE                   _MK_ENUM_CONST(0)
#define PMC_IMPL_PART_NVENCA_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_ENABLE                    _MK_ENUM_CONST(1)


// Register PMC_IMPL_PART_NVENCA_POWER_GATE_STATUS_0
#define PMC_IMPL_PART_NVENCA_POWER_GATE_STATUS_0                        _MK_ADDR_CONST(0x494)
#define PMC_IMPL_PART_NVENCA_POWER_GATE_STATUS_0_SECURE                         0x0
#define PMC_IMPL_PART_NVENCA_POWER_GATE_STATUS_0_DUAL                   0x0
#define PMC_IMPL_PART_NVENCA_POWER_GATE_STATUS_0_SCR                    PG_NVENCA_SCR_0
#define PMC_IMPL_PART_NVENCA_POWER_GATE_STATUS_0_WORD_COUNT                     0x1
#define PMC_IMPL_PART_NVENCA_POWER_GATE_STATUS_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_NVENCA_POWER_GATE_STATUS_0_RESET_MASK                     _MK_MASK_CONST(0x7)
#define PMC_IMPL_PART_NVENCA_POWER_GATE_STATUS_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_NVENCA_POWER_GATE_STATUS_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_NVENCA_POWER_GATE_STATUS_0_READ_MASK                      _MK_MASK_CONST(0x7)
#define PMC_IMPL_PART_NVENCA_POWER_GATE_STATUS_0_WRITE_MASK                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_NVENCA_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SHIFT                  _MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_NVENCA_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_FIELD                  _MK_FIELD_CONST(0x1, PMC_IMPL_PART_NVENCA_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SHIFT)
#define PMC_IMPL_PART_NVENCA_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_RANGE                  0:0
#define PMC_IMPL_PART_NVENCA_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_WOFFSET                        0x0
#define PMC_IMPL_PART_NVENCA_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_DEFAULT                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_NVENCA_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_NVENCA_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_NVENCA_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_NVENCA_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_NVENCA_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_NVENCA_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_INIT_ENUM                      OFF
#define PMC_IMPL_PART_NVENCA_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_OFF                    _MK_ENUM_CONST(0)
#define PMC_IMPL_PART_NVENCA_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_ON                     _MK_ENUM_CONST(1)

#define PMC_IMPL_PART_NVENCA_POWER_GATE_STATUS_0_SRAM_RET_STS_SHIFT                     _MK_SHIFT_CONST(1)
#define PMC_IMPL_PART_NVENCA_POWER_GATE_STATUS_0_SRAM_RET_STS_FIELD                     _MK_FIELD_CONST(0x1, PMC_IMPL_PART_NVENCA_POWER_GATE_STATUS_0_SRAM_RET_STS_SHIFT)
#define PMC_IMPL_PART_NVENCA_POWER_GATE_STATUS_0_SRAM_RET_STS_RANGE                     1:1
#define PMC_IMPL_PART_NVENCA_POWER_GATE_STATUS_0_SRAM_RET_STS_WOFFSET                   0x0
#define PMC_IMPL_PART_NVENCA_POWER_GATE_STATUS_0_SRAM_RET_STS_DEFAULT                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_NVENCA_POWER_GATE_STATUS_0_SRAM_RET_STS_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_NVENCA_POWER_GATE_STATUS_0_SRAM_RET_STS_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_NVENCA_POWER_GATE_STATUS_0_SRAM_RET_STS_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_NVENCA_POWER_GATE_STATUS_0_SRAM_RET_STS_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_NVENCA_POWER_GATE_STATUS_0_SRAM_RET_STS_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_NVENCA_POWER_GATE_STATUS_0_SRAM_RET_STS_INIT_ENUM                 OFF
#define PMC_IMPL_PART_NVENCA_POWER_GATE_STATUS_0_SRAM_RET_STS_OFF                       _MK_ENUM_CONST(0)
#define PMC_IMPL_PART_NVENCA_POWER_GATE_STATUS_0_SRAM_RET_STS_ON                        _MK_ENUM_CONST(1)

#define PMC_IMPL_PART_NVENCA_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SHIFT                   _MK_SHIFT_CONST(2)
#define PMC_IMPL_PART_NVENCA_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_FIELD                   _MK_FIELD_CONST(0x1, PMC_IMPL_PART_NVENCA_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SHIFT)
#define PMC_IMPL_PART_NVENCA_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_RANGE                   2:2
#define PMC_IMPL_PART_NVENCA_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_WOFFSET                 0x0
#define PMC_IMPL_PART_NVENCA_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_DEFAULT                 _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_NVENCA_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_NVENCA_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_NVENCA_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_NVENCA_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_NVENCA_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_NVENCA_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_INIT_ENUM                       OFF
#define PMC_IMPL_PART_NVENCA_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_OFF                     _MK_ENUM_CONST(0)
#define PMC_IMPL_PART_NVENCA_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_ON                      _MK_ENUM_CONST(1)


// Register PMC_IMPL_PART_NVENCA_CLAMP_CONTROL_0
#define PMC_IMPL_PART_NVENCA_CLAMP_CONTROL_0                    _MK_ADDR_CONST(0x498)
#define PMC_IMPL_PART_NVENCA_CLAMP_CONTROL_0_SECURE                     0x0
#define PMC_IMPL_PART_NVENCA_CLAMP_CONTROL_0_DUAL                       0x0
#define PMC_IMPL_PART_NVENCA_CLAMP_CONTROL_0_SCR                        PG_NVENCA_SCR_0
#define PMC_IMPL_PART_NVENCA_CLAMP_CONTROL_0_WORD_COUNT                         0x1
#define PMC_IMPL_PART_NVENCA_CLAMP_CONTROL_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_NVENCA_CLAMP_CONTROL_0_RESET_MASK                         _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_NVENCA_CLAMP_CONTROL_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_NVENCA_CLAMP_CONTROL_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_NVENCA_CLAMP_CONTROL_0_READ_MASK                  _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_NVENCA_CLAMP_CONTROL_0_WRITE_MASK                         _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_NVENCA_CLAMP_CONTROL_0_CLAMP_SHIFT                        _MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_NVENCA_CLAMP_CONTROL_0_CLAMP_FIELD                        _MK_FIELD_CONST(0x1, PMC_IMPL_PART_NVENCA_CLAMP_CONTROL_0_CLAMP_SHIFT)
#define PMC_IMPL_PART_NVENCA_CLAMP_CONTROL_0_CLAMP_RANGE                        0:0
#define PMC_IMPL_PART_NVENCA_CLAMP_CONTROL_0_CLAMP_WOFFSET                      0x0
#define PMC_IMPL_PART_NVENCA_CLAMP_CONTROL_0_CLAMP_DEFAULT                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_NVENCA_CLAMP_CONTROL_0_CLAMP_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_NVENCA_CLAMP_CONTROL_0_CLAMP_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_NVENCA_CLAMP_CONTROL_0_CLAMP_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_NVENCA_CLAMP_CONTROL_0_CLAMP_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_NVENCA_CLAMP_CONTROL_0_CLAMP_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_NVENCA_CLAMP_CONTROL_0_CLAMP_INIT_ENUM                    OFF
#define PMC_IMPL_PART_NVENCA_CLAMP_CONTROL_0_CLAMP_OFF                  _MK_ENUM_CONST(0)
#define PMC_IMPL_PART_NVENCA_CLAMP_CONTROL_0_CLAMP_ON                   _MK_ENUM_CONST(1)


// Register PMC_IMPL_PART_NVENCB_POWER_GATE_CONTROL_0
#define PMC_IMPL_PART_NVENCB_POWER_GATE_CONTROL_0                       _MK_ADDR_CONST(0x49c)
#define PMC_IMPL_PART_NVENCB_POWER_GATE_CONTROL_0_SECURE                        0x0
#define PMC_IMPL_PART_NVENCB_POWER_GATE_CONTROL_0_DUAL                  0x0
#define PMC_IMPL_PART_NVENCB_POWER_GATE_CONTROL_0_SCR                   PG_NVENCB_SCR_0
#define PMC_IMPL_PART_NVENCB_POWER_GATE_CONTROL_0_WORD_COUNT                    0x1
#define PMC_IMPL_PART_NVENCB_POWER_GATE_CONTROL_0_RESET_VAL                     _MK_MASK_CONST(0x80000000)
#define PMC_IMPL_PART_NVENCB_POWER_GATE_CONTROL_0_RESET_MASK                    _MK_MASK_CONST(0x80000107)
#define PMC_IMPL_PART_NVENCB_POWER_GATE_CONTROL_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_NVENCB_POWER_GATE_CONTROL_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_NVENCB_POWER_GATE_CONTROL_0_READ_MASK                     _MK_MASK_CONST(0x80000107)
#define PMC_IMPL_PART_NVENCB_POWER_GATE_CONTROL_0_WRITE_MASK                    _MK_MASK_CONST(0x80000107)
#define PMC_IMPL_PART_NVENCB_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SHIFT                     _MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_NVENCB_POWER_GATE_CONTROL_0_LOGIC_SLEEP_FIELD                     _MK_FIELD_CONST(0x1, PMC_IMPL_PART_NVENCB_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SHIFT)
#define PMC_IMPL_PART_NVENCB_POWER_GATE_CONTROL_0_LOGIC_SLEEP_RANGE                     0:0
#define PMC_IMPL_PART_NVENCB_POWER_GATE_CONTROL_0_LOGIC_SLEEP_WOFFSET                   0x0
#define PMC_IMPL_PART_NVENCB_POWER_GATE_CONTROL_0_LOGIC_SLEEP_DEFAULT                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_NVENCB_POWER_GATE_CONTROL_0_LOGIC_SLEEP_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_NVENCB_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_NVENCB_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_NVENCB_POWER_GATE_CONTROL_0_LOGIC_SLEEP_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_NVENCB_POWER_GATE_CONTROL_0_LOGIC_SLEEP_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_NVENCB_POWER_GATE_CONTROL_0_LOGIC_SLEEP_INIT_ENUM                 OFF
#define PMC_IMPL_PART_NVENCB_POWER_GATE_CONTROL_0_LOGIC_SLEEP_OFF                       _MK_ENUM_CONST(0)
#define PMC_IMPL_PART_NVENCB_POWER_GATE_CONTROL_0_LOGIC_SLEEP_ON                        _MK_ENUM_CONST(1)

#define PMC_IMPL_PART_NVENCB_POWER_GATE_CONTROL_0_SRAM_RET_EN_SHIFT                     _MK_SHIFT_CONST(1)
#define PMC_IMPL_PART_NVENCB_POWER_GATE_CONTROL_0_SRAM_RET_EN_FIELD                     _MK_FIELD_CONST(0x1, PMC_IMPL_PART_NVENCB_POWER_GATE_CONTROL_0_SRAM_RET_EN_SHIFT)
#define PMC_IMPL_PART_NVENCB_POWER_GATE_CONTROL_0_SRAM_RET_EN_RANGE                     1:1
#define PMC_IMPL_PART_NVENCB_POWER_GATE_CONTROL_0_SRAM_RET_EN_WOFFSET                   0x0
#define PMC_IMPL_PART_NVENCB_POWER_GATE_CONTROL_0_SRAM_RET_EN_DEFAULT                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_NVENCB_POWER_GATE_CONTROL_0_SRAM_RET_EN_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_NVENCB_POWER_GATE_CONTROL_0_SRAM_RET_EN_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_NVENCB_POWER_GATE_CONTROL_0_SRAM_RET_EN_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_NVENCB_POWER_GATE_CONTROL_0_SRAM_RET_EN_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_NVENCB_POWER_GATE_CONTROL_0_SRAM_RET_EN_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_NVENCB_POWER_GATE_CONTROL_0_SRAM_RET_EN_INIT_ENUM                 OFF
#define PMC_IMPL_PART_NVENCB_POWER_GATE_CONTROL_0_SRAM_RET_EN_OFF                       _MK_ENUM_CONST(0)
#define PMC_IMPL_PART_NVENCB_POWER_GATE_CONTROL_0_SRAM_RET_EN_ON                        _MK_ENUM_CONST(1)

#define PMC_IMPL_PART_NVENCB_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SHIFT                   _MK_SHIFT_CONST(2)
#define PMC_IMPL_PART_NVENCB_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_FIELD                   _MK_FIELD_CONST(0x1, PMC_IMPL_PART_NVENCB_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SHIFT)
#define PMC_IMPL_PART_NVENCB_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_RANGE                   2:2
#define PMC_IMPL_PART_NVENCB_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_WOFFSET                 0x0
#define PMC_IMPL_PART_NVENCB_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_DEFAULT                 _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_NVENCB_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_NVENCB_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_NVENCB_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_NVENCB_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_NVENCB_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_NVENCB_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_INIT_ENUM                       OFF
#define PMC_IMPL_PART_NVENCB_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_OFF                     _MK_ENUM_CONST(0)
#define PMC_IMPL_PART_NVENCB_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_ON                      _MK_ENUM_CONST(1)

#define PMC_IMPL_PART_NVENCB_POWER_GATE_CONTROL_0_START_SHIFT                   _MK_SHIFT_CONST(8)
#define PMC_IMPL_PART_NVENCB_POWER_GATE_CONTROL_0_START_FIELD                   _MK_FIELD_CONST(0x1, PMC_IMPL_PART_NVENCB_POWER_GATE_CONTROL_0_START_SHIFT)
#define PMC_IMPL_PART_NVENCB_POWER_GATE_CONTROL_0_START_RANGE                   8:8
#define PMC_IMPL_PART_NVENCB_POWER_GATE_CONTROL_0_START_WOFFSET                 0x0
#define PMC_IMPL_PART_NVENCB_POWER_GATE_CONTROL_0_START_DEFAULT                 _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_NVENCB_POWER_GATE_CONTROL_0_START_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_NVENCB_POWER_GATE_CONTROL_0_START_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_NVENCB_POWER_GATE_CONTROL_0_START_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_NVENCB_POWER_GATE_CONTROL_0_START_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_NVENCB_POWER_GATE_CONTROL_0_START_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_NVENCB_POWER_GATE_CONTROL_0_START_INIT_ENUM                       DONE
#define PMC_IMPL_PART_NVENCB_POWER_GATE_CONTROL_0_START_DONE                    _MK_ENUM_CONST(0)
#define PMC_IMPL_PART_NVENCB_POWER_GATE_CONTROL_0_START_PENDING                 _MK_ENUM_CONST(1)

#define PMC_IMPL_PART_NVENCB_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SHIFT                     _MK_SHIFT_CONST(31)
#define PMC_IMPL_PART_NVENCB_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_FIELD                     _MK_FIELD_CONST(0x1, PMC_IMPL_PART_NVENCB_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SHIFT)
#define PMC_IMPL_PART_NVENCB_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_RANGE                     31:31
#define PMC_IMPL_PART_NVENCB_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_WOFFSET                   0x0
#define PMC_IMPL_PART_NVENCB_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_DEFAULT                   _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_NVENCB_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_NVENCB_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_NVENCB_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_NVENCB_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_NVENCB_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_NVENCB_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_INIT_ENUM                 ENABLE
#define PMC_IMPL_PART_NVENCB_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_DISABLE                   _MK_ENUM_CONST(0)
#define PMC_IMPL_PART_NVENCB_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_ENABLE                    _MK_ENUM_CONST(1)


// Register PMC_IMPL_PART_NVENCB_POWER_GATE_STATUS_0
#define PMC_IMPL_PART_NVENCB_POWER_GATE_STATUS_0                        _MK_ADDR_CONST(0x4a0)
#define PMC_IMPL_PART_NVENCB_POWER_GATE_STATUS_0_SECURE                         0x0
#define PMC_IMPL_PART_NVENCB_POWER_GATE_STATUS_0_DUAL                   0x0
#define PMC_IMPL_PART_NVENCB_POWER_GATE_STATUS_0_SCR                    PG_NVENCB_SCR_0
#define PMC_IMPL_PART_NVENCB_POWER_GATE_STATUS_0_WORD_COUNT                     0x1
#define PMC_IMPL_PART_NVENCB_POWER_GATE_STATUS_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_NVENCB_POWER_GATE_STATUS_0_RESET_MASK                     _MK_MASK_CONST(0x7)
#define PMC_IMPL_PART_NVENCB_POWER_GATE_STATUS_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_NVENCB_POWER_GATE_STATUS_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_NVENCB_POWER_GATE_STATUS_0_READ_MASK                      _MK_MASK_CONST(0x7)
#define PMC_IMPL_PART_NVENCB_POWER_GATE_STATUS_0_WRITE_MASK                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_NVENCB_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SHIFT                  _MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_NVENCB_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_FIELD                  _MK_FIELD_CONST(0x1, PMC_IMPL_PART_NVENCB_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SHIFT)
#define PMC_IMPL_PART_NVENCB_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_RANGE                  0:0
#define PMC_IMPL_PART_NVENCB_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_WOFFSET                        0x0
#define PMC_IMPL_PART_NVENCB_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_DEFAULT                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_NVENCB_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_NVENCB_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_NVENCB_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_NVENCB_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_NVENCB_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_NVENCB_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_INIT_ENUM                      OFF
#define PMC_IMPL_PART_NVENCB_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_OFF                    _MK_ENUM_CONST(0)
#define PMC_IMPL_PART_NVENCB_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_ON                     _MK_ENUM_CONST(1)

#define PMC_IMPL_PART_NVENCB_POWER_GATE_STATUS_0_SRAM_RET_STS_SHIFT                     _MK_SHIFT_CONST(1)
#define PMC_IMPL_PART_NVENCB_POWER_GATE_STATUS_0_SRAM_RET_STS_FIELD                     _MK_FIELD_CONST(0x1, PMC_IMPL_PART_NVENCB_POWER_GATE_STATUS_0_SRAM_RET_STS_SHIFT)
#define PMC_IMPL_PART_NVENCB_POWER_GATE_STATUS_0_SRAM_RET_STS_RANGE                     1:1
#define PMC_IMPL_PART_NVENCB_POWER_GATE_STATUS_0_SRAM_RET_STS_WOFFSET                   0x0
#define PMC_IMPL_PART_NVENCB_POWER_GATE_STATUS_0_SRAM_RET_STS_DEFAULT                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_NVENCB_POWER_GATE_STATUS_0_SRAM_RET_STS_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_NVENCB_POWER_GATE_STATUS_0_SRAM_RET_STS_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_NVENCB_POWER_GATE_STATUS_0_SRAM_RET_STS_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_NVENCB_POWER_GATE_STATUS_0_SRAM_RET_STS_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_NVENCB_POWER_GATE_STATUS_0_SRAM_RET_STS_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_NVENCB_POWER_GATE_STATUS_0_SRAM_RET_STS_INIT_ENUM                 OFF
#define PMC_IMPL_PART_NVENCB_POWER_GATE_STATUS_0_SRAM_RET_STS_OFF                       _MK_ENUM_CONST(0)
#define PMC_IMPL_PART_NVENCB_POWER_GATE_STATUS_0_SRAM_RET_STS_ON                        _MK_ENUM_CONST(1)

#define PMC_IMPL_PART_NVENCB_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SHIFT                   _MK_SHIFT_CONST(2)
#define PMC_IMPL_PART_NVENCB_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_FIELD                   _MK_FIELD_CONST(0x1, PMC_IMPL_PART_NVENCB_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SHIFT)
#define PMC_IMPL_PART_NVENCB_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_RANGE                   2:2
#define PMC_IMPL_PART_NVENCB_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_WOFFSET                 0x0
#define PMC_IMPL_PART_NVENCB_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_DEFAULT                 _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_NVENCB_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_NVENCB_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_NVENCB_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_NVENCB_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_NVENCB_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_NVENCB_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_INIT_ENUM                       OFF
#define PMC_IMPL_PART_NVENCB_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_OFF                     _MK_ENUM_CONST(0)
#define PMC_IMPL_PART_NVENCB_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_ON                      _MK_ENUM_CONST(1)


// Register PMC_IMPL_PART_NVENCB_CLAMP_CONTROL_0
#define PMC_IMPL_PART_NVENCB_CLAMP_CONTROL_0                    _MK_ADDR_CONST(0x4a4)
#define PMC_IMPL_PART_NVENCB_CLAMP_CONTROL_0_SECURE                     0x0
#define PMC_IMPL_PART_NVENCB_CLAMP_CONTROL_0_DUAL                       0x0
#define PMC_IMPL_PART_NVENCB_CLAMP_CONTROL_0_SCR                        PG_NVENCB_SCR_0
#define PMC_IMPL_PART_NVENCB_CLAMP_CONTROL_0_WORD_COUNT                         0x1
#define PMC_IMPL_PART_NVENCB_CLAMP_CONTROL_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_NVENCB_CLAMP_CONTROL_0_RESET_MASK                         _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_NVENCB_CLAMP_CONTROL_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_NVENCB_CLAMP_CONTROL_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_NVENCB_CLAMP_CONTROL_0_READ_MASK                  _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_NVENCB_CLAMP_CONTROL_0_WRITE_MASK                         _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_NVENCB_CLAMP_CONTROL_0_CLAMP_SHIFT                        _MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_NVENCB_CLAMP_CONTROL_0_CLAMP_FIELD                        _MK_FIELD_CONST(0x1, PMC_IMPL_PART_NVENCB_CLAMP_CONTROL_0_CLAMP_SHIFT)
#define PMC_IMPL_PART_NVENCB_CLAMP_CONTROL_0_CLAMP_RANGE                        0:0
#define PMC_IMPL_PART_NVENCB_CLAMP_CONTROL_0_CLAMP_WOFFSET                      0x0
#define PMC_IMPL_PART_NVENCB_CLAMP_CONTROL_0_CLAMP_DEFAULT                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_NVENCB_CLAMP_CONTROL_0_CLAMP_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_NVENCB_CLAMP_CONTROL_0_CLAMP_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_NVENCB_CLAMP_CONTROL_0_CLAMP_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_NVENCB_CLAMP_CONTROL_0_CLAMP_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_NVENCB_CLAMP_CONTROL_0_CLAMP_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_NVENCB_CLAMP_CONTROL_0_CLAMP_INIT_ENUM                    OFF
#define PMC_IMPL_PART_NVENCB_CLAMP_CONTROL_0_CLAMP_OFF                  _MK_ENUM_CONST(0)
#define PMC_IMPL_PART_NVENCB_CLAMP_CONTROL_0_CLAMP_ON                   _MK_ENUM_CONST(1)


// Register PMC_IMPL_PART_RCE_POWER_GATE_CONTROL_0
#define PMC_IMPL_PART_RCE_POWER_GATE_CONTROL_0                  _MK_ADDR_CONST(0x4a8)
#define PMC_IMPL_PART_RCE_POWER_GATE_CONTROL_0_SECURE                   0x0
#define PMC_IMPL_PART_RCE_POWER_GATE_CONTROL_0_DUAL                     0x0
#define PMC_IMPL_PART_RCE_POWER_GATE_CONTROL_0_SCR                      PG_RCE_SCR_0
#define PMC_IMPL_PART_RCE_POWER_GATE_CONTROL_0_WORD_COUNT                       0x1
#define PMC_IMPL_PART_RCE_POWER_GATE_CONTROL_0_RESET_VAL                        _MK_MASK_CONST(0x80000000)
#define PMC_IMPL_PART_RCE_POWER_GATE_CONTROL_0_RESET_MASK                       _MK_MASK_CONST(0x80000107)
#define PMC_IMPL_PART_RCE_POWER_GATE_CONTROL_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_RCE_POWER_GATE_CONTROL_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_RCE_POWER_GATE_CONTROL_0_READ_MASK                        _MK_MASK_CONST(0x80000107)
#define PMC_IMPL_PART_RCE_POWER_GATE_CONTROL_0_WRITE_MASK                       _MK_MASK_CONST(0x80000107)
#define PMC_IMPL_PART_RCE_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SHIFT                        _MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_RCE_POWER_GATE_CONTROL_0_LOGIC_SLEEP_FIELD                        _MK_FIELD_CONST(0x1, PMC_IMPL_PART_RCE_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SHIFT)
#define PMC_IMPL_PART_RCE_POWER_GATE_CONTROL_0_LOGIC_SLEEP_RANGE                        0:0
#define PMC_IMPL_PART_RCE_POWER_GATE_CONTROL_0_LOGIC_SLEEP_WOFFSET                      0x0
#define PMC_IMPL_PART_RCE_POWER_GATE_CONTROL_0_LOGIC_SLEEP_DEFAULT                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_RCE_POWER_GATE_CONTROL_0_LOGIC_SLEEP_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_RCE_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_RCE_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_RCE_POWER_GATE_CONTROL_0_LOGIC_SLEEP_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_RCE_POWER_GATE_CONTROL_0_LOGIC_SLEEP_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_RCE_POWER_GATE_CONTROL_0_LOGIC_SLEEP_INIT_ENUM                    OFF
#define PMC_IMPL_PART_RCE_POWER_GATE_CONTROL_0_LOGIC_SLEEP_OFF                  _MK_ENUM_CONST(0)
#define PMC_IMPL_PART_RCE_POWER_GATE_CONTROL_0_LOGIC_SLEEP_ON                   _MK_ENUM_CONST(1)

#define PMC_IMPL_PART_RCE_POWER_GATE_CONTROL_0_SRAM_RET_EN_SHIFT                        _MK_SHIFT_CONST(1)
#define PMC_IMPL_PART_RCE_POWER_GATE_CONTROL_0_SRAM_RET_EN_FIELD                        _MK_FIELD_CONST(0x1, PMC_IMPL_PART_RCE_POWER_GATE_CONTROL_0_SRAM_RET_EN_SHIFT)
#define PMC_IMPL_PART_RCE_POWER_GATE_CONTROL_0_SRAM_RET_EN_RANGE                        1:1
#define PMC_IMPL_PART_RCE_POWER_GATE_CONTROL_0_SRAM_RET_EN_WOFFSET                      0x0
#define PMC_IMPL_PART_RCE_POWER_GATE_CONTROL_0_SRAM_RET_EN_DEFAULT                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_RCE_POWER_GATE_CONTROL_0_SRAM_RET_EN_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_RCE_POWER_GATE_CONTROL_0_SRAM_RET_EN_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_RCE_POWER_GATE_CONTROL_0_SRAM_RET_EN_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_RCE_POWER_GATE_CONTROL_0_SRAM_RET_EN_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_RCE_POWER_GATE_CONTROL_0_SRAM_RET_EN_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_RCE_POWER_GATE_CONTROL_0_SRAM_RET_EN_INIT_ENUM                    OFF
#define PMC_IMPL_PART_RCE_POWER_GATE_CONTROL_0_SRAM_RET_EN_OFF                  _MK_ENUM_CONST(0)
#define PMC_IMPL_PART_RCE_POWER_GATE_CONTROL_0_SRAM_RET_EN_ON                   _MK_ENUM_CONST(1)

#define PMC_IMPL_PART_RCE_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SHIFT                      _MK_SHIFT_CONST(2)
#define PMC_IMPL_PART_RCE_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_FIELD                      _MK_FIELD_CONST(0x1, PMC_IMPL_PART_RCE_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SHIFT)
#define PMC_IMPL_PART_RCE_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_RANGE                      2:2
#define PMC_IMPL_PART_RCE_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_WOFFSET                    0x0
#define PMC_IMPL_PART_RCE_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_DEFAULT                    _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_RCE_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_RCE_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_RCE_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_RCE_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_RCE_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_RCE_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_INIT_ENUM                  OFF
#define PMC_IMPL_PART_RCE_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_OFF                        _MK_ENUM_CONST(0)
#define PMC_IMPL_PART_RCE_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_ON                 _MK_ENUM_CONST(1)

#define PMC_IMPL_PART_RCE_POWER_GATE_CONTROL_0_START_SHIFT                      _MK_SHIFT_CONST(8)
#define PMC_IMPL_PART_RCE_POWER_GATE_CONTROL_0_START_FIELD                      _MK_FIELD_CONST(0x1, PMC_IMPL_PART_RCE_POWER_GATE_CONTROL_0_START_SHIFT)
#define PMC_IMPL_PART_RCE_POWER_GATE_CONTROL_0_START_RANGE                      8:8
#define PMC_IMPL_PART_RCE_POWER_GATE_CONTROL_0_START_WOFFSET                    0x0
#define PMC_IMPL_PART_RCE_POWER_GATE_CONTROL_0_START_DEFAULT                    _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_RCE_POWER_GATE_CONTROL_0_START_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_RCE_POWER_GATE_CONTROL_0_START_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_RCE_POWER_GATE_CONTROL_0_START_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_RCE_POWER_GATE_CONTROL_0_START_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_RCE_POWER_GATE_CONTROL_0_START_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_RCE_POWER_GATE_CONTROL_0_START_INIT_ENUM                  DONE
#define PMC_IMPL_PART_RCE_POWER_GATE_CONTROL_0_START_DONE                       _MK_ENUM_CONST(0)
#define PMC_IMPL_PART_RCE_POWER_GATE_CONTROL_0_START_PENDING                    _MK_ENUM_CONST(1)

#define PMC_IMPL_PART_RCE_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SHIFT                        _MK_SHIFT_CONST(31)
#define PMC_IMPL_PART_RCE_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_FIELD                        _MK_FIELD_CONST(0x1, PMC_IMPL_PART_RCE_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SHIFT)
#define PMC_IMPL_PART_RCE_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_RANGE                        31:31
#define PMC_IMPL_PART_RCE_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_WOFFSET                      0x0
#define PMC_IMPL_PART_RCE_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_DEFAULT                      _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_RCE_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_RCE_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_RCE_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_RCE_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_RCE_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_RCE_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_INIT_ENUM                    ENABLE
#define PMC_IMPL_PART_RCE_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_DISABLE                      _MK_ENUM_CONST(0)
#define PMC_IMPL_PART_RCE_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_ENABLE                       _MK_ENUM_CONST(1)


// Register PMC_IMPL_PART_RCE_POWER_GATE_STATUS_0
#define PMC_IMPL_PART_RCE_POWER_GATE_STATUS_0                   _MK_ADDR_CONST(0x4ac)
#define PMC_IMPL_PART_RCE_POWER_GATE_STATUS_0_SECURE                    0x0
#define PMC_IMPL_PART_RCE_POWER_GATE_STATUS_0_DUAL                      0x0
#define PMC_IMPL_PART_RCE_POWER_GATE_STATUS_0_SCR                       PG_RCE_SCR_0
#define PMC_IMPL_PART_RCE_POWER_GATE_STATUS_0_WORD_COUNT                        0x1
#define PMC_IMPL_PART_RCE_POWER_GATE_STATUS_0_RESET_VAL                         _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_RCE_POWER_GATE_STATUS_0_RESET_MASK                        _MK_MASK_CONST(0x7)
#define PMC_IMPL_PART_RCE_POWER_GATE_STATUS_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_RCE_POWER_GATE_STATUS_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_RCE_POWER_GATE_STATUS_0_READ_MASK                         _MK_MASK_CONST(0x7)
#define PMC_IMPL_PART_RCE_POWER_GATE_STATUS_0_WRITE_MASK                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_RCE_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SHIFT                     _MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_RCE_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_FIELD                     _MK_FIELD_CONST(0x1, PMC_IMPL_PART_RCE_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SHIFT)
#define PMC_IMPL_PART_RCE_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_RANGE                     0:0
#define PMC_IMPL_PART_RCE_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_WOFFSET                   0x0
#define PMC_IMPL_PART_RCE_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_DEFAULT                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_RCE_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_RCE_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_RCE_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_RCE_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_RCE_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_RCE_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_INIT_ENUM                 OFF
#define PMC_IMPL_PART_RCE_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_OFF                       _MK_ENUM_CONST(0)
#define PMC_IMPL_PART_RCE_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_ON                        _MK_ENUM_CONST(1)

#define PMC_IMPL_PART_RCE_POWER_GATE_STATUS_0_SRAM_RET_STS_SHIFT                        _MK_SHIFT_CONST(1)
#define PMC_IMPL_PART_RCE_POWER_GATE_STATUS_0_SRAM_RET_STS_FIELD                        _MK_FIELD_CONST(0x1, PMC_IMPL_PART_RCE_POWER_GATE_STATUS_0_SRAM_RET_STS_SHIFT)
#define PMC_IMPL_PART_RCE_POWER_GATE_STATUS_0_SRAM_RET_STS_RANGE                        1:1
#define PMC_IMPL_PART_RCE_POWER_GATE_STATUS_0_SRAM_RET_STS_WOFFSET                      0x0
#define PMC_IMPL_PART_RCE_POWER_GATE_STATUS_0_SRAM_RET_STS_DEFAULT                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_RCE_POWER_GATE_STATUS_0_SRAM_RET_STS_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_RCE_POWER_GATE_STATUS_0_SRAM_RET_STS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_RCE_POWER_GATE_STATUS_0_SRAM_RET_STS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_RCE_POWER_GATE_STATUS_0_SRAM_RET_STS_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_RCE_POWER_GATE_STATUS_0_SRAM_RET_STS_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_RCE_POWER_GATE_STATUS_0_SRAM_RET_STS_INIT_ENUM                    OFF
#define PMC_IMPL_PART_RCE_POWER_GATE_STATUS_0_SRAM_RET_STS_OFF                  _MK_ENUM_CONST(0)
#define PMC_IMPL_PART_RCE_POWER_GATE_STATUS_0_SRAM_RET_STS_ON                   _MK_ENUM_CONST(1)

#define PMC_IMPL_PART_RCE_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SHIFT                      _MK_SHIFT_CONST(2)
#define PMC_IMPL_PART_RCE_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_FIELD                      _MK_FIELD_CONST(0x1, PMC_IMPL_PART_RCE_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SHIFT)
#define PMC_IMPL_PART_RCE_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_RANGE                      2:2
#define PMC_IMPL_PART_RCE_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_WOFFSET                    0x0
#define PMC_IMPL_PART_RCE_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_DEFAULT                    _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_RCE_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_RCE_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_RCE_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_RCE_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_RCE_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_RCE_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_INIT_ENUM                  OFF
#define PMC_IMPL_PART_RCE_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_OFF                        _MK_ENUM_CONST(0)
#define PMC_IMPL_PART_RCE_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_ON                 _MK_ENUM_CONST(1)


// Register PMC_IMPL_PART_RCE_CLAMP_CONTROL_0
#define PMC_IMPL_PART_RCE_CLAMP_CONTROL_0                       _MK_ADDR_CONST(0x4b0)
#define PMC_IMPL_PART_RCE_CLAMP_CONTROL_0_SECURE                        0x0
#define PMC_IMPL_PART_RCE_CLAMP_CONTROL_0_DUAL                  0x0
#define PMC_IMPL_PART_RCE_CLAMP_CONTROL_0_SCR                   PG_RCE_SCR_0
#define PMC_IMPL_PART_RCE_CLAMP_CONTROL_0_WORD_COUNT                    0x1
#define PMC_IMPL_PART_RCE_CLAMP_CONTROL_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_RCE_CLAMP_CONTROL_0_RESET_MASK                    _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_RCE_CLAMP_CONTROL_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_RCE_CLAMP_CONTROL_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_RCE_CLAMP_CONTROL_0_READ_MASK                     _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_RCE_CLAMP_CONTROL_0_WRITE_MASK                    _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_RCE_CLAMP_CONTROL_0_CLAMP_SHIFT                   _MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_RCE_CLAMP_CONTROL_0_CLAMP_FIELD                   _MK_FIELD_CONST(0x1, PMC_IMPL_PART_RCE_CLAMP_CONTROL_0_CLAMP_SHIFT)
#define PMC_IMPL_PART_RCE_CLAMP_CONTROL_0_CLAMP_RANGE                   0:0
#define PMC_IMPL_PART_RCE_CLAMP_CONTROL_0_CLAMP_WOFFSET                 0x0
#define PMC_IMPL_PART_RCE_CLAMP_CONTROL_0_CLAMP_DEFAULT                 _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_RCE_CLAMP_CONTROL_0_CLAMP_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_RCE_CLAMP_CONTROL_0_CLAMP_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_RCE_CLAMP_CONTROL_0_CLAMP_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_RCE_CLAMP_CONTROL_0_CLAMP_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_RCE_CLAMP_CONTROL_0_CLAMP_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_RCE_CLAMP_CONTROL_0_CLAMP_INIT_ENUM                       OFF
#define PMC_IMPL_PART_RCE_CLAMP_CONTROL_0_CLAMP_OFF                     _MK_ENUM_CONST(0)
#define PMC_IMPL_PART_RCE_CLAMP_CONTROL_0_CLAMP_ON                      _MK_ENUM_CONST(1)


// Register PMC_IMPL_PART_NVDECB_POWER_GATE_CONTROL_0
#define PMC_IMPL_PART_NVDECB_POWER_GATE_CONTROL_0                       _MK_ADDR_CONST(0x4b4)
#define PMC_IMPL_PART_NVDECB_POWER_GATE_CONTROL_0_SECURE                        0x0
#define PMC_IMPL_PART_NVDECB_POWER_GATE_CONTROL_0_DUAL                  0x0
#define PMC_IMPL_PART_NVDECB_POWER_GATE_CONTROL_0_SCR                   PG_NVDECB_SCR_0
#define PMC_IMPL_PART_NVDECB_POWER_GATE_CONTROL_0_WORD_COUNT                    0x1
#define PMC_IMPL_PART_NVDECB_POWER_GATE_CONTROL_0_RESET_VAL                     _MK_MASK_CONST(0x80000000)
#define PMC_IMPL_PART_NVDECB_POWER_GATE_CONTROL_0_RESET_MASK                    _MK_MASK_CONST(0x80000107)
#define PMC_IMPL_PART_NVDECB_POWER_GATE_CONTROL_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_NVDECB_POWER_GATE_CONTROL_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_NVDECB_POWER_GATE_CONTROL_0_READ_MASK                     _MK_MASK_CONST(0x80000107)
#define PMC_IMPL_PART_NVDECB_POWER_GATE_CONTROL_0_WRITE_MASK                    _MK_MASK_CONST(0x80000107)
#define PMC_IMPL_PART_NVDECB_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SHIFT                     _MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_NVDECB_POWER_GATE_CONTROL_0_LOGIC_SLEEP_FIELD                     _MK_FIELD_CONST(0x1, PMC_IMPL_PART_NVDECB_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SHIFT)
#define PMC_IMPL_PART_NVDECB_POWER_GATE_CONTROL_0_LOGIC_SLEEP_RANGE                     0:0
#define PMC_IMPL_PART_NVDECB_POWER_GATE_CONTROL_0_LOGIC_SLEEP_WOFFSET                   0x0
#define PMC_IMPL_PART_NVDECB_POWER_GATE_CONTROL_0_LOGIC_SLEEP_DEFAULT                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_NVDECB_POWER_GATE_CONTROL_0_LOGIC_SLEEP_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_NVDECB_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_NVDECB_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_NVDECB_POWER_GATE_CONTROL_0_LOGIC_SLEEP_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_NVDECB_POWER_GATE_CONTROL_0_LOGIC_SLEEP_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_NVDECB_POWER_GATE_CONTROL_0_LOGIC_SLEEP_INIT_ENUM                 OFF
#define PMC_IMPL_PART_NVDECB_POWER_GATE_CONTROL_0_LOGIC_SLEEP_OFF                       _MK_ENUM_CONST(0)
#define PMC_IMPL_PART_NVDECB_POWER_GATE_CONTROL_0_LOGIC_SLEEP_ON                        _MK_ENUM_CONST(1)

#define PMC_IMPL_PART_NVDECB_POWER_GATE_CONTROL_0_SRAM_RET_EN_SHIFT                     _MK_SHIFT_CONST(1)
#define PMC_IMPL_PART_NVDECB_POWER_GATE_CONTROL_0_SRAM_RET_EN_FIELD                     _MK_FIELD_CONST(0x1, PMC_IMPL_PART_NVDECB_POWER_GATE_CONTROL_0_SRAM_RET_EN_SHIFT)
#define PMC_IMPL_PART_NVDECB_POWER_GATE_CONTROL_0_SRAM_RET_EN_RANGE                     1:1
#define PMC_IMPL_PART_NVDECB_POWER_GATE_CONTROL_0_SRAM_RET_EN_WOFFSET                   0x0
#define PMC_IMPL_PART_NVDECB_POWER_GATE_CONTROL_0_SRAM_RET_EN_DEFAULT                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_NVDECB_POWER_GATE_CONTROL_0_SRAM_RET_EN_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_NVDECB_POWER_GATE_CONTROL_0_SRAM_RET_EN_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_NVDECB_POWER_GATE_CONTROL_0_SRAM_RET_EN_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_NVDECB_POWER_GATE_CONTROL_0_SRAM_RET_EN_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_NVDECB_POWER_GATE_CONTROL_0_SRAM_RET_EN_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_NVDECB_POWER_GATE_CONTROL_0_SRAM_RET_EN_INIT_ENUM                 OFF
#define PMC_IMPL_PART_NVDECB_POWER_GATE_CONTROL_0_SRAM_RET_EN_OFF                       _MK_ENUM_CONST(0)
#define PMC_IMPL_PART_NVDECB_POWER_GATE_CONTROL_0_SRAM_RET_EN_ON                        _MK_ENUM_CONST(1)

#define PMC_IMPL_PART_NVDECB_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SHIFT                   _MK_SHIFT_CONST(2)
#define PMC_IMPL_PART_NVDECB_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_FIELD                   _MK_FIELD_CONST(0x1, PMC_IMPL_PART_NVDECB_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SHIFT)
#define PMC_IMPL_PART_NVDECB_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_RANGE                   2:2
#define PMC_IMPL_PART_NVDECB_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_WOFFSET                 0x0
#define PMC_IMPL_PART_NVDECB_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_DEFAULT                 _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_NVDECB_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_NVDECB_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_NVDECB_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_NVDECB_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_NVDECB_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_NVDECB_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_INIT_ENUM                       OFF
#define PMC_IMPL_PART_NVDECB_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_OFF                     _MK_ENUM_CONST(0)
#define PMC_IMPL_PART_NVDECB_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_ON                      _MK_ENUM_CONST(1)

#define PMC_IMPL_PART_NVDECB_POWER_GATE_CONTROL_0_START_SHIFT                   _MK_SHIFT_CONST(8)
#define PMC_IMPL_PART_NVDECB_POWER_GATE_CONTROL_0_START_FIELD                   _MK_FIELD_CONST(0x1, PMC_IMPL_PART_NVDECB_POWER_GATE_CONTROL_0_START_SHIFT)
#define PMC_IMPL_PART_NVDECB_POWER_GATE_CONTROL_0_START_RANGE                   8:8
#define PMC_IMPL_PART_NVDECB_POWER_GATE_CONTROL_0_START_WOFFSET                 0x0
#define PMC_IMPL_PART_NVDECB_POWER_GATE_CONTROL_0_START_DEFAULT                 _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_NVDECB_POWER_GATE_CONTROL_0_START_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_NVDECB_POWER_GATE_CONTROL_0_START_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_NVDECB_POWER_GATE_CONTROL_0_START_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_NVDECB_POWER_GATE_CONTROL_0_START_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_NVDECB_POWER_GATE_CONTROL_0_START_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_NVDECB_POWER_GATE_CONTROL_0_START_INIT_ENUM                       DONE
#define PMC_IMPL_PART_NVDECB_POWER_GATE_CONTROL_0_START_DONE                    _MK_ENUM_CONST(0)
#define PMC_IMPL_PART_NVDECB_POWER_GATE_CONTROL_0_START_PENDING                 _MK_ENUM_CONST(1)

#define PMC_IMPL_PART_NVDECB_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SHIFT                     _MK_SHIFT_CONST(31)
#define PMC_IMPL_PART_NVDECB_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_FIELD                     _MK_FIELD_CONST(0x1, PMC_IMPL_PART_NVDECB_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SHIFT)
#define PMC_IMPL_PART_NVDECB_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_RANGE                     31:31
#define PMC_IMPL_PART_NVDECB_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_WOFFSET                   0x0
#define PMC_IMPL_PART_NVDECB_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_DEFAULT                   _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_NVDECB_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_NVDECB_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_NVDECB_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_NVDECB_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_NVDECB_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_NVDECB_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_INIT_ENUM                 ENABLE
#define PMC_IMPL_PART_NVDECB_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_DISABLE                   _MK_ENUM_CONST(0)
#define PMC_IMPL_PART_NVDECB_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_ENABLE                    _MK_ENUM_CONST(1)


// Register PMC_IMPL_PART_NVDECB_POWER_GATE_STATUS_0
#define PMC_IMPL_PART_NVDECB_POWER_GATE_STATUS_0                        _MK_ADDR_CONST(0x4b8)
#define PMC_IMPL_PART_NVDECB_POWER_GATE_STATUS_0_SECURE                         0x0
#define PMC_IMPL_PART_NVDECB_POWER_GATE_STATUS_0_DUAL                   0x0
#define PMC_IMPL_PART_NVDECB_POWER_GATE_STATUS_0_SCR                    PG_NVDECB_SCR_0
#define PMC_IMPL_PART_NVDECB_POWER_GATE_STATUS_0_WORD_COUNT                     0x1
#define PMC_IMPL_PART_NVDECB_POWER_GATE_STATUS_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_NVDECB_POWER_GATE_STATUS_0_RESET_MASK                     _MK_MASK_CONST(0x7)
#define PMC_IMPL_PART_NVDECB_POWER_GATE_STATUS_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_NVDECB_POWER_GATE_STATUS_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_NVDECB_POWER_GATE_STATUS_0_READ_MASK                      _MK_MASK_CONST(0x7)
#define PMC_IMPL_PART_NVDECB_POWER_GATE_STATUS_0_WRITE_MASK                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_NVDECB_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SHIFT                  _MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_NVDECB_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_FIELD                  _MK_FIELD_CONST(0x1, PMC_IMPL_PART_NVDECB_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SHIFT)
#define PMC_IMPL_PART_NVDECB_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_RANGE                  0:0
#define PMC_IMPL_PART_NVDECB_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_WOFFSET                        0x0
#define PMC_IMPL_PART_NVDECB_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_DEFAULT                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_NVDECB_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_NVDECB_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_NVDECB_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_NVDECB_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_NVDECB_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_NVDECB_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_INIT_ENUM                      OFF
#define PMC_IMPL_PART_NVDECB_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_OFF                    _MK_ENUM_CONST(0)
#define PMC_IMPL_PART_NVDECB_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_ON                     _MK_ENUM_CONST(1)

#define PMC_IMPL_PART_NVDECB_POWER_GATE_STATUS_0_SRAM_RET_STS_SHIFT                     _MK_SHIFT_CONST(1)
#define PMC_IMPL_PART_NVDECB_POWER_GATE_STATUS_0_SRAM_RET_STS_FIELD                     _MK_FIELD_CONST(0x1, PMC_IMPL_PART_NVDECB_POWER_GATE_STATUS_0_SRAM_RET_STS_SHIFT)
#define PMC_IMPL_PART_NVDECB_POWER_GATE_STATUS_0_SRAM_RET_STS_RANGE                     1:1
#define PMC_IMPL_PART_NVDECB_POWER_GATE_STATUS_0_SRAM_RET_STS_WOFFSET                   0x0
#define PMC_IMPL_PART_NVDECB_POWER_GATE_STATUS_0_SRAM_RET_STS_DEFAULT                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_NVDECB_POWER_GATE_STATUS_0_SRAM_RET_STS_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_NVDECB_POWER_GATE_STATUS_0_SRAM_RET_STS_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_NVDECB_POWER_GATE_STATUS_0_SRAM_RET_STS_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_NVDECB_POWER_GATE_STATUS_0_SRAM_RET_STS_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_NVDECB_POWER_GATE_STATUS_0_SRAM_RET_STS_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_NVDECB_POWER_GATE_STATUS_0_SRAM_RET_STS_INIT_ENUM                 OFF
#define PMC_IMPL_PART_NVDECB_POWER_GATE_STATUS_0_SRAM_RET_STS_OFF                       _MK_ENUM_CONST(0)
#define PMC_IMPL_PART_NVDECB_POWER_GATE_STATUS_0_SRAM_RET_STS_ON                        _MK_ENUM_CONST(1)

#define PMC_IMPL_PART_NVDECB_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SHIFT                   _MK_SHIFT_CONST(2)
#define PMC_IMPL_PART_NVDECB_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_FIELD                   _MK_FIELD_CONST(0x1, PMC_IMPL_PART_NVDECB_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SHIFT)
#define PMC_IMPL_PART_NVDECB_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_RANGE                   2:2
#define PMC_IMPL_PART_NVDECB_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_WOFFSET                 0x0
#define PMC_IMPL_PART_NVDECB_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_DEFAULT                 _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_NVDECB_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_NVDECB_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_NVDECB_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_NVDECB_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_NVDECB_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_NVDECB_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_INIT_ENUM                       OFF
#define PMC_IMPL_PART_NVDECB_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_OFF                     _MK_ENUM_CONST(0)
#define PMC_IMPL_PART_NVDECB_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_ON                      _MK_ENUM_CONST(1)


// Register PMC_IMPL_PART_NVDECB_CLAMP_CONTROL_0
#define PMC_IMPL_PART_NVDECB_CLAMP_CONTROL_0                    _MK_ADDR_CONST(0x4bc)
#define PMC_IMPL_PART_NVDECB_CLAMP_CONTROL_0_SECURE                     0x0
#define PMC_IMPL_PART_NVDECB_CLAMP_CONTROL_0_DUAL                       0x0
#define PMC_IMPL_PART_NVDECB_CLAMP_CONTROL_0_SCR                        PG_NVDECB_SCR_0
#define PMC_IMPL_PART_NVDECB_CLAMP_CONTROL_0_WORD_COUNT                         0x1
#define PMC_IMPL_PART_NVDECB_CLAMP_CONTROL_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_NVDECB_CLAMP_CONTROL_0_RESET_MASK                         _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_NVDECB_CLAMP_CONTROL_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_NVDECB_CLAMP_CONTROL_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_NVDECB_CLAMP_CONTROL_0_READ_MASK                  _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_NVDECB_CLAMP_CONTROL_0_WRITE_MASK                         _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_NVDECB_CLAMP_CONTROL_0_CLAMP_SHIFT                        _MK_SHIFT_CONST(0)
#define PMC_IMPL_PART_NVDECB_CLAMP_CONTROL_0_CLAMP_FIELD                        _MK_FIELD_CONST(0x1, PMC_IMPL_PART_NVDECB_CLAMP_CONTROL_0_CLAMP_SHIFT)
#define PMC_IMPL_PART_NVDECB_CLAMP_CONTROL_0_CLAMP_RANGE                        0:0
#define PMC_IMPL_PART_NVDECB_CLAMP_CONTROL_0_CLAMP_WOFFSET                      0x0
#define PMC_IMPL_PART_NVDECB_CLAMP_CONTROL_0_CLAMP_DEFAULT                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_NVDECB_CLAMP_CONTROL_0_CLAMP_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_NVDECB_CLAMP_CONTROL_0_CLAMP_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_NVDECB_CLAMP_CONTROL_0_CLAMP_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_NVDECB_CLAMP_CONTROL_0_CLAMP_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define PMC_IMPL_PART_NVDECB_CLAMP_CONTROL_0_CLAMP_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)
#define PMC_IMPL_PART_NVDECB_CLAMP_CONTROL_0_CLAMP_INIT_ENUM                    OFF
#define PMC_IMPL_PART_NVDECB_CLAMP_CONTROL_0_CLAMP_OFF                  _MK_ENUM_CONST(0)
#define PMC_IMPL_PART_NVDECB_CLAMP_CONTROL_0_CLAMP_ON                   _MK_ENUM_CONST(1)


// Register PMC_IMPL_SW_OVERRIDE_CTRL_1_0
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0                   _MK_ADDR_CONST(0x4c0)
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_SECURE                    0x0
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_DUAL                      0x0
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_SCR                       PG_OVERRIDE_SCR_0
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_WORD_COUNT                        0x1
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_RESET_VAL                         _MK_MASK_CONST(0x0)
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_RESET_MASK                        _MK_MASK_CONST(0xffffffff)
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_READ_MASK                         _MK_MASK_CONST(0xffffffff)
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_WRITE_MASK                        _MK_MASK_CONST(0xffffffff)
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM0_RET_SHIFT                   _MK_SHIFT_CONST(0)
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM0_RET_FIELD                   _MK_FIELD_CONST(0x1, PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM0_RET_SHIFT)
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM0_RET_RANGE                   0:0
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM0_RET_WOFFSET                 0x0
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM0_RET_DEFAULT                 _MK_MASK_CONST(0x0)
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM0_RET_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM0_RET_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM0_RET_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM0_RET_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM0_RET_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM0_RET_INIT_ENUM                       DISABLE
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM0_RET_ENABLE                  _MK_ENUM_CONST(1)
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM0_RET_DISABLE                 _MK_ENUM_CONST(0)

#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM0_SLEEP_SHIFT                 _MK_SHIFT_CONST(1)
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM0_SLEEP_FIELD                 _MK_FIELD_CONST(0x3, PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM0_SLEEP_SHIFT)
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM0_SLEEP_RANGE                 2:1
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM0_SLEEP_WOFFSET                       0x0
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM0_SLEEP_DEFAULT                       _MK_MASK_CONST(0x0)
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM0_SLEEP_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM0_SLEEP_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM0_SLEEP_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM0_SLEEP_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM0_SLEEP_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)

#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_EN_AOPG_TCM0_SHIFT                        _MK_SHIFT_CONST(3)
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_EN_AOPG_TCM0_FIELD                        _MK_FIELD_CONST(0x1, PMC_IMPL_SW_OVERRIDE_CTRL_1_0_EN_AOPG_TCM0_SHIFT)
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_EN_AOPG_TCM0_RANGE                        3:3
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_EN_AOPG_TCM0_WOFFSET                      0x0
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_EN_AOPG_TCM0_DEFAULT                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_EN_AOPG_TCM0_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_EN_AOPG_TCM0_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_EN_AOPG_TCM0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_EN_AOPG_TCM0_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_EN_AOPG_TCM0_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_EN_AOPG_TCM0_INIT_ENUM                    DISABLE
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_EN_AOPG_TCM0_ENABLE                       _MK_ENUM_CONST(1)
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_EN_AOPG_TCM0_DISABLE                      _MK_ENUM_CONST(0)

#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM1_RET_SHIFT                   _MK_SHIFT_CONST(4)
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM1_RET_FIELD                   _MK_FIELD_CONST(0x1, PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM1_RET_SHIFT)
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM1_RET_RANGE                   4:4
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM1_RET_WOFFSET                 0x0
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM1_RET_DEFAULT                 _MK_MASK_CONST(0x0)
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM1_RET_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM1_RET_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM1_RET_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM1_RET_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM1_RET_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM1_RET_INIT_ENUM                       DISABLE
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM1_RET_ENABLE                  _MK_ENUM_CONST(1)
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM1_RET_DISABLE                 _MK_ENUM_CONST(0)

#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM1_SLEEP_SHIFT                 _MK_SHIFT_CONST(5)
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM1_SLEEP_FIELD                 _MK_FIELD_CONST(0x3, PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM1_SLEEP_SHIFT)
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM1_SLEEP_RANGE                 6:5
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM1_SLEEP_WOFFSET                       0x0
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM1_SLEEP_DEFAULT                       _MK_MASK_CONST(0x0)
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM1_SLEEP_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM1_SLEEP_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM1_SLEEP_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM1_SLEEP_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM1_SLEEP_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)

#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_EN_AOPG_TCM1_SHIFT                        _MK_SHIFT_CONST(7)
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_EN_AOPG_TCM1_FIELD                        _MK_FIELD_CONST(0x1, PMC_IMPL_SW_OVERRIDE_CTRL_1_0_EN_AOPG_TCM1_SHIFT)
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_EN_AOPG_TCM1_RANGE                        7:7
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_EN_AOPG_TCM1_WOFFSET                      0x0
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_EN_AOPG_TCM1_DEFAULT                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_EN_AOPG_TCM1_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_EN_AOPG_TCM1_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_EN_AOPG_TCM1_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_EN_AOPG_TCM1_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_EN_AOPG_TCM1_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_EN_AOPG_TCM1_INIT_ENUM                    DISABLE
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_EN_AOPG_TCM1_ENABLE                       _MK_ENUM_CONST(1)
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_EN_AOPG_TCM1_DISABLE                      _MK_ENUM_CONST(0)

#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM2_RET_SHIFT                   _MK_SHIFT_CONST(8)
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM2_RET_FIELD                   _MK_FIELD_CONST(0x1, PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM2_RET_SHIFT)
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM2_RET_RANGE                   8:8
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM2_RET_WOFFSET                 0x0
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM2_RET_DEFAULT                 _MK_MASK_CONST(0x0)
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM2_RET_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM2_RET_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM2_RET_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM2_RET_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM2_RET_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM2_RET_INIT_ENUM                       DISABLE
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM2_RET_ENABLE                  _MK_ENUM_CONST(1)
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM2_RET_DISABLE                 _MK_ENUM_CONST(0)

#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM2_SLEEP_SHIFT                 _MK_SHIFT_CONST(9)
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM2_SLEEP_FIELD                 _MK_FIELD_CONST(0x3, PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM2_SLEEP_SHIFT)
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM2_SLEEP_RANGE                 10:9
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM2_SLEEP_WOFFSET                       0x0
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM2_SLEEP_DEFAULT                       _MK_MASK_CONST(0x0)
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM2_SLEEP_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM2_SLEEP_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM2_SLEEP_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM2_SLEEP_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM2_SLEEP_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)

#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_EN_AOPG_TCM2_SHIFT                        _MK_SHIFT_CONST(11)
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_EN_AOPG_TCM2_FIELD                        _MK_FIELD_CONST(0x1, PMC_IMPL_SW_OVERRIDE_CTRL_1_0_EN_AOPG_TCM2_SHIFT)
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_EN_AOPG_TCM2_RANGE                        11:11
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_EN_AOPG_TCM2_WOFFSET                      0x0
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_EN_AOPG_TCM2_DEFAULT                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_EN_AOPG_TCM2_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_EN_AOPG_TCM2_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_EN_AOPG_TCM2_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_EN_AOPG_TCM2_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_EN_AOPG_TCM2_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_EN_AOPG_TCM2_INIT_ENUM                    DISABLE
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_EN_AOPG_TCM2_ENABLE                       _MK_ENUM_CONST(1)
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_EN_AOPG_TCM2_DISABLE                      _MK_ENUM_CONST(0)

#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM3_RET_SHIFT                   _MK_SHIFT_CONST(12)
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM3_RET_FIELD                   _MK_FIELD_CONST(0x1, PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM3_RET_SHIFT)
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM3_RET_RANGE                   12:12
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM3_RET_WOFFSET                 0x0
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM3_RET_DEFAULT                 _MK_MASK_CONST(0x0)
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM3_RET_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM3_RET_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM3_RET_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM3_RET_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM3_RET_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM3_RET_INIT_ENUM                       DISABLE
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM3_RET_ENABLE                  _MK_ENUM_CONST(1)
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM3_RET_DISABLE                 _MK_ENUM_CONST(0)

#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM3_SLEEP_SHIFT                 _MK_SHIFT_CONST(13)
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM3_SLEEP_FIELD                 _MK_FIELD_CONST(0x3, PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM3_SLEEP_SHIFT)
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM3_SLEEP_RANGE                 14:13
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM3_SLEEP_WOFFSET                       0x0
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM3_SLEEP_DEFAULT                       _MK_MASK_CONST(0x0)
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM3_SLEEP_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM3_SLEEP_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM3_SLEEP_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM3_SLEEP_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM3_SLEEP_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)

#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_EN_AOPG_TCM3_SHIFT                        _MK_SHIFT_CONST(15)
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_EN_AOPG_TCM3_FIELD                        _MK_FIELD_CONST(0x1, PMC_IMPL_SW_OVERRIDE_CTRL_1_0_EN_AOPG_TCM3_SHIFT)
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_EN_AOPG_TCM3_RANGE                        15:15
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_EN_AOPG_TCM3_WOFFSET                      0x0
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_EN_AOPG_TCM3_DEFAULT                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_EN_AOPG_TCM3_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_EN_AOPG_TCM3_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_EN_AOPG_TCM3_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_EN_AOPG_TCM3_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_EN_AOPG_TCM3_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_EN_AOPG_TCM3_INIT_ENUM                    DISABLE
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_EN_AOPG_TCM3_ENABLE                       _MK_ENUM_CONST(1)
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_EN_AOPG_TCM3_DISABLE                      _MK_ENUM_CONST(0)

#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM4_RET_SHIFT                   _MK_SHIFT_CONST(16)
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM4_RET_FIELD                   _MK_FIELD_CONST(0x1, PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM4_RET_SHIFT)
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM4_RET_RANGE                   16:16
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM4_RET_WOFFSET                 0x0
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM4_RET_DEFAULT                 _MK_MASK_CONST(0x0)
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM4_RET_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM4_RET_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM4_RET_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM4_RET_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM4_RET_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM4_RET_INIT_ENUM                       DISABLE
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM4_RET_ENABLE                  _MK_ENUM_CONST(1)
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM4_RET_DISABLE                 _MK_ENUM_CONST(0)

#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM4_SLEEP_SHIFT                 _MK_SHIFT_CONST(17)
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM4_SLEEP_FIELD                 _MK_FIELD_CONST(0x3, PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM4_SLEEP_SHIFT)
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM4_SLEEP_RANGE                 18:17
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM4_SLEEP_WOFFSET                       0x0
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM4_SLEEP_DEFAULT                       _MK_MASK_CONST(0x0)
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM4_SLEEP_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM4_SLEEP_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM4_SLEEP_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM4_SLEEP_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM4_SLEEP_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)

#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_EN_AOPG_TCM4_SHIFT                        _MK_SHIFT_CONST(19)
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_EN_AOPG_TCM4_FIELD                        _MK_FIELD_CONST(0x1, PMC_IMPL_SW_OVERRIDE_CTRL_1_0_EN_AOPG_TCM4_SHIFT)
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_EN_AOPG_TCM4_RANGE                        19:19
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_EN_AOPG_TCM4_WOFFSET                      0x0
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_EN_AOPG_TCM4_DEFAULT                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_EN_AOPG_TCM4_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_EN_AOPG_TCM4_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_EN_AOPG_TCM4_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_EN_AOPG_TCM4_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_EN_AOPG_TCM4_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_EN_AOPG_TCM4_INIT_ENUM                    DISABLE
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_EN_AOPG_TCM4_ENABLE                       _MK_ENUM_CONST(1)
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_EN_AOPG_TCM4_DISABLE                      _MK_ENUM_CONST(0)

#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM5_RET_SHIFT                   _MK_SHIFT_CONST(20)
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM5_RET_FIELD                   _MK_FIELD_CONST(0x1, PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM5_RET_SHIFT)
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM5_RET_RANGE                   20:20
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM5_RET_WOFFSET                 0x0
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM5_RET_DEFAULT                 _MK_MASK_CONST(0x0)
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM5_RET_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM5_RET_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM5_RET_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM5_RET_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM5_RET_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM5_RET_INIT_ENUM                       DISABLE
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM5_RET_ENABLE                  _MK_ENUM_CONST(1)
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM5_RET_DISABLE                 _MK_ENUM_CONST(0)

#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM5_SLEEP_SHIFT                 _MK_SHIFT_CONST(21)
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM5_SLEEP_FIELD                 _MK_FIELD_CONST(0x3, PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM5_SLEEP_SHIFT)
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM5_SLEEP_RANGE                 22:21
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM5_SLEEP_WOFFSET                       0x0
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM5_SLEEP_DEFAULT                       _MK_MASK_CONST(0x0)
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM5_SLEEP_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM5_SLEEP_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM5_SLEEP_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM5_SLEEP_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM5_SLEEP_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)

#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_EN_AOPG_TCM5_SHIFT                        _MK_SHIFT_CONST(23)
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_EN_AOPG_TCM5_FIELD                        _MK_FIELD_CONST(0x1, PMC_IMPL_SW_OVERRIDE_CTRL_1_0_EN_AOPG_TCM5_SHIFT)
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_EN_AOPG_TCM5_RANGE                        23:23
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_EN_AOPG_TCM5_WOFFSET                      0x0
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_EN_AOPG_TCM5_DEFAULT                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_EN_AOPG_TCM5_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_EN_AOPG_TCM5_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_EN_AOPG_TCM5_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_EN_AOPG_TCM5_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_EN_AOPG_TCM5_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_EN_AOPG_TCM5_INIT_ENUM                    DISABLE
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_EN_AOPG_TCM5_ENABLE                       _MK_ENUM_CONST(1)
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_EN_AOPG_TCM5_DISABLE                      _MK_ENUM_CONST(0)

#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM6_RET_SHIFT                   _MK_SHIFT_CONST(24)
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM6_RET_FIELD                   _MK_FIELD_CONST(0x1, PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM6_RET_SHIFT)
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM6_RET_RANGE                   24:24
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM6_RET_WOFFSET                 0x0
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM6_RET_DEFAULT                 _MK_MASK_CONST(0x0)
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM6_RET_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM6_RET_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM6_RET_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM6_RET_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM6_RET_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM6_RET_INIT_ENUM                       DISABLE
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM6_RET_ENABLE                  _MK_ENUM_CONST(1)
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM6_RET_DISABLE                 _MK_ENUM_CONST(0)

#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM6_SLEEP_SHIFT                 _MK_SHIFT_CONST(25)
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM6_SLEEP_FIELD                 _MK_FIELD_CONST(0x3, PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM6_SLEEP_SHIFT)
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM6_SLEEP_RANGE                 26:25
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM6_SLEEP_WOFFSET                       0x0
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM6_SLEEP_DEFAULT                       _MK_MASK_CONST(0x0)
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM6_SLEEP_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM6_SLEEP_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM6_SLEEP_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM6_SLEEP_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM6_SLEEP_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)

#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_EN_AOPG_TCM6_SHIFT                        _MK_SHIFT_CONST(27)
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_EN_AOPG_TCM6_FIELD                        _MK_FIELD_CONST(0x1, PMC_IMPL_SW_OVERRIDE_CTRL_1_0_EN_AOPG_TCM6_SHIFT)
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_EN_AOPG_TCM6_RANGE                        27:27
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_EN_AOPG_TCM6_WOFFSET                      0x0
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_EN_AOPG_TCM6_DEFAULT                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_EN_AOPG_TCM6_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_EN_AOPG_TCM6_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_EN_AOPG_TCM6_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_EN_AOPG_TCM6_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_EN_AOPG_TCM6_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_EN_AOPG_TCM6_INIT_ENUM                    DISABLE
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_EN_AOPG_TCM6_ENABLE                       _MK_ENUM_CONST(1)
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_EN_AOPG_TCM6_DISABLE                      _MK_ENUM_CONST(0)

#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM7_RET_SHIFT                   _MK_SHIFT_CONST(28)
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM7_RET_FIELD                   _MK_FIELD_CONST(0x1, PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM7_RET_SHIFT)
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM7_RET_RANGE                   28:28
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM7_RET_WOFFSET                 0x0
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM7_RET_DEFAULT                 _MK_MASK_CONST(0x0)
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM7_RET_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM7_RET_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM7_RET_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM7_RET_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM7_RET_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM7_RET_INIT_ENUM                       DISABLE
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM7_RET_ENABLE                  _MK_ENUM_CONST(1)
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM7_RET_DISABLE                 _MK_ENUM_CONST(0)

#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM7_SLEEP_SHIFT                 _MK_SHIFT_CONST(29)
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM7_SLEEP_FIELD                 _MK_FIELD_CONST(0x3, PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM7_SLEEP_SHIFT)
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM7_SLEEP_RANGE                 30:29
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM7_SLEEP_WOFFSET                       0x0
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM7_SLEEP_DEFAULT                       _MK_MASK_CONST(0x0)
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM7_SLEEP_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM7_SLEEP_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM7_SLEEP_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM7_SLEEP_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM7_SLEEP_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)

#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_EN_AOPG_TCM7_SHIFT                        _MK_SHIFT_CONST(31)
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_EN_AOPG_TCM7_FIELD                        _MK_FIELD_CONST(0x1, PMC_IMPL_SW_OVERRIDE_CTRL_1_0_EN_AOPG_TCM7_SHIFT)
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_EN_AOPG_TCM7_RANGE                        31:31
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_EN_AOPG_TCM7_WOFFSET                      0x0
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_EN_AOPG_TCM7_DEFAULT                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_EN_AOPG_TCM7_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_EN_AOPG_TCM7_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_EN_AOPG_TCM7_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_EN_AOPG_TCM7_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_EN_AOPG_TCM7_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_EN_AOPG_TCM7_INIT_ENUM                    DISABLE
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_EN_AOPG_TCM7_ENABLE                       _MK_ENUM_CONST(1)
#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_EN_AOPG_TCM7_DISABLE                      _MK_ENUM_CONST(0)


// Register PMC_IMPL_SW_OVERRIDE_CTRL_2_0
#define PMC_IMPL_SW_OVERRIDE_CTRL_2_0                   _MK_ADDR_CONST(0x4c4)
#define PMC_IMPL_SW_OVERRIDE_CTRL_2_0_SECURE                    0x0
#define PMC_IMPL_SW_OVERRIDE_CTRL_2_0_DUAL                      0x0
#define PMC_IMPL_SW_OVERRIDE_CTRL_2_0_SCR                       PG_OVERRIDE_SCR_0
#define PMC_IMPL_SW_OVERRIDE_CTRL_2_0_WORD_COUNT                        0x1
#define PMC_IMPL_SW_OVERRIDE_CTRL_2_0_RESET_VAL                         _MK_MASK_CONST(0x0)
#define PMC_IMPL_SW_OVERRIDE_CTRL_2_0_RESET_MASK                        _MK_MASK_CONST(0x1fffff)
#define PMC_IMPL_SW_OVERRIDE_CTRL_2_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define PMC_IMPL_SW_OVERRIDE_CTRL_2_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_SW_OVERRIDE_CTRL_2_0_READ_MASK                         _MK_MASK_CONST(0x1fffff)
#define PMC_IMPL_SW_OVERRIDE_CTRL_2_0_WRITE_MASK                        _MK_MASK_CONST(0x1fffff)
#define PMC_IMPL_SW_OVERRIDE_CTRL_2_0_VAL_AOPG_CACHE_RET_SHIFT                  _MK_SHIFT_CONST(0)
#define PMC_IMPL_SW_OVERRIDE_CTRL_2_0_VAL_AOPG_CACHE_RET_FIELD                  _MK_FIELD_CONST(0x1, PMC_IMPL_SW_OVERRIDE_CTRL_2_0_VAL_AOPG_CACHE_RET_SHIFT)
#define PMC_IMPL_SW_OVERRIDE_CTRL_2_0_VAL_AOPG_CACHE_RET_RANGE                  0:0
#define PMC_IMPL_SW_OVERRIDE_CTRL_2_0_VAL_AOPG_CACHE_RET_WOFFSET                        0x0
#define PMC_IMPL_SW_OVERRIDE_CTRL_2_0_VAL_AOPG_CACHE_RET_DEFAULT                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_SW_OVERRIDE_CTRL_2_0_VAL_AOPG_CACHE_RET_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define PMC_IMPL_SW_OVERRIDE_CTRL_2_0_VAL_AOPG_CACHE_RET_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_SW_OVERRIDE_CTRL_2_0_VAL_AOPG_CACHE_RET_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_SW_OVERRIDE_CTRL_2_0_VAL_AOPG_CACHE_RET_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_SW_OVERRIDE_CTRL_2_0_VAL_AOPG_CACHE_RET_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define PMC_IMPL_SW_OVERRIDE_CTRL_2_0_VAL_AOPG_CACHE_RET_INIT_ENUM                      DISABLE
#define PMC_IMPL_SW_OVERRIDE_CTRL_2_0_VAL_AOPG_CACHE_RET_ENABLE                 _MK_ENUM_CONST(1)
#define PMC_IMPL_SW_OVERRIDE_CTRL_2_0_VAL_AOPG_CACHE_RET_DISABLE                        _MK_ENUM_CONST(0)

#define PMC_IMPL_SW_OVERRIDE_CTRL_2_0_VAL_AOPG_CACHE_SLEEP_SHIFT                        _MK_SHIFT_CONST(1)
#define PMC_IMPL_SW_OVERRIDE_CTRL_2_0_VAL_AOPG_CACHE_SLEEP_FIELD                        _MK_FIELD_CONST(0x3, PMC_IMPL_SW_OVERRIDE_CTRL_2_0_VAL_AOPG_CACHE_SLEEP_SHIFT)
#define PMC_IMPL_SW_OVERRIDE_CTRL_2_0_VAL_AOPG_CACHE_SLEEP_RANGE                        2:1
#define PMC_IMPL_SW_OVERRIDE_CTRL_2_0_VAL_AOPG_CACHE_SLEEP_WOFFSET                      0x0
#define PMC_IMPL_SW_OVERRIDE_CTRL_2_0_VAL_AOPG_CACHE_SLEEP_DEFAULT                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_SW_OVERRIDE_CTRL_2_0_VAL_AOPG_CACHE_SLEEP_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define PMC_IMPL_SW_OVERRIDE_CTRL_2_0_VAL_AOPG_CACHE_SLEEP_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_SW_OVERRIDE_CTRL_2_0_VAL_AOPG_CACHE_SLEEP_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_SW_OVERRIDE_CTRL_2_0_VAL_AOPG_CACHE_SLEEP_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define PMC_IMPL_SW_OVERRIDE_CTRL_2_0_VAL_AOPG_CACHE_SLEEP_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define PMC_IMPL_SW_OVERRIDE_CTRL_2_0_EN_AOPG_CACHE_SHIFT                       _MK_SHIFT_CONST(3)
#define PMC_IMPL_SW_OVERRIDE_CTRL_2_0_EN_AOPG_CACHE_FIELD                       _MK_FIELD_CONST(0x1, PMC_IMPL_SW_OVERRIDE_CTRL_2_0_EN_AOPG_CACHE_SHIFT)
#define PMC_IMPL_SW_OVERRIDE_CTRL_2_0_EN_AOPG_CACHE_RANGE                       3:3
#define PMC_IMPL_SW_OVERRIDE_CTRL_2_0_EN_AOPG_CACHE_WOFFSET                     0x0
#define PMC_IMPL_SW_OVERRIDE_CTRL_2_0_EN_AOPG_CACHE_DEFAULT                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_SW_OVERRIDE_CTRL_2_0_EN_AOPG_CACHE_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define PMC_IMPL_SW_OVERRIDE_CTRL_2_0_EN_AOPG_CACHE_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define PMC_IMPL_SW_OVERRIDE_CTRL_2_0_EN_AOPG_CACHE_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_SW_OVERRIDE_CTRL_2_0_EN_AOPG_CACHE_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_SW_OVERRIDE_CTRL_2_0_EN_AOPG_CACHE_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define PMC_IMPL_SW_OVERRIDE_CTRL_2_0_EN_AOPG_CACHE_INIT_ENUM                   DISABLE
#define PMC_IMPL_SW_OVERRIDE_CTRL_2_0_EN_AOPG_CACHE_ENABLE                      _MK_ENUM_CONST(1)
#define PMC_IMPL_SW_OVERRIDE_CTRL_2_0_EN_AOPG_CACHE_DISABLE                     _MK_ENUM_CONST(0)

#define PMC_IMPL_SW_OVERRIDE_CTRL_2_0_VAL_AOPG_CAN0_RET_SHIFT                   _MK_SHIFT_CONST(4)
#define PMC_IMPL_SW_OVERRIDE_CTRL_2_0_VAL_AOPG_CAN0_RET_FIELD                   _MK_FIELD_CONST(0x1, PMC_IMPL_SW_OVERRIDE_CTRL_2_0_VAL_AOPG_CAN0_RET_SHIFT)
#define PMC_IMPL_SW_OVERRIDE_CTRL_2_0_VAL_AOPG_CAN0_RET_RANGE                   4:4
#define PMC_IMPL_SW_OVERRIDE_CTRL_2_0_VAL_AOPG_CAN0_RET_WOFFSET                 0x0
#define PMC_IMPL_SW_OVERRIDE_CTRL_2_0_VAL_AOPG_CAN0_RET_DEFAULT                 _MK_MASK_CONST(0x0)
#define PMC_IMPL_SW_OVERRIDE_CTRL_2_0_VAL_AOPG_CAN0_RET_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define PMC_IMPL_SW_OVERRIDE_CTRL_2_0_VAL_AOPG_CAN0_RET_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_SW_OVERRIDE_CTRL_2_0_VAL_AOPG_CAN0_RET_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define PMC_IMPL_SW_OVERRIDE_CTRL_2_0_VAL_AOPG_CAN0_RET_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define PMC_IMPL_SW_OVERRIDE_CTRL_2_0_VAL_AOPG_CAN0_RET_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define PMC_IMPL_SW_OVERRIDE_CTRL_2_0_VAL_AOPG_CAN0_RET_INIT_ENUM                       DISABLE
#define PMC_IMPL_SW_OVERRIDE_CTRL_2_0_VAL_AOPG_CAN0_RET_ENABLE                  _MK_ENUM_CONST(1)
#define PMC_IMPL_SW_OVERRIDE_CTRL_2_0_VAL_AOPG_CAN0_RET_DISABLE                 _MK_ENUM_CONST(0)

#define PMC_IMPL_SW_OVERRIDE_CTRL_2_0_VAL_AOPG_CAN0_SLEEP_SHIFT                 _MK_SHIFT_CONST(5)
#define PMC_IMPL_SW_OVERRIDE_CTRL_2_0_VAL_AOPG_CAN0_SLEEP_FIELD                 _MK_FIELD_CONST(0x3, PMC_IMPL_SW_OVERRIDE_CTRL_2_0_VAL_AOPG_CAN0_SLEEP_SHIFT)
#define PMC_IMPL_SW_OVERRIDE_CTRL_2_0_VAL_AOPG_CAN0_SLEEP_RANGE                 6:5
#define PMC_IMPL_SW_OVERRIDE_CTRL_2_0_VAL_AOPG_CAN0_SLEEP_WOFFSET                       0x0
#define PMC_IMPL_SW_OVERRIDE_CTRL_2_0_VAL_AOPG_CAN0_SLEEP_DEFAULT                       _MK_MASK_CONST(0x0)
#define PMC_IMPL_SW_OVERRIDE_CTRL_2_0_VAL_AOPG_CAN0_SLEEP_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
#define PMC_IMPL_SW_OVERRIDE_CTRL_2_0_VAL_AOPG_CAN0_SLEEP_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define PMC_IMPL_SW_OVERRIDE_CTRL_2_0_VAL_AOPG_CAN0_SLEEP_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define PMC_IMPL_SW_OVERRIDE_CTRL_2_0_VAL_AOPG_CAN0_SLEEP_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_SW_OVERRIDE_CTRL_2_0_VAL_AOPG_CAN0_SLEEP_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)

#define PMC_IMPL_SW_OVERRIDE_CTRL_2_0_EN_AOPG_CAN0_SHIFT                        _MK_SHIFT_CONST(7)
#define PMC_IMPL_SW_OVERRIDE_CTRL_2_0_EN_AOPG_CAN0_FIELD                        _MK_FIELD_CONST(0x1, PMC_IMPL_SW_OVERRIDE_CTRL_2_0_EN_AOPG_CAN0_SHIFT)
#define PMC_IMPL_SW_OVERRIDE_CTRL_2_0_EN_AOPG_CAN0_RANGE                        7:7
#define PMC_IMPL_SW_OVERRIDE_CTRL_2_0_EN_AOPG_CAN0_WOFFSET                      0x0
#define PMC_IMPL_SW_OVERRIDE_CTRL_2_0_EN_AOPG_CAN0_DEFAULT                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_SW_OVERRIDE_CTRL_2_0_EN_AOPG_CAN0_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define PMC_IMPL_SW_OVERRIDE_CTRL_2_0_EN_AOPG_CAN0_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_SW_OVERRIDE_CTRL_2_0_EN_AOPG_CAN0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_SW_OVERRIDE_CTRL_2_0_EN_AOPG_CAN0_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define PMC_IMPL_SW_OVERRIDE_CTRL_2_0_EN_AOPG_CAN0_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)
#define PMC_IMPL_SW_OVERRIDE_CTRL_2_0_EN_AOPG_CAN0_INIT_ENUM                    DISABLE
#define PMC_IMPL_SW_OVERRIDE_CTRL_2_0_EN_AOPG_CAN0_ENABLE                       _MK_ENUM_CONST(1)
#define PMC_IMPL_SW_OVERRIDE_CTRL_2_0_EN_AOPG_CAN0_DISABLE                      _MK_ENUM_CONST(0)

#define PMC_IMPL_SW_OVERRIDE_CTRL_2_0_VAL_AOPG_CAN1_RET_SHIFT                   _MK_SHIFT_CONST(8)
#define PMC_IMPL_SW_OVERRIDE_CTRL_2_0_VAL_AOPG_CAN1_RET_FIELD                   _MK_FIELD_CONST(0x1, PMC_IMPL_SW_OVERRIDE_CTRL_2_0_VAL_AOPG_CAN1_RET_SHIFT)
#define PMC_IMPL_SW_OVERRIDE_CTRL_2_0_VAL_AOPG_CAN1_RET_RANGE                   8:8
#define PMC_IMPL_SW_OVERRIDE_CTRL_2_0_VAL_AOPG_CAN1_RET_WOFFSET                 0x0
#define PMC_IMPL_SW_OVERRIDE_CTRL_2_0_VAL_AOPG_CAN1_RET_DEFAULT                 _MK_MASK_CONST(0x0)
#define PMC_IMPL_SW_OVERRIDE_CTRL_2_0_VAL_AOPG_CAN1_RET_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define PMC_IMPL_SW_OVERRIDE_CTRL_2_0_VAL_AOPG_CAN1_RET_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_SW_OVERRIDE_CTRL_2_0_VAL_AOPG_CAN1_RET_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define PMC_IMPL_SW_OVERRIDE_CTRL_2_0_VAL_AOPG_CAN1_RET_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define PMC_IMPL_SW_OVERRIDE_CTRL_2_0_VAL_AOPG_CAN1_RET_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define PMC_IMPL_SW_OVERRIDE_CTRL_2_0_VAL_AOPG_CAN1_RET_INIT_ENUM                       DISABLE
#define PMC_IMPL_SW_OVERRIDE_CTRL_2_0_VAL_AOPG_CAN1_RET_ENABLE                  _MK_ENUM_CONST(1)
#define PMC_IMPL_SW_OVERRIDE_CTRL_2_0_VAL_AOPG_CAN1_RET_DISABLE                 _MK_ENUM_CONST(0)

#define PMC_IMPL_SW_OVERRIDE_CTRL_2_0_VAL_AOPG_CAN1_SLEEP_SHIFT                 _MK_SHIFT_CONST(9)
#define PMC_IMPL_SW_OVERRIDE_CTRL_2_0_VAL_AOPG_CAN1_SLEEP_FIELD                 _MK_FIELD_CONST(0x3, PMC_IMPL_SW_OVERRIDE_CTRL_2_0_VAL_AOPG_CAN1_SLEEP_SHIFT)
#define PMC_IMPL_SW_OVERRIDE_CTRL_2_0_VAL_AOPG_CAN1_SLEEP_RANGE                 10:9
#define PMC_IMPL_SW_OVERRIDE_CTRL_2_0_VAL_AOPG_CAN1_SLEEP_WOFFSET                       0x0
#define PMC_IMPL_SW_OVERRIDE_CTRL_2_0_VAL_AOPG_CAN1_SLEEP_DEFAULT                       _MK_MASK_CONST(0x0)
#define PMC_IMPL_SW_OVERRIDE_CTRL_2_0_VAL_AOPG_CAN1_SLEEP_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
#define PMC_IMPL_SW_OVERRIDE_CTRL_2_0_VAL_AOPG_CAN1_SLEEP_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define PMC_IMPL_SW_OVERRIDE_CTRL_2_0_VAL_AOPG_CAN1_SLEEP_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define PMC_IMPL_SW_OVERRIDE_CTRL_2_0_VAL_AOPG_CAN1_SLEEP_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_SW_OVERRIDE_CTRL_2_0_VAL_AOPG_CAN1_SLEEP_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)

#define PMC_IMPL_SW_OVERRIDE_CTRL_2_0_EN_AOPG_CAN1_SHIFT                        _MK_SHIFT_CONST(11)
#define PMC_IMPL_SW_OVERRIDE_CTRL_2_0_EN_AOPG_CAN1_FIELD                        _MK_FIELD_CONST(0x1, PMC_IMPL_SW_OVERRIDE_CTRL_2_0_EN_AOPG_CAN1_SHIFT)
#define PMC_IMPL_SW_OVERRIDE_CTRL_2_0_EN_AOPG_CAN1_RANGE                        11:11
#define PMC_IMPL_SW_OVERRIDE_CTRL_2_0_EN_AOPG_CAN1_WOFFSET                      0x0
#define PMC_IMPL_SW_OVERRIDE_CTRL_2_0_EN_AOPG_CAN1_DEFAULT                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_SW_OVERRIDE_CTRL_2_0_EN_AOPG_CAN1_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define PMC_IMPL_SW_OVERRIDE_CTRL_2_0_EN_AOPG_CAN1_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_SW_OVERRIDE_CTRL_2_0_EN_AOPG_CAN1_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_SW_OVERRIDE_CTRL_2_0_EN_AOPG_CAN1_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define PMC_IMPL_SW_OVERRIDE_CTRL_2_0_EN_AOPG_CAN1_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)
#define PMC_IMPL_SW_OVERRIDE_CTRL_2_0_EN_AOPG_CAN1_INIT_ENUM                    DISABLE
#define PMC_IMPL_SW_OVERRIDE_CTRL_2_0_EN_AOPG_CAN1_ENABLE                       _MK_ENUM_CONST(1)
#define PMC_IMPL_SW_OVERRIDE_CTRL_2_0_EN_AOPG_CAN1_DISABLE                      _MK_ENUM_CONST(0)

#define PMC_IMPL_SW_OVERRIDE_CTRL_2_0_VAL_COMMON_ZONE_SHIFT                     _MK_SHIFT_CONST(12)
#define PMC_IMPL_SW_OVERRIDE_CTRL_2_0_VAL_COMMON_ZONE_FIELD                     _MK_FIELD_CONST(0xff, PMC_IMPL_SW_OVERRIDE_CTRL_2_0_VAL_COMMON_ZONE_SHIFT)
#define PMC_IMPL_SW_OVERRIDE_CTRL_2_0_VAL_COMMON_ZONE_RANGE                     19:12
#define PMC_IMPL_SW_OVERRIDE_CTRL_2_0_VAL_COMMON_ZONE_WOFFSET                   0x0
#define PMC_IMPL_SW_OVERRIDE_CTRL_2_0_VAL_COMMON_ZONE_DEFAULT                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_SW_OVERRIDE_CTRL_2_0_VAL_COMMON_ZONE_DEFAULT_MASK                      _MK_MASK_CONST(0xff)
#define PMC_IMPL_SW_OVERRIDE_CTRL_2_0_VAL_COMMON_ZONE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_SW_OVERRIDE_CTRL_2_0_VAL_COMMON_ZONE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_SW_OVERRIDE_CTRL_2_0_VAL_COMMON_ZONE_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define PMC_IMPL_SW_OVERRIDE_CTRL_2_0_VAL_COMMON_ZONE_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)

#define PMC_IMPL_SW_OVERRIDE_CTRL_2_0_EN_COMMON_ZONE_SHIFT                      _MK_SHIFT_CONST(20)
#define PMC_IMPL_SW_OVERRIDE_CTRL_2_0_EN_COMMON_ZONE_FIELD                      _MK_FIELD_CONST(0x1, PMC_IMPL_SW_OVERRIDE_CTRL_2_0_EN_COMMON_ZONE_SHIFT)
#define PMC_IMPL_SW_OVERRIDE_CTRL_2_0_EN_COMMON_ZONE_RANGE                      20:20
#define PMC_IMPL_SW_OVERRIDE_CTRL_2_0_EN_COMMON_ZONE_WOFFSET                    0x0
#define PMC_IMPL_SW_OVERRIDE_CTRL_2_0_EN_COMMON_ZONE_DEFAULT                    _MK_MASK_CONST(0x0)
#define PMC_IMPL_SW_OVERRIDE_CTRL_2_0_EN_COMMON_ZONE_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define PMC_IMPL_SW_OVERRIDE_CTRL_2_0_EN_COMMON_ZONE_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define PMC_IMPL_SW_OVERRIDE_CTRL_2_0_EN_COMMON_ZONE_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define PMC_IMPL_SW_OVERRIDE_CTRL_2_0_EN_COMMON_ZONE_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define PMC_IMPL_SW_OVERRIDE_CTRL_2_0_EN_COMMON_ZONE_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define PMC_IMPL_SW_OVERRIDE_CTRL_2_0_EN_COMMON_ZONE_INIT_ENUM                  DISABLE
#define PMC_IMPL_SW_OVERRIDE_CTRL_2_0_EN_COMMON_ZONE_ENABLE                     _MK_ENUM_CONST(1)
#define PMC_IMPL_SW_OVERRIDE_CTRL_2_0_EN_COMMON_ZONE_DISABLE                    _MK_ENUM_CONST(0)


// Register PMC_IMPL_MISC_CTRL_0
#define PMC_IMPL_MISC_CTRL_0                    _MK_ADDR_CONST(0x4c8)
#define PMC_IMPL_MISC_CTRL_0_SECURE                     0x0
#define PMC_IMPL_MISC_CTRL_0_DUAL                       0x0
#define PMC_IMPL_MISC_CTRL_0_SCR                        PG_MISC_SCR_0
#define PMC_IMPL_MISC_CTRL_0_WORD_COUNT                         0x1
#define PMC_IMPL_MISC_CTRL_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define PMC_IMPL_MISC_CTRL_0_RESET_MASK                         _MK_MASK_CONST(0x1)
#define PMC_IMPL_MISC_CTRL_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_MISC_CTRL_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define PMC_IMPL_MISC_CTRL_0_READ_MASK                  _MK_MASK_CONST(0x1)
#define PMC_IMPL_MISC_CTRL_0_WRITE_MASK                         _MK_MASK_CONST(0x1)
#define PMC_IMPL_MISC_CTRL_0_HW_AOPG_ALLRAMS_SHIFT                      _MK_SHIFT_CONST(0)
#define PMC_IMPL_MISC_CTRL_0_HW_AOPG_ALLRAMS_FIELD                      _MK_FIELD_CONST(0x1, PMC_IMPL_MISC_CTRL_0_HW_AOPG_ALLRAMS_SHIFT)
#define PMC_IMPL_MISC_CTRL_0_HW_AOPG_ALLRAMS_RANGE                      0:0
#define PMC_IMPL_MISC_CTRL_0_HW_AOPG_ALLRAMS_WOFFSET                    0x0
#define PMC_IMPL_MISC_CTRL_0_HW_AOPG_ALLRAMS_DEFAULT                    _MK_MASK_CONST(0x0)
#define PMC_IMPL_MISC_CTRL_0_HW_AOPG_ALLRAMS_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define PMC_IMPL_MISC_CTRL_0_HW_AOPG_ALLRAMS_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define PMC_IMPL_MISC_CTRL_0_HW_AOPG_ALLRAMS_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define PMC_IMPL_MISC_CTRL_0_HW_AOPG_ALLRAMS_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define PMC_IMPL_MISC_CTRL_0_HW_AOPG_ALLRAMS_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define PMC_IMPL_MISC_CTRL_0_HW_AOPG_ALLRAMS_INIT_ENUM                  DISABLE
#define PMC_IMPL_MISC_CTRL_0_HW_AOPG_ALLRAMS_ENABLE                     _MK_ENUM_CONST(1)
#define PMC_IMPL_MISC_CTRL_0_HW_AOPG_ALLRAMS_DISABLE                    _MK_ENUM_CONST(0)


// Register PMC_IMPL_PMC2LIC_INTR_STATUS_0
#define PMC_IMPL_PMC2LIC_INTR_STATUS_0                  _MK_ADDR_CONST(0x800)
#define PMC_IMPL_PMC2LIC_INTR_STATUS_0_SECURE                   0x0
#define PMC_IMPL_PMC2LIC_INTR_STATUS_0_DUAL                     0x0
#define PMC_IMPL_PMC2LIC_INTR_STATUS_0_SCR                      CNTRL_SCR_0
#define PMC_IMPL_PMC2LIC_INTR_STATUS_0_WORD_COUNT                       0x1
#define PMC_IMPL_PMC2LIC_INTR_STATUS_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_PMC2LIC_INTR_STATUS_0_RESET_MASK                       _MK_MASK_CONST(0x3)
#define PMC_IMPL_PMC2LIC_INTR_STATUS_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_PMC2LIC_INTR_STATUS_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define PMC_IMPL_PMC2LIC_INTR_STATUS_0_READ_MASK                        _MK_MASK_CONST(0x3)
#define PMC_IMPL_PMC2LIC_INTR_STATUS_0_WRITE_MASK                       _MK_MASK_CONST(0x3)
#define PMC_IMPL_PMC2LIC_INTR_STATUS_0_ILLEGAL_SRAM_LOGIC_POWER_STATE_SHIFT                     _MK_SHIFT_CONST(1)
#define PMC_IMPL_PMC2LIC_INTR_STATUS_0_ILLEGAL_SRAM_LOGIC_POWER_STATE_FIELD                     _MK_FIELD_CONST(0x1, PMC_IMPL_PMC2LIC_INTR_STATUS_0_ILLEGAL_SRAM_LOGIC_POWER_STATE_SHIFT)
#define PMC_IMPL_PMC2LIC_INTR_STATUS_0_ILLEGAL_SRAM_LOGIC_POWER_STATE_RANGE                     1:1
#define PMC_IMPL_PMC2LIC_INTR_STATUS_0_ILLEGAL_SRAM_LOGIC_POWER_STATE_WOFFSET                   0x0
#define PMC_IMPL_PMC2LIC_INTR_STATUS_0_ILLEGAL_SRAM_LOGIC_POWER_STATE_DEFAULT                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_PMC2LIC_INTR_STATUS_0_ILLEGAL_SRAM_LOGIC_POWER_STATE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define PMC_IMPL_PMC2LIC_INTR_STATUS_0_ILLEGAL_SRAM_LOGIC_POWER_STATE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_PMC2LIC_INTR_STATUS_0_ILLEGAL_SRAM_LOGIC_POWER_STATE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_PMC2LIC_INTR_STATUS_0_ILLEGAL_SRAM_LOGIC_POWER_STATE_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define PMC_IMPL_PMC2LIC_INTR_STATUS_0_ILLEGAL_SRAM_LOGIC_POWER_STATE_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)

#define PMC_IMPL_PMC2LIC_INTR_STATUS_0_UNSUPPORTED_PG_REQUEST_SHIFT                     _MK_SHIFT_CONST(0)
#define PMC_IMPL_PMC2LIC_INTR_STATUS_0_UNSUPPORTED_PG_REQUEST_FIELD                     _MK_FIELD_CONST(0x1, PMC_IMPL_PMC2LIC_INTR_STATUS_0_UNSUPPORTED_PG_REQUEST_SHIFT)
#define PMC_IMPL_PMC2LIC_INTR_STATUS_0_UNSUPPORTED_PG_REQUEST_RANGE                     0:0
#define PMC_IMPL_PMC2LIC_INTR_STATUS_0_UNSUPPORTED_PG_REQUEST_WOFFSET                   0x0
#define PMC_IMPL_PMC2LIC_INTR_STATUS_0_UNSUPPORTED_PG_REQUEST_DEFAULT                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_PMC2LIC_INTR_STATUS_0_UNSUPPORTED_PG_REQUEST_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define PMC_IMPL_PMC2LIC_INTR_STATUS_0_UNSUPPORTED_PG_REQUEST_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_PMC2LIC_INTR_STATUS_0_UNSUPPORTED_PG_REQUEST_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_PMC2LIC_INTR_STATUS_0_UNSUPPORTED_PG_REQUEST_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define PMC_IMPL_PMC2LIC_INTR_STATUS_0_UNSUPPORTED_PG_REQUEST_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)


// Register PMC_IMPL_PMC2LIC_INTR_ENABLE_0
#define PMC_IMPL_PMC2LIC_INTR_ENABLE_0                  _MK_ADDR_CONST(0x804)
#define PMC_IMPL_PMC2LIC_INTR_ENABLE_0_SECURE                   0x0
#define PMC_IMPL_PMC2LIC_INTR_ENABLE_0_DUAL                     0x0
#define PMC_IMPL_PMC2LIC_INTR_ENABLE_0_SCR                      CNTRL_SCR_0
#define PMC_IMPL_PMC2LIC_INTR_ENABLE_0_WORD_COUNT                       0x1
#define PMC_IMPL_PMC2LIC_INTR_ENABLE_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_PMC2LIC_INTR_ENABLE_0_RESET_MASK                       _MK_MASK_CONST(0x3)
#define PMC_IMPL_PMC2LIC_INTR_ENABLE_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_PMC2LIC_INTR_ENABLE_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define PMC_IMPL_PMC2LIC_INTR_ENABLE_0_READ_MASK                        _MK_MASK_CONST(0x3)
#define PMC_IMPL_PMC2LIC_INTR_ENABLE_0_WRITE_MASK                       _MK_MASK_CONST(0x3)
#define PMC_IMPL_PMC2LIC_INTR_ENABLE_0_ILLEGAL_SRAM_LOGIC_POWER_STATE_SHIFT                     _MK_SHIFT_CONST(1)
#define PMC_IMPL_PMC2LIC_INTR_ENABLE_0_ILLEGAL_SRAM_LOGIC_POWER_STATE_FIELD                     _MK_FIELD_CONST(0x1, PMC_IMPL_PMC2LIC_INTR_ENABLE_0_ILLEGAL_SRAM_LOGIC_POWER_STATE_SHIFT)
#define PMC_IMPL_PMC2LIC_INTR_ENABLE_0_ILLEGAL_SRAM_LOGIC_POWER_STATE_RANGE                     1:1
#define PMC_IMPL_PMC2LIC_INTR_ENABLE_0_ILLEGAL_SRAM_LOGIC_POWER_STATE_WOFFSET                   0x0
#define PMC_IMPL_PMC2LIC_INTR_ENABLE_0_ILLEGAL_SRAM_LOGIC_POWER_STATE_DEFAULT                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_PMC2LIC_INTR_ENABLE_0_ILLEGAL_SRAM_LOGIC_POWER_STATE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define PMC_IMPL_PMC2LIC_INTR_ENABLE_0_ILLEGAL_SRAM_LOGIC_POWER_STATE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_PMC2LIC_INTR_ENABLE_0_ILLEGAL_SRAM_LOGIC_POWER_STATE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_PMC2LIC_INTR_ENABLE_0_ILLEGAL_SRAM_LOGIC_POWER_STATE_PARITY_PROTECTION                 _MK_MASK_CONST(0x1)
#define PMC_IMPL_PMC2LIC_INTR_ENABLE_0_ILLEGAL_SRAM_LOGIC_POWER_STATE_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define PMC_IMPL_PMC2LIC_INTR_ENABLE_0_ILLEGAL_SRAM_LOGIC_POWER_STATE_INIT_ENUM                 DISABLE
#define PMC_IMPL_PMC2LIC_INTR_ENABLE_0_ILLEGAL_SRAM_LOGIC_POWER_STATE_DISABLE                   _MK_ENUM_CONST(0)
#define PMC_IMPL_PMC2LIC_INTR_ENABLE_0_ILLEGAL_SRAM_LOGIC_POWER_STATE_ENABLE                    _MK_ENUM_CONST(1)

#define PMC_IMPL_PMC2LIC_INTR_ENABLE_0_UNSUPPORTED_PG_REQUEST_SHIFT                     _MK_SHIFT_CONST(0)
#define PMC_IMPL_PMC2LIC_INTR_ENABLE_0_UNSUPPORTED_PG_REQUEST_FIELD                     _MK_FIELD_CONST(0x1, PMC_IMPL_PMC2LIC_INTR_ENABLE_0_UNSUPPORTED_PG_REQUEST_SHIFT)
#define PMC_IMPL_PMC2LIC_INTR_ENABLE_0_UNSUPPORTED_PG_REQUEST_RANGE                     0:0
#define PMC_IMPL_PMC2LIC_INTR_ENABLE_0_UNSUPPORTED_PG_REQUEST_WOFFSET                   0x0
#define PMC_IMPL_PMC2LIC_INTR_ENABLE_0_UNSUPPORTED_PG_REQUEST_DEFAULT                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_PMC2LIC_INTR_ENABLE_0_UNSUPPORTED_PG_REQUEST_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define PMC_IMPL_PMC2LIC_INTR_ENABLE_0_UNSUPPORTED_PG_REQUEST_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_PMC2LIC_INTR_ENABLE_0_UNSUPPORTED_PG_REQUEST_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_PMC2LIC_INTR_ENABLE_0_UNSUPPORTED_PG_REQUEST_PARITY_PROTECTION                 _MK_MASK_CONST(0x1)
#define PMC_IMPL_PMC2LIC_INTR_ENABLE_0_UNSUPPORTED_PG_REQUEST_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define PMC_IMPL_PMC2LIC_INTR_ENABLE_0_UNSUPPORTED_PG_REQUEST_INIT_ENUM                 DISABLE
#define PMC_IMPL_PMC2LIC_INTR_ENABLE_0_UNSUPPORTED_PG_REQUEST_DISABLE                   _MK_ENUM_CONST(0)
#define PMC_IMPL_PMC2LIC_INTR_ENABLE_0_UNSUPPORTED_PG_REQUEST_ENABLE                    _MK_ENUM_CONST(1)


// Register PMC_IMPL_AOVC_LOCK_CNTRL_0
#define PMC_IMPL_AOVC_LOCK_CNTRL_0                      _MK_ADDR_CONST(0x808)
#define PMC_IMPL_AOVC_LOCK_CNTRL_0_SECURE                       0x0
#define PMC_IMPL_AOVC_LOCK_CNTRL_0_DUAL                         0x0
#define PMC_IMPL_AOVC_LOCK_CNTRL_0_SCR                  AOVC_LOCK_SCR_0
#define PMC_IMPL_AOVC_LOCK_CNTRL_0_WORD_COUNT                   0x1
#define PMC_IMPL_AOVC_LOCK_CNTRL_0_RESET_VAL                    _MK_MASK_CONST(0x0)
#define PMC_IMPL_AOVC_LOCK_CNTRL_0_RESET_MASK                   _MK_MASK_CONST(0x71)
#define PMC_IMPL_AOVC_LOCK_CNTRL_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define PMC_IMPL_AOVC_LOCK_CNTRL_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_AOVC_LOCK_CNTRL_0_READ_MASK                    _MK_MASK_CONST(0x71)
#define PMC_IMPL_AOVC_LOCK_CNTRL_0_WRITE_MASK                   _MK_MASK_CONST(0x71)
#define PMC_IMPL_AOVC_LOCK_CNTRL_0_SW_LOCK_REQ_SHIFT                    _MK_SHIFT_CONST(6)
#define PMC_IMPL_AOVC_LOCK_CNTRL_0_SW_LOCK_REQ_FIELD                    _MK_FIELD_CONST(0x1, PMC_IMPL_AOVC_LOCK_CNTRL_0_SW_LOCK_REQ_SHIFT)
#define PMC_IMPL_AOVC_LOCK_CNTRL_0_SW_LOCK_REQ_RANGE                    6:6
#define PMC_IMPL_AOVC_LOCK_CNTRL_0_SW_LOCK_REQ_WOFFSET                  0x0
#define PMC_IMPL_AOVC_LOCK_CNTRL_0_SW_LOCK_REQ_DEFAULT                  _MK_MASK_CONST(0x0)
#define PMC_IMPL_AOVC_LOCK_CNTRL_0_SW_LOCK_REQ_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define PMC_IMPL_AOVC_LOCK_CNTRL_0_SW_LOCK_REQ_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define PMC_IMPL_AOVC_LOCK_CNTRL_0_SW_LOCK_REQ_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define PMC_IMPL_AOVC_LOCK_CNTRL_0_SW_LOCK_REQ_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_AOVC_LOCK_CNTRL_0_SW_LOCK_REQ_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)

#define PMC_IMPL_AOVC_LOCK_CNTRL_0_SW_LOCK_REQ_ID_SHIFT                 _MK_SHIFT_CONST(4)
#define PMC_IMPL_AOVC_LOCK_CNTRL_0_SW_LOCK_REQ_ID_FIELD                 _MK_FIELD_CONST(0x3, PMC_IMPL_AOVC_LOCK_CNTRL_0_SW_LOCK_REQ_ID_SHIFT)
#define PMC_IMPL_AOVC_LOCK_CNTRL_0_SW_LOCK_REQ_ID_RANGE                 5:4
#define PMC_IMPL_AOVC_LOCK_CNTRL_0_SW_LOCK_REQ_ID_WOFFSET                       0x0
#define PMC_IMPL_AOVC_LOCK_CNTRL_0_SW_LOCK_REQ_ID_DEFAULT                       _MK_MASK_CONST(0x0)
#define PMC_IMPL_AOVC_LOCK_CNTRL_0_SW_LOCK_REQ_ID_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
#define PMC_IMPL_AOVC_LOCK_CNTRL_0_SW_LOCK_REQ_ID_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define PMC_IMPL_AOVC_LOCK_CNTRL_0_SW_LOCK_REQ_ID_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define PMC_IMPL_AOVC_LOCK_CNTRL_0_SW_LOCK_REQ_ID_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_AOVC_LOCK_CNTRL_0_SW_LOCK_REQ_ID_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)
#define PMC_IMPL_AOVC_LOCK_CNTRL_0_SW_LOCK_REQ_ID_INIT_ENUM                     FREE
#define PMC_IMPL_AOVC_LOCK_CNTRL_0_SW_LOCK_REQ_ID_FREE                  _MK_ENUM_CONST(0)
#define PMC_IMPL_AOVC_LOCK_CNTRL_0_SW_LOCK_REQ_ID_AOVC                  _MK_ENUM_CONST(1)
#define PMC_IMPL_AOVC_LOCK_CNTRL_0_SW_LOCK_REQ_ID_APB_PWR_I2C                   _MK_ENUM_CONST(2)
#define PMC_IMPL_AOVC_LOCK_CNTRL_0_SW_LOCK_REQ_ID_ILLEGAL                       _MK_ENUM_CONST(3)

#define PMC_IMPL_AOVC_LOCK_CNTRL_0_RELEASE_SHIFT                        _MK_SHIFT_CONST(0)
#define PMC_IMPL_AOVC_LOCK_CNTRL_0_RELEASE_FIELD                        _MK_FIELD_CONST(0x1, PMC_IMPL_AOVC_LOCK_CNTRL_0_RELEASE_SHIFT)
#define PMC_IMPL_AOVC_LOCK_CNTRL_0_RELEASE_RANGE                        0:0
#define PMC_IMPL_AOVC_LOCK_CNTRL_0_RELEASE_WOFFSET                      0x0
#define PMC_IMPL_AOVC_LOCK_CNTRL_0_RELEASE_DEFAULT                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_AOVC_LOCK_CNTRL_0_RELEASE_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define PMC_IMPL_AOVC_LOCK_CNTRL_0_RELEASE_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_AOVC_LOCK_CNTRL_0_RELEASE_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_AOVC_LOCK_CNTRL_0_RELEASE_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define PMC_IMPL_AOVC_LOCK_CNTRL_0_RELEASE_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)


// Register PMC_IMPL_AOVC_LOCK_ID_STATUS_0
#define PMC_IMPL_AOVC_LOCK_ID_STATUS_0                  _MK_ADDR_CONST(0x80c)
#define PMC_IMPL_AOVC_LOCK_ID_STATUS_0_SECURE                   0x0
#define PMC_IMPL_AOVC_LOCK_ID_STATUS_0_DUAL                     0x0
#define PMC_IMPL_AOVC_LOCK_ID_STATUS_0_SCR                      AOVC_LOCK_SCR_0
#define PMC_IMPL_AOVC_LOCK_ID_STATUS_0_WORD_COUNT                       0x1
#define PMC_IMPL_AOVC_LOCK_ID_STATUS_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_AOVC_LOCK_ID_STATUS_0_RESET_MASK                       _MK_MASK_CONST(0x0)
#define PMC_IMPL_AOVC_LOCK_ID_STATUS_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_AOVC_LOCK_ID_STATUS_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define PMC_IMPL_AOVC_LOCK_ID_STATUS_0_READ_MASK                        _MK_MASK_CONST(0x3)
#define PMC_IMPL_AOVC_LOCK_ID_STATUS_0_WRITE_MASK                       _MK_MASK_CONST(0x0)
#define PMC_IMPL_AOVC_LOCK_ID_STATUS_0_DATA_SHIFT                       _MK_SHIFT_CONST(0)
#define PMC_IMPL_AOVC_LOCK_ID_STATUS_0_DATA_FIELD                       _MK_FIELD_CONST(0x3, PMC_IMPL_AOVC_LOCK_ID_STATUS_0_DATA_SHIFT)
#define PMC_IMPL_AOVC_LOCK_ID_STATUS_0_DATA_RANGE                       1:0
#define PMC_IMPL_AOVC_LOCK_ID_STATUS_0_DATA_WOFFSET                     0x0
#define PMC_IMPL_AOVC_LOCK_ID_STATUS_0_DATA_DEFAULT                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_AOVC_LOCK_ID_STATUS_0_DATA_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_AOVC_LOCK_ID_STATUS_0_DATA_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define PMC_IMPL_AOVC_LOCK_ID_STATUS_0_DATA_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_AOVC_LOCK_ID_STATUS_0_DATA_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_AOVC_LOCK_ID_STATUS_0_DATA_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)


// Register PMC_IMPL_TEST_CLK_MUX_SEL_0
#define PMC_IMPL_TEST_CLK_MUX_SEL_0                     _MK_ADDR_CONST(0x810)
#define PMC_IMPL_TEST_CLK_MUX_SEL_0_SECURE                      0x0
#define PMC_IMPL_TEST_CLK_MUX_SEL_0_DUAL                        0x0
#define PMC_IMPL_TEST_CLK_MUX_SEL_0_SCR                         TEST_CLK_MUX_SCR_0
#define PMC_IMPL_TEST_CLK_MUX_SEL_0_WORD_COUNT                  0x1
#define PMC_IMPL_TEST_CLK_MUX_SEL_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_TEST_CLK_MUX_SEL_0_RESET_MASK                  _MK_MASK_CONST(0x1)
#define PMC_IMPL_TEST_CLK_MUX_SEL_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_TEST_CLK_MUX_SEL_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_TEST_CLK_MUX_SEL_0_READ_MASK                   _MK_MASK_CONST(0x1)
#define PMC_IMPL_TEST_CLK_MUX_SEL_0_WRITE_MASK                  _MK_MASK_CONST(0x1)
#define PMC_IMPL_TEST_CLK_MUX_SEL_0_SEL_SHIFT                   _MK_SHIFT_CONST(0)
#define PMC_IMPL_TEST_CLK_MUX_SEL_0_SEL_FIELD                   _MK_FIELD_CONST(0x1, PMC_IMPL_TEST_CLK_MUX_SEL_0_SEL_SHIFT)
#define PMC_IMPL_TEST_CLK_MUX_SEL_0_SEL_RANGE                   0:0
#define PMC_IMPL_TEST_CLK_MUX_SEL_0_SEL_WOFFSET                 0x0
#define PMC_IMPL_TEST_CLK_MUX_SEL_0_SEL_DEFAULT                 _MK_MASK_CONST(0x0)
#define PMC_IMPL_TEST_CLK_MUX_SEL_0_SEL_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define PMC_IMPL_TEST_CLK_MUX_SEL_0_SEL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_TEST_CLK_MUX_SEL_0_SEL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define PMC_IMPL_TEST_CLK_MUX_SEL_0_SEL_PARITY_PROTECTION                       _MK_MASK_CONST(0x1)
#define PMC_IMPL_TEST_CLK_MUX_SEL_0_SEL_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define PMC_IMPL_TEST_CLK_MUX_SEL_0_SEL_INIT_ENUM                       DISABLE
#define PMC_IMPL_TEST_CLK_MUX_SEL_0_SEL_DISABLE                 _MK_ENUM_CONST(0)
#define PMC_IMPL_TEST_CLK_MUX_SEL_0_SEL_ENABLE                  _MK_ENUM_CONST(1)


// Register PMC_IMPL_DPD_FSM_STATUS_0
#define PMC_IMPL_DPD_FSM_STATUS_0                       _MK_ADDR_CONST(0x814)
#define PMC_IMPL_DPD_FSM_STATUS_0_SECURE                        0x0
#define PMC_IMPL_DPD_FSM_STATUS_0_DUAL                  0x0
#define PMC_IMPL_DPD_FSM_STATUS_0_SCR                   0
#define PMC_IMPL_DPD_FSM_STATUS_0_WORD_COUNT                    0x1
#define PMC_IMPL_DPD_FSM_STATUS_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_DPD_FSM_STATUS_0_RESET_MASK                    _MK_MASK_CONST(0xfc003f)
#define PMC_IMPL_DPD_FSM_STATUS_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_DPD_FSM_STATUS_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define PMC_IMPL_DPD_FSM_STATUS_0_READ_MASK                     _MK_MASK_CONST(0xfc003f)
#define PMC_IMPL_DPD_FSM_STATUS_0_WRITE_MASK                    _MK_MASK_CONST(0x0)
#define PMC_IMPL_DPD_FSM_STATUS_0_DPD1_CSTATE_SHIFT                     _MK_SHIFT_CONST(0)
#define PMC_IMPL_DPD_FSM_STATUS_0_DPD1_CSTATE_FIELD                     _MK_FIELD_CONST(0x7, PMC_IMPL_DPD_FSM_STATUS_0_DPD1_CSTATE_SHIFT)
#define PMC_IMPL_DPD_FSM_STATUS_0_DPD1_CSTATE_RANGE                     2:0
#define PMC_IMPL_DPD_FSM_STATUS_0_DPD1_CSTATE_WOFFSET                   0x0
#define PMC_IMPL_DPD_FSM_STATUS_0_DPD1_CSTATE_DEFAULT                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_DPD_FSM_STATUS_0_DPD1_CSTATE_DEFAULT_MASK                      _MK_MASK_CONST(0x7)
#define PMC_IMPL_DPD_FSM_STATUS_0_DPD1_CSTATE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_DPD_FSM_STATUS_0_DPD1_CSTATE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_DPD_FSM_STATUS_0_DPD1_CSTATE_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define PMC_IMPL_DPD_FSM_STATUS_0_DPD1_CSTATE_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define PMC_IMPL_DPD_FSM_STATUS_0_DPD1_CSTATE_INIT_ENUM                 IDLE
#define PMC_IMPL_DPD_FSM_STATUS_0_DPD1_CSTATE_IDLE                      _MK_ENUM_CONST(0)
#define PMC_IMPL_DPD_FSM_STATUS_0_DPD1_CSTATE_ASSERT_WAIT                       _MK_ENUM_CONST(1)
#define PMC_IMPL_DPD_FSM_STATUS_0_DPD1_CSTATE_ASSERT                    _MK_ENUM_CONST(2)
#define PMC_IMPL_DPD_FSM_STATUS_0_DPD1_CSTATE_DEASSERT_WAIT                     _MK_ENUM_CONST(3)
#define PMC_IMPL_DPD_FSM_STATUS_0_DPD1_CSTATE_DEASSERT                  _MK_ENUM_CONST(4)

#define PMC_IMPL_DPD_FSM_STATUS_0_DPD2_CSTATE_SHIFT                     _MK_SHIFT_CONST(3)
#define PMC_IMPL_DPD_FSM_STATUS_0_DPD2_CSTATE_FIELD                     _MK_FIELD_CONST(0x7, PMC_IMPL_DPD_FSM_STATUS_0_DPD2_CSTATE_SHIFT)
#define PMC_IMPL_DPD_FSM_STATUS_0_DPD2_CSTATE_RANGE                     5:3
#define PMC_IMPL_DPD_FSM_STATUS_0_DPD2_CSTATE_WOFFSET                   0x0
#define PMC_IMPL_DPD_FSM_STATUS_0_DPD2_CSTATE_DEFAULT                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_DPD_FSM_STATUS_0_DPD2_CSTATE_DEFAULT_MASK                      _MK_MASK_CONST(0x7)
#define PMC_IMPL_DPD_FSM_STATUS_0_DPD2_CSTATE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_DPD_FSM_STATUS_0_DPD2_CSTATE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_DPD_FSM_STATUS_0_DPD2_CSTATE_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define PMC_IMPL_DPD_FSM_STATUS_0_DPD2_CSTATE_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define PMC_IMPL_DPD_FSM_STATUS_0_DPD2_CSTATE_INIT_ENUM                 IDLE
#define PMC_IMPL_DPD_FSM_STATUS_0_DPD2_CSTATE_IDLE                      _MK_ENUM_CONST(0)
#define PMC_IMPL_DPD_FSM_STATUS_0_DPD2_CSTATE_ASSERT_WAIT                       _MK_ENUM_CONST(1)
#define PMC_IMPL_DPD_FSM_STATUS_0_DPD2_CSTATE_ASSERT                    _MK_ENUM_CONST(2)
#define PMC_IMPL_DPD_FSM_STATUS_0_DPD2_CSTATE_DEASSERT_WAIT                     _MK_ENUM_CONST(3)
#define PMC_IMPL_DPD_FSM_STATUS_0_DPD2_CSTATE_DEASSERT                  _MK_ENUM_CONST(4)

#define PMC_IMPL_DPD_FSM_STATUS_0_DPD7_CSTATE_SHIFT                     _MK_SHIFT_CONST(18)
#define PMC_IMPL_DPD_FSM_STATUS_0_DPD7_CSTATE_FIELD                     _MK_FIELD_CONST(0x7, PMC_IMPL_DPD_FSM_STATUS_0_DPD7_CSTATE_SHIFT)
#define PMC_IMPL_DPD_FSM_STATUS_0_DPD7_CSTATE_RANGE                     20:18
#define PMC_IMPL_DPD_FSM_STATUS_0_DPD7_CSTATE_WOFFSET                   0x0
#define PMC_IMPL_DPD_FSM_STATUS_0_DPD7_CSTATE_DEFAULT                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_DPD_FSM_STATUS_0_DPD7_CSTATE_DEFAULT_MASK                      _MK_MASK_CONST(0x7)
#define PMC_IMPL_DPD_FSM_STATUS_0_DPD7_CSTATE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_DPD_FSM_STATUS_0_DPD7_CSTATE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_DPD_FSM_STATUS_0_DPD7_CSTATE_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define PMC_IMPL_DPD_FSM_STATUS_0_DPD7_CSTATE_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define PMC_IMPL_DPD_FSM_STATUS_0_DPD7_CSTATE_INIT_ENUM                 IDLE
#define PMC_IMPL_DPD_FSM_STATUS_0_DPD7_CSTATE_IDLE                      _MK_ENUM_CONST(0)
#define PMC_IMPL_DPD_FSM_STATUS_0_DPD7_CSTATE_ASSERT_WAIT                       _MK_ENUM_CONST(1)
#define PMC_IMPL_DPD_FSM_STATUS_0_DPD7_CSTATE_ASSERT                    _MK_ENUM_CONST(2)
#define PMC_IMPL_DPD_FSM_STATUS_0_DPD7_CSTATE_DEASSERT_WAIT                     _MK_ENUM_CONST(3)
#define PMC_IMPL_DPD_FSM_STATUS_0_DPD7_CSTATE_DEASSERT                  _MK_ENUM_CONST(4)

#define PMC_IMPL_DPD_FSM_STATUS_0_DPD8_CSTATE_SHIFT                     _MK_SHIFT_CONST(21)
#define PMC_IMPL_DPD_FSM_STATUS_0_DPD8_CSTATE_FIELD                     _MK_FIELD_CONST(0x7, PMC_IMPL_DPD_FSM_STATUS_0_DPD8_CSTATE_SHIFT)
#define PMC_IMPL_DPD_FSM_STATUS_0_DPD8_CSTATE_RANGE                     23:21
#define PMC_IMPL_DPD_FSM_STATUS_0_DPD8_CSTATE_WOFFSET                   0x0
#define PMC_IMPL_DPD_FSM_STATUS_0_DPD8_CSTATE_DEFAULT                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_DPD_FSM_STATUS_0_DPD8_CSTATE_DEFAULT_MASK                      _MK_MASK_CONST(0x7)
#define PMC_IMPL_DPD_FSM_STATUS_0_DPD8_CSTATE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_DPD_FSM_STATUS_0_DPD8_CSTATE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_DPD_FSM_STATUS_0_DPD8_CSTATE_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define PMC_IMPL_DPD_FSM_STATUS_0_DPD8_CSTATE_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define PMC_IMPL_DPD_FSM_STATUS_0_DPD8_CSTATE_INIT_ENUM                 IDLE
#define PMC_IMPL_DPD_FSM_STATUS_0_DPD8_CSTATE_IDLE                      _MK_ENUM_CONST(0)
#define PMC_IMPL_DPD_FSM_STATUS_0_DPD8_CSTATE_ASSERT_WAIT                       _MK_ENUM_CONST(1)
#define PMC_IMPL_DPD_FSM_STATUS_0_DPD8_CSTATE_ASSERT                    _MK_ENUM_CONST(2)
#define PMC_IMPL_DPD_FSM_STATUS_0_DPD8_CSTATE_DEASSERT_WAIT                     _MK_ENUM_CONST(3)
#define PMC_IMPL_DPD_FSM_STATUS_0_DPD8_CSTATE_DEASSERT                  _MK_ENUM_CONST(4)


// Register PMC_IMPL_SC7_FSM_STATUS_0
#define PMC_IMPL_SC7_FSM_STATUS_0                       _MK_ADDR_CONST(0x818)
#define PMC_IMPL_SC7_FSM_STATUS_0_SECURE                        0x0
#define PMC_IMPL_SC7_FSM_STATUS_0_DUAL                  0x0
#define PMC_IMPL_SC7_FSM_STATUS_0_SCR                   0
#define PMC_IMPL_SC7_FSM_STATUS_0_WORD_COUNT                    0x1
#define PMC_IMPL_SC7_FSM_STATUS_0_RESET_VAL                     _MK_MASK_CONST(0x1)
#define PMC_IMPL_SC7_FSM_STATUS_0_RESET_MASK                    _MK_MASK_CONST(0x7ffff)
#define PMC_IMPL_SC7_FSM_STATUS_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_SC7_FSM_STATUS_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define PMC_IMPL_SC7_FSM_STATUS_0_READ_MASK                     _MK_MASK_CONST(0x7ffff)
#define PMC_IMPL_SC7_FSM_STATUS_0_WRITE_MASK                    _MK_MASK_CONST(0x0)
#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_IDLE_SHIFT                        _MK_SHIFT_CONST(0)
#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_IDLE_FIELD                        _MK_FIELD_CONST(0x1, PMC_IMPL_SC7_FSM_STATUS_0_SC7_IDLE_SHIFT)
#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_IDLE_RANGE                        0:0
#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_IDLE_WOFFSET                      0x0
#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_IDLE_DEFAULT                      _MK_MASK_CONST(0x1)
#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_IDLE_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_IDLE_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_IDLE_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_IDLE_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_IDLE_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)
#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_IDLE_INIT_ENUM                    TRUE
#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_IDLE_FALSE                        _MK_ENUM_CONST(0)
#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_IDLE_TRUE                 _MK_ENUM_CONST(1)

#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_ASSERT_SLEEP_SHIFT                        _MK_SHIFT_CONST(1)
#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_ASSERT_SLEEP_FIELD                        _MK_FIELD_CONST(0x1, PMC_IMPL_SC7_FSM_STATUS_0_SC7_ASSERT_SLEEP_SHIFT)
#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_ASSERT_SLEEP_RANGE                        1:1
#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_ASSERT_SLEEP_WOFFSET                      0x0
#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_ASSERT_SLEEP_DEFAULT                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_ASSERT_SLEEP_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_ASSERT_SLEEP_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_ASSERT_SLEEP_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_ASSERT_SLEEP_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_ASSERT_SLEEP_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)
#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_ASSERT_SLEEP_INIT_ENUM                    FALSE
#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_ASSERT_SLEEP_FALSE                        _MK_ENUM_CONST(0)
#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_ASSERT_SLEEP_TRUE                 _MK_ENUM_CONST(1)

#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_ASSERT_SEL_SHIFT                  _MK_SHIFT_CONST(2)
#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_ASSERT_SEL_FIELD                  _MK_FIELD_CONST(0x1, PMC_IMPL_SC7_FSM_STATUS_0_SC7_ASSERT_SEL_SHIFT)
#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_ASSERT_SEL_RANGE                  2:2
#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_ASSERT_SEL_WOFFSET                        0x0
#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_ASSERT_SEL_DEFAULT                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_ASSERT_SEL_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_ASSERT_SEL_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_ASSERT_SEL_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_ASSERT_SEL_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_ASSERT_SEL_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_ASSERT_SEL_INIT_ENUM                      FALSE
#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_ASSERT_SEL_FALSE                  _MK_ENUM_CONST(0)
#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_ASSERT_SEL_TRUE                   _MK_ENUM_CONST(1)

#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_ASSERT_E_SHIFT                    _MK_SHIFT_CONST(3)
#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_ASSERT_E_FIELD                    _MK_FIELD_CONST(0x1, PMC_IMPL_SC7_FSM_STATUS_0_SC7_ASSERT_E_SHIFT)
#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_ASSERT_E_RANGE                    3:3
#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_ASSERT_E_WOFFSET                  0x0
#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_ASSERT_E_DEFAULT                  _MK_MASK_CONST(0x0)
#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_ASSERT_E_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_ASSERT_E_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_ASSERT_E_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_ASSERT_E_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_ASSERT_E_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)
#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_ASSERT_E_INIT_ENUM                        FALSE
#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_ASSERT_E_FALSE                    _MK_ENUM_CONST(0)
#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_ASSERT_E_TRUE                     _MK_ENUM_CONST(1)

#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_EARLY_CLAMP_SHIFT                 _MK_SHIFT_CONST(4)
#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_EARLY_CLAMP_FIELD                 _MK_FIELD_CONST(0x1, PMC_IMPL_SC7_FSM_STATUS_0_SC7_EARLY_CLAMP_SHIFT)
#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_EARLY_CLAMP_RANGE                 4:4
#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_EARLY_CLAMP_WOFFSET                       0x0
#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_EARLY_CLAMP_DEFAULT                       _MK_MASK_CONST(0x0)
#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_EARLY_CLAMP_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_EARLY_CLAMP_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_EARLY_CLAMP_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_EARLY_CLAMP_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_EARLY_CLAMP_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)
#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_EARLY_CLAMP_INIT_ENUM                     FALSE
#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_EARLY_CLAMP_FALSE                 _MK_ENUM_CONST(0)
#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_EARLY_CLAMP_TRUE                  _MK_ENUM_CONST(1)

#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_MAIN_CLAMP_SHIFT                  _MK_SHIFT_CONST(5)
#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_MAIN_CLAMP_FIELD                  _MK_FIELD_CONST(0x1, PMC_IMPL_SC7_FSM_STATUS_0_SC7_MAIN_CLAMP_SHIFT)
#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_MAIN_CLAMP_RANGE                  5:5
#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_MAIN_CLAMP_WOFFSET                        0x0
#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_MAIN_CLAMP_DEFAULT                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_MAIN_CLAMP_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_MAIN_CLAMP_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_MAIN_CLAMP_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_MAIN_CLAMP_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_MAIN_CLAMP_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_MAIN_CLAMP_INIT_ENUM                      FALSE
#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_MAIN_CLAMP_FALSE                  _MK_ENUM_CONST(0)
#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_MAIN_CLAMP_TRUE                   _MK_ENUM_CONST(1)

#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_PWR_OFF_SHIFT                     _MK_SHIFT_CONST(6)
#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_PWR_OFF_FIELD                     _MK_FIELD_CONST(0x1, PMC_IMPL_SC7_FSM_STATUS_0_SC7_PWR_OFF_SHIFT)
#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_PWR_OFF_RANGE                     6:6
#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_PWR_OFF_WOFFSET                   0x0
#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_PWR_OFF_DEFAULT                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_PWR_OFF_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_PWR_OFF_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_PWR_OFF_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_PWR_OFF_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_PWR_OFF_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_PWR_OFF_INIT_ENUM                 FALSE
#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_PWR_OFF_FALSE                     _MK_ENUM_CONST(0)
#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_PWR_OFF_TRUE                      _MK_ENUM_CONST(1)

#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_ALLOW_AOPG_SHIFT                  _MK_SHIFT_CONST(7)
#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_ALLOW_AOPG_FIELD                  _MK_FIELD_CONST(0x1, PMC_IMPL_SC7_FSM_STATUS_0_SC7_ALLOW_AOPG_SHIFT)
#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_ALLOW_AOPG_RANGE                  7:7
#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_ALLOW_AOPG_WOFFSET                        0x0
#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_ALLOW_AOPG_DEFAULT                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_ALLOW_AOPG_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_ALLOW_AOPG_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_ALLOW_AOPG_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_ALLOW_AOPG_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_ALLOW_AOPG_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_ALLOW_AOPG_INIT_ENUM                      FALSE
#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_ALLOW_AOPG_FALSE                  _MK_ENUM_CONST(0)
#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_ALLOW_AOPG_TRUE                   _MK_ENUM_CONST(1)

#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_OSC_OFF_SHIFT                     _MK_SHIFT_CONST(8)
#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_OSC_OFF_FIELD                     _MK_FIELD_CONST(0x1, PMC_IMPL_SC7_FSM_STATUS_0_SC7_OSC_OFF_SHIFT)
#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_OSC_OFF_RANGE                     8:8
#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_OSC_OFF_WOFFSET                   0x0
#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_OSC_OFF_DEFAULT                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_OSC_OFF_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_OSC_OFF_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_OSC_OFF_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_OSC_OFF_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_OSC_OFF_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_OSC_OFF_INIT_ENUM                 FALSE
#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_OSC_OFF_FALSE                     _MK_ENUM_CONST(0)
#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_OSC_OFF_TRUE                      _MK_ENUM_CONST(1)

#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_WAIT_FOR_RET_SHIFT                        _MK_SHIFT_CONST(9)
#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_WAIT_FOR_RET_FIELD                        _MK_FIELD_CONST(0x1, PMC_IMPL_SC7_FSM_STATUS_0_SC7_WAIT_FOR_RET_SHIFT)
#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_WAIT_FOR_RET_RANGE                        9:9
#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_WAIT_FOR_RET_WOFFSET                      0x0
#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_WAIT_FOR_RET_DEFAULT                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_WAIT_FOR_RET_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_WAIT_FOR_RET_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_WAIT_FOR_RET_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_WAIT_FOR_RET_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_WAIT_FOR_RET_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)
#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_WAIT_FOR_RET_INIT_ENUM                    FALSE
#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_WAIT_FOR_RET_FALSE                        _MK_ENUM_CONST(0)
#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_WAIT_FOR_RET_TRUE                 _MK_ENUM_CONST(1)

#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_OSC_ON_SHIFT                      _MK_SHIFT_CONST(10)
#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_OSC_ON_FIELD                      _MK_FIELD_CONST(0x1, PMC_IMPL_SC7_FSM_STATUS_0_SC7_OSC_ON_SHIFT)
#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_OSC_ON_RANGE                      10:10
#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_OSC_ON_WOFFSET                    0x0
#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_OSC_ON_DEFAULT                    _MK_MASK_CONST(0x0)
#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_OSC_ON_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_OSC_ON_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_OSC_ON_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_OSC_ON_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_OSC_ON_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_OSC_ON_INIT_ENUM                  FALSE
#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_OSC_ON_FALSE                      _MK_ENUM_CONST(0)
#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_OSC_ON_TRUE                       _MK_ENUM_CONST(1)

#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_ALLOW_AOUPG_SHIFT                 _MK_SHIFT_CONST(11)
#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_ALLOW_AOUPG_FIELD                 _MK_FIELD_CONST(0x1, PMC_IMPL_SC7_FSM_STATUS_0_SC7_ALLOW_AOUPG_SHIFT)
#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_ALLOW_AOUPG_RANGE                 11:11
#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_ALLOW_AOUPG_WOFFSET                       0x0
#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_ALLOW_AOUPG_DEFAULT                       _MK_MASK_CONST(0x0)
#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_ALLOW_AOUPG_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_ALLOW_AOUPG_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_ALLOW_AOUPG_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_ALLOW_AOUPG_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_ALLOW_AOUPG_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)
#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_ALLOW_AOUPG_INIT_ENUM                     FALSE
#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_ALLOW_AOUPG_FALSE                 _MK_ENUM_CONST(0)
#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_ALLOW_AOUPG_TRUE                  _MK_ENUM_CONST(1)

#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_PWR_ON_SHIFT                      _MK_SHIFT_CONST(12)
#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_PWR_ON_FIELD                      _MK_FIELD_CONST(0x1, PMC_IMPL_SC7_FSM_STATUS_0_SC7_PWR_ON_SHIFT)
#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_PWR_ON_RANGE                      12:12
#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_PWR_ON_WOFFSET                    0x0
#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_PWR_ON_DEFAULT                    _MK_MASK_CONST(0x0)
#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_PWR_ON_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_PWR_ON_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_PWR_ON_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_PWR_ON_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_PWR_ON_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_PWR_ON_INIT_ENUM                  FALSE
#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_PWR_ON_FALSE                      _MK_ENUM_CONST(0)
#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_PWR_ON_TRUE                       _MK_ENUM_CONST(1)

#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_REMOVE_CLAMP_SHIFT                        _MK_SHIFT_CONST(13)
#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_REMOVE_CLAMP_FIELD                        _MK_FIELD_CONST(0x1, PMC_IMPL_SC7_FSM_STATUS_0_SC7_REMOVE_CLAMP_SHIFT)
#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_REMOVE_CLAMP_RANGE                        13:13
#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_REMOVE_CLAMP_WOFFSET                      0x0
#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_REMOVE_CLAMP_DEFAULT                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_REMOVE_CLAMP_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_REMOVE_CLAMP_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_REMOVE_CLAMP_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_REMOVE_CLAMP_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_REMOVE_CLAMP_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)
#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_REMOVE_CLAMP_INIT_ENUM                    FALSE
#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_REMOVE_CLAMP_FALSE                        _MK_ENUM_CONST(0)
#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_REMOVE_CLAMP_TRUE                 _MK_ENUM_CONST(1)

#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_REMOVE_E_SHIFT                    _MK_SHIFT_CONST(14)
#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_REMOVE_E_FIELD                    _MK_FIELD_CONST(0x1, PMC_IMPL_SC7_FSM_STATUS_0_SC7_REMOVE_E_SHIFT)
#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_REMOVE_E_RANGE                    14:14
#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_REMOVE_E_WOFFSET                  0x0
#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_REMOVE_E_DEFAULT                  _MK_MASK_CONST(0x0)
#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_REMOVE_E_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_REMOVE_E_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_REMOVE_E_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_REMOVE_E_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_REMOVE_E_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)
#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_REMOVE_E_INIT_ENUM                        FALSE
#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_REMOVE_E_FALSE                    _MK_ENUM_CONST(0)
#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_REMOVE_E_TRUE                     _MK_ENUM_CONST(1)

#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_REMOVE_SEL_SHIFT                  _MK_SHIFT_CONST(15)
#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_REMOVE_SEL_FIELD                  _MK_FIELD_CONST(0x1, PMC_IMPL_SC7_FSM_STATUS_0_SC7_REMOVE_SEL_SHIFT)
#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_REMOVE_SEL_RANGE                  15:15
#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_REMOVE_SEL_WOFFSET                        0x0
#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_REMOVE_SEL_DEFAULT                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_REMOVE_SEL_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_REMOVE_SEL_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_REMOVE_SEL_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_REMOVE_SEL_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_REMOVE_SEL_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_REMOVE_SEL_INIT_ENUM                      FALSE
#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_REMOVE_SEL_FALSE                  _MK_ENUM_CONST(0)
#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_REMOVE_SEL_TRUE                   _MK_ENUM_CONST(1)

#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_REMOVE_RESET_SHIFT                        _MK_SHIFT_CONST(16)
#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_REMOVE_RESET_FIELD                        _MK_FIELD_CONST(0x1, PMC_IMPL_SC7_FSM_STATUS_0_SC7_REMOVE_RESET_SHIFT)
#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_REMOVE_RESET_RANGE                        16:16
#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_REMOVE_RESET_WOFFSET                      0x0
#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_REMOVE_RESET_DEFAULT                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_REMOVE_RESET_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_REMOVE_RESET_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_REMOVE_RESET_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_REMOVE_RESET_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_REMOVE_RESET_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)
#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_REMOVE_RESET_INIT_ENUM                    FALSE
#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_REMOVE_RESET_FALSE                        _MK_ENUM_CONST(0)
#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_REMOVE_RESET_TRUE                 _MK_ENUM_CONST(1)

#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_REMOVE_SLEEP_SHIFT                        _MK_SHIFT_CONST(17)
#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_REMOVE_SLEEP_FIELD                        _MK_FIELD_CONST(0x1, PMC_IMPL_SC7_FSM_STATUS_0_SC7_REMOVE_SLEEP_SHIFT)
#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_REMOVE_SLEEP_RANGE                        17:17
#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_REMOVE_SLEEP_WOFFSET                      0x0
#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_REMOVE_SLEEP_DEFAULT                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_REMOVE_SLEEP_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_REMOVE_SLEEP_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_REMOVE_SLEEP_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_REMOVE_SLEEP_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_REMOVE_SLEEP_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)
#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_REMOVE_SLEEP_INIT_ENUM                    FALSE
#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_REMOVE_SLEEP_FALSE                        _MK_ENUM_CONST(0)
#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_REMOVE_SLEEP_TRUE                 _MK_ENUM_CONST(1)

#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_WAIT_DPD_DIS_SHIFT                        _MK_SHIFT_CONST(18)
#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_WAIT_DPD_DIS_FIELD                        _MK_FIELD_CONST(0x1, PMC_IMPL_SC7_FSM_STATUS_0_SC7_WAIT_DPD_DIS_SHIFT)
#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_WAIT_DPD_DIS_RANGE                        18:18
#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_WAIT_DPD_DIS_WOFFSET                      0x0
#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_WAIT_DPD_DIS_DEFAULT                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_WAIT_DPD_DIS_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_WAIT_DPD_DIS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_WAIT_DPD_DIS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_WAIT_DPD_DIS_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_WAIT_DPD_DIS_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)
#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_WAIT_DPD_DIS_INIT_ENUM                    FALSE
#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_WAIT_DPD_DIS_FALSE                        _MK_ENUM_CONST(0)
#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_WAIT_DPD_DIS_TRUE                 _MK_ENUM_CONST(1)


// Register PMC_IMPL_RAMDUMP_FIQ_EXIT_0
#define PMC_IMPL_RAMDUMP_FIQ_EXIT_0                     _MK_ADDR_CONST(0x81c)
#define PMC_IMPL_RAMDUMP_FIQ_EXIT_0_SECURE                      0x0
#define PMC_IMPL_RAMDUMP_FIQ_EXIT_0_DUAL                        0x0
#define PMC_IMPL_RAMDUMP_FIQ_EXIT_0_SCR                         RAMDUMP_COM_SCR_0
#define PMC_IMPL_RAMDUMP_FIQ_EXIT_0_WORD_COUNT                  0x1
#define PMC_IMPL_RAMDUMP_FIQ_EXIT_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_RAMDUMP_FIQ_EXIT_0_RESET_MASK                  _MK_MASK_CONST(0x3)
#define PMC_IMPL_RAMDUMP_FIQ_EXIT_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_RAMDUMP_FIQ_EXIT_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_RAMDUMP_FIQ_EXIT_0_READ_MASK                   _MK_MASK_CONST(0x3)
#define PMC_IMPL_RAMDUMP_FIQ_EXIT_0_WRITE_MASK                  _MK_MASK_CONST(0x3)
#define PMC_IMPL_RAMDUMP_FIQ_EXIT_0_PVA0_FIQ_EXITED_GRACEFULLY_SHIFT                    _MK_SHIFT_CONST(0)
#define PMC_IMPL_RAMDUMP_FIQ_EXIT_0_PVA0_FIQ_EXITED_GRACEFULLY_FIELD                    _MK_FIELD_CONST(0x1, PMC_IMPL_RAMDUMP_FIQ_EXIT_0_PVA0_FIQ_EXITED_GRACEFULLY_SHIFT)
#define PMC_IMPL_RAMDUMP_FIQ_EXIT_0_PVA0_FIQ_EXITED_GRACEFULLY_RANGE                    0:0
#define PMC_IMPL_RAMDUMP_FIQ_EXIT_0_PVA0_FIQ_EXITED_GRACEFULLY_WOFFSET                  0x0
#define PMC_IMPL_RAMDUMP_FIQ_EXIT_0_PVA0_FIQ_EXITED_GRACEFULLY_DEFAULT                  _MK_MASK_CONST(0x0)
#define PMC_IMPL_RAMDUMP_FIQ_EXIT_0_PVA0_FIQ_EXITED_GRACEFULLY_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define PMC_IMPL_RAMDUMP_FIQ_EXIT_0_PVA0_FIQ_EXITED_GRACEFULLY_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define PMC_IMPL_RAMDUMP_FIQ_EXIT_0_PVA0_FIQ_EXITED_GRACEFULLY_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define PMC_IMPL_RAMDUMP_FIQ_EXIT_0_PVA0_FIQ_EXITED_GRACEFULLY_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_RAMDUMP_FIQ_EXIT_0_PVA0_FIQ_EXITED_GRACEFULLY_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)

#define PMC_IMPL_RAMDUMP_FIQ_EXIT_0_PVA1_FIQ_EXITED_GRACEFULLY_SHIFT                    _MK_SHIFT_CONST(1)
#define PMC_IMPL_RAMDUMP_FIQ_EXIT_0_PVA1_FIQ_EXITED_GRACEFULLY_FIELD                    _MK_FIELD_CONST(0x1, PMC_IMPL_RAMDUMP_FIQ_EXIT_0_PVA1_FIQ_EXITED_GRACEFULLY_SHIFT)
#define PMC_IMPL_RAMDUMP_FIQ_EXIT_0_PVA1_FIQ_EXITED_GRACEFULLY_RANGE                    1:1
#define PMC_IMPL_RAMDUMP_FIQ_EXIT_0_PVA1_FIQ_EXITED_GRACEFULLY_WOFFSET                  0x0
#define PMC_IMPL_RAMDUMP_FIQ_EXIT_0_PVA1_FIQ_EXITED_GRACEFULLY_DEFAULT                  _MK_MASK_CONST(0x0)
#define PMC_IMPL_RAMDUMP_FIQ_EXIT_0_PVA1_FIQ_EXITED_GRACEFULLY_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define PMC_IMPL_RAMDUMP_FIQ_EXIT_0_PVA1_FIQ_EXITED_GRACEFULLY_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define PMC_IMPL_RAMDUMP_FIQ_EXIT_0_PVA1_FIQ_EXITED_GRACEFULLY_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define PMC_IMPL_RAMDUMP_FIQ_EXIT_0_PVA1_FIQ_EXITED_GRACEFULLY_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_RAMDUMP_FIQ_EXIT_0_PVA1_FIQ_EXITED_GRACEFULLY_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)


// Register PMC_IMPL_SET_RAMDUMP_FIQ_EXIT_0
#define PMC_IMPL_SET_RAMDUMP_FIQ_EXIT_0                 _MK_ADDR_CONST(0x820)
#define PMC_IMPL_SET_RAMDUMP_FIQ_EXIT_0_SECURE                  0x0
#define PMC_IMPL_SET_RAMDUMP_FIQ_EXIT_0_DUAL                    0x0
#define PMC_IMPL_SET_RAMDUMP_FIQ_EXIT_0_SCR                     RAMDUMP_COM_SCR_0
#define PMC_IMPL_SET_RAMDUMP_FIQ_EXIT_0_WORD_COUNT                      0x1
#define PMC_IMPL_SET_RAMDUMP_FIQ_EXIT_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define PMC_IMPL_SET_RAMDUMP_FIQ_EXIT_0_RESET_MASK                      _MK_MASK_CONST(0x3)
#define PMC_IMPL_SET_RAMDUMP_FIQ_EXIT_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define PMC_IMPL_SET_RAMDUMP_FIQ_EXIT_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define PMC_IMPL_SET_RAMDUMP_FIQ_EXIT_0_READ_MASK                       _MK_MASK_CONST(0x3)
#define PMC_IMPL_SET_RAMDUMP_FIQ_EXIT_0_WRITE_MASK                      _MK_MASK_CONST(0x3)
#define PMC_IMPL_SET_RAMDUMP_FIQ_EXIT_0_SET_PVA0_FIQ_EXITED_GRACEFULLY_SHIFT                    _MK_SHIFT_CONST(0)
#define PMC_IMPL_SET_RAMDUMP_FIQ_EXIT_0_SET_PVA0_FIQ_EXITED_GRACEFULLY_FIELD                    _MK_FIELD_CONST(0x1, PMC_IMPL_SET_RAMDUMP_FIQ_EXIT_0_SET_PVA0_FIQ_EXITED_GRACEFULLY_SHIFT)
#define PMC_IMPL_SET_RAMDUMP_FIQ_EXIT_0_SET_PVA0_FIQ_EXITED_GRACEFULLY_RANGE                    0:0
#define PMC_IMPL_SET_RAMDUMP_FIQ_EXIT_0_SET_PVA0_FIQ_EXITED_GRACEFULLY_WOFFSET                  0x0
#define PMC_IMPL_SET_RAMDUMP_FIQ_EXIT_0_SET_PVA0_FIQ_EXITED_GRACEFULLY_DEFAULT                  _MK_MASK_CONST(0x0)
#define PMC_IMPL_SET_RAMDUMP_FIQ_EXIT_0_SET_PVA0_FIQ_EXITED_GRACEFULLY_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define PMC_IMPL_SET_RAMDUMP_FIQ_EXIT_0_SET_PVA0_FIQ_EXITED_GRACEFULLY_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define PMC_IMPL_SET_RAMDUMP_FIQ_EXIT_0_SET_PVA0_FIQ_EXITED_GRACEFULLY_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define PMC_IMPL_SET_RAMDUMP_FIQ_EXIT_0_SET_PVA0_FIQ_EXITED_GRACEFULLY_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_SET_RAMDUMP_FIQ_EXIT_0_SET_PVA0_FIQ_EXITED_GRACEFULLY_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)

#define PMC_IMPL_SET_RAMDUMP_FIQ_EXIT_0_SET_PVA1_FIQ_EXITED_GRACEFULLY_SHIFT                    _MK_SHIFT_CONST(1)
#define PMC_IMPL_SET_RAMDUMP_FIQ_EXIT_0_SET_PVA1_FIQ_EXITED_GRACEFULLY_FIELD                    _MK_FIELD_CONST(0x1, PMC_IMPL_SET_RAMDUMP_FIQ_EXIT_0_SET_PVA1_FIQ_EXITED_GRACEFULLY_SHIFT)
#define PMC_IMPL_SET_RAMDUMP_FIQ_EXIT_0_SET_PVA1_FIQ_EXITED_GRACEFULLY_RANGE                    1:1
#define PMC_IMPL_SET_RAMDUMP_FIQ_EXIT_0_SET_PVA1_FIQ_EXITED_GRACEFULLY_WOFFSET                  0x0
#define PMC_IMPL_SET_RAMDUMP_FIQ_EXIT_0_SET_PVA1_FIQ_EXITED_GRACEFULLY_DEFAULT                  _MK_MASK_CONST(0x0)
#define PMC_IMPL_SET_RAMDUMP_FIQ_EXIT_0_SET_PVA1_FIQ_EXITED_GRACEFULLY_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define PMC_IMPL_SET_RAMDUMP_FIQ_EXIT_0_SET_PVA1_FIQ_EXITED_GRACEFULLY_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define PMC_IMPL_SET_RAMDUMP_FIQ_EXIT_0_SET_PVA1_FIQ_EXITED_GRACEFULLY_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define PMC_IMPL_SET_RAMDUMP_FIQ_EXIT_0_SET_PVA1_FIQ_EXITED_GRACEFULLY_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_SET_RAMDUMP_FIQ_EXIT_0_SET_PVA1_FIQ_EXITED_GRACEFULLY_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)


// Register PMC_IMPL_CLR_RAMDUMP_FIQ_EXIT_0
#define PMC_IMPL_CLR_RAMDUMP_FIQ_EXIT_0                 _MK_ADDR_CONST(0x824)
#define PMC_IMPL_CLR_RAMDUMP_FIQ_EXIT_0_SECURE                  0x0
#define PMC_IMPL_CLR_RAMDUMP_FIQ_EXIT_0_DUAL                    0x0
#define PMC_IMPL_CLR_RAMDUMP_FIQ_EXIT_0_SCR                     RAMDUMP_COM_SCR_0
#define PMC_IMPL_CLR_RAMDUMP_FIQ_EXIT_0_WORD_COUNT                      0x1
#define PMC_IMPL_CLR_RAMDUMP_FIQ_EXIT_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define PMC_IMPL_CLR_RAMDUMP_FIQ_EXIT_0_RESET_MASK                      _MK_MASK_CONST(0x3)
#define PMC_IMPL_CLR_RAMDUMP_FIQ_EXIT_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define PMC_IMPL_CLR_RAMDUMP_FIQ_EXIT_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define PMC_IMPL_CLR_RAMDUMP_FIQ_EXIT_0_READ_MASK                       _MK_MASK_CONST(0x3)
#define PMC_IMPL_CLR_RAMDUMP_FIQ_EXIT_0_WRITE_MASK                      _MK_MASK_CONST(0x3)
#define PMC_IMPL_CLR_RAMDUMP_FIQ_EXIT_0_CLR_PVA0_FIQ_EXITED_GRACEFULLY_SHIFT                    _MK_SHIFT_CONST(0)
#define PMC_IMPL_CLR_RAMDUMP_FIQ_EXIT_0_CLR_PVA0_FIQ_EXITED_GRACEFULLY_FIELD                    _MK_FIELD_CONST(0x1, PMC_IMPL_CLR_RAMDUMP_FIQ_EXIT_0_CLR_PVA0_FIQ_EXITED_GRACEFULLY_SHIFT)
#define PMC_IMPL_CLR_RAMDUMP_FIQ_EXIT_0_CLR_PVA0_FIQ_EXITED_GRACEFULLY_RANGE                    0:0
#define PMC_IMPL_CLR_RAMDUMP_FIQ_EXIT_0_CLR_PVA0_FIQ_EXITED_GRACEFULLY_WOFFSET                  0x0
#define PMC_IMPL_CLR_RAMDUMP_FIQ_EXIT_0_CLR_PVA0_FIQ_EXITED_GRACEFULLY_DEFAULT                  _MK_MASK_CONST(0x0)
#define PMC_IMPL_CLR_RAMDUMP_FIQ_EXIT_0_CLR_PVA0_FIQ_EXITED_GRACEFULLY_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define PMC_IMPL_CLR_RAMDUMP_FIQ_EXIT_0_CLR_PVA0_FIQ_EXITED_GRACEFULLY_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define PMC_IMPL_CLR_RAMDUMP_FIQ_EXIT_0_CLR_PVA0_FIQ_EXITED_GRACEFULLY_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define PMC_IMPL_CLR_RAMDUMP_FIQ_EXIT_0_CLR_PVA0_FIQ_EXITED_GRACEFULLY_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_CLR_RAMDUMP_FIQ_EXIT_0_CLR_PVA0_FIQ_EXITED_GRACEFULLY_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)

#define PMC_IMPL_CLR_RAMDUMP_FIQ_EXIT_0_CLR_PVA1_FIQ_EXITED_GRACEFULLY_SHIFT                    _MK_SHIFT_CONST(1)
#define PMC_IMPL_CLR_RAMDUMP_FIQ_EXIT_0_CLR_PVA1_FIQ_EXITED_GRACEFULLY_FIELD                    _MK_FIELD_CONST(0x1, PMC_IMPL_CLR_RAMDUMP_FIQ_EXIT_0_CLR_PVA1_FIQ_EXITED_GRACEFULLY_SHIFT)
#define PMC_IMPL_CLR_RAMDUMP_FIQ_EXIT_0_CLR_PVA1_FIQ_EXITED_GRACEFULLY_RANGE                    1:1
#define PMC_IMPL_CLR_RAMDUMP_FIQ_EXIT_0_CLR_PVA1_FIQ_EXITED_GRACEFULLY_WOFFSET                  0x0
#define PMC_IMPL_CLR_RAMDUMP_FIQ_EXIT_0_CLR_PVA1_FIQ_EXITED_GRACEFULLY_DEFAULT                  _MK_MASK_CONST(0x0)
#define PMC_IMPL_CLR_RAMDUMP_FIQ_EXIT_0_CLR_PVA1_FIQ_EXITED_GRACEFULLY_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define PMC_IMPL_CLR_RAMDUMP_FIQ_EXIT_0_CLR_PVA1_FIQ_EXITED_GRACEFULLY_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define PMC_IMPL_CLR_RAMDUMP_FIQ_EXIT_0_CLR_PVA1_FIQ_EXITED_GRACEFULLY_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define PMC_IMPL_CLR_RAMDUMP_FIQ_EXIT_0_CLR_PVA1_FIQ_EXITED_GRACEFULLY_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_CLR_RAMDUMP_FIQ_EXIT_0_CLR_PVA1_FIQ_EXITED_GRACEFULLY_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)


// Register PMC_IMPL_FMON_THRESHOLD_HIGH_PMC_CK_0
#define PMC_IMPL_FMON_THRESHOLD_HIGH_PMC_CK_0                   _MK_ADDR_CONST(0x828)
#define PMC_IMPL_FMON_THRESHOLD_HIGH_PMC_CK_0_SECURE                    0x0
#define PMC_IMPL_FMON_THRESHOLD_HIGH_PMC_CK_0_DUAL                      0x0
#define PMC_IMPL_FMON_THRESHOLD_HIGH_PMC_CK_0_SCR                       PMC_CK_SCR_0
#define PMC_IMPL_FMON_THRESHOLD_HIGH_PMC_CK_0_WORD_COUNT                        0x1
#define PMC_IMPL_FMON_THRESHOLD_HIGH_PMC_CK_0_RESET_VAL                         _MK_MASK_CONST(0x865)
#define PMC_IMPL_FMON_THRESHOLD_HIGH_PMC_CK_0_RESET_MASK                        _MK_MASK_CONST(0xffffffff)
#define PMC_IMPL_FMON_THRESHOLD_HIGH_PMC_CK_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define PMC_IMPL_FMON_THRESHOLD_HIGH_PMC_CK_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_FMON_THRESHOLD_HIGH_PMC_CK_0_READ_MASK                         _MK_MASK_CONST(0xffffffff)
#define PMC_IMPL_FMON_THRESHOLD_HIGH_PMC_CK_0_WRITE_MASK                        _MK_MASK_CONST(0xffffffff)
#define PMC_IMPL_FMON_THRESHOLD_HIGH_PMC_CK_0_FMON_COUNT_THRESH_HIGH_PMC_CK_SHIFT                       _MK_SHIFT_CONST(0)
#define PMC_IMPL_FMON_THRESHOLD_HIGH_PMC_CK_0_FMON_COUNT_THRESH_HIGH_PMC_CK_FIELD                       _MK_FIELD_CONST(0xffffffff, PMC_IMPL_FMON_THRESHOLD_HIGH_PMC_CK_0_FMON_COUNT_THRESH_HIGH_PMC_CK_SHIFT)
#define PMC_IMPL_FMON_THRESHOLD_HIGH_PMC_CK_0_FMON_COUNT_THRESH_HIGH_PMC_CK_RANGE                       31:0
#define PMC_IMPL_FMON_THRESHOLD_HIGH_PMC_CK_0_FMON_COUNT_THRESH_HIGH_PMC_CK_WOFFSET                     0x0
#define PMC_IMPL_FMON_THRESHOLD_HIGH_PMC_CK_0_FMON_COUNT_THRESH_HIGH_PMC_CK_DEFAULT                     _MK_MASK_CONST(0x865)
#define PMC_IMPL_FMON_THRESHOLD_HIGH_PMC_CK_0_FMON_COUNT_THRESH_HIGH_PMC_CK_DEFAULT_MASK                        _MK_MASK_CONST(0xffffffff)
#define PMC_IMPL_FMON_THRESHOLD_HIGH_PMC_CK_0_FMON_COUNT_THRESH_HIGH_PMC_CK_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define PMC_IMPL_FMON_THRESHOLD_HIGH_PMC_CK_0_FMON_COUNT_THRESH_HIGH_PMC_CK_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_FMON_THRESHOLD_HIGH_PMC_CK_0_FMON_COUNT_THRESH_HIGH_PMC_CK_PARITY_PROTECTION                   _MK_MASK_CONST(0x1)
#define PMC_IMPL_FMON_THRESHOLD_HIGH_PMC_CK_0_FMON_COUNT_THRESH_HIGH_PMC_CK_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)


// Register PMC_IMPL_FMON_THRESHOLD_LOW_PMC_CK_0
#define PMC_IMPL_FMON_THRESHOLD_LOW_PMC_CK_0                    _MK_ADDR_CONST(0x82c)
#define PMC_IMPL_FMON_THRESHOLD_LOW_PMC_CK_0_SECURE                     0x0
#define PMC_IMPL_FMON_THRESHOLD_LOW_PMC_CK_0_DUAL                       0x0
#define PMC_IMPL_FMON_THRESHOLD_LOW_PMC_CK_0_SCR                        PMC_CK_SCR_0
#define PMC_IMPL_FMON_THRESHOLD_LOW_PMC_CK_0_WORD_COUNT                         0x1
#define PMC_IMPL_FMON_THRESHOLD_LOW_PMC_CK_0_RESET_VAL                  _MK_MASK_CONST(0x388)
#define PMC_IMPL_FMON_THRESHOLD_LOW_PMC_CK_0_RESET_MASK                         _MK_MASK_CONST(0xffffffff)
#define PMC_IMPL_FMON_THRESHOLD_LOW_PMC_CK_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_FMON_THRESHOLD_LOW_PMC_CK_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define PMC_IMPL_FMON_THRESHOLD_LOW_PMC_CK_0_READ_MASK                  _MK_MASK_CONST(0xffffffff)
#define PMC_IMPL_FMON_THRESHOLD_LOW_PMC_CK_0_WRITE_MASK                         _MK_MASK_CONST(0xffffffff)
#define PMC_IMPL_FMON_THRESHOLD_LOW_PMC_CK_0_FMON_COUNT_THRESH_LOW_PMC_CK_SHIFT                 _MK_SHIFT_CONST(0)
#define PMC_IMPL_FMON_THRESHOLD_LOW_PMC_CK_0_FMON_COUNT_THRESH_LOW_PMC_CK_FIELD                 _MK_FIELD_CONST(0xffffffff, PMC_IMPL_FMON_THRESHOLD_LOW_PMC_CK_0_FMON_COUNT_THRESH_LOW_PMC_CK_SHIFT)
#define PMC_IMPL_FMON_THRESHOLD_LOW_PMC_CK_0_FMON_COUNT_THRESH_LOW_PMC_CK_RANGE                 31:0
#define PMC_IMPL_FMON_THRESHOLD_LOW_PMC_CK_0_FMON_COUNT_THRESH_LOW_PMC_CK_WOFFSET                       0x0
#define PMC_IMPL_FMON_THRESHOLD_LOW_PMC_CK_0_FMON_COUNT_THRESH_LOW_PMC_CK_DEFAULT                       _MK_MASK_CONST(0x388)
#define PMC_IMPL_FMON_THRESHOLD_LOW_PMC_CK_0_FMON_COUNT_THRESH_LOW_PMC_CK_DEFAULT_MASK                  _MK_MASK_CONST(0xffffffff)
#define PMC_IMPL_FMON_THRESHOLD_LOW_PMC_CK_0_FMON_COUNT_THRESH_LOW_PMC_CK_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define PMC_IMPL_FMON_THRESHOLD_LOW_PMC_CK_0_FMON_COUNT_THRESH_LOW_PMC_CK_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define PMC_IMPL_FMON_THRESHOLD_LOW_PMC_CK_0_FMON_COUNT_THRESH_LOW_PMC_CK_PARITY_PROTECTION                     _MK_MASK_CONST(0x1)
#define PMC_IMPL_FMON_THRESHOLD_LOW_PMC_CK_0_FMON_COUNT_THRESH_LOW_PMC_CK_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)


// Register PMC_IMPL_FMON_REF_WINDOW_COUNT_PMC_CK_0
#define PMC_IMPL_FMON_REF_WINDOW_COUNT_PMC_CK_0                 _MK_ADDR_CONST(0x830)
#define PMC_IMPL_FMON_REF_WINDOW_COUNT_PMC_CK_0_SECURE                  0x0
#define PMC_IMPL_FMON_REF_WINDOW_COUNT_PMC_CK_0_DUAL                    0x0
#define PMC_IMPL_FMON_REF_WINDOW_COUNT_PMC_CK_0_SCR                     PMC_CK_SCR_0
#define PMC_IMPL_FMON_REF_WINDOW_COUNT_PMC_CK_0_WORD_COUNT                      0x1
#define PMC_IMPL_FMON_REF_WINDOW_COUNT_PMC_CK_0_RESET_VAL                       _MK_MASK_CONST(0x1)
#define PMC_IMPL_FMON_REF_WINDOW_COUNT_PMC_CK_0_RESET_MASK                      _MK_MASK_CONST(0xffffff)
#define PMC_IMPL_FMON_REF_WINDOW_COUNT_PMC_CK_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define PMC_IMPL_FMON_REF_WINDOW_COUNT_PMC_CK_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define PMC_IMPL_FMON_REF_WINDOW_COUNT_PMC_CK_0_READ_MASK                       _MK_MASK_CONST(0xffffff)
#define PMC_IMPL_FMON_REF_WINDOW_COUNT_PMC_CK_0_WRITE_MASK                      _MK_MASK_CONST(0xffffff)
#define PMC_IMPL_FMON_REF_WINDOW_COUNT_PMC_CK_0_FMON_REF_WINDOW_COUNT_PMC_CK_SHIFT                      _MK_SHIFT_CONST(0)
#define PMC_IMPL_FMON_REF_WINDOW_COUNT_PMC_CK_0_FMON_REF_WINDOW_COUNT_PMC_CK_FIELD                      _MK_FIELD_CONST(0xffffff, PMC_IMPL_FMON_REF_WINDOW_COUNT_PMC_CK_0_FMON_REF_WINDOW_COUNT_PMC_CK_SHIFT)
#define PMC_IMPL_FMON_REF_WINDOW_COUNT_PMC_CK_0_FMON_REF_WINDOW_COUNT_PMC_CK_RANGE                      23:0
#define PMC_IMPL_FMON_REF_WINDOW_COUNT_PMC_CK_0_FMON_REF_WINDOW_COUNT_PMC_CK_WOFFSET                    0x0
#define PMC_IMPL_FMON_REF_WINDOW_COUNT_PMC_CK_0_FMON_REF_WINDOW_COUNT_PMC_CK_DEFAULT                    _MK_MASK_CONST(0x1)
#define PMC_IMPL_FMON_REF_WINDOW_COUNT_PMC_CK_0_FMON_REF_WINDOW_COUNT_PMC_CK_DEFAULT_MASK                       _MK_MASK_CONST(0xffffff)
#define PMC_IMPL_FMON_REF_WINDOW_COUNT_PMC_CK_0_FMON_REF_WINDOW_COUNT_PMC_CK_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define PMC_IMPL_FMON_REF_WINDOW_COUNT_PMC_CK_0_FMON_REF_WINDOW_COUNT_PMC_CK_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define PMC_IMPL_FMON_REF_WINDOW_COUNT_PMC_CK_0_FMON_REF_WINDOW_COUNT_PMC_CK_PARITY_PROTECTION                  _MK_MASK_CONST(0x1)
#define PMC_IMPL_FMON_REF_WINDOW_COUNT_PMC_CK_0_FMON_REF_WINDOW_COUNT_PMC_CK_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)


// Register PMC_IMPL_FMON_REF_WINDOW_DC_CHECK_COUNT_PMC_CK_0
#define PMC_IMPL_FMON_REF_WINDOW_DC_CHECK_COUNT_PMC_CK_0                        _MK_ADDR_CONST(0x834)
#define PMC_IMPL_FMON_REF_WINDOW_DC_CHECK_COUNT_PMC_CK_0_SECURE                         0x0
#define PMC_IMPL_FMON_REF_WINDOW_DC_CHECK_COUNT_PMC_CK_0_DUAL                   0x0
#define PMC_IMPL_FMON_REF_WINDOW_DC_CHECK_COUNT_PMC_CK_0_SCR                    PMC_CK_SCR_0
#define PMC_IMPL_FMON_REF_WINDOW_DC_CHECK_COUNT_PMC_CK_0_WORD_COUNT                     0x1
#define PMC_IMPL_FMON_REF_WINDOW_DC_CHECK_COUNT_PMC_CK_0_RESET_VAL                      _MK_MASK_CONST(0xffffff)
#define PMC_IMPL_FMON_REF_WINDOW_DC_CHECK_COUNT_PMC_CK_0_RESET_MASK                     _MK_MASK_CONST(0xffffff)
#define PMC_IMPL_FMON_REF_WINDOW_DC_CHECK_COUNT_PMC_CK_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define PMC_IMPL_FMON_REF_WINDOW_DC_CHECK_COUNT_PMC_CK_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_FMON_REF_WINDOW_DC_CHECK_COUNT_PMC_CK_0_READ_MASK                      _MK_MASK_CONST(0xffffff)
#define PMC_IMPL_FMON_REF_WINDOW_DC_CHECK_COUNT_PMC_CK_0_WRITE_MASK                     _MK_MASK_CONST(0xffffff)
#define PMC_IMPL_FMON_REF_WINDOW_DC_CHECK_COUNT_PMC_CK_0_FMON_REF_WINDOW_DC_CHECK_COUNT_PMC_CK_SHIFT                    _MK_SHIFT_CONST(0)
#define PMC_IMPL_FMON_REF_WINDOW_DC_CHECK_COUNT_PMC_CK_0_FMON_REF_WINDOW_DC_CHECK_COUNT_PMC_CK_FIELD                    _MK_FIELD_CONST(0xffffff, PMC_IMPL_FMON_REF_WINDOW_DC_CHECK_COUNT_PMC_CK_0_FMON_REF_WINDOW_DC_CHECK_COUNT_PMC_CK_SHIFT)
#define PMC_IMPL_FMON_REF_WINDOW_DC_CHECK_COUNT_PMC_CK_0_FMON_REF_WINDOW_DC_CHECK_COUNT_PMC_CK_RANGE                    23:0
#define PMC_IMPL_FMON_REF_WINDOW_DC_CHECK_COUNT_PMC_CK_0_FMON_REF_WINDOW_DC_CHECK_COUNT_PMC_CK_WOFFSET                  0x0
#define PMC_IMPL_FMON_REF_WINDOW_DC_CHECK_COUNT_PMC_CK_0_FMON_REF_WINDOW_DC_CHECK_COUNT_PMC_CK_DEFAULT                  _MK_MASK_CONST(0xffffff)
#define PMC_IMPL_FMON_REF_WINDOW_DC_CHECK_COUNT_PMC_CK_0_FMON_REF_WINDOW_DC_CHECK_COUNT_PMC_CK_DEFAULT_MASK                     _MK_MASK_CONST(0xffffff)
#define PMC_IMPL_FMON_REF_WINDOW_DC_CHECK_COUNT_PMC_CK_0_FMON_REF_WINDOW_DC_CHECK_COUNT_PMC_CK_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define PMC_IMPL_FMON_REF_WINDOW_DC_CHECK_COUNT_PMC_CK_0_FMON_REF_WINDOW_DC_CHECK_COUNT_PMC_CK_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define PMC_IMPL_FMON_REF_WINDOW_DC_CHECK_COUNT_PMC_CK_0_FMON_REF_WINDOW_DC_CHECK_COUNT_PMC_CK_PARITY_PROTECTION                        _MK_MASK_CONST(0x1)
#define PMC_IMPL_FMON_REF_WINDOW_DC_CHECK_COUNT_PMC_CK_0_FMON_REF_WINDOW_DC_CHECK_COUNT_PMC_CK_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)


// Register PMC_IMPL_FMON_FAULT_ACTION_PMC_CK_0
#define PMC_IMPL_FMON_FAULT_ACTION_PMC_CK_0                     _MK_ADDR_CONST(0x838)
#define PMC_IMPL_FMON_FAULT_ACTION_PMC_CK_0_SECURE                      0x0
#define PMC_IMPL_FMON_FAULT_ACTION_PMC_CK_0_DUAL                        0x0
#define PMC_IMPL_FMON_FAULT_ACTION_PMC_CK_0_SCR                         PMC_CK_SCR_0
#define PMC_IMPL_FMON_FAULT_ACTION_PMC_CK_0_WORD_COUNT                  0x1
#define PMC_IMPL_FMON_FAULT_ACTION_PMC_CK_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_FMON_FAULT_ACTION_PMC_CK_0_RESET_MASK                  _MK_MASK_CONST(0x7)
#define PMC_IMPL_FMON_FAULT_ACTION_PMC_CK_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_FMON_FAULT_ACTION_PMC_CK_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_FMON_FAULT_ACTION_PMC_CK_0_READ_MASK                   _MK_MASK_CONST(0x7)
#define PMC_IMPL_FMON_FAULT_ACTION_PMC_CK_0_WRITE_MASK                  _MK_MASK_CONST(0x7)
#define PMC_IMPL_FMON_FAULT_ACTION_PMC_CK_0_FMON_ACTION_DC_RESET_REQ_PMC_CK_SHIFT                       _MK_SHIFT_CONST(2)
#define PMC_IMPL_FMON_FAULT_ACTION_PMC_CK_0_FMON_ACTION_DC_RESET_REQ_PMC_CK_FIELD                       _MK_FIELD_CONST(0x1, PMC_IMPL_FMON_FAULT_ACTION_PMC_CK_0_FMON_ACTION_DC_RESET_REQ_PMC_CK_SHIFT)
#define PMC_IMPL_FMON_FAULT_ACTION_PMC_CK_0_FMON_ACTION_DC_RESET_REQ_PMC_CK_RANGE                       2:2
#define PMC_IMPL_FMON_FAULT_ACTION_PMC_CK_0_FMON_ACTION_DC_RESET_REQ_PMC_CK_WOFFSET                     0x0
#define PMC_IMPL_FMON_FAULT_ACTION_PMC_CK_0_FMON_ACTION_DC_RESET_REQ_PMC_CK_DEFAULT                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_FMON_FAULT_ACTION_PMC_CK_0_FMON_ACTION_DC_RESET_REQ_PMC_CK_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define PMC_IMPL_FMON_FAULT_ACTION_PMC_CK_0_FMON_ACTION_DC_RESET_REQ_PMC_CK_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define PMC_IMPL_FMON_FAULT_ACTION_PMC_CK_0_FMON_ACTION_DC_RESET_REQ_PMC_CK_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_FMON_FAULT_ACTION_PMC_CK_0_FMON_ACTION_DC_RESET_REQ_PMC_CK_PARITY_PROTECTION                   _MK_MASK_CONST(0x1)
#define PMC_IMPL_FMON_FAULT_ACTION_PMC_CK_0_FMON_ACTION_DC_RESET_REQ_PMC_CK_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define PMC_IMPL_FMON_FAULT_ACTION_PMC_CK_0_FMON_ACTION_DC_RESET_REQ_PMC_CK_INIT_ENUM                   DISABLE
#define PMC_IMPL_FMON_FAULT_ACTION_PMC_CK_0_FMON_ACTION_DC_RESET_REQ_PMC_CK_DISABLE                     _MK_ENUM_CONST(0)
#define PMC_IMPL_FMON_FAULT_ACTION_PMC_CK_0_FMON_ACTION_DC_RESET_REQ_PMC_CK_ENABLE                      _MK_ENUM_CONST(1)

#define PMC_IMPL_FMON_FAULT_ACTION_PMC_CK_0_FMON_ACTION_FAULT_REPORT_PMC_CK_SHIFT                       _MK_SHIFT_CONST(1)
#define PMC_IMPL_FMON_FAULT_ACTION_PMC_CK_0_FMON_ACTION_FAULT_REPORT_PMC_CK_FIELD                       _MK_FIELD_CONST(0x1, PMC_IMPL_FMON_FAULT_ACTION_PMC_CK_0_FMON_ACTION_FAULT_REPORT_PMC_CK_SHIFT)
#define PMC_IMPL_FMON_FAULT_ACTION_PMC_CK_0_FMON_ACTION_FAULT_REPORT_PMC_CK_RANGE                       1:1
#define PMC_IMPL_FMON_FAULT_ACTION_PMC_CK_0_FMON_ACTION_FAULT_REPORT_PMC_CK_WOFFSET                     0x0
#define PMC_IMPL_FMON_FAULT_ACTION_PMC_CK_0_FMON_ACTION_FAULT_REPORT_PMC_CK_DEFAULT                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_FMON_FAULT_ACTION_PMC_CK_0_FMON_ACTION_FAULT_REPORT_PMC_CK_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define PMC_IMPL_FMON_FAULT_ACTION_PMC_CK_0_FMON_ACTION_FAULT_REPORT_PMC_CK_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define PMC_IMPL_FMON_FAULT_ACTION_PMC_CK_0_FMON_ACTION_FAULT_REPORT_PMC_CK_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_FMON_FAULT_ACTION_PMC_CK_0_FMON_ACTION_FAULT_REPORT_PMC_CK_PARITY_PROTECTION                   _MK_MASK_CONST(0x1)
#define PMC_IMPL_FMON_FAULT_ACTION_PMC_CK_0_FMON_ACTION_FAULT_REPORT_PMC_CK_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define PMC_IMPL_FMON_FAULT_ACTION_PMC_CK_0_FMON_ACTION_FAULT_REPORT_PMC_CK_INIT_ENUM                   DISABLE
#define PMC_IMPL_FMON_FAULT_ACTION_PMC_CK_0_FMON_ACTION_FAULT_REPORT_PMC_CK_DISABLE                     _MK_ENUM_CONST(0)
#define PMC_IMPL_FMON_FAULT_ACTION_PMC_CK_0_FMON_ACTION_FAULT_REPORT_PMC_CK_ENABLE                      _MK_ENUM_CONST(1)

#define PMC_IMPL_FMON_FAULT_ACTION_PMC_CK_0_FMON_ACTION_RESET_REQ_PMC_CK_SHIFT                  _MK_SHIFT_CONST(0)
#define PMC_IMPL_FMON_FAULT_ACTION_PMC_CK_0_FMON_ACTION_RESET_REQ_PMC_CK_FIELD                  _MK_FIELD_CONST(0x1, PMC_IMPL_FMON_FAULT_ACTION_PMC_CK_0_FMON_ACTION_RESET_REQ_PMC_CK_SHIFT)
#define PMC_IMPL_FMON_FAULT_ACTION_PMC_CK_0_FMON_ACTION_RESET_REQ_PMC_CK_RANGE                  0:0
#define PMC_IMPL_FMON_FAULT_ACTION_PMC_CK_0_FMON_ACTION_RESET_REQ_PMC_CK_WOFFSET                        0x0
#define PMC_IMPL_FMON_FAULT_ACTION_PMC_CK_0_FMON_ACTION_RESET_REQ_PMC_CK_DEFAULT                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_FMON_FAULT_ACTION_PMC_CK_0_FMON_ACTION_RESET_REQ_PMC_CK_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define PMC_IMPL_FMON_FAULT_ACTION_PMC_CK_0_FMON_ACTION_RESET_REQ_PMC_CK_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_FMON_FAULT_ACTION_PMC_CK_0_FMON_ACTION_RESET_REQ_PMC_CK_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_FMON_FAULT_ACTION_PMC_CK_0_FMON_ACTION_RESET_REQ_PMC_CK_PARITY_PROTECTION                      _MK_MASK_CONST(0x1)
#define PMC_IMPL_FMON_FAULT_ACTION_PMC_CK_0_FMON_ACTION_RESET_REQ_PMC_CK_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define PMC_IMPL_FMON_FAULT_ACTION_PMC_CK_0_FMON_ACTION_RESET_REQ_PMC_CK_INIT_ENUM                      DISABLE
#define PMC_IMPL_FMON_FAULT_ACTION_PMC_CK_0_FMON_ACTION_RESET_REQ_PMC_CK_DISABLE                        _MK_ENUM_CONST(0)
#define PMC_IMPL_FMON_FAULT_ACTION_PMC_CK_0_FMON_ACTION_RESET_REQ_PMC_CK_ENABLE                 _MK_ENUM_CONST(1)


// Register PMC_IMPL_FMON_CONFIG_PMC_CK_0
#define PMC_IMPL_FMON_CONFIG_PMC_CK_0                   _MK_ADDR_CONST(0x83c)
#define PMC_IMPL_FMON_CONFIG_PMC_CK_0_SECURE                    0x0
#define PMC_IMPL_FMON_CONFIG_PMC_CK_0_DUAL                      0x0
#define PMC_IMPL_FMON_CONFIG_PMC_CK_0_SCR                       PMC_CK_SCR_0
#define PMC_IMPL_FMON_CONFIG_PMC_CK_0_WORD_COUNT                        0x1
#define PMC_IMPL_FMON_CONFIG_PMC_CK_0_RESET_VAL                         _MK_MASK_CONST(0x7f)
#define PMC_IMPL_FMON_CONFIG_PMC_CK_0_RESET_MASK                        _MK_MASK_CONST(0x7f)
#define PMC_IMPL_FMON_CONFIG_PMC_CK_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define PMC_IMPL_FMON_CONFIG_PMC_CK_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_FMON_CONFIG_PMC_CK_0_READ_MASK                         _MK_MASK_CONST(0x7f)
#define PMC_IMPL_FMON_CONFIG_PMC_CK_0_WRITE_MASK                        _MK_MASK_CONST(0x7f)
#define PMC_IMPL_FMON_CONFIG_PMC_CK_0_FMON_REPORT_DC_FAULT_VIOL_PMC_CK_SHIFT                    _MK_SHIFT_CONST(6)
#define PMC_IMPL_FMON_CONFIG_PMC_CK_0_FMON_REPORT_DC_FAULT_VIOL_PMC_CK_FIELD                    _MK_FIELD_CONST(0x1, PMC_IMPL_FMON_CONFIG_PMC_CK_0_FMON_REPORT_DC_FAULT_VIOL_PMC_CK_SHIFT)
#define PMC_IMPL_FMON_CONFIG_PMC_CK_0_FMON_REPORT_DC_FAULT_VIOL_PMC_CK_RANGE                    6:6
#define PMC_IMPL_FMON_CONFIG_PMC_CK_0_FMON_REPORT_DC_FAULT_VIOL_PMC_CK_WOFFSET                  0x0
#define PMC_IMPL_FMON_CONFIG_PMC_CK_0_FMON_REPORT_DC_FAULT_VIOL_PMC_CK_DEFAULT                  _MK_MASK_CONST(0x1)
#define PMC_IMPL_FMON_CONFIG_PMC_CK_0_FMON_REPORT_DC_FAULT_VIOL_PMC_CK_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define PMC_IMPL_FMON_CONFIG_PMC_CK_0_FMON_REPORT_DC_FAULT_VIOL_PMC_CK_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define PMC_IMPL_FMON_CONFIG_PMC_CK_0_FMON_REPORT_DC_FAULT_VIOL_PMC_CK_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define PMC_IMPL_FMON_CONFIG_PMC_CK_0_FMON_REPORT_DC_FAULT_VIOL_PMC_CK_PARITY_PROTECTION                        _MK_MASK_CONST(0x1)
#define PMC_IMPL_FMON_CONFIG_PMC_CK_0_FMON_REPORT_DC_FAULT_VIOL_PMC_CK_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)
#define PMC_IMPL_FMON_CONFIG_PMC_CK_0_FMON_REPORT_DC_FAULT_VIOL_PMC_CK_INIT_ENUM                        ENABLE
#define PMC_IMPL_FMON_CONFIG_PMC_CK_0_FMON_REPORT_DC_FAULT_VIOL_PMC_CK_DISABLE                  _MK_ENUM_CONST(0)
#define PMC_IMPL_FMON_CONFIG_PMC_CK_0_FMON_REPORT_DC_FAULT_VIOL_PMC_CK_ENABLE                   _MK_ENUM_CONST(1)

#define PMC_IMPL_FMON_CONFIG_PMC_CK_0_FMON_REPORT_HIGH_THRESH_VIOL_PMC_CK_SHIFT                 _MK_SHIFT_CONST(5)
#define PMC_IMPL_FMON_CONFIG_PMC_CK_0_FMON_REPORT_HIGH_THRESH_VIOL_PMC_CK_FIELD                 _MK_FIELD_CONST(0x1, PMC_IMPL_FMON_CONFIG_PMC_CK_0_FMON_REPORT_HIGH_THRESH_VIOL_PMC_CK_SHIFT)
#define PMC_IMPL_FMON_CONFIG_PMC_CK_0_FMON_REPORT_HIGH_THRESH_VIOL_PMC_CK_RANGE                 5:5
#define PMC_IMPL_FMON_CONFIG_PMC_CK_0_FMON_REPORT_HIGH_THRESH_VIOL_PMC_CK_WOFFSET                       0x0
#define PMC_IMPL_FMON_CONFIG_PMC_CK_0_FMON_REPORT_HIGH_THRESH_VIOL_PMC_CK_DEFAULT                       _MK_MASK_CONST(0x1)
#define PMC_IMPL_FMON_CONFIG_PMC_CK_0_FMON_REPORT_HIGH_THRESH_VIOL_PMC_CK_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define PMC_IMPL_FMON_CONFIG_PMC_CK_0_FMON_REPORT_HIGH_THRESH_VIOL_PMC_CK_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define PMC_IMPL_FMON_CONFIG_PMC_CK_0_FMON_REPORT_HIGH_THRESH_VIOL_PMC_CK_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define PMC_IMPL_FMON_CONFIG_PMC_CK_0_FMON_REPORT_HIGH_THRESH_VIOL_PMC_CK_PARITY_PROTECTION                     _MK_MASK_CONST(0x1)
#define PMC_IMPL_FMON_CONFIG_PMC_CK_0_FMON_REPORT_HIGH_THRESH_VIOL_PMC_CK_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)
#define PMC_IMPL_FMON_CONFIG_PMC_CK_0_FMON_REPORT_HIGH_THRESH_VIOL_PMC_CK_INIT_ENUM                     ENABLE
#define PMC_IMPL_FMON_CONFIG_PMC_CK_0_FMON_REPORT_HIGH_THRESH_VIOL_PMC_CK_DISABLE                       _MK_ENUM_CONST(0)
#define PMC_IMPL_FMON_CONFIG_PMC_CK_0_FMON_REPORT_HIGH_THRESH_VIOL_PMC_CK_ENABLE                        _MK_ENUM_CONST(1)

#define PMC_IMPL_FMON_CONFIG_PMC_CK_0_FMON_REPORT_LOW_THRESH_VIOL_PMC_CK_SHIFT                  _MK_SHIFT_CONST(4)
#define PMC_IMPL_FMON_CONFIG_PMC_CK_0_FMON_REPORT_LOW_THRESH_VIOL_PMC_CK_FIELD                  _MK_FIELD_CONST(0x1, PMC_IMPL_FMON_CONFIG_PMC_CK_0_FMON_REPORT_LOW_THRESH_VIOL_PMC_CK_SHIFT)
#define PMC_IMPL_FMON_CONFIG_PMC_CK_0_FMON_REPORT_LOW_THRESH_VIOL_PMC_CK_RANGE                  4:4
#define PMC_IMPL_FMON_CONFIG_PMC_CK_0_FMON_REPORT_LOW_THRESH_VIOL_PMC_CK_WOFFSET                        0x0
#define PMC_IMPL_FMON_CONFIG_PMC_CK_0_FMON_REPORT_LOW_THRESH_VIOL_PMC_CK_DEFAULT                        _MK_MASK_CONST(0x1)
#define PMC_IMPL_FMON_CONFIG_PMC_CK_0_FMON_REPORT_LOW_THRESH_VIOL_PMC_CK_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define PMC_IMPL_FMON_CONFIG_PMC_CK_0_FMON_REPORT_LOW_THRESH_VIOL_PMC_CK_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_FMON_CONFIG_PMC_CK_0_FMON_REPORT_LOW_THRESH_VIOL_PMC_CK_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_FMON_CONFIG_PMC_CK_0_FMON_REPORT_LOW_THRESH_VIOL_PMC_CK_PARITY_PROTECTION                      _MK_MASK_CONST(0x1)
#define PMC_IMPL_FMON_CONFIG_PMC_CK_0_FMON_REPORT_LOW_THRESH_VIOL_PMC_CK_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define PMC_IMPL_FMON_CONFIG_PMC_CK_0_FMON_REPORT_LOW_THRESH_VIOL_PMC_CK_INIT_ENUM                      ENABLE
#define PMC_IMPL_FMON_CONFIG_PMC_CK_0_FMON_REPORT_LOW_THRESH_VIOL_PMC_CK_DISABLE                        _MK_ENUM_CONST(0)
#define PMC_IMPL_FMON_CONFIG_PMC_CK_0_FMON_REPORT_LOW_THRESH_VIOL_PMC_CK_ENABLE                 _MK_ENUM_CONST(1)

#define PMC_IMPL_FMON_CONFIG_PMC_CK_0_FMON_REPORT_OVERFLOW_ERROR_PMC_CK_SHIFT                   _MK_SHIFT_CONST(3)
#define PMC_IMPL_FMON_CONFIG_PMC_CK_0_FMON_REPORT_OVERFLOW_ERROR_PMC_CK_FIELD                   _MK_FIELD_CONST(0x1, PMC_IMPL_FMON_CONFIG_PMC_CK_0_FMON_REPORT_OVERFLOW_ERROR_PMC_CK_SHIFT)
#define PMC_IMPL_FMON_CONFIG_PMC_CK_0_FMON_REPORT_OVERFLOW_ERROR_PMC_CK_RANGE                   3:3
#define PMC_IMPL_FMON_CONFIG_PMC_CK_0_FMON_REPORT_OVERFLOW_ERROR_PMC_CK_WOFFSET                 0x0
#define PMC_IMPL_FMON_CONFIG_PMC_CK_0_FMON_REPORT_OVERFLOW_ERROR_PMC_CK_DEFAULT                 _MK_MASK_CONST(0x1)
#define PMC_IMPL_FMON_CONFIG_PMC_CK_0_FMON_REPORT_OVERFLOW_ERROR_PMC_CK_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define PMC_IMPL_FMON_CONFIG_PMC_CK_0_FMON_REPORT_OVERFLOW_ERROR_PMC_CK_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_FMON_CONFIG_PMC_CK_0_FMON_REPORT_OVERFLOW_ERROR_PMC_CK_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define PMC_IMPL_FMON_CONFIG_PMC_CK_0_FMON_REPORT_OVERFLOW_ERROR_PMC_CK_PARITY_PROTECTION                       _MK_MASK_CONST(0x1)
#define PMC_IMPL_FMON_CONFIG_PMC_CK_0_FMON_REPORT_OVERFLOW_ERROR_PMC_CK_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define PMC_IMPL_FMON_CONFIG_PMC_CK_0_FMON_REPORT_OVERFLOW_ERROR_PMC_CK_INIT_ENUM                       ENABLE
#define PMC_IMPL_FMON_CONFIG_PMC_CK_0_FMON_REPORT_OVERFLOW_ERROR_PMC_CK_DISABLE                 _MK_ENUM_CONST(0)
#define PMC_IMPL_FMON_CONFIG_PMC_CK_0_FMON_REPORT_OVERFLOW_ERROR_PMC_CK_ENABLE                  _MK_ENUM_CONST(1)

#define PMC_IMPL_FMON_CONFIG_PMC_CK_0_FMON_REF_CLK_WINDOW_EN_PMC_CK_SHIFT                       _MK_SHIFT_CONST(2)
#define PMC_IMPL_FMON_CONFIG_PMC_CK_0_FMON_REF_CLK_WINDOW_EN_PMC_CK_FIELD                       _MK_FIELD_CONST(0x1, PMC_IMPL_FMON_CONFIG_PMC_CK_0_FMON_REF_CLK_WINDOW_EN_PMC_CK_SHIFT)
#define PMC_IMPL_FMON_CONFIG_PMC_CK_0_FMON_REF_CLK_WINDOW_EN_PMC_CK_RANGE                       2:2
#define PMC_IMPL_FMON_CONFIG_PMC_CK_0_FMON_REF_CLK_WINDOW_EN_PMC_CK_WOFFSET                     0x0
#define PMC_IMPL_FMON_CONFIG_PMC_CK_0_FMON_REF_CLK_WINDOW_EN_PMC_CK_DEFAULT                     _MK_MASK_CONST(0x1)
#define PMC_IMPL_FMON_CONFIG_PMC_CK_0_FMON_REF_CLK_WINDOW_EN_PMC_CK_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define PMC_IMPL_FMON_CONFIG_PMC_CK_0_FMON_REF_CLK_WINDOW_EN_PMC_CK_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define PMC_IMPL_FMON_CONFIG_PMC_CK_0_FMON_REF_CLK_WINDOW_EN_PMC_CK_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_FMON_CONFIG_PMC_CK_0_FMON_REF_CLK_WINDOW_EN_PMC_CK_PARITY_PROTECTION                   _MK_MASK_CONST(0x1)
#define PMC_IMPL_FMON_CONFIG_PMC_CK_0_FMON_REF_CLK_WINDOW_EN_PMC_CK_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define PMC_IMPL_FMON_CONFIG_PMC_CK_0_FMON_REF_CLK_WINDOW_EN_PMC_CK_INIT_ENUM                   ENABLE
#define PMC_IMPL_FMON_CONFIG_PMC_CK_0_FMON_REF_CLK_WINDOW_EN_PMC_CK_DISABLE                     _MK_ENUM_CONST(0)
#define PMC_IMPL_FMON_CONFIG_PMC_CK_0_FMON_REF_CLK_WINDOW_EN_PMC_CK_ENABLE                      _MK_ENUM_CONST(1)

#define PMC_IMPL_FMON_CONFIG_PMC_CK_0_FMON_ENABLE_FMON_COUNTER_PMC_CK_SHIFT                     _MK_SHIFT_CONST(1)
#define PMC_IMPL_FMON_CONFIG_PMC_CK_0_FMON_ENABLE_FMON_COUNTER_PMC_CK_FIELD                     _MK_FIELD_CONST(0x1, PMC_IMPL_FMON_CONFIG_PMC_CK_0_FMON_ENABLE_FMON_COUNTER_PMC_CK_SHIFT)
#define PMC_IMPL_FMON_CONFIG_PMC_CK_0_FMON_ENABLE_FMON_COUNTER_PMC_CK_RANGE                     1:1
#define PMC_IMPL_FMON_CONFIG_PMC_CK_0_FMON_ENABLE_FMON_COUNTER_PMC_CK_WOFFSET                   0x0
#define PMC_IMPL_FMON_CONFIG_PMC_CK_0_FMON_ENABLE_FMON_COUNTER_PMC_CK_DEFAULT                   _MK_MASK_CONST(0x1)
#define PMC_IMPL_FMON_CONFIG_PMC_CK_0_FMON_ENABLE_FMON_COUNTER_PMC_CK_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define PMC_IMPL_FMON_CONFIG_PMC_CK_0_FMON_ENABLE_FMON_COUNTER_PMC_CK_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_FMON_CONFIG_PMC_CK_0_FMON_ENABLE_FMON_COUNTER_PMC_CK_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_FMON_CONFIG_PMC_CK_0_FMON_ENABLE_FMON_COUNTER_PMC_CK_PARITY_PROTECTION                 _MK_MASK_CONST(0x1)
#define PMC_IMPL_FMON_CONFIG_PMC_CK_0_FMON_ENABLE_FMON_COUNTER_PMC_CK_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define PMC_IMPL_FMON_CONFIG_PMC_CK_0_FMON_ENABLE_FMON_COUNTER_PMC_CK_INIT_ENUM                 ENABLE
#define PMC_IMPL_FMON_CONFIG_PMC_CK_0_FMON_ENABLE_FMON_COUNTER_PMC_CK_DISABLE                   _MK_ENUM_CONST(0)
#define PMC_IMPL_FMON_CONFIG_PMC_CK_0_FMON_ENABLE_FMON_COUNTER_PMC_CK_ENABLE                    _MK_ENUM_CONST(1)

#define PMC_IMPL_FMON_CONFIG_PMC_CK_0_FMON_ENABLE_PMC_CK_SHIFT                  _MK_SHIFT_CONST(0)
#define PMC_IMPL_FMON_CONFIG_PMC_CK_0_FMON_ENABLE_PMC_CK_FIELD                  _MK_FIELD_CONST(0x1, PMC_IMPL_FMON_CONFIG_PMC_CK_0_FMON_ENABLE_PMC_CK_SHIFT)
#define PMC_IMPL_FMON_CONFIG_PMC_CK_0_FMON_ENABLE_PMC_CK_RANGE                  0:0
#define PMC_IMPL_FMON_CONFIG_PMC_CK_0_FMON_ENABLE_PMC_CK_WOFFSET                        0x0
#define PMC_IMPL_FMON_CONFIG_PMC_CK_0_FMON_ENABLE_PMC_CK_DEFAULT                        _MK_MASK_CONST(0x1)
#define PMC_IMPL_FMON_CONFIG_PMC_CK_0_FMON_ENABLE_PMC_CK_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define PMC_IMPL_FMON_CONFIG_PMC_CK_0_FMON_ENABLE_PMC_CK_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_FMON_CONFIG_PMC_CK_0_FMON_ENABLE_PMC_CK_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_FMON_CONFIG_PMC_CK_0_FMON_ENABLE_PMC_CK_PARITY_PROTECTION                      _MK_MASK_CONST(0x1)
#define PMC_IMPL_FMON_CONFIG_PMC_CK_0_FMON_ENABLE_PMC_CK_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define PMC_IMPL_FMON_CONFIG_PMC_CK_0_FMON_ENABLE_PMC_CK_INIT_ENUM                      ENABLE
#define PMC_IMPL_FMON_CONFIG_PMC_CK_0_FMON_ENABLE_PMC_CK_DISABLE                        _MK_ENUM_CONST(0)
#define PMC_IMPL_FMON_CONFIG_PMC_CK_0_FMON_ENABLE_PMC_CK_ENABLE                 _MK_ENUM_CONST(1)


// Register PMC_IMPL_FMON_ENABLE_STATUS_PMC_CK_0
#define PMC_IMPL_FMON_ENABLE_STATUS_PMC_CK_0                    _MK_ADDR_CONST(0x840)
#define PMC_IMPL_FMON_ENABLE_STATUS_PMC_CK_0_SECURE                     0x0
#define PMC_IMPL_FMON_ENABLE_STATUS_PMC_CK_0_DUAL                       0x0
#define PMC_IMPL_FMON_ENABLE_STATUS_PMC_CK_0_SCR                        PMC_CK_SCR_0
#define PMC_IMPL_FMON_ENABLE_STATUS_PMC_CK_0_WORD_COUNT                         0x1
#define PMC_IMPL_FMON_ENABLE_STATUS_PMC_CK_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define PMC_IMPL_FMON_ENABLE_STATUS_PMC_CK_0_RESET_MASK                         _MK_MASK_CONST(0x7)
#define PMC_IMPL_FMON_ENABLE_STATUS_PMC_CK_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_FMON_ENABLE_STATUS_PMC_CK_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define PMC_IMPL_FMON_ENABLE_STATUS_PMC_CK_0_READ_MASK                  _MK_MASK_CONST(0x7)
#define PMC_IMPL_FMON_ENABLE_STATUS_PMC_CK_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
#define PMC_IMPL_FMON_ENABLE_STATUS_PMC_CK_0_FMON_ENABLE_FMON_CLK_STATUS_PMC_CK_SHIFT                   _MK_SHIFT_CONST(2)
#define PMC_IMPL_FMON_ENABLE_STATUS_PMC_CK_0_FMON_ENABLE_FMON_CLK_STATUS_PMC_CK_FIELD                   _MK_FIELD_CONST(0x1, PMC_IMPL_FMON_ENABLE_STATUS_PMC_CK_0_FMON_ENABLE_FMON_CLK_STATUS_PMC_CK_SHIFT)
#define PMC_IMPL_FMON_ENABLE_STATUS_PMC_CK_0_FMON_ENABLE_FMON_CLK_STATUS_PMC_CK_RANGE                   2:2
#define PMC_IMPL_FMON_ENABLE_STATUS_PMC_CK_0_FMON_ENABLE_FMON_CLK_STATUS_PMC_CK_WOFFSET                 0x0
#define PMC_IMPL_FMON_ENABLE_STATUS_PMC_CK_0_FMON_ENABLE_FMON_CLK_STATUS_PMC_CK_DEFAULT                 _MK_MASK_CONST(0x0)
#define PMC_IMPL_FMON_ENABLE_STATUS_PMC_CK_0_FMON_ENABLE_FMON_CLK_STATUS_PMC_CK_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define PMC_IMPL_FMON_ENABLE_STATUS_PMC_CK_0_FMON_ENABLE_FMON_CLK_STATUS_PMC_CK_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_FMON_ENABLE_STATUS_PMC_CK_0_FMON_ENABLE_FMON_CLK_STATUS_PMC_CK_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define PMC_IMPL_FMON_ENABLE_STATUS_PMC_CK_0_FMON_ENABLE_FMON_CLK_STATUS_PMC_CK_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define PMC_IMPL_FMON_ENABLE_STATUS_PMC_CK_0_FMON_ENABLE_FMON_CLK_STATUS_PMC_CK_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define PMC_IMPL_FMON_ENABLE_STATUS_PMC_CK_0_FMON_ENABLE_FMON_CLK_STATUS_PMC_CK_INIT_ENUM                       FALSE
#define PMC_IMPL_FMON_ENABLE_STATUS_PMC_CK_0_FMON_ENABLE_FMON_CLK_STATUS_PMC_CK_FALSE                   _MK_ENUM_CONST(0)
#define PMC_IMPL_FMON_ENABLE_STATUS_PMC_CK_0_FMON_ENABLE_FMON_CLK_STATUS_PMC_CK_TRUE                    _MK_ENUM_CONST(1)

#define PMC_IMPL_FMON_ENABLE_STATUS_PMC_CK_0_FMON_ENABLE_FMON_ERR_CLK_STATUS_PMC_CK_SHIFT                       _MK_SHIFT_CONST(1)
#define PMC_IMPL_FMON_ENABLE_STATUS_PMC_CK_0_FMON_ENABLE_FMON_ERR_CLK_STATUS_PMC_CK_FIELD                       _MK_FIELD_CONST(0x1, PMC_IMPL_FMON_ENABLE_STATUS_PMC_CK_0_FMON_ENABLE_FMON_ERR_CLK_STATUS_PMC_CK_SHIFT)
#define PMC_IMPL_FMON_ENABLE_STATUS_PMC_CK_0_FMON_ENABLE_FMON_ERR_CLK_STATUS_PMC_CK_RANGE                       1:1
#define PMC_IMPL_FMON_ENABLE_STATUS_PMC_CK_0_FMON_ENABLE_FMON_ERR_CLK_STATUS_PMC_CK_WOFFSET                     0x0
#define PMC_IMPL_FMON_ENABLE_STATUS_PMC_CK_0_FMON_ENABLE_FMON_ERR_CLK_STATUS_PMC_CK_DEFAULT                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_FMON_ENABLE_STATUS_PMC_CK_0_FMON_ENABLE_FMON_ERR_CLK_STATUS_PMC_CK_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define PMC_IMPL_FMON_ENABLE_STATUS_PMC_CK_0_FMON_ENABLE_FMON_ERR_CLK_STATUS_PMC_CK_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define PMC_IMPL_FMON_ENABLE_STATUS_PMC_CK_0_FMON_ENABLE_FMON_ERR_CLK_STATUS_PMC_CK_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_FMON_ENABLE_STATUS_PMC_CK_0_FMON_ENABLE_FMON_ERR_CLK_STATUS_PMC_CK_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_FMON_ENABLE_STATUS_PMC_CK_0_FMON_ENABLE_FMON_ERR_CLK_STATUS_PMC_CK_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define PMC_IMPL_FMON_ENABLE_STATUS_PMC_CK_0_FMON_ENABLE_FMON_ERR_CLK_STATUS_PMC_CK_INIT_ENUM                   FALSE
#define PMC_IMPL_FMON_ENABLE_STATUS_PMC_CK_0_FMON_ENABLE_FMON_ERR_CLK_STATUS_PMC_CK_FALSE                       _MK_ENUM_CONST(0)
#define PMC_IMPL_FMON_ENABLE_STATUS_PMC_CK_0_FMON_ENABLE_FMON_ERR_CLK_STATUS_PMC_CK_TRUE                        _MK_ENUM_CONST(1)

#define PMC_IMPL_FMON_ENABLE_STATUS_PMC_CK_0_FMON_ENABLE_FMON_REF_CLK_STATUS_PMC_CK_SHIFT                       _MK_SHIFT_CONST(0)
#define PMC_IMPL_FMON_ENABLE_STATUS_PMC_CK_0_FMON_ENABLE_FMON_REF_CLK_STATUS_PMC_CK_FIELD                       _MK_FIELD_CONST(0x1, PMC_IMPL_FMON_ENABLE_STATUS_PMC_CK_0_FMON_ENABLE_FMON_REF_CLK_STATUS_PMC_CK_SHIFT)
#define PMC_IMPL_FMON_ENABLE_STATUS_PMC_CK_0_FMON_ENABLE_FMON_REF_CLK_STATUS_PMC_CK_RANGE                       0:0
#define PMC_IMPL_FMON_ENABLE_STATUS_PMC_CK_0_FMON_ENABLE_FMON_REF_CLK_STATUS_PMC_CK_WOFFSET                     0x0
#define PMC_IMPL_FMON_ENABLE_STATUS_PMC_CK_0_FMON_ENABLE_FMON_REF_CLK_STATUS_PMC_CK_DEFAULT                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_FMON_ENABLE_STATUS_PMC_CK_0_FMON_ENABLE_FMON_REF_CLK_STATUS_PMC_CK_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define PMC_IMPL_FMON_ENABLE_STATUS_PMC_CK_0_FMON_ENABLE_FMON_REF_CLK_STATUS_PMC_CK_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define PMC_IMPL_FMON_ENABLE_STATUS_PMC_CK_0_FMON_ENABLE_FMON_REF_CLK_STATUS_PMC_CK_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_FMON_ENABLE_STATUS_PMC_CK_0_FMON_ENABLE_FMON_REF_CLK_STATUS_PMC_CK_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_FMON_ENABLE_STATUS_PMC_CK_0_FMON_ENABLE_FMON_REF_CLK_STATUS_PMC_CK_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define PMC_IMPL_FMON_ENABLE_STATUS_PMC_CK_0_FMON_ENABLE_FMON_REF_CLK_STATUS_PMC_CK_INIT_ENUM                   FALSE
#define PMC_IMPL_FMON_ENABLE_STATUS_PMC_CK_0_FMON_ENABLE_FMON_REF_CLK_STATUS_PMC_CK_FALSE                       _MK_ENUM_CONST(0)
#define PMC_IMPL_FMON_ENABLE_STATUS_PMC_CK_0_FMON_ENABLE_FMON_REF_CLK_STATUS_PMC_CK_TRUE                        _MK_ENUM_CONST(1)


// Register PMC_IMPL_FMON_FAULT_STATUS_PMC_CK_0
#define PMC_IMPL_FMON_FAULT_STATUS_PMC_CK_0                     _MK_ADDR_CONST(0x844)
#define PMC_IMPL_FMON_FAULT_STATUS_PMC_CK_0_SECURE                      0x0
#define PMC_IMPL_FMON_FAULT_STATUS_PMC_CK_0_DUAL                        0x0
#define PMC_IMPL_FMON_FAULT_STATUS_PMC_CK_0_SCR                         PMC_CK_SCR_0
#define PMC_IMPL_FMON_FAULT_STATUS_PMC_CK_0_WORD_COUNT                  0x1
#define PMC_IMPL_FMON_FAULT_STATUS_PMC_CK_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_FMON_FAULT_STATUS_PMC_CK_0_RESET_MASK                  _MK_MASK_CONST(0x8000001f)
#define PMC_IMPL_FMON_FAULT_STATUS_PMC_CK_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_FMON_FAULT_STATUS_PMC_CK_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_FMON_FAULT_STATUS_PMC_CK_0_READ_MASK                   _MK_MASK_CONST(0x8000001f)
#define PMC_IMPL_FMON_FAULT_STATUS_PMC_CK_0_WRITE_MASK                  _MK_MASK_CONST(0x80000000)
#define PMC_IMPL_FMON_FAULT_STATUS_PMC_CK_0_FMON_FAULT_CLEAR_PMC_CK_SHIFT                       _MK_SHIFT_CONST(31)
#define PMC_IMPL_FMON_FAULT_STATUS_PMC_CK_0_FMON_FAULT_CLEAR_PMC_CK_FIELD                       _MK_FIELD_CONST(0x1, PMC_IMPL_FMON_FAULT_STATUS_PMC_CK_0_FMON_FAULT_CLEAR_PMC_CK_SHIFT)
#define PMC_IMPL_FMON_FAULT_STATUS_PMC_CK_0_FMON_FAULT_CLEAR_PMC_CK_RANGE                       31:31
#define PMC_IMPL_FMON_FAULT_STATUS_PMC_CK_0_FMON_FAULT_CLEAR_PMC_CK_WOFFSET                     0x0
#define PMC_IMPL_FMON_FAULT_STATUS_PMC_CK_0_FMON_FAULT_CLEAR_PMC_CK_DEFAULT                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_FMON_FAULT_STATUS_PMC_CK_0_FMON_FAULT_CLEAR_PMC_CK_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define PMC_IMPL_FMON_FAULT_STATUS_PMC_CK_0_FMON_FAULT_CLEAR_PMC_CK_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define PMC_IMPL_FMON_FAULT_STATUS_PMC_CK_0_FMON_FAULT_CLEAR_PMC_CK_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_FMON_FAULT_STATUS_PMC_CK_0_FMON_FAULT_CLEAR_PMC_CK_PARITY_PROTECTION                   _MK_MASK_CONST(0x1)
#define PMC_IMPL_FMON_FAULT_STATUS_PMC_CK_0_FMON_FAULT_CLEAR_PMC_CK_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define PMC_IMPL_FMON_FAULT_STATUS_PMC_CK_0_FMON_FAULT_CLEAR_PMC_CK_INIT_ENUM                   FALSE
#define PMC_IMPL_FMON_FAULT_STATUS_PMC_CK_0_FMON_FAULT_CLEAR_PMC_CK_FALSE                       _MK_ENUM_CONST(0)
#define PMC_IMPL_FMON_FAULT_STATUS_PMC_CK_0_FMON_FAULT_CLEAR_PMC_CK_TRUE                        _MK_ENUM_CONST(1)

#define PMC_IMPL_FMON_FAULT_STATUS_PMC_CK_0_FMON_FAULT_OUT_STATUS_PMC_CK_SHIFT                  _MK_SHIFT_CONST(4)
#define PMC_IMPL_FMON_FAULT_STATUS_PMC_CK_0_FMON_FAULT_OUT_STATUS_PMC_CK_FIELD                  _MK_FIELD_CONST(0x1, PMC_IMPL_FMON_FAULT_STATUS_PMC_CK_0_FMON_FAULT_OUT_STATUS_PMC_CK_SHIFT)
#define PMC_IMPL_FMON_FAULT_STATUS_PMC_CK_0_FMON_FAULT_OUT_STATUS_PMC_CK_RANGE                  4:4
#define PMC_IMPL_FMON_FAULT_STATUS_PMC_CK_0_FMON_FAULT_OUT_STATUS_PMC_CK_WOFFSET                        0x0
#define PMC_IMPL_FMON_FAULT_STATUS_PMC_CK_0_FMON_FAULT_OUT_STATUS_PMC_CK_DEFAULT                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_FMON_FAULT_STATUS_PMC_CK_0_FMON_FAULT_OUT_STATUS_PMC_CK_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define PMC_IMPL_FMON_FAULT_STATUS_PMC_CK_0_FMON_FAULT_OUT_STATUS_PMC_CK_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_FMON_FAULT_STATUS_PMC_CK_0_FMON_FAULT_OUT_STATUS_PMC_CK_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_FMON_FAULT_STATUS_PMC_CK_0_FMON_FAULT_OUT_STATUS_PMC_CK_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_FMON_FAULT_STATUS_PMC_CK_0_FMON_FAULT_OUT_STATUS_PMC_CK_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define PMC_IMPL_FMON_FAULT_STATUS_PMC_CK_0_FMON_FAULT_OUT_STATUS_PMC_CK_INIT_ENUM                      FALSE
#define PMC_IMPL_FMON_FAULT_STATUS_PMC_CK_0_FMON_FAULT_OUT_STATUS_PMC_CK_FALSE                  _MK_ENUM_CONST(0)
#define PMC_IMPL_FMON_FAULT_STATUS_PMC_CK_0_FMON_FAULT_OUT_STATUS_PMC_CK_TRUE                   _MK_ENUM_CONST(1)

#define PMC_IMPL_FMON_FAULT_STATUS_PMC_CK_0_FMON_OVERFLOW_ERROR_PMC_CK_SHIFT                    _MK_SHIFT_CONST(3)
#define PMC_IMPL_FMON_FAULT_STATUS_PMC_CK_0_FMON_OVERFLOW_ERROR_PMC_CK_FIELD                    _MK_FIELD_CONST(0x1, PMC_IMPL_FMON_FAULT_STATUS_PMC_CK_0_FMON_OVERFLOW_ERROR_PMC_CK_SHIFT)
#define PMC_IMPL_FMON_FAULT_STATUS_PMC_CK_0_FMON_OVERFLOW_ERROR_PMC_CK_RANGE                    3:3
#define PMC_IMPL_FMON_FAULT_STATUS_PMC_CK_0_FMON_OVERFLOW_ERROR_PMC_CK_WOFFSET                  0x0
#define PMC_IMPL_FMON_FAULT_STATUS_PMC_CK_0_FMON_OVERFLOW_ERROR_PMC_CK_DEFAULT                  _MK_MASK_CONST(0x0)
#define PMC_IMPL_FMON_FAULT_STATUS_PMC_CK_0_FMON_OVERFLOW_ERROR_PMC_CK_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define PMC_IMPL_FMON_FAULT_STATUS_PMC_CK_0_FMON_OVERFLOW_ERROR_PMC_CK_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define PMC_IMPL_FMON_FAULT_STATUS_PMC_CK_0_FMON_OVERFLOW_ERROR_PMC_CK_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define PMC_IMPL_FMON_FAULT_STATUS_PMC_CK_0_FMON_OVERFLOW_ERROR_PMC_CK_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_FMON_FAULT_STATUS_PMC_CK_0_FMON_OVERFLOW_ERROR_PMC_CK_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)
#define PMC_IMPL_FMON_FAULT_STATUS_PMC_CK_0_FMON_OVERFLOW_ERROR_PMC_CK_INIT_ENUM                        FALSE
#define PMC_IMPL_FMON_FAULT_STATUS_PMC_CK_0_FMON_OVERFLOW_ERROR_PMC_CK_FALSE                    _MK_ENUM_CONST(0)
#define PMC_IMPL_FMON_FAULT_STATUS_PMC_CK_0_FMON_OVERFLOW_ERROR_PMC_CK_TRUE                     _MK_ENUM_CONST(1)

#define PMC_IMPL_FMON_FAULT_STATUS_PMC_CK_0_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_PMC_CK_SHIFT                    _MK_SHIFT_CONST(2)
#define PMC_IMPL_FMON_FAULT_STATUS_PMC_CK_0_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_PMC_CK_FIELD                    _MK_FIELD_CONST(0x1, PMC_IMPL_FMON_FAULT_STATUS_PMC_CK_0_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_PMC_CK_SHIFT)
#define PMC_IMPL_FMON_FAULT_STATUS_PMC_CK_0_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_PMC_CK_RANGE                    2:2
#define PMC_IMPL_FMON_FAULT_STATUS_PMC_CK_0_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_PMC_CK_WOFFSET                  0x0
#define PMC_IMPL_FMON_FAULT_STATUS_PMC_CK_0_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_PMC_CK_DEFAULT                  _MK_MASK_CONST(0x0)
#define PMC_IMPL_FMON_FAULT_STATUS_PMC_CK_0_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_PMC_CK_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define PMC_IMPL_FMON_FAULT_STATUS_PMC_CK_0_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_PMC_CK_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define PMC_IMPL_FMON_FAULT_STATUS_PMC_CK_0_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_PMC_CK_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define PMC_IMPL_FMON_FAULT_STATUS_PMC_CK_0_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_PMC_CK_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_FMON_FAULT_STATUS_PMC_CK_0_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_PMC_CK_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)
#define PMC_IMPL_FMON_FAULT_STATUS_PMC_CK_0_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_PMC_CK_INIT_ENUM                        FALSE
#define PMC_IMPL_FMON_FAULT_STATUS_PMC_CK_0_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_PMC_CK_FALSE                    _MK_ENUM_CONST(0)
#define PMC_IMPL_FMON_FAULT_STATUS_PMC_CK_0_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_PMC_CK_TRUE                     _MK_ENUM_CONST(1)

#define PMC_IMPL_FMON_FAULT_STATUS_PMC_CK_0_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_PMC_CK_SHIFT                     _MK_SHIFT_CONST(1)
#define PMC_IMPL_FMON_FAULT_STATUS_PMC_CK_0_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_PMC_CK_FIELD                     _MK_FIELD_CONST(0x1, PMC_IMPL_FMON_FAULT_STATUS_PMC_CK_0_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_PMC_CK_SHIFT)
#define PMC_IMPL_FMON_FAULT_STATUS_PMC_CK_0_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_PMC_CK_RANGE                     1:1
#define PMC_IMPL_FMON_FAULT_STATUS_PMC_CK_0_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_PMC_CK_WOFFSET                   0x0
#define PMC_IMPL_FMON_FAULT_STATUS_PMC_CK_0_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_PMC_CK_DEFAULT                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_FMON_FAULT_STATUS_PMC_CK_0_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_PMC_CK_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define PMC_IMPL_FMON_FAULT_STATUS_PMC_CK_0_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_PMC_CK_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_FMON_FAULT_STATUS_PMC_CK_0_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_PMC_CK_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_FMON_FAULT_STATUS_PMC_CK_0_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_PMC_CK_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define PMC_IMPL_FMON_FAULT_STATUS_PMC_CK_0_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_PMC_CK_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define PMC_IMPL_FMON_FAULT_STATUS_PMC_CK_0_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_PMC_CK_INIT_ENUM                 FALSE
#define PMC_IMPL_FMON_FAULT_STATUS_PMC_CK_0_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_PMC_CK_FALSE                     _MK_ENUM_CONST(0)
#define PMC_IMPL_FMON_FAULT_STATUS_PMC_CK_0_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_PMC_CK_TRUE                      _MK_ENUM_CONST(1)

#define PMC_IMPL_FMON_FAULT_STATUS_PMC_CK_0_FMON_DC_FAULT_PMC_CK_SHIFT                  _MK_SHIFT_CONST(0)
#define PMC_IMPL_FMON_FAULT_STATUS_PMC_CK_0_FMON_DC_FAULT_PMC_CK_FIELD                  _MK_FIELD_CONST(0x1, PMC_IMPL_FMON_FAULT_STATUS_PMC_CK_0_FMON_DC_FAULT_PMC_CK_SHIFT)
#define PMC_IMPL_FMON_FAULT_STATUS_PMC_CK_0_FMON_DC_FAULT_PMC_CK_RANGE                  0:0
#define PMC_IMPL_FMON_FAULT_STATUS_PMC_CK_0_FMON_DC_FAULT_PMC_CK_WOFFSET                        0x0
#define PMC_IMPL_FMON_FAULT_STATUS_PMC_CK_0_FMON_DC_FAULT_PMC_CK_DEFAULT                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_FMON_FAULT_STATUS_PMC_CK_0_FMON_DC_FAULT_PMC_CK_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define PMC_IMPL_FMON_FAULT_STATUS_PMC_CK_0_FMON_DC_FAULT_PMC_CK_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_FMON_FAULT_STATUS_PMC_CK_0_FMON_DC_FAULT_PMC_CK_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_FMON_FAULT_STATUS_PMC_CK_0_FMON_DC_FAULT_PMC_CK_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_FMON_FAULT_STATUS_PMC_CK_0_FMON_DC_FAULT_PMC_CK_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define PMC_IMPL_FMON_FAULT_STATUS_PMC_CK_0_FMON_DC_FAULT_PMC_CK_INIT_ENUM                      FALSE
#define PMC_IMPL_FMON_FAULT_STATUS_PMC_CK_0_FMON_DC_FAULT_PMC_CK_FALSE                  _MK_ENUM_CONST(0)
#define PMC_IMPL_FMON_FAULT_STATUS_PMC_CK_0_FMON_DC_FAULT_PMC_CK_TRUE                   _MK_ENUM_CONST(1)


// Register PMC_IMPL_FMON_LOAD_DATA_CTRL_PMC_CK_0
#define PMC_IMPL_FMON_LOAD_DATA_CTRL_PMC_CK_0                   _MK_ADDR_CONST(0x848)
#define PMC_IMPL_FMON_LOAD_DATA_CTRL_PMC_CK_0_SECURE                    0x0
#define PMC_IMPL_FMON_LOAD_DATA_CTRL_PMC_CK_0_DUAL                      0x0
#define PMC_IMPL_FMON_LOAD_DATA_CTRL_PMC_CK_0_SCR                       PMC_CK_SCR_0
#define PMC_IMPL_FMON_LOAD_DATA_CTRL_PMC_CK_0_WORD_COUNT                        0x1
#define PMC_IMPL_FMON_LOAD_DATA_CTRL_PMC_CK_0_RESET_VAL                         _MK_MASK_CONST(0x0)
#define PMC_IMPL_FMON_LOAD_DATA_CTRL_PMC_CK_0_RESET_MASK                        _MK_MASK_CONST(0x80000007)
#define PMC_IMPL_FMON_LOAD_DATA_CTRL_PMC_CK_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define PMC_IMPL_FMON_LOAD_DATA_CTRL_PMC_CK_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_FMON_LOAD_DATA_CTRL_PMC_CK_0_READ_MASK                         _MK_MASK_CONST(0x80000007)
#define PMC_IMPL_FMON_LOAD_DATA_CTRL_PMC_CK_0_WRITE_MASK                        _MK_MASK_CONST(0x80000007)
#define PMC_IMPL_FMON_LOAD_DATA_CTRL_PMC_CK_0_FMON_LOAD_DATA_PMC_CK_SHIFT                       _MK_SHIFT_CONST(31)
#define PMC_IMPL_FMON_LOAD_DATA_CTRL_PMC_CK_0_FMON_LOAD_DATA_PMC_CK_FIELD                       _MK_FIELD_CONST(0x1, PMC_IMPL_FMON_LOAD_DATA_CTRL_PMC_CK_0_FMON_LOAD_DATA_PMC_CK_SHIFT)
#define PMC_IMPL_FMON_LOAD_DATA_CTRL_PMC_CK_0_FMON_LOAD_DATA_PMC_CK_RANGE                       31:31
#define PMC_IMPL_FMON_LOAD_DATA_CTRL_PMC_CK_0_FMON_LOAD_DATA_PMC_CK_WOFFSET                     0x0
#define PMC_IMPL_FMON_LOAD_DATA_CTRL_PMC_CK_0_FMON_LOAD_DATA_PMC_CK_DEFAULT                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_FMON_LOAD_DATA_CTRL_PMC_CK_0_FMON_LOAD_DATA_PMC_CK_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define PMC_IMPL_FMON_LOAD_DATA_CTRL_PMC_CK_0_FMON_LOAD_DATA_PMC_CK_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define PMC_IMPL_FMON_LOAD_DATA_CTRL_PMC_CK_0_FMON_LOAD_DATA_PMC_CK_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_FMON_LOAD_DATA_CTRL_PMC_CK_0_FMON_LOAD_DATA_PMC_CK_PARITY_PROTECTION                   _MK_MASK_CONST(0x1)
#define PMC_IMPL_FMON_LOAD_DATA_CTRL_PMC_CK_0_FMON_LOAD_DATA_PMC_CK_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define PMC_IMPL_FMON_LOAD_DATA_CTRL_PMC_CK_0_FMON_LOAD_DATA_PMC_CK_INIT_ENUM                   DISABLE
#define PMC_IMPL_FMON_LOAD_DATA_CTRL_PMC_CK_0_FMON_LOAD_DATA_PMC_CK_DISABLE                     _MK_ENUM_CONST(0)
#define PMC_IMPL_FMON_LOAD_DATA_CTRL_PMC_CK_0_FMON_LOAD_DATA_PMC_CK_ENABLE                      _MK_ENUM_CONST(1)

#define PMC_IMPL_FMON_LOAD_DATA_CTRL_PMC_CK_0_FMON_LOAD_DATA_SEL_PMC_CK_SHIFT                   _MK_SHIFT_CONST(0)
#define PMC_IMPL_FMON_LOAD_DATA_CTRL_PMC_CK_0_FMON_LOAD_DATA_SEL_PMC_CK_FIELD                   _MK_FIELD_CONST(0x7, PMC_IMPL_FMON_LOAD_DATA_CTRL_PMC_CK_0_FMON_LOAD_DATA_SEL_PMC_CK_SHIFT)
#define PMC_IMPL_FMON_LOAD_DATA_CTRL_PMC_CK_0_FMON_LOAD_DATA_SEL_PMC_CK_RANGE                   2:0
#define PMC_IMPL_FMON_LOAD_DATA_CTRL_PMC_CK_0_FMON_LOAD_DATA_SEL_PMC_CK_WOFFSET                 0x0
#define PMC_IMPL_FMON_LOAD_DATA_CTRL_PMC_CK_0_FMON_LOAD_DATA_SEL_PMC_CK_DEFAULT                 _MK_MASK_CONST(0x0)
#define PMC_IMPL_FMON_LOAD_DATA_CTRL_PMC_CK_0_FMON_LOAD_DATA_SEL_PMC_CK_DEFAULT_MASK                    _MK_MASK_CONST(0x7)
#define PMC_IMPL_FMON_LOAD_DATA_CTRL_PMC_CK_0_FMON_LOAD_DATA_SEL_PMC_CK_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_FMON_LOAD_DATA_CTRL_PMC_CK_0_FMON_LOAD_DATA_SEL_PMC_CK_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define PMC_IMPL_FMON_LOAD_DATA_CTRL_PMC_CK_0_FMON_LOAD_DATA_SEL_PMC_CK_PARITY_PROTECTION                       _MK_MASK_CONST(0x1)
#define PMC_IMPL_FMON_LOAD_DATA_CTRL_PMC_CK_0_FMON_LOAD_DATA_SEL_PMC_CK_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define PMC_IMPL_FMON_LOAD_DATA_CTRL_PMC_CK_0_FMON_LOAD_DATA_SEL_PMC_CK_INIT_ENUM                       DISABLE
#define PMC_IMPL_FMON_LOAD_DATA_CTRL_PMC_CK_0_FMON_LOAD_DATA_SEL_PMC_CK_DISABLE                 _MK_ENUM_CONST(0)
#define PMC_IMPL_FMON_LOAD_DATA_CTRL_PMC_CK_0_FMON_LOAD_DATA_SEL_PMC_CK_ENABLE                  _MK_ENUM_CONST(1)


// Register PMC_IMPL_FMON_LOAD_DATA_STATUS_0_PMC_CK_0
#define PMC_IMPL_FMON_LOAD_DATA_STATUS_0_PMC_CK_0                       _MK_ADDR_CONST(0x84c)
#define PMC_IMPL_FMON_LOAD_DATA_STATUS_0_PMC_CK_0_SECURE                        0x0
#define PMC_IMPL_FMON_LOAD_DATA_STATUS_0_PMC_CK_0_DUAL                  0x0
#define PMC_IMPL_FMON_LOAD_DATA_STATUS_0_PMC_CK_0_SCR                   PMC_CK_SCR_0
#define PMC_IMPL_FMON_LOAD_DATA_STATUS_0_PMC_CK_0_WORD_COUNT                    0x1
#define PMC_IMPL_FMON_LOAD_DATA_STATUS_0_PMC_CK_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_FMON_LOAD_DATA_STATUS_0_PMC_CK_0_RESET_MASK                    _MK_MASK_CONST(0x1)
#define PMC_IMPL_FMON_LOAD_DATA_STATUS_0_PMC_CK_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_FMON_LOAD_DATA_STATUS_0_PMC_CK_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define PMC_IMPL_FMON_LOAD_DATA_STATUS_0_PMC_CK_0_READ_MASK                     _MK_MASK_CONST(0x1)
#define PMC_IMPL_FMON_LOAD_DATA_STATUS_0_PMC_CK_0_WRITE_MASK                    _MK_MASK_CONST(0x0)
#define PMC_IMPL_FMON_LOAD_DATA_STATUS_0_PMC_CK_0_FMON_LOAD_DATA_DONE_PMC_CK_SHIFT                      _MK_SHIFT_CONST(0)
#define PMC_IMPL_FMON_LOAD_DATA_STATUS_0_PMC_CK_0_FMON_LOAD_DATA_DONE_PMC_CK_FIELD                      _MK_FIELD_CONST(0x1, PMC_IMPL_FMON_LOAD_DATA_STATUS_0_PMC_CK_0_FMON_LOAD_DATA_DONE_PMC_CK_SHIFT)
#define PMC_IMPL_FMON_LOAD_DATA_STATUS_0_PMC_CK_0_FMON_LOAD_DATA_DONE_PMC_CK_RANGE                      0:0
#define PMC_IMPL_FMON_LOAD_DATA_STATUS_0_PMC_CK_0_FMON_LOAD_DATA_DONE_PMC_CK_WOFFSET                    0x0
#define PMC_IMPL_FMON_LOAD_DATA_STATUS_0_PMC_CK_0_FMON_LOAD_DATA_DONE_PMC_CK_DEFAULT                    _MK_MASK_CONST(0x0)
#define PMC_IMPL_FMON_LOAD_DATA_STATUS_0_PMC_CK_0_FMON_LOAD_DATA_DONE_PMC_CK_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define PMC_IMPL_FMON_LOAD_DATA_STATUS_0_PMC_CK_0_FMON_LOAD_DATA_DONE_PMC_CK_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define PMC_IMPL_FMON_LOAD_DATA_STATUS_0_PMC_CK_0_FMON_LOAD_DATA_DONE_PMC_CK_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define PMC_IMPL_FMON_LOAD_DATA_STATUS_0_PMC_CK_0_FMON_LOAD_DATA_DONE_PMC_CK_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define PMC_IMPL_FMON_LOAD_DATA_STATUS_0_PMC_CK_0_FMON_LOAD_DATA_DONE_PMC_CK_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define PMC_IMPL_FMON_LOAD_DATA_STATUS_0_PMC_CK_0_FMON_LOAD_DATA_DONE_PMC_CK_INIT_ENUM                  DISABLE
#define PMC_IMPL_FMON_LOAD_DATA_STATUS_0_PMC_CK_0_FMON_LOAD_DATA_DONE_PMC_CK_DISABLE                    _MK_ENUM_CONST(0)
#define PMC_IMPL_FMON_LOAD_DATA_STATUS_0_PMC_CK_0_FMON_LOAD_DATA_DONE_PMC_CK_ENABLE                     _MK_ENUM_CONST(1)


// Register PMC_IMPL_FMON_LOAD_DATA_STATUS_1_PMC_CK_0
#define PMC_IMPL_FMON_LOAD_DATA_STATUS_1_PMC_CK_0                       _MK_ADDR_CONST(0x850)
#define PMC_IMPL_FMON_LOAD_DATA_STATUS_1_PMC_CK_0_SECURE                        0x0
#define PMC_IMPL_FMON_LOAD_DATA_STATUS_1_PMC_CK_0_DUAL                  0x0
#define PMC_IMPL_FMON_LOAD_DATA_STATUS_1_PMC_CK_0_SCR                   PMC_CK_SCR_0
#define PMC_IMPL_FMON_LOAD_DATA_STATUS_1_PMC_CK_0_WORD_COUNT                    0x1
#define PMC_IMPL_FMON_LOAD_DATA_STATUS_1_PMC_CK_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_FMON_LOAD_DATA_STATUS_1_PMC_CK_0_RESET_MASK                    _MK_MASK_CONST(0x7)
#define PMC_IMPL_FMON_LOAD_DATA_STATUS_1_PMC_CK_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_FMON_LOAD_DATA_STATUS_1_PMC_CK_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define PMC_IMPL_FMON_LOAD_DATA_STATUS_1_PMC_CK_0_READ_MASK                     _MK_MASK_CONST(0x7)
#define PMC_IMPL_FMON_LOAD_DATA_STATUS_1_PMC_CK_0_WRITE_MASK                    _MK_MASK_CONST(0x0)
#define PMC_IMPL_FMON_LOAD_DATA_STATUS_1_PMC_CK_0_FMON_LOAD_DATA_SEL_STATUS_PMC_CK_SHIFT                        _MK_SHIFT_CONST(0)
#define PMC_IMPL_FMON_LOAD_DATA_STATUS_1_PMC_CK_0_FMON_LOAD_DATA_SEL_STATUS_PMC_CK_FIELD                        _MK_FIELD_CONST(0x7, PMC_IMPL_FMON_LOAD_DATA_STATUS_1_PMC_CK_0_FMON_LOAD_DATA_SEL_STATUS_PMC_CK_SHIFT)
#define PMC_IMPL_FMON_LOAD_DATA_STATUS_1_PMC_CK_0_FMON_LOAD_DATA_SEL_STATUS_PMC_CK_RANGE                        2:0
#define PMC_IMPL_FMON_LOAD_DATA_STATUS_1_PMC_CK_0_FMON_LOAD_DATA_SEL_STATUS_PMC_CK_WOFFSET                      0x0
#define PMC_IMPL_FMON_LOAD_DATA_STATUS_1_PMC_CK_0_FMON_LOAD_DATA_SEL_STATUS_PMC_CK_DEFAULT                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_FMON_LOAD_DATA_STATUS_1_PMC_CK_0_FMON_LOAD_DATA_SEL_STATUS_PMC_CK_DEFAULT_MASK                 _MK_MASK_CONST(0x7)
#define PMC_IMPL_FMON_LOAD_DATA_STATUS_1_PMC_CK_0_FMON_LOAD_DATA_SEL_STATUS_PMC_CK_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_FMON_LOAD_DATA_STATUS_1_PMC_CK_0_FMON_LOAD_DATA_SEL_STATUS_PMC_CK_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_FMON_LOAD_DATA_STATUS_1_PMC_CK_0_FMON_LOAD_DATA_SEL_STATUS_PMC_CK_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define PMC_IMPL_FMON_LOAD_DATA_STATUS_1_PMC_CK_0_FMON_LOAD_DATA_SEL_STATUS_PMC_CK_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)


// Register PMC_IMPL_FMON_LOAD_DATA_STATUS_2_PMC_CK_0
#define PMC_IMPL_FMON_LOAD_DATA_STATUS_2_PMC_CK_0                       _MK_ADDR_CONST(0x854)
#define PMC_IMPL_FMON_LOAD_DATA_STATUS_2_PMC_CK_0_SECURE                        0x0
#define PMC_IMPL_FMON_LOAD_DATA_STATUS_2_PMC_CK_0_DUAL                  0x0
#define PMC_IMPL_FMON_LOAD_DATA_STATUS_2_PMC_CK_0_SCR                   PMC_CK_SCR_0
#define PMC_IMPL_FMON_LOAD_DATA_STATUS_2_PMC_CK_0_WORD_COUNT                    0x1
#define PMC_IMPL_FMON_LOAD_DATA_STATUS_2_PMC_CK_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_FMON_LOAD_DATA_STATUS_2_PMC_CK_0_RESET_MASK                    _MK_MASK_CONST(0xffffffff)
#define PMC_IMPL_FMON_LOAD_DATA_STATUS_2_PMC_CK_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_FMON_LOAD_DATA_STATUS_2_PMC_CK_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define PMC_IMPL_FMON_LOAD_DATA_STATUS_2_PMC_CK_0_READ_MASK                     _MK_MASK_CONST(0xffffffff)
#define PMC_IMPL_FMON_LOAD_DATA_STATUS_2_PMC_CK_0_WRITE_MASK                    _MK_MASK_CONST(0x0)
#define PMC_IMPL_FMON_LOAD_DATA_STATUS_2_PMC_CK_0_FMON_LOAD_DATA_VAL_PMC_CK_SHIFT                       _MK_SHIFT_CONST(0)
#define PMC_IMPL_FMON_LOAD_DATA_STATUS_2_PMC_CK_0_FMON_LOAD_DATA_VAL_PMC_CK_FIELD                       _MK_FIELD_CONST(0xffffffff, PMC_IMPL_FMON_LOAD_DATA_STATUS_2_PMC_CK_0_FMON_LOAD_DATA_VAL_PMC_CK_SHIFT)
#define PMC_IMPL_FMON_LOAD_DATA_STATUS_2_PMC_CK_0_FMON_LOAD_DATA_VAL_PMC_CK_RANGE                       31:0
#define PMC_IMPL_FMON_LOAD_DATA_STATUS_2_PMC_CK_0_FMON_LOAD_DATA_VAL_PMC_CK_WOFFSET                     0x0
#define PMC_IMPL_FMON_LOAD_DATA_STATUS_2_PMC_CK_0_FMON_LOAD_DATA_VAL_PMC_CK_DEFAULT                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_FMON_LOAD_DATA_STATUS_2_PMC_CK_0_FMON_LOAD_DATA_VAL_PMC_CK_DEFAULT_MASK                        _MK_MASK_CONST(0xffffffff)
#define PMC_IMPL_FMON_LOAD_DATA_STATUS_2_PMC_CK_0_FMON_LOAD_DATA_VAL_PMC_CK_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define PMC_IMPL_FMON_LOAD_DATA_STATUS_2_PMC_CK_0_FMON_LOAD_DATA_VAL_PMC_CK_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_FMON_LOAD_DATA_STATUS_2_PMC_CK_0_FMON_LOAD_DATA_VAL_PMC_CK_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_FMON_LOAD_DATA_STATUS_2_PMC_CK_0_FMON_LOAD_DATA_VAL_PMC_CK_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)


// Register PMC_IMPL_FMON_CLEAR_COUNTER_PMC_CK_0
#define PMC_IMPL_FMON_CLEAR_COUNTER_PMC_CK_0                    _MK_ADDR_CONST(0x858)
#define PMC_IMPL_FMON_CLEAR_COUNTER_PMC_CK_0_SECURE                     0x0
#define PMC_IMPL_FMON_CLEAR_COUNTER_PMC_CK_0_DUAL                       0x0
#define PMC_IMPL_FMON_CLEAR_COUNTER_PMC_CK_0_SCR                        PMC_CK_SCR_0
#define PMC_IMPL_FMON_CLEAR_COUNTER_PMC_CK_0_WORD_COUNT                         0x1
#define PMC_IMPL_FMON_CLEAR_COUNTER_PMC_CK_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define PMC_IMPL_FMON_CLEAR_COUNTER_PMC_CK_0_RESET_MASK                         _MK_MASK_CONST(0xf)
#define PMC_IMPL_FMON_CLEAR_COUNTER_PMC_CK_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_FMON_CLEAR_COUNTER_PMC_CK_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define PMC_IMPL_FMON_CLEAR_COUNTER_PMC_CK_0_READ_MASK                  _MK_MASK_CONST(0xf)
#define PMC_IMPL_FMON_CLEAR_COUNTER_PMC_CK_0_WRITE_MASK                         _MK_MASK_CONST(0xf)
#define PMC_IMPL_FMON_CLEAR_COUNTER_PMC_CK_0_FMON_HOLD_COUNT_SAMPLES_PMC_CK_SHIFT                       _MK_SHIFT_CONST(3)
#define PMC_IMPL_FMON_CLEAR_COUNTER_PMC_CK_0_FMON_HOLD_COUNT_SAMPLES_PMC_CK_FIELD                       _MK_FIELD_CONST(0x1, PMC_IMPL_FMON_CLEAR_COUNTER_PMC_CK_0_FMON_HOLD_COUNT_SAMPLES_PMC_CK_SHIFT)
#define PMC_IMPL_FMON_CLEAR_COUNTER_PMC_CK_0_FMON_HOLD_COUNT_SAMPLES_PMC_CK_RANGE                       3:3
#define PMC_IMPL_FMON_CLEAR_COUNTER_PMC_CK_0_FMON_HOLD_COUNT_SAMPLES_PMC_CK_WOFFSET                     0x0
#define PMC_IMPL_FMON_CLEAR_COUNTER_PMC_CK_0_FMON_HOLD_COUNT_SAMPLES_PMC_CK_DEFAULT                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_FMON_CLEAR_COUNTER_PMC_CK_0_FMON_HOLD_COUNT_SAMPLES_PMC_CK_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define PMC_IMPL_FMON_CLEAR_COUNTER_PMC_CK_0_FMON_HOLD_COUNT_SAMPLES_PMC_CK_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define PMC_IMPL_FMON_CLEAR_COUNTER_PMC_CK_0_FMON_HOLD_COUNT_SAMPLES_PMC_CK_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_FMON_CLEAR_COUNTER_PMC_CK_0_FMON_HOLD_COUNT_SAMPLES_PMC_CK_PARITY_PROTECTION                   _MK_MASK_CONST(0x1)
#define PMC_IMPL_FMON_CLEAR_COUNTER_PMC_CK_0_FMON_HOLD_COUNT_SAMPLES_PMC_CK_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define PMC_IMPL_FMON_CLEAR_COUNTER_PMC_CK_0_FMON_CLEAR_FMON_COUNTER_PMC_CK_SHIFT                       _MK_SHIFT_CONST(2)
#define PMC_IMPL_FMON_CLEAR_COUNTER_PMC_CK_0_FMON_CLEAR_FMON_COUNTER_PMC_CK_FIELD                       _MK_FIELD_CONST(0x1, PMC_IMPL_FMON_CLEAR_COUNTER_PMC_CK_0_FMON_CLEAR_FMON_COUNTER_PMC_CK_SHIFT)
#define PMC_IMPL_FMON_CLEAR_COUNTER_PMC_CK_0_FMON_CLEAR_FMON_COUNTER_PMC_CK_RANGE                       2:2
#define PMC_IMPL_FMON_CLEAR_COUNTER_PMC_CK_0_FMON_CLEAR_FMON_COUNTER_PMC_CK_WOFFSET                     0x0
#define PMC_IMPL_FMON_CLEAR_COUNTER_PMC_CK_0_FMON_CLEAR_FMON_COUNTER_PMC_CK_DEFAULT                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_FMON_CLEAR_COUNTER_PMC_CK_0_FMON_CLEAR_FMON_COUNTER_PMC_CK_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define PMC_IMPL_FMON_CLEAR_COUNTER_PMC_CK_0_FMON_CLEAR_FMON_COUNTER_PMC_CK_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define PMC_IMPL_FMON_CLEAR_COUNTER_PMC_CK_0_FMON_CLEAR_FMON_COUNTER_PMC_CK_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_FMON_CLEAR_COUNTER_PMC_CK_0_FMON_CLEAR_FMON_COUNTER_PMC_CK_PARITY_PROTECTION                   _MK_MASK_CONST(0x1)
#define PMC_IMPL_FMON_CLEAR_COUNTER_PMC_CK_0_FMON_CLEAR_FMON_COUNTER_PMC_CK_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define PMC_IMPL_FMON_CLEAR_COUNTER_PMC_CK_0_FMON_MASK_MIN_MAX_COUNT_CLEAR_PMC_CK_SHIFT                 _MK_SHIFT_CONST(1)
#define PMC_IMPL_FMON_CLEAR_COUNTER_PMC_CK_0_FMON_MASK_MIN_MAX_COUNT_CLEAR_PMC_CK_FIELD                 _MK_FIELD_CONST(0x1, PMC_IMPL_FMON_CLEAR_COUNTER_PMC_CK_0_FMON_MASK_MIN_MAX_COUNT_CLEAR_PMC_CK_SHIFT)
#define PMC_IMPL_FMON_CLEAR_COUNTER_PMC_CK_0_FMON_MASK_MIN_MAX_COUNT_CLEAR_PMC_CK_RANGE                 1:1
#define PMC_IMPL_FMON_CLEAR_COUNTER_PMC_CK_0_FMON_MASK_MIN_MAX_COUNT_CLEAR_PMC_CK_WOFFSET                       0x0
#define PMC_IMPL_FMON_CLEAR_COUNTER_PMC_CK_0_FMON_MASK_MIN_MAX_COUNT_CLEAR_PMC_CK_DEFAULT                       _MK_MASK_CONST(0x0)
#define PMC_IMPL_FMON_CLEAR_COUNTER_PMC_CK_0_FMON_MASK_MIN_MAX_COUNT_CLEAR_PMC_CK_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define PMC_IMPL_FMON_CLEAR_COUNTER_PMC_CK_0_FMON_MASK_MIN_MAX_COUNT_CLEAR_PMC_CK_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define PMC_IMPL_FMON_CLEAR_COUNTER_PMC_CK_0_FMON_MASK_MIN_MAX_COUNT_CLEAR_PMC_CK_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define PMC_IMPL_FMON_CLEAR_COUNTER_PMC_CK_0_FMON_MASK_MIN_MAX_COUNT_CLEAR_PMC_CK_PARITY_PROTECTION                     _MK_MASK_CONST(0x1)
#define PMC_IMPL_FMON_CLEAR_COUNTER_PMC_CK_0_FMON_MASK_MIN_MAX_COUNT_CLEAR_PMC_CK_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)

#define PMC_IMPL_FMON_CLEAR_COUNTER_PMC_CK_0_FMON_MIN_MAX_LASTN_COUNT_CLEAR_PMC_CK_SHIFT                        _MK_SHIFT_CONST(0)
#define PMC_IMPL_FMON_CLEAR_COUNTER_PMC_CK_0_FMON_MIN_MAX_LASTN_COUNT_CLEAR_PMC_CK_FIELD                        _MK_FIELD_CONST(0x1, PMC_IMPL_FMON_CLEAR_COUNTER_PMC_CK_0_FMON_MIN_MAX_LASTN_COUNT_CLEAR_PMC_CK_SHIFT)
#define PMC_IMPL_FMON_CLEAR_COUNTER_PMC_CK_0_FMON_MIN_MAX_LASTN_COUNT_CLEAR_PMC_CK_RANGE                        0:0
#define PMC_IMPL_FMON_CLEAR_COUNTER_PMC_CK_0_FMON_MIN_MAX_LASTN_COUNT_CLEAR_PMC_CK_WOFFSET                      0x0
#define PMC_IMPL_FMON_CLEAR_COUNTER_PMC_CK_0_FMON_MIN_MAX_LASTN_COUNT_CLEAR_PMC_CK_DEFAULT                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_FMON_CLEAR_COUNTER_PMC_CK_0_FMON_MIN_MAX_LASTN_COUNT_CLEAR_PMC_CK_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define PMC_IMPL_FMON_CLEAR_COUNTER_PMC_CK_0_FMON_MIN_MAX_LASTN_COUNT_CLEAR_PMC_CK_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_FMON_CLEAR_COUNTER_PMC_CK_0_FMON_MIN_MAX_LASTN_COUNT_CLEAR_PMC_CK_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_FMON_CLEAR_COUNTER_PMC_CK_0_FMON_MIN_MAX_LASTN_COUNT_CLEAR_PMC_CK_PARITY_PROTECTION                    _MK_MASK_CONST(0x1)
#define PMC_IMPL_FMON_CLEAR_COUNTER_PMC_CK_0_FMON_MIN_MAX_LASTN_COUNT_CLEAR_PMC_CK_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)


// Register PMC_IMPL_FMON_DEBUG_CONFIG_PMC_CK_0
#define PMC_IMPL_FMON_DEBUG_CONFIG_PMC_CK_0                     _MK_ADDR_CONST(0x85c)
#define PMC_IMPL_FMON_DEBUG_CONFIG_PMC_CK_0_SECURE                      0x0
#define PMC_IMPL_FMON_DEBUG_CONFIG_PMC_CK_0_DUAL                        0x0
#define PMC_IMPL_FMON_DEBUG_CONFIG_PMC_CK_0_SCR                         PMC_CK_SCR_0
#define PMC_IMPL_FMON_DEBUG_CONFIG_PMC_CK_0_WORD_COUNT                  0x1
#define PMC_IMPL_FMON_DEBUG_CONFIG_PMC_CK_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_FMON_DEBUG_CONFIG_PMC_CK_0_RESET_MASK                  _MK_MASK_CONST(0x3)
#define PMC_IMPL_FMON_DEBUG_CONFIG_PMC_CK_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_FMON_DEBUG_CONFIG_PMC_CK_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_FMON_DEBUG_CONFIG_PMC_CK_0_READ_MASK                   _MK_MASK_CONST(0x3)
#define PMC_IMPL_FMON_DEBUG_CONFIG_PMC_CK_0_WRITE_MASK                  _MK_MASK_CONST(0x1)
#define PMC_IMPL_FMON_DEBUG_CONFIG_PMC_CK_0_FMON_REF_WINDOW_PMC_CK_SHIFT                        _MK_SHIFT_CONST(1)
#define PMC_IMPL_FMON_DEBUG_CONFIG_PMC_CK_0_FMON_REF_WINDOW_PMC_CK_FIELD                        _MK_FIELD_CONST(0x1, PMC_IMPL_FMON_DEBUG_CONFIG_PMC_CK_0_FMON_REF_WINDOW_PMC_CK_SHIFT)
#define PMC_IMPL_FMON_DEBUG_CONFIG_PMC_CK_0_FMON_REF_WINDOW_PMC_CK_RANGE                        1:1
#define PMC_IMPL_FMON_DEBUG_CONFIG_PMC_CK_0_FMON_REF_WINDOW_PMC_CK_WOFFSET                      0x0
#define PMC_IMPL_FMON_DEBUG_CONFIG_PMC_CK_0_FMON_REF_WINDOW_PMC_CK_DEFAULT                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_FMON_DEBUG_CONFIG_PMC_CK_0_FMON_REF_WINDOW_PMC_CK_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define PMC_IMPL_FMON_DEBUG_CONFIG_PMC_CK_0_FMON_REF_WINDOW_PMC_CK_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_FMON_DEBUG_CONFIG_PMC_CK_0_FMON_REF_WINDOW_PMC_CK_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_FMON_DEBUG_CONFIG_PMC_CK_0_FMON_REF_WINDOW_PMC_CK_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define PMC_IMPL_FMON_DEBUG_CONFIG_PMC_CK_0_FMON_REF_WINDOW_PMC_CK_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define PMC_IMPL_FMON_DEBUG_CONFIG_PMC_CK_0_FMON_ENABLE_DEBUG_PMC_CK_SHIFT                      _MK_SHIFT_CONST(0)
#define PMC_IMPL_FMON_DEBUG_CONFIG_PMC_CK_0_FMON_ENABLE_DEBUG_PMC_CK_FIELD                      _MK_FIELD_CONST(0x1, PMC_IMPL_FMON_DEBUG_CONFIG_PMC_CK_0_FMON_ENABLE_DEBUG_PMC_CK_SHIFT)
#define PMC_IMPL_FMON_DEBUG_CONFIG_PMC_CK_0_FMON_ENABLE_DEBUG_PMC_CK_RANGE                      0:0
#define PMC_IMPL_FMON_DEBUG_CONFIG_PMC_CK_0_FMON_ENABLE_DEBUG_PMC_CK_WOFFSET                    0x0
#define PMC_IMPL_FMON_DEBUG_CONFIG_PMC_CK_0_FMON_ENABLE_DEBUG_PMC_CK_DEFAULT                    _MK_MASK_CONST(0x0)
#define PMC_IMPL_FMON_DEBUG_CONFIG_PMC_CK_0_FMON_ENABLE_DEBUG_PMC_CK_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define PMC_IMPL_FMON_DEBUG_CONFIG_PMC_CK_0_FMON_ENABLE_DEBUG_PMC_CK_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define PMC_IMPL_FMON_DEBUG_CONFIG_PMC_CK_0_FMON_ENABLE_DEBUG_PMC_CK_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define PMC_IMPL_FMON_DEBUG_CONFIG_PMC_CK_0_FMON_ENABLE_DEBUG_PMC_CK_PARITY_PROTECTION                  _MK_MASK_CONST(0x1)
#define PMC_IMPL_FMON_DEBUG_CONFIG_PMC_CK_0_FMON_ENABLE_DEBUG_PMC_CK_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define PMC_IMPL_FMON_DEBUG_CONFIG_PMC_CK_0_FMON_ENABLE_DEBUG_PMC_CK_INIT_ENUM                  DISABLE
#define PMC_IMPL_FMON_DEBUG_CONFIG_PMC_CK_0_FMON_ENABLE_DEBUG_PMC_CK_DISABLE                    _MK_ENUM_CONST(0)
#define PMC_IMPL_FMON_DEBUG_CONFIG_PMC_CK_0_FMON_ENABLE_DEBUG_PMC_CK_ENABLE                     _MK_ENUM_CONST(1)


// Register PMC_IMPL_FMON_CNTR_OVERFLOW_CTRL_PMC_CK_0
#define PMC_IMPL_FMON_CNTR_OVERFLOW_CTRL_PMC_CK_0                       _MK_ADDR_CONST(0x860)
#define PMC_IMPL_FMON_CNTR_OVERFLOW_CTRL_PMC_CK_0_SECURE                        0x0
#define PMC_IMPL_FMON_CNTR_OVERFLOW_CTRL_PMC_CK_0_DUAL                  0x0
#define PMC_IMPL_FMON_CNTR_OVERFLOW_CTRL_PMC_CK_0_SCR                   PMC_CK_SCR_0
#define PMC_IMPL_FMON_CNTR_OVERFLOW_CTRL_PMC_CK_0_WORD_COUNT                    0x1
#define PMC_IMPL_FMON_CNTR_OVERFLOW_CTRL_PMC_CK_0_RESET_VAL                     _MK_MASK_CONST(0x8000000c)
#define PMC_IMPL_FMON_CNTR_OVERFLOW_CTRL_PMC_CK_0_RESET_MASK                    _MK_MASK_CONST(0x8000001f)
#define PMC_IMPL_FMON_CNTR_OVERFLOW_CTRL_PMC_CK_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_FMON_CNTR_OVERFLOW_CTRL_PMC_CK_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define PMC_IMPL_FMON_CNTR_OVERFLOW_CTRL_PMC_CK_0_READ_MASK                     _MK_MASK_CONST(0x8000001f)
#define PMC_IMPL_FMON_CNTR_OVERFLOW_CTRL_PMC_CK_0_WRITE_MASK                    _MK_MASK_CONST(0x8000001f)
#define PMC_IMPL_FMON_CNTR_OVERFLOW_CTRL_PMC_CK_0_FMON_OVERFLOW_BIT_SEL_PMC_CK_SHIFT                    _MK_SHIFT_CONST(0)
#define PMC_IMPL_FMON_CNTR_OVERFLOW_CTRL_PMC_CK_0_FMON_OVERFLOW_BIT_SEL_PMC_CK_FIELD                    _MK_FIELD_CONST(0x1f, PMC_IMPL_FMON_CNTR_OVERFLOW_CTRL_PMC_CK_0_FMON_OVERFLOW_BIT_SEL_PMC_CK_SHIFT)
#define PMC_IMPL_FMON_CNTR_OVERFLOW_CTRL_PMC_CK_0_FMON_OVERFLOW_BIT_SEL_PMC_CK_RANGE                    4:0
#define PMC_IMPL_FMON_CNTR_OVERFLOW_CTRL_PMC_CK_0_FMON_OVERFLOW_BIT_SEL_PMC_CK_WOFFSET                  0x0
#define PMC_IMPL_FMON_CNTR_OVERFLOW_CTRL_PMC_CK_0_FMON_OVERFLOW_BIT_SEL_PMC_CK_DEFAULT                  _MK_MASK_CONST(0xc)
#define PMC_IMPL_FMON_CNTR_OVERFLOW_CTRL_PMC_CK_0_FMON_OVERFLOW_BIT_SEL_PMC_CK_DEFAULT_MASK                     _MK_MASK_CONST(0x1f)
#define PMC_IMPL_FMON_CNTR_OVERFLOW_CTRL_PMC_CK_0_FMON_OVERFLOW_BIT_SEL_PMC_CK_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define PMC_IMPL_FMON_CNTR_OVERFLOW_CTRL_PMC_CK_0_FMON_OVERFLOW_BIT_SEL_PMC_CK_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define PMC_IMPL_FMON_CNTR_OVERFLOW_CTRL_PMC_CK_0_FMON_OVERFLOW_BIT_SEL_PMC_CK_PARITY_PROTECTION                        _MK_MASK_CONST(0x1)
#define PMC_IMPL_FMON_CNTR_OVERFLOW_CTRL_PMC_CK_0_FMON_OVERFLOW_BIT_SEL_PMC_CK_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)

#define PMC_IMPL_FMON_CNTR_OVERFLOW_CTRL_PMC_CK_0_USE_CNTR_OVERFLOW_DC_FAULT_PMC_CK_SHIFT                       _MK_SHIFT_CONST(31)
#define PMC_IMPL_FMON_CNTR_OVERFLOW_CTRL_PMC_CK_0_USE_CNTR_OVERFLOW_DC_FAULT_PMC_CK_FIELD                       _MK_FIELD_CONST(0x1, PMC_IMPL_FMON_CNTR_OVERFLOW_CTRL_PMC_CK_0_USE_CNTR_OVERFLOW_DC_FAULT_PMC_CK_SHIFT)
#define PMC_IMPL_FMON_CNTR_OVERFLOW_CTRL_PMC_CK_0_USE_CNTR_OVERFLOW_DC_FAULT_PMC_CK_RANGE                       31:31
#define PMC_IMPL_FMON_CNTR_OVERFLOW_CTRL_PMC_CK_0_USE_CNTR_OVERFLOW_DC_FAULT_PMC_CK_WOFFSET                     0x0
#define PMC_IMPL_FMON_CNTR_OVERFLOW_CTRL_PMC_CK_0_USE_CNTR_OVERFLOW_DC_FAULT_PMC_CK_DEFAULT                     _MK_MASK_CONST(0x1)
#define PMC_IMPL_FMON_CNTR_OVERFLOW_CTRL_PMC_CK_0_USE_CNTR_OVERFLOW_DC_FAULT_PMC_CK_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define PMC_IMPL_FMON_CNTR_OVERFLOW_CTRL_PMC_CK_0_USE_CNTR_OVERFLOW_DC_FAULT_PMC_CK_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define PMC_IMPL_FMON_CNTR_OVERFLOW_CTRL_PMC_CK_0_USE_CNTR_OVERFLOW_DC_FAULT_PMC_CK_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_FMON_CNTR_OVERFLOW_CTRL_PMC_CK_0_USE_CNTR_OVERFLOW_DC_FAULT_PMC_CK_PARITY_PROTECTION                   _MK_MASK_CONST(0x1)
#define PMC_IMPL_FMON_CNTR_OVERFLOW_CTRL_PMC_CK_0_USE_CNTR_OVERFLOW_DC_FAULT_PMC_CK_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define PMC_IMPL_FMON_CNTR_OVERFLOW_CTRL_PMC_CK_0_USE_CNTR_OVERFLOW_DC_FAULT_PMC_CK_INIT_ENUM                   ENABLE
#define PMC_IMPL_FMON_CNTR_OVERFLOW_CTRL_PMC_CK_0_USE_CNTR_OVERFLOW_DC_FAULT_PMC_CK_DISABLE                     _MK_ENUM_CONST(0)
#define PMC_IMPL_FMON_CNTR_OVERFLOW_CTRL_PMC_CK_0_USE_CNTR_OVERFLOW_DC_FAULT_PMC_CK_ENABLE                      _MK_ENUM_CONST(1)


// Register PMC_IMPL_FMON_THRESHOLD_HIGH_OSCnFUSE_CK_0
#define PMC_IMPL_FMON_THRESHOLD_HIGH_OSCnFUSE_CK_0                      _MK_ADDR_CONST(0x864)
#define PMC_IMPL_FMON_THRESHOLD_HIGH_OSCnFUSE_CK_0_SECURE                       0x0
#define PMC_IMPL_FMON_THRESHOLD_HIGH_OSCnFUSE_CK_0_DUAL                         0x0
#define PMC_IMPL_FMON_THRESHOLD_HIGH_OSCnFUSE_CK_0_SCR                  OSCnFUSE_CK_SCR_0
#define PMC_IMPL_FMON_THRESHOLD_HIGH_OSCnFUSE_CK_0_WORD_COUNT                   0x1
#define PMC_IMPL_FMON_THRESHOLD_HIGH_OSCnFUSE_CK_0_RESET_VAL                    _MK_MASK_CONST(0x4e2)
#define PMC_IMPL_FMON_THRESHOLD_HIGH_OSCnFUSE_CK_0_RESET_MASK                   _MK_MASK_CONST(0xffffffff)
#define PMC_IMPL_FMON_THRESHOLD_HIGH_OSCnFUSE_CK_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define PMC_IMPL_FMON_THRESHOLD_HIGH_OSCnFUSE_CK_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_FMON_THRESHOLD_HIGH_OSCnFUSE_CK_0_READ_MASK                    _MK_MASK_CONST(0xffffffff)
#define PMC_IMPL_FMON_THRESHOLD_HIGH_OSCnFUSE_CK_0_WRITE_MASK                   _MK_MASK_CONST(0xffffffff)
#define PMC_IMPL_FMON_THRESHOLD_HIGH_OSCnFUSE_CK_0_FMON_COUNT_THRESH_HIGH_OSCnFUSE_CK_SHIFT                     _MK_SHIFT_CONST(0)
#define PMC_IMPL_FMON_THRESHOLD_HIGH_OSCnFUSE_CK_0_FMON_COUNT_THRESH_HIGH_OSCnFUSE_CK_FIELD                     _MK_FIELD_CONST(0xffffffff, PMC_IMPL_FMON_THRESHOLD_HIGH_OSCnFUSE_CK_0_FMON_COUNT_THRESH_HIGH_OSCnFUSE_CK_SHIFT)
#define PMC_IMPL_FMON_THRESHOLD_HIGH_OSCnFUSE_CK_0_FMON_COUNT_THRESH_HIGH_OSCnFUSE_CK_RANGE                     31:0
#define PMC_IMPL_FMON_THRESHOLD_HIGH_OSCnFUSE_CK_0_FMON_COUNT_THRESH_HIGH_OSCnFUSE_CK_WOFFSET                   0x0
#define PMC_IMPL_FMON_THRESHOLD_HIGH_OSCnFUSE_CK_0_FMON_COUNT_THRESH_HIGH_OSCnFUSE_CK_DEFAULT                   _MK_MASK_CONST(0x4e2)
#define PMC_IMPL_FMON_THRESHOLD_HIGH_OSCnFUSE_CK_0_FMON_COUNT_THRESH_HIGH_OSCnFUSE_CK_DEFAULT_MASK                      _MK_MASK_CONST(0xffffffff)
#define PMC_IMPL_FMON_THRESHOLD_HIGH_OSCnFUSE_CK_0_FMON_COUNT_THRESH_HIGH_OSCnFUSE_CK_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_FMON_THRESHOLD_HIGH_OSCnFUSE_CK_0_FMON_COUNT_THRESH_HIGH_OSCnFUSE_CK_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_FMON_THRESHOLD_HIGH_OSCnFUSE_CK_0_FMON_COUNT_THRESH_HIGH_OSCnFUSE_CK_PARITY_PROTECTION                 _MK_MASK_CONST(0x1)
#define PMC_IMPL_FMON_THRESHOLD_HIGH_OSCnFUSE_CK_0_FMON_COUNT_THRESH_HIGH_OSCnFUSE_CK_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)


// Register PMC_IMPL_FMON_THRESHOLD_LOW_OSCnFUSE_CK_0
#define PMC_IMPL_FMON_THRESHOLD_LOW_OSCnFUSE_CK_0                       _MK_ADDR_CONST(0x868)
#define PMC_IMPL_FMON_THRESHOLD_LOW_OSCnFUSE_CK_0_SECURE                        0x0
#define PMC_IMPL_FMON_THRESHOLD_LOW_OSCnFUSE_CK_0_DUAL                  0x0
#define PMC_IMPL_FMON_THRESHOLD_LOW_OSCnFUSE_CK_0_SCR                   OSCnFUSE_CK_SCR_0
#define PMC_IMPL_FMON_THRESHOLD_LOW_OSCnFUSE_CK_0_WORD_COUNT                    0x1
#define PMC_IMPL_FMON_THRESHOLD_LOW_OSCnFUSE_CK_0_RESET_VAL                     _MK_MASK_CONST(0x1a0)
#define PMC_IMPL_FMON_THRESHOLD_LOW_OSCnFUSE_CK_0_RESET_MASK                    _MK_MASK_CONST(0xffffffff)
#define PMC_IMPL_FMON_THRESHOLD_LOW_OSCnFUSE_CK_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_FMON_THRESHOLD_LOW_OSCnFUSE_CK_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define PMC_IMPL_FMON_THRESHOLD_LOW_OSCnFUSE_CK_0_READ_MASK                     _MK_MASK_CONST(0xffffffff)
#define PMC_IMPL_FMON_THRESHOLD_LOW_OSCnFUSE_CK_0_WRITE_MASK                    _MK_MASK_CONST(0xffffffff)
#define PMC_IMPL_FMON_THRESHOLD_LOW_OSCnFUSE_CK_0_FMON_COUNT_THRESH_LOW_OSCnFUSE_CK_SHIFT                       _MK_SHIFT_CONST(0)
#define PMC_IMPL_FMON_THRESHOLD_LOW_OSCnFUSE_CK_0_FMON_COUNT_THRESH_LOW_OSCnFUSE_CK_FIELD                       _MK_FIELD_CONST(0xffffffff, PMC_IMPL_FMON_THRESHOLD_LOW_OSCnFUSE_CK_0_FMON_COUNT_THRESH_LOW_OSCnFUSE_CK_SHIFT)
#define PMC_IMPL_FMON_THRESHOLD_LOW_OSCnFUSE_CK_0_FMON_COUNT_THRESH_LOW_OSCnFUSE_CK_RANGE                       31:0
#define PMC_IMPL_FMON_THRESHOLD_LOW_OSCnFUSE_CK_0_FMON_COUNT_THRESH_LOW_OSCnFUSE_CK_WOFFSET                     0x0
#define PMC_IMPL_FMON_THRESHOLD_LOW_OSCnFUSE_CK_0_FMON_COUNT_THRESH_LOW_OSCnFUSE_CK_DEFAULT                     _MK_MASK_CONST(0x1a0)
#define PMC_IMPL_FMON_THRESHOLD_LOW_OSCnFUSE_CK_0_FMON_COUNT_THRESH_LOW_OSCnFUSE_CK_DEFAULT_MASK                        _MK_MASK_CONST(0xffffffff)
#define PMC_IMPL_FMON_THRESHOLD_LOW_OSCnFUSE_CK_0_FMON_COUNT_THRESH_LOW_OSCnFUSE_CK_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define PMC_IMPL_FMON_THRESHOLD_LOW_OSCnFUSE_CK_0_FMON_COUNT_THRESH_LOW_OSCnFUSE_CK_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_FMON_THRESHOLD_LOW_OSCnFUSE_CK_0_FMON_COUNT_THRESH_LOW_OSCnFUSE_CK_PARITY_PROTECTION                   _MK_MASK_CONST(0x1)
#define PMC_IMPL_FMON_THRESHOLD_LOW_OSCnFUSE_CK_0_FMON_COUNT_THRESH_LOW_OSCnFUSE_CK_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)


// Register PMC_IMPL_FMON_REF_WINDOW_COUNT_OSCnFUSE_CK_0
#define PMC_IMPL_FMON_REF_WINDOW_COUNT_OSCnFUSE_CK_0                    _MK_ADDR_CONST(0x86c)
#define PMC_IMPL_FMON_REF_WINDOW_COUNT_OSCnFUSE_CK_0_SECURE                     0x0
#define PMC_IMPL_FMON_REF_WINDOW_COUNT_OSCnFUSE_CK_0_DUAL                       0x0
#define PMC_IMPL_FMON_REF_WINDOW_COUNT_OSCnFUSE_CK_0_SCR                        OSCnFUSE_CK_SCR_0
#define PMC_IMPL_FMON_REF_WINDOW_COUNT_OSCnFUSE_CK_0_WORD_COUNT                         0x1
#define PMC_IMPL_FMON_REF_WINDOW_COUNT_OSCnFUSE_CK_0_RESET_VAL                  _MK_MASK_CONST(0x280)
#define PMC_IMPL_FMON_REF_WINDOW_COUNT_OSCnFUSE_CK_0_RESET_MASK                         _MK_MASK_CONST(0xffffff)
#define PMC_IMPL_FMON_REF_WINDOW_COUNT_OSCnFUSE_CK_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_FMON_REF_WINDOW_COUNT_OSCnFUSE_CK_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define PMC_IMPL_FMON_REF_WINDOW_COUNT_OSCnFUSE_CK_0_READ_MASK                  _MK_MASK_CONST(0xffffff)
#define PMC_IMPL_FMON_REF_WINDOW_COUNT_OSCnFUSE_CK_0_WRITE_MASK                         _MK_MASK_CONST(0xffffff)
#define PMC_IMPL_FMON_REF_WINDOW_COUNT_OSCnFUSE_CK_0_FMON_REF_WINDOW_COUNT_OSCnFUSE_CK_SHIFT                    _MK_SHIFT_CONST(0)
#define PMC_IMPL_FMON_REF_WINDOW_COUNT_OSCnFUSE_CK_0_FMON_REF_WINDOW_COUNT_OSCnFUSE_CK_FIELD                    _MK_FIELD_CONST(0xffffff, PMC_IMPL_FMON_REF_WINDOW_COUNT_OSCnFUSE_CK_0_FMON_REF_WINDOW_COUNT_OSCnFUSE_CK_SHIFT)
#define PMC_IMPL_FMON_REF_WINDOW_COUNT_OSCnFUSE_CK_0_FMON_REF_WINDOW_COUNT_OSCnFUSE_CK_RANGE                    23:0
#define PMC_IMPL_FMON_REF_WINDOW_COUNT_OSCnFUSE_CK_0_FMON_REF_WINDOW_COUNT_OSCnFUSE_CK_WOFFSET                  0x0
#define PMC_IMPL_FMON_REF_WINDOW_COUNT_OSCnFUSE_CK_0_FMON_REF_WINDOW_COUNT_OSCnFUSE_CK_DEFAULT                  _MK_MASK_CONST(0x280)
#define PMC_IMPL_FMON_REF_WINDOW_COUNT_OSCnFUSE_CK_0_FMON_REF_WINDOW_COUNT_OSCnFUSE_CK_DEFAULT_MASK                     _MK_MASK_CONST(0xffffff)
#define PMC_IMPL_FMON_REF_WINDOW_COUNT_OSCnFUSE_CK_0_FMON_REF_WINDOW_COUNT_OSCnFUSE_CK_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define PMC_IMPL_FMON_REF_WINDOW_COUNT_OSCnFUSE_CK_0_FMON_REF_WINDOW_COUNT_OSCnFUSE_CK_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define PMC_IMPL_FMON_REF_WINDOW_COUNT_OSCnFUSE_CK_0_FMON_REF_WINDOW_COUNT_OSCnFUSE_CK_PARITY_PROTECTION                        _MK_MASK_CONST(0x1)
#define PMC_IMPL_FMON_REF_WINDOW_COUNT_OSCnFUSE_CK_0_FMON_REF_WINDOW_COUNT_OSCnFUSE_CK_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)


// Register PMC_IMPL_FMON_REF_WINDOW_DC_CHECK_COUNT_OSCnFUSE_CK_0
#define PMC_IMPL_FMON_REF_WINDOW_DC_CHECK_COUNT_OSCnFUSE_CK_0                   _MK_ADDR_CONST(0x870)
#define PMC_IMPL_FMON_REF_WINDOW_DC_CHECK_COUNT_OSCnFUSE_CK_0_SECURE                    0x0
#define PMC_IMPL_FMON_REF_WINDOW_DC_CHECK_COUNT_OSCnFUSE_CK_0_DUAL                      0x0
#define PMC_IMPL_FMON_REF_WINDOW_DC_CHECK_COUNT_OSCnFUSE_CK_0_SCR                       OSCnFUSE_CK_SCR_0
#define PMC_IMPL_FMON_REF_WINDOW_DC_CHECK_COUNT_OSCnFUSE_CK_0_WORD_COUNT                        0x1
#define PMC_IMPL_FMON_REF_WINDOW_DC_CHECK_COUNT_OSCnFUSE_CK_0_RESET_VAL                         _MK_MASK_CONST(0xffffff)
#define PMC_IMPL_FMON_REF_WINDOW_DC_CHECK_COUNT_OSCnFUSE_CK_0_RESET_MASK                        _MK_MASK_CONST(0xffffff)
#define PMC_IMPL_FMON_REF_WINDOW_DC_CHECK_COUNT_OSCnFUSE_CK_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define PMC_IMPL_FMON_REF_WINDOW_DC_CHECK_COUNT_OSCnFUSE_CK_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_FMON_REF_WINDOW_DC_CHECK_COUNT_OSCnFUSE_CK_0_READ_MASK                         _MK_MASK_CONST(0xffffff)
#define PMC_IMPL_FMON_REF_WINDOW_DC_CHECK_COUNT_OSCnFUSE_CK_0_WRITE_MASK                        _MK_MASK_CONST(0xffffff)
#define PMC_IMPL_FMON_REF_WINDOW_DC_CHECK_COUNT_OSCnFUSE_CK_0_FMON_REF_WINDOW_DC_CHECK_COUNT_OSCnFUSE_CK_SHIFT                  _MK_SHIFT_CONST(0)
#define PMC_IMPL_FMON_REF_WINDOW_DC_CHECK_COUNT_OSCnFUSE_CK_0_FMON_REF_WINDOW_DC_CHECK_COUNT_OSCnFUSE_CK_FIELD                  _MK_FIELD_CONST(0xffffff, PMC_IMPL_FMON_REF_WINDOW_DC_CHECK_COUNT_OSCnFUSE_CK_0_FMON_REF_WINDOW_DC_CHECK_COUNT_OSCnFUSE_CK_SHIFT)
#define PMC_IMPL_FMON_REF_WINDOW_DC_CHECK_COUNT_OSCnFUSE_CK_0_FMON_REF_WINDOW_DC_CHECK_COUNT_OSCnFUSE_CK_RANGE                  23:0
#define PMC_IMPL_FMON_REF_WINDOW_DC_CHECK_COUNT_OSCnFUSE_CK_0_FMON_REF_WINDOW_DC_CHECK_COUNT_OSCnFUSE_CK_WOFFSET                        0x0
#define PMC_IMPL_FMON_REF_WINDOW_DC_CHECK_COUNT_OSCnFUSE_CK_0_FMON_REF_WINDOW_DC_CHECK_COUNT_OSCnFUSE_CK_DEFAULT                        _MK_MASK_CONST(0xffffff)
#define PMC_IMPL_FMON_REF_WINDOW_DC_CHECK_COUNT_OSCnFUSE_CK_0_FMON_REF_WINDOW_DC_CHECK_COUNT_OSCnFUSE_CK_DEFAULT_MASK                   _MK_MASK_CONST(0xffffff)
#define PMC_IMPL_FMON_REF_WINDOW_DC_CHECK_COUNT_OSCnFUSE_CK_0_FMON_REF_WINDOW_DC_CHECK_COUNT_OSCnFUSE_CK_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_FMON_REF_WINDOW_DC_CHECK_COUNT_OSCnFUSE_CK_0_FMON_REF_WINDOW_DC_CHECK_COUNT_OSCnFUSE_CK_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_FMON_REF_WINDOW_DC_CHECK_COUNT_OSCnFUSE_CK_0_FMON_REF_WINDOW_DC_CHECK_COUNT_OSCnFUSE_CK_PARITY_PROTECTION                      _MK_MASK_CONST(0x1)
#define PMC_IMPL_FMON_REF_WINDOW_DC_CHECK_COUNT_OSCnFUSE_CK_0_FMON_REF_WINDOW_DC_CHECK_COUNT_OSCnFUSE_CK_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)


// Register PMC_IMPL_FMON_FAULT_ACTION_OSCnFUSE_CK_0
#define PMC_IMPL_FMON_FAULT_ACTION_OSCnFUSE_CK_0                        _MK_ADDR_CONST(0x874)
#define PMC_IMPL_FMON_FAULT_ACTION_OSCnFUSE_CK_0_SECURE                         0x0
#define PMC_IMPL_FMON_FAULT_ACTION_OSCnFUSE_CK_0_DUAL                   0x0
#define PMC_IMPL_FMON_FAULT_ACTION_OSCnFUSE_CK_0_SCR                    OSCnFUSE_CK_SCR_0
#define PMC_IMPL_FMON_FAULT_ACTION_OSCnFUSE_CK_0_WORD_COUNT                     0x1
#define PMC_IMPL_FMON_FAULT_ACTION_OSCnFUSE_CK_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_FMON_FAULT_ACTION_OSCnFUSE_CK_0_RESET_MASK                     _MK_MASK_CONST(0x7)
#define PMC_IMPL_FMON_FAULT_ACTION_OSCnFUSE_CK_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define PMC_IMPL_FMON_FAULT_ACTION_OSCnFUSE_CK_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_FMON_FAULT_ACTION_OSCnFUSE_CK_0_READ_MASK                      _MK_MASK_CONST(0x7)
#define PMC_IMPL_FMON_FAULT_ACTION_OSCnFUSE_CK_0_WRITE_MASK                     _MK_MASK_CONST(0x7)
#define PMC_IMPL_FMON_FAULT_ACTION_OSCnFUSE_CK_0_FMON_ACTION_DC_RESET_REQ_OSCnFUSE_CK_SHIFT                     _MK_SHIFT_CONST(2)
#define PMC_IMPL_FMON_FAULT_ACTION_OSCnFUSE_CK_0_FMON_ACTION_DC_RESET_REQ_OSCnFUSE_CK_FIELD                     _MK_FIELD_CONST(0x1, PMC_IMPL_FMON_FAULT_ACTION_OSCnFUSE_CK_0_FMON_ACTION_DC_RESET_REQ_OSCnFUSE_CK_SHIFT)
#define PMC_IMPL_FMON_FAULT_ACTION_OSCnFUSE_CK_0_FMON_ACTION_DC_RESET_REQ_OSCnFUSE_CK_RANGE                     2:2
#define PMC_IMPL_FMON_FAULT_ACTION_OSCnFUSE_CK_0_FMON_ACTION_DC_RESET_REQ_OSCnFUSE_CK_WOFFSET                   0x0
#define PMC_IMPL_FMON_FAULT_ACTION_OSCnFUSE_CK_0_FMON_ACTION_DC_RESET_REQ_OSCnFUSE_CK_DEFAULT                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_FMON_FAULT_ACTION_OSCnFUSE_CK_0_FMON_ACTION_DC_RESET_REQ_OSCnFUSE_CK_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define PMC_IMPL_FMON_FAULT_ACTION_OSCnFUSE_CK_0_FMON_ACTION_DC_RESET_REQ_OSCnFUSE_CK_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_FMON_FAULT_ACTION_OSCnFUSE_CK_0_FMON_ACTION_DC_RESET_REQ_OSCnFUSE_CK_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_FMON_FAULT_ACTION_OSCnFUSE_CK_0_FMON_ACTION_DC_RESET_REQ_OSCnFUSE_CK_PARITY_PROTECTION                 _MK_MASK_CONST(0x1)
#define PMC_IMPL_FMON_FAULT_ACTION_OSCnFUSE_CK_0_FMON_ACTION_DC_RESET_REQ_OSCnFUSE_CK_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define PMC_IMPL_FMON_FAULT_ACTION_OSCnFUSE_CK_0_FMON_ACTION_DC_RESET_REQ_OSCnFUSE_CK_INIT_ENUM                 DISABLE
#define PMC_IMPL_FMON_FAULT_ACTION_OSCnFUSE_CK_0_FMON_ACTION_DC_RESET_REQ_OSCnFUSE_CK_DISABLE                   _MK_ENUM_CONST(0)
#define PMC_IMPL_FMON_FAULT_ACTION_OSCnFUSE_CK_0_FMON_ACTION_DC_RESET_REQ_OSCnFUSE_CK_ENABLE                    _MK_ENUM_CONST(1)

#define PMC_IMPL_FMON_FAULT_ACTION_OSCnFUSE_CK_0_FMON_ACTION_FAULT_REPORT_OSCnFUSE_CK_SHIFT                     _MK_SHIFT_CONST(1)
#define PMC_IMPL_FMON_FAULT_ACTION_OSCnFUSE_CK_0_FMON_ACTION_FAULT_REPORT_OSCnFUSE_CK_FIELD                     _MK_FIELD_CONST(0x1, PMC_IMPL_FMON_FAULT_ACTION_OSCnFUSE_CK_0_FMON_ACTION_FAULT_REPORT_OSCnFUSE_CK_SHIFT)
#define PMC_IMPL_FMON_FAULT_ACTION_OSCnFUSE_CK_0_FMON_ACTION_FAULT_REPORT_OSCnFUSE_CK_RANGE                     1:1
#define PMC_IMPL_FMON_FAULT_ACTION_OSCnFUSE_CK_0_FMON_ACTION_FAULT_REPORT_OSCnFUSE_CK_WOFFSET                   0x0
#define PMC_IMPL_FMON_FAULT_ACTION_OSCnFUSE_CK_0_FMON_ACTION_FAULT_REPORT_OSCnFUSE_CK_DEFAULT                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_FMON_FAULT_ACTION_OSCnFUSE_CK_0_FMON_ACTION_FAULT_REPORT_OSCnFUSE_CK_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define PMC_IMPL_FMON_FAULT_ACTION_OSCnFUSE_CK_0_FMON_ACTION_FAULT_REPORT_OSCnFUSE_CK_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_FMON_FAULT_ACTION_OSCnFUSE_CK_0_FMON_ACTION_FAULT_REPORT_OSCnFUSE_CK_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_FMON_FAULT_ACTION_OSCnFUSE_CK_0_FMON_ACTION_FAULT_REPORT_OSCnFUSE_CK_PARITY_PROTECTION                 _MK_MASK_CONST(0x1)
#define PMC_IMPL_FMON_FAULT_ACTION_OSCnFUSE_CK_0_FMON_ACTION_FAULT_REPORT_OSCnFUSE_CK_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define PMC_IMPL_FMON_FAULT_ACTION_OSCnFUSE_CK_0_FMON_ACTION_FAULT_REPORT_OSCnFUSE_CK_INIT_ENUM                 DISABLE
#define PMC_IMPL_FMON_FAULT_ACTION_OSCnFUSE_CK_0_FMON_ACTION_FAULT_REPORT_OSCnFUSE_CK_DISABLE                   _MK_ENUM_CONST(0)
#define PMC_IMPL_FMON_FAULT_ACTION_OSCnFUSE_CK_0_FMON_ACTION_FAULT_REPORT_OSCnFUSE_CK_ENABLE                    _MK_ENUM_CONST(1)

#define PMC_IMPL_FMON_FAULT_ACTION_OSCnFUSE_CK_0_FMON_ACTION_RESET_REQ_OSCnFUSE_CK_SHIFT                        _MK_SHIFT_CONST(0)
#define PMC_IMPL_FMON_FAULT_ACTION_OSCnFUSE_CK_0_FMON_ACTION_RESET_REQ_OSCnFUSE_CK_FIELD                        _MK_FIELD_CONST(0x1, PMC_IMPL_FMON_FAULT_ACTION_OSCnFUSE_CK_0_FMON_ACTION_RESET_REQ_OSCnFUSE_CK_SHIFT)
#define PMC_IMPL_FMON_FAULT_ACTION_OSCnFUSE_CK_0_FMON_ACTION_RESET_REQ_OSCnFUSE_CK_RANGE                        0:0
#define PMC_IMPL_FMON_FAULT_ACTION_OSCnFUSE_CK_0_FMON_ACTION_RESET_REQ_OSCnFUSE_CK_WOFFSET                      0x0
#define PMC_IMPL_FMON_FAULT_ACTION_OSCnFUSE_CK_0_FMON_ACTION_RESET_REQ_OSCnFUSE_CK_DEFAULT                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_FMON_FAULT_ACTION_OSCnFUSE_CK_0_FMON_ACTION_RESET_REQ_OSCnFUSE_CK_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define PMC_IMPL_FMON_FAULT_ACTION_OSCnFUSE_CK_0_FMON_ACTION_RESET_REQ_OSCnFUSE_CK_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_FMON_FAULT_ACTION_OSCnFUSE_CK_0_FMON_ACTION_RESET_REQ_OSCnFUSE_CK_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_FMON_FAULT_ACTION_OSCnFUSE_CK_0_FMON_ACTION_RESET_REQ_OSCnFUSE_CK_PARITY_PROTECTION                    _MK_MASK_CONST(0x1)
#define PMC_IMPL_FMON_FAULT_ACTION_OSCnFUSE_CK_0_FMON_ACTION_RESET_REQ_OSCnFUSE_CK_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)
#define PMC_IMPL_FMON_FAULT_ACTION_OSCnFUSE_CK_0_FMON_ACTION_RESET_REQ_OSCnFUSE_CK_INIT_ENUM                    DISABLE
#define PMC_IMPL_FMON_FAULT_ACTION_OSCnFUSE_CK_0_FMON_ACTION_RESET_REQ_OSCnFUSE_CK_DISABLE                      _MK_ENUM_CONST(0)
#define PMC_IMPL_FMON_FAULT_ACTION_OSCnFUSE_CK_0_FMON_ACTION_RESET_REQ_OSCnFUSE_CK_ENABLE                       _MK_ENUM_CONST(1)


// Register PMC_IMPL_FMON_CONFIG_OSCnFUSE_CK_0
#define PMC_IMPL_FMON_CONFIG_OSCnFUSE_CK_0                      _MK_ADDR_CONST(0x878)
#define PMC_IMPL_FMON_CONFIG_OSCnFUSE_CK_0_SECURE                       0x0
#define PMC_IMPL_FMON_CONFIG_OSCnFUSE_CK_0_DUAL                         0x0
#define PMC_IMPL_FMON_CONFIG_OSCnFUSE_CK_0_SCR                  OSCnFUSE_CK_SCR_0
#define PMC_IMPL_FMON_CONFIG_OSCnFUSE_CK_0_WORD_COUNT                   0x1
#define PMC_IMPL_FMON_CONFIG_OSCnFUSE_CK_0_RESET_VAL                    _MK_MASK_CONST(0x7f)
#define PMC_IMPL_FMON_CONFIG_OSCnFUSE_CK_0_RESET_MASK                   _MK_MASK_CONST(0x7f)
#define PMC_IMPL_FMON_CONFIG_OSCnFUSE_CK_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define PMC_IMPL_FMON_CONFIG_OSCnFUSE_CK_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_FMON_CONFIG_OSCnFUSE_CK_0_READ_MASK                    _MK_MASK_CONST(0x7f)
#define PMC_IMPL_FMON_CONFIG_OSCnFUSE_CK_0_WRITE_MASK                   _MK_MASK_CONST(0x7f)
#define PMC_IMPL_FMON_CONFIG_OSCnFUSE_CK_0_FMON_REPORT_DC_FAULT_VIOL_OSCnFUSE_CK_SHIFT                  _MK_SHIFT_CONST(6)
#define PMC_IMPL_FMON_CONFIG_OSCnFUSE_CK_0_FMON_REPORT_DC_FAULT_VIOL_OSCnFUSE_CK_FIELD                  _MK_FIELD_CONST(0x1, PMC_IMPL_FMON_CONFIG_OSCnFUSE_CK_0_FMON_REPORT_DC_FAULT_VIOL_OSCnFUSE_CK_SHIFT)
#define PMC_IMPL_FMON_CONFIG_OSCnFUSE_CK_0_FMON_REPORT_DC_FAULT_VIOL_OSCnFUSE_CK_RANGE                  6:6
#define PMC_IMPL_FMON_CONFIG_OSCnFUSE_CK_0_FMON_REPORT_DC_FAULT_VIOL_OSCnFUSE_CK_WOFFSET                        0x0
#define PMC_IMPL_FMON_CONFIG_OSCnFUSE_CK_0_FMON_REPORT_DC_FAULT_VIOL_OSCnFUSE_CK_DEFAULT                        _MK_MASK_CONST(0x1)
#define PMC_IMPL_FMON_CONFIG_OSCnFUSE_CK_0_FMON_REPORT_DC_FAULT_VIOL_OSCnFUSE_CK_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define PMC_IMPL_FMON_CONFIG_OSCnFUSE_CK_0_FMON_REPORT_DC_FAULT_VIOL_OSCnFUSE_CK_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_FMON_CONFIG_OSCnFUSE_CK_0_FMON_REPORT_DC_FAULT_VIOL_OSCnFUSE_CK_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_FMON_CONFIG_OSCnFUSE_CK_0_FMON_REPORT_DC_FAULT_VIOL_OSCnFUSE_CK_PARITY_PROTECTION                      _MK_MASK_CONST(0x1)
#define PMC_IMPL_FMON_CONFIG_OSCnFUSE_CK_0_FMON_REPORT_DC_FAULT_VIOL_OSCnFUSE_CK_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define PMC_IMPL_FMON_CONFIG_OSCnFUSE_CK_0_FMON_REPORT_DC_FAULT_VIOL_OSCnFUSE_CK_INIT_ENUM                      ENABLE
#define PMC_IMPL_FMON_CONFIG_OSCnFUSE_CK_0_FMON_REPORT_DC_FAULT_VIOL_OSCnFUSE_CK_DISABLE                        _MK_ENUM_CONST(0)
#define PMC_IMPL_FMON_CONFIG_OSCnFUSE_CK_0_FMON_REPORT_DC_FAULT_VIOL_OSCnFUSE_CK_ENABLE                 _MK_ENUM_CONST(1)

#define PMC_IMPL_FMON_CONFIG_OSCnFUSE_CK_0_FMON_REPORT_HIGH_THRESH_VIOL_OSCnFUSE_CK_SHIFT                       _MK_SHIFT_CONST(5)
#define PMC_IMPL_FMON_CONFIG_OSCnFUSE_CK_0_FMON_REPORT_HIGH_THRESH_VIOL_OSCnFUSE_CK_FIELD                       _MK_FIELD_CONST(0x1, PMC_IMPL_FMON_CONFIG_OSCnFUSE_CK_0_FMON_REPORT_HIGH_THRESH_VIOL_OSCnFUSE_CK_SHIFT)
#define PMC_IMPL_FMON_CONFIG_OSCnFUSE_CK_0_FMON_REPORT_HIGH_THRESH_VIOL_OSCnFUSE_CK_RANGE                       5:5
#define PMC_IMPL_FMON_CONFIG_OSCnFUSE_CK_0_FMON_REPORT_HIGH_THRESH_VIOL_OSCnFUSE_CK_WOFFSET                     0x0
#define PMC_IMPL_FMON_CONFIG_OSCnFUSE_CK_0_FMON_REPORT_HIGH_THRESH_VIOL_OSCnFUSE_CK_DEFAULT                     _MK_MASK_CONST(0x1)
#define PMC_IMPL_FMON_CONFIG_OSCnFUSE_CK_0_FMON_REPORT_HIGH_THRESH_VIOL_OSCnFUSE_CK_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define PMC_IMPL_FMON_CONFIG_OSCnFUSE_CK_0_FMON_REPORT_HIGH_THRESH_VIOL_OSCnFUSE_CK_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define PMC_IMPL_FMON_CONFIG_OSCnFUSE_CK_0_FMON_REPORT_HIGH_THRESH_VIOL_OSCnFUSE_CK_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_FMON_CONFIG_OSCnFUSE_CK_0_FMON_REPORT_HIGH_THRESH_VIOL_OSCnFUSE_CK_PARITY_PROTECTION                   _MK_MASK_CONST(0x1)
#define PMC_IMPL_FMON_CONFIG_OSCnFUSE_CK_0_FMON_REPORT_HIGH_THRESH_VIOL_OSCnFUSE_CK_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define PMC_IMPL_FMON_CONFIG_OSCnFUSE_CK_0_FMON_REPORT_HIGH_THRESH_VIOL_OSCnFUSE_CK_INIT_ENUM                   ENABLE
#define PMC_IMPL_FMON_CONFIG_OSCnFUSE_CK_0_FMON_REPORT_HIGH_THRESH_VIOL_OSCnFUSE_CK_DISABLE                     _MK_ENUM_CONST(0)
#define PMC_IMPL_FMON_CONFIG_OSCnFUSE_CK_0_FMON_REPORT_HIGH_THRESH_VIOL_OSCnFUSE_CK_ENABLE                      _MK_ENUM_CONST(1)

#define PMC_IMPL_FMON_CONFIG_OSCnFUSE_CK_0_FMON_REPORT_LOW_THRESH_VIOL_OSCnFUSE_CK_SHIFT                        _MK_SHIFT_CONST(4)
#define PMC_IMPL_FMON_CONFIG_OSCnFUSE_CK_0_FMON_REPORT_LOW_THRESH_VIOL_OSCnFUSE_CK_FIELD                        _MK_FIELD_CONST(0x1, PMC_IMPL_FMON_CONFIG_OSCnFUSE_CK_0_FMON_REPORT_LOW_THRESH_VIOL_OSCnFUSE_CK_SHIFT)
#define PMC_IMPL_FMON_CONFIG_OSCnFUSE_CK_0_FMON_REPORT_LOW_THRESH_VIOL_OSCnFUSE_CK_RANGE                        4:4
#define PMC_IMPL_FMON_CONFIG_OSCnFUSE_CK_0_FMON_REPORT_LOW_THRESH_VIOL_OSCnFUSE_CK_WOFFSET                      0x0
#define PMC_IMPL_FMON_CONFIG_OSCnFUSE_CK_0_FMON_REPORT_LOW_THRESH_VIOL_OSCnFUSE_CK_DEFAULT                      _MK_MASK_CONST(0x1)
#define PMC_IMPL_FMON_CONFIG_OSCnFUSE_CK_0_FMON_REPORT_LOW_THRESH_VIOL_OSCnFUSE_CK_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define PMC_IMPL_FMON_CONFIG_OSCnFUSE_CK_0_FMON_REPORT_LOW_THRESH_VIOL_OSCnFUSE_CK_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_FMON_CONFIG_OSCnFUSE_CK_0_FMON_REPORT_LOW_THRESH_VIOL_OSCnFUSE_CK_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_FMON_CONFIG_OSCnFUSE_CK_0_FMON_REPORT_LOW_THRESH_VIOL_OSCnFUSE_CK_PARITY_PROTECTION                    _MK_MASK_CONST(0x1)
#define PMC_IMPL_FMON_CONFIG_OSCnFUSE_CK_0_FMON_REPORT_LOW_THRESH_VIOL_OSCnFUSE_CK_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)
#define PMC_IMPL_FMON_CONFIG_OSCnFUSE_CK_0_FMON_REPORT_LOW_THRESH_VIOL_OSCnFUSE_CK_INIT_ENUM                    ENABLE
#define PMC_IMPL_FMON_CONFIG_OSCnFUSE_CK_0_FMON_REPORT_LOW_THRESH_VIOL_OSCnFUSE_CK_DISABLE                      _MK_ENUM_CONST(0)
#define PMC_IMPL_FMON_CONFIG_OSCnFUSE_CK_0_FMON_REPORT_LOW_THRESH_VIOL_OSCnFUSE_CK_ENABLE                       _MK_ENUM_CONST(1)

#define PMC_IMPL_FMON_CONFIG_OSCnFUSE_CK_0_FMON_REPORT_OVERFLOW_ERROR_OSCnFUSE_CK_SHIFT                 _MK_SHIFT_CONST(3)
#define PMC_IMPL_FMON_CONFIG_OSCnFUSE_CK_0_FMON_REPORT_OVERFLOW_ERROR_OSCnFUSE_CK_FIELD                 _MK_FIELD_CONST(0x1, PMC_IMPL_FMON_CONFIG_OSCnFUSE_CK_0_FMON_REPORT_OVERFLOW_ERROR_OSCnFUSE_CK_SHIFT)
#define PMC_IMPL_FMON_CONFIG_OSCnFUSE_CK_0_FMON_REPORT_OVERFLOW_ERROR_OSCnFUSE_CK_RANGE                 3:3
#define PMC_IMPL_FMON_CONFIG_OSCnFUSE_CK_0_FMON_REPORT_OVERFLOW_ERROR_OSCnFUSE_CK_WOFFSET                       0x0
#define PMC_IMPL_FMON_CONFIG_OSCnFUSE_CK_0_FMON_REPORT_OVERFLOW_ERROR_OSCnFUSE_CK_DEFAULT                       _MK_MASK_CONST(0x1)
#define PMC_IMPL_FMON_CONFIG_OSCnFUSE_CK_0_FMON_REPORT_OVERFLOW_ERROR_OSCnFUSE_CK_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define PMC_IMPL_FMON_CONFIG_OSCnFUSE_CK_0_FMON_REPORT_OVERFLOW_ERROR_OSCnFUSE_CK_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define PMC_IMPL_FMON_CONFIG_OSCnFUSE_CK_0_FMON_REPORT_OVERFLOW_ERROR_OSCnFUSE_CK_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define PMC_IMPL_FMON_CONFIG_OSCnFUSE_CK_0_FMON_REPORT_OVERFLOW_ERROR_OSCnFUSE_CK_PARITY_PROTECTION                     _MK_MASK_CONST(0x1)
#define PMC_IMPL_FMON_CONFIG_OSCnFUSE_CK_0_FMON_REPORT_OVERFLOW_ERROR_OSCnFUSE_CK_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)
#define PMC_IMPL_FMON_CONFIG_OSCnFUSE_CK_0_FMON_REPORT_OVERFLOW_ERROR_OSCnFUSE_CK_INIT_ENUM                     ENABLE
#define PMC_IMPL_FMON_CONFIG_OSCnFUSE_CK_0_FMON_REPORT_OVERFLOW_ERROR_OSCnFUSE_CK_DISABLE                       _MK_ENUM_CONST(0)
#define PMC_IMPL_FMON_CONFIG_OSCnFUSE_CK_0_FMON_REPORT_OVERFLOW_ERROR_OSCnFUSE_CK_ENABLE                        _MK_ENUM_CONST(1)

#define PMC_IMPL_FMON_CONFIG_OSCnFUSE_CK_0_FMON_REF_CLK_WINDOW_EN_OSCnFUSE_CK_SHIFT                     _MK_SHIFT_CONST(2)
#define PMC_IMPL_FMON_CONFIG_OSCnFUSE_CK_0_FMON_REF_CLK_WINDOW_EN_OSCnFUSE_CK_FIELD                     _MK_FIELD_CONST(0x1, PMC_IMPL_FMON_CONFIG_OSCnFUSE_CK_0_FMON_REF_CLK_WINDOW_EN_OSCnFUSE_CK_SHIFT)
#define PMC_IMPL_FMON_CONFIG_OSCnFUSE_CK_0_FMON_REF_CLK_WINDOW_EN_OSCnFUSE_CK_RANGE                     2:2
#define PMC_IMPL_FMON_CONFIG_OSCnFUSE_CK_0_FMON_REF_CLK_WINDOW_EN_OSCnFUSE_CK_WOFFSET                   0x0
#define PMC_IMPL_FMON_CONFIG_OSCnFUSE_CK_0_FMON_REF_CLK_WINDOW_EN_OSCnFUSE_CK_DEFAULT                   _MK_MASK_CONST(0x1)
#define PMC_IMPL_FMON_CONFIG_OSCnFUSE_CK_0_FMON_REF_CLK_WINDOW_EN_OSCnFUSE_CK_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define PMC_IMPL_FMON_CONFIG_OSCnFUSE_CK_0_FMON_REF_CLK_WINDOW_EN_OSCnFUSE_CK_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_FMON_CONFIG_OSCnFUSE_CK_0_FMON_REF_CLK_WINDOW_EN_OSCnFUSE_CK_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_FMON_CONFIG_OSCnFUSE_CK_0_FMON_REF_CLK_WINDOW_EN_OSCnFUSE_CK_PARITY_PROTECTION                 _MK_MASK_CONST(0x1)
#define PMC_IMPL_FMON_CONFIG_OSCnFUSE_CK_0_FMON_REF_CLK_WINDOW_EN_OSCnFUSE_CK_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define PMC_IMPL_FMON_CONFIG_OSCnFUSE_CK_0_FMON_REF_CLK_WINDOW_EN_OSCnFUSE_CK_INIT_ENUM                 ENABLE
#define PMC_IMPL_FMON_CONFIG_OSCnFUSE_CK_0_FMON_REF_CLK_WINDOW_EN_OSCnFUSE_CK_DISABLE                   _MK_ENUM_CONST(0)
#define PMC_IMPL_FMON_CONFIG_OSCnFUSE_CK_0_FMON_REF_CLK_WINDOW_EN_OSCnFUSE_CK_ENABLE                    _MK_ENUM_CONST(1)

#define PMC_IMPL_FMON_CONFIG_OSCnFUSE_CK_0_FMON_ENABLE_FMON_COUNTER_OSCnFUSE_CK_SHIFT                   _MK_SHIFT_CONST(1)
#define PMC_IMPL_FMON_CONFIG_OSCnFUSE_CK_0_FMON_ENABLE_FMON_COUNTER_OSCnFUSE_CK_FIELD                   _MK_FIELD_CONST(0x1, PMC_IMPL_FMON_CONFIG_OSCnFUSE_CK_0_FMON_ENABLE_FMON_COUNTER_OSCnFUSE_CK_SHIFT)
#define PMC_IMPL_FMON_CONFIG_OSCnFUSE_CK_0_FMON_ENABLE_FMON_COUNTER_OSCnFUSE_CK_RANGE                   1:1
#define PMC_IMPL_FMON_CONFIG_OSCnFUSE_CK_0_FMON_ENABLE_FMON_COUNTER_OSCnFUSE_CK_WOFFSET                 0x0
#define PMC_IMPL_FMON_CONFIG_OSCnFUSE_CK_0_FMON_ENABLE_FMON_COUNTER_OSCnFUSE_CK_DEFAULT                 _MK_MASK_CONST(0x1)
#define PMC_IMPL_FMON_CONFIG_OSCnFUSE_CK_0_FMON_ENABLE_FMON_COUNTER_OSCnFUSE_CK_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define PMC_IMPL_FMON_CONFIG_OSCnFUSE_CK_0_FMON_ENABLE_FMON_COUNTER_OSCnFUSE_CK_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_FMON_CONFIG_OSCnFUSE_CK_0_FMON_ENABLE_FMON_COUNTER_OSCnFUSE_CK_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define PMC_IMPL_FMON_CONFIG_OSCnFUSE_CK_0_FMON_ENABLE_FMON_COUNTER_OSCnFUSE_CK_PARITY_PROTECTION                       _MK_MASK_CONST(0x1)
#define PMC_IMPL_FMON_CONFIG_OSCnFUSE_CK_0_FMON_ENABLE_FMON_COUNTER_OSCnFUSE_CK_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define PMC_IMPL_FMON_CONFIG_OSCnFUSE_CK_0_FMON_ENABLE_FMON_COUNTER_OSCnFUSE_CK_INIT_ENUM                       ENABLE
#define PMC_IMPL_FMON_CONFIG_OSCnFUSE_CK_0_FMON_ENABLE_FMON_COUNTER_OSCnFUSE_CK_DISABLE                 _MK_ENUM_CONST(0)
#define PMC_IMPL_FMON_CONFIG_OSCnFUSE_CK_0_FMON_ENABLE_FMON_COUNTER_OSCnFUSE_CK_ENABLE                  _MK_ENUM_CONST(1)

#define PMC_IMPL_FMON_CONFIG_OSCnFUSE_CK_0_FMON_ENABLE_OSCnFUSE_CK_SHIFT                        _MK_SHIFT_CONST(0)
#define PMC_IMPL_FMON_CONFIG_OSCnFUSE_CK_0_FMON_ENABLE_OSCnFUSE_CK_FIELD                        _MK_FIELD_CONST(0x1, PMC_IMPL_FMON_CONFIG_OSCnFUSE_CK_0_FMON_ENABLE_OSCnFUSE_CK_SHIFT)
#define PMC_IMPL_FMON_CONFIG_OSCnFUSE_CK_0_FMON_ENABLE_OSCnFUSE_CK_RANGE                        0:0
#define PMC_IMPL_FMON_CONFIG_OSCnFUSE_CK_0_FMON_ENABLE_OSCnFUSE_CK_WOFFSET                      0x0
#define PMC_IMPL_FMON_CONFIG_OSCnFUSE_CK_0_FMON_ENABLE_OSCnFUSE_CK_DEFAULT                      _MK_MASK_CONST(0x1)
#define PMC_IMPL_FMON_CONFIG_OSCnFUSE_CK_0_FMON_ENABLE_OSCnFUSE_CK_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define PMC_IMPL_FMON_CONFIG_OSCnFUSE_CK_0_FMON_ENABLE_OSCnFUSE_CK_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_FMON_CONFIG_OSCnFUSE_CK_0_FMON_ENABLE_OSCnFUSE_CK_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_FMON_CONFIG_OSCnFUSE_CK_0_FMON_ENABLE_OSCnFUSE_CK_PARITY_PROTECTION                    _MK_MASK_CONST(0x1)
#define PMC_IMPL_FMON_CONFIG_OSCnFUSE_CK_0_FMON_ENABLE_OSCnFUSE_CK_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)
#define PMC_IMPL_FMON_CONFIG_OSCnFUSE_CK_0_FMON_ENABLE_OSCnFUSE_CK_INIT_ENUM                    ENABLE
#define PMC_IMPL_FMON_CONFIG_OSCnFUSE_CK_0_FMON_ENABLE_OSCnFUSE_CK_DISABLE                      _MK_ENUM_CONST(0)
#define PMC_IMPL_FMON_CONFIG_OSCnFUSE_CK_0_FMON_ENABLE_OSCnFUSE_CK_ENABLE                       _MK_ENUM_CONST(1)


// Register PMC_IMPL_FMON_ENABLE_STATUS_OSCnFUSE_CK_0
#define PMC_IMPL_FMON_ENABLE_STATUS_OSCnFUSE_CK_0                       _MK_ADDR_CONST(0x87c)
#define PMC_IMPL_FMON_ENABLE_STATUS_OSCnFUSE_CK_0_SECURE                        0x0
#define PMC_IMPL_FMON_ENABLE_STATUS_OSCnFUSE_CK_0_DUAL                  0x0
#define PMC_IMPL_FMON_ENABLE_STATUS_OSCnFUSE_CK_0_SCR                   OSCnFUSE_CK_SCR_0
#define PMC_IMPL_FMON_ENABLE_STATUS_OSCnFUSE_CK_0_WORD_COUNT                    0x1
#define PMC_IMPL_FMON_ENABLE_STATUS_OSCnFUSE_CK_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_FMON_ENABLE_STATUS_OSCnFUSE_CK_0_RESET_MASK                    _MK_MASK_CONST(0x7)
#define PMC_IMPL_FMON_ENABLE_STATUS_OSCnFUSE_CK_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_FMON_ENABLE_STATUS_OSCnFUSE_CK_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define PMC_IMPL_FMON_ENABLE_STATUS_OSCnFUSE_CK_0_READ_MASK                     _MK_MASK_CONST(0x7)
#define PMC_IMPL_FMON_ENABLE_STATUS_OSCnFUSE_CK_0_WRITE_MASK                    _MK_MASK_CONST(0x0)
#define PMC_IMPL_FMON_ENABLE_STATUS_OSCnFUSE_CK_0_FMON_ENABLE_FMON_CLK_STATUS_OSCnFUSE_CK_SHIFT                 _MK_SHIFT_CONST(2)
#define PMC_IMPL_FMON_ENABLE_STATUS_OSCnFUSE_CK_0_FMON_ENABLE_FMON_CLK_STATUS_OSCnFUSE_CK_FIELD                 _MK_FIELD_CONST(0x1, PMC_IMPL_FMON_ENABLE_STATUS_OSCnFUSE_CK_0_FMON_ENABLE_FMON_CLK_STATUS_OSCnFUSE_CK_SHIFT)
#define PMC_IMPL_FMON_ENABLE_STATUS_OSCnFUSE_CK_0_FMON_ENABLE_FMON_CLK_STATUS_OSCnFUSE_CK_RANGE                 2:2
#define PMC_IMPL_FMON_ENABLE_STATUS_OSCnFUSE_CK_0_FMON_ENABLE_FMON_CLK_STATUS_OSCnFUSE_CK_WOFFSET                       0x0
#define PMC_IMPL_FMON_ENABLE_STATUS_OSCnFUSE_CK_0_FMON_ENABLE_FMON_CLK_STATUS_OSCnFUSE_CK_DEFAULT                       _MK_MASK_CONST(0x0)
#define PMC_IMPL_FMON_ENABLE_STATUS_OSCnFUSE_CK_0_FMON_ENABLE_FMON_CLK_STATUS_OSCnFUSE_CK_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define PMC_IMPL_FMON_ENABLE_STATUS_OSCnFUSE_CK_0_FMON_ENABLE_FMON_CLK_STATUS_OSCnFUSE_CK_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define PMC_IMPL_FMON_ENABLE_STATUS_OSCnFUSE_CK_0_FMON_ENABLE_FMON_CLK_STATUS_OSCnFUSE_CK_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define PMC_IMPL_FMON_ENABLE_STATUS_OSCnFUSE_CK_0_FMON_ENABLE_FMON_CLK_STATUS_OSCnFUSE_CK_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_FMON_ENABLE_STATUS_OSCnFUSE_CK_0_FMON_ENABLE_FMON_CLK_STATUS_OSCnFUSE_CK_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)
#define PMC_IMPL_FMON_ENABLE_STATUS_OSCnFUSE_CK_0_FMON_ENABLE_FMON_CLK_STATUS_OSCnFUSE_CK_INIT_ENUM                     FALSE
#define PMC_IMPL_FMON_ENABLE_STATUS_OSCnFUSE_CK_0_FMON_ENABLE_FMON_CLK_STATUS_OSCnFUSE_CK_FALSE                 _MK_ENUM_CONST(0)
#define PMC_IMPL_FMON_ENABLE_STATUS_OSCnFUSE_CK_0_FMON_ENABLE_FMON_CLK_STATUS_OSCnFUSE_CK_TRUE                  _MK_ENUM_CONST(1)

#define PMC_IMPL_FMON_ENABLE_STATUS_OSCnFUSE_CK_0_FMON_ENABLE_FMON_ERR_CLK_STATUS_OSCnFUSE_CK_SHIFT                     _MK_SHIFT_CONST(1)
#define PMC_IMPL_FMON_ENABLE_STATUS_OSCnFUSE_CK_0_FMON_ENABLE_FMON_ERR_CLK_STATUS_OSCnFUSE_CK_FIELD                     _MK_FIELD_CONST(0x1, PMC_IMPL_FMON_ENABLE_STATUS_OSCnFUSE_CK_0_FMON_ENABLE_FMON_ERR_CLK_STATUS_OSCnFUSE_CK_SHIFT)
#define PMC_IMPL_FMON_ENABLE_STATUS_OSCnFUSE_CK_0_FMON_ENABLE_FMON_ERR_CLK_STATUS_OSCnFUSE_CK_RANGE                     1:1
#define PMC_IMPL_FMON_ENABLE_STATUS_OSCnFUSE_CK_0_FMON_ENABLE_FMON_ERR_CLK_STATUS_OSCnFUSE_CK_WOFFSET                   0x0
#define PMC_IMPL_FMON_ENABLE_STATUS_OSCnFUSE_CK_0_FMON_ENABLE_FMON_ERR_CLK_STATUS_OSCnFUSE_CK_DEFAULT                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_FMON_ENABLE_STATUS_OSCnFUSE_CK_0_FMON_ENABLE_FMON_ERR_CLK_STATUS_OSCnFUSE_CK_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define PMC_IMPL_FMON_ENABLE_STATUS_OSCnFUSE_CK_0_FMON_ENABLE_FMON_ERR_CLK_STATUS_OSCnFUSE_CK_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_FMON_ENABLE_STATUS_OSCnFUSE_CK_0_FMON_ENABLE_FMON_ERR_CLK_STATUS_OSCnFUSE_CK_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_FMON_ENABLE_STATUS_OSCnFUSE_CK_0_FMON_ENABLE_FMON_ERR_CLK_STATUS_OSCnFUSE_CK_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define PMC_IMPL_FMON_ENABLE_STATUS_OSCnFUSE_CK_0_FMON_ENABLE_FMON_ERR_CLK_STATUS_OSCnFUSE_CK_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define PMC_IMPL_FMON_ENABLE_STATUS_OSCnFUSE_CK_0_FMON_ENABLE_FMON_ERR_CLK_STATUS_OSCnFUSE_CK_INIT_ENUM                 FALSE
#define PMC_IMPL_FMON_ENABLE_STATUS_OSCnFUSE_CK_0_FMON_ENABLE_FMON_ERR_CLK_STATUS_OSCnFUSE_CK_FALSE                     _MK_ENUM_CONST(0)
#define PMC_IMPL_FMON_ENABLE_STATUS_OSCnFUSE_CK_0_FMON_ENABLE_FMON_ERR_CLK_STATUS_OSCnFUSE_CK_TRUE                      _MK_ENUM_CONST(1)

#define PMC_IMPL_FMON_ENABLE_STATUS_OSCnFUSE_CK_0_FMON_ENABLE_FMON_REF_CLK_STATUS_OSCnFUSE_CK_SHIFT                     _MK_SHIFT_CONST(0)
#define PMC_IMPL_FMON_ENABLE_STATUS_OSCnFUSE_CK_0_FMON_ENABLE_FMON_REF_CLK_STATUS_OSCnFUSE_CK_FIELD                     _MK_FIELD_CONST(0x1, PMC_IMPL_FMON_ENABLE_STATUS_OSCnFUSE_CK_0_FMON_ENABLE_FMON_REF_CLK_STATUS_OSCnFUSE_CK_SHIFT)
#define PMC_IMPL_FMON_ENABLE_STATUS_OSCnFUSE_CK_0_FMON_ENABLE_FMON_REF_CLK_STATUS_OSCnFUSE_CK_RANGE                     0:0
#define PMC_IMPL_FMON_ENABLE_STATUS_OSCnFUSE_CK_0_FMON_ENABLE_FMON_REF_CLK_STATUS_OSCnFUSE_CK_WOFFSET                   0x0
#define PMC_IMPL_FMON_ENABLE_STATUS_OSCnFUSE_CK_0_FMON_ENABLE_FMON_REF_CLK_STATUS_OSCnFUSE_CK_DEFAULT                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_FMON_ENABLE_STATUS_OSCnFUSE_CK_0_FMON_ENABLE_FMON_REF_CLK_STATUS_OSCnFUSE_CK_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define PMC_IMPL_FMON_ENABLE_STATUS_OSCnFUSE_CK_0_FMON_ENABLE_FMON_REF_CLK_STATUS_OSCnFUSE_CK_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_FMON_ENABLE_STATUS_OSCnFUSE_CK_0_FMON_ENABLE_FMON_REF_CLK_STATUS_OSCnFUSE_CK_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_FMON_ENABLE_STATUS_OSCnFUSE_CK_0_FMON_ENABLE_FMON_REF_CLK_STATUS_OSCnFUSE_CK_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define PMC_IMPL_FMON_ENABLE_STATUS_OSCnFUSE_CK_0_FMON_ENABLE_FMON_REF_CLK_STATUS_OSCnFUSE_CK_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define PMC_IMPL_FMON_ENABLE_STATUS_OSCnFUSE_CK_0_FMON_ENABLE_FMON_REF_CLK_STATUS_OSCnFUSE_CK_INIT_ENUM                 FALSE
#define PMC_IMPL_FMON_ENABLE_STATUS_OSCnFUSE_CK_0_FMON_ENABLE_FMON_REF_CLK_STATUS_OSCnFUSE_CK_FALSE                     _MK_ENUM_CONST(0)
#define PMC_IMPL_FMON_ENABLE_STATUS_OSCnFUSE_CK_0_FMON_ENABLE_FMON_REF_CLK_STATUS_OSCnFUSE_CK_TRUE                      _MK_ENUM_CONST(1)


// Register PMC_IMPL_FMON_FAULT_STATUS_OSCnFUSE_CK_0
#define PMC_IMPL_FMON_FAULT_STATUS_OSCnFUSE_CK_0                        _MK_ADDR_CONST(0x880)
#define PMC_IMPL_FMON_FAULT_STATUS_OSCnFUSE_CK_0_SECURE                         0x0
#define PMC_IMPL_FMON_FAULT_STATUS_OSCnFUSE_CK_0_DUAL                   0x0
#define PMC_IMPL_FMON_FAULT_STATUS_OSCnFUSE_CK_0_SCR                    OSCnFUSE_CK_SCR_0
#define PMC_IMPL_FMON_FAULT_STATUS_OSCnFUSE_CK_0_WORD_COUNT                     0x1
#define PMC_IMPL_FMON_FAULT_STATUS_OSCnFUSE_CK_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_FMON_FAULT_STATUS_OSCnFUSE_CK_0_RESET_MASK                     _MK_MASK_CONST(0x8000001f)
#define PMC_IMPL_FMON_FAULT_STATUS_OSCnFUSE_CK_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define PMC_IMPL_FMON_FAULT_STATUS_OSCnFUSE_CK_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_FMON_FAULT_STATUS_OSCnFUSE_CK_0_READ_MASK                      _MK_MASK_CONST(0x8000001f)
#define PMC_IMPL_FMON_FAULT_STATUS_OSCnFUSE_CK_0_WRITE_MASK                     _MK_MASK_CONST(0x80000000)
#define PMC_IMPL_FMON_FAULT_STATUS_OSCnFUSE_CK_0_FMON_FAULT_CLEAR_OSCnFUSE_CK_SHIFT                     _MK_SHIFT_CONST(31)
#define PMC_IMPL_FMON_FAULT_STATUS_OSCnFUSE_CK_0_FMON_FAULT_CLEAR_OSCnFUSE_CK_FIELD                     _MK_FIELD_CONST(0x1, PMC_IMPL_FMON_FAULT_STATUS_OSCnFUSE_CK_0_FMON_FAULT_CLEAR_OSCnFUSE_CK_SHIFT)
#define PMC_IMPL_FMON_FAULT_STATUS_OSCnFUSE_CK_0_FMON_FAULT_CLEAR_OSCnFUSE_CK_RANGE                     31:31
#define PMC_IMPL_FMON_FAULT_STATUS_OSCnFUSE_CK_0_FMON_FAULT_CLEAR_OSCnFUSE_CK_WOFFSET                   0x0
#define PMC_IMPL_FMON_FAULT_STATUS_OSCnFUSE_CK_0_FMON_FAULT_CLEAR_OSCnFUSE_CK_DEFAULT                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_FMON_FAULT_STATUS_OSCnFUSE_CK_0_FMON_FAULT_CLEAR_OSCnFUSE_CK_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define PMC_IMPL_FMON_FAULT_STATUS_OSCnFUSE_CK_0_FMON_FAULT_CLEAR_OSCnFUSE_CK_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_FMON_FAULT_STATUS_OSCnFUSE_CK_0_FMON_FAULT_CLEAR_OSCnFUSE_CK_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_FMON_FAULT_STATUS_OSCnFUSE_CK_0_FMON_FAULT_CLEAR_OSCnFUSE_CK_PARITY_PROTECTION                 _MK_MASK_CONST(0x1)
#define PMC_IMPL_FMON_FAULT_STATUS_OSCnFUSE_CK_0_FMON_FAULT_CLEAR_OSCnFUSE_CK_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define PMC_IMPL_FMON_FAULT_STATUS_OSCnFUSE_CK_0_FMON_FAULT_CLEAR_OSCnFUSE_CK_INIT_ENUM                 FALSE
#define PMC_IMPL_FMON_FAULT_STATUS_OSCnFUSE_CK_0_FMON_FAULT_CLEAR_OSCnFUSE_CK_FALSE                     _MK_ENUM_CONST(0)
#define PMC_IMPL_FMON_FAULT_STATUS_OSCnFUSE_CK_0_FMON_FAULT_CLEAR_OSCnFUSE_CK_TRUE                      _MK_ENUM_CONST(1)

#define PMC_IMPL_FMON_FAULT_STATUS_OSCnFUSE_CK_0_FMON_FAULT_OUT_STATUS_OSCnFUSE_CK_SHIFT                        _MK_SHIFT_CONST(4)
#define PMC_IMPL_FMON_FAULT_STATUS_OSCnFUSE_CK_0_FMON_FAULT_OUT_STATUS_OSCnFUSE_CK_FIELD                        _MK_FIELD_CONST(0x1, PMC_IMPL_FMON_FAULT_STATUS_OSCnFUSE_CK_0_FMON_FAULT_OUT_STATUS_OSCnFUSE_CK_SHIFT)
#define PMC_IMPL_FMON_FAULT_STATUS_OSCnFUSE_CK_0_FMON_FAULT_OUT_STATUS_OSCnFUSE_CK_RANGE                        4:4
#define PMC_IMPL_FMON_FAULT_STATUS_OSCnFUSE_CK_0_FMON_FAULT_OUT_STATUS_OSCnFUSE_CK_WOFFSET                      0x0
#define PMC_IMPL_FMON_FAULT_STATUS_OSCnFUSE_CK_0_FMON_FAULT_OUT_STATUS_OSCnFUSE_CK_DEFAULT                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_FMON_FAULT_STATUS_OSCnFUSE_CK_0_FMON_FAULT_OUT_STATUS_OSCnFUSE_CK_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define PMC_IMPL_FMON_FAULT_STATUS_OSCnFUSE_CK_0_FMON_FAULT_OUT_STATUS_OSCnFUSE_CK_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_FMON_FAULT_STATUS_OSCnFUSE_CK_0_FMON_FAULT_OUT_STATUS_OSCnFUSE_CK_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_FMON_FAULT_STATUS_OSCnFUSE_CK_0_FMON_FAULT_OUT_STATUS_OSCnFUSE_CK_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define PMC_IMPL_FMON_FAULT_STATUS_OSCnFUSE_CK_0_FMON_FAULT_OUT_STATUS_OSCnFUSE_CK_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)
#define PMC_IMPL_FMON_FAULT_STATUS_OSCnFUSE_CK_0_FMON_FAULT_OUT_STATUS_OSCnFUSE_CK_INIT_ENUM                    FALSE
#define PMC_IMPL_FMON_FAULT_STATUS_OSCnFUSE_CK_0_FMON_FAULT_OUT_STATUS_OSCnFUSE_CK_FALSE                        _MK_ENUM_CONST(0)
#define PMC_IMPL_FMON_FAULT_STATUS_OSCnFUSE_CK_0_FMON_FAULT_OUT_STATUS_OSCnFUSE_CK_TRUE                 _MK_ENUM_CONST(1)

#define PMC_IMPL_FMON_FAULT_STATUS_OSCnFUSE_CK_0_FMON_OVERFLOW_ERROR_OSCnFUSE_CK_SHIFT                  _MK_SHIFT_CONST(3)
#define PMC_IMPL_FMON_FAULT_STATUS_OSCnFUSE_CK_0_FMON_OVERFLOW_ERROR_OSCnFUSE_CK_FIELD                  _MK_FIELD_CONST(0x1, PMC_IMPL_FMON_FAULT_STATUS_OSCnFUSE_CK_0_FMON_OVERFLOW_ERROR_OSCnFUSE_CK_SHIFT)
#define PMC_IMPL_FMON_FAULT_STATUS_OSCnFUSE_CK_0_FMON_OVERFLOW_ERROR_OSCnFUSE_CK_RANGE                  3:3
#define PMC_IMPL_FMON_FAULT_STATUS_OSCnFUSE_CK_0_FMON_OVERFLOW_ERROR_OSCnFUSE_CK_WOFFSET                        0x0
#define PMC_IMPL_FMON_FAULT_STATUS_OSCnFUSE_CK_0_FMON_OVERFLOW_ERROR_OSCnFUSE_CK_DEFAULT                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_FMON_FAULT_STATUS_OSCnFUSE_CK_0_FMON_OVERFLOW_ERROR_OSCnFUSE_CK_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define PMC_IMPL_FMON_FAULT_STATUS_OSCnFUSE_CK_0_FMON_OVERFLOW_ERROR_OSCnFUSE_CK_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_FMON_FAULT_STATUS_OSCnFUSE_CK_0_FMON_OVERFLOW_ERROR_OSCnFUSE_CK_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_FMON_FAULT_STATUS_OSCnFUSE_CK_0_FMON_OVERFLOW_ERROR_OSCnFUSE_CK_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_FMON_FAULT_STATUS_OSCnFUSE_CK_0_FMON_OVERFLOW_ERROR_OSCnFUSE_CK_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define PMC_IMPL_FMON_FAULT_STATUS_OSCnFUSE_CK_0_FMON_OVERFLOW_ERROR_OSCnFUSE_CK_INIT_ENUM                      FALSE
#define PMC_IMPL_FMON_FAULT_STATUS_OSCnFUSE_CK_0_FMON_OVERFLOW_ERROR_OSCnFUSE_CK_FALSE                  _MK_ENUM_CONST(0)
#define PMC_IMPL_FMON_FAULT_STATUS_OSCnFUSE_CK_0_FMON_OVERFLOW_ERROR_OSCnFUSE_CK_TRUE                   _MK_ENUM_CONST(1)

#define PMC_IMPL_FMON_FAULT_STATUS_OSCnFUSE_CK_0_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_OSCnFUSE_CK_SHIFT                  _MK_SHIFT_CONST(2)
#define PMC_IMPL_FMON_FAULT_STATUS_OSCnFUSE_CK_0_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_OSCnFUSE_CK_FIELD                  _MK_FIELD_CONST(0x1, PMC_IMPL_FMON_FAULT_STATUS_OSCnFUSE_CK_0_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_OSCnFUSE_CK_SHIFT)
#define PMC_IMPL_FMON_FAULT_STATUS_OSCnFUSE_CK_0_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_OSCnFUSE_CK_RANGE                  2:2
#define PMC_IMPL_FMON_FAULT_STATUS_OSCnFUSE_CK_0_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_OSCnFUSE_CK_WOFFSET                        0x0
#define PMC_IMPL_FMON_FAULT_STATUS_OSCnFUSE_CK_0_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_OSCnFUSE_CK_DEFAULT                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_FMON_FAULT_STATUS_OSCnFUSE_CK_0_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_OSCnFUSE_CK_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define PMC_IMPL_FMON_FAULT_STATUS_OSCnFUSE_CK_0_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_OSCnFUSE_CK_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_FMON_FAULT_STATUS_OSCnFUSE_CK_0_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_OSCnFUSE_CK_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_FMON_FAULT_STATUS_OSCnFUSE_CK_0_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_OSCnFUSE_CK_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_FMON_FAULT_STATUS_OSCnFUSE_CK_0_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_OSCnFUSE_CK_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define PMC_IMPL_FMON_FAULT_STATUS_OSCnFUSE_CK_0_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_OSCnFUSE_CK_INIT_ENUM                      FALSE
#define PMC_IMPL_FMON_FAULT_STATUS_OSCnFUSE_CK_0_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_OSCnFUSE_CK_FALSE                  _MK_ENUM_CONST(0)
#define PMC_IMPL_FMON_FAULT_STATUS_OSCnFUSE_CK_0_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_OSCnFUSE_CK_TRUE                   _MK_ENUM_CONST(1)

#define PMC_IMPL_FMON_FAULT_STATUS_OSCnFUSE_CK_0_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_OSCnFUSE_CK_SHIFT                   _MK_SHIFT_CONST(1)
#define PMC_IMPL_FMON_FAULT_STATUS_OSCnFUSE_CK_0_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_OSCnFUSE_CK_FIELD                   _MK_FIELD_CONST(0x1, PMC_IMPL_FMON_FAULT_STATUS_OSCnFUSE_CK_0_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_OSCnFUSE_CK_SHIFT)
#define PMC_IMPL_FMON_FAULT_STATUS_OSCnFUSE_CK_0_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_OSCnFUSE_CK_RANGE                   1:1
#define PMC_IMPL_FMON_FAULT_STATUS_OSCnFUSE_CK_0_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_OSCnFUSE_CK_WOFFSET                 0x0
#define PMC_IMPL_FMON_FAULT_STATUS_OSCnFUSE_CK_0_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_OSCnFUSE_CK_DEFAULT                 _MK_MASK_CONST(0x0)
#define PMC_IMPL_FMON_FAULT_STATUS_OSCnFUSE_CK_0_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_OSCnFUSE_CK_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define PMC_IMPL_FMON_FAULT_STATUS_OSCnFUSE_CK_0_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_OSCnFUSE_CK_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_FMON_FAULT_STATUS_OSCnFUSE_CK_0_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_OSCnFUSE_CK_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define PMC_IMPL_FMON_FAULT_STATUS_OSCnFUSE_CK_0_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_OSCnFUSE_CK_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define PMC_IMPL_FMON_FAULT_STATUS_OSCnFUSE_CK_0_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_OSCnFUSE_CK_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define PMC_IMPL_FMON_FAULT_STATUS_OSCnFUSE_CK_0_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_OSCnFUSE_CK_INIT_ENUM                       FALSE
#define PMC_IMPL_FMON_FAULT_STATUS_OSCnFUSE_CK_0_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_OSCnFUSE_CK_FALSE                   _MK_ENUM_CONST(0)
#define PMC_IMPL_FMON_FAULT_STATUS_OSCnFUSE_CK_0_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_OSCnFUSE_CK_TRUE                    _MK_ENUM_CONST(1)

#define PMC_IMPL_FMON_FAULT_STATUS_OSCnFUSE_CK_0_FMON_DC_FAULT_OSCnFUSE_CK_SHIFT                        _MK_SHIFT_CONST(0)
#define PMC_IMPL_FMON_FAULT_STATUS_OSCnFUSE_CK_0_FMON_DC_FAULT_OSCnFUSE_CK_FIELD                        _MK_FIELD_CONST(0x1, PMC_IMPL_FMON_FAULT_STATUS_OSCnFUSE_CK_0_FMON_DC_FAULT_OSCnFUSE_CK_SHIFT)
#define PMC_IMPL_FMON_FAULT_STATUS_OSCnFUSE_CK_0_FMON_DC_FAULT_OSCnFUSE_CK_RANGE                        0:0
#define PMC_IMPL_FMON_FAULT_STATUS_OSCnFUSE_CK_0_FMON_DC_FAULT_OSCnFUSE_CK_WOFFSET                      0x0
#define PMC_IMPL_FMON_FAULT_STATUS_OSCnFUSE_CK_0_FMON_DC_FAULT_OSCnFUSE_CK_DEFAULT                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_FMON_FAULT_STATUS_OSCnFUSE_CK_0_FMON_DC_FAULT_OSCnFUSE_CK_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define PMC_IMPL_FMON_FAULT_STATUS_OSCnFUSE_CK_0_FMON_DC_FAULT_OSCnFUSE_CK_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_FMON_FAULT_STATUS_OSCnFUSE_CK_0_FMON_DC_FAULT_OSCnFUSE_CK_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_FMON_FAULT_STATUS_OSCnFUSE_CK_0_FMON_DC_FAULT_OSCnFUSE_CK_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define PMC_IMPL_FMON_FAULT_STATUS_OSCnFUSE_CK_0_FMON_DC_FAULT_OSCnFUSE_CK_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)
#define PMC_IMPL_FMON_FAULT_STATUS_OSCnFUSE_CK_0_FMON_DC_FAULT_OSCnFUSE_CK_INIT_ENUM                    FALSE
#define PMC_IMPL_FMON_FAULT_STATUS_OSCnFUSE_CK_0_FMON_DC_FAULT_OSCnFUSE_CK_FALSE                        _MK_ENUM_CONST(0)
#define PMC_IMPL_FMON_FAULT_STATUS_OSCnFUSE_CK_0_FMON_DC_FAULT_OSCnFUSE_CK_TRUE                 _MK_ENUM_CONST(1)


// Register PMC_IMPL_FMON_LOAD_DATA_CTRL_OSCnFUSE_CK_0
#define PMC_IMPL_FMON_LOAD_DATA_CTRL_OSCnFUSE_CK_0                      _MK_ADDR_CONST(0x884)
#define PMC_IMPL_FMON_LOAD_DATA_CTRL_OSCnFUSE_CK_0_SECURE                       0x0
#define PMC_IMPL_FMON_LOAD_DATA_CTRL_OSCnFUSE_CK_0_DUAL                         0x0
#define PMC_IMPL_FMON_LOAD_DATA_CTRL_OSCnFUSE_CK_0_SCR                  OSCnFUSE_CK_SCR_0
#define PMC_IMPL_FMON_LOAD_DATA_CTRL_OSCnFUSE_CK_0_WORD_COUNT                   0x1
#define PMC_IMPL_FMON_LOAD_DATA_CTRL_OSCnFUSE_CK_0_RESET_VAL                    _MK_MASK_CONST(0x0)
#define PMC_IMPL_FMON_LOAD_DATA_CTRL_OSCnFUSE_CK_0_RESET_MASK                   _MK_MASK_CONST(0x80000007)
#define PMC_IMPL_FMON_LOAD_DATA_CTRL_OSCnFUSE_CK_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define PMC_IMPL_FMON_LOAD_DATA_CTRL_OSCnFUSE_CK_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_FMON_LOAD_DATA_CTRL_OSCnFUSE_CK_0_READ_MASK                    _MK_MASK_CONST(0x80000007)
#define PMC_IMPL_FMON_LOAD_DATA_CTRL_OSCnFUSE_CK_0_WRITE_MASK                   _MK_MASK_CONST(0x80000007)
#define PMC_IMPL_FMON_LOAD_DATA_CTRL_OSCnFUSE_CK_0_FMON_LOAD_DATA_OSCnFUSE_CK_SHIFT                     _MK_SHIFT_CONST(31)
#define PMC_IMPL_FMON_LOAD_DATA_CTRL_OSCnFUSE_CK_0_FMON_LOAD_DATA_OSCnFUSE_CK_FIELD                     _MK_FIELD_CONST(0x1, PMC_IMPL_FMON_LOAD_DATA_CTRL_OSCnFUSE_CK_0_FMON_LOAD_DATA_OSCnFUSE_CK_SHIFT)
#define PMC_IMPL_FMON_LOAD_DATA_CTRL_OSCnFUSE_CK_0_FMON_LOAD_DATA_OSCnFUSE_CK_RANGE                     31:31
#define PMC_IMPL_FMON_LOAD_DATA_CTRL_OSCnFUSE_CK_0_FMON_LOAD_DATA_OSCnFUSE_CK_WOFFSET                   0x0
#define PMC_IMPL_FMON_LOAD_DATA_CTRL_OSCnFUSE_CK_0_FMON_LOAD_DATA_OSCnFUSE_CK_DEFAULT                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_FMON_LOAD_DATA_CTRL_OSCnFUSE_CK_0_FMON_LOAD_DATA_OSCnFUSE_CK_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define PMC_IMPL_FMON_LOAD_DATA_CTRL_OSCnFUSE_CK_0_FMON_LOAD_DATA_OSCnFUSE_CK_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_FMON_LOAD_DATA_CTRL_OSCnFUSE_CK_0_FMON_LOAD_DATA_OSCnFUSE_CK_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_FMON_LOAD_DATA_CTRL_OSCnFUSE_CK_0_FMON_LOAD_DATA_OSCnFUSE_CK_PARITY_PROTECTION                 _MK_MASK_CONST(0x1)
#define PMC_IMPL_FMON_LOAD_DATA_CTRL_OSCnFUSE_CK_0_FMON_LOAD_DATA_OSCnFUSE_CK_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define PMC_IMPL_FMON_LOAD_DATA_CTRL_OSCnFUSE_CK_0_FMON_LOAD_DATA_OSCnFUSE_CK_INIT_ENUM                 DISABLE
#define PMC_IMPL_FMON_LOAD_DATA_CTRL_OSCnFUSE_CK_0_FMON_LOAD_DATA_OSCnFUSE_CK_DISABLE                   _MK_ENUM_CONST(0)
#define PMC_IMPL_FMON_LOAD_DATA_CTRL_OSCnFUSE_CK_0_FMON_LOAD_DATA_OSCnFUSE_CK_ENABLE                    _MK_ENUM_CONST(1)

#define PMC_IMPL_FMON_LOAD_DATA_CTRL_OSCnFUSE_CK_0_FMON_LOAD_DATA_SEL_OSCnFUSE_CK_SHIFT                 _MK_SHIFT_CONST(0)
#define PMC_IMPL_FMON_LOAD_DATA_CTRL_OSCnFUSE_CK_0_FMON_LOAD_DATA_SEL_OSCnFUSE_CK_FIELD                 _MK_FIELD_CONST(0x7, PMC_IMPL_FMON_LOAD_DATA_CTRL_OSCnFUSE_CK_0_FMON_LOAD_DATA_SEL_OSCnFUSE_CK_SHIFT)
#define PMC_IMPL_FMON_LOAD_DATA_CTRL_OSCnFUSE_CK_0_FMON_LOAD_DATA_SEL_OSCnFUSE_CK_RANGE                 2:0
#define PMC_IMPL_FMON_LOAD_DATA_CTRL_OSCnFUSE_CK_0_FMON_LOAD_DATA_SEL_OSCnFUSE_CK_WOFFSET                       0x0
#define PMC_IMPL_FMON_LOAD_DATA_CTRL_OSCnFUSE_CK_0_FMON_LOAD_DATA_SEL_OSCnFUSE_CK_DEFAULT                       _MK_MASK_CONST(0x0)
#define PMC_IMPL_FMON_LOAD_DATA_CTRL_OSCnFUSE_CK_0_FMON_LOAD_DATA_SEL_OSCnFUSE_CK_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
#define PMC_IMPL_FMON_LOAD_DATA_CTRL_OSCnFUSE_CK_0_FMON_LOAD_DATA_SEL_OSCnFUSE_CK_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define PMC_IMPL_FMON_LOAD_DATA_CTRL_OSCnFUSE_CK_0_FMON_LOAD_DATA_SEL_OSCnFUSE_CK_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define PMC_IMPL_FMON_LOAD_DATA_CTRL_OSCnFUSE_CK_0_FMON_LOAD_DATA_SEL_OSCnFUSE_CK_PARITY_PROTECTION                     _MK_MASK_CONST(0x1)
#define PMC_IMPL_FMON_LOAD_DATA_CTRL_OSCnFUSE_CK_0_FMON_LOAD_DATA_SEL_OSCnFUSE_CK_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)
#define PMC_IMPL_FMON_LOAD_DATA_CTRL_OSCnFUSE_CK_0_FMON_LOAD_DATA_SEL_OSCnFUSE_CK_INIT_ENUM                     DISABLE
#define PMC_IMPL_FMON_LOAD_DATA_CTRL_OSCnFUSE_CK_0_FMON_LOAD_DATA_SEL_OSCnFUSE_CK_DISABLE                       _MK_ENUM_CONST(0)
#define PMC_IMPL_FMON_LOAD_DATA_CTRL_OSCnFUSE_CK_0_FMON_LOAD_DATA_SEL_OSCnFUSE_CK_ENABLE                        _MK_ENUM_CONST(1)


// Register PMC_IMPL_FMON_LOAD_DATA_STATUS_0_OSCnFUSE_CK_0
#define PMC_IMPL_FMON_LOAD_DATA_STATUS_0_OSCnFUSE_CK_0                  _MK_ADDR_CONST(0x888)
#define PMC_IMPL_FMON_LOAD_DATA_STATUS_0_OSCnFUSE_CK_0_SECURE                   0x0
#define PMC_IMPL_FMON_LOAD_DATA_STATUS_0_OSCnFUSE_CK_0_DUAL                     0x0
#define PMC_IMPL_FMON_LOAD_DATA_STATUS_0_OSCnFUSE_CK_0_SCR                      OSCnFUSE_CK_SCR_0
#define PMC_IMPL_FMON_LOAD_DATA_STATUS_0_OSCnFUSE_CK_0_WORD_COUNT                       0x1
#define PMC_IMPL_FMON_LOAD_DATA_STATUS_0_OSCnFUSE_CK_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_FMON_LOAD_DATA_STATUS_0_OSCnFUSE_CK_0_RESET_MASK                       _MK_MASK_CONST(0x1)
#define PMC_IMPL_FMON_LOAD_DATA_STATUS_0_OSCnFUSE_CK_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_FMON_LOAD_DATA_STATUS_0_OSCnFUSE_CK_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define PMC_IMPL_FMON_LOAD_DATA_STATUS_0_OSCnFUSE_CK_0_READ_MASK                        _MK_MASK_CONST(0x1)
#define PMC_IMPL_FMON_LOAD_DATA_STATUS_0_OSCnFUSE_CK_0_WRITE_MASK                       _MK_MASK_CONST(0x0)
#define PMC_IMPL_FMON_LOAD_DATA_STATUS_0_OSCnFUSE_CK_0_FMON_LOAD_DATA_DONE_OSCnFUSE_CK_SHIFT                    _MK_SHIFT_CONST(0)
#define PMC_IMPL_FMON_LOAD_DATA_STATUS_0_OSCnFUSE_CK_0_FMON_LOAD_DATA_DONE_OSCnFUSE_CK_FIELD                    _MK_FIELD_CONST(0x1, PMC_IMPL_FMON_LOAD_DATA_STATUS_0_OSCnFUSE_CK_0_FMON_LOAD_DATA_DONE_OSCnFUSE_CK_SHIFT)
#define PMC_IMPL_FMON_LOAD_DATA_STATUS_0_OSCnFUSE_CK_0_FMON_LOAD_DATA_DONE_OSCnFUSE_CK_RANGE                    0:0
#define PMC_IMPL_FMON_LOAD_DATA_STATUS_0_OSCnFUSE_CK_0_FMON_LOAD_DATA_DONE_OSCnFUSE_CK_WOFFSET                  0x0
#define PMC_IMPL_FMON_LOAD_DATA_STATUS_0_OSCnFUSE_CK_0_FMON_LOAD_DATA_DONE_OSCnFUSE_CK_DEFAULT                  _MK_MASK_CONST(0x0)
#define PMC_IMPL_FMON_LOAD_DATA_STATUS_0_OSCnFUSE_CK_0_FMON_LOAD_DATA_DONE_OSCnFUSE_CK_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define PMC_IMPL_FMON_LOAD_DATA_STATUS_0_OSCnFUSE_CK_0_FMON_LOAD_DATA_DONE_OSCnFUSE_CK_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define PMC_IMPL_FMON_LOAD_DATA_STATUS_0_OSCnFUSE_CK_0_FMON_LOAD_DATA_DONE_OSCnFUSE_CK_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define PMC_IMPL_FMON_LOAD_DATA_STATUS_0_OSCnFUSE_CK_0_FMON_LOAD_DATA_DONE_OSCnFUSE_CK_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_FMON_LOAD_DATA_STATUS_0_OSCnFUSE_CK_0_FMON_LOAD_DATA_DONE_OSCnFUSE_CK_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)
#define PMC_IMPL_FMON_LOAD_DATA_STATUS_0_OSCnFUSE_CK_0_FMON_LOAD_DATA_DONE_OSCnFUSE_CK_INIT_ENUM                        DISABLE
#define PMC_IMPL_FMON_LOAD_DATA_STATUS_0_OSCnFUSE_CK_0_FMON_LOAD_DATA_DONE_OSCnFUSE_CK_DISABLE                  _MK_ENUM_CONST(0)
#define PMC_IMPL_FMON_LOAD_DATA_STATUS_0_OSCnFUSE_CK_0_FMON_LOAD_DATA_DONE_OSCnFUSE_CK_ENABLE                   _MK_ENUM_CONST(1)


// Register PMC_IMPL_FMON_LOAD_DATA_STATUS_1_OSCnFUSE_CK_0
#define PMC_IMPL_FMON_LOAD_DATA_STATUS_1_OSCnFUSE_CK_0                  _MK_ADDR_CONST(0x88c)
#define PMC_IMPL_FMON_LOAD_DATA_STATUS_1_OSCnFUSE_CK_0_SECURE                   0x0
#define PMC_IMPL_FMON_LOAD_DATA_STATUS_1_OSCnFUSE_CK_0_DUAL                     0x0
#define PMC_IMPL_FMON_LOAD_DATA_STATUS_1_OSCnFUSE_CK_0_SCR                      OSCnFUSE_CK_SCR_0
#define PMC_IMPL_FMON_LOAD_DATA_STATUS_1_OSCnFUSE_CK_0_WORD_COUNT                       0x1
#define PMC_IMPL_FMON_LOAD_DATA_STATUS_1_OSCnFUSE_CK_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_FMON_LOAD_DATA_STATUS_1_OSCnFUSE_CK_0_RESET_MASK                       _MK_MASK_CONST(0x7)
#define PMC_IMPL_FMON_LOAD_DATA_STATUS_1_OSCnFUSE_CK_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_FMON_LOAD_DATA_STATUS_1_OSCnFUSE_CK_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define PMC_IMPL_FMON_LOAD_DATA_STATUS_1_OSCnFUSE_CK_0_READ_MASK                        _MK_MASK_CONST(0x7)
#define PMC_IMPL_FMON_LOAD_DATA_STATUS_1_OSCnFUSE_CK_0_WRITE_MASK                       _MK_MASK_CONST(0x0)
#define PMC_IMPL_FMON_LOAD_DATA_STATUS_1_OSCnFUSE_CK_0_FMON_LOAD_DATA_SEL_STATUS_OSCnFUSE_CK_SHIFT                      _MK_SHIFT_CONST(0)
#define PMC_IMPL_FMON_LOAD_DATA_STATUS_1_OSCnFUSE_CK_0_FMON_LOAD_DATA_SEL_STATUS_OSCnFUSE_CK_FIELD                      _MK_FIELD_CONST(0x7, PMC_IMPL_FMON_LOAD_DATA_STATUS_1_OSCnFUSE_CK_0_FMON_LOAD_DATA_SEL_STATUS_OSCnFUSE_CK_SHIFT)
#define PMC_IMPL_FMON_LOAD_DATA_STATUS_1_OSCnFUSE_CK_0_FMON_LOAD_DATA_SEL_STATUS_OSCnFUSE_CK_RANGE                      2:0
#define PMC_IMPL_FMON_LOAD_DATA_STATUS_1_OSCnFUSE_CK_0_FMON_LOAD_DATA_SEL_STATUS_OSCnFUSE_CK_WOFFSET                    0x0
#define PMC_IMPL_FMON_LOAD_DATA_STATUS_1_OSCnFUSE_CK_0_FMON_LOAD_DATA_SEL_STATUS_OSCnFUSE_CK_DEFAULT                    _MK_MASK_CONST(0x0)
#define PMC_IMPL_FMON_LOAD_DATA_STATUS_1_OSCnFUSE_CK_0_FMON_LOAD_DATA_SEL_STATUS_OSCnFUSE_CK_DEFAULT_MASK                       _MK_MASK_CONST(0x7)
#define PMC_IMPL_FMON_LOAD_DATA_STATUS_1_OSCnFUSE_CK_0_FMON_LOAD_DATA_SEL_STATUS_OSCnFUSE_CK_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define PMC_IMPL_FMON_LOAD_DATA_STATUS_1_OSCnFUSE_CK_0_FMON_LOAD_DATA_SEL_STATUS_OSCnFUSE_CK_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define PMC_IMPL_FMON_LOAD_DATA_STATUS_1_OSCnFUSE_CK_0_FMON_LOAD_DATA_SEL_STATUS_OSCnFUSE_CK_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define PMC_IMPL_FMON_LOAD_DATA_STATUS_1_OSCnFUSE_CK_0_FMON_LOAD_DATA_SEL_STATUS_OSCnFUSE_CK_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)


// Register PMC_IMPL_FMON_LOAD_DATA_STATUS_2_OSCnFUSE_CK_0
#define PMC_IMPL_FMON_LOAD_DATA_STATUS_2_OSCnFUSE_CK_0                  _MK_ADDR_CONST(0x890)
#define PMC_IMPL_FMON_LOAD_DATA_STATUS_2_OSCnFUSE_CK_0_SECURE                   0x0
#define PMC_IMPL_FMON_LOAD_DATA_STATUS_2_OSCnFUSE_CK_0_DUAL                     0x0
#define PMC_IMPL_FMON_LOAD_DATA_STATUS_2_OSCnFUSE_CK_0_SCR                      OSCnFUSE_CK_SCR_0
#define PMC_IMPL_FMON_LOAD_DATA_STATUS_2_OSCnFUSE_CK_0_WORD_COUNT                       0x1
#define PMC_IMPL_FMON_LOAD_DATA_STATUS_2_OSCnFUSE_CK_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_FMON_LOAD_DATA_STATUS_2_OSCnFUSE_CK_0_RESET_MASK                       _MK_MASK_CONST(0xffffffff)
#define PMC_IMPL_FMON_LOAD_DATA_STATUS_2_OSCnFUSE_CK_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_FMON_LOAD_DATA_STATUS_2_OSCnFUSE_CK_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define PMC_IMPL_FMON_LOAD_DATA_STATUS_2_OSCnFUSE_CK_0_READ_MASK                        _MK_MASK_CONST(0xffffffff)
#define PMC_IMPL_FMON_LOAD_DATA_STATUS_2_OSCnFUSE_CK_0_WRITE_MASK                       _MK_MASK_CONST(0x0)
#define PMC_IMPL_FMON_LOAD_DATA_STATUS_2_OSCnFUSE_CK_0_FMON_LOAD_DATA_VAL_OSCnFUSE_CK_SHIFT                     _MK_SHIFT_CONST(0)
#define PMC_IMPL_FMON_LOAD_DATA_STATUS_2_OSCnFUSE_CK_0_FMON_LOAD_DATA_VAL_OSCnFUSE_CK_FIELD                     _MK_FIELD_CONST(0xffffffff, PMC_IMPL_FMON_LOAD_DATA_STATUS_2_OSCnFUSE_CK_0_FMON_LOAD_DATA_VAL_OSCnFUSE_CK_SHIFT)
#define PMC_IMPL_FMON_LOAD_DATA_STATUS_2_OSCnFUSE_CK_0_FMON_LOAD_DATA_VAL_OSCnFUSE_CK_RANGE                     31:0
#define PMC_IMPL_FMON_LOAD_DATA_STATUS_2_OSCnFUSE_CK_0_FMON_LOAD_DATA_VAL_OSCnFUSE_CK_WOFFSET                   0x0
#define PMC_IMPL_FMON_LOAD_DATA_STATUS_2_OSCnFUSE_CK_0_FMON_LOAD_DATA_VAL_OSCnFUSE_CK_DEFAULT                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_FMON_LOAD_DATA_STATUS_2_OSCnFUSE_CK_0_FMON_LOAD_DATA_VAL_OSCnFUSE_CK_DEFAULT_MASK                      _MK_MASK_CONST(0xffffffff)
#define PMC_IMPL_FMON_LOAD_DATA_STATUS_2_OSCnFUSE_CK_0_FMON_LOAD_DATA_VAL_OSCnFUSE_CK_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_FMON_LOAD_DATA_STATUS_2_OSCnFUSE_CK_0_FMON_LOAD_DATA_VAL_OSCnFUSE_CK_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_FMON_LOAD_DATA_STATUS_2_OSCnFUSE_CK_0_FMON_LOAD_DATA_VAL_OSCnFUSE_CK_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define PMC_IMPL_FMON_LOAD_DATA_STATUS_2_OSCnFUSE_CK_0_FMON_LOAD_DATA_VAL_OSCnFUSE_CK_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)


// Register PMC_IMPL_FMON_CLEAR_COUNTER_OSCnFUSE_CK_0
#define PMC_IMPL_FMON_CLEAR_COUNTER_OSCnFUSE_CK_0                       _MK_ADDR_CONST(0x894)
#define PMC_IMPL_FMON_CLEAR_COUNTER_OSCnFUSE_CK_0_SECURE                        0x0
#define PMC_IMPL_FMON_CLEAR_COUNTER_OSCnFUSE_CK_0_DUAL                  0x0
#define PMC_IMPL_FMON_CLEAR_COUNTER_OSCnFUSE_CK_0_SCR                   OSCnFUSE_CK_SCR_0
#define PMC_IMPL_FMON_CLEAR_COUNTER_OSCnFUSE_CK_0_WORD_COUNT                    0x1
#define PMC_IMPL_FMON_CLEAR_COUNTER_OSCnFUSE_CK_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_FMON_CLEAR_COUNTER_OSCnFUSE_CK_0_RESET_MASK                    _MK_MASK_CONST(0xf)
#define PMC_IMPL_FMON_CLEAR_COUNTER_OSCnFUSE_CK_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_FMON_CLEAR_COUNTER_OSCnFUSE_CK_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define PMC_IMPL_FMON_CLEAR_COUNTER_OSCnFUSE_CK_0_READ_MASK                     _MK_MASK_CONST(0xf)
#define PMC_IMPL_FMON_CLEAR_COUNTER_OSCnFUSE_CK_0_WRITE_MASK                    _MK_MASK_CONST(0xf)
#define PMC_IMPL_FMON_CLEAR_COUNTER_OSCnFUSE_CK_0_FMON_HOLD_COUNT_SAMPLES_OSCnFUSE_CK_SHIFT                     _MK_SHIFT_CONST(3)
#define PMC_IMPL_FMON_CLEAR_COUNTER_OSCnFUSE_CK_0_FMON_HOLD_COUNT_SAMPLES_OSCnFUSE_CK_FIELD                     _MK_FIELD_CONST(0x1, PMC_IMPL_FMON_CLEAR_COUNTER_OSCnFUSE_CK_0_FMON_HOLD_COUNT_SAMPLES_OSCnFUSE_CK_SHIFT)
#define PMC_IMPL_FMON_CLEAR_COUNTER_OSCnFUSE_CK_0_FMON_HOLD_COUNT_SAMPLES_OSCnFUSE_CK_RANGE                     3:3
#define PMC_IMPL_FMON_CLEAR_COUNTER_OSCnFUSE_CK_0_FMON_HOLD_COUNT_SAMPLES_OSCnFUSE_CK_WOFFSET                   0x0
#define PMC_IMPL_FMON_CLEAR_COUNTER_OSCnFUSE_CK_0_FMON_HOLD_COUNT_SAMPLES_OSCnFUSE_CK_DEFAULT                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_FMON_CLEAR_COUNTER_OSCnFUSE_CK_0_FMON_HOLD_COUNT_SAMPLES_OSCnFUSE_CK_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define PMC_IMPL_FMON_CLEAR_COUNTER_OSCnFUSE_CK_0_FMON_HOLD_COUNT_SAMPLES_OSCnFUSE_CK_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_FMON_CLEAR_COUNTER_OSCnFUSE_CK_0_FMON_HOLD_COUNT_SAMPLES_OSCnFUSE_CK_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_FMON_CLEAR_COUNTER_OSCnFUSE_CK_0_FMON_HOLD_COUNT_SAMPLES_OSCnFUSE_CK_PARITY_PROTECTION                 _MK_MASK_CONST(0x1)
#define PMC_IMPL_FMON_CLEAR_COUNTER_OSCnFUSE_CK_0_FMON_HOLD_COUNT_SAMPLES_OSCnFUSE_CK_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)

#define PMC_IMPL_FMON_CLEAR_COUNTER_OSCnFUSE_CK_0_FMON_CLEAR_FMON_COUNTER_OSCnFUSE_CK_SHIFT                     _MK_SHIFT_CONST(2)
#define PMC_IMPL_FMON_CLEAR_COUNTER_OSCnFUSE_CK_0_FMON_CLEAR_FMON_COUNTER_OSCnFUSE_CK_FIELD                     _MK_FIELD_CONST(0x1, PMC_IMPL_FMON_CLEAR_COUNTER_OSCnFUSE_CK_0_FMON_CLEAR_FMON_COUNTER_OSCnFUSE_CK_SHIFT)
#define PMC_IMPL_FMON_CLEAR_COUNTER_OSCnFUSE_CK_0_FMON_CLEAR_FMON_COUNTER_OSCnFUSE_CK_RANGE                     2:2
#define PMC_IMPL_FMON_CLEAR_COUNTER_OSCnFUSE_CK_0_FMON_CLEAR_FMON_COUNTER_OSCnFUSE_CK_WOFFSET                   0x0
#define PMC_IMPL_FMON_CLEAR_COUNTER_OSCnFUSE_CK_0_FMON_CLEAR_FMON_COUNTER_OSCnFUSE_CK_DEFAULT                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_FMON_CLEAR_COUNTER_OSCnFUSE_CK_0_FMON_CLEAR_FMON_COUNTER_OSCnFUSE_CK_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define PMC_IMPL_FMON_CLEAR_COUNTER_OSCnFUSE_CK_0_FMON_CLEAR_FMON_COUNTER_OSCnFUSE_CK_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_FMON_CLEAR_COUNTER_OSCnFUSE_CK_0_FMON_CLEAR_FMON_COUNTER_OSCnFUSE_CK_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_FMON_CLEAR_COUNTER_OSCnFUSE_CK_0_FMON_CLEAR_FMON_COUNTER_OSCnFUSE_CK_PARITY_PROTECTION                 _MK_MASK_CONST(0x1)
#define PMC_IMPL_FMON_CLEAR_COUNTER_OSCnFUSE_CK_0_FMON_CLEAR_FMON_COUNTER_OSCnFUSE_CK_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)

#define PMC_IMPL_FMON_CLEAR_COUNTER_OSCnFUSE_CK_0_FMON_MASK_MIN_MAX_COUNT_CLEAR_OSCnFUSE_CK_SHIFT                       _MK_SHIFT_CONST(1)
#define PMC_IMPL_FMON_CLEAR_COUNTER_OSCnFUSE_CK_0_FMON_MASK_MIN_MAX_COUNT_CLEAR_OSCnFUSE_CK_FIELD                       _MK_FIELD_CONST(0x1, PMC_IMPL_FMON_CLEAR_COUNTER_OSCnFUSE_CK_0_FMON_MASK_MIN_MAX_COUNT_CLEAR_OSCnFUSE_CK_SHIFT)
#define PMC_IMPL_FMON_CLEAR_COUNTER_OSCnFUSE_CK_0_FMON_MASK_MIN_MAX_COUNT_CLEAR_OSCnFUSE_CK_RANGE                       1:1
#define PMC_IMPL_FMON_CLEAR_COUNTER_OSCnFUSE_CK_0_FMON_MASK_MIN_MAX_COUNT_CLEAR_OSCnFUSE_CK_WOFFSET                     0x0
#define PMC_IMPL_FMON_CLEAR_COUNTER_OSCnFUSE_CK_0_FMON_MASK_MIN_MAX_COUNT_CLEAR_OSCnFUSE_CK_DEFAULT                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_FMON_CLEAR_COUNTER_OSCnFUSE_CK_0_FMON_MASK_MIN_MAX_COUNT_CLEAR_OSCnFUSE_CK_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define PMC_IMPL_FMON_CLEAR_COUNTER_OSCnFUSE_CK_0_FMON_MASK_MIN_MAX_COUNT_CLEAR_OSCnFUSE_CK_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define PMC_IMPL_FMON_CLEAR_COUNTER_OSCnFUSE_CK_0_FMON_MASK_MIN_MAX_COUNT_CLEAR_OSCnFUSE_CK_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_FMON_CLEAR_COUNTER_OSCnFUSE_CK_0_FMON_MASK_MIN_MAX_COUNT_CLEAR_OSCnFUSE_CK_PARITY_PROTECTION                   _MK_MASK_CONST(0x1)
#define PMC_IMPL_FMON_CLEAR_COUNTER_OSCnFUSE_CK_0_FMON_MASK_MIN_MAX_COUNT_CLEAR_OSCnFUSE_CK_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define PMC_IMPL_FMON_CLEAR_COUNTER_OSCnFUSE_CK_0_FMON_MIN_MAX_LASTN_COUNT_CLEAR_OSCnFUSE_CK_SHIFT                      _MK_SHIFT_CONST(0)
#define PMC_IMPL_FMON_CLEAR_COUNTER_OSCnFUSE_CK_0_FMON_MIN_MAX_LASTN_COUNT_CLEAR_OSCnFUSE_CK_FIELD                      _MK_FIELD_CONST(0x1, PMC_IMPL_FMON_CLEAR_COUNTER_OSCnFUSE_CK_0_FMON_MIN_MAX_LASTN_COUNT_CLEAR_OSCnFUSE_CK_SHIFT)
#define PMC_IMPL_FMON_CLEAR_COUNTER_OSCnFUSE_CK_0_FMON_MIN_MAX_LASTN_COUNT_CLEAR_OSCnFUSE_CK_RANGE                      0:0
#define PMC_IMPL_FMON_CLEAR_COUNTER_OSCnFUSE_CK_0_FMON_MIN_MAX_LASTN_COUNT_CLEAR_OSCnFUSE_CK_WOFFSET                    0x0
#define PMC_IMPL_FMON_CLEAR_COUNTER_OSCnFUSE_CK_0_FMON_MIN_MAX_LASTN_COUNT_CLEAR_OSCnFUSE_CK_DEFAULT                    _MK_MASK_CONST(0x0)
#define PMC_IMPL_FMON_CLEAR_COUNTER_OSCnFUSE_CK_0_FMON_MIN_MAX_LASTN_COUNT_CLEAR_OSCnFUSE_CK_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define PMC_IMPL_FMON_CLEAR_COUNTER_OSCnFUSE_CK_0_FMON_MIN_MAX_LASTN_COUNT_CLEAR_OSCnFUSE_CK_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define PMC_IMPL_FMON_CLEAR_COUNTER_OSCnFUSE_CK_0_FMON_MIN_MAX_LASTN_COUNT_CLEAR_OSCnFUSE_CK_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define PMC_IMPL_FMON_CLEAR_COUNTER_OSCnFUSE_CK_0_FMON_MIN_MAX_LASTN_COUNT_CLEAR_OSCnFUSE_CK_PARITY_PROTECTION                  _MK_MASK_CONST(0x1)
#define PMC_IMPL_FMON_CLEAR_COUNTER_OSCnFUSE_CK_0_FMON_MIN_MAX_LASTN_COUNT_CLEAR_OSCnFUSE_CK_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)


// Register PMC_IMPL_FMON_DEBUG_CONFIG_OSCnFUSE_CK_0
#define PMC_IMPL_FMON_DEBUG_CONFIG_OSCnFUSE_CK_0                        _MK_ADDR_CONST(0x898)
#define PMC_IMPL_FMON_DEBUG_CONFIG_OSCnFUSE_CK_0_SECURE                         0x0
#define PMC_IMPL_FMON_DEBUG_CONFIG_OSCnFUSE_CK_0_DUAL                   0x0
#define PMC_IMPL_FMON_DEBUG_CONFIG_OSCnFUSE_CK_0_SCR                    OSCnFUSE_CK_SCR_0
#define PMC_IMPL_FMON_DEBUG_CONFIG_OSCnFUSE_CK_0_WORD_COUNT                     0x1
#define PMC_IMPL_FMON_DEBUG_CONFIG_OSCnFUSE_CK_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_FMON_DEBUG_CONFIG_OSCnFUSE_CK_0_RESET_MASK                     _MK_MASK_CONST(0x3)
#define PMC_IMPL_FMON_DEBUG_CONFIG_OSCnFUSE_CK_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define PMC_IMPL_FMON_DEBUG_CONFIG_OSCnFUSE_CK_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_FMON_DEBUG_CONFIG_OSCnFUSE_CK_0_READ_MASK                      _MK_MASK_CONST(0x3)
#define PMC_IMPL_FMON_DEBUG_CONFIG_OSCnFUSE_CK_0_WRITE_MASK                     _MK_MASK_CONST(0x1)
#define PMC_IMPL_FMON_DEBUG_CONFIG_OSCnFUSE_CK_0_FMON_REF_WINDOW_OSCnFUSE_CK_SHIFT                      _MK_SHIFT_CONST(1)
#define PMC_IMPL_FMON_DEBUG_CONFIG_OSCnFUSE_CK_0_FMON_REF_WINDOW_OSCnFUSE_CK_FIELD                      _MK_FIELD_CONST(0x1, PMC_IMPL_FMON_DEBUG_CONFIG_OSCnFUSE_CK_0_FMON_REF_WINDOW_OSCnFUSE_CK_SHIFT)
#define PMC_IMPL_FMON_DEBUG_CONFIG_OSCnFUSE_CK_0_FMON_REF_WINDOW_OSCnFUSE_CK_RANGE                      1:1
#define PMC_IMPL_FMON_DEBUG_CONFIG_OSCnFUSE_CK_0_FMON_REF_WINDOW_OSCnFUSE_CK_WOFFSET                    0x0
#define PMC_IMPL_FMON_DEBUG_CONFIG_OSCnFUSE_CK_0_FMON_REF_WINDOW_OSCnFUSE_CK_DEFAULT                    _MK_MASK_CONST(0x0)
#define PMC_IMPL_FMON_DEBUG_CONFIG_OSCnFUSE_CK_0_FMON_REF_WINDOW_OSCnFUSE_CK_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define PMC_IMPL_FMON_DEBUG_CONFIG_OSCnFUSE_CK_0_FMON_REF_WINDOW_OSCnFUSE_CK_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define PMC_IMPL_FMON_DEBUG_CONFIG_OSCnFUSE_CK_0_FMON_REF_WINDOW_OSCnFUSE_CK_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define PMC_IMPL_FMON_DEBUG_CONFIG_OSCnFUSE_CK_0_FMON_REF_WINDOW_OSCnFUSE_CK_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define PMC_IMPL_FMON_DEBUG_CONFIG_OSCnFUSE_CK_0_FMON_REF_WINDOW_OSCnFUSE_CK_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)

#define PMC_IMPL_FMON_DEBUG_CONFIG_OSCnFUSE_CK_0_FMON_ENABLE_DEBUG_OSCnFUSE_CK_SHIFT                    _MK_SHIFT_CONST(0)
#define PMC_IMPL_FMON_DEBUG_CONFIG_OSCnFUSE_CK_0_FMON_ENABLE_DEBUG_OSCnFUSE_CK_FIELD                    _MK_FIELD_CONST(0x1, PMC_IMPL_FMON_DEBUG_CONFIG_OSCnFUSE_CK_0_FMON_ENABLE_DEBUG_OSCnFUSE_CK_SHIFT)
#define PMC_IMPL_FMON_DEBUG_CONFIG_OSCnFUSE_CK_0_FMON_ENABLE_DEBUG_OSCnFUSE_CK_RANGE                    0:0
#define PMC_IMPL_FMON_DEBUG_CONFIG_OSCnFUSE_CK_0_FMON_ENABLE_DEBUG_OSCnFUSE_CK_WOFFSET                  0x0
#define PMC_IMPL_FMON_DEBUG_CONFIG_OSCnFUSE_CK_0_FMON_ENABLE_DEBUG_OSCnFUSE_CK_DEFAULT                  _MK_MASK_CONST(0x0)
#define PMC_IMPL_FMON_DEBUG_CONFIG_OSCnFUSE_CK_0_FMON_ENABLE_DEBUG_OSCnFUSE_CK_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define PMC_IMPL_FMON_DEBUG_CONFIG_OSCnFUSE_CK_0_FMON_ENABLE_DEBUG_OSCnFUSE_CK_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define PMC_IMPL_FMON_DEBUG_CONFIG_OSCnFUSE_CK_0_FMON_ENABLE_DEBUG_OSCnFUSE_CK_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define PMC_IMPL_FMON_DEBUG_CONFIG_OSCnFUSE_CK_0_FMON_ENABLE_DEBUG_OSCnFUSE_CK_PARITY_PROTECTION                        _MK_MASK_CONST(0x1)
#define PMC_IMPL_FMON_DEBUG_CONFIG_OSCnFUSE_CK_0_FMON_ENABLE_DEBUG_OSCnFUSE_CK_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)
#define PMC_IMPL_FMON_DEBUG_CONFIG_OSCnFUSE_CK_0_FMON_ENABLE_DEBUG_OSCnFUSE_CK_INIT_ENUM                        DISABLE
#define PMC_IMPL_FMON_DEBUG_CONFIG_OSCnFUSE_CK_0_FMON_ENABLE_DEBUG_OSCnFUSE_CK_DISABLE                  _MK_ENUM_CONST(0)
#define PMC_IMPL_FMON_DEBUG_CONFIG_OSCnFUSE_CK_0_FMON_ENABLE_DEBUG_OSCnFUSE_CK_ENABLE                   _MK_ENUM_CONST(1)


// Register PMC_IMPL_FMON_CNTR_OVERFLOW_CTRL_OSCnFUSE_CK_0
#define PMC_IMPL_FMON_CNTR_OVERFLOW_CTRL_OSCnFUSE_CK_0                  _MK_ADDR_CONST(0x89c)
#define PMC_IMPL_FMON_CNTR_OVERFLOW_CTRL_OSCnFUSE_CK_0_SECURE                   0x0
#define PMC_IMPL_FMON_CNTR_OVERFLOW_CTRL_OSCnFUSE_CK_0_DUAL                     0x0
#define PMC_IMPL_FMON_CNTR_OVERFLOW_CTRL_OSCnFUSE_CK_0_SCR                      OSCnFUSE_CK_SCR_0
#define PMC_IMPL_FMON_CNTR_OVERFLOW_CTRL_OSCnFUSE_CK_0_WORD_COUNT                       0x1
#define PMC_IMPL_FMON_CNTR_OVERFLOW_CTRL_OSCnFUSE_CK_0_RESET_VAL                        _MK_MASK_CONST(0x8000000b)
#define PMC_IMPL_FMON_CNTR_OVERFLOW_CTRL_OSCnFUSE_CK_0_RESET_MASK                       _MK_MASK_CONST(0x8000001f)
#define PMC_IMPL_FMON_CNTR_OVERFLOW_CTRL_OSCnFUSE_CK_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_FMON_CNTR_OVERFLOW_CTRL_OSCnFUSE_CK_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define PMC_IMPL_FMON_CNTR_OVERFLOW_CTRL_OSCnFUSE_CK_0_READ_MASK                        _MK_MASK_CONST(0x8000001f)
#define PMC_IMPL_FMON_CNTR_OVERFLOW_CTRL_OSCnFUSE_CK_0_WRITE_MASK                       _MK_MASK_CONST(0x8000001f)
#define PMC_IMPL_FMON_CNTR_OVERFLOW_CTRL_OSCnFUSE_CK_0_FMON_OVERFLOW_BIT_SEL_OSCnFUSE_CK_SHIFT                  _MK_SHIFT_CONST(0)
#define PMC_IMPL_FMON_CNTR_OVERFLOW_CTRL_OSCnFUSE_CK_0_FMON_OVERFLOW_BIT_SEL_OSCnFUSE_CK_FIELD                  _MK_FIELD_CONST(0x1f, PMC_IMPL_FMON_CNTR_OVERFLOW_CTRL_OSCnFUSE_CK_0_FMON_OVERFLOW_BIT_SEL_OSCnFUSE_CK_SHIFT)
#define PMC_IMPL_FMON_CNTR_OVERFLOW_CTRL_OSCnFUSE_CK_0_FMON_OVERFLOW_BIT_SEL_OSCnFUSE_CK_RANGE                  4:0
#define PMC_IMPL_FMON_CNTR_OVERFLOW_CTRL_OSCnFUSE_CK_0_FMON_OVERFLOW_BIT_SEL_OSCnFUSE_CK_WOFFSET                        0x0
#define PMC_IMPL_FMON_CNTR_OVERFLOW_CTRL_OSCnFUSE_CK_0_FMON_OVERFLOW_BIT_SEL_OSCnFUSE_CK_DEFAULT                        _MK_MASK_CONST(0xb)
#define PMC_IMPL_FMON_CNTR_OVERFLOW_CTRL_OSCnFUSE_CK_0_FMON_OVERFLOW_BIT_SEL_OSCnFUSE_CK_DEFAULT_MASK                   _MK_MASK_CONST(0x1f)
#define PMC_IMPL_FMON_CNTR_OVERFLOW_CTRL_OSCnFUSE_CK_0_FMON_OVERFLOW_BIT_SEL_OSCnFUSE_CK_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_FMON_CNTR_OVERFLOW_CTRL_OSCnFUSE_CK_0_FMON_OVERFLOW_BIT_SEL_OSCnFUSE_CK_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_FMON_CNTR_OVERFLOW_CTRL_OSCnFUSE_CK_0_FMON_OVERFLOW_BIT_SEL_OSCnFUSE_CK_PARITY_PROTECTION                      _MK_MASK_CONST(0x1)
#define PMC_IMPL_FMON_CNTR_OVERFLOW_CTRL_OSCnFUSE_CK_0_FMON_OVERFLOW_BIT_SEL_OSCnFUSE_CK_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)

#define PMC_IMPL_FMON_CNTR_OVERFLOW_CTRL_OSCnFUSE_CK_0_USE_CNTR_OVERFLOW_DC_FAULT_OSCnFUSE_CK_SHIFT                     _MK_SHIFT_CONST(31)
#define PMC_IMPL_FMON_CNTR_OVERFLOW_CTRL_OSCnFUSE_CK_0_USE_CNTR_OVERFLOW_DC_FAULT_OSCnFUSE_CK_FIELD                     _MK_FIELD_CONST(0x1, PMC_IMPL_FMON_CNTR_OVERFLOW_CTRL_OSCnFUSE_CK_0_USE_CNTR_OVERFLOW_DC_FAULT_OSCnFUSE_CK_SHIFT)
#define PMC_IMPL_FMON_CNTR_OVERFLOW_CTRL_OSCnFUSE_CK_0_USE_CNTR_OVERFLOW_DC_FAULT_OSCnFUSE_CK_RANGE                     31:31
#define PMC_IMPL_FMON_CNTR_OVERFLOW_CTRL_OSCnFUSE_CK_0_USE_CNTR_OVERFLOW_DC_FAULT_OSCnFUSE_CK_WOFFSET                   0x0
#define PMC_IMPL_FMON_CNTR_OVERFLOW_CTRL_OSCnFUSE_CK_0_USE_CNTR_OVERFLOW_DC_FAULT_OSCnFUSE_CK_DEFAULT                   _MK_MASK_CONST(0x1)
#define PMC_IMPL_FMON_CNTR_OVERFLOW_CTRL_OSCnFUSE_CK_0_USE_CNTR_OVERFLOW_DC_FAULT_OSCnFUSE_CK_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define PMC_IMPL_FMON_CNTR_OVERFLOW_CTRL_OSCnFUSE_CK_0_USE_CNTR_OVERFLOW_DC_FAULT_OSCnFUSE_CK_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_FMON_CNTR_OVERFLOW_CTRL_OSCnFUSE_CK_0_USE_CNTR_OVERFLOW_DC_FAULT_OSCnFUSE_CK_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_FMON_CNTR_OVERFLOW_CTRL_OSCnFUSE_CK_0_USE_CNTR_OVERFLOW_DC_FAULT_OSCnFUSE_CK_PARITY_PROTECTION                 _MK_MASK_CONST(0x1)
#define PMC_IMPL_FMON_CNTR_OVERFLOW_CTRL_OSCnFUSE_CK_0_USE_CNTR_OVERFLOW_DC_FAULT_OSCnFUSE_CK_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define PMC_IMPL_FMON_CNTR_OVERFLOW_CTRL_OSCnFUSE_CK_0_USE_CNTR_OVERFLOW_DC_FAULT_OSCnFUSE_CK_INIT_ENUM                 ENABLE
#define PMC_IMPL_FMON_CNTR_OVERFLOW_CTRL_OSCnFUSE_CK_0_USE_CNTR_OVERFLOW_DC_FAULT_OSCnFUSE_CK_DISABLE                   _MK_ENUM_CONST(0)
#define PMC_IMPL_FMON_CNTR_OVERFLOW_CTRL_OSCnFUSE_CK_0_USE_CNTR_OVERFLOW_DC_FAULT_OSCnFUSE_CK_ENABLE                    _MK_ENUM_CONST(1)


// Register PMC_IMPL_FMON_DBG_CONFIG_0
#define PMC_IMPL_FMON_DBG_CONFIG_0                      _MK_ADDR_CONST(0x8a0)
#define PMC_IMPL_FMON_DBG_CONFIG_0_SECURE                       0x0
#define PMC_IMPL_FMON_DBG_CONFIG_0_DUAL                         0x0
#define PMC_IMPL_FMON_DBG_CONFIG_0_SCR                  FMON_COM_SCR_0
#define PMC_IMPL_FMON_DBG_CONFIG_0_WORD_COUNT                   0x1
#define PMC_IMPL_FMON_DBG_CONFIG_0_RESET_VAL                    _MK_MASK_CONST(0x0)
#define PMC_IMPL_FMON_DBG_CONFIG_0_RESET_MASK                   _MK_MASK_CONST(0xf01)
#define PMC_IMPL_FMON_DBG_CONFIG_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define PMC_IMPL_FMON_DBG_CONFIG_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_FMON_DBG_CONFIG_0_READ_MASK                    _MK_MASK_CONST(0xf01)
#define PMC_IMPL_FMON_DBG_CONFIG_0_WRITE_MASK                   _MK_MASK_CONST(0xf01)
#define PMC_IMPL_FMON_DBG_CONFIG_0_USE_OSC_STABLE_IN_FOSC_FMON_ENABLE_SHIFT                     _MK_SHIFT_CONST(0)
#define PMC_IMPL_FMON_DBG_CONFIG_0_USE_OSC_STABLE_IN_FOSC_FMON_ENABLE_FIELD                     _MK_FIELD_CONST(0x1, PMC_IMPL_FMON_DBG_CONFIG_0_USE_OSC_STABLE_IN_FOSC_FMON_ENABLE_SHIFT)
#define PMC_IMPL_FMON_DBG_CONFIG_0_USE_OSC_STABLE_IN_FOSC_FMON_ENABLE_RANGE                     0:0
#define PMC_IMPL_FMON_DBG_CONFIG_0_USE_OSC_STABLE_IN_FOSC_FMON_ENABLE_WOFFSET                   0x0
#define PMC_IMPL_FMON_DBG_CONFIG_0_USE_OSC_STABLE_IN_FOSC_FMON_ENABLE_DEFAULT                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_FMON_DBG_CONFIG_0_USE_OSC_STABLE_IN_FOSC_FMON_ENABLE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define PMC_IMPL_FMON_DBG_CONFIG_0_USE_OSC_STABLE_IN_FOSC_FMON_ENABLE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_FMON_DBG_CONFIG_0_USE_OSC_STABLE_IN_FOSC_FMON_ENABLE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_FMON_DBG_CONFIG_0_USE_OSC_STABLE_IN_FOSC_FMON_ENABLE_PARITY_PROTECTION                 _MK_MASK_CONST(0x1)
#define PMC_IMPL_FMON_DBG_CONFIG_0_USE_OSC_STABLE_IN_FOSC_FMON_ENABLE_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define PMC_IMPL_FMON_DBG_CONFIG_0_USE_OSC_STABLE_IN_FOSC_FMON_ENABLE_INIT_ENUM                 DISABLE
#define PMC_IMPL_FMON_DBG_CONFIG_0_USE_OSC_STABLE_IN_FOSC_FMON_ENABLE_DISABLE                   _MK_ENUM_CONST(0)
#define PMC_IMPL_FMON_DBG_CONFIG_0_USE_OSC_STABLE_IN_FOSC_FMON_ENABLE_ENABLE                    _MK_ENUM_CONST(1)

#define PMC_IMPL_FMON_DBG_CONFIG_0_FMON_FAULT_CLEAR2HSM_OSCNFUSE_CK_SHIFT                       _MK_SHIFT_CONST(8)
#define PMC_IMPL_FMON_DBG_CONFIG_0_FMON_FAULT_CLEAR2HSM_OSCNFUSE_CK_FIELD                       _MK_FIELD_CONST(0x1, PMC_IMPL_FMON_DBG_CONFIG_0_FMON_FAULT_CLEAR2HSM_OSCNFUSE_CK_SHIFT)
#define PMC_IMPL_FMON_DBG_CONFIG_0_FMON_FAULT_CLEAR2HSM_OSCNFUSE_CK_RANGE                       8:8
#define PMC_IMPL_FMON_DBG_CONFIG_0_FMON_FAULT_CLEAR2HSM_OSCNFUSE_CK_WOFFSET                     0x0
#define PMC_IMPL_FMON_DBG_CONFIG_0_FMON_FAULT_CLEAR2HSM_OSCNFUSE_CK_DEFAULT                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_FMON_DBG_CONFIG_0_FMON_FAULT_CLEAR2HSM_OSCNFUSE_CK_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define PMC_IMPL_FMON_DBG_CONFIG_0_FMON_FAULT_CLEAR2HSM_OSCNFUSE_CK_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define PMC_IMPL_FMON_DBG_CONFIG_0_FMON_FAULT_CLEAR2HSM_OSCNFUSE_CK_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_FMON_DBG_CONFIG_0_FMON_FAULT_CLEAR2HSM_OSCNFUSE_CK_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_FMON_DBG_CONFIG_0_FMON_FAULT_CLEAR2HSM_OSCNFUSE_CK_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define PMC_IMPL_FMON_DBG_CONFIG_0_FMON_FAULT_SET2HSM_OSCNFUSE_CK_SHIFT                 _MK_SHIFT_CONST(9)
#define PMC_IMPL_FMON_DBG_CONFIG_0_FMON_FAULT_SET2HSM_OSCNFUSE_CK_FIELD                 _MK_FIELD_CONST(0x1, PMC_IMPL_FMON_DBG_CONFIG_0_FMON_FAULT_SET2HSM_OSCNFUSE_CK_SHIFT)
#define PMC_IMPL_FMON_DBG_CONFIG_0_FMON_FAULT_SET2HSM_OSCNFUSE_CK_RANGE                 9:9
#define PMC_IMPL_FMON_DBG_CONFIG_0_FMON_FAULT_SET2HSM_OSCNFUSE_CK_WOFFSET                       0x0
#define PMC_IMPL_FMON_DBG_CONFIG_0_FMON_FAULT_SET2HSM_OSCNFUSE_CK_DEFAULT                       _MK_MASK_CONST(0x0)
#define PMC_IMPL_FMON_DBG_CONFIG_0_FMON_FAULT_SET2HSM_OSCNFUSE_CK_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define PMC_IMPL_FMON_DBG_CONFIG_0_FMON_FAULT_SET2HSM_OSCNFUSE_CK_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define PMC_IMPL_FMON_DBG_CONFIG_0_FMON_FAULT_SET2HSM_OSCNFUSE_CK_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define PMC_IMPL_FMON_DBG_CONFIG_0_FMON_FAULT_SET2HSM_OSCNFUSE_CK_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_FMON_DBG_CONFIG_0_FMON_FAULT_SET2HSM_OSCNFUSE_CK_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)

#define PMC_IMPL_FMON_DBG_CONFIG_0_FMON_FAULT_CLEAR2HSM_PMC_CK_SHIFT                    _MK_SHIFT_CONST(10)
#define PMC_IMPL_FMON_DBG_CONFIG_0_FMON_FAULT_CLEAR2HSM_PMC_CK_FIELD                    _MK_FIELD_CONST(0x1, PMC_IMPL_FMON_DBG_CONFIG_0_FMON_FAULT_CLEAR2HSM_PMC_CK_SHIFT)
#define PMC_IMPL_FMON_DBG_CONFIG_0_FMON_FAULT_CLEAR2HSM_PMC_CK_RANGE                    10:10
#define PMC_IMPL_FMON_DBG_CONFIG_0_FMON_FAULT_CLEAR2HSM_PMC_CK_WOFFSET                  0x0
#define PMC_IMPL_FMON_DBG_CONFIG_0_FMON_FAULT_CLEAR2HSM_PMC_CK_DEFAULT                  _MK_MASK_CONST(0x0)
#define PMC_IMPL_FMON_DBG_CONFIG_0_FMON_FAULT_CLEAR2HSM_PMC_CK_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define PMC_IMPL_FMON_DBG_CONFIG_0_FMON_FAULT_CLEAR2HSM_PMC_CK_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define PMC_IMPL_FMON_DBG_CONFIG_0_FMON_FAULT_CLEAR2HSM_PMC_CK_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define PMC_IMPL_FMON_DBG_CONFIG_0_FMON_FAULT_CLEAR2HSM_PMC_CK_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_FMON_DBG_CONFIG_0_FMON_FAULT_CLEAR2HSM_PMC_CK_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)

#define PMC_IMPL_FMON_DBG_CONFIG_0_FMON_FAULT_SET2HSM_PMC_CK_SHIFT                      _MK_SHIFT_CONST(11)
#define PMC_IMPL_FMON_DBG_CONFIG_0_FMON_FAULT_SET2HSM_PMC_CK_FIELD                      _MK_FIELD_CONST(0x1, PMC_IMPL_FMON_DBG_CONFIG_0_FMON_FAULT_SET2HSM_PMC_CK_SHIFT)
#define PMC_IMPL_FMON_DBG_CONFIG_0_FMON_FAULT_SET2HSM_PMC_CK_RANGE                      11:11
#define PMC_IMPL_FMON_DBG_CONFIG_0_FMON_FAULT_SET2HSM_PMC_CK_WOFFSET                    0x0
#define PMC_IMPL_FMON_DBG_CONFIG_0_FMON_FAULT_SET2HSM_PMC_CK_DEFAULT                    _MK_MASK_CONST(0x0)
#define PMC_IMPL_FMON_DBG_CONFIG_0_FMON_FAULT_SET2HSM_PMC_CK_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define PMC_IMPL_FMON_DBG_CONFIG_0_FMON_FAULT_SET2HSM_PMC_CK_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define PMC_IMPL_FMON_DBG_CONFIG_0_FMON_FAULT_SET2HSM_PMC_CK_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define PMC_IMPL_FMON_DBG_CONFIG_0_FMON_FAULT_SET2HSM_PMC_CK_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define PMC_IMPL_FMON_DBG_CONFIG_0_FMON_FAULT_SET2HSM_PMC_CK_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)


// Register PMC_IMPL_L0L1A_RST_SOURCE_EN_0
#define PMC_IMPL_L0L1A_RST_SOURCE_EN_0                  _MK_ADDR_CONST(0x8a4)
#define PMC_IMPL_L0L1A_RST_SOURCE_EN_0_SECURE                   0x0
#define PMC_IMPL_L0L1A_RST_SOURCE_EN_0_DUAL                     0x0
#define PMC_IMPL_L0L1A_RST_SOURCE_EN_0_SCR                      ASYNC_RST_SCR_0
#define PMC_IMPL_L0L1A_RST_SOURCE_EN_0_WORD_COUNT                       0x1
#define PMC_IMPL_L0L1A_RST_SOURCE_EN_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_L0L1A_RST_SOURCE_EN_0_RESET_MASK                       _MK_MASK_CONST(0x771)
#define PMC_IMPL_L0L1A_RST_SOURCE_EN_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_L0L1A_RST_SOURCE_EN_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define PMC_IMPL_L0L1A_RST_SOURCE_EN_0_READ_MASK                        _MK_MASK_CONST(0x771)
#define PMC_IMPL_L0L1A_RST_SOURCE_EN_0_WRITE_MASK                       _MK_MASK_CONST(0x771)
#define PMC_IMPL_L0L1A_RST_SOURCE_EN_0_SW_VREFRORST_EN_SHIFT                    _MK_SHIFT_CONST(0)
#define PMC_IMPL_L0L1A_RST_SOURCE_EN_0_SW_VREFRORST_EN_FIELD                    _MK_FIELD_CONST(0x1, PMC_IMPL_L0L1A_RST_SOURCE_EN_0_SW_VREFRORST_EN_SHIFT)
#define PMC_IMPL_L0L1A_RST_SOURCE_EN_0_SW_VREFRORST_EN_RANGE                    0:0
#define PMC_IMPL_L0L1A_RST_SOURCE_EN_0_SW_VREFRORST_EN_WOFFSET                  0x0
#define PMC_IMPL_L0L1A_RST_SOURCE_EN_0_SW_VREFRORST_EN_DEFAULT                  _MK_MASK_CONST(0x0)
#define PMC_IMPL_L0L1A_RST_SOURCE_EN_0_SW_VREFRORST_EN_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define PMC_IMPL_L0L1A_RST_SOURCE_EN_0_SW_VREFRORST_EN_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define PMC_IMPL_L0L1A_RST_SOURCE_EN_0_SW_VREFRORST_EN_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define PMC_IMPL_L0L1A_RST_SOURCE_EN_0_SW_VREFRORST_EN_PARITY_PROTECTION                        _MK_MASK_CONST(0x1)
#define PMC_IMPL_L0L1A_RST_SOURCE_EN_0_SW_VREFRORST_EN_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)
#define PMC_IMPL_L0L1A_RST_SOURCE_EN_0_SW_VREFRORST_EN_INIT_ENUM                        DISABLE
#define PMC_IMPL_L0L1A_RST_SOURCE_EN_0_SW_VREFRORST_EN_DISABLE                  _MK_ENUM_CONST(0)
#define PMC_IMPL_L0L1A_RST_SOURCE_EN_0_SW_VREFRORST_EN_ENABLE                   _MK_ENUM_CONST(1)

#define PMC_IMPL_L0L1A_RST_SOURCE_EN_0_SW_OSCRSTREQ_SHIFT                       _MK_SHIFT_CONST(4)
#define PMC_IMPL_L0L1A_RST_SOURCE_EN_0_SW_OSCRSTREQ_FIELD                       _MK_FIELD_CONST(0x1, PMC_IMPL_L0L1A_RST_SOURCE_EN_0_SW_OSCRSTREQ_SHIFT)
#define PMC_IMPL_L0L1A_RST_SOURCE_EN_0_SW_OSCRSTREQ_RANGE                       4:4
#define PMC_IMPL_L0L1A_RST_SOURCE_EN_0_SW_OSCRSTREQ_WOFFSET                     0x0
#define PMC_IMPL_L0L1A_RST_SOURCE_EN_0_SW_OSCRSTREQ_DEFAULT                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_L0L1A_RST_SOURCE_EN_0_SW_OSCRSTREQ_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define PMC_IMPL_L0L1A_RST_SOURCE_EN_0_SW_OSCRSTREQ_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define PMC_IMPL_L0L1A_RST_SOURCE_EN_0_SW_OSCRSTREQ_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_L0L1A_RST_SOURCE_EN_0_SW_OSCRSTREQ_PARITY_PROTECTION                   _MK_MASK_CONST(0x1)
#define PMC_IMPL_L0L1A_RST_SOURCE_EN_0_SW_OSCRSTREQ_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define PMC_IMPL_L0L1A_RST_SOURCE_EN_0_SW_OSCRSTREQ_INIT_ENUM                   DISABLE
#define PMC_IMPL_L0L1A_RST_SOURCE_EN_0_SW_OSCRSTREQ_DISABLE                     _MK_ENUM_CONST(0)
#define PMC_IMPL_L0L1A_RST_SOURCE_EN_0_SW_OSCRSTREQ_ENABLE                      _MK_ENUM_CONST(1)

#define PMC_IMPL_L0L1A_RST_SOURCE_EN_0_SW_VDDSOCRST_EN_SHIFT                    _MK_SHIFT_CONST(5)
#define PMC_IMPL_L0L1A_RST_SOURCE_EN_0_SW_VDDSOCRST_EN_FIELD                    _MK_FIELD_CONST(0x1, PMC_IMPL_L0L1A_RST_SOURCE_EN_0_SW_VDDSOCRST_EN_SHIFT)
#define PMC_IMPL_L0L1A_RST_SOURCE_EN_0_SW_VDDSOCRST_EN_RANGE                    5:5
#define PMC_IMPL_L0L1A_RST_SOURCE_EN_0_SW_VDDSOCRST_EN_WOFFSET                  0x0
#define PMC_IMPL_L0L1A_RST_SOURCE_EN_0_SW_VDDSOCRST_EN_DEFAULT                  _MK_MASK_CONST(0x0)
#define PMC_IMPL_L0L1A_RST_SOURCE_EN_0_SW_VDDSOCRST_EN_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define PMC_IMPL_L0L1A_RST_SOURCE_EN_0_SW_VDDSOCRST_EN_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define PMC_IMPL_L0L1A_RST_SOURCE_EN_0_SW_VDDSOCRST_EN_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define PMC_IMPL_L0L1A_RST_SOURCE_EN_0_SW_VDDSOCRST_EN_PARITY_PROTECTION                        _MK_MASK_CONST(0x1)
#define PMC_IMPL_L0L1A_RST_SOURCE_EN_0_SW_VDDSOCRST_EN_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)
#define PMC_IMPL_L0L1A_RST_SOURCE_EN_0_SW_VDDSOCRST_EN_INIT_ENUM                        DISABLE
#define PMC_IMPL_L0L1A_RST_SOURCE_EN_0_SW_VDDSOCRST_EN_DISABLE                  _MK_ENUM_CONST(0)
#define PMC_IMPL_L0L1A_RST_SOURCE_EN_0_SW_VDDSOCRST_EN_ENABLE                   _MK_ENUM_CONST(1)

#define PMC_IMPL_L0L1A_RST_SOURCE_EN_0_SW_FUSECRC_RSTREQ_SHIFT                  _MK_SHIFT_CONST(6)
#define PMC_IMPL_L0L1A_RST_SOURCE_EN_0_SW_FUSECRC_RSTREQ_FIELD                  _MK_FIELD_CONST(0x1, PMC_IMPL_L0L1A_RST_SOURCE_EN_0_SW_FUSECRC_RSTREQ_SHIFT)
#define PMC_IMPL_L0L1A_RST_SOURCE_EN_0_SW_FUSECRC_RSTREQ_RANGE                  6:6
#define PMC_IMPL_L0L1A_RST_SOURCE_EN_0_SW_FUSECRC_RSTREQ_WOFFSET                        0x0
#define PMC_IMPL_L0L1A_RST_SOURCE_EN_0_SW_FUSECRC_RSTREQ_DEFAULT                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_L0L1A_RST_SOURCE_EN_0_SW_FUSECRC_RSTREQ_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define PMC_IMPL_L0L1A_RST_SOURCE_EN_0_SW_FUSECRC_RSTREQ_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_L0L1A_RST_SOURCE_EN_0_SW_FUSECRC_RSTREQ_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_L0L1A_RST_SOURCE_EN_0_SW_FUSECRC_RSTREQ_PARITY_PROTECTION                      _MK_MASK_CONST(0x1)
#define PMC_IMPL_L0L1A_RST_SOURCE_EN_0_SW_FUSECRC_RSTREQ_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define PMC_IMPL_L0L1A_RST_SOURCE_EN_0_SW_FUSECRC_RSTREQ_INIT_ENUM                      DISABLE
#define PMC_IMPL_L0L1A_RST_SOURCE_EN_0_SW_FUSECRC_RSTREQ_DISABLE                        _MK_ENUM_CONST(0)
#define PMC_IMPL_L0L1A_RST_SOURCE_EN_0_SW_FUSECRC_RSTREQ_ENABLE                 _MK_ENUM_CONST(1)

#define PMC_IMPL_L0L1A_RST_SOURCE_EN_0_SW_VDDCPU0RST_EN_SHIFT                   _MK_SHIFT_CONST(8)
#define PMC_IMPL_L0L1A_RST_SOURCE_EN_0_SW_VDDCPU0RST_EN_FIELD                   _MK_FIELD_CONST(0x1, PMC_IMPL_L0L1A_RST_SOURCE_EN_0_SW_VDDCPU0RST_EN_SHIFT)
#define PMC_IMPL_L0L1A_RST_SOURCE_EN_0_SW_VDDCPU0RST_EN_RANGE                   8:8
#define PMC_IMPL_L0L1A_RST_SOURCE_EN_0_SW_VDDCPU0RST_EN_WOFFSET                 0x0
#define PMC_IMPL_L0L1A_RST_SOURCE_EN_0_SW_VDDCPU0RST_EN_DEFAULT                 _MK_MASK_CONST(0x0)
#define PMC_IMPL_L0L1A_RST_SOURCE_EN_0_SW_VDDCPU0RST_EN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define PMC_IMPL_L0L1A_RST_SOURCE_EN_0_SW_VDDCPU0RST_EN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_L0L1A_RST_SOURCE_EN_0_SW_VDDCPU0RST_EN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define PMC_IMPL_L0L1A_RST_SOURCE_EN_0_SW_VDDCPU0RST_EN_PARITY_PROTECTION                       _MK_MASK_CONST(0x1)
#define PMC_IMPL_L0L1A_RST_SOURCE_EN_0_SW_VDDCPU0RST_EN_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define PMC_IMPL_L0L1A_RST_SOURCE_EN_0_SW_VDDCPU0RST_EN_INIT_ENUM                       DISABLE
#define PMC_IMPL_L0L1A_RST_SOURCE_EN_0_SW_VDDCPU0RST_EN_DISABLE                 _MK_ENUM_CONST(0)
#define PMC_IMPL_L0L1A_RST_SOURCE_EN_0_SW_VDDCPU0RST_EN_ENABLE                  _MK_ENUM_CONST(1)

#define PMC_IMPL_L0L1A_RST_SOURCE_EN_0_SW_VDDCPU1RST_EN_SHIFT                   _MK_SHIFT_CONST(9)
#define PMC_IMPL_L0L1A_RST_SOURCE_EN_0_SW_VDDCPU1RST_EN_FIELD                   _MK_FIELD_CONST(0x1, PMC_IMPL_L0L1A_RST_SOURCE_EN_0_SW_VDDCPU1RST_EN_SHIFT)
#define PMC_IMPL_L0L1A_RST_SOURCE_EN_0_SW_VDDCPU1RST_EN_RANGE                   9:9
#define PMC_IMPL_L0L1A_RST_SOURCE_EN_0_SW_VDDCPU1RST_EN_WOFFSET                 0x0
#define PMC_IMPL_L0L1A_RST_SOURCE_EN_0_SW_VDDCPU1RST_EN_DEFAULT                 _MK_MASK_CONST(0x0)
#define PMC_IMPL_L0L1A_RST_SOURCE_EN_0_SW_VDDCPU1RST_EN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define PMC_IMPL_L0L1A_RST_SOURCE_EN_0_SW_VDDCPU1RST_EN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_L0L1A_RST_SOURCE_EN_0_SW_VDDCPU1RST_EN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define PMC_IMPL_L0L1A_RST_SOURCE_EN_0_SW_VDDCPU1RST_EN_PARITY_PROTECTION                       _MK_MASK_CONST(0x1)
#define PMC_IMPL_L0L1A_RST_SOURCE_EN_0_SW_VDDCPU1RST_EN_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define PMC_IMPL_L0L1A_RST_SOURCE_EN_0_SW_VDDCPU1RST_EN_INIT_ENUM                       DISABLE
#define PMC_IMPL_L0L1A_RST_SOURCE_EN_0_SW_VDDCPU1RST_EN_DISABLE                 _MK_ENUM_CONST(0)
#define PMC_IMPL_L0L1A_RST_SOURCE_EN_0_SW_VDDCPU1RST_EN_ENABLE                  _MK_ENUM_CONST(1)

#define PMC_IMPL_L0L1A_RST_SOURCE_EN_0_SW_BPMPRST_EN_SHIFT                      _MK_SHIFT_CONST(10)
#define PMC_IMPL_L0L1A_RST_SOURCE_EN_0_SW_BPMPRST_EN_FIELD                      _MK_FIELD_CONST(0x1, PMC_IMPL_L0L1A_RST_SOURCE_EN_0_SW_BPMPRST_EN_SHIFT)
#define PMC_IMPL_L0L1A_RST_SOURCE_EN_0_SW_BPMPRST_EN_RANGE                      10:10
#define PMC_IMPL_L0L1A_RST_SOURCE_EN_0_SW_BPMPRST_EN_WOFFSET                    0x0
#define PMC_IMPL_L0L1A_RST_SOURCE_EN_0_SW_BPMPRST_EN_DEFAULT                    _MK_MASK_CONST(0x0)
#define PMC_IMPL_L0L1A_RST_SOURCE_EN_0_SW_BPMPRST_EN_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define PMC_IMPL_L0L1A_RST_SOURCE_EN_0_SW_BPMPRST_EN_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define PMC_IMPL_L0L1A_RST_SOURCE_EN_0_SW_BPMPRST_EN_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define PMC_IMPL_L0L1A_RST_SOURCE_EN_0_SW_BPMPRST_EN_PARITY_PROTECTION                  _MK_MASK_CONST(0x1)
#define PMC_IMPL_L0L1A_RST_SOURCE_EN_0_SW_BPMPRST_EN_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define PMC_IMPL_L0L1A_RST_SOURCE_EN_0_SW_BPMPRST_EN_INIT_ENUM                  DISABLE
#define PMC_IMPL_L0L1A_RST_SOURCE_EN_0_SW_BPMPRST_EN_DISABLE                    _MK_ENUM_CONST(0)
#define PMC_IMPL_L0L1A_RST_SOURCE_EN_0_SW_BPMPRST_EN_ENABLE                     _MK_ENUM_CONST(1)


// Register PMC_IMPL_L0L1A_RST_LEVEL_EN_0
#define PMC_IMPL_L0L1A_RST_LEVEL_EN_0                   _MK_ADDR_CONST(0x8a8)
#define PMC_IMPL_L0L1A_RST_LEVEL_EN_0_SECURE                    0x0
#define PMC_IMPL_L0L1A_RST_LEVEL_EN_0_DUAL                      0x0
#define PMC_IMPL_L0L1A_RST_LEVEL_EN_0_SCR                       ASYNC_RST_SCR_0
#define PMC_IMPL_L0L1A_RST_LEVEL_EN_0_WORD_COUNT                        0x1
#define PMC_IMPL_L0L1A_RST_LEVEL_EN_0_RESET_VAL                         _MK_MASK_CONST(0x0)
#define PMC_IMPL_L0L1A_RST_LEVEL_EN_0_RESET_MASK                        _MK_MASK_CONST(0x3)
#define PMC_IMPL_L0L1A_RST_LEVEL_EN_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define PMC_IMPL_L0L1A_RST_LEVEL_EN_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_L0L1A_RST_LEVEL_EN_0_READ_MASK                         _MK_MASK_CONST(0x3)
#define PMC_IMPL_L0L1A_RST_LEVEL_EN_0_WRITE_MASK                        _MK_MASK_CONST(0x3)
#define PMC_IMPL_L0L1A_RST_LEVEL_EN_0_SW_ASYNCL0RST_EN_SHIFT                    _MK_SHIFT_CONST(0)
#define PMC_IMPL_L0L1A_RST_LEVEL_EN_0_SW_ASYNCL0RST_EN_FIELD                    _MK_FIELD_CONST(0x1, PMC_IMPL_L0L1A_RST_LEVEL_EN_0_SW_ASYNCL0RST_EN_SHIFT)
#define PMC_IMPL_L0L1A_RST_LEVEL_EN_0_SW_ASYNCL0RST_EN_RANGE                    0:0
#define PMC_IMPL_L0L1A_RST_LEVEL_EN_0_SW_ASYNCL0RST_EN_WOFFSET                  0x0
#define PMC_IMPL_L0L1A_RST_LEVEL_EN_0_SW_ASYNCL0RST_EN_DEFAULT                  _MK_MASK_CONST(0x0)
#define PMC_IMPL_L0L1A_RST_LEVEL_EN_0_SW_ASYNCL0RST_EN_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define PMC_IMPL_L0L1A_RST_LEVEL_EN_0_SW_ASYNCL0RST_EN_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define PMC_IMPL_L0L1A_RST_LEVEL_EN_0_SW_ASYNCL0RST_EN_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define PMC_IMPL_L0L1A_RST_LEVEL_EN_0_SW_ASYNCL0RST_EN_PARITY_PROTECTION                        _MK_MASK_CONST(0x1)
#define PMC_IMPL_L0L1A_RST_LEVEL_EN_0_SW_ASYNCL0RST_EN_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)
#define PMC_IMPL_L0L1A_RST_LEVEL_EN_0_SW_ASYNCL0RST_EN_INIT_ENUM                        DISABLE
#define PMC_IMPL_L0L1A_RST_LEVEL_EN_0_SW_ASYNCL0RST_EN_DISABLE                  _MK_ENUM_CONST(0)
#define PMC_IMPL_L0L1A_RST_LEVEL_EN_0_SW_ASYNCL0RST_EN_ENABLE                   _MK_ENUM_CONST(1)

#define PMC_IMPL_L0L1A_RST_LEVEL_EN_0_SW_ASYNCL1ARST_EN_SHIFT                   _MK_SHIFT_CONST(1)
#define PMC_IMPL_L0L1A_RST_LEVEL_EN_0_SW_ASYNCL1ARST_EN_FIELD                   _MK_FIELD_CONST(0x1, PMC_IMPL_L0L1A_RST_LEVEL_EN_0_SW_ASYNCL1ARST_EN_SHIFT)
#define PMC_IMPL_L0L1A_RST_LEVEL_EN_0_SW_ASYNCL1ARST_EN_RANGE                   1:1
#define PMC_IMPL_L0L1A_RST_LEVEL_EN_0_SW_ASYNCL1ARST_EN_WOFFSET                 0x0
#define PMC_IMPL_L0L1A_RST_LEVEL_EN_0_SW_ASYNCL1ARST_EN_DEFAULT                 _MK_MASK_CONST(0x0)
#define PMC_IMPL_L0L1A_RST_LEVEL_EN_0_SW_ASYNCL1ARST_EN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define PMC_IMPL_L0L1A_RST_LEVEL_EN_0_SW_ASYNCL1ARST_EN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_L0L1A_RST_LEVEL_EN_0_SW_ASYNCL1ARST_EN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define PMC_IMPL_L0L1A_RST_LEVEL_EN_0_SW_ASYNCL1ARST_EN_PARITY_PROTECTION                       _MK_MASK_CONST(0x1)
#define PMC_IMPL_L0L1A_RST_LEVEL_EN_0_SW_ASYNCL1ARST_EN_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define PMC_IMPL_L0L1A_RST_LEVEL_EN_0_SW_ASYNCL1ARST_EN_INIT_ENUM                       DISABLE
#define PMC_IMPL_L0L1A_RST_LEVEL_EN_0_SW_ASYNCL1ARST_EN_DISABLE                 _MK_ENUM_CONST(0)
#define PMC_IMPL_L0L1A_RST_LEVEL_EN_0_SW_ASYNCL1ARST_EN_ENABLE                  _MK_ENUM_CONST(1)


// Register PMC_IMPL_L0L1A_RST_STATUS_0
#define PMC_IMPL_L0L1A_RST_STATUS_0                     _MK_ADDR_CONST(0x8ac)
#define PMC_IMPL_L0L1A_RST_STATUS_0_SECURE                      0x0
#define PMC_IMPL_L0L1A_RST_STATUS_0_DUAL                        0x0
#define PMC_IMPL_L0L1A_RST_STATUS_0_SCR                         ASYNC_RST_SCR_0
#define PMC_IMPL_L0L1A_RST_STATUS_0_WORD_COUNT                  0x1
#define PMC_IMPL_L0L1A_RST_STATUS_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_L0L1A_RST_STATUS_0_RESET_MASK                  _MK_MASK_CONST(0x3)
#define PMC_IMPL_L0L1A_RST_STATUS_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_L0L1A_RST_STATUS_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_L0L1A_RST_STATUS_0_READ_MASK                   _MK_MASK_CONST(0x3)
#define PMC_IMPL_L0L1A_RST_STATUS_0_WRITE_MASK                  _MK_MASK_CONST(0x0)
#define PMC_IMPL_L0L1A_RST_STATUS_0_FUSE_ASYNCL0RST_ENABLE_SHIFT                        _MK_SHIFT_CONST(0)
#define PMC_IMPL_L0L1A_RST_STATUS_0_FUSE_ASYNCL0RST_ENABLE_FIELD                        _MK_FIELD_CONST(0x1, PMC_IMPL_L0L1A_RST_STATUS_0_FUSE_ASYNCL0RST_ENABLE_SHIFT)
#define PMC_IMPL_L0L1A_RST_STATUS_0_FUSE_ASYNCL0RST_ENABLE_RANGE                        0:0
#define PMC_IMPL_L0L1A_RST_STATUS_0_FUSE_ASYNCL0RST_ENABLE_WOFFSET                      0x0
#define PMC_IMPL_L0L1A_RST_STATUS_0_FUSE_ASYNCL0RST_ENABLE_DEFAULT                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_L0L1A_RST_STATUS_0_FUSE_ASYNCL0RST_ENABLE_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define PMC_IMPL_L0L1A_RST_STATUS_0_FUSE_ASYNCL0RST_ENABLE_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_L0L1A_RST_STATUS_0_FUSE_ASYNCL0RST_ENABLE_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_L0L1A_RST_STATUS_0_FUSE_ASYNCL0RST_ENABLE_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define PMC_IMPL_L0L1A_RST_STATUS_0_FUSE_ASYNCL0RST_ENABLE_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)
#define PMC_IMPL_L0L1A_RST_STATUS_0_FUSE_ASYNCL0RST_ENABLE_INIT_ENUM                    DISABLE
#define PMC_IMPL_L0L1A_RST_STATUS_0_FUSE_ASYNCL0RST_ENABLE_DISABLE                      _MK_ENUM_CONST(0)
#define PMC_IMPL_L0L1A_RST_STATUS_0_FUSE_ASYNCL0RST_ENABLE_ENABLE                       _MK_ENUM_CONST(1)

#define PMC_IMPL_L0L1A_RST_STATUS_0_FUSE_ASYNCL1ARST_ENABLE_SHIFT                       _MK_SHIFT_CONST(1)
#define PMC_IMPL_L0L1A_RST_STATUS_0_FUSE_ASYNCL1ARST_ENABLE_FIELD                       _MK_FIELD_CONST(0x1, PMC_IMPL_L0L1A_RST_STATUS_0_FUSE_ASYNCL1ARST_ENABLE_SHIFT)
#define PMC_IMPL_L0L1A_RST_STATUS_0_FUSE_ASYNCL1ARST_ENABLE_RANGE                       1:1
#define PMC_IMPL_L0L1A_RST_STATUS_0_FUSE_ASYNCL1ARST_ENABLE_WOFFSET                     0x0
#define PMC_IMPL_L0L1A_RST_STATUS_0_FUSE_ASYNCL1ARST_ENABLE_DEFAULT                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_L0L1A_RST_STATUS_0_FUSE_ASYNCL1ARST_ENABLE_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define PMC_IMPL_L0L1A_RST_STATUS_0_FUSE_ASYNCL1ARST_ENABLE_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define PMC_IMPL_L0L1A_RST_STATUS_0_FUSE_ASYNCL1ARST_ENABLE_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_L0L1A_RST_STATUS_0_FUSE_ASYNCL1ARST_ENABLE_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_L0L1A_RST_STATUS_0_FUSE_ASYNCL1ARST_ENABLE_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define PMC_IMPL_L0L1A_RST_STATUS_0_FUSE_ASYNCL1ARST_ENABLE_INIT_ENUM                   DISABLE
#define PMC_IMPL_L0L1A_RST_STATUS_0_FUSE_ASYNCL1ARST_ENABLE_DISABLE                     _MK_ENUM_CONST(0)
#define PMC_IMPL_L0L1A_RST_STATUS_0_FUSE_ASYNCL1ARST_ENABLE_ENABLE                      _MK_ENUM_CONST(1)


// Register PMC_IMPL_DVDD_RG_CNTRL_0
#define PMC_IMPL_DVDD_RG_CNTRL_0                        _MK_ADDR_CONST(0x8b0)
#define PMC_IMPL_DVDD_RG_CNTRL_0_SECURE                         0x0
#define PMC_IMPL_DVDD_RG_CNTRL_0_DUAL                   0x0
#define PMC_IMPL_DVDD_RG_CNTRL_0_SCR                    DVDD_SCR_0
#define PMC_IMPL_DVDD_RG_CNTRL_0_WORD_COUNT                     0x1
#define PMC_IMPL_DVDD_RG_CNTRL_0_RESET_VAL                      _MK_MASK_CONST(0x1)
#define PMC_IMPL_DVDD_RG_CNTRL_0_RESET_MASK                     _MK_MASK_CONST(0x1)
#define PMC_IMPL_DVDD_RG_CNTRL_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define PMC_IMPL_DVDD_RG_CNTRL_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_DVDD_RG_CNTRL_0_READ_MASK                      _MK_MASK_CONST(0x1)
#define PMC_IMPL_DVDD_RG_CNTRL_0_WRITE_MASK                     _MK_MASK_CONST(0x1)
#define PMC_IMPL_DVDD_RG_CNTRL_0_RAIL_CLAMP_SHIFT                       _MK_SHIFT_CONST(0)
#define PMC_IMPL_DVDD_RG_CNTRL_0_RAIL_CLAMP_FIELD                       _MK_FIELD_CONST(0x1, PMC_IMPL_DVDD_RG_CNTRL_0_RAIL_CLAMP_SHIFT)
#define PMC_IMPL_DVDD_RG_CNTRL_0_RAIL_CLAMP_RANGE                       0:0
#define PMC_IMPL_DVDD_RG_CNTRL_0_RAIL_CLAMP_WOFFSET                     0x0
#define PMC_IMPL_DVDD_RG_CNTRL_0_RAIL_CLAMP_DEFAULT                     _MK_MASK_CONST(0x1)
#define PMC_IMPL_DVDD_RG_CNTRL_0_RAIL_CLAMP_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define PMC_IMPL_DVDD_RG_CNTRL_0_RAIL_CLAMP_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define PMC_IMPL_DVDD_RG_CNTRL_0_RAIL_CLAMP_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_DVDD_RG_CNTRL_0_RAIL_CLAMP_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_DVDD_RG_CNTRL_0_RAIL_CLAMP_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define PMC_IMPL_DVDD_RG_CNTRL_0_RAIL_CLAMP_DISABLE                     _MK_ENUM_CONST(0)
#define PMC_IMPL_DVDD_RG_CNTRL_0_RAIL_CLAMP_ENABLE                      _MK_ENUM_CONST(1)


// Register PMC_IMPL_CV_RG_CNTRL_0
#define PMC_IMPL_CV_RG_CNTRL_0                  _MK_ADDR_CONST(0x8b4)
#define PMC_IMPL_CV_RG_CNTRL_0_SECURE                   0x0
#define PMC_IMPL_CV_RG_CNTRL_0_DUAL                     0x0
#define PMC_IMPL_CV_RG_CNTRL_0_SCR                      CV_SCR_0
#define PMC_IMPL_CV_RG_CNTRL_0_WORD_COUNT                       0x1
#define PMC_IMPL_CV_RG_CNTRL_0_RESET_VAL                        _MK_MASK_CONST(0x1)
#define PMC_IMPL_CV_RG_CNTRL_0_RESET_MASK                       _MK_MASK_CONST(0x1)
#define PMC_IMPL_CV_RG_CNTRL_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_CV_RG_CNTRL_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define PMC_IMPL_CV_RG_CNTRL_0_READ_MASK                        _MK_MASK_CONST(0x1)
#define PMC_IMPL_CV_RG_CNTRL_0_WRITE_MASK                       _MK_MASK_CONST(0x1)
#define PMC_IMPL_CV_RG_CNTRL_0_RAIL_CLAMP_SHIFT                 _MK_SHIFT_CONST(0)
#define PMC_IMPL_CV_RG_CNTRL_0_RAIL_CLAMP_FIELD                 _MK_FIELD_CONST(0x1, PMC_IMPL_CV_RG_CNTRL_0_RAIL_CLAMP_SHIFT)
#define PMC_IMPL_CV_RG_CNTRL_0_RAIL_CLAMP_RANGE                 0:0
#define PMC_IMPL_CV_RG_CNTRL_0_RAIL_CLAMP_WOFFSET                       0x0
#define PMC_IMPL_CV_RG_CNTRL_0_RAIL_CLAMP_DEFAULT                       _MK_MASK_CONST(0x1)
#define PMC_IMPL_CV_RG_CNTRL_0_RAIL_CLAMP_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define PMC_IMPL_CV_RG_CNTRL_0_RAIL_CLAMP_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define PMC_IMPL_CV_RG_CNTRL_0_RAIL_CLAMP_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define PMC_IMPL_CV_RG_CNTRL_0_RAIL_CLAMP_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_CV_RG_CNTRL_0_RAIL_CLAMP_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)
#define PMC_IMPL_CV_RG_CNTRL_0_RAIL_CLAMP_DISABLE                       _MK_ENUM_CONST(0)
#define PMC_IMPL_CV_RG_CNTRL_0_RAIL_CLAMP_ENABLE                        _MK_ENUM_CONST(1)


// Register PMC_IMPL_SC7_RST_REQ_TIMER_0
#define PMC_IMPL_SC7_RST_REQ_TIMER_0                    _MK_ADDR_CONST(0x8b8)
#define PMC_IMPL_SC7_RST_REQ_TIMER_0_SECURE                     0x0
#define PMC_IMPL_SC7_RST_REQ_TIMER_0_DUAL                       0x0
#define PMC_IMPL_SC7_RST_REQ_TIMER_0_SCR                        SC7_DEBUG_SCR_0
#define PMC_IMPL_SC7_RST_REQ_TIMER_0_WORD_COUNT                         0x1
#define PMC_IMPL_SC7_RST_REQ_TIMER_0_RESET_VAL                  _MK_MASK_CONST(0x1)
#define PMC_IMPL_SC7_RST_REQ_TIMER_0_RESET_MASK                         _MK_MASK_CONST(0xff)
#define PMC_IMPL_SC7_RST_REQ_TIMER_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_SC7_RST_REQ_TIMER_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define PMC_IMPL_SC7_RST_REQ_TIMER_0_READ_MASK                  _MK_MASK_CONST(0xff)
#define PMC_IMPL_SC7_RST_REQ_TIMER_0_WRITE_MASK                         _MK_MASK_CONST(0xff)
#define PMC_IMPL_SC7_RST_REQ_TIMER_0_PRERST_TGT_SHIFT                   _MK_SHIFT_CONST(0)
#define PMC_IMPL_SC7_RST_REQ_TIMER_0_PRERST_TGT_FIELD                   _MK_FIELD_CONST(0xf, PMC_IMPL_SC7_RST_REQ_TIMER_0_PRERST_TGT_SHIFT)
#define PMC_IMPL_SC7_RST_REQ_TIMER_0_PRERST_TGT_RANGE                   3:0
#define PMC_IMPL_SC7_RST_REQ_TIMER_0_PRERST_TGT_WOFFSET                 0x0
#define PMC_IMPL_SC7_RST_REQ_TIMER_0_PRERST_TGT_DEFAULT                 _MK_MASK_CONST(0x1)
#define PMC_IMPL_SC7_RST_REQ_TIMER_0_PRERST_TGT_DEFAULT_MASK                    _MK_MASK_CONST(0xf)
#define PMC_IMPL_SC7_RST_REQ_TIMER_0_PRERST_TGT_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_SC7_RST_REQ_TIMER_0_PRERST_TGT_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define PMC_IMPL_SC7_RST_REQ_TIMER_0_PRERST_TGT_PARITY_PROTECTION                       _MK_MASK_CONST(0x1)
#define PMC_IMPL_SC7_RST_REQ_TIMER_0_PRERST_TGT_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define PMC_IMPL_SC7_RST_REQ_TIMER_0_POSTRST_TGT_SHIFT                  _MK_SHIFT_CONST(4)
#define PMC_IMPL_SC7_RST_REQ_TIMER_0_POSTRST_TGT_FIELD                  _MK_FIELD_CONST(0xf, PMC_IMPL_SC7_RST_REQ_TIMER_0_POSTRST_TGT_SHIFT)
#define PMC_IMPL_SC7_RST_REQ_TIMER_0_POSTRST_TGT_RANGE                  7:4
#define PMC_IMPL_SC7_RST_REQ_TIMER_0_POSTRST_TGT_WOFFSET                        0x0
#define PMC_IMPL_SC7_RST_REQ_TIMER_0_POSTRST_TGT_DEFAULT                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_SC7_RST_REQ_TIMER_0_POSTRST_TGT_DEFAULT_MASK                   _MK_MASK_CONST(0xf)
#define PMC_IMPL_SC7_RST_REQ_TIMER_0_POSTRST_TGT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define PMC_IMPL_SC7_RST_REQ_TIMER_0_POSTRST_TGT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_SC7_RST_REQ_TIMER_0_POSTRST_TGT_PARITY_PROTECTION                      _MK_MASK_CONST(0x1)
#define PMC_IMPL_SC7_RST_REQ_TIMER_0_POSTRST_TGT_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)


// Register PMC_IMPL_RST_REQ_TIMER_0
#define PMC_IMPL_RST_REQ_TIMER_0                        _MK_ADDR_CONST(0x8bc)
#define PMC_IMPL_RST_REQ_TIMER_0_SECURE                         0x0
#define PMC_IMPL_RST_REQ_TIMER_0_DUAL                   0x0
#define PMC_IMPL_RST_REQ_TIMER_0_SCR                    CNTRL_SCR_0
#define PMC_IMPL_RST_REQ_TIMER_0_WORD_COUNT                     0x1
#define PMC_IMPL_RST_REQ_TIMER_0_RESET_VAL                      _MK_MASK_CONST(0x6)
#define PMC_IMPL_RST_REQ_TIMER_0_RESET_MASK                     _MK_MASK_CONST(0xff)
#define PMC_IMPL_RST_REQ_TIMER_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define PMC_IMPL_RST_REQ_TIMER_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_RST_REQ_TIMER_0_READ_MASK                      _MK_MASK_CONST(0xff)
#define PMC_IMPL_RST_REQ_TIMER_0_WRITE_MASK                     _MK_MASK_CONST(0xff)
#define PMC_IMPL_RST_REQ_TIMER_0_WAIT_CLK_STOP_VAL_SHIFT                        _MK_SHIFT_CONST(0)
#define PMC_IMPL_RST_REQ_TIMER_0_WAIT_CLK_STOP_VAL_FIELD                        _MK_FIELD_CONST(0xff, PMC_IMPL_RST_REQ_TIMER_0_WAIT_CLK_STOP_VAL_SHIFT)
#define PMC_IMPL_RST_REQ_TIMER_0_WAIT_CLK_STOP_VAL_RANGE                        7:0
#define PMC_IMPL_RST_REQ_TIMER_0_WAIT_CLK_STOP_VAL_WOFFSET                      0x0
#define PMC_IMPL_RST_REQ_TIMER_0_WAIT_CLK_STOP_VAL_DEFAULT                      _MK_MASK_CONST(0x6)
#define PMC_IMPL_RST_REQ_TIMER_0_WAIT_CLK_STOP_VAL_DEFAULT_MASK                 _MK_MASK_CONST(0xff)
#define PMC_IMPL_RST_REQ_TIMER_0_WAIT_CLK_STOP_VAL_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_RST_REQ_TIMER_0_WAIT_CLK_STOP_VAL_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_RST_REQ_TIMER_0_WAIT_CLK_STOP_VAL_PARITY_PROTECTION                    _MK_MASK_CONST(0x1)
#define PMC_IMPL_RST_REQ_TIMER_0_WAIT_CLK_STOP_VAL_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)


// Register PMC_IMPL_ASYNC_RST_SC7_CONFIG_0
#define PMC_IMPL_ASYNC_RST_SC7_CONFIG_0                 _MK_ADDR_CONST(0x8c0)
#define PMC_IMPL_ASYNC_RST_SC7_CONFIG_0_SECURE                  0x0
#define PMC_IMPL_ASYNC_RST_SC7_CONFIG_0_DUAL                    0x0
#define PMC_IMPL_ASYNC_RST_SC7_CONFIG_0_SCR                     ASYNC_RST_SC7_SCR_0
#define PMC_IMPL_ASYNC_RST_SC7_CONFIG_0_WORD_COUNT                      0x1
#define PMC_IMPL_ASYNC_RST_SC7_CONFIG_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define PMC_IMPL_ASYNC_RST_SC7_CONFIG_0_RESET_MASK                      _MK_MASK_CONST(0x1)
#define PMC_IMPL_ASYNC_RST_SC7_CONFIG_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define PMC_IMPL_ASYNC_RST_SC7_CONFIG_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define PMC_IMPL_ASYNC_RST_SC7_CONFIG_0_READ_MASK                       _MK_MASK_CONST(0x1)
#define PMC_IMPL_ASYNC_RST_SC7_CONFIG_0_WRITE_MASK                      _MK_MASK_CONST(0x1)
#define PMC_IMPL_ASYNC_RST_SC7_CONFIG_0_SW_SC7_DIS_SHIFT                        _MK_SHIFT_CONST(0)
#define PMC_IMPL_ASYNC_RST_SC7_CONFIG_0_SW_SC7_DIS_FIELD                        _MK_FIELD_CONST(0x1, PMC_IMPL_ASYNC_RST_SC7_CONFIG_0_SW_SC7_DIS_SHIFT)
#define PMC_IMPL_ASYNC_RST_SC7_CONFIG_0_SW_SC7_DIS_RANGE                        0:0
#define PMC_IMPL_ASYNC_RST_SC7_CONFIG_0_SW_SC7_DIS_WOFFSET                      0x0
#define PMC_IMPL_ASYNC_RST_SC7_CONFIG_0_SW_SC7_DIS_DEFAULT                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_ASYNC_RST_SC7_CONFIG_0_SW_SC7_DIS_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define PMC_IMPL_ASYNC_RST_SC7_CONFIG_0_SW_SC7_DIS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_ASYNC_RST_SC7_CONFIG_0_SW_SC7_DIS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define PMC_IMPL_ASYNC_RST_SC7_CONFIG_0_SW_SC7_DIS_PARITY_PROTECTION                    _MK_MASK_CONST(0x1)
#define PMC_IMPL_ASYNC_RST_SC7_CONFIG_0_SW_SC7_DIS_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)
#define PMC_IMPL_ASYNC_RST_SC7_CONFIG_0_SW_SC7_DIS_INIT_ENUM                    UNMASKED
#define PMC_IMPL_ASYNC_RST_SC7_CONFIG_0_SW_SC7_DIS_UNMASKED                     _MK_ENUM_CONST(0)
#define PMC_IMPL_ASYNC_RST_SC7_CONFIG_0_SW_SC7_DIS_MASKED                       _MK_ENUM_CONST(1)


// Register PMC_IMPL_PMC_RESET_DETECTOR_0
#define PMC_IMPL_PMC_RESET_DETECTOR_0                   _MK_ADDR_CONST(0x8c4)
#define PMC_IMPL_PMC_RESET_DETECTOR_0_SECURE                    0x0
#define PMC_IMPL_PMC_RESET_DETECTOR_0_DUAL                      0x0
#define PMC_IMPL_PMC_RESET_DETECTOR_0_SCR                       0
#define PMC_IMPL_PMC_RESET_DETECTOR_0_WORD_COUNT                        0x1
#define PMC_IMPL_PMC_RESET_DETECTOR_0_RESET_VAL                         _MK_MASK_CONST(0x1)
#define PMC_IMPL_PMC_RESET_DETECTOR_0_RESET_MASK                        _MK_MASK_CONST(0x1)
#define PMC_IMPL_PMC_RESET_DETECTOR_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define PMC_IMPL_PMC_RESET_DETECTOR_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define PMC_IMPL_PMC_RESET_DETECTOR_0_READ_MASK                         _MK_MASK_CONST(0x1)
#define PMC_IMPL_PMC_RESET_DETECTOR_0_WRITE_MASK                        _MK_MASK_CONST(0x0)
#define PMC_IMPL_PMC_RESET_DETECTOR_0_pmc2dfd_reset_detector_SHIFT                      _MK_SHIFT_CONST(0)
#define PMC_IMPL_PMC_RESET_DETECTOR_0_pmc2dfd_reset_detector_FIELD                      _MK_FIELD_CONST(0x1, PMC_IMPL_PMC_RESET_DETECTOR_0_pmc2dfd_reset_detector_SHIFT)
#define PMC_IMPL_PMC_RESET_DETECTOR_0_pmc2dfd_reset_detector_RANGE                      0:0
#define PMC_IMPL_PMC_RESET_DETECTOR_0_pmc2dfd_reset_detector_WOFFSET                    0x0
#define PMC_IMPL_PMC_RESET_DETECTOR_0_pmc2dfd_reset_detector_DEFAULT                    _MK_MASK_CONST(0x1)
#define PMC_IMPL_PMC_RESET_DETECTOR_0_pmc2dfd_reset_detector_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define PMC_IMPL_PMC_RESET_DETECTOR_0_pmc2dfd_reset_detector_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define PMC_IMPL_PMC_RESET_DETECTOR_0_pmc2dfd_reset_detector_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define PMC_IMPL_PMC_RESET_DETECTOR_0_pmc2dfd_reset_detector_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define PMC_IMPL_PMC_RESET_DETECTOR_0_pmc2dfd_reset_detector_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define PMC_IMPL_PMC_RESET_DETECTOR_0_pmc2dfd_reset_detector_INIT_ENUM                  DETECTED
#define PMC_IMPL_PMC_RESET_DETECTOR_0_pmc2dfd_reset_detector_DETECTED                   _MK_ENUM_CONST(1)
#define PMC_IMPL_PMC_RESET_DETECTOR_0_pmc2dfd_reset_detector_NOT_DETECTED                       _MK_ENUM_CONST(0)


//
// REGISTER LIST
//
#define LIST_ARPMC_IMPL_REGS(_op_) \
_op_(PMC_IMPL_CNTRL_0) \
_op_(PMC_IMPL_SLCG_CTRL_0) \
_op_(PMC_IMPL_DPD_PADS_ORIDE_0) \
_op_(PMC_IMPL_DPD_ENABLE_0) \
_op_(PMC_IMPL_SC7_CONFIG_0) \
_op_(PMC_IMPL_SC7_STATUS_0) \
_op_(PMC_IMPL_SC8_FSM_INIT_0) \
_op_(PMC_IMPL_SC8_CONTROL_0) \
_op_(PMC_IMPL_RETENTION_CONTROL_0) \
_op_(PMC_IMPL_SC7_DEBUG_CTRL_0) \
_op_(PMC_IMPL_PWRGOOD_TIMER_0) \
_op_(PMC_IMPL_BLINK_TIMER_0) \
_op_(PMC_IMPL_NO_IOPOWER_0) \
_op_(PMC_IMPL_E_18V_PWR_0) \
_op_(PMC_IMPL_E_33V_PWR_0) \
_op_(PMC_IMPL_OSC_EDPD_OVER_0) \
_op_(PMC_IMPL_CLK_OUT_CNTRL_0) \
_op_(PMC_IMPL_SENSOR_CTRL_0) \
_op_(PMC_IMPL_RST_STATUS_0) \
_op_(PMC_IMPL_IO_DPD_REQ_0) \
_op_(PMC_IMPL_IO_DPD_STATUS_0) \
_op_(PMC_IMPL_IO_DPD2_REQ_0) \
_op_(PMC_IMPL_IO_DPD2_STATUS_0) \
_op_(PMC_IMPL_IO_DPD7_REQ_0) \
_op_(PMC_IMPL_IO_DPD7_STATUS_0) \
_op_(PMC_IMPL_IO_DPD8_REQ_0) \
_op_(PMC_IMPL_IO_DPD8_STATUS_0) \
_op_(PMC_IMPL_IO_DPD7_OFF_MASK_0) \
_op_(PMC_IMPL_IO_DPD8_OFF_MASK_0) \
_op_(PMC_IMPL_SEL_DPD_TIM_0) \
_op_(PMC_IMPL_TSC_MULT_0) \
_op_(PMC_IMPL_GLB_AMAP_CFG_0) \
_op_(PMC_IMPL_GPU_RG_CNTRL_0) \
_op_(PMC_IMPL_UFSHC_PWR_CNTRL_0) \
_op_(PMC_IMPL_CNTRL2_0) \
_op_(PMC_IMPL_EVENT_COUNTER_0) \
_op_(PMC_IMPL_DIRECT_THERMTRIP_CFG_0) \
_op_(PMC_IMPL_RAMDUMP_CTL_STATUS_0) \
_op_(PMC_IMPL_RAMDUMP_TIMEOUT_0) \
_op_(PMC_IMPL_RST_REQ_CONFIG_0) \
_op_(PMC_IMPL_RST_REQ_CNTVAL_0) \
_op_(PMC_IMPL_VFMON_ACTION_0) \
_op_(PMC_IMPL_VFMON_INT_STATUS_0) \
_op_(PMC_IMPL_VFMON_INT_MASK_0) \
_op_(PMC_IMPL_POWER_GATE_TIMERS_0) \
_op_(PMC_IMPL_LOGIC_ZONE_DELAY_0) \
_op_(PMC_IMPL_SRAM_ZONE_DELAY_0) \
_op_(PMC_IMPL_ZONE_CONFIG_0) \
_op_(PMC_IMPL_INTER_PARTITION_PG_DELAY_0) \
_op_(PMC_IMPL_AO_PG_TIMERS_0) \
_op_(PMC_IMPL_PG_STATUS_0) \
_op_(PMC_IMPL_PART_AUD_POWER_GATE_CONTROL_0) \
_op_(PMC_IMPL_PART_AUD_POWER_GATE_STATUS_0) \
_op_(PMC_IMPL_PART_AUD_CLAMP_CONTROL_0) \
_op_(PMC_IMPL_PART_DISP_POWER_GATE_CONTROL_0) \
_op_(PMC_IMPL_PART_DISP_POWER_GATE_STATUS_0) \
_op_(PMC_IMPL_PART_DISP_CLAMP_CONTROL_0) \
_op_(PMC_IMPL_PART_DISPB_POWER_GATE_CONTROL_0) \
_op_(PMC_IMPL_PART_DISPB_POWER_GATE_STATUS_0) \
_op_(PMC_IMPL_PART_DISPB_CLAMP_CONTROL_0) \
_op_(PMC_IMPL_PART_DISPC_POWER_GATE_CONTROL_0) \
_op_(PMC_IMPL_PART_DISPC_POWER_GATE_STATUS_0) \
_op_(PMC_IMPL_PART_DISPC_CLAMP_CONTROL_0) \
_op_(PMC_IMPL_PART_ISPA_POWER_GATE_CONTROL_0) \
_op_(PMC_IMPL_PART_ISPA_POWER_GATE_STATUS_0) \
_op_(PMC_IMPL_PART_ISPA_CLAMP_CONTROL_0) \
_op_(PMC_IMPL_PART_NVDECA_POWER_GATE_CONTROL_0) \
_op_(PMC_IMPL_PART_NVDECA_POWER_GATE_STATUS_0) \
_op_(PMC_IMPL_PART_NVDECA_CLAMP_CONTROL_0) \
_op_(PMC_IMPL_PART_NVJPG_POWER_GATE_CONTROL_0) \
_op_(PMC_IMPL_PART_NVJPG_POWER_GATE_STATUS_0) \
_op_(PMC_IMPL_PART_NVJPG_CLAMP_CONTROL_0) \
_op_(PMC_IMPL_PART_SAX_POWER_GATE_CONTROL_0) \
_op_(PMC_IMPL_PART_SAX_POWER_GATE_STATUS_0) \
_op_(PMC_IMPL_PART_SAX_CLAMP_CONTROL_0) \
_op_(PMC_IMPL_PART_VE_POWER_GATE_CONTROL_0) \
_op_(PMC_IMPL_PART_VE_POWER_GATE_STATUS_0) \
_op_(PMC_IMPL_PART_VE_CLAMP_CONTROL_0) \
_op_(PMC_IMPL_PART_VIC_POWER_GATE_CONTROL_0) \
_op_(PMC_IMPL_PART_VIC_POWER_GATE_STATUS_0) \
_op_(PMC_IMPL_PART_VIC_CLAMP_CONTROL_0) \
_op_(PMC_IMPL_PART_XUSBA_POWER_GATE_CONTROL_0) \
_op_(PMC_IMPL_PART_XUSBA_POWER_GATE_STATUS_0) \
_op_(PMC_IMPL_PART_XUSBA_CLAMP_CONTROL_0) \
_op_(PMC_IMPL_PART_XUSBB_POWER_GATE_CONTROL_0) \
_op_(PMC_IMPL_PART_XUSBB_POWER_GATE_STATUS_0) \
_op_(PMC_IMPL_PART_XUSBB_CLAMP_CONTROL_0) \
_op_(PMC_IMPL_PART_XUSBC_POWER_GATE_CONTROL_0) \
_op_(PMC_IMPL_PART_XUSBC_POWER_GATE_STATUS_0) \
_op_(PMC_IMPL_PART_XUSBC_CLAMP_CONTROL_0) \
_op_(PMC_IMPL_PART_SCRATCH_POWER_GATE_CONTROL_0) \
_op_(PMC_IMPL_PART_SCRATCH_POWER_GATE_STATUS_0) \
_op_(PMC_IMPL_PART_SCRATCH_CLAMP_CONTROL_0) \
_op_(PMC_IMPL_PART_AONPG_POWER_GATE_CONTROL_0) \
_op_(PMC_IMPL_PART_AONPG_POWER_GATE_STATUS_0) \
_op_(PMC_IMPL_PART_AONPG_CLAMP_CONTROL_0) \
_op_(PMC_IMPL_PART_BPMP_POWER_GATE_CONTROL_0) \
_op_(PMC_IMPL_PART_BPMP_POWER_GATE_STATUS_0) \
_op_(PMC_IMPL_PART_BPMP_CLAMP_CONTROL_0) \
_op_(PMC_IMPL_PART_SCE_POWER_GATE_CONTROL_0) \
_op_(PMC_IMPL_PART_SCE_POWER_GATE_STATUS_0) \
_op_(PMC_IMPL_PART_SCE_CLAMP_CONTROL_0) \
_op_(PMC_IMPL_PART_AOPG_TCM0_POWER_GATE_CONTROL_0) \
_op_(PMC_IMPL_PART_AOPG_TCM0_POWER_GATE_STATUS_0) \
_op_(PMC_IMPL_PART_AOPG_TCM0_CLAMP_CONTROL_0) \
_op_(PMC_IMPL_PART_AOPG_TCM1_POWER_GATE_CONTROL_0) \
_op_(PMC_IMPL_PART_AOPG_TCM1_POWER_GATE_STATUS_0) \
_op_(PMC_IMPL_PART_AOPG_TCM1_CLAMP_CONTROL_0) \
_op_(PMC_IMPL_PART_AOPG_TCM2_POWER_GATE_CONTROL_0) \
_op_(PMC_IMPL_PART_AOPG_TCM2_POWER_GATE_STATUS_0) \
_op_(PMC_IMPL_PART_AOPG_TCM2_CLAMP_CONTROL_0) \
_op_(PMC_IMPL_PART_AOPG_TCM3_POWER_GATE_CONTROL_0) \
_op_(PMC_IMPL_PART_AOPG_TCM3_POWER_GATE_STATUS_0) \
_op_(PMC_IMPL_PART_AOPG_TCM3_CLAMP_CONTROL_0) \
_op_(PMC_IMPL_PART_AOPG_TCM4_POWER_GATE_CONTROL_0) \
_op_(PMC_IMPL_PART_AOPG_TCM4_POWER_GATE_STATUS_0) \
_op_(PMC_IMPL_PART_AOPG_TCM4_CLAMP_CONTROL_0) \
_op_(PMC_IMPL_PART_AOPG_TCM5_POWER_GATE_CONTROL_0) \
_op_(PMC_IMPL_PART_AOPG_TCM5_POWER_GATE_STATUS_0) \
_op_(PMC_IMPL_PART_AOPG_TCM5_CLAMP_CONTROL_0) \
_op_(PMC_IMPL_PART_AOPG_TCM6_POWER_GATE_CONTROL_0) \
_op_(PMC_IMPL_PART_AOPG_TCM6_POWER_GATE_STATUS_0) \
_op_(PMC_IMPL_PART_AOPG_TCM6_CLAMP_CONTROL_0) \
_op_(PMC_IMPL_PART_AOPG_TCM7_POWER_GATE_CONTROL_0) \
_op_(PMC_IMPL_PART_AOPG_TCM7_POWER_GATE_STATUS_0) \
_op_(PMC_IMPL_PART_AOPG_TCM7_CLAMP_CONTROL_0) \
_op_(PMC_IMPL_PART_AOPG_CACHE_POWER_GATE_CONTROL_0) \
_op_(PMC_IMPL_PART_AOPG_CACHE_POWER_GATE_STATUS_0) \
_op_(PMC_IMPL_PART_AOPG_CACHE_CLAMP_CONTROL_0) \
_op_(PMC_IMPL_PART_AOPG_CAN0_POWER_GATE_CONTROL_0) \
_op_(PMC_IMPL_PART_AOPG_CAN0_POWER_GATE_STATUS_0) \
_op_(PMC_IMPL_PART_AOPG_CAN0_CLAMP_CONTROL_0) \
_op_(PMC_IMPL_PART_AOPG_CAN1_POWER_GATE_CONTROL_0) \
_op_(PMC_IMPL_PART_AOPG_CAN1_POWER_GATE_STATUS_0) \
_op_(PMC_IMPL_PART_AOPG_CAN1_CLAMP_CONTROL_0) \
_op_(PMC_IMPL_PART_MSS_SCRATCH_POWER_GATE_CONTROL_0) \
_op_(PMC_IMPL_PART_MSS_SCRATCH_POWER_GATE_STATUS_0) \
_op_(PMC_IMPL_PART_MSS_SCRATCH_CLAMP_CONTROL_0) \
_op_(PMC_IMPL_PART_PCIEX8A_POWER_GATE_CONTROL_0) \
_op_(PMC_IMPL_PART_PCIEX8A_POWER_GATE_STATUS_0) \
_op_(PMC_IMPL_PART_PCIEX8A_CLAMP_CONTROL_0) \
_op_(PMC_IMPL_PART_PCIEX4A_POWER_GATE_CONTROL_0) \
_op_(PMC_IMPL_PART_PCIEX4A_POWER_GATE_STATUS_0) \
_op_(PMC_IMPL_PART_PCIEX4A_CLAMP_CONTROL_0) \
_op_(PMC_IMPL_PART_PCIEX1A_POWER_GATE_CONTROL_0) \
_op_(PMC_IMPL_PART_PCIEX1A_POWER_GATE_STATUS_0) \
_op_(PMC_IMPL_PART_PCIEX1A_CLAMP_CONTROL_0) \
_op_(PMC_IMPL_PART_NVL_POWER_GATE_CONTROL_0) \
_op_(PMC_IMPL_PART_NVL_POWER_GATE_STATUS_0) \
_op_(PMC_IMPL_PART_NVL_CLAMP_CONTROL_0) \
_op_(PMC_IMPL_PART_PCIEX8B_POWER_GATE_CONTROL_0) \
_op_(PMC_IMPL_PART_PCIEX8B_POWER_GATE_STATUS_0) \
_op_(PMC_IMPL_PART_PCIEX8B_CLAMP_CONTROL_0) \
_op_(PMC_IMPL_PART_PVAA_POWER_GATE_CONTROL_0) \
_op_(PMC_IMPL_PART_PVAA_POWER_GATE_STATUS_0) \
_op_(PMC_IMPL_PART_PVAA_CLAMP_CONTROL_0) \
_op_(PMC_IMPL_PART_PVAB_POWER_GATE_CONTROL_0) \
_op_(PMC_IMPL_PART_PVAB_POWER_GATE_STATUS_0) \
_op_(PMC_IMPL_PART_PVAB_CLAMP_CONTROL_0) \
_op_(PMC_IMPL_PART_DLAA_POWER_GATE_CONTROL_0) \
_op_(PMC_IMPL_PART_DLAA_POWER_GATE_STATUS_0) \
_op_(PMC_IMPL_PART_DLAA_CLAMP_CONTROL_0) \
_op_(PMC_IMPL_PART_DLAB_POWER_GATE_CONTROL_0) \
_op_(PMC_IMPL_PART_DLAB_POWER_GATE_STATUS_0) \
_op_(PMC_IMPL_PART_DLAB_CLAMP_CONTROL_0) \
_op_(PMC_IMPL_PART_NVENCA_POWER_GATE_CONTROL_0) \
_op_(PMC_IMPL_PART_NVENCA_POWER_GATE_STATUS_0) \
_op_(PMC_IMPL_PART_NVENCA_CLAMP_CONTROL_0) \
_op_(PMC_IMPL_PART_NVENCB_POWER_GATE_CONTROL_0) \
_op_(PMC_IMPL_PART_NVENCB_POWER_GATE_STATUS_0) \
_op_(PMC_IMPL_PART_NVENCB_CLAMP_CONTROL_0) \
_op_(PMC_IMPL_PART_RCE_POWER_GATE_CONTROL_0) \
_op_(PMC_IMPL_PART_RCE_POWER_GATE_STATUS_0) \
_op_(PMC_IMPL_PART_RCE_CLAMP_CONTROL_0) \
_op_(PMC_IMPL_PART_NVDECB_POWER_GATE_CONTROL_0) \
_op_(PMC_IMPL_PART_NVDECB_POWER_GATE_STATUS_0) \
_op_(PMC_IMPL_PART_NVDECB_CLAMP_CONTROL_0) \
_op_(PMC_IMPL_SW_OVERRIDE_CTRL_1_0) \
_op_(PMC_IMPL_SW_OVERRIDE_CTRL_2_0) \
_op_(PMC_IMPL_MISC_CTRL_0) \
_op_(PMC_IMPL_PMC2LIC_INTR_STATUS_0) \
_op_(PMC_IMPL_PMC2LIC_INTR_ENABLE_0) \
_op_(PMC_IMPL_AOVC_LOCK_CNTRL_0) \
_op_(PMC_IMPL_AOVC_LOCK_ID_STATUS_0) \
_op_(PMC_IMPL_TEST_CLK_MUX_SEL_0) \
_op_(PMC_IMPL_DPD_FSM_STATUS_0) \
_op_(PMC_IMPL_SC7_FSM_STATUS_0) \
_op_(PMC_IMPL_RAMDUMP_FIQ_EXIT_0) \
_op_(PMC_IMPL_SET_RAMDUMP_FIQ_EXIT_0) \
_op_(PMC_IMPL_CLR_RAMDUMP_FIQ_EXIT_0) \
_op_(PMC_IMPL_FMON_THRESHOLD_HIGH_PMC_CK_0) \
_op_(PMC_IMPL_FMON_THRESHOLD_LOW_PMC_CK_0) \
_op_(PMC_IMPL_FMON_REF_WINDOW_COUNT_PMC_CK_0) \
_op_(PMC_IMPL_FMON_REF_WINDOW_DC_CHECK_COUNT_PMC_CK_0) \
_op_(PMC_IMPL_FMON_FAULT_ACTION_PMC_CK_0) \
_op_(PMC_IMPL_FMON_CONFIG_PMC_CK_0) \
_op_(PMC_IMPL_FMON_ENABLE_STATUS_PMC_CK_0) \
_op_(PMC_IMPL_FMON_FAULT_STATUS_PMC_CK_0) \
_op_(PMC_IMPL_FMON_LOAD_DATA_CTRL_PMC_CK_0) \
_op_(PMC_IMPL_FMON_LOAD_DATA_STATUS_0_PMC_CK_0) \
_op_(PMC_IMPL_FMON_LOAD_DATA_STATUS_1_PMC_CK_0) \
_op_(PMC_IMPL_FMON_LOAD_DATA_STATUS_2_PMC_CK_0) \
_op_(PMC_IMPL_FMON_CLEAR_COUNTER_PMC_CK_0) \
_op_(PMC_IMPL_FMON_DEBUG_CONFIG_PMC_CK_0) \
_op_(PMC_IMPL_FMON_CNTR_OVERFLOW_CTRL_PMC_CK_0) \
_op_(PMC_IMPL_FMON_THRESHOLD_HIGH_OSCnFUSE_CK_0) \
_op_(PMC_IMPL_FMON_THRESHOLD_LOW_OSCnFUSE_CK_0) \
_op_(PMC_IMPL_FMON_REF_WINDOW_COUNT_OSCnFUSE_CK_0) \
_op_(PMC_IMPL_FMON_REF_WINDOW_DC_CHECK_COUNT_OSCnFUSE_CK_0) \
_op_(PMC_IMPL_FMON_FAULT_ACTION_OSCnFUSE_CK_0) \
_op_(PMC_IMPL_FMON_CONFIG_OSCnFUSE_CK_0) \
_op_(PMC_IMPL_FMON_ENABLE_STATUS_OSCnFUSE_CK_0) \
_op_(PMC_IMPL_FMON_FAULT_STATUS_OSCnFUSE_CK_0) \
_op_(PMC_IMPL_FMON_LOAD_DATA_CTRL_OSCnFUSE_CK_0) \
_op_(PMC_IMPL_FMON_LOAD_DATA_STATUS_0_OSCnFUSE_CK_0) \
_op_(PMC_IMPL_FMON_LOAD_DATA_STATUS_1_OSCnFUSE_CK_0) \
_op_(PMC_IMPL_FMON_LOAD_DATA_STATUS_2_OSCnFUSE_CK_0) \
_op_(PMC_IMPL_FMON_CLEAR_COUNTER_OSCnFUSE_CK_0) \
_op_(PMC_IMPL_FMON_DEBUG_CONFIG_OSCnFUSE_CK_0) \
_op_(PMC_IMPL_FMON_CNTR_OVERFLOW_CTRL_OSCnFUSE_CK_0) \
_op_(PMC_IMPL_FMON_DBG_CONFIG_0) \
_op_(PMC_IMPL_L0L1A_RST_SOURCE_EN_0) \
_op_(PMC_IMPL_L0L1A_RST_LEVEL_EN_0) \
_op_(PMC_IMPL_L0L1A_RST_STATUS_0) \
_op_(PMC_IMPL_DVDD_RG_CNTRL_0) \
_op_(PMC_IMPL_CV_RG_CNTRL_0) \
_op_(PMC_IMPL_SC7_RST_REQ_TIMER_0) \
_op_(PMC_IMPL_RST_REQ_TIMER_0) \
_op_(PMC_IMPL_ASYNC_RST_SC7_CONFIG_0) \
_op_(PMC_IMPL_PMC_RESET_DETECTOR_0)


//
// ADDRESS SPACES
//

#define BASE_ADDRESS_PMC_IMPL   0x00000000

//
// ARPMC_IMPL REGISTER BANKS
//

#define PMC_IMPL0_FIRST_REG 0x0000 // PMC_IMPL_CNTRL_0
#define PMC_IMPL0_LAST_REG 0x0008 // PMC_IMPL_DPD_PADS_ORIDE_0
#define PMC_IMPL1_FIRST_REG 0x0010 // PMC_IMPL_DPD_ENABLE_0
#define PMC_IMPL1_LAST_REG 0x0034 // PMC_IMPL_NO_IOPOWER_0
#define PMC_IMPL2_FIRST_REG 0x003c // PMC_IMPL_E_18V_PWR_0
#define PMC_IMPL2_LAST_REG 0x0040 // PMC_IMPL_E_33V_PWR_0
#define PMC_IMPL3_FIRST_REG 0x0060 // PMC_IMPL_OSC_EDPD_OVER_0
#define PMC_IMPL3_LAST_REG 0x0064 // PMC_IMPL_CLK_OUT_CNTRL_0
#define PMC_IMPL4_FIRST_REG 0x006c // PMC_IMPL_SENSOR_CTRL_0
#define PMC_IMPL4_LAST_REG 0x0080 // PMC_IMPL_IO_DPD2_STATUS_0
#define PMC_IMPL5_FIRST_REG 0x00a4 // PMC_IMPL_IO_DPD7_REQ_0
#define PMC_IMPL5_LAST_REG 0x00bc // PMC_IMPL_SEL_DPD_TIM_0
#define PMC_IMPL6_FIRST_REG 0x00d4 // PMC_IMPL_TSC_MULT_0
#define PMC_IMPL6_LAST_REG 0x00d8 // PMC_IMPL_GLB_AMAP_CFG_0
#define PMC_IMPL7_FIRST_REG 0x00e8 // PMC_IMPL_GPU_RG_CNTRL_0
#define PMC_IMPL7_LAST_REG 0x00e8 // PMC_IMPL_GPU_RG_CNTRL_0
#define PMC_IMPL8_FIRST_REG 0x00f4 // PMC_IMPL_UFSHC_PWR_CNTRL_0
#define PMC_IMPL8_LAST_REG 0x00fc // PMC_IMPL_EVENT_COUNTER_0
#define PMC_IMPL9_FIRST_REG 0x0104 // PMC_IMPL_DIRECT_THERMTRIP_CFG_0
#define PMC_IMPL9_LAST_REG 0x0104 // PMC_IMPL_DIRECT_THERMTRIP_CFG_0
#define PMC_IMPL10_FIRST_REG 0x010c // PMC_IMPL_RAMDUMP_CTL_STATUS_0
#define PMC_IMPL10_LAST_REG 0x0118 // PMC_IMPL_RST_REQ_CNTVAL_0
#define PMC_IMPL11_FIRST_REG 0x01d4 // PMC_IMPL_VFMON_ACTION_0
#define PMC_IMPL11_LAST_REG 0x01dc // PMC_IMPL_VFMON_INT_MASK_0
#define PMC_IMPL12_FIRST_REG 0x01ec // PMC_IMPL_POWER_GATE_TIMERS_0
#define PMC_IMPL12_LAST_REG 0x0210 // PMC_IMPL_PART_AUD_CLAMP_CONTROL_0
#define PMC_IMPL13_FIRST_REG 0x0220 // PMC_IMPL_PART_DISP_POWER_GATE_CONTROL_0
#define PMC_IMPL13_LAST_REG 0x0264 // PMC_IMPL_PART_NVJPG_CLAMP_CONTROL_0
#define PMC_IMPL14_FIRST_REG 0x0280 // PMC_IMPL_PART_SAX_POWER_GATE_CONTROL_0
#define PMC_IMPL14_LAST_REG 0x02dc // PMC_IMPL_PART_AONPG_CLAMP_CONTROL_0
#define PMC_IMPL15_FIRST_REG 0x0370 // PMC_IMPL_PART_BPMP_POWER_GATE_CONTROL_0
#define PMC_IMPL15_LAST_REG 0x0408 // PMC_IMPL_PART_AOPG_CAN1_CLAMP_CONTROL_0
#define PMC_IMPL16_FIRST_REG 0x0418 // PMC_IMPL_PART_MSS_SCRATCH_POWER_GATE_CONTROL_0
#define PMC_IMPL16_LAST_REG 0x04c8 // PMC_IMPL_MISC_CTRL_0
#define PMC_IMPL17_FIRST_REG 0x0800 // PMC_IMPL_PMC2LIC_INTR_STATUS_0
#define PMC_IMPL17_LAST_REG 0x08c4 // PMC_IMPL_PMC_RESET_DETECTOR_0

// To satisfy various compilers and platforms,
// we let users control the types and syntax of certain constants, using macros.
#ifndef _MK_SHIFT_CONST
  #define _MK_SHIFT_CONST(_constant_) _constant_
#endif
#ifndef _MK_MASK_CONST
  #define _MK_MASK_CONST(_constant_) _constant_
#endif
#ifndef _MK_ENUM_CONST
  #define _MK_ENUM_CONST(_constant_) (_constant_ ## UL)
#endif
#ifndef _MK_ADDR_CONST
  #define _MK_ADDR_CONST(_constant_) _constant_
#endif
#ifndef _MK_FIELD_CONST
  #define _MK_FIELD_CONST(_mask_, _shift_) (_MK_MASK_CONST(_mask_) << _MK_SHIFT_CONST(_shift_))
#endif

#endif // ifndef ___ARPMC_IMPL_H_INC_
