#ifndef ARDEV_T_FPCI_SATA0_H_
#define ARDEV_T_FPCI_SATA0_H_

// generated by manual_ref_to_h.py from dev_t_fpci_sata0.ref - do not edit

//
// Copyright (c) 2011 NVIDIA Corporation.
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are met:
//
// Redistributions of source code must retain the above copyright notice,
// this list of conditions and the following disclaimer.
//
// Redistributions in binary form must reproduce the above copyright notice,
// this list of conditions and the following disclaimer in the documentation
// and/or other materials provided with the distribution.
//
// Neither the name of the NVIDIA Corporation nor the names of its contributors
// may be used to endorse or promote products derived from this software
// without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS AS IS
// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
// POSSIBILITY OF SUCH DAMAGE.
// 
// 
// 
// 
// 
// 
// 
// 
// 
// 
//                          SATA FPCI Bus Reference Manual
// 
//                                   Ambuj Kumar
// 
// 
//                                NVidia Corporation
// 
//                                  2701 San Tomas Expy
// 
//                               Santa Clara, CA  95050
// 
// 
// 
//                                  $Id: //hw/mcp/manuals/dev_t_pxb_sata.ref#10 $
// 
//                                  $Date: 2008/1/20 $
// 
// 
// 
// 
// 
// 
// 
// 
// 
// 
// 
// 
// 
// 
// 
// 
// 
// 
// 
// 
// 
// 
// This Document contains unpublished, proprietary information and describes
// subject matter proprietary to NVidia Corporation.  This document may not be
// disclosed to third parties or copied or duplicated in any form without the
// prior written consent of NVidia Corporation.
// 
// 
// .LABEL PRIVATE
// 
// 
// 
// 
// CONTENTS
// 
// Chapter  1  -  Introduction
// 
// Chapter  2  -  Boot Registers
// 
// Chapter  3  -  Delay Registers
// 
// Chapter  4  -  Debug Registers
// 
// Chapter  5  -  Green Registers
// 
// Chapter  6  -  Interrupt Registers
// 
// Chapter  7  -  Context Switching Registers
// 
// Chapter  8  -  Configuration Registers
// 
// Chapter  9  -  Real Mode Control Registers
// 
// Chapter 10  -  PCI Configuration Registers
// 
// Appendix A  -  NV3 Memory Map
// 
// Appendix B  -  Bus Interface Acknowledges
// 
// Appendix C  -  Issues
// 
// Appendix D  -  Key
// 
// 
// 
// 
// 0  -  PRELIMINARY MANUAL CAVEATS/WARNINGS/ISSUES/EDITORIAL NOTES
// 
//         The module is paramatizable. Therefore, this manual will need to be
// modified for each block.
// 
// 
// 
// 1  -  INTRODUCTION
// 
//         The FPCI is a standard interface used internally to the Crush architecture.
// It is based on PCI 2.2 but has extentions for support split read
// transactions.
// 
// 
// 
// 
// 
// 2  -  BOOT REGISTERS
// 
//      The BOOT registers are used to configure each of the devices in NV at
// reset.  These register are not normally changed after reset.  Only the BIOS
// should access these registers.
// 
//         Only one boot register is defined: Device_Enable. This register bit will
// reside in another block of the device. This register bit will control whether
// the FPCI (and interfaced device) is "seen" by the system.
// 
//      There currently are no boot registers (0x0000).
// 
// 
// 
// 
// 3  -  DELAY REGISTERS
// 
//      The DELAY registers allow the output signals to be shifted in time with
// respect to the clock.  Only the BIOS should access these registers.
// 
//      There currently are no delay registers (0x0040).
// 
// 
// 
// 
// 4  -  DEBUG REGISTERS
// 
//      The DEBUG registers are used to reconfigure NV during debug or chip
// testing.  These registers may contain function disable bits and hidden
// context.  Only the BIOS should access these registers.
// 
//      There currently are no debug registers (0x0080).
// 
// 
// 
// 
// 
// 
// 5  -  GREEN REGISTERS
// 
//      The GREEN registers control power down levels for each of the devices in
// NV.  Only the BIOS should access these registers.
// 
//      There currently are no green registers (0x00c0).
// 
// 
// 
// 
// 6  -  INTERRUPT REGISTERS
// 
//      The interrupt registers control the interrupts for the local devices.
// Interrupts are set by an event and are cleared by software.
// 
//      There currently are no interrupt registers (0x00c0).
// 
// 
// 
// 
// 7  -  CONTEXT SWITCHING REGISTERS
// 
//      The context switching registers control the context switching of the
// local user devices.
// 
//      There currently are no context switching registers (0x0180).
// 
// 
// 
// 
// 8  -  CONFIGURATION REGISTERS
// 
//      The CONFIG registers are used to configure each of the devices in NV
// after reset.
// 
//      There currently are no config registers (0x0180).
// 
// 
// 
// 
// 9  -  REAL MODE CONTROL REGISTERS
// 
//      There currently are no real mode registers (0x0180).
// 
// 
// 
// 
// 10  -  PCI CONFIGURATION REGISTERS
// 
// *****************************************************************************
// *****************************************************************************
// 
// The PCI Configuration registers are located in PCI Configuration Space.
// The method for accessing all of PCI Configuration space is via the 0xCF8
// and 0xCFC I/O index/data register pair.  The address of the PCI Configuration
// register is written to 0xCF8 (nvpci od cf8 80000810), and then the contents
// of the register can be read/written through 0xCFC (nvpci id cfc).
// 
// The PCI Configuration addressing scheme is based on the topology of
// the PCI Bus.  The fields of the PCI Configuration Address scheme are as
// follows:
// 
// 31 -- Enable PCI Configuration Mode (Always set this bit)
// 30:24 -- Reserved (Always set to 0)
// 23:16 -- Bus Number (Bus 0 for internal NVIDIA devices)
// 15:11 -- Device Number
// 10:8  -- Function Number
// 7:0   -- Register Offset (the value of the /* RX-4R */ fields below)
// 
// Device Number and function number vary from device to device.  In CK804
// the SATA blocks are Dev 7,8, Function 0.  So the Configuration Address
// of the T_SATA0_CFG_0 registers are 0x80003800 and 0x80004000.
// 
// nvpci od cf8 80003800  (SATA0)
// (nvpci od cf8 80004000) (SATA1)
// nvpci id cfc
// 
// nvpci also has a read command that is based on device/function number.
// The equivalent read of T_SATA0_CFG_0 is below.
// 
// nvpci rd 7 0  (SATA0)
// (nvpci rd 8 0) (SATA1)
// 
// CK804 has what is called a base unit ID.  This allows an offset to the
// Device Number to be programmed.  It is expected that this offset will
// be 0.
// 
// *****************************************************************************
// *****************************************************************************
// 
// .LABEL PCI_CONFIG
// *****************************************************************************
// *****************************************************************************
// .LABEL PUBLIC
// .SECTION config Serial ATA CONTROLLER CONFIGURATION REGISTERS
// .PCI_DEVICE    0xA
// .PCI_FUNCTION    0
// 
#define BASE_ADDRESS_SATA0                                 0x00000000                                                                       // 0x00000FFF:0x00000000 RW--D
// 
// .POWER VCORE
// //.RESET I reset_ "PCI Reset"
// 
//      The PCI definition provides for totally software driven initialization
// and configuration via a separate configuration address space.  PCI devices are
// required to provide 256 bytes of configuration register for this purpose.
//      FPCI defines one PCI unit:function and only decodes and acknowledges the
// first 256 bytes of the configuration address space.
// 
// .SUBSECTION PCI Configuration Registers
// .TITLE PCI Vendor and Device ID register 00h
// .FIELD VENDOR_ID
//      The VENDOR_ID bits identify the manufacturer of the device.  Valid vendor
// identifiers are allocated by the PCI SIG to ensure uniqueness.  VENDOR_ID is
// the joint SGS/NVIDIA PCI vendor ID.
// .FIELD DEVICE_ID_UNIT
//      The DEVICE_ID bits identify the particular device.  This identifier is
// allocated by the vendor.  DEVICE_ID_FUNC bits contain the function number from
// the Configuration Address bits 10-8.  DEVICE_ID_UNIT bits contain the Unit
// number within the chip.
// 
// .LABEL PRIVATE
// Mcp65 supports a backdoor register to update device id. 0x3F6 is the default and
// used for OEM configuration.However BIOS can change it to 0x3F6 for channel configuration
// if it wants by writing to T_SATA0_CFG_38_BKDOOR_DEVICE_ID.
// .LABEL PCI_CONFIG
// 
//         The Unit and Function are defined by parameters per block.
// 
// 
//  31           24 23           16 15            8 7             0
// .-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-.
// |0 0 0 0 1 1 0 1 1 1 1 0 0|0 0 1|0 0 0 1 0 0 0 0 1 1 0 1 1 1 1 0| CFG_0
// `-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-'
// 
#define SATA0_CFG_0_0                                      0x00000000                                                                       // R--4R
#define SATA0_CFG_0_0_SECURE                               0
#define SATA0_CFG_0_0_WORD_COUNT                           1
#define SATA0_CFG_0_0_RESET_VAL                            0x0
#define SATA0_CFG_0_0_RESET_MASK                           0x0
#define SATA0_CFG_0_0_SW_DEFAULT_VAL                       0x0
#define SATA0_CFG_0_0_SW_DEFAULT_MASK                      0x0
#define SATA0_CFG_0_0_READ_MASK                            0xffffffff
#define SATA0_CFG_0_0_WRITE_MASK                           0x0
#define SATA0_CFG_0_0_VENDOR_ID_SHIFT                       _MK_SHIFT_CONST(0)                                                              // C--UF
#define SATA0_CFG_0_0_VENDOR_ID_FIELD                      (_MK_SHIFT_CONST(0xffff) << SATA0_CFG_0_0_VENDOR_ID_SHIFT)
#define SATA0_CFG_0_0_VENDOR_ID_RANGE                      15:0
#define SATA0_CFG_0_0_VENDOR_ID_WOFFSET                    0
#define SATA0_CFG_0_0_VENDOR_ID_NVIDIA                     _MK_ENUM_CONST(0x000010DE)                                                       // C---V
#define SATA0_CFG_0_0_DEVICE_ID_UNIT_SHIFT                  _MK_SHIFT_CONST(16)                                                             // R-WUF
#define SATA0_CFG_0_0_DEVICE_ID_UNIT_FIELD                 (_MK_SHIFT_CONST(0xffff) << SATA0_CFG_0_0_DEVICE_ID_UNIT_SHIFT)
#define SATA0_CFG_0_0_DEVICE_ID_UNIT_RANGE                 31:16
#define SATA0_CFG_0_0_DEVICE_ID_UNIT_WOFFSET               0
#define SATA0_CFG_0_0_DEVICE_ID_UNIT_DEFAULT               (_MK_MASK_CONST(0x00001AD3)
#define SATA0_CFG_0_0_DEVICE_ID_UNIT_DEFAULT_MASK          (_MK_MASK_CONST(0xffff)
#define SATA0_CFG_0_0_DEVICE_ID_UNIT_SW_DEFAULT            (_MK_MASK_CONST(0x00001AD3)
#define SATA0_CFG_0_0_DEVICE_ID_UNIT_SW_DEFAULT_MASK       (_MK_MASK_CONST(0xffff)
#define SATA0_CFG_0_0_DEVICE_ID_UNIT_MCP50                 _MK_ENUM_CONST(0x000003F6)                                                       // R---V
#define SATA0_CFG_0_0_DEVICE_ID_UNIT_MCP61                 _MK_ENUM_CONST(0x000003F6)                                                       // R---V
#define SATA0_CFG_0_0_DEVICE_ID_UNIT_MCP61_NBP             _MK_ENUM_CONST(0x000003E7)                                                       // R---V
#define SATA0_CFG_0_0_DEVICE_ID_UNIT_MCP65                 _MK_ENUM_CONST(0x0000044C)                                                       // R---V
#define SATA0_CFG_0_0_DEVICE_ID_UNIT_MCP65_NBP             _MK_ENUM_CONST(0x0000044E)                                                       // R---V
#define SATA0_CFG_0_0_DEVICE_ID_UNIT_MCP67                 _MK_ENUM_CONST(0x00000550)                                                       // R---V
#define SATA0_CFG_0_0_DEVICE_ID_UNIT_MCP67_NBP             _MK_ENUM_CONST(0x00000550)                                                       // R---V
#define SATA0_CFG_0_0_DEVICE_ID_UNIT_MCP6B                 _MK_ENUM_CONST(0x00000680)                                                       // R---V
#define SATA0_CFG_0_0_DEVICE_ID_UNIT_MCP6B_NBP             _MK_ENUM_CONST(0x00000682)                                                       // R---V
#define SATA0_CFG_0_0_DEVICE_ID_UNIT_MCP72                 _MK_ENUM_CONST(0x000007B0)                                                       // R---V
#define SATA0_CFG_0_0_DEVICE_ID_UNIT_MCP72_NBP             _MK_ENUM_CONST(0x000007B4)                                                       // R---V
#define SATA0_CFG_0_0_DEVICE_ID_UNIT_MCP72_EMU             _MK_ENUM_CONST(0x000007B0)                                                       // R---V
#define SATA0_CFG_0_0_DEVICE_ID_UNIT_MCP72_EMU_NBP         _MK_ENUM_CONST(0x000007B4)                                                       // R---V
#define SATA0_CFG_0_0_DEVICE_ID_UNIT_MCP77                 _MK_ENUM_CONST(0x00000AD0)                                                       // R---V
#define SATA0_CFG_0_0_DEVICE_ID_UNIT_MCP77_NBP             _MK_ENUM_CONST(0x00000AD0)                                                       // R---V
#define SATA0_CFG_0_0_DEVICE_ID_UNIT_MCP77_PATA            _MK_ENUM_CONST(0x00000AD1)                                                       // R---V
#define SATA0_CFG_0_0_DEVICE_ID_UNIT_MCP77_AHCI            _MK_ENUM_CONST(0x00000AD5)                                                       // R---V
#define SATA0_CFG_0_0_DEVICE_ID_UNIT_MCP77_RAID            _MK_ENUM_CONST(0x00000AD9)                                                       // R---V
#define SATA0_CFG_0_0_DEVICE_ID_UNIT_MCP78_PATA            _MK_ENUM_CONST(0x00000AD0)                                                       // R---V
#define SATA0_CFG_0_0_DEVICE_ID_UNIT_MCP78_AHCI            _MK_ENUM_CONST(0x00000AD4)                                                       // R---V
#define SATA0_CFG_0_0_DEVICE_ID_UNIT_MCP78_RAID            _MK_ENUM_CONST(0x00000AD8)                                                       // R---V
#define SATA0_CFG_0_0_DEVICE_ID_UNIT_MCP77_EMU             _MK_ENUM_CONST(0x00000AD0)                                                       // R---V
#define SATA0_CFG_0_0_DEVICE_ID_UNIT_MCP77_EMU_NBP         _MK_ENUM_CONST(0x00000AD0)                                                       // R---V
#define SATA0_CFG_0_0_DEVICE_ID_UNIT_T65                   _MK_ENUM_CONST(0x0000047C)                                                       // R---V
#define SATA0_CFG_0_0_DEVICE_ID_UNIT_MCP87                 _MK_ENUM_CONST(0x00000B64)                                                       // R---V
#define SATA0_CFG_0_0_DEVICE_ID_UNIT_MCP87_NBP             _MK_ENUM_CONST(0x00000B65)                                                       // R---V
#define SATA0_CFG_0_0_DEVICE_ID_UNIT_MCP87_EMU             _MK_ENUM_CONST(0x00000B64)                                                       // R---V
#define SATA0_CFG_0_0_DEVICE_ID_UNIT_MCP87_EMU_NBP         _MK_ENUM_CONST(0x00000B65)                                                       // R---V
#define SATA0_CFG_0_0_DEVICE_ID_UNIT_MCP87_PATA            _MK_ENUM_CONST(0x00000B64)                                                       // R---V
#define SATA0_CFG_0_0_DEVICE_ID_UNIT_MCP87_AHCI            _MK_ENUM_CONST(0x00000B68)                                                       // R---V
#define SATA0_CFG_0_0_DEVICE_ID_UNIT_MCP87_RAID            _MK_ENUM_CONST(0x00000B6C)                                                       // R---V
#define SATA0_CFG_0_0_DEVICE_ID_UNIT_1_MCP87_PATA          _MK_ENUM_CONST(0x00000B60)                                                       // R---V
#define SATA0_CFG_0_0_DEVICE_ID_UNIT_1_MCP87_NBP           _MK_ENUM_CONST(0x00000B61)                                                       // R---V
#define SATA0_CFG_0_0_DEVICE_ID_UNIT_1_MCP87_EMU_PATA      _MK_ENUM_CONST(0x00000B60)                                                       // R---V
#define SATA0_CFG_0_0_DEVICE_ID_UNIT_1_MCP87_EMU_NBP       _MK_ENUM_CONST(0x00000B61)                                                       // R---V
#define SATA0_CFG_0_0_DEVICE_ID_UNIT_MCP88                 _MK_ENUM_CONST(0x00000B64)                                                       // R---V
#define SATA0_CFG_0_0_DEVICE_ID_UNIT_MCP88_NBP             _MK_ENUM_CONST(0x00000B65)                                                       // R---V
#define SATA0_CFG_0_0_DEVICE_ID_UNIT_MCP88_EMU             _MK_ENUM_CONST(0x00000B64)                                                       // R---V
#define SATA0_CFG_0_0_DEVICE_ID_UNIT_MCP88_EMU_NBP         _MK_ENUM_CONST(0x00000B65)                                                       // R---V
#define SATA0_CFG_0_0_DEVICE_ID_UNIT_MCP88_PATA            _MK_ENUM_CONST(0x00000B64)                                                       // R---V
#define SATA0_CFG_0_0_DEVICE_ID_UNIT_MCP88_AHCI            _MK_ENUM_CONST(0x00000B68)                                                       // R---V
#define SATA0_CFG_0_0_DEVICE_ID_UNIT_MCP88_RAID            _MK_ENUM_CONST(0x00000B6C)                                                       // R---V
#define SATA0_CFG_0_0_DEVICE_ID_UNIT_1_MCP88_PATA          _MK_ENUM_CONST(0x00000B60)                                                       // R---V
#define SATA0_CFG_0_0_DEVICE_ID_UNIT_1_MCP88_NBP           _MK_ENUM_CONST(0x00000B61)                                                       // R---V
#define SATA0_CFG_0_0_DEVICE_ID_UNIT_1_MCP88_EMU_PATA      _MK_ENUM_CONST(0x00000B60)                                                       // R---V
#define SATA0_CFG_0_0_DEVICE_ID_UNIT_1_MCP88_EMU_NBP       _MK_ENUM_CONST(0x00000B61)                                                       // R---V
#define SATA0_CFG_0_0_DEVICE_ID_UNIT_MCP89                 _MK_ENUM_CONST(0x00000D84)                                                       // R---V
#define SATA0_CFG_0_0_DEVICE_ID_UNIT_MCP89_EMU             _MK_ENUM_CONST(0x00000D84)                                                       // R---V
#define SATA0_CFG_0_0_DEVICE_ID_UNIT_MCP89_PATA_DT         _MK_ENUM_CONST(0x00000D84)                                                       // R---V
#define SATA0_CFG_0_0_DEVICE_ID_UNIT_MCP89_PATA_NB         _MK_ENUM_CONST(0x00000D85)                                                       // R---V
#define SATA0_CFG_0_0_DEVICE_ID_UNIT_MCP89_AHCI_DT         _MK_ENUM_CONST(0x00000D88)                                                       // R---V
#define SATA0_CFG_0_0_DEVICE_ID_UNIT_MCP89_AHCI_NB         _MK_ENUM_CONST(0x00000D89)                                                       // R---V
#define SATA0_CFG_0_0_DEVICE_ID_UNIT_MCP89_AHCI_LINUX      _MK_ENUM_CONST(0x00000580)                                                       // R---V
#define SATA0_CFG_0_0_DEVICE_ID_UNIT_MCP89_RAID_DT         _MK_ENUM_CONST(0x00000D8C)                                                       // R---V
#define SATA0_CFG_0_0_DEVICE_ID_UNIT_MCP89_RAID_NB         _MK_ENUM_CONST(0x00000D8D)                                                       // R---V
#define SATA0_CFG_0_0_DEVICE_ID_UNIT_MCP89_EMU_PATA_DT     _MK_ENUM_CONST(0x00000D84)                                                       // R---V
#define SATA0_CFG_0_0_DEVICE_ID_UNIT_MCP89_EMU_PATA_NB     _MK_ENUM_CONST(0x00000D85)                                                       // R---V
#define SATA0_CFG_0_0_DEVICE_ID_UNIT_MCP89_EMU_AHCI_DT     _MK_ENUM_CONST(0x00000D88)                                                       // R---V
#define SATA0_CFG_0_0_DEVICE_ID_UNIT_MCP89_EMU_AHCI_NB     _MK_ENUM_CONST(0x00000D89)                                                       // R---V
#define SATA0_CFG_0_0_DEVICE_ID_UNIT_MCP89_EMU_RAID_DT     _MK_ENUM_CONST(0x00000D8C)                                                       // R---V
#define SATA0_CFG_0_0_DEVICE_ID_UNIT_MCP89_EMU_RAID_NB     _MK_ENUM_CONST(0x00000D8D)                                                       // R---V
#define SATA0_CFG_0_0_DEVICE_ID_UNIT_MCP8D                 _MK_ENUM_CONST(0x00000D84)                                                       // R---V
#define SATA0_CFG_0_0_DEVICE_ID_UNIT_T30                   _MK_ENUM_CONST(0x00000E1E)                                                       // R---V
#define SATA0_CFG_0_0_DEVICE_ID_UNIT_T30_EMU               _MK_ENUM_CONST(0x00000E1E)                                                       // R---V
#define SATA0_CFG_0_0_DEVICE_ID_UNIT_T30_PATA_DT           _MK_ENUM_CONST(0x00000E1E)                                                       // R---V
#define SATA0_CFG_0_0_DEVICE_ID_UNIT_T30_PATA_NB           _MK_ENUM_CONST(0x00000E1F)                                                       // R---V
#define SATA0_CFG_0_0_DEVICE_ID_UNIT_T30_AHCI_DT           _MK_ENUM_CONST(0x00000E22)                                                       // R---V
#define SATA0_CFG_0_0_DEVICE_ID_UNIT_T30_AHCI_NB           _MK_ENUM_CONST(0x00000E23)                                                       // R---V
#define SATA0_CFG_0_0_DEVICE_ID_UNIT_T30_RAID_DT           _MK_ENUM_CONST(0x00000E26)                                                       // R---V
#define SATA0_CFG_0_0_DEVICE_ID_UNIT_T30_RAID_NB           _MK_ENUM_CONST(0x00000E27)                                                       // R---V
#define SATA0_CFG_0_0_DEVICE_ID_UNIT_T30_EMU_PATA_DT       _MK_ENUM_CONST(0x00000E1E)                                                       // R---V
#define SATA0_CFG_0_0_DEVICE_ID_UNIT_T30_EMU_PATA_NB       _MK_ENUM_CONST(0x00000E1F)                                                       // R---V
#define SATA0_CFG_0_0_DEVICE_ID_UNIT_T30_EMU_AHCI_DT       _MK_ENUM_CONST(0x00000E22)                                                       // R---V
#define SATA0_CFG_0_0_DEVICE_ID_UNIT_T30_EMU_AHCI_NB       _MK_ENUM_CONST(0x00000E23)                                                       // R---V
#define SATA0_CFG_0_0_DEVICE_ID_UNIT_T30_EMU_RAID_DT       _MK_ENUM_CONST(0x00000E26)                                                       // R---V
#define SATA0_CFG_0_0_DEVICE_ID_UNIT_T30_EMU_RAID_NB       _MK_ENUM_CONST(0x00000E27)                                                       // R---V
#define SATA0_CFG_0_0_DEVICE_ID_UNIT_T32                   _MK_ENUM_CONST(0x00000E1E)                                                       // R---V
#define SATA0_CFG_0_0_DEVICE_ID_UNIT_T32_EMU               _MK_ENUM_CONST(0x00000E1E)                                                       // R---V
#define SATA0_CFG_0_0_DEVICE_ID_UNIT_T32_PATA_DT           _MK_ENUM_CONST(0x00000E1E)                                                       // R---V
#define SATA0_CFG_0_0_DEVICE_ID_UNIT_T32_PATA_NB           _MK_ENUM_CONST(0x00000E1F)                                                       // R---V
#define SATA0_CFG_0_0_DEVICE_ID_UNIT_T32_AHCI_DT           _MK_ENUM_CONST(0x00000E22)                                                       // R---V
#define SATA0_CFG_0_0_DEVICE_ID_UNIT_T32_AHCI_NB           _MK_ENUM_CONST(0x00000E23)                                                       // R---V
#define SATA0_CFG_0_0_DEVICE_ID_UNIT_T32_RAID_DT           _MK_ENUM_CONST(0x00000E26)                                                       // R---V
#define SATA0_CFG_0_0_DEVICE_ID_UNIT_T32_RAID_NB           _MK_ENUM_CONST(0x00000E27)                                                       // R---V
#define SATA0_CFG_0_0_DEVICE_ID_UNIT_T32_EMU_PATA_DT       _MK_ENUM_CONST(0x00000E1E)                                                       // R---V
#define SATA0_CFG_0_0_DEVICE_ID_UNIT_T32_EMU_PATA_NB       _MK_ENUM_CONST(0x00000E1F)                                                       // R---V
#define SATA0_CFG_0_0_DEVICE_ID_UNIT_T32_EMU_AHCI_DT       _MK_ENUM_CONST(0x00000E22)                                                       // R---V
#define SATA0_CFG_0_0_DEVICE_ID_UNIT_T32_EMU_AHCI_NB       _MK_ENUM_CONST(0x00000E23)                                                       // R---V
#define SATA0_CFG_0_0_DEVICE_ID_UNIT_T32_EMU_RAID_DT       _MK_ENUM_CONST(0x00000E26)                                                       // R---V
#define SATA0_CFG_0_0_DEVICE_ID_UNIT_T32_EMU_RAID_NB       _MK_ENUM_CONST(0x00000E27)                                                       // R---V
#define SATA0_CFG_0_0_DEVICE_ID_UNIT_T35                   _MK_ENUM_CONST(0x00000E1E)                                                       // R---V
#define SATA0_CFG_0_0_DEVICE_ID_UNIT_T35_EMU               _MK_ENUM_CONST(0x00000E1E)                                                       // R---V
#define SATA0_CFG_0_0_DEVICE_ID_UNIT_T35_PATA_DT           _MK_ENUM_CONST(0x00000E1E)                                                       // R---V
#define SATA0_CFG_0_0_DEVICE_ID_UNIT_T35_PATA_NB           _MK_ENUM_CONST(0x00000E1F)                                                       // R---V
#define SATA0_CFG_0_0_DEVICE_ID_UNIT_T35_AHCI_DT           _MK_ENUM_CONST(0x00000E22)                                                       // R---V
#define SATA0_CFG_0_0_DEVICE_ID_UNIT_T35_AHCI_NB           _MK_ENUM_CONST(0x00000E23)                                                       // R---V
#define SATA0_CFG_0_0_DEVICE_ID_UNIT_T35_RAID_DT           _MK_ENUM_CONST(0x00000E26)                                                       // R---V
#define SATA0_CFG_0_0_DEVICE_ID_UNIT_T35_RAID_NB           _MK_ENUM_CONST(0x00000E27)                                                       // R---V
#define SATA0_CFG_0_0_DEVICE_ID_UNIT_T35_EMU_PATA_DT       _MK_ENUM_CONST(0x00000E1E)                                                       // R---V
#define SATA0_CFG_0_0_DEVICE_ID_UNIT_T35_EMU_PATA_NB       _MK_ENUM_CONST(0x00000E1F)                                                       // R---V
#define SATA0_CFG_0_0_DEVICE_ID_UNIT_T35_EMU_AHCI_DT       _MK_ENUM_CONST(0x00000E22)                                                       // R---V
#define SATA0_CFG_0_0_DEVICE_ID_UNIT_T35_EMU_AHCI_NB       _MK_ENUM_CONST(0x00000E23)                                                       // R---V
#define SATA0_CFG_0_0_DEVICE_ID_UNIT_T35_EMU_RAID_DT       _MK_ENUM_CONST(0x00000E26)                                                       // R---V
#define SATA0_CFG_0_0_DEVICE_ID_UNIT_T35_EMU_RAID_NB       _MK_ENUM_CONST(0x00000E27)                                                       // R---V
#define SATA0_CFG_0_0_DEVICE_ID_UNIT_T40                   _MK_ENUM_CONST(0x00000E1E)                                                       // R---V
#define SATA0_CFG_0_0_DEVICE_ID_UNIT_T40_EMU               _MK_ENUM_CONST(0x00000E1E)                                                       // R---V
#define SATA0_CFG_0_0_DEVICE_ID_UNIT_T40_PATA_DT           _MK_ENUM_CONST(0x00000E1E)                                                       // R---V
#define SATA0_CFG_0_0_DEVICE_ID_UNIT_T40_PATA_NB           _MK_ENUM_CONST(0x00000E1F)                                                       // R---V
#define SATA0_CFG_0_0_DEVICE_ID_UNIT_T40_AHCI_DT           _MK_ENUM_CONST(0x00000E22)                                                       // R---V
#define SATA0_CFG_0_0_DEVICE_ID_UNIT_T40_AHCI_NB           _MK_ENUM_CONST(0x00000E23)                                                       // R---V
#define SATA0_CFG_0_0_DEVICE_ID_UNIT_T40_RAID_DT           _MK_ENUM_CONST(0x00000E26)                                                       // R---V
#define SATA0_CFG_0_0_DEVICE_ID_UNIT_T40_RAID_NB           _MK_ENUM_CONST(0x00000E27)                                                       // R---V
#define SATA0_CFG_0_0_DEVICE_ID_UNIT_T40_EMU_PATA_DT       _MK_ENUM_CONST(0x00000E1E)                                                       // R---V
#define SATA0_CFG_0_0_DEVICE_ID_UNIT_T40_EMU_PATA_NB       _MK_ENUM_CONST(0x00000E1F)                                                       // R---V
#define SATA0_CFG_0_0_DEVICE_ID_UNIT_T40_EMU_AHCI_DT       _MK_ENUM_CONST(0x00000E22)                                                       // R---V
#define SATA0_CFG_0_0_DEVICE_ID_UNIT_T40_EMU_AHCI_NB       _MK_ENUM_CONST(0x00000E23)                                                       // R---V
#define SATA0_CFG_0_0_DEVICE_ID_UNIT_T40_EMU_RAID_DT       _MK_ENUM_CONST(0x00000E26)                                                       // R---V
#define SATA0_CFG_0_0_DEVICE_ID_UNIT_T40_EMU_RAID_NB       _MK_ENUM_CONST(0x00000E27)                                                       // R---V
#define SATA0_CFG_0_0_DEVICE_ID_UNIT_TLIT                  _MK_ENUM_CONST(0x00001AD3)                                                       // R-W-V
#define SATA0_CFG_0_0_DEVICE_ID_UNIT_TLIT_EMU              _MK_ENUM_CONST(0x00001AD3)                                                       // R---V
#define SATA0_CFG_0_0_DEVICE_ID_UNIT_TLIT_PATA_DT          _MK_ENUM_CONST(0x00001AD3)                                                       // R---V
#define SATA0_CFG_0_0_DEVICE_ID_UNIT_TLIT_PATA_NB          _MK_ENUM_CONST(0x00000E1F)                                                       // R---V
#define SATA0_CFG_0_0_DEVICE_ID_UNIT_TLIT_AHCI_DT          _MK_ENUM_CONST(0x00000E22)                                                       // R---V
#define SATA0_CFG_0_0_DEVICE_ID_UNIT_TLIT_AHCI_NB          _MK_ENUM_CONST(0x00000E23)                                                       // R---V
#define SATA0_CFG_0_0_DEVICE_ID_UNIT_TLIT_RAID_DT          _MK_ENUM_CONST(0x00000E26)                                                       // R---V
#define SATA0_CFG_0_0_DEVICE_ID_UNIT_TLIT_RAID_NB          _MK_ENUM_CONST(0x00000E27)                                                       // R---V
#define SATA0_CFG_0_0_DEVICE_ID_UNIT_TLIT_EMU_PATA_DT      _MK_ENUM_CONST(0x00000E1E)                                                       // R---V
#define SATA0_CFG_0_0_DEVICE_ID_UNIT_TLIT_EMU_PATA_NB      _MK_ENUM_CONST(0x00000E1F)                                                       // R---V
#define SATA0_CFG_0_0_DEVICE_ID_UNIT_TLIT_EMU_AHCI_DT      _MK_ENUM_CONST(0x00000E22)                                                       // R---V
#define SATA0_CFG_0_0_DEVICE_ID_UNIT_TLIT_EMU_AHCI_NB      _MK_ENUM_CONST(0x00000E23)                                                       // R---V
#define SATA0_CFG_0_0_DEVICE_ID_UNIT_TLIT_EMU_RAID_DT      _MK_ENUM_CONST(0x00000E26)                                                       // R---V
#define SATA0_CFG_0_0_DEVICE_ID_UNIT_TLIT_EMU_RAID_NB      _MK_ENUM_CONST(0x00000E27)                                                       // R---V
#define SATA0_CFG_0_0_DEVICE_ID_UNIT_T65_NBP               _MK_ENUM_CONST(0x0000047E)                                                       // R---V
// 
// 
// 
// .LABEL PRIVATE
// .LABEL PUBLIC
// .LABEL EMULATION
// .LABEL PUBLIC
// .LABEL EMULATION
// 
// 
// 
// 
// 
// 
// 
// 
// 
// .LABEL ERROR: Please choose appropriate device id values and move the R-W-V below to define the init value.
// 
// 
// .LABEL PUBLIC
// .define T_SATA0_CFG_0_DEVICE_ID_UNIT_SATA                0x00000F70 /* R-W-V */
// 
// 
//                 Figure 10-1  FPCI Configuration Register 00h
// 
// 
// 
// .TITLE PCI Device Control Register 04h
//      The Device Control Command register provides coarse control over a
// device's ability to generate and respond to PCI cycles.
// .FIELD IO_SPACE
//      The IO_SPACE bit indicates that the device will respond to I/O space
// accesses.  A value of 0 disables the device response.  A value of 1 allows the
// device to respond to I/O space accesses.  IO_SPACE is writable.
// .FIELD MEMORY_SPACE
//      The MEMORY_SPACE bit indicates that the device will respond to memory
// space accesses.  A value of 0 disables the device response.  A value of 1
// allows the device to respond to Memory space accesses.  MEMORY_SPACE is
// writable.
// .FIELD BUS_MASTER
//      The BUS_MASTER bit indicates that the device can act as a master on the
// PCI bus.  A value of 0 disables the device from generating PCI accesses.  A
// value of 1 allows the device to behave as a bus master.  BUS_MASTER is
// writable.
// .FIELD WRITE_AND_INVAL
//      The WRITE_AND_INVAL bit indicates that the device can use the Memory
// Write and Invalidate command when the transfer is aligned and 16 bytes and the
// contents of the Cache Line Size Register is 4 DWORDS.  When this bit is 1,
// masters may generate the command.  When it is 0, Memory Write must be used
// instead.  State after RST# is 0.  This bit must be implemented by master
// devices that can generate the Memory Write and Invalidate command.
// .FIELD PALETTE_SNOOP
//      The PALETTE_SNOOP bit indicates that VGA compatible devices should snoop
// their palette registers.  When this bit is set, special palette snooping
// behavior is enabled (ie, device must not respond).  When the bit is reset, the
// device should treat palette accesses like all other accesses.  VGA compatible
// devices should implement this bit.  PALETTE_SNOOP is writable.
// .FIELD INTR_DISABLE
//      The INTR_DISABLE bit indicates that it could disable the device/function
// from asserting INTx#. A value of 0 enables the assertion of INTx#, and a value
// of 1 disables the assertion of INTx# signal.
// 
//      The Device Status register is used to record status information for PCI
// bus related events.
// .FIELD INTR_STATUS
//      The INTR_STATUS bit is read-only and reflects the state of the interrupt
// in the device/function. Only when the INTR_DISABLE bit in the command register
// is a 0 and this INTR_STATUS bit is a 1, will the device's/function's INTx#
// singal be asserted. Setting the INTR_DISABLE bit to 1 has no effect on the
// state of this bit.
// .FIELD CAPLIST
//      The CAPLIST bit indicates that the device configuration space includes a
// capabilities list starting at the offset indicated by T_SATA0_CFG_13.
// .FIELD 66MHZ
//      The 66MHZ bit indicates that the device is capable of 66 MHz PCI Bus
// operation.  This value is initialized by a strapping bit.
// .FIELD FAST_BACK2BACK
//      The FAST_BACK2BACK bit indicates that the device is capable of handling
// back-to-back transfers when the transactions are not to the same agent.  This
// bit can be set to 1 if the device can accept these transactions, and must be
// set to 0 otherwise.
// .FIELD DEVSEL_TIMING
//      The DEVSEL_TIMING bits contain the timing of DEVSEL#.  There are three
// allowable timings for assertion of DEVSEL#.  These are encoded as 00b for
// fast, 01b for medium, and 10b for slow (11b is reserved).  These bits are read
// only and must indicate the slowest time that a device asserts DEVSEL# for any
// bus command except Configuration Read and Configuration Write.  Positive
// decode devices are required to respond with fast DEVSEL# (0-cycle). Only the
// subtractive function will respond with medium DEVSEL# to accept the
// cycle for the subtractive bus.
// .FIELD SIGNALED_TARGET
//      The SIGNALED_TARGET bit indicates that the device has terminated a
// transaction with target-abort.  Devices that will never signal target-abort
// do not need to implement this bit.  When this bit is set, an interrupt is
// signaled in the PBUS_INTR_0 register.
// .FIELD RECEIVED_TARGET
//      The RECEIVED_TARGET bit indicates that a master device's transaction was
// terminated with a target-abort.  All master devices must implement this bit.
// When this bit is set, an interrupt is signaled in the PBUS_INTR_0 register.
// .FIELD RECEIVED_MASTER
//      The RECEIVED_MASTER bit indicates that a master device's transaction
// (except for Special Cycle) was terminated with a master-abort.  This means
// that no device on the PCI bus responded to the address of the mastered
// transaction.  All master devices must implement this bit.  When this bit is
// set, an interrupt is signaled in the PBUS_INTR_0 register.
// .LABEL PRIVATE
// /*         Regarding the SIGNALED_TARGET, RECEIVED_TARGET, and RECEIVED_MASTER bits,
// unfortunately, there is no way of knowing what the offending address of the bus
// error was, except by using a logic analyzer. */
// .LABEL PCI_CONFIG
// .FIELD SIGNALED_SERR
//      The SIGNALED_SERR bit indicates that the device has asserted SERR#.
// .FIELD DETECTED_PERR
//      The DETECTED_PERR bit indicates that the device has detected a parity
// error, even if parity error handing is disabled. (Bit 6 -
// T_SATA0_FPCI_PERR_DISABLED)
// 
//  31           24 23           16 15            8 7             0
// .-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-.
// |0 0| | | |0 1|0|1|0|0| |0 0 0 0 0 0 0 0 0 0 0 0 0 0| |0| | | | | CFG_1
// `-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-'
// 
#define SATA0_CFG_1_0                                      0x00000004                                                                       // RW-4R
#define SATA0_CFG_1_0_SECURE                               0
#define SATA0_CFG_1_0_WORD_COUNT                           1
#define SATA0_CFG_1_0_RESET_VAL                            0x0
#define SATA0_CFG_1_0_RESET_MASK                           0x0
#define SATA0_CFG_1_0_SW_DEFAULT_VAL                       0x0
#define SATA0_CFG_1_0_SW_DEFAULT_MASK                      0x0
#define SATA0_CFG_1_0_READ_MASK                            0xffb807ff
#define SATA0_CFG_1_0_WRITE_MASK                           0x70000507
#define SATA0_CFG_1_0_IO_SPACE_SHIFT                        _MK_SHIFT_CONST(0)                                                              // RWWVF
#define SATA0_CFG_1_0_IO_SPACE_FIELD                       (_MK_SHIFT_CONST(0x1) << SATA0_CFG_1_0_IO_SPACE_SHIFT)
#define SATA0_CFG_1_0_IO_SPACE_RANGE                       0:0
#define SATA0_CFG_1_0_IO_SPACE_WOFFSET                     0
#define SATA0_CFG_1_0_IO_SPACE_DEFAULT                     (_MK_MASK_CONST(0x00000000)
#define SATA0_CFG_1_0_IO_SPACE_DEFAULT_MASK                (_MK_MASK_CONST(0x1)
#define SATA0_CFG_1_0_IO_SPACE_SW_DEFAULT                  (_MK_MASK_CONST(0x00000000)
#define SATA0_CFG_1_0_IO_SPACE_SW_DEFAULT_MASK             (_MK_MASK_CONST(0x1)
#define SATA0_CFG_1_0_IO_SPACE__WRNPRDCHK                  _MK_ENUM_CONST(0x00000001)                                                       // ----V
#define SATA0_CFG_1_0_IO_SPACE_DISABLED                    _MK_ENUM_CONST(0x00000000)                                                       // RWW-V
#define SATA0_CFG_1_0_IO_SPACE_ENABLED                     _MK_ENUM_CONST(0x00000001)                                                       // RW--V
#define SATA0_CFG_1_0_MEMORY_SPACE_SHIFT                    _MK_SHIFT_CONST(1)                                                              // RWWVF
#define SATA0_CFG_1_0_MEMORY_SPACE_FIELD                   (_MK_SHIFT_CONST(0x1) << SATA0_CFG_1_0_MEMORY_SPACE_SHIFT)
#define SATA0_CFG_1_0_MEMORY_SPACE_RANGE                   1:1
#define SATA0_CFG_1_0_MEMORY_SPACE_WOFFSET                 0
#define SATA0_CFG_1_0_MEMORY_SPACE_DEFAULT                 (_MK_MASK_CONST(0x00000000)
#define SATA0_CFG_1_0_MEMORY_SPACE_DEFAULT_MASK            (_MK_MASK_CONST(0x1)
#define SATA0_CFG_1_0_MEMORY_SPACE_SW_DEFAULT              (_MK_MASK_CONST(0x00000000)
#define SATA0_CFG_1_0_MEMORY_SPACE_SW_DEFAULT_MASK         (_MK_MASK_CONST(0x1)
#define SATA0_CFG_1_0_MEMORY_SPACE__WRNPRDCHK              _MK_ENUM_CONST(0x00000001)                                                       // ----V
#define SATA0_CFG_1_0_MEMORY_SPACE_DISABLED                _MK_ENUM_CONST(0x00000000)                                                       // RWW-V
#define SATA0_CFG_1_0_MEMORY_SPACE_ENABLED                 _MK_ENUM_CONST(0x00000001)                                                       // RW--V
#define SATA0_CFG_1_0_BUS_MASTER_SHIFT                      _MK_SHIFT_CONST(2)                                                              // RWWVF
#define SATA0_CFG_1_0_BUS_MASTER_FIELD                     (_MK_SHIFT_CONST(0x1) << SATA0_CFG_1_0_BUS_MASTER_SHIFT)
#define SATA0_CFG_1_0_BUS_MASTER_RANGE                     2:2
#define SATA0_CFG_1_0_BUS_MASTER_WOFFSET                   0
#define SATA0_CFG_1_0_BUS_MASTER_DEFAULT                   (_MK_MASK_CONST(0x00000000)
#define SATA0_CFG_1_0_BUS_MASTER_DEFAULT_MASK              (_MK_MASK_CONST(0x1)
#define SATA0_CFG_1_0_BUS_MASTER_SW_DEFAULT                (_MK_MASK_CONST(0x00000000)
#define SATA0_CFG_1_0_BUS_MASTER_SW_DEFAULT_MASK           (_MK_MASK_CONST(0x1)
#define SATA0_CFG_1_0_BUS_MASTER__WRNPRDCHK                _MK_ENUM_CONST(0x00000001)                                                       // ----V
#define SATA0_CFG_1_0_BUS_MASTER_DISABLED                  _MK_ENUM_CONST(0x00000000)                                                       // RWW-V
#define SATA0_CFG_1_0_BUS_MASTER_ENABLED                   _MK_ENUM_CONST(0x00000001)                                                       // RW--V
#define SATA0_CFG_1_0_SPECIAL_CYCLE_SHIFT                   _MK_SHIFT_CONST(3)                                                              // C--VF
#define SATA0_CFG_1_0_SPECIAL_CYCLE_FIELD                  (_MK_SHIFT_CONST(0x1) << SATA0_CFG_1_0_SPECIAL_CYCLE_SHIFT)
#define SATA0_CFG_1_0_SPECIAL_CYCLE_RANGE                  3:3
#define SATA0_CFG_1_0_SPECIAL_CYCLE_WOFFSET                0
#define SATA0_CFG_1_0_SPECIAL_CYCLE_DISABLED               _MK_ENUM_CONST(0x00000000)                                                       // C---V
#define SATA0_CFG_1_0_SPECIAL_CYCLE_ENABLED                _MK_ENUM_CONST(0x00000001)                                                       // ----V
#define SATA0_CFG_1_0_WRITE_AND_INVAL_SHIFT                 _MK_SHIFT_CONST(4)                                                              // C--VF
#define SATA0_CFG_1_0_WRITE_AND_INVAL_FIELD                (_MK_SHIFT_CONST(0x1) << SATA0_CFG_1_0_WRITE_AND_INVAL_SHIFT)
#define SATA0_CFG_1_0_WRITE_AND_INVAL_RANGE                4:4
#define SATA0_CFG_1_0_WRITE_AND_INVAL_WOFFSET              0
#define SATA0_CFG_1_0_WRITE_AND_INVAL_DISABLED             _MK_ENUM_CONST(0x00000000)                                                       // C---V
#define SATA0_CFG_1_0_WRITE_AND_INVAL_ENABLED              _MK_ENUM_CONST(0x00000001)                                                       // ----V
#define SATA0_CFG_1_0_PALETTE_SNOOP_SHIFT                   _MK_SHIFT_CONST(5)                                                              // C--VF
#define SATA0_CFG_1_0_PALETTE_SNOOP_FIELD                  (_MK_SHIFT_CONST(0x1) << SATA0_CFG_1_0_PALETTE_SNOOP_SHIFT)
#define SATA0_CFG_1_0_PALETTE_SNOOP_RANGE                  5:5
#define SATA0_CFG_1_0_PALETTE_SNOOP_WOFFSET                0
#define SATA0_CFG_1_0_PALETTE_SNOOP_DISABLED               _MK_ENUM_CONST(0x00000000)                                                       // C---V
#define SATA0_CFG_1_0_PALETTE_SNOOP_ENABLED                _MK_ENUM_CONST(0x00000001)                                                       // ----V
#define SATA0_CFG_1_0_PERR_SHIFT                            _MK_SHIFT_CONST(6)                                                              // C--VF
#define SATA0_CFG_1_0_PERR_FIELD                           (_MK_SHIFT_CONST(0x1) << SATA0_CFG_1_0_PERR_SHIFT)
#define SATA0_CFG_1_0_PERR_RANGE                           6:6
#define SATA0_CFG_1_0_PERR_WOFFSET                         0
#define SATA0_CFG_1_0_PERR_DISABLED                        _MK_ENUM_CONST(0x00000000)                                                       // C---V
#define SATA0_CFG_1_0_PERR_ENABLED                         _MK_ENUM_CONST(0x00000001)                                                       // ----V
#define SATA0_CFG_1_0_STEP_SHIFT                            _MK_SHIFT_CONST(7)                                                              // C--VF
#define SATA0_CFG_1_0_STEP_FIELD                           (_MK_SHIFT_CONST(0x1) << SATA0_CFG_1_0_STEP_SHIFT)
#define SATA0_CFG_1_0_STEP_RANGE                           7:7
#define SATA0_CFG_1_0_STEP_WOFFSET                         0
#define SATA0_CFG_1_0_STEP_DISABLED                        _MK_ENUM_CONST(0x00000000)                                                       // C---V
#define SATA0_CFG_1_0_STEP_ENABLED                         _MK_ENUM_CONST(0x00000001)                                                       // ----V
#define SATA0_CFG_1_0_SERR_SHIFT                            _MK_SHIFT_CONST(8)                                                              // RWWVF
#define SATA0_CFG_1_0_SERR_FIELD                           (_MK_SHIFT_CONST(0x1) << SATA0_CFG_1_0_SERR_SHIFT)
#define SATA0_CFG_1_0_SERR_RANGE                           8:8
#define SATA0_CFG_1_0_SERR_WOFFSET                         0
#define SATA0_CFG_1_0_SERR_DEFAULT                         (_MK_MASK_CONST(0x00000000)
#define SATA0_CFG_1_0_SERR_DEFAULT_MASK                    (_MK_MASK_CONST(0x1)
#define SATA0_CFG_1_0_SERR_SW_DEFAULT                      (_MK_MASK_CONST(0x00000000)
#define SATA0_CFG_1_0_SERR_SW_DEFAULT_MASK                 (_MK_MASK_CONST(0x1)
#define SATA0_CFG_1_0_SERR__WRNPRDCHK                      _MK_ENUM_CONST(0x00000001)                                                       // ----V
#define SATA0_CFG_1_0_SERR_DISABLED                        _MK_ENUM_CONST(0x00000000)                                                       // RWW-V
#define SATA0_CFG_1_0_SERR_ENABLED                         _MK_ENUM_CONST(0x00000001)                                                       // RW--V
#define SATA0_CFG_1_0_BACK2BACK_SHIFT                       _MK_SHIFT_CONST(9)                                                              // C--VF
#define SATA0_CFG_1_0_BACK2BACK_FIELD                      (_MK_SHIFT_CONST(0x1) << SATA0_CFG_1_0_BACK2BACK_SHIFT)
#define SATA0_CFG_1_0_BACK2BACK_RANGE                      9:9
#define SATA0_CFG_1_0_BACK2BACK_WOFFSET                    0
#define SATA0_CFG_1_0_BACK2BACK_DISABLED                   _MK_ENUM_CONST(0x00000000)                                                       // C---V
#define SATA0_CFG_1_0_BACK2BACK_ENABLED                    _MK_ENUM_CONST(0x00000001)                                                       // ----V
#define SATA0_CFG_1_0_INTR_DISABLE_SHIFT                    _MK_SHIFT_CONST(10)                                                             // RWWVF
#define SATA0_CFG_1_0_INTR_DISABLE_FIELD                   (_MK_SHIFT_CONST(0x1) << SATA0_CFG_1_0_INTR_DISABLE_SHIFT)
#define SATA0_CFG_1_0_INTR_DISABLE_RANGE                   10:10
#define SATA0_CFG_1_0_INTR_DISABLE_WOFFSET                 0
#define SATA0_CFG_1_0_INTR_DISABLE_DEFAULT                 (_MK_MASK_CONST(0x00000000)
#define SATA0_CFG_1_0_INTR_DISABLE_DEFAULT_MASK            (_MK_MASK_CONST(0x1)
#define SATA0_CFG_1_0_INTR_DISABLE_SW_DEFAULT              (_MK_MASK_CONST(0x00000000)
#define SATA0_CFG_1_0_INTR_DISABLE_SW_DEFAULT_MASK         (_MK_MASK_CONST(0x1)
#define SATA0_CFG_1_0_INTR_DISABLE_ON                      _MK_ENUM_CONST(0x00000000)                                                       // RWW-V
#define SATA0_CFG_1_0_INTR_DISABLE_OFF                     _MK_ENUM_CONST(0x00000001)                                                       // RW--V
#define SATA0_CFG_1_0_INTR_STATUS_SHIFT                     _MK_SHIFT_CONST(19)                                                             // R--VF
#define SATA0_CFG_1_0_INTR_STATUS_FIELD                    (_MK_SHIFT_CONST(0x1) << SATA0_CFG_1_0_INTR_STATUS_SHIFT)
#define SATA0_CFG_1_0_INTR_STATUS_RANGE                    19:19
#define SATA0_CFG_1_0_INTR_STATUS_WOFFSET                  0
#define SATA0_CFG_1_0_INTR_STATUS_0                        _MK_ENUM_CONST(0x00000000)                                                       // ----V
#define SATA0_CFG_1_0_INTR_STATUS_1                        _MK_ENUM_CONST(0x00000001)                                                       // ----V
#define SATA0_CFG_1_0_CAPLIST_SHIFT                         _MK_SHIFT_CONST(20)                                                             // C--VF
#define SATA0_CFG_1_0_CAPLIST_FIELD                        (_MK_SHIFT_CONST(0x1) << SATA0_CFG_1_0_CAPLIST_SHIFT)
#define SATA0_CFG_1_0_CAPLIST_RANGE                        20:20
#define SATA0_CFG_1_0_CAPLIST_WOFFSET                      0
#define SATA0_CFG_1_0_CAPLIST_PRESENT                      _MK_ENUM_CONST(0x00000001)                                                       // C---V
#define SATA0_CFG_1_0_CAPLIST_NOT_PRESENT                  _MK_ENUM_CONST(0x00000000)                                                       // ----V
#define SATA0_CFG_1_0_66MHZ_SHIFT                           _MK_SHIFT_CONST(21)                                                             // C--VF
#define SATA0_CFG_1_0_66MHZ_FIELD                          (_MK_SHIFT_CONST(0x1) << SATA0_CFG_1_0_66MHZ_SHIFT)
#define SATA0_CFG_1_0_66MHZ_RANGE                          21:21
#define SATA0_CFG_1_0_66MHZ_WOFFSET                        0
#define SATA0_CFG_1_0_66MHZ_CAPABLE                        _MK_ENUM_CONST(0x00000001)                                                       // C---V
#define SATA0_CFG_1_0_66MHZ_INCAPABLE                      _MK_ENUM_CONST(0x00000000)                                                       // ----V
#define SATA0_CFG_1_0_FAST_BACK2BACK_SHIFT                  _MK_SHIFT_CONST(23)                                                             // C--VF
#define SATA0_CFG_1_0_FAST_BACK2BACK_FIELD                 (_MK_SHIFT_CONST(0x1) << SATA0_CFG_1_0_FAST_BACK2BACK_SHIFT)
#define SATA0_CFG_1_0_FAST_BACK2BACK_RANGE                 23:23
#define SATA0_CFG_1_0_FAST_BACK2BACK_WOFFSET               0
#define SATA0_CFG_1_0_FAST_BACK2BACK_CAPABLE               _MK_ENUM_CONST(0x00000001)                                                       // C---V
#define SATA0_CFG_1_0_FAST_BACK2BACK_INCAPABLE             _MK_ENUM_CONST(0x00000000)                                                       // ----V
#define SATA0_CFG_1_0_MASTER_DATA_PERR_SHIFT                _MK_SHIFT_CONST(24)                                                             // C--VF
#define SATA0_CFG_1_0_MASTER_DATA_PERR_FIELD               (_MK_SHIFT_CONST(0x1) << SATA0_CFG_1_0_MASTER_DATA_PERR_SHIFT)
#define SATA0_CFG_1_0_MASTER_DATA_PERR_RANGE               24:24
#define SATA0_CFG_1_0_MASTER_DATA_PERR_WOFFSET             0
#define SATA0_CFG_1_0_MASTER_DATA_PERR_NOT_ACTIVE          _MK_ENUM_CONST(0x00000000)                                                       // C---V
#define SATA0_CFG_1_0_DEVSEL_TIMING_SHIFT                   _MK_SHIFT_CONST(25)                                                             // C--VF
#define SATA0_CFG_1_0_DEVSEL_TIMING_FIELD                  (_MK_SHIFT_CONST(0x3) << SATA0_CFG_1_0_DEVSEL_TIMING_SHIFT)
#define SATA0_CFG_1_0_DEVSEL_TIMING_RANGE                  26:25
#define SATA0_CFG_1_0_DEVSEL_TIMING_WOFFSET                0
#define SATA0_CFG_1_0_DEVSEL_TIMING_FAST                   _MK_ENUM_CONST(0x00000000)                                                       // C---V
#define SATA0_CFG_1_0_DEVSEL_TIMING_MEDIUM                 _MK_ENUM_CONST(0x00000001)                                                       // ----V
#define SATA0_CFG_1_0_DEVSEL_TIMING_SLOW                   _MK_ENUM_CONST(0x00000002)                                                       // ----V
#define SATA0_CFG_1_0_SIGNALED_TARGET_SHIFT                 _MK_SHIFT_CONST(27)                                                             // C--VF
#define SATA0_CFG_1_0_SIGNALED_TARGET_FIELD                (_MK_SHIFT_CONST(0x1) << SATA0_CFG_1_0_SIGNALED_TARGET_SHIFT)
#define SATA0_CFG_1_0_SIGNALED_TARGET_RANGE                27:27
#define SATA0_CFG_1_0_SIGNALED_TARGET_WOFFSET              0
#define SATA0_CFG_1_0_SIGNALED_TARGET_NO_ABORT             _MK_ENUM_CONST(0x00000000)                                                       // C---V
#define SATA0_CFG_1_0_RECEIVED_TARGET_SHIFT                 _MK_SHIFT_CONST(28)                                                             // RWCVF
#define SATA0_CFG_1_0_RECEIVED_TARGET_FIELD                (_MK_SHIFT_CONST(0x1) << SATA0_CFG_1_0_RECEIVED_TARGET_SHIFT)
#define SATA0_CFG_1_0_RECEIVED_TARGET_RANGE                28:28
#define SATA0_CFG_1_0_RECEIVED_TARGET_WOFFSET              0
#define SATA0_CFG_1_0_RECEIVED_TARGET_NO_ABORT             _MK_ENUM_CONST(0x00000000)                                                       // R-C-V
#define SATA0_CFG_1_0_RECEIVED_TARGET_ABORT                _MK_ENUM_CONST(0x00000001)                                                       // R---V
#define SATA0_CFG_1_0_RECEIVED_TARGET_CLEAR                _MK_ENUM_CONST(0x00000001)                                                       // -W--C
#define SATA0_CFG_1_0_RECEIVED_MASTER_SHIFT                 _MK_SHIFT_CONST(29)                                                             // RWCVF
#define SATA0_CFG_1_0_RECEIVED_MASTER_FIELD                (_MK_SHIFT_CONST(0x1) << SATA0_CFG_1_0_RECEIVED_MASTER_SHIFT)
#define SATA0_CFG_1_0_RECEIVED_MASTER_RANGE                29:29
#define SATA0_CFG_1_0_RECEIVED_MASTER_WOFFSET              0
#define SATA0_CFG_1_0_RECEIVED_MASTER_NO_ABORT             _MK_ENUM_CONST(0x00000000)                                                       // R-C-V
#define SATA0_CFG_1_0_RECEIVED_MASTER_ABORT                _MK_ENUM_CONST(0x00000001)                                                       // R---V
#define SATA0_CFG_1_0_RECEIVED_MASTER_CLEAR                _MK_ENUM_CONST(0x00000001)                                                       // -W--C
#define SATA0_CFG_1_0_SIGNALED_SERR_SHIFT                   _MK_SHIFT_CONST(30)                                                             // RWCVF
#define SATA0_CFG_1_0_SIGNALED_SERR_FIELD                  (_MK_SHIFT_CONST(0x1) << SATA0_CFG_1_0_SIGNALED_SERR_SHIFT)
#define SATA0_CFG_1_0_SIGNALED_SERR_RANGE                  30:30
#define SATA0_CFG_1_0_SIGNALED_SERR_WOFFSET                0
#define SATA0_CFG_1_0_SIGNALED_SERR_NOT_ACTIVE             _MK_ENUM_CONST(0x00000000)                                                       // R-C-V
#define SATA0_CFG_1_0_SIGNALED_SERR_ACTIVE                 _MK_ENUM_CONST(0x00000001)                                                       // R---V
#define SATA0_CFG_1_0_SIGNALED_SERR_CLEAR                  _MK_ENUM_CONST(0x00000001)                                                       // -W--C
#define SATA0_CFG_1_0_DETECTED_PERR_SHIFT                   _MK_SHIFT_CONST(31)                                                             // C--VF
#define SATA0_CFG_1_0_DETECTED_PERR_FIELD                  (_MK_SHIFT_CONST(0x1) << SATA0_CFG_1_0_DETECTED_PERR_SHIFT)
#define SATA0_CFG_1_0_DETECTED_PERR_RANGE                  31:31
#define SATA0_CFG_1_0_DETECTED_PERR_WOFFSET                0
#define SATA0_CFG_1_0_DETECTED_PERR_NOT_ACTIVE             _MK_ENUM_CONST(0x00000000)                                                       // C---V
// 
// 
//                 Figure 10-2  FPCI Configuration Register 04h
// 
// 
// 
// .TITLE PCI Revision ID and Class Code Register 08h
// This register provides a way to configure the SATA channel to
// operate in either compatability or native PCI mode.
// 
// .FIELD REVISION_ID
//      The REVISION_ID bits specify a device specific revision identifier.  The
// value is chosen by the vendor.  Zero is an acceptable value.  This field
// should be viewed as a vendor defined extension to the DEVICE_ID.
// /*
//          The Programming Interface provide a way to configure the SATA channel to
// operate in either compatability or native PCI mode. Bit MASTER_SATA defines
// the Bus mastering capability of SATA controller. Bits SEC_PROG_IND and
// PRI_PROG_IND define if channels can operate in both modes or not. And bits
// SEC_OP_MODE and PRI_OP_MODE defines the operating mode.
// */
// 
// .LABEL PRIVATE
// /*** A HACK was made here to work around a microsoft D0/D3 bug.
// We now report ourselves as non-programmable.
// The actual mode (native or legacy) is determined by the
// force_native bit in register 0x7C. ***/
// .LABEL PCI_CONFIG
// 
// 
// .FIELD PRI_OP_MODE
// Primary Operating Mode
// 0 = Compatibility Mode (Use Legacy Addresses)
// 1 = Native Mode (Use Addresses Define in PCI I/O BARs)
// 
// .FIELD PRI_PROG_IND
// Primary Programmable Indicator. Set to indicate it is programmable and can
// operate in both compatability or native PCI mode.
// 
// .FIELD SEC_OP_MODE
// Secondary Operating Mode
// 0 = Compatibility Mode (Use Legacy Addresses)
// 1 = Native Mode (Use Addresses Define in PCI I/O BARs)
// 
// .FIELD SEC_PROG_IND
// Secondary Programmable Indicator. Set to indicate it is programmable and can
// operate in both compatability or native PCI mode.
// 
// .FIELD CLASS_CODE
//      The CLASS_CODE bits identify the the generic function of the device and
// (in some cases) a specific register-level programming interface.  The register
// is broken into three byte-size fields.  The upper byte (at offset 0BH) is a
// base class code which broadly classifies the type of function the device
// performs.  The middle-byte (at offset 0AH)is a sub-class code which identifies
// more specificly the function of the device.  The lower byte (at offset 09H)
// identifies a specific register-level programming interface (if any) so that
// device independent software can interact with the device.
// 
// .FIELD SATA_BUS_MASTER
// This bit defines the Bus mastering capability of SATA controller.
// 
// .LABEL PRIVATE INT_REL
//     SATA implements a back door register which can be used to change the class
// code. This register is T_SATA0_CFG_38_BKDOOR_CLASS_CODE. This provides BIOS a
// way to change the class code.
// .LABEL PCI_CONFIG
// 
//  31           24 23           16 15            8 7             0
// .-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-.
// |0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1|1 0 0 0|1   1  |0 0 0 0 0 0 0 0| CFG_2
// `-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-'
// 
#define SATA0_CFG_2_0                                      0x00000008                                                                       // R--4R
#define SATA0_CFG_2_0_SECURE                               0
#define SATA0_CFG_2_0_WORD_COUNT                           1
#define SATA0_CFG_2_0_RESET_VAL                            0x0
#define SATA0_CFG_2_0_RESET_MASK                           0x0
#define SATA0_CFG_2_0_SW_DEFAULT_VAL                       0x0
#define SATA0_CFG_2_0_SW_DEFAULT_MASK                      0x0
#define SATA0_CFG_2_0_READ_MASK                            0xffff8fff
#define SATA0_CFG_2_0_WRITE_MASK                           0x0
#define SATA0_CFG_2_0_REVISION_ID_SHIFT                     _MK_SHIFT_CONST(0)                                                              // R-WVF
#define SATA0_CFG_2_0_REVISION_ID_FIELD                    (_MK_SHIFT_CONST(0xff) << SATA0_CFG_2_0_REVISION_ID_SHIFT)
#define SATA0_CFG_2_0_REVISION_ID_RANGE                    7:0
#define SATA0_CFG_2_0_REVISION_ID_WOFFSET                  0
#define SATA0_CFG_2_0_REVISION_ID_DEFAULT                  (_MK_MASK_CONST(0x000000A1)
#define SATA0_CFG_2_0_REVISION_ID_DEFAULT_MASK             (_MK_MASK_CONST(0xff)
#define SATA0_CFG_2_0_REVISION_ID_SW_DEFAULT               (_MK_MASK_CONST(0x000000A1)
#define SATA0_CFG_2_0_REVISION_ID_SW_DEFAULT_MASK          (_MK_MASK_CONST(0xff)
#define SATA0_CFG_2_0_REVISION_ID_VAL                      _MK_ENUM_CONST(0x000000A1)                                                       // R-W-V
#define SATA0_CFG_2_0_REVISION_ID_A1                       _MK_ENUM_CONST(0x000000A1)                                                       // ----V
#define SATA0_CFG_2_0_REVISION_ID_A2                       _MK_ENUM_CONST(0x000000A2)                                                       // ----V
#define SATA0_CFG_2_0_PRI_OP_MODE_SHIFT                     _MK_SHIFT_CONST(8)                                                              // R-WVF
#define SATA0_CFG_2_0_PRI_OP_MODE_FIELD                    (_MK_SHIFT_CONST(0x1) << SATA0_CFG_2_0_PRI_OP_MODE_SHIFT)
#define SATA0_CFG_2_0_PRI_OP_MODE_RANGE                    8:8
#define SATA0_CFG_2_0_PRI_OP_MODE_WOFFSET                  0
#define SATA0_CFG_2_0_PRI_OP_MODE_DEFAULT                  (_MK_MASK_CONST(0x00000001)
#define SATA0_CFG_2_0_PRI_OP_MODE_DEFAULT_MASK             (_MK_MASK_CONST(0x1)
#define SATA0_CFG_2_0_PRI_OP_MODE_SW_DEFAULT               (_MK_MASK_CONST(0x00000001)
#define SATA0_CFG_2_0_PRI_OP_MODE_SW_DEFAULT_MASK          (_MK_MASK_CONST(0x1)
#define SATA0_CFG_2_0_PRI_OP_MODE_INIT                     _MK_ENUM_CONST(0x00000001)                                                       // R-W-V
#define SATA0_CFG_2_0_PRI_OP_MODE_COMP                     _MK_ENUM_CONST(0x00000000)                                                       // ----V
#define SATA0_CFG_2_0_PRI_OP_MODE_NTV                      _MK_ENUM_CONST(0x00000001)                                                       // ----V
#define SATA0_CFG_2_0_PRI_PROG_IND_SHIFT                    _MK_SHIFT_CONST(9)                                                              // C--UF
#define SATA0_CFG_2_0_PRI_PROG_IND_FIELD                   (_MK_SHIFT_CONST(0x1) << SATA0_CFG_2_0_PRI_PROG_IND_SHIFT)
#define SATA0_CFG_2_0_PRI_PROG_IND_RANGE                   9:9
#define SATA0_CFG_2_0_PRI_PROG_IND_WOFFSET                 0
#define SATA0_CFG_2_0_PRI_PROG_IND_NO                      _MK_ENUM_CONST(0x00000000)                                                       // C---V
#define SATA0_CFG_2_0_SEC_OP_MODE_SHIFT                     _MK_SHIFT_CONST(10)                                                             // R-WVF
#define SATA0_CFG_2_0_SEC_OP_MODE_FIELD                    (_MK_SHIFT_CONST(0x1) << SATA0_CFG_2_0_SEC_OP_MODE_SHIFT)
#define SATA0_CFG_2_0_SEC_OP_MODE_RANGE                    10:10
#define SATA0_CFG_2_0_SEC_OP_MODE_WOFFSET                  0
#define SATA0_CFG_2_0_SEC_OP_MODE_DEFAULT                  (_MK_MASK_CONST(0x00000001)
#define SATA0_CFG_2_0_SEC_OP_MODE_DEFAULT_MASK             (_MK_MASK_CONST(0x1)
#define SATA0_CFG_2_0_SEC_OP_MODE_SW_DEFAULT               (_MK_MASK_CONST(0x00000001)
#define SATA0_CFG_2_0_SEC_OP_MODE_SW_DEFAULT_MASK          (_MK_MASK_CONST(0x1)
#define SATA0_CFG_2_0_SEC_OP_MODE_INIT                     _MK_ENUM_CONST(0x00000001)                                                       // R-W-V
#define SATA0_CFG_2_0_SEC_OP_MODE_COMP                     _MK_ENUM_CONST(0x00000000)                                                       // ----V
#define SATA0_CFG_2_0_SEC_OP_MODE_NTV                      _MK_ENUM_CONST(0x00000001)                                                       // ----V
#define SATA0_CFG_2_0_SEC_PROG_IND_SHIFT                    _MK_SHIFT_CONST(11)                                                             // C--UF
#define SATA0_CFG_2_0_SEC_PROG_IND_FIELD                   (_MK_SHIFT_CONST(0x1) << SATA0_CFG_2_0_SEC_PROG_IND_SHIFT)
#define SATA0_CFG_2_0_SEC_PROG_IND_RANGE                   11:11
#define SATA0_CFG_2_0_SEC_PROG_IND_WOFFSET                 0
#define SATA0_CFG_2_0_SEC_PROG_IND_NO                      _MK_ENUM_CONST(0x00000000)                                                       // C---V
#define SATA0_CFG_2_0_SATA_BUS_MASTER_SHIFT                 _MK_SHIFT_CONST(15)                                                             // C--UF
#define SATA0_CFG_2_0_SATA_BUS_MASTER_FIELD                (_MK_SHIFT_CONST(0x1) << SATA0_CFG_2_0_SATA_BUS_MASTER_SHIFT)
#define SATA0_CFG_2_0_SATA_BUS_MASTER_RANGE                15:15
#define SATA0_CFG_2_0_SATA_BUS_MASTER_WOFFSET              0
#define SATA0_CFG_2_0_SATA_BUS_MASTER_YES                  _MK_ENUM_CONST(0x00000001)                                                       // C---V
#define SATA0_CFG_2_0_CLASS_CODE_SHIFT                      _MK_SHIFT_CONST(16)                                                             // C--VF
#define SATA0_CFG_2_0_CLASS_CODE_FIELD                     (_MK_SHIFT_CONST(0xffff) << SATA0_CFG_2_0_CLASS_CODE_SHIFT)
#define SATA0_CFG_2_0_CLASS_CODE_RANGE                     31:16
#define SATA0_CFG_2_0_CLASS_CODE_WOFFSET                   0
#define SATA0_CFG_2_0_CLASS_CODE_0101                      _MK_ENUM_CONST(0x00000101)                                                       // C---V
// 
// 
// 
// 
// 
// 
// 
// 
// 
//                 Figure 10-3  FPCI Configuration Register 08h
// 
// 
// 
// 
// .TITLE PCI Configuration Register 0Ch
// 
// .FIELD LATENCY_TIMER
//      The LATENCY_TIMER bits contain, in units of PCI bus clocks, the value of
// the Latency Timer for this PCI bus master.  This register must be implemented
// as writable by any master that can burst more than two data phases.  This
// register may be implemented as read-only for devices that burst two or fewer
// data phases, but the hardwired value must be limited to 16 or less.  A typical
// implementation would be to build the five high-order bits (leaving the bottom
// three as read-only), resulting in a timer granularity of eight clocks.  At
// reset, the register should be set to 0 (if programmable).  LATENCY_TIMER bits
// are writable.
// .FIELD HEADER_TYPE_DEVICE
//      The HEADER_TYPE bits identify the layout of the bytes 10h through 3FH in
// configuration space and also whether or not the device contains multiple
// functions.  Bit 7 in this register is used to identify a multi-function
// device.  If the bit is 0, then the device is single function.  If the bit is
// 1, then the device has multiple functions.  Bits 6 through 0 specify the
// layout of bytes 10h through 3Fh.
// 
//      The LATENCY_TIMER and HEADER_TYPE are defined by parameters per block.
// 
//  31           24 23           16 15            8 7             0
// .-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-.
// |0 0 0 0 0 0 0 0|0 0 0 0 0 0 0 0|0 0 0 0 0 0 0 0|0 0 0 0 0 0 0 0| CFG_3
// `-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-'
// 
#define SATA0_CFG_3_0                                      0x0000000C                                                                       // RW-4R
#define SATA0_CFG_3_0_SECURE                               0
#define SATA0_CFG_3_0_WORD_COUNT                           1
#define SATA0_CFG_3_0_RESET_VAL                            0x0
#define SATA0_CFG_3_0_RESET_MASK                           0x0
#define SATA0_CFG_3_0_SW_DEFAULT_VAL                       0x0
#define SATA0_CFG_3_0_SW_DEFAULT_MASK                      0x0
#define SATA0_CFG_3_0_READ_MASK                            0xfff8ff
#define SATA0_CFG_3_0_WRITE_MASK                           0x0
#define SATA0_CFG_3_0_CACHE_LINE_SIZE_SHIFT                 _MK_SHIFT_CONST(0)                                                              // C--VF
#define SATA0_CFG_3_0_CACHE_LINE_SIZE_FIELD                (_MK_SHIFT_CONST(0xff) << SATA0_CFG_3_0_CACHE_LINE_SIZE_SHIFT)
#define SATA0_CFG_3_0_CACHE_LINE_SIZE_RANGE                7:0
#define SATA0_CFG_3_0_CACHE_LINE_SIZE_WOFFSET              0
#define SATA0_CFG_3_0_CACHE_LINE_SIZE_0                    _MK_ENUM_CONST(0x00000000)                                                       // C---V
#define SATA0_CFG_3_0_CACHE_LINE_SIZE_32                   _MK_ENUM_CONST(0x00000020)                                                       // ----V
#define SATA0_CFG_3_0_CACHE_LINE_SIZE_64                   _MK_ENUM_CONST(0x00000040)                                                       // ----V
#define SATA0_CFG_3_0_LATENCY_TIMER_SHIFT                   _MK_SHIFT_CONST(11)                                                             // C--VF
#define SATA0_CFG_3_0_LATENCY_TIMER_FIELD                  (_MK_SHIFT_CONST(0x1f) << SATA0_CFG_3_0_LATENCY_TIMER_SHIFT)
#define SATA0_CFG_3_0_LATENCY_TIMER_RANGE                  15:11
#define SATA0_CFG_3_0_LATENCY_TIMER_WOFFSET                0
#define SATA0_CFG_3_0_LATENCY_TIMER_0_CLOCKS               _MK_ENUM_CONST(0x00000000)                                                       // C---V
#define SATA0_CFG_3_0_LATENCY_TIMER_8_CLOCKS               _MK_ENUM_CONST(0x00000001)                                                       // ----V
#define SATA0_CFG_3_0_LATENCY_TIMER_240_CLOCKS             _MK_ENUM_CONST(0x0000001E)                                                       // ----V
#define SATA0_CFG_3_0_LATENCY_TIMER_248_CLOCKS             _MK_ENUM_CONST(0x0000001F)                                                       // ----V
#define SATA0_CFG_3_0_HEADER_TYPE_DEVICE_SHIFT              _MK_SHIFT_CONST(16)                                                             // C--VF
#define SATA0_CFG_3_0_HEADER_TYPE_DEVICE_FIELD             (_MK_SHIFT_CONST(0x7f) << SATA0_CFG_3_0_HEADER_TYPE_DEVICE_SHIFT)
#define SATA0_CFG_3_0_HEADER_TYPE_DEVICE_RANGE             22:16
#define SATA0_CFG_3_0_HEADER_TYPE_DEVICE_WOFFSET           0
#define SATA0_CFG_3_0_HEADER_TYPE_DEVICE_NON_BRIDGE        _MK_ENUM_CONST(0x00000000)                                                       // C---V
#define SATA0_CFG_3_0_HEADER_TYPE_DEVICE_P2P_BRIDGE        _MK_ENUM_CONST(0x00000001)                                                       // ----V
#define SATA0_CFG_3_0_HEADER_TYPE_FUNC_SHIFT                _MK_SHIFT_CONST(23)                                                             // C--VF
#define SATA0_CFG_3_0_HEADER_TYPE_FUNC_FIELD               (_MK_SHIFT_CONST(0x1) << SATA0_CFG_3_0_HEADER_TYPE_FUNC_SHIFT)
#define SATA0_CFG_3_0_HEADER_TYPE_FUNC_RANGE               23:23
#define SATA0_CFG_3_0_HEADER_TYPE_FUNC_WOFFSET             0
#define SATA0_CFG_3_0_HEADER_TYPE_FUNC_SINGLE              _MK_ENUM_CONST(0x00000000)                                                       // C---V
#define SATA0_CFG_3_0_HEADER_TYPE_FUNC_MULTI               _MK_ENUM_CONST(0x00000001)                                                       // ----V
// 
// 
// 
//                 Figure 10-4  FPCI Configuration Register 0Ch
// 
// 
// 
// 
// .TITLE PCI Configuration Register 10h
// 
// .FIELD SPACE_TYPE
//      The SPACE_TYPE bit indicates whether the register maps into Memory or I/O
// space.
// .FIELD BASE_ADDRESS
//      The BASE_ADDRESS bits contain the base address of the device.  The number
// of upper bits that a device actually implements depends on how much of the
// address space the device will respond to.  A device that wants a 1 MB memory
// address space (using a 32-bit base address register) would build the top 12
// bits of the address register, hardwiring the other bits to 0.  Power-up
// software can determine how much address space the device requires by writing a
// value of all 1's to the register and then reading the value back.  The device
// will return 0's in all address bits which are not required, effectively specifying the
// address space required.
// 
// When T_SATA0_CFG_2_PRI_OP_MODE is cleared, T_SATA_CFG_4 and T_SATA_CFG_5
// will always read 32'h00000000. And when T_SATA0_CFG_2_SEC_OP_MODE is cleared,
// T_SATA0_CFG_6 and T_SATA_CFG_7 will always read 32'h00000000.
// 
// 
//  31           24 23           16 15            8 7             0
// .-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-.
// |                                                         |0 0|1| CFG_4
// `-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-'
// 
#define SATA0_CFG_4_0                                      0x00000010                                                                       // RW-4R
#define SATA0_CFG_4_0_SECURE                               0
#define SATA0_CFG_4_0_WORD_COUNT                           1
#define SATA0_CFG_4_0_RESET_VAL                            0x0
#define SATA0_CFG_4_0_RESET_MASK                           0x0
#define SATA0_CFG_4_0_SW_DEFAULT_VAL                       0x0
#define SATA0_CFG_4_0_SW_DEFAULT_MASK                      0x0
#define SATA0_CFG_4_0_READ_MASK                            0xfffffff9
#define SATA0_CFG_4_0_WRITE_MASK                           0xfffffff8
#define SATA0_CFG_4_0_SPACE_TYPE_SHIFT                      _MK_SHIFT_CONST(0)                                                              // R-WVF
#define SATA0_CFG_4_0_SPACE_TYPE_FIELD                     (_MK_SHIFT_CONST(0x1) << SATA0_CFG_4_0_SPACE_TYPE_SHIFT)
#define SATA0_CFG_4_0_SPACE_TYPE_RANGE                     0:0
#define SATA0_CFG_4_0_SPACE_TYPE_WOFFSET                   0
#define SATA0_CFG_4_0_SPACE_TYPE_DEFAULT                   (_MK_MASK_CONST(0x00000001)
#define SATA0_CFG_4_0_SPACE_TYPE_DEFAULT_MASK              (_MK_MASK_CONST(0x1)
#define SATA0_CFG_4_0_SPACE_TYPE_SW_DEFAULT                (_MK_MASK_CONST(0x00000001)
#define SATA0_CFG_4_0_SPACE_TYPE_SW_DEFAULT_MASK           (_MK_MASK_CONST(0x1)
#define SATA0_CFG_4_0_SPACE_TYPE_MEMORY                    _MK_ENUM_CONST(0x00000000)                                                       // R---V
#define SATA0_CFG_4_0_SPACE_TYPE_IO                        _MK_ENUM_CONST(0x00000001)                                                       // R-W-V
#define SATA0_CFG_4_0_BASE_ADDRESS_SHIFT                    _MK_SHIFT_CONST(3)                                                              // RWWUF
#define SATA0_CFG_4_0_BASE_ADDRESS_FIELD                   (_MK_SHIFT_CONST(0x1fffffff) << SATA0_CFG_4_0_BASE_ADDRESS_SHIFT)
#define SATA0_CFG_4_0_BASE_ADDRESS_RANGE                   31:3
#define SATA0_CFG_4_0_BASE_ADDRESS_WOFFSET                 0
#define SATA0_CFG_4_0_BASE_ADDRESS_DEFAULT                 (_MK_MASK_CONST(0x00000000)
#define SATA0_CFG_4_0_BASE_ADDRESS_DEFAULT_MASK            (_MK_MASK_CONST(0x1fffffff)
#define SATA0_CFG_4_0_BASE_ADDRESS_SW_DEFAULT              (_MK_MASK_CONST(0x00000000)
#define SATA0_CFG_4_0_BASE_ADDRESS_SW_DEFAULT_MASK         (_MK_MASK_CONST(0x1fffffff)
#define SATA0_CFG_4_0_BASE_ADDRESS__NOPRDCHK               _MK_ENUM_CONST(0x00000001)                                                       // ----V
#define SATA0_CFG_4_0_BASE_ADDRESS_00                      _MK_ENUM_CONST(0x00000000)                                                       // RWW-V
#define SATA0_CFG_4_0_BASE_ADDRESS_NTV_PCA                 _MK_ENUM_CONST(0x00000000)                                                       // RW--V
// 
// 
//                 Figure 10-5  FPCI Configuration Register 10h
// 
// .TITLE  PCI Configuration Register 14h
// 
// .FIELD SPACE_TYPE
//      The SPACE_TYPE bit indicates whether the register maps into Memory or I/O
// space.
// .FIELD BASE_ADDRESS
//      The BASE_ADDRESS bits contain the base address of the device.  The number
// of upper bits that a device actually implements depends on how much of the
// address space the device will respond to.  A device that wants a 1 MB memory
// address space (using a 32-bit base address register) would build the top 12
// bits of the address register, hardwiring the other bits to 0.  Power-up
// software can determine how much address space the device requires by writing a
// value of all 1's to the register and then reading the value back.  The device
// will return 0's in all address bits which are not required, effectively specifying the
// address space required.
// 
// When T_SATA0_CFG_2_PRI_OP_MODE is cleared, T_SATA_CFG_4 and T_SATA_CFG_5
// will always read 32'h00000000. And when T_SATA0_CFG_2_SEC_OP_MODE is cleared,
// T_SATA0_CFG_6 and T_SATA_CFG_7 will always read 32'h00000000.
// 
//  31           24 23           16 15            8 7             0
// .-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-.
// |                                                           |0|1| CFG_5
// `-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-'
// 
#define SATA0_CFG_5_0                                      0x00000014                                                                       // RW-4R
#define SATA0_CFG_5_0_SECURE                               0
#define SATA0_CFG_5_0_WORD_COUNT                           1
#define SATA0_CFG_5_0_RESET_VAL                            0x0
#define SATA0_CFG_5_0_RESET_MASK                           0x0
#define SATA0_CFG_5_0_SW_DEFAULT_VAL                       0x0
#define SATA0_CFG_5_0_SW_DEFAULT_MASK                      0x0
#define SATA0_CFG_5_0_READ_MASK                            0xfffffffd
#define SATA0_CFG_5_0_WRITE_MASK                           0xfffffffc
#define SATA0_CFG_5_0_SPACE_TYPE_SHIFT                      _MK_SHIFT_CONST(0)                                                              // R-WVF
#define SATA0_CFG_5_0_SPACE_TYPE_FIELD                     (_MK_SHIFT_CONST(0x1) << SATA0_CFG_5_0_SPACE_TYPE_SHIFT)
#define SATA0_CFG_5_0_SPACE_TYPE_RANGE                     0:0
#define SATA0_CFG_5_0_SPACE_TYPE_WOFFSET                   0
#define SATA0_CFG_5_0_SPACE_TYPE_DEFAULT                   (_MK_MASK_CONST(0x00000001)
#define SATA0_CFG_5_0_SPACE_TYPE_DEFAULT_MASK              (_MK_MASK_CONST(0x1)
#define SATA0_CFG_5_0_SPACE_TYPE_SW_DEFAULT                (_MK_MASK_CONST(0x00000001)
#define SATA0_CFG_5_0_SPACE_TYPE_SW_DEFAULT_MASK           (_MK_MASK_CONST(0x1)
#define SATA0_CFG_5_0_SPACE_TYPE_MEMORY                    _MK_ENUM_CONST(0x00000000)                                                       // R---V
#define SATA0_CFG_5_0_SPACE_TYPE_IO                        _MK_ENUM_CONST(0x00000001)                                                       // R-W-V
#define SATA0_CFG_5_0_BASE_ADDRESS_SHIFT                    _MK_SHIFT_CONST(2)                                                              // RWWUF
#define SATA0_CFG_5_0_BASE_ADDRESS_FIELD                   (_MK_SHIFT_CONST(0x3fffffff) << SATA0_CFG_5_0_BASE_ADDRESS_SHIFT)
#define SATA0_CFG_5_0_BASE_ADDRESS_RANGE                   31:2
#define SATA0_CFG_5_0_BASE_ADDRESS_WOFFSET                 0
#define SATA0_CFG_5_0_BASE_ADDRESS_DEFAULT                 (_MK_MASK_CONST(0x00000000)
#define SATA0_CFG_5_0_BASE_ADDRESS_DEFAULT_MASK            (_MK_MASK_CONST(0x3fffffff)
#define SATA0_CFG_5_0_BASE_ADDRESS_SW_DEFAULT              (_MK_MASK_CONST(0x00000000)
#define SATA0_CFG_5_0_BASE_ADDRESS_SW_DEFAULT_MASK         (_MK_MASK_CONST(0x3fffffff)
#define SATA0_CFG_5_0_BASE_ADDRESS__NOPRDCHK               _MK_ENUM_CONST(0x00000001)                                                       // ----V
#define SATA0_CFG_5_0_BASE_ADDRESS_00                      _MK_ENUM_CONST(0x00000000)                                                       // RWW-V
#define SATA0_CFG_5_0_BASE_ADDRESS_NTV_PSA                 _MK_ENUM_CONST(0x00000000)                                                       // RW--V
// 
// 
//                 Figure 10-6  FPCI Configuration Register 14h
// 
// .TITLE  PCI Configuration Register 18h
// 
// .FIELD SPACE_TYPE
//      The SPACE_TYPE bit indicates whether the register maps into Memory or I/O
// space.
// .FIELD BASE_ADDRESS
//      The BASE_ADDRESS bits contain the base address of the device.  The number
// of upper bits that a device actually implements depends on how much of the
// address space the device will respond to.  A device that wants a 1 MB memory
// address space (using a 32-bit base address register) would build the top 12
// bits of the address register, hardwiring the other bits to 0.  Power-up
// software can determine how much address space the device requires by writing a
// value of all 1's to the register and then reading the value back.  The device
// will return 0's in all address bits which are not required, effectively specifying the
// address space required.
// 
// When T_SATA0_CFG_2_PRI_OP_MODE is cleared, T_SATA_CFG_4 and T_SATA_CFG_5
// will always read 32'h00000000. And when T_SATA0_CFG_2_SEC_OP_MODE is cleared,
// T_SATA0_CFG_6 and T_SATA_CFG_7 will always read 32'h00000000.
// 
//  31           24 23           16 15            8 7             0
// .-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-.
// |                                                         |0|0|1| CFG_6
// `-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-'
// 
#define SATA0_CFG_6_0                                      0x00000018                                                                       // RW-4R
#define SATA0_CFG_6_0_SECURE                               0
#define SATA0_CFG_6_0_WORD_COUNT                           1
#define SATA0_CFG_6_0_RESET_VAL                            0x0
#define SATA0_CFG_6_0_RESET_MASK                           0x0
#define SATA0_CFG_6_0_SW_DEFAULT_VAL                       0x0
#define SATA0_CFG_6_0_SW_DEFAULT_MASK                      0x0
#define SATA0_CFG_6_0_READ_MASK                            0xfffffff9
#define SATA0_CFG_6_0_WRITE_MASK                           0xfffffff8
#define SATA0_CFG_6_0_SPACE_TYPE_SHIFT                      _MK_SHIFT_CONST(0)                                                              // R-WVF
#define SATA0_CFG_6_0_SPACE_TYPE_FIELD                     (_MK_SHIFT_CONST(0x1) << SATA0_CFG_6_0_SPACE_TYPE_SHIFT)
#define SATA0_CFG_6_0_SPACE_TYPE_RANGE                     0:0
#define SATA0_CFG_6_0_SPACE_TYPE_WOFFSET                   0
#define SATA0_CFG_6_0_SPACE_TYPE_DEFAULT                   (_MK_MASK_CONST(0x00000001)
#define SATA0_CFG_6_0_SPACE_TYPE_DEFAULT_MASK              (_MK_MASK_CONST(0x1)
#define SATA0_CFG_6_0_SPACE_TYPE_SW_DEFAULT                (_MK_MASK_CONST(0x00000001)
#define SATA0_CFG_6_0_SPACE_TYPE_SW_DEFAULT_MASK           (_MK_MASK_CONST(0x1)
#define SATA0_CFG_6_0_SPACE_TYPE_MEMORY                    _MK_ENUM_CONST(0x00000000)                                                       // R---V
#define SATA0_CFG_6_0_SPACE_TYPE_IO                        _MK_ENUM_CONST(0x00000001)                                                       // R-W-V
#define SATA0_CFG_6_0_BASE_ADDRESS_SHIFT                    _MK_SHIFT_CONST(3)                                                              // RWWUF
#define SATA0_CFG_6_0_BASE_ADDRESS_FIELD                   (_MK_SHIFT_CONST(0x1fffffff) << SATA0_CFG_6_0_BASE_ADDRESS_SHIFT)
#define SATA0_CFG_6_0_BASE_ADDRESS_RANGE                   31:3
#define SATA0_CFG_6_0_BASE_ADDRESS_WOFFSET                 0
#define SATA0_CFG_6_0_BASE_ADDRESS_DEFAULT                 (_MK_MASK_CONST(0x00000000)
#define SATA0_CFG_6_0_BASE_ADDRESS_DEFAULT_MASK            (_MK_MASK_CONST(0x1fffffff)
#define SATA0_CFG_6_0_BASE_ADDRESS_SW_DEFAULT              (_MK_MASK_CONST(0x00000000)
#define SATA0_CFG_6_0_BASE_ADDRESS_SW_DEFAULT_MASK         (_MK_MASK_CONST(0x1fffffff)
#define SATA0_CFG_6_0_BASE_ADDRESS__NOPRDCHK               _MK_ENUM_CONST(0x00000001)                                                       // ----V
#define SATA0_CFG_6_0_BASE_ADDRESS_00                      _MK_ENUM_CONST(0x00000000)                                                       // RWW-V
#define SATA0_CFG_6_0_BASE_ADDRESS_NTV_SCA                 _MK_ENUM_CONST(0x00000000)                                                       // RW--V
// 
// 
//                 Figure 10-7  FPCI Configuration Register 18h
// 
// .TITLE  PCI Configuration Register 1Ch
// 
// .FIELD SPACE_TYPE
//      The SPACE_TYPE bit indicates whether the register maps into Memory or I/O
// space.
// .FIELD BASE_ADDRESS
//      The BASE_ADDRESS bits contain the base address of the device.  The number
// of upper bits that a device actually implements depends on how much of the
// address space the device will respond to.  A device that wants a 1 MB memory
// address space (using a 32-bit base address register) would build the top 12
// bits of the address register, hardwiring the other bits to 0.  Power-up
// software can determine how much address space the device requires by writing a
// value of all 1's to the register and then reading the value back.  The device
// will return 0's in all address bits which are not required, effectively specifying the
// address space required.
// 
// When T_SATA0_CFG_2_SEC_OP_MODE is cleared, this register will always read 32'h00000000.
// 
//  31           24 23           16 15            8 7             0
// .-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-.
// |                                                           |0|1| CFG_7
// `-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-'
// 
#define SATA0_CFG_7_0                                      0x0000001C                                                                       // RW-4R
#define SATA0_CFG_7_0_SECURE                               0
#define SATA0_CFG_7_0_WORD_COUNT                           1
#define SATA0_CFG_7_0_RESET_VAL                            0x0
#define SATA0_CFG_7_0_RESET_MASK                           0x0
#define SATA0_CFG_7_0_SW_DEFAULT_VAL                       0x0
#define SATA0_CFG_7_0_SW_DEFAULT_MASK                      0x0
#define SATA0_CFG_7_0_READ_MASK                            0xfffffffd
#define SATA0_CFG_7_0_WRITE_MASK                           0xfffffffc
#define SATA0_CFG_7_0_SPACE_TYPE_SHIFT                      _MK_SHIFT_CONST(0)                                                              // R-WVF
#define SATA0_CFG_7_0_SPACE_TYPE_FIELD                     (_MK_SHIFT_CONST(0x1) << SATA0_CFG_7_0_SPACE_TYPE_SHIFT)
#define SATA0_CFG_7_0_SPACE_TYPE_RANGE                     0:0
#define SATA0_CFG_7_0_SPACE_TYPE_WOFFSET                   0
#define SATA0_CFG_7_0_SPACE_TYPE_DEFAULT                   (_MK_MASK_CONST(0x00000001)
#define SATA0_CFG_7_0_SPACE_TYPE_DEFAULT_MASK              (_MK_MASK_CONST(0x1)
#define SATA0_CFG_7_0_SPACE_TYPE_SW_DEFAULT                (_MK_MASK_CONST(0x00000001)
#define SATA0_CFG_7_0_SPACE_TYPE_SW_DEFAULT_MASK           (_MK_MASK_CONST(0x1)
#define SATA0_CFG_7_0_SPACE_TYPE_MEMORY                    _MK_ENUM_CONST(0x00000000)                                                       // R---V
#define SATA0_CFG_7_0_SPACE_TYPE_IO                        _MK_ENUM_CONST(0x00000001)                                                       // R-W-V
#define SATA0_CFG_7_0_BASE_ADDRESS_SHIFT                    _MK_SHIFT_CONST(2)                                                              // RWWUF
#define SATA0_CFG_7_0_BASE_ADDRESS_FIELD                   (_MK_SHIFT_CONST(0x3fffffff) << SATA0_CFG_7_0_BASE_ADDRESS_SHIFT)
#define SATA0_CFG_7_0_BASE_ADDRESS_RANGE                   31:2
#define SATA0_CFG_7_0_BASE_ADDRESS_WOFFSET                 0
#define SATA0_CFG_7_0_BASE_ADDRESS_DEFAULT                 (_MK_MASK_CONST(0x00000000)
#define SATA0_CFG_7_0_BASE_ADDRESS_DEFAULT_MASK            (_MK_MASK_CONST(0x3fffffff)
#define SATA0_CFG_7_0_BASE_ADDRESS_SW_DEFAULT              (_MK_MASK_CONST(0x00000000)
#define SATA0_CFG_7_0_BASE_ADDRESS_SW_DEFAULT_MASK         (_MK_MASK_CONST(0x3fffffff)
#define SATA0_CFG_7_0_BASE_ADDRESS__NOPRDCHK               _MK_ENUM_CONST(0x00000001)                                                       // ----V
#define SATA0_CFG_7_0_BASE_ADDRESS_00                      _MK_ENUM_CONST(0x00000000)                                                       // RWW-V
#define SATA0_CFG_7_0_BASE_ADDRESS_NTV_SSA                 _MK_ENUM_CONST(0x00000000)                                                       // RW--V
// 
// 
//                 Figure 10-8  FPCI Configuration Register 1Ch
// 
// .TITLE PCI Configuration Register 20h
// T_SATA0_CFG_8 is a 16-byte I/O BAR for two things:
//   - The BusMaster control registers for both channels.
// 
// .FIELD SPACE_TYPE
//      The SPACE_TYPE bit indicates whether the register maps into Memory or I/O
// space.
// .FIELD BASE_ADDRESS
//      The BASE_ADDRESS bits contain the base address of the device.  The number
// of upper bits that a device actually implements depends on how much of the
// address space the device will respond to.  A device that wants a 1 MB memory
// address space (using a 32-bit base address register) would build the top 12
// bits of the address register, hardwiring the other bits to 0.  Power-up
// software can determine how much address space the device requires by writing a
// value of all 1's to the register and then reading the value back.  The device
// will return 0's in all address bits which are not required, effectively specifying the
// address space required.
// 
//  31           24 23           16 15            8 7             0
// .-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-.
// |                                                       |0 0 0 1| CFG_8
// `-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-'
#define SATA0_CFG_8_0                                      0x00000020                                                                       // RW-4R
#define SATA0_CFG_8_0_SECURE                               0
#define SATA0_CFG_8_0_WORD_COUNT                           1
#define SATA0_CFG_8_0_RESET_VAL                            0x0
#define SATA0_CFG_8_0_RESET_MASK                           0x0
#define SATA0_CFG_8_0_SW_DEFAULT_VAL                       0x0
#define SATA0_CFG_8_0_SW_DEFAULT_MASK                      0x0
#define SATA0_CFG_8_0_READ_MASK                            0xfffffff1
#define SATA0_CFG_8_0_WRITE_MASK                           0xfffffff0
#define SATA0_CFG_8_0_SPACE_TYPE_SHIFT                      _MK_SHIFT_CONST(0)                                                              // C--VF
#define SATA0_CFG_8_0_SPACE_TYPE_FIELD                     (_MK_SHIFT_CONST(0x1) << SATA0_CFG_8_0_SPACE_TYPE_SHIFT)
#define SATA0_CFG_8_0_SPACE_TYPE_RANGE                     0:0
#define SATA0_CFG_8_0_SPACE_TYPE_WOFFSET                   0
#define SATA0_CFG_8_0_SPACE_TYPE_IO                        _MK_ENUM_CONST(0x00000001)                                                       // C---V
#define SATA0_CFG_8_0_SPACE_TYPE_MEMORY                    _MK_ENUM_CONST(0x00000000)                                                       // ----V
#define SATA0_CFG_8_0_BASE_ADDRESS_SHIFT                    _MK_SHIFT_CONST(4)                                                              // RWWUF
#define SATA0_CFG_8_0_BASE_ADDRESS_FIELD                   (_MK_SHIFT_CONST(0xfffffff) << SATA0_CFG_8_0_BASE_ADDRESS_SHIFT)
#define SATA0_CFG_8_0_BASE_ADDRESS_RANGE                   31:4
#define SATA0_CFG_8_0_BASE_ADDRESS_WOFFSET                 0
#define SATA0_CFG_8_0_BASE_ADDRESS_DEFAULT                 (_MK_MASK_CONST(0x00000000)
#define SATA0_CFG_8_0_BASE_ADDRESS_DEFAULT_MASK            (_MK_MASK_CONST(0xfffffff)
#define SATA0_CFG_8_0_BASE_ADDRESS_SW_DEFAULT              (_MK_MASK_CONST(0x00000000)
#define SATA0_CFG_8_0_BASE_ADDRESS_SW_DEFAULT_MASK         (_MK_MASK_CONST(0xfffffff)
#define SATA0_CFG_8_0_BASE_ADDRESS__NOPRDCHK               _MK_ENUM_CONST(0x00000001)                                                       // ----V
#define SATA0_CFG_8_0_BASE_ADDRESS_BMA                     _MK_ENUM_CONST(0x00000000)                                                       // RWW-V
// 
// 
// 
// 
//                 Figure 10-9  PCI Configuration Register 20h
// 
// .TITLE  PCI Mem BAR For AHCI Register 24h
// 
// T_SATA0_CFG_9 is memory-BAR register for AHCI registers. Size of this memory
// space is 4KB+256Bytes.
// First 32 Bytes are used for Host control regsiters.
// Next 128 Bytes are reserved.
// Next 96 Bytes for vendor specific regsiters.
// Each port has 128 Byte register space.
// 
//  31           24 23           16 15            8 7             0
// .-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-.
// |                                     |0 0 0 0 0 0 0 0 0 0 0 0 1| CFG_9
// `-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-'
#define SATA0_CFG_9_0                                      0x00000024                                                                       // RW-4R
#define SATA0_CFG_9_0_SECURE                               0
#define SATA0_CFG_9_0_WORD_COUNT                           1
#define SATA0_CFG_9_0_RESET_VAL                            0x0
#define SATA0_CFG_9_0_RESET_MASK                           0x0
#define SATA0_CFG_9_0_SW_DEFAULT_VAL                       0x0
#define SATA0_CFG_9_0_SW_DEFAULT_MASK                      0x0
#define SATA0_CFG_9_0_READ_MASK                            0xffffe001
#define SATA0_CFG_9_0_WRITE_MASK                           0xffffe000
#define SATA0_CFG_9_0_SPACE_TYPE_SHIFT                      _MK_SHIFT_CONST(0)                                                              // C--VF
#define SATA0_CFG_9_0_SPACE_TYPE_FIELD                     (_MK_SHIFT_CONST(0x1) << SATA0_CFG_9_0_SPACE_TYPE_SHIFT)
#define SATA0_CFG_9_0_SPACE_TYPE_RANGE                     0:0
#define SATA0_CFG_9_0_SPACE_TYPE_WOFFSET                   0
#define SATA0_CFG_9_0_SPACE_TYPE_IO                        _MK_ENUM_CONST(0x00000001)                                                       // ----V
#define SATA0_CFG_9_0_SPACE_TYPE_MEMORY                    _MK_ENUM_CONST(0x00000000)                                                       // C---V
#define SATA0_CFG_9_0_BASE_ADDRESS_SHIFT                    _MK_SHIFT_CONST(13)                                                             // RWWUF
#define SATA0_CFG_9_0_BASE_ADDRESS_FIELD                   (_MK_SHIFT_CONST(0x7ffff) << SATA0_CFG_9_0_BASE_ADDRESS_SHIFT)
#define SATA0_CFG_9_0_BASE_ADDRESS_RANGE                   31:13
#define SATA0_CFG_9_0_BASE_ADDRESS_WOFFSET                 0
#define SATA0_CFG_9_0_BASE_ADDRESS_DEFAULT                 (_MK_MASK_CONST(0x00000000)
#define SATA0_CFG_9_0_BASE_ADDRESS_DEFAULT_MASK            (_MK_MASK_CONST(0x7ffff)
#define SATA0_CFG_9_0_BASE_ADDRESS_SW_DEFAULT              (_MK_MASK_CONST(0x00000000)
#define SATA0_CFG_9_0_BASE_ADDRESS_SW_DEFAULT_MASK         (_MK_MASK_CONST(0x7ffff)
#define SATA0_CFG_9_0_BASE_ADDRESS__NOPRDCHK               _MK_ENUM_CONST(0x00000001)                                                       // ----V
#define SATA0_CFG_9_0_BASE_ADDRESS_INIT                    _MK_ENUM_CONST(0x00000000)                                                       // RWW-V
// 
// 
// 
//                 Figure 10-10  PCI Configuration Register 24h
// 
// 
//      These are unused BAR locations.
// 
// .-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-.
// |0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0| CFG_10
// `-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-'
#define SATA0_CFG_10_0                                     0x00000028                                                                       // R--4R
#define SATA0_CFG_10_0_SECURE                              0
#define SATA0_CFG_10_0_WORD_COUNT                          1
#define SATA0_CFG_10_0_RESET_VAL                           0x0
#define SATA0_CFG_10_0_RESET_MASK                          0x0
#define SATA0_CFG_10_0_SW_DEFAULT_VAL                      0x0
#define SATA0_CFG_10_0_SW_DEFAULT_MASK                     0x0
#define SATA0_CFG_10_0_READ_MASK                           0xffffffff
#define SATA0_CFG_10_0_WRITE_MASK                          0x0
#define SATA0_CFG_10_0_RESERVED_SHIFT                       _MK_SHIFT_CONST(0)                                                              // C--VF
#define SATA0_CFG_10_0_RESERVED_FIELD                      (_MK_SHIFT_CONST(0xffffffff) << SATA0_CFG_10_0_RESERVED_SHIFT)
#define SATA0_CFG_10_0_RESERVED_RANGE                      31:0
#define SATA0_CFG_10_0_RESERVED_WOFFSET                    0
#define SATA0_CFG_10_0_RESERVED_0                          _MK_ENUM_CONST(0x00000000)                                                       // C---V
// 
//                 Figure 10-10  PCI Configuration Register 28h
// 
// .LABEL PCI_CONFIG
// 
// .TITLE PCI Subsystem Vendor ID and Subsystem ID 2Ch
// 
// .FIELD SUBSYSTEM_VENDOR_ID
//      Subsystem Vendor ID is read-only. The system BIOS can set this value
// by writing to Configuration [40h].
// .FIELD SUBSYSTEM_ID
//      Subsystem ID is read-only. The system BIOS can set this value by
// writing to Configuration [42h].
// .LABEL PRIVATE
// /*     The SUBSYSTEM_VENDOR_ID bits and SUBSYSTEM_ID bits are used to uniquely
// identify the add-in board or subsystem where the device resides.  When the
// device is on the motherboard, there is no serial ROM and the registers both
// initialize to NONE.  The motherboard BIOS must set the values of the Subsystem
// ID and Subsystem Vendor ID by writing the proper values to the
// SUBSYSTEM_VENDOR_ID and SUBSYSTEM_ID bits in the CFG_16 register
// (NOT CFG_11). */
// .LABEL PCI_CONFIG
// 
//  31           24 23           16 15            8 7             0
// .-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-.
// |                               |                               | CFG_11
// `-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-'
// 
#define SATA0_CFG_11_0                                     0x0000002C                                                                       // R--4R
#define SATA0_CFG_11_0_SECURE                              0
#define SATA0_CFG_11_0_WORD_COUNT                          1
#define SATA0_CFG_11_0_RESET_VAL                           0x0
#define SATA0_CFG_11_0_RESET_MASK                          0x0
#define SATA0_CFG_11_0_SW_DEFAULT_VAL                      0x0
#define SATA0_CFG_11_0_SW_DEFAULT_MASK                     0x0
#define SATA0_CFG_11_0_READ_MASK                           0xffffffff
#define SATA0_CFG_11_0_WRITE_MASK                          0x0
#define SATA0_CFG_11_0_SUBSYSTEM_VENDOR_ID_SHIFT            _MK_SHIFT_CONST(0)                                                              // R-WUF
#define SATA0_CFG_11_0_SUBSYSTEM_VENDOR_ID_FIELD           (_MK_SHIFT_CONST(0xffff) << SATA0_CFG_11_0_SUBSYSTEM_VENDOR_ID_SHIFT)
#define SATA0_CFG_11_0_SUBSYSTEM_VENDOR_ID_RANGE           15:0
#define SATA0_CFG_11_0_SUBSYSTEM_VENDOR_ID_WOFFSET         0
#define SATA0_CFG_11_0_SUBSYSTEM_VENDOR_ID_DEFAULT         (_MK_MASK_CONST(0x00000000)
#define SATA0_CFG_11_0_SUBSYSTEM_VENDOR_ID_DEFAULT_MASK    (_MK_MASK_CONST(0xffff)
#define SATA0_CFG_11_0_SUBSYSTEM_VENDOR_ID_SW_DEFAULT      (_MK_MASK_CONST(0x00000000)
#define SATA0_CFG_11_0_SUBSYSTEM_VENDOR_ID_SW_DEFAULT_MASK (_MK_MASK_CONST(0xffff)
#define SATA0_CFG_11_0_SUBSYSTEM_VENDOR_ID_NONE            _MK_ENUM_CONST(0x00000000)                                                       // R-W-V
#define SATA0_CFG_11_0_SUBSYSTEM_ID_SHIFT                   _MK_SHIFT_CONST(16)                                                             // R-WUF
#define SATA0_CFG_11_0_SUBSYSTEM_ID_FIELD                  (_MK_SHIFT_CONST(0xffff) << SATA0_CFG_11_0_SUBSYSTEM_ID_SHIFT)
#define SATA0_CFG_11_0_SUBSYSTEM_ID_RANGE                  31:16
#define SATA0_CFG_11_0_SUBSYSTEM_ID_WOFFSET                0
#define SATA0_CFG_11_0_SUBSYSTEM_ID_DEFAULT                (_MK_MASK_CONST(0x00000000)
#define SATA0_CFG_11_0_SUBSYSTEM_ID_DEFAULT_MASK           (_MK_MASK_CONST(0xffff)
#define SATA0_CFG_11_0_SUBSYSTEM_ID_SW_DEFAULT             (_MK_MASK_CONST(0x00000000)
#define SATA0_CFG_11_0_SUBSYSTEM_ID_SW_DEFAULT_MASK        (_MK_MASK_CONST(0xffff)
#define SATA0_CFG_11_0_SUBSYSTEM_ID_NONE                   _MK_ENUM_CONST(0x00000000)                                                       // R-W-V
// 
// 
// 
//                 Figure 10-11  PCI Configuration Register 2Ch
// 
// 
// 
// .TITLE Expansion ROM Base Address Configuration Register 30h
// 
//      The Expansion ROM Base Address configuration register should not be used
// for any PCI integrated blocks.
// 
//  31           24 23           16 15            8 7             0
// .-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-.
// |0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0| CFG_12
// `-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-'
// 
#define SATA0_CFG_12_0                                     0x00000030                                                                       // R--4R
#define SATA0_CFG_12_0_SECURE                              0
#define SATA0_CFG_12_0_WORD_COUNT                          1
#define SATA0_CFG_12_0_RESET_VAL                           0x0
#define SATA0_CFG_12_0_RESET_MASK                          0x0
#define SATA0_CFG_12_0_SW_DEFAULT_VAL                      0x0
#define SATA0_CFG_12_0_SW_DEFAULT_MASK                     0x0
#define SATA0_CFG_12_0_READ_MASK                           0xffffffff
#define SATA0_CFG_12_0_WRITE_MASK                          0x0
#define SATA0_CFG_12_0_RESERVED_SHIFT                       _MK_SHIFT_CONST(0)                                                              // C--VF
#define SATA0_CFG_12_0_RESERVED_FIELD                      (_MK_SHIFT_CONST(0xffffffff) << SATA0_CFG_12_0_RESERVED_SHIFT)
#define SATA0_CFG_12_0_RESERVED_RANGE                      31:0
#define SATA0_CFG_12_0_RESERVED_WOFFSET                    0
#define SATA0_CFG_12_0_RESERVED_0                          _MK_ENUM_CONST(0x00000000)                                                       // C---V
// 
// 
// 
//                 Figure 10-12  PCI Configuration Register 30h
// 
// 
// 
// 
// .TITLE PCI Capability Pointer Register 34h
// 
// .FIELD CAP_PTR
//      The CAP_PTR bits indicate the offset into configuration space where the
// capabilities list begins. This always points to 0x44 where at least the PCI-PM
// registers are expected to reside.
// 
//  31           24 23           16 15            8 7             0
// .-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-.
// |0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0|0 1 0 0 0 1 0 0| CFG_13
// `-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-'
// 
#define SATA0_CFG_13_0                                     0x00000034                                                                       // RW-4R
#define SATA0_CFG_13_0_SECURE                              0
#define SATA0_CFG_13_0_WORD_COUNT                          1
#define SATA0_CFG_13_0_RESET_VAL                           0x0
#define SATA0_CFG_13_0_RESET_MASK                          0x0
#define SATA0_CFG_13_0_SW_DEFAULT_VAL                      0x0
#define SATA0_CFG_13_0_SW_DEFAULT_MASK                     0x0
#define SATA0_CFG_13_0_READ_MASK                           0xff
#define SATA0_CFG_13_0_WRITE_MASK                          0x0
#define SATA0_CFG_13_0_CAP_PTR_SHIFT                        _MK_SHIFT_CONST(0)                                                              // C--VF
#define SATA0_CFG_13_0_CAP_PTR_FIELD                       (_MK_SHIFT_CONST(0xff) << SATA0_CFG_13_0_CAP_PTR_SHIFT)
#define SATA0_CFG_13_0_CAP_PTR_RANGE                       7:0
#define SATA0_CFG_13_0_CAP_PTR_WOFFSET                     0
#define SATA0_CFG_13_0_CAP_PTR_PCIPM                       _MK_ENUM_CONST(0x00000044)                                                       // C---V
// 
// 
//                 Figure 10-13  PCI Configuration Register 34h
// 
// .TITLE PCI Configuration Register 38h
// 
// .FIELD RESERVED
//      The RESERVED bits are reserved for future use.
// 
//  31           24 23           16 15            8 7             0
// .-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-.
// |0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0| CFG_14
// `-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-'
// 
#define SATA0_CFG_14_0                                     0x00000038                                                                       // R--4R
#define SATA0_CFG_14_0_SECURE                              0
#define SATA0_CFG_14_0_WORD_COUNT                          1
#define SATA0_CFG_14_0_RESET_VAL                           0x0
#define SATA0_CFG_14_0_RESET_MASK                          0x0
#define SATA0_CFG_14_0_SW_DEFAULT_VAL                      0x0
#define SATA0_CFG_14_0_SW_DEFAULT_MASK                     0x0
#define SATA0_CFG_14_0_READ_MASK                           0xffffffff
#define SATA0_CFG_14_0_WRITE_MASK                          0x0
#define SATA0_CFG_14_0_RESERVED_SHIFT                       _MK_SHIFT_CONST(0)                                                              // C--VF
#define SATA0_CFG_14_0_RESERVED_FIELD                      (_MK_SHIFT_CONST(0xffffffff) << SATA0_CFG_14_0_RESERVED_SHIFT)
#define SATA0_CFG_14_0_RESERVED_RANGE                      31:0
#define SATA0_CFG_14_0_RESERVED_WOFFSET                    0
#define SATA0_CFG_14_0_RESERVED_0                          _MK_ENUM_CONST(0x00000000)                                                       // C---V
// 
// 
//                 Figure 10-14  PCI Configuration Register 38h
// 
// 
// .TITLE PCI Configuration Register 3Ch
// 
// 
// .FIELD INTR_LINE
//      The INTR_LINE bits contain the interrupt routing information.  The
// register is read/write and must be implemented by any device (or device
// function) that uses an interrupt pin.  POST software will write the routing
// information into this register as it initializes and configures the system.
// The value in this register tells which input of the system interrupt
// controller(s) the device's interrupt pin is connected to.  Device drivers and
// operating systems can use this information to determine priority and vector
// information.  INTR_LINE is initialized to 0xff (no connection) at reset.  Some
// PCI BIOS' can't handle aliased INTR_LINEs. If T_SATA0_CFG_2_PRI_OP_MODE or
// T_SATA0_CFG_2_SEC_OP_MODE are set, this register will read whatever value
// written by software. If both the bits are cleared the register will always
// return 00h
// .FIELD INTR_PIN
//      The INTR_PIN bits contain the interrupt pin the device (or device
// function) uses.  A value of 1 corresponds to INTA#.  A value of 2 corresponds
// to INTB#.  A value of 3 corresponds to INTC#.  A value of 4 corresponds to
// INTD#.  Devices (or device functions) that don't use an interrupt pin must put
// a 0 in this register.
// 
// .LABEL PRIVATE
// /* ====================================================
// This register is read-only and returns 00h if both
// T_SATA0_CFG_2_PRI_OP_MODE and T_SATA_CFG_2_SEC_OP_MODE bits are
// cleared. If either of the bits are set, this register will return 1
//  ==================================================== */
// 
//  Due to an ECO, the INTR_PIN now returns the value of T_SATA0_CFG_43_FORCE_NATIVE
//  by default.
// .LABEL PCI_CONFIG
// 
// .FIELD MIN_GNT
//      The MIN_GNT bits contain the length of the burst period a device needs
// assuming a clock rate of 33 MHz.  This read-only register is used to specify
// the device's desired settings for Latency Timer values.  The value specifies a
// period of time in units of 1/4 microsecond.  Values of 0 indicate that the
// device has no major requirements for the settings of Latency Timers.  MIN_GNT
// is nonzero.
// .FIELD MAX_LAT
//      The MAX_LAT bits contain the maximum time the device requires to gain
// access to the PCI bus.  This read-only register is used to specify the
// device's desired settings for Latency Timer values.  The value specifies a
// period of time in units of 1/4 microsecond.  Values of 0 indicate that the
// device has no major requirements for the settings of Latency Timers.  MAX_LAT
// is nonzero.
// 
//      The INTR_PIN, MIN_GNT, and MAX_LAT are configurable per block.
// 
// 
//  31           24 23           16 15            8 7             0
// .-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-.
// |0 0 0 0 0 0 0 1|0 0 0 0 0 0 1 1|0 0 0 0 0 0 0 1|               | CFG_15
// `-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-'
// 
#define SATA0_CFG_15_0                                     0x0000003C                                                                       // RW-4R
#define SATA0_CFG_15_0_SECURE                              0
#define SATA0_CFG_15_0_WORD_COUNT                          1
#define SATA0_CFG_15_0_RESET_VAL                           0x0
#define SATA0_CFG_15_0_RESET_MASK                          0x0
#define SATA0_CFG_15_0_SW_DEFAULT_VAL                      0x0
#define SATA0_CFG_15_0_SW_DEFAULT_MASK                     0x0
#define SATA0_CFG_15_0_READ_MASK                           0xffffffff
#define SATA0_CFG_15_0_WRITE_MASK                          0xff
#define SATA0_CFG_15_0_INTR_LINE_SHIFT                      _MK_SHIFT_CONST(0)                                                              // RWWVF
#define SATA0_CFG_15_0_INTR_LINE_FIELD                     (_MK_SHIFT_CONST(0xff) << SATA0_CFG_15_0_INTR_LINE_SHIFT)
#define SATA0_CFG_15_0_INTR_LINE_RANGE                     7:0
#define SATA0_CFG_15_0_INTR_LINE_WOFFSET                   0
#define SATA0_CFG_15_0_INTR_LINE_DEFAULT                   (_MK_MASK_CONST(0x00000000)
#define SATA0_CFG_15_0_INTR_LINE_DEFAULT_MASK              (_MK_MASK_CONST(0xff)
#define SATA0_CFG_15_0_INTR_LINE_SW_DEFAULT                (_MK_MASK_CONST(0x00000000)
#define SATA0_CFG_15_0_INTR_LINE_SW_DEFAULT_MASK           (_MK_MASK_CONST(0xff)
#define SATA0_CFG_15_0_INTR_LINE__NOPRDCHK                 _MK_ENUM_CONST(0x00000001)                                                       // ----V
#define SATA0_CFG_15_0_INTR_LINE_IRQ0                      _MK_ENUM_CONST(0x00000000)                                                       // RWW-V
#define SATA0_CFG_15_0_INTR_LINE_IRQ1                      _MK_ENUM_CONST(0x00000001)                                                       // RW--V
#define SATA0_CFG_15_0_INTR_LINE_IRQ15                     _MK_ENUM_CONST(0x0000000F)                                                       // RW--V
#define SATA0_CFG_15_0_INTR_LINE_UNKNOWN                   _MK_ENUM_CONST(0x000000FF)                                                       // RW--V
#define SATA0_CFG_15_0_INTR_PIN_SHIFT                       _MK_SHIFT_CONST(8)                                                              // R-WVF
#define SATA0_CFG_15_0_INTR_PIN_FIELD                      (_MK_SHIFT_CONST(0xff) << SATA0_CFG_15_0_INTR_PIN_SHIFT)
#define SATA0_CFG_15_0_INTR_PIN_RANGE                      15:8
#define SATA0_CFG_15_0_INTR_PIN_WOFFSET                    0
#define SATA0_CFG_15_0_INTR_PIN_DEFAULT                    (_MK_MASK_CONST(0x00000001)
#define SATA0_CFG_15_0_INTR_PIN_DEFAULT_MASK               (_MK_MASK_CONST(0xff)
#define SATA0_CFG_15_0_INTR_PIN_SW_DEFAULT                 (_MK_MASK_CONST(0x00000001)
#define SATA0_CFG_15_0_INTR_PIN_SW_DEFAULT_MASK            (_MK_MASK_CONST(0xff)
#define SATA0_CFG_15_0_INTR_PIN_NONE                       _MK_ENUM_CONST(0x00000000)                                                       // R---V
#define SATA0_CFG_15_0_INTR_PIN_INTA                       _MK_ENUM_CONST(0x00000001)                                                       // R-W-V
#define SATA0_CFG_15_0_INTR_PIN_INTB                       _MK_ENUM_CONST(0x00000002)                                                       // ----V
#define SATA0_CFG_15_0_INTR_PIN_INTC                       _MK_ENUM_CONST(0x00000003)                                                       // ----V
#define SATA0_CFG_15_0_INTR_PIN_INTD                       _MK_ENUM_CONST(0x00000004)                                                       // ----V
#define SATA0_CFG_15_0_MIN_GNT_SHIFT                        _MK_SHIFT_CONST(16)                                                             // C--VF
#define SATA0_CFG_15_0_MIN_GNT_FIELD                       (_MK_SHIFT_CONST(0xff) << SATA0_CFG_15_0_MIN_GNT_SHIFT)
#define SATA0_CFG_15_0_MIN_GNT_RANGE                       23:16
#define SATA0_CFG_15_0_MIN_GNT_WOFFSET                     0
#define SATA0_CFG_15_0_MIN_GNT_NO_REQUIREMENTS             _MK_ENUM_CONST(0x00000000)                                                       // ----V
#define SATA0_CFG_15_0_MIN_GNT_750NS                       _MK_ENUM_CONST(0x00000003)                                                       // C---V
#define SATA0_CFG_15_0_MAX_LAT_SHIFT                        _MK_SHIFT_CONST(24)                                                             // C--VF
#define SATA0_CFG_15_0_MAX_LAT_FIELD                       (_MK_SHIFT_CONST(0xff) << SATA0_CFG_15_0_MAX_LAT_SHIFT)
#define SATA0_CFG_15_0_MAX_LAT_RANGE                       31:24
#define SATA0_CFG_15_0_MAX_LAT_WOFFSET                     0
#define SATA0_CFG_15_0_MAX_LAT_NO_REQUIREMENTS             _MK_ENUM_CONST(0x00000000)                                                       // ----V
#define SATA0_CFG_15_0_MAX_LAT_250NS                       _MK_ENUM_CONST(0x00000001)                                                       // C---V
// 
// Warning: unsupported define: #define T_SATA0_CFG_15_INTR_PIN__NO_CHECK                       0x0 /*       */
// 
// 
//                 Figure 10-15  PCI Configuration Register 3Ch
// 
// 
// 
// 
// .SUBSECTION Device Specific Configuration Registers
// 
//       The CFG_16 through CFG_63 registers are Device Specific PCI
// configuration registers.
// 
// .TITLE Write Subsystem Vendor ID and Subsystem ID register 40h
// 
// .FIELD SUBSYSTEM_VENDOR_ID
//       Subsystem Vendor ID write register. The system BIOS can set the Subsystem
//       Vendor ID value in [2Ch] by writing to this register.
// 
// .FIELD SUBSYSTEM_ID
//       Subsystem ID write register. The system BIOS can set the Subsystem
// ID value in [2Eh] by writing to this register.
// 
// .LABEL PRIVATE INT_REL
// /*      The CFG_16 register is a writable alias of the CFG_11 register.
// This allows software to modify the SUBSYSTEM_ID and SUBSYSTEM_VENDOR_ID bits
// in the case of a motherboard, where there is no ROM available for the hardware
// to read the values from. */
// .LABEL FUNC_BIOS
// 
//  31           24 23           16 15            8 7             0
// .-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-.
// |                               |                               | CFG_16
// `-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-'
// 
#define SATA0_CFG_16_0                                     0x00000040                                                                       // RW-4R
#define SATA0_CFG_16_0_SECURE                              0
#define SATA0_CFG_16_0_WORD_COUNT                          1
#define SATA0_CFG_16_0_RESET_VAL                           0x0
#define SATA0_CFG_16_0_RESET_MASK                          0x0
#define SATA0_CFG_16_0_SW_DEFAULT_VAL                      0x0
#define SATA0_CFG_16_0_SW_DEFAULT_MASK                     0x0
#define SATA0_CFG_16_0_READ_MASK                           0xffffffff
#define SATA0_CFG_16_0_WRITE_MASK                          0xffffffff
#define SATA0_CFG_16_0_SUBSYSTEM_VENDOR_ID_SHIFT            _MK_SHIFT_CONST(0)                                                              // RWWVF
#define SATA0_CFG_16_0_SUBSYSTEM_VENDOR_ID_FIELD           (_MK_SHIFT_CONST(0xffff) << SATA0_CFG_16_0_SUBSYSTEM_VENDOR_ID_SHIFT)
#define SATA0_CFG_16_0_SUBSYSTEM_VENDOR_ID_RANGE           15:0
#define SATA0_CFG_16_0_SUBSYSTEM_VENDOR_ID_WOFFSET         0
#define SATA0_CFG_16_0_SUBSYSTEM_VENDOR_ID_DEFAULT         (_MK_MASK_CONST(0x00000000)
#define SATA0_CFG_16_0_SUBSYSTEM_VENDOR_ID_DEFAULT_MASK    (_MK_MASK_CONST(0xffff)
#define SATA0_CFG_16_0_SUBSYSTEM_VENDOR_ID_SW_DEFAULT      (_MK_MASK_CONST(0x00000000)
#define SATA0_CFG_16_0_SUBSYSTEM_VENDOR_ID_SW_DEFAULT_MASK (_MK_MASK_CONST(0xffff)
#define SATA0_CFG_16_0_SUBSYSTEM_VENDOR_ID__NOPRDCHK       _MK_ENUM_CONST(0x00000001)                                                       // ----V
#define SATA0_CFG_16_0_SUBSYSTEM_VENDOR_ID_NONE            _MK_ENUM_CONST(0x00000000)                                                       // R-W-V
#define SATA0_CFG_16_0_SUBSYSTEM_ID_SHIFT                   _MK_SHIFT_CONST(16)                                                             // RWWVF
#define SATA0_CFG_16_0_SUBSYSTEM_ID_FIELD                  (_MK_SHIFT_CONST(0xffff) << SATA0_CFG_16_0_SUBSYSTEM_ID_SHIFT)
#define SATA0_CFG_16_0_SUBSYSTEM_ID_RANGE                  31:16
#define SATA0_CFG_16_0_SUBSYSTEM_ID_WOFFSET                0
#define SATA0_CFG_16_0_SUBSYSTEM_ID_DEFAULT                (_MK_MASK_CONST(0x00000000)
#define SATA0_CFG_16_0_SUBSYSTEM_ID_DEFAULT_MASK           (_MK_MASK_CONST(0xffff)
#define SATA0_CFG_16_0_SUBSYSTEM_ID_SW_DEFAULT             (_MK_MASK_CONST(0x00000000)
#define SATA0_CFG_16_0_SUBSYSTEM_ID_SW_DEFAULT_MASK        (_MK_MASK_CONST(0xffff)
#define SATA0_CFG_16_0_SUBSYSTEM_ID__NOPRDCHK              _MK_ENUM_CONST(0x00000001)                                                       // ----V
#define SATA0_CFG_16_0_SUBSYSTEM_ID_NONE                   _MK_ENUM_CONST(0x00000000)                                                       // R-W-V
// 
// 
//                 Figure 10-16  PCI Configuration Register 40h
// 
//      The CFG_17 through CFG_18 registers are for PCI Power Management
// operation. The ROM Based Power Data is not supported.
// 
// .TITLE PCI Power Management Capabilities Register 44h
// 
// The CFG_17 register is the Capabilities Identification information register
// for the PCI PM functionality.  NEXT_PTR is a byte offset which points to the
// next item in the capabilities list.  CAP_ID indicates
// this capability's record type.
// 
//  31           24 23           16 15            8 7             0
// .-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-.
// |0 0 0 0 0 0 0|0 0 0|0 0 0|0 1 0|0 0 0 0 0 0 0 0|0 0 0 0 0 0 0 1| CFG_17
// +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
// 
#define SATA0_CFG_17_0                                     0x00000044                                                                       // RW-4R
#define SATA0_CFG_17_0_SECURE                              0
#define SATA0_CFG_17_0_WORD_COUNT                          1
#define SATA0_CFG_17_0_RESET_VAL                           0x0
#define SATA0_CFG_17_0_RESET_MASK                          0x0
#define SATA0_CFG_17_0_SW_DEFAULT_VAL                      0x0
#define SATA0_CFG_17_0_SW_DEFAULT_MASK                     0x0
#define SATA0_CFG_17_0_READ_MASK                           0xffefffff
#define SATA0_CFG_17_0_WRITE_MASK                          0x0
#define SATA0_CFG_17_0_PME_SUPPORT_D3C_SHIFT                _MK_SHIFT_CONST(31)                                                             // C--VF
#define SATA0_CFG_17_0_PME_SUPPORT_D3C_FIELD               (_MK_SHIFT_CONST(0x1) << SATA0_CFG_17_0_PME_SUPPORT_D3C_SHIFT)
#define SATA0_CFG_17_0_PME_SUPPORT_D3C_RANGE               31:31
#define SATA0_CFG_17_0_PME_SUPPORT_D3C_WOFFSET             0
#define SATA0_CFG_17_0_PME_SUPPORT_D3C_YES                 _MK_ENUM_CONST(0x00000001)                                                       // ----V
#define SATA0_CFG_17_0_PME_SUPPORT_D3C_NO                  _MK_ENUM_CONST(0x00000000)                                                       // C---V
#define SATA0_CFG_17_0_PME_SUPPORT_D3H_SHIFT                _MK_SHIFT_CONST(30)                                                             // C--VF
#define SATA0_CFG_17_0_PME_SUPPORT_D3H_FIELD               (_MK_SHIFT_CONST(0x1) << SATA0_CFG_17_0_PME_SUPPORT_D3H_SHIFT)
#define SATA0_CFG_17_0_PME_SUPPORT_D3H_RANGE               30:30
#define SATA0_CFG_17_0_PME_SUPPORT_D3H_WOFFSET             0
#define SATA0_CFG_17_0_PME_SUPPORT_D3H_YES                 _MK_ENUM_CONST(0x00000001)                                                       // ----V
#define SATA0_CFG_17_0_PME_SUPPORT_D3H_NO                  _MK_ENUM_CONST(0x00000000)                                                       // C---V
#define SATA0_CFG_17_0_PME_SUPPORT_D2_SHIFT                 _MK_SHIFT_CONST(29)                                                             // C--VF
#define SATA0_CFG_17_0_PME_SUPPORT_D2_FIELD                (_MK_SHIFT_CONST(0x1) << SATA0_CFG_17_0_PME_SUPPORT_D2_SHIFT)
#define SATA0_CFG_17_0_PME_SUPPORT_D2_RANGE                29:29
#define SATA0_CFG_17_0_PME_SUPPORT_D2_WOFFSET              0
#define SATA0_CFG_17_0_PME_SUPPORT_D2_YES                  _MK_ENUM_CONST(0x00000001)                                                       // ----V
#define SATA0_CFG_17_0_PME_SUPPORT_D2_NO                   _MK_ENUM_CONST(0x00000000)                                                       // C---V
#define SATA0_CFG_17_0_PME_SUPPORT_D1_SHIFT                 _MK_SHIFT_CONST(28)                                                             // C--VF
#define SATA0_CFG_17_0_PME_SUPPORT_D1_FIELD                (_MK_SHIFT_CONST(0x1) << SATA0_CFG_17_0_PME_SUPPORT_D1_SHIFT)
#define SATA0_CFG_17_0_PME_SUPPORT_D1_RANGE                28:28
#define SATA0_CFG_17_0_PME_SUPPORT_D1_WOFFSET              0
#define SATA0_CFG_17_0_PME_SUPPORT_D1_YES                  _MK_ENUM_CONST(0x00000001)                                                       // ----V
#define SATA0_CFG_17_0_PME_SUPPORT_D1_NO                   _MK_ENUM_CONST(0x00000000)                                                       // C---V
#define SATA0_CFG_17_0_PME_SUPPORT_D0_SHIFT                 _MK_SHIFT_CONST(27)                                                             // C--VF
#define SATA0_CFG_17_0_PME_SUPPORT_D0_FIELD                (_MK_SHIFT_CONST(0x1) << SATA0_CFG_17_0_PME_SUPPORT_D0_SHIFT)
#define SATA0_CFG_17_0_PME_SUPPORT_D0_RANGE                27:27
#define SATA0_CFG_17_0_PME_SUPPORT_D0_WOFFSET              0
#define SATA0_CFG_17_0_PME_SUPPORT_D0_YES                  _MK_ENUM_CONST(0x00000001)                                                       // ----V
#define SATA0_CFG_17_0_PME_SUPPORT_D0_NO                   _MK_ENUM_CONST(0x00000000)                                                       // C---V
#define SATA0_CFG_17_0_D2_SUPPORT_SHIFT                     _MK_SHIFT_CONST(26)                                                             // C--VF
#define SATA0_CFG_17_0_D2_SUPPORT_FIELD                    (_MK_SHIFT_CONST(0x1) << SATA0_CFG_17_0_D2_SUPPORT_SHIFT)
#define SATA0_CFG_17_0_D2_SUPPORT_RANGE                    26:26
#define SATA0_CFG_17_0_D2_SUPPORT_WOFFSET                  0
#define SATA0_CFG_17_0_D2_SUPPORT_YES                      _MK_ENUM_CONST(0x00000001)                                                       // ----V
#define SATA0_CFG_17_0_D2_SUPPORT_NO                       _MK_ENUM_CONST(0x00000000)                                                       // C---V
#define SATA0_CFG_17_0_D1_SUPPORT_SHIFT                     _MK_SHIFT_CONST(25)                                                             // C--VF
#define SATA0_CFG_17_0_D1_SUPPORT_FIELD                    (_MK_SHIFT_CONST(0x1) << SATA0_CFG_17_0_D1_SUPPORT_SHIFT)
#define SATA0_CFG_17_0_D1_SUPPORT_RANGE                    25:25
#define SATA0_CFG_17_0_D1_SUPPORT_WOFFSET                  0
#define SATA0_CFG_17_0_D1_SUPPORT_YES                      _MK_ENUM_CONST(0x00000001)                                                       // ----V
#define SATA0_CFG_17_0_D1_SUPPORT_NO                       _MK_ENUM_CONST(0x00000000)                                                       // C---V
#define SATA0_CFG_17_0_AUX_CURRENT_SHIFT                    _MK_SHIFT_CONST(22)                                                             // C--VF
#define SATA0_CFG_17_0_AUX_CURRENT_FIELD                   (_MK_SHIFT_CONST(0x7) << SATA0_CFG_17_0_AUX_CURRENT_SHIFT)
#define SATA0_CFG_17_0_AUX_CURRENT_RANGE                   24:22
#define SATA0_CFG_17_0_AUX_CURRENT_WOFFSET                 0
#define SATA0_CFG_17_0_AUX_CURRENT_0                       _MK_ENUM_CONST(0x00000000)                                                       // C---V
#define SATA0_CFG_17_0_AUX_CURRENT_55MA                    _MK_ENUM_CONST(0x00000001)                                                       // ----V
#define SATA0_CFG_17_0_AUX_CURRENT_100MA                   _MK_ENUM_CONST(0x00000002)                                                       // ----V
#define SATA0_CFG_17_0_AUX_CURRENT_160MA                   _MK_ENUM_CONST(0x00000003)                                                       // ----V
#define SATA0_CFG_17_0_AUX_CURRENT_220MA                   _MK_ENUM_CONST(0x00000004)                                                       // ----V
#define SATA0_CFG_17_0_AUX_CURRENT_270MA                   _MK_ENUM_CONST(0x00000005)                                                       // ----V
#define SATA0_CFG_17_0_AUX_CURRENT_320MA                   _MK_ENUM_CONST(0x00000006)                                                       // ----V
#define SATA0_CFG_17_0_AUX_CURRENT_375MA                   _MK_ENUM_CONST(0x00000007)                                                       // ----V
#define SATA0_CFG_17_0_DEV_SPEC_INIT_SHIFT                  _MK_SHIFT_CONST(21)                                                             // C--VF
#define SATA0_CFG_17_0_DEV_SPEC_INIT_FIELD                 (_MK_SHIFT_CONST(0x1) << SATA0_CFG_17_0_DEV_SPEC_INIT_SHIFT)
#define SATA0_CFG_17_0_DEV_SPEC_INIT_RANGE                 21:21
#define SATA0_CFG_17_0_DEV_SPEC_INIT_WOFFSET               0
#define SATA0_CFG_17_0_DEV_SPEC_INIT_NOT_NEEDED            _MK_ENUM_CONST(0x00000000)                                                       // C---V
#define SATA0_CFG_17_0_DEV_SPEC_INIT_NEEDED                _MK_ENUM_CONST(0x00000001)                                                       // ----V
#define SATA0_CFG_17_0_PME_CLOCK_SHIFT                      _MK_SHIFT_CONST(19)                                                             // C--VF
#define SATA0_CFG_17_0_PME_CLOCK_FIELD                     (_MK_SHIFT_CONST(0x1) << SATA0_CFG_17_0_PME_CLOCK_SHIFT)
#define SATA0_CFG_17_0_PME_CLOCK_RANGE                     19:19
#define SATA0_CFG_17_0_PME_CLOCK_WOFFSET                   0
#define SATA0_CFG_17_0_PME_CLOCK_NOT_NEEDED                _MK_ENUM_CONST(0x00000000)                                                       // C---V
#define SATA0_CFG_17_0_PME_CLOCK_NEEDED                    _MK_ENUM_CONST(0x00000001)                                                       // ----V
#define SATA0_CFG_17_0_PCIPM_REV_SHIFT                      _MK_SHIFT_CONST(16)                                                             // C--VF
#define SATA0_CFG_17_0_PCIPM_REV_FIELD                     (_MK_SHIFT_CONST(0x7) << SATA0_CFG_17_0_PCIPM_REV_SHIFT)
#define SATA0_CFG_17_0_PCIPM_REV_RANGE                     18:16
#define SATA0_CFG_17_0_PCIPM_REV_WOFFSET                   0
#define SATA0_CFG_17_0_PCIPM_REV_11                        _MK_ENUM_CONST(0x00000002)                                                       // C---V
#define SATA0_CFG_17_0_NEXT_PTR_SHIFT                       _MK_SHIFT_CONST(8)                                                              // R-CVF
#define SATA0_CFG_17_0_NEXT_PTR_FIELD                      (_MK_SHIFT_CONST(0xff) << SATA0_CFG_17_0_NEXT_PTR_SHIFT)
#define SATA0_CFG_17_0_NEXT_PTR_RANGE                      15:8
#define SATA0_CFG_17_0_NEXT_PTR_WOFFSET                    0
#define SATA0_CFG_17_0_NEXT_PTR_MSI                        _MK_ENUM_CONST(0x000000B0)                                                       // R---V
#define SATA0_CFG_17_0_NEXT_PTR_MSIX                       _MK_ENUM_CONST(0x000000C4)                                                       // R---V
#define SATA0_CFG_17_0_NEXT_PTR_SATA                       _MK_ENUM_CONST(0x0000008C)                                                       // R-C-V
#define SATA0_CFG_17_0_NEXT_PTR_NULL                       _MK_ENUM_CONST(0x00000000)                                                       // R---V
#define SATA0_CFG_17_0_CAP_ID_SHIFT                         _MK_SHIFT_CONST(0)                                                              // C--VF
#define SATA0_CFG_17_0_CAP_ID_FIELD                        (_MK_SHIFT_CONST(0xff) << SATA0_CFG_17_0_CAP_ID_SHIFT)
#define SATA0_CFG_17_0_CAP_ID_RANGE                        7:0
#define SATA0_CFG_17_0_CAP_ID_WOFFSET                      0
#define SATA0_CFG_17_0_CAP_ID_PM                           _MK_ENUM_CONST(0x00000001)                                                       // C---V
// 
// 
// 
//                 Figure 10-17  PCI Configuration Register 44h
// 
// .TITLE PCI Power Management Control/Status Register 48h
// 
// 
// .FIELD PME_STATUS
// PME Status : The SATA function does not support PME generation.
// .FIELD PME
// PME Enable : The SATA function does not support PME generation.
// .FIELD PM_STATE
// Power State : This is used to determine the current power state.
// Software updates this register when changing power states.
// 00b = D0, 01b = D1, 10b = D2, 11b = D3hot.
// 
//  31           24 23           16 15            8 7             0
// .-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-.
// |0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0| |0 0 0 0 0 0| |0 0 0 0 0 0|   | CFG_18
// +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
// 
#define SATA0_CFG_18_0                                     0x00000048                                                                       // RW-4R
#define SATA0_CFG_18_0_SECURE                              0
#define SATA0_CFG_18_0_WORD_COUNT                          1
#define SATA0_CFG_18_0_RESET_VAL                           0x0
#define SATA0_CFG_18_0_RESET_MASK                          0x0
#define SATA0_CFG_18_0_SW_DEFAULT_VAL                      0x0
#define SATA0_CFG_18_0_SW_DEFAULT_MASK                     0x0
#define SATA0_CFG_18_0_READ_MASK                           0x8103
#define SATA0_CFG_18_0_WRITE_MASK                          0x3
#define SATA0_CFG_18_0_PME_STATUS_SHIFT                     _MK_SHIFT_CONST(15)                                                             // C--VF
#define SATA0_CFG_18_0_PME_STATUS_FIELD                    (_MK_SHIFT_CONST(0x1) << SATA0_CFG_18_0_PME_STATUS_SHIFT)
#define SATA0_CFG_18_0_PME_STATUS_RANGE                    15:15
#define SATA0_CFG_18_0_PME_STATUS_WOFFSET                  0
#define SATA0_CFG_18_0_PME_STATUS_NOT_ACTIVE               _MK_ENUM_CONST(0x00000000)                                                       // C---V
#define SATA0_CFG_18_0_PME_SHIFT                            _MK_SHIFT_CONST(8)                                                              // C--VF
#define SATA0_CFG_18_0_PME_FIELD                           (_MK_SHIFT_CONST(0x1) << SATA0_CFG_18_0_PME_SHIFT)
#define SATA0_CFG_18_0_PME_RANGE                           8:8
#define SATA0_CFG_18_0_PME_WOFFSET                         0
#define SATA0_CFG_18_0_PME_DISABLE                         _MK_ENUM_CONST(0x00000000)                                                       // C---V
#define SATA0_CFG_18_0_PM_STATE_SHIFT                       _MK_SHIFT_CONST(0)                                                              // RWWVF
#define SATA0_CFG_18_0_PM_STATE_FIELD                      (_MK_SHIFT_CONST(0x3) << SATA0_CFG_18_0_PM_STATE_SHIFT)
#define SATA0_CFG_18_0_PM_STATE_RANGE                      1:0
#define SATA0_CFG_18_0_PM_STATE_WOFFSET                    0
#define SATA0_CFG_18_0_PM_STATE_DEFAULT                    (_MK_MASK_CONST(0x00000000)
#define SATA0_CFG_18_0_PM_STATE_DEFAULT_MASK               (_MK_MASK_CONST(0x3)
#define SATA0_CFG_18_0_PM_STATE_SW_DEFAULT                 (_MK_MASK_CONST(0x00000000)
#define SATA0_CFG_18_0_PM_STATE_SW_DEFAULT_MASK            (_MK_MASK_CONST(0x3)
#define SATA0_CFG_18_0_PM_STATE_D0                         _MK_ENUM_CONST(0x00000000)                                                       // RWW-V
#define SATA0_CFG_18_0_PM_STATE_D3                         _MK_ENUM_CONST(0x00000003)                                                       // RW--V
// 
// 
//                 Figure 10-18  PCI Configuration Register 48h
// 
// .LABEL PRIVATE
// .TITLE FPCI_DBG_0
// .FIELD SEL - to select different parts of debug bus
//  31           24 23           16 15            8 7             0
// .-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-.
// |0 0 0 0 0 0 0 0|                                               | FPCI_DBG_0
// +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
#define SATA0_FPCI_DBG_0_0                                 0x0000004C                                                                       // RW-4R
#define SATA0_FPCI_DBG_0_0_SECURE                          0
#define SATA0_FPCI_DBG_0_0_WORD_COUNT                      1
#define SATA0_FPCI_DBG_0_0_RESET_VAL                       0x0
#define SATA0_FPCI_DBG_0_0_RESET_MASK                      0x0
#define SATA0_FPCI_DBG_0_0_SW_DEFAULT_VAL                  0x0
#define SATA0_FPCI_DBG_0_0_SW_DEFAULT_MASK                 0x0
#define SATA0_FPCI_DBG_0_0_READ_MASK                       0xffffffff
#define SATA0_FPCI_DBG_0_0_WRITE_MASK                      0xffffffff
#define SATA0_FPCI_DBG_0_0_SEL_SHIFT                        _MK_SHIFT_CONST(0)                                                              // RWWVF
#define SATA0_FPCI_DBG_0_0_SEL_FIELD                       (_MK_SHIFT_CONST(0xffffffff) << SATA0_FPCI_DBG_0_0_SEL_SHIFT)
#define SATA0_FPCI_DBG_0_0_SEL_RANGE                       31:0
#define SATA0_FPCI_DBG_0_0_SEL_WOFFSET                     0
#define SATA0_FPCI_DBG_0_0_SEL_DEFAULT                     (_MK_MASK_CONST(0x00000000)
#define SATA0_FPCI_DBG_0_0_SEL_DEFAULT_MASK                (_MK_MASK_CONST(0xffffffff)
#define SATA0_FPCI_DBG_0_0_SEL_SW_DEFAULT                  (_MK_MASK_CONST(0x00000000)
#define SATA0_FPCI_DBG_0_0_SEL_SW_DEFAULT_MASK             (_MK_MASK_CONST(0xffffffff)
// 
// .LABEL PUBLIC
// 
// .LABEL PRIVATE
// .TITLE FPCI_DBG_1
// .FIELD SEL - to select different parts of debug bus
//  31           24 23           16 15            8 7             0
// .-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-.
// |0 0 0 0 0 0 0 0|                                               | FPCI_DBG_1
// +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
#define SATA0_FPCI_DBG_1_0                                 0x00000050                                                                       // RW-4R
#define SATA0_FPCI_DBG_1_0_SECURE                          0
#define SATA0_FPCI_DBG_1_0_WORD_COUNT                      1
#define SATA0_FPCI_DBG_1_0_RESET_VAL                       0x0
#define SATA0_FPCI_DBG_1_0_RESET_MASK                      0x0
#define SATA0_FPCI_DBG_1_0_SW_DEFAULT_VAL                  0x0
#define SATA0_FPCI_DBG_1_0_SW_DEFAULT_MASK                 0x0
#define SATA0_FPCI_DBG_1_0_READ_MASK                       0xffffffff
#define SATA0_FPCI_DBG_1_0_WRITE_MASK                      0xffffffff
#define SATA0_FPCI_DBG_1_0_SEL_SHIFT                        _MK_SHIFT_CONST(0)                                                              // RWWVF
#define SATA0_FPCI_DBG_1_0_SEL_FIELD                       (_MK_SHIFT_CONST(0xffffffff) << SATA0_FPCI_DBG_1_0_SEL_SHIFT)
#define SATA0_FPCI_DBG_1_0_SEL_RANGE                       31:0
#define SATA0_FPCI_DBG_1_0_SEL_WOFFSET                     0
#define SATA0_FPCI_DBG_1_0_SEL_DEFAULT                     (_MK_MASK_CONST(0x00000000)
#define SATA0_FPCI_DBG_1_0_SEL_DEFAULT_MASK                (_MK_MASK_CONST(0xffffffff)
#define SATA0_FPCI_DBG_1_0_SEL_SW_DEFAULT                  (_MK_MASK_CONST(0x00000000)
#define SATA0_FPCI_DBG_1_0_SEL_SW_DEFAULT_MASK             (_MK_MASK_CONST(0xffffffff)
// 
// .LABEL PUBLIC
// 
// .LABEL PRIVATE INT_REL
// .TITLE FPCI_SW
// .FIELD IDDQ_PG
// SW writes this bit to one/ zero when Power Gated which drives the IDDQ to the pads
// Single bit is used to drive all port's IDDQ
// .LABEL PRIVATE INT_REL
// .FIELD WAKEUP_PLL
// When the dev_clk PLL is shutdown, this field is written to one by SW to wakeup the PLL before issuing any other write
// 
//  31           24 23           16 15            8 7             0
// .-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-.
// |0 0 0 0 0 0 0 0|                                               | FPCI_SW
// +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
// .LABEL PRIVATE INT_REL
#define SATA0_FPCI_SW_0                                    0x00000054                                                                       // RW-4R
#define SATA0_FPCI_SW_0_SECURE                             0
#define SATA0_FPCI_SW_0_WORD_COUNT                         1
#define SATA0_FPCI_SW_0_RESET_VAL                          0x0
#define SATA0_FPCI_SW_0_RESET_MASK                         0x0
#define SATA0_FPCI_SW_0_SW_DEFAULT_VAL                     0x0
#define SATA0_FPCI_SW_0_SW_DEFAULT_MASK                    0x0
#define SATA0_FPCI_SW_0_READ_MASK                          0xffffffff
#define SATA0_FPCI_SW_0_WRITE_MASK                         0x101
#define SATA0_FPCI_SW_0_IDDQ_PG_SHIFT                       _MK_SHIFT_CONST(0)                                                              // RWWVF
#define SATA0_FPCI_SW_0_IDDQ_PG_FIELD                      (_MK_SHIFT_CONST(0x1) << SATA0_FPCI_SW_0_IDDQ_PG_SHIFT)
#define SATA0_FPCI_SW_0_IDDQ_PG_RANGE                      0:0
#define SATA0_FPCI_SW_0_IDDQ_PG_WOFFSET                    0
#define SATA0_FPCI_SW_0_IDDQ_PG_DEFAULT                    (_MK_MASK_CONST(0x00000000)
#define SATA0_FPCI_SW_0_IDDQ_PG_DEFAULT_MASK               (_MK_MASK_CONST(0x1)
#define SATA0_FPCI_SW_0_IDDQ_PG_SW_DEFAULT                 (_MK_MASK_CONST(0x00000000)
#define SATA0_FPCI_SW_0_IDDQ_PG_SW_DEFAULT_MASK            (_MK_MASK_CONST(0x1)
#define SATA0_FPCI_SW_0_IDDQ_PG_INIT                       _MK_ENUM_CONST(0x00000000)                                                       // RWW-V
#define SATA0_FPCI_SW_0_RSVD_1_7_SHIFT                      _MK_SHIFT_CONST(1)                                                              // C--VF
#define SATA0_FPCI_SW_0_RSVD_1_7_FIELD                     (_MK_SHIFT_CONST(0x7f) << SATA0_FPCI_SW_0_RSVD_1_7_SHIFT)
#define SATA0_FPCI_SW_0_RSVD_1_7_RANGE                     7:1
#define SATA0_FPCI_SW_0_RSVD_1_7_WOFFSET                   0
#define SATA0_FPCI_SW_0_RSVD_1_7_VAL                       _MK_ENUM_CONST(0x00000000)                                                       // C---V
#define SATA0_FPCI_SW_0_WAKEUP_PLL_SHIFT                    _MK_SHIFT_CONST(8)                                                              // RWWVF
#define SATA0_FPCI_SW_0_WAKEUP_PLL_FIELD                   (_MK_SHIFT_CONST(0x1) << SATA0_FPCI_SW_0_WAKEUP_PLL_SHIFT)
#define SATA0_FPCI_SW_0_WAKEUP_PLL_RANGE                   8:8
#define SATA0_FPCI_SW_0_WAKEUP_PLL_WOFFSET                 0
#define SATA0_FPCI_SW_0_WAKEUP_PLL_DEFAULT                 (_MK_MASK_CONST(0x00000000)
#define SATA0_FPCI_SW_0_WAKEUP_PLL_DEFAULT_MASK            (_MK_MASK_CONST(0x1)
#define SATA0_FPCI_SW_0_WAKEUP_PLL_SW_DEFAULT              (_MK_MASK_CONST(0x00000000)
#define SATA0_FPCI_SW_0_WAKEUP_PLL_SW_DEFAULT_MASK         (_MK_MASK_CONST(0x1)
#define SATA0_FPCI_SW_0_WAKEUP_PLL_INIT                    _MK_ENUM_CONST(0x00000000)                                                       // RWW-V
#define SATA0_FPCI_SW_0_RSVD_9_31_SHIFT                     _MK_SHIFT_CONST(9)                                                              // C--VF
#define SATA0_FPCI_SW_0_RSVD_9_31_FIELD                    (_MK_SHIFT_CONST(0x7fffff) << SATA0_FPCI_SW_0_RSVD_9_31_SHIFT)
#define SATA0_FPCI_SW_0_RSVD_9_31_RANGE                    31:9
#define SATA0_FPCI_SW_0_RSVD_9_31_WOFFSET                  0
#define SATA0_FPCI_SW_0_RSVD_9_31_VAL                      _MK_ENUM_CONST(0x00000000)                                                       // C---V
// .LABEL PRIVATE INT_REL
// 
// .LABEL PUBLIC
// 
// .LABEL PCI_CONFIG
// 
// .LABEL PUBLIC
// .LABEL FUNC_BIOS
// 
// .TITLE Serial ATA Capability Register 0
// 
// This is Serial ATA Capability register 0 as defined in AHCI rev 1.1 spec.
// 
// 31           24 23           16 15            8 7             0
// .-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-.
// |                                                               | ATACAP0
// +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
#define SATA0_ATACAP0_0                                    0x0000008C                                                                       // R--4R
#define SATA0_ATACAP0_0_SECURE                             0
#define SATA0_ATACAP0_0_WORD_COUNT                         1
#define SATA0_ATACAP0_0_RESET_VAL                          0x0
#define SATA0_ATACAP0_0_RESET_MASK                         0x0
#define SATA0_ATACAP0_0_SW_DEFAULT_VAL                     0x0
#define SATA0_ATACAP0_0_SW_DEFAULT_MASK                    0x0
#define SATA0_ATACAP0_0_READ_MASK                          0xffffffff
#define SATA0_ATACAP0_0_WRITE_MASK                         0x0
#define SATA0_ATACAP0_0_RESERVED_SHIFT                      _MK_SHIFT_CONST(24)                                                             // C---F
#define SATA0_ATACAP0_0_RESERVED_FIELD                     (_MK_SHIFT_CONST(0xff) << SATA0_ATACAP0_0_RESERVED_SHIFT)
#define SATA0_ATACAP0_0_RESERVED_RANGE                     31:24
#define SATA0_ATACAP0_0_RESERVED_WOFFSET                   0
#define SATA0_ATACAP0_0_RESERVED_0                         _MK_ENUM_CONST(0x00000000)                                                       // C---V
#define SATA0_ATACAP0_0_MAJREV_SHIFT                        _MK_SHIFT_CONST(20)                                                             // C---F
#define SATA0_ATACAP0_0_MAJREV_FIELD                       (_MK_SHIFT_CONST(0xf) << SATA0_ATACAP0_0_MAJREV_SHIFT)
#define SATA0_ATACAP0_0_MAJREV_RANGE                       23:20
#define SATA0_ATACAP0_0_MAJREV_WOFFSET                     0
#define SATA0_ATACAP0_0_MAJREV_INIT                        _MK_ENUM_CONST(0x00000001)                                                       // C---V
#define SATA0_ATACAP0_0_MINREV_SHIFT                        _MK_SHIFT_CONST(16)                                                             // C---F
#define SATA0_ATACAP0_0_MINREV_FIELD                       (_MK_SHIFT_CONST(0xf) << SATA0_ATACAP0_0_MINREV_SHIFT)
#define SATA0_ATACAP0_0_MINREV_RANGE                       19:16
#define SATA0_ATACAP0_0_MINREV_WOFFSET                     0
#define SATA0_ATACAP0_0_MINREV_INIT                        _MK_ENUM_CONST(0x00000000)                                                       // C---V
#define SATA0_ATACAP0_0_NEXT_SHIFT                          _MK_SHIFT_CONST(8)                                                              // R-CVF
#define SATA0_ATACAP0_0_NEXT_FIELD                         (_MK_SHIFT_CONST(0xff) << SATA0_ATACAP0_0_NEXT_SHIFT)
#define SATA0_ATACAP0_0_NEXT_RANGE                         15:8
#define SATA0_ATACAP0_0_NEXT_WOFFSET                       0
#define SATA0_ATACAP0_0_NEXT_MSI                           _MK_ENUM_CONST(0x000000B0)                                                       // R-C-V
#define SATA0_ATACAP0_0_NEXT_MSIX                          _MK_ENUM_CONST(0x000000C4)                                                       // R---V
#define SATA0_ATACAP0_0_NEXT_NULL                          _MK_ENUM_CONST(0x00000000)                                                       // R---V
#define SATA0_ATACAP0_0_CID_SHIFT                           _MK_SHIFT_CONST(0)                                                              // C---F
#define SATA0_ATACAP0_0_CID_FIELD                          (_MK_SHIFT_CONST(0xff) << SATA0_ATACAP0_0_CID_SHIFT)
#define SATA0_ATACAP0_0_CID_RANGE                          7:0
#define SATA0_ATACAP0_0_CID_WOFFSET                        0
#define SATA0_ATACAP0_0_CID_SATA                           _MK_ENUM_CONST(0x00000012)                                                       // C---V
// 
// 
// 
// 
// .LABEL PRIVATE INT_REL
// .LABEL FUNC_BIOS
// 
// 
// .LABEL PUBLIC
// 
// .LABEL PUBLIC
// .TITLE Serial ATA Capability Register 1
// 
// This is Serial ATA Capability register 1 as defined in AHCI rev 1.1 spec.
// 
// 31           24 23           16 15            8 7             0
// .-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-.
// |                                                               | ATACAP1
// +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
#define SATA0_ATACAP1_0                                    0x00000090                                                                       // R--4R
#define SATA0_ATACAP1_0_SECURE                             0
#define SATA0_ATACAP1_0_WORD_COUNT                         1
#define SATA0_ATACAP1_0_RESET_VAL                          0x0
#define SATA0_ATACAP1_0_RESET_MASK                         0x0
#define SATA0_ATACAP1_0_SW_DEFAULT_VAL                     0x0
#define SATA0_ATACAP1_0_SW_DEFAULT_MASK                    0x0
#define SATA0_ATACAP1_0_READ_MASK                          0xffffffff
#define SATA0_ATACAP1_0_WRITE_MASK                         0x0
#define SATA0_ATACAP1_0_RESERVED_SHIFT                      _MK_SHIFT_CONST(16)                                                             // C---F
#define SATA0_ATACAP1_0_RESERVED_FIELD                     (_MK_SHIFT_CONST(0xffff) << SATA0_ATACAP1_0_RESERVED_SHIFT)
#define SATA0_ATACAP1_0_RESERVED_RANGE                     31:16
#define SATA0_ATACAP1_0_RESERVED_WOFFSET                   0
#define SATA0_ATACAP1_0_RESERVED_0                         _MK_ENUM_CONST(0x00000000)                                                       // C---V
#define SATA0_ATACAP1_0_BAROFST_SHIFT                       _MK_SHIFT_CONST(4)                                                              // C---F
#define SATA0_ATACAP1_0_BAROFST_FIELD                      (_MK_SHIFT_CONST(0xfff) << SATA0_ATACAP1_0_BAROFST_SHIFT)
#define SATA0_ATACAP1_0_BAROFST_RANGE                      15:4
#define SATA0_ATACAP1_0_BAROFST_WOFFSET                    0
#define SATA0_ATACAP1_0_BAROFST_94H                        _MK_ENUM_CONST(0x00000025)                                                       // C---V
#define SATA0_ATACAP1_0_BARLOC_SHIFT                        _MK_SHIFT_CONST(0)                                                              // C---F
#define SATA0_ATACAP1_0_BARLOC_FIELD                       (_MK_SHIFT_CONST(0xf) << SATA0_ATACAP1_0_BARLOC_SHIFT)
#define SATA0_ATACAP1_0_BARLOC_RANGE                       3:0
#define SATA0_ATACAP1_0_BARLOC_WOFFSET                     0
#define SATA0_ATACAP1_0_BARLOC_CFG                         _MK_ENUM_CONST(0x0000000F)                                                       // C---V
// 
// 
// 
// 
// .LABEL PUBLIC
// 
// 
// .LABEL PUBLIC
// .TITLE Serial ATA IDP Index
// 
// This is Serial ATA IDP Index register as defined in AHCI rev 1.1 spec.
// 
// 31           24 23           16 15            8 7             0
// .-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-.
// |                                                               | CFG_35
// +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
// 
#define SATA0_CFG_35_0                                     0x00000094                                                                       // RW-4R
#define SATA0_CFG_35_0_SECURE                              0
#define SATA0_CFG_35_0_WORD_COUNT                          1
#define SATA0_CFG_35_0_RESET_VAL                           0x0
#define SATA0_CFG_35_0_RESET_MASK                          0x0
#define SATA0_CFG_35_0_SW_DEFAULT_VAL                      0x0
#define SATA0_CFG_35_0_SW_DEFAULT_MASK                     0x0
#define SATA0_CFG_35_0_READ_MASK                           0xffffffff
#define SATA0_CFG_35_0_WRITE_MASK                          0xffffffff
#define SATA0_CFG_35_0_RESERVED_SHIFT                       _MK_SHIFT_CONST(13)                                                             // RWW-F
#define SATA0_CFG_35_0_RESERVED_FIELD                      (_MK_SHIFT_CONST(0x7ffff) << SATA0_CFG_35_0_RESERVED_SHIFT)
#define SATA0_CFG_35_0_RESERVED_RANGE                      31:13
#define SATA0_CFG_35_0_RESERVED_WOFFSET                    0
#define SATA0_CFG_35_0_RESERVED_DEFAULT                    (_MK_MASK_CONST(0x00000000)
#define SATA0_CFG_35_0_RESERVED_DEFAULT_MASK               (_MK_MASK_CONST(0x7ffff)
#define SATA0_CFG_35_0_RESERVED_SW_DEFAULT                 (_MK_MASK_CONST(0x00000000)
#define SATA0_CFG_35_0_RESERVED_SW_DEFAULT_MASK            (_MK_MASK_CONST(0x7ffff)
#define SATA0_CFG_35_0_RESERVED_0                          _MK_ENUM_CONST(0x00000000)                                                       // RWW-V
#define SATA0_CFG_35_0_IDP_INDEX_SHIFT                      _MK_SHIFT_CONST(2)                                                              // RWW-F
#define SATA0_CFG_35_0_IDP_INDEX_FIELD                     (_MK_SHIFT_CONST(0x7ff) << SATA0_CFG_35_0_IDP_INDEX_SHIFT)
#define SATA0_CFG_35_0_IDP_INDEX_RANGE                     12:2
#define SATA0_CFG_35_0_IDP_INDEX_WOFFSET                   0
#define SATA0_CFG_35_0_IDP_INDEX_DEFAULT                   (_MK_MASK_CONST(0x00000000)
#define SATA0_CFG_35_0_IDP_INDEX_DEFAULT_MASK              (_MK_MASK_CONST(0x7ff)
#define SATA0_CFG_35_0_IDP_INDEX_SW_DEFAULT                (_MK_MASK_CONST(0x00000000)
#define SATA0_CFG_35_0_IDP_INDEX_SW_DEFAULT_MASK           (_MK_MASK_CONST(0x7ff)
#define SATA0_CFG_35_0_IDP_INDEX__NOPRDCHK                 _MK_ENUM_CONST(0x00000001)                                                       // ----V
#define SATA0_CFG_35_0_IDP_INDEX_0                         _MK_ENUM_CONST(0x00000000)                                                       // RWW-V
#define SATA0_CFG_35_0_RESERVED1_SHIFT                      _MK_SHIFT_CONST(0)                                                              // RWW-F
#define SATA0_CFG_35_0_RESERVED1_FIELD                     (_MK_SHIFT_CONST(0x3) << SATA0_CFG_35_0_RESERVED1_SHIFT)
#define SATA0_CFG_35_0_RESERVED1_RANGE                     1:0
#define SATA0_CFG_35_0_RESERVED1_WOFFSET                   0
#define SATA0_CFG_35_0_RESERVED1_DEFAULT                   (_MK_MASK_CONST(0x00000000)
#define SATA0_CFG_35_0_RESERVED1_DEFAULT_MASK              (_MK_MASK_CONST(0x3)
#define SATA0_CFG_35_0_RESERVED1_SW_DEFAULT                (_MK_MASK_CONST(0x00000000)
#define SATA0_CFG_35_0_RESERVED1_SW_DEFAULT_MASK           (_MK_MASK_CONST(0x3)
#define SATA0_CFG_35_0_RESERVED1_0                         _MK_ENUM_CONST(0x00000000)                                                       // RWW-V
// 
// 
// 
// 
// .LABEL PUBLIC
// 
// .LABEL PUBLIC
// .TITLE Serial ATA IDP DATA
// 
// This is Serial ATA IDP Data register as defined in AHCI rev 1.1 spec.
// 
// 31           24 23           16 15            8 7             0
// .-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-.
// |                                                               | CFG_36
// +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
#define SATA0_AHCI_IDP1_0                                  0x00000098                                                                       // RW-4R
#define SATA0_AHCI_IDP1_0_SECURE                           0
#define SATA0_AHCI_IDP1_0_WORD_COUNT                       1
#define SATA0_AHCI_IDP1_0_RESET_VAL                        0x0
#define SATA0_AHCI_IDP1_0_RESET_MASK                       0x0
#define SATA0_AHCI_IDP1_0_SW_DEFAULT_VAL                   0x0
#define SATA0_AHCI_IDP1_0_SW_DEFAULT_MASK                  0x0
#define SATA0_AHCI_IDP1_0_READ_MASK                        0xffffffff
#define SATA0_AHCI_IDP1_0_WRITE_MASK                       0xffffffff
#define SATA0_AHCI_IDP1_0_DATA_SHIFT                        _MK_SHIFT_CONST(0)                                                              // RW--F
#define SATA0_AHCI_IDP1_0_DATA_FIELD                       (_MK_SHIFT_CONST(0xffffffff) << SATA0_AHCI_IDP1_0_DATA_SHIFT)
#define SATA0_AHCI_IDP1_0_DATA_RANGE                       31:0
#define SATA0_AHCI_IDP1_0_DATA_WOFFSET                     0
// .LABEL PUBLIC
// 
// 
// 
// .LABEL PRIVATE INT_REL
// Following are registers required to support MSI interrupt modes.
// 
// int0 is either non-ADMA primary channel interrupt or primary channel ADMA interrupt if the
// command completes without any error. int1 is similarly non-ADMA secondary channel interrupt
// or secondary channel ADMA inerrupt if the command completes without any error.
// int2 is used to signal primary channel errorneous command completetion.
// int3 is used to signal secondary channel errorneous command completetion.
// 
// 
// .LABEL PCI_CONFIG
// .TITLE MSI Message Control and Capability Register B0h
// 
// MSI_CTRL is the main control register for MSI support.
// 
// .FIELD CAP_ID
//    The CAP_ID field identifies this capability block as the MSI capability block.
// This is read-only as 0x5.
// .FIELD NEXT_PTR
//    The NEXT_PTR field identifies the next item in the capabilities list.  It is
// a read-only field.
// .FIELD MSI_ENABLE
//    The MSI_ENABLE field enables the MSI capability.  If MSI_ENABLE is written
// to a 1, the controller is permitted to use MSI to request service and is
// prohibited from using the legacy interrupt.  System configuration software
// sets this bit to enable MSI.
//    A device driver is prohibited from writing this bit to mask the
// controller's service request.
//    If this bit is written to a 0, the controller is prohibited from using
// MSI to request service.
// .FIELD MULT_MSG_CAP
//    System software reads this field to determine the number of requested
// vectors.  The number of requested vectors must be aligned to a power of two.
// Values of 6 and 7 in this field are reserved.
// .FIELD MULT_MSG_ENABLE
//    System software writes to this field to indicate the number of
// allocated vectors (less than or equal to  the number of vectors
// requested).  The number of vectors is aligned as a power of two.
// When MSI is enabled, the controller will be allocated at least one vector.
// .FIELD 64_ADDR_CAP
//    The 64_ADDR_CAP field indicates whether or not the controller is
// capable of generating a 64-bit message address.  A value of 1 means
// the controller is capable of generating a 64-bit message address.
// .FIELD VECTOR_MASK_CAP
//   The VECTOR_MASK_CAP field indicates whether or not the controller
// supports MSI-per-vector masking.
// 
// 
//  31           24 23           16 15            8 7             0
// .-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-.
// |0 0 0 0 0 0 0 0|                                               | MSI_CTRL
// +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
// 
#define SATA0_MSI_CTRL_0                                   0x000000B0                                                                       // RW-4R
#define SATA0_MSI_CTRL_0_SECURE                            0
#define SATA0_MSI_CTRL_0_WORD_COUNT                        1
#define SATA0_MSI_CTRL_0_RESET_VAL                         0x0
#define SATA0_MSI_CTRL_0_RESET_MASK                        0x0
#define SATA0_MSI_CTRL_0_SW_DEFAULT_VAL                    0x0
#define SATA0_MSI_CTRL_0_SW_DEFAULT_MASK                   0x0
#define SATA0_MSI_CTRL_0_READ_MASK                         0x1ffffff
#define SATA0_MSI_CTRL_0_WRITE_MASK                        0x710000
#define SATA0_MSI_CTRL_0_VECTOR_MASK_CAP_SHIFT              _MK_SHIFT_CONST(24)                                                             // C--VF
#define SATA0_MSI_CTRL_0_VECTOR_MASK_CAP_FIELD             (_MK_SHIFT_CONST(0x1) << SATA0_MSI_CTRL_0_VECTOR_MASK_CAP_SHIFT)
#define SATA0_MSI_CTRL_0_VECTOR_MASK_CAP_RANGE             24:24
#define SATA0_MSI_CTRL_0_VECTOR_MASK_CAP_WOFFSET           0
#define SATA0_MSI_CTRL_0_VECTOR_MASK_CAP_DIS               _MK_ENUM_CONST(0x00000000)                                                       // ----V
#define SATA0_MSI_CTRL_0_VECTOR_MASK_CAP_EN                _MK_ENUM_CONST(0x00000001)                                                       // ----V
#define SATA0_MSI_CTRL_0_64_ADDR_CAP_SHIFT                  _MK_SHIFT_CONST(23)                                                             // C--VF
#define SATA0_MSI_CTRL_0_64_ADDR_CAP_FIELD                 (_MK_SHIFT_CONST(0x1) << SATA0_MSI_CTRL_0_64_ADDR_CAP_SHIFT)
#define SATA0_MSI_CTRL_0_64_ADDR_CAP_RANGE                 23:23
#define SATA0_MSI_CTRL_0_64_ADDR_CAP_WOFFSET               0
#define SATA0_MSI_CTRL_0_64_ADDR_CAP_DIS                   _MK_ENUM_CONST(0x00000000)                                                       // ----V
#define SATA0_MSI_CTRL_0_64_ADDR_CAP_EN                    _MK_ENUM_CONST(0x00000001)                                                       // ----V
#define SATA0_MSI_CTRL_0_MULT_MSG_ENABLE_SHIFT              _MK_SHIFT_CONST(20)                                                             // RWWVF
#define SATA0_MSI_CTRL_0_MULT_MSG_ENABLE_FIELD             (_MK_SHIFT_CONST(0x7) << SATA0_MSI_CTRL_0_MULT_MSG_ENABLE_SHIFT)
#define SATA0_MSI_CTRL_0_MULT_MSG_ENABLE_RANGE             22:20
#define SATA0_MSI_CTRL_0_MULT_MSG_ENABLE_WOFFSET           0
#define SATA0_MSI_CTRL_0_MULT_MSG_ENABLE_DEFAULT           (_MK_MASK_CONST(0x00000000)
#define SATA0_MSI_CTRL_0_MULT_MSG_ENABLE_DEFAULT_MASK      (_MK_MASK_CONST(0x7)
#define SATA0_MSI_CTRL_0_MULT_MSG_ENABLE_SW_DEFAULT        (_MK_MASK_CONST(0x00000000)
#define SATA0_MSI_CTRL_0_MULT_MSG_ENABLE_SW_DEFAULT_MASK   (_MK_MASK_CONST(0x7)
#define SATA0_MSI_CTRL_0_MULT_MSG_ENABLE_1                 _MK_ENUM_CONST(0x00000000)                                                       // ----V
#define SATA0_MSI_CTRL_0_MULT_MSG_ENABLE_2                 _MK_ENUM_CONST(0x00000001)                                                       // ----V
#define SATA0_MSI_CTRL_0_MULT_MSG_ENABLE_4                 _MK_ENUM_CONST(0x00000002)                                                       // ----V
#define SATA0_MSI_CTRL_0_MULT_MSG_ENABLE_8                 _MK_ENUM_CONST(0x00000003)                                                       // ----V
#define SATA0_MSI_CTRL_0_MULT_MSG_ENABLE_16                _MK_ENUM_CONST(0x00000004)                                                       // ----V
#define SATA0_MSI_CTRL_0_MULT_MSG_ENABLE_32                _MK_ENUM_CONST(0x00000005)                                                       // ----V
#define SATA0_MSI_CTRL_0_MULT_MSG_CAP_SHIFT                 _MK_SHIFT_CONST(17)                                                             // C--VF
#define SATA0_MSI_CTRL_0_MULT_MSG_CAP_FIELD                (_MK_SHIFT_CONST(0x7) << SATA0_MSI_CTRL_0_MULT_MSG_CAP_SHIFT)
#define SATA0_MSI_CTRL_0_MULT_MSG_CAP_RANGE                19:17
#define SATA0_MSI_CTRL_0_MULT_MSG_CAP_WOFFSET              0
#define SATA0_MSI_CTRL_0_MULT_MSG_CAP_1                    _MK_ENUM_CONST(0x00000000)                                                       // ----V
#define SATA0_MSI_CTRL_0_MULT_MSG_CAP_2                    _MK_ENUM_CONST(0x00000001)                                                       // ----V
#define SATA0_MSI_CTRL_0_MULT_MSG_CAP_4                    _MK_ENUM_CONST(0x00000002)                                                       // ----V
#define SATA0_MSI_CTRL_0_MULT_MSG_CAP_8                    _MK_ENUM_CONST(0x00000003)                                                       // ----V
#define SATA0_MSI_CTRL_0_MULT_MSG_CAP_16                   _MK_ENUM_CONST(0x00000004)                                                       // ----V
#define SATA0_MSI_CTRL_0_MULT_MSG_CAP_32                   _MK_ENUM_CONST(0x00000005)                                                       // ----V
#define SATA0_MSI_CTRL_0_MSI_ENABLE_SHIFT                   _MK_SHIFT_CONST(16)                                                             // RWWVF
#define SATA0_MSI_CTRL_0_MSI_ENABLE_FIELD                  (_MK_SHIFT_CONST(0x1) << SATA0_MSI_CTRL_0_MSI_ENABLE_SHIFT)
#define SATA0_MSI_CTRL_0_MSI_ENABLE_RANGE                  16:16
#define SATA0_MSI_CTRL_0_MSI_ENABLE_WOFFSET                0
#define SATA0_MSI_CTRL_0_MSI_ENABLE_DEFAULT                (_MK_MASK_CONST(0x00000000)
#define SATA0_MSI_CTRL_0_MSI_ENABLE_DEFAULT_MASK           (_MK_MASK_CONST(0x1)
#define SATA0_MSI_CTRL_0_MSI_ENABLE_SW_DEFAULT             (_MK_MASK_CONST(0x00000000)
#define SATA0_MSI_CTRL_0_MSI_ENABLE_SW_DEFAULT_MASK        (_MK_MASK_CONST(0x1)
#define SATA0_MSI_CTRL_0_MSI_ENABLE_OFF                    _MK_ENUM_CONST(0x00000000)                                                       // ----V
#define SATA0_MSI_CTRL_0_MSI_ENABLE_ON                     _MK_ENUM_CONST(0x00000001)                                                       // ----V
#define SATA0_MSI_CTRL_0_NEXT_PTR_SHIFT                     _MK_SHIFT_CONST(8)                                                              // C--VF
#define SATA0_MSI_CTRL_0_NEXT_PTR_FIELD                    (_MK_SHIFT_CONST(0xff) << SATA0_MSI_CTRL_0_NEXT_PTR_SHIFT)
#define SATA0_MSI_CTRL_0_NEXT_PTR_RANGE                    15:8
#define SATA0_MSI_CTRL_0_NEXT_PTR_WOFFSET                  0
#define SATA0_MSI_CTRL_0_NEXT_PTR_NULL                     _MK_ENUM_CONST(0x00000000)                                                       // ----V
#define SATA0_MSI_CTRL_0_NEXT_PTR_MMAP                     _MK_ENUM_CONST(0x000000EC)                                                       // ----V
#define SATA0_MSI_CTRL_0_CAP_ID_SHIFT                       _MK_SHIFT_CONST(0)                                                              // C--VF
#define SATA0_MSI_CTRL_0_CAP_ID_FIELD                      (_MK_SHIFT_CONST(0xff) << SATA0_MSI_CTRL_0_CAP_ID_SHIFT)
#define SATA0_MSI_CTRL_0_CAP_ID_RANGE                      7:0
#define SATA0_MSI_CTRL_0_CAP_ID_WOFFSET                    0
#define SATA0_MSI_CTRL_0_CAP_ID_MSI                        _MK_ENUM_CONST(0x00000005)                                                       // C---V
// 
//                 Figure 10-42
// 
// .LABEL PUBLIC
// 
// .LABEL PRIVATE INT_REL
// .LABEL FUNC_BIOS
// 
// .TITLE MSI Message Address Register B4h
// 
// MSI_ADDR1 specifies the lower 32 bits to which a MSI memory write transaction
// should occur.
// 
// .FIELD MSG_ADDR
//    System-specified message address.  When MSI is enabled, this field
// specifies the dword-aligned address for the MSI memory write transaction.
// 
//  31           24 23           16 15            8 7             0
// .-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-.
// |                                                           |0 0| MSI_ADDR1
// +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
// 
#define SATA0_MSI_ADDR1_0                                  0x000000B4                                                                       // RW-4R
#define SATA0_MSI_ADDR1_0_SECURE                           0
#define SATA0_MSI_ADDR1_0_WORD_COUNT                       1
#define SATA0_MSI_ADDR1_0_RESET_VAL                        0x0
#define SATA0_MSI_ADDR1_0_RESET_MASK                       0x0
#define SATA0_MSI_ADDR1_0_SW_DEFAULT_VAL                   0x0
#define SATA0_MSI_ADDR1_0_SW_DEFAULT_MASK                  0x0
#define SATA0_MSI_ADDR1_0_READ_MASK                        0xfffffffc
#define SATA0_MSI_ADDR1_0_WRITE_MASK                       0xfffffffc
#define SATA0_MSI_ADDR1_0_MSG_ADDR_SHIFT                    _MK_SHIFT_CONST(2)                                                              // RWWVF
#define SATA0_MSI_ADDR1_0_MSG_ADDR_FIELD                   (_MK_SHIFT_CONST(0x3fffffff) << SATA0_MSI_ADDR1_0_MSG_ADDR_SHIFT)
#define SATA0_MSI_ADDR1_0_MSG_ADDR_RANGE                   31:2
#define SATA0_MSI_ADDR1_0_MSG_ADDR_WOFFSET                 0
#define SATA0_MSI_ADDR1_0_MSG_ADDR_DEFAULT                 (_MK_MASK_CONST(0x00000000)
#define SATA0_MSI_ADDR1_0_MSG_ADDR_DEFAULT_MASK            (_MK_MASK_CONST(0x3fffffff)
#define SATA0_MSI_ADDR1_0_MSG_ADDR_SW_DEFAULT              (_MK_MASK_CONST(0x00000000)
#define SATA0_MSI_ADDR1_0_MSG_ADDR_SW_DEFAULT_MASK         (_MK_MASK_CONST(0x3fffffff)
// 
//                 Figure 10-43
// .LABEL PUBLIC
// 
// .LABEL PRIVATE INT_REL
// .LABEL FUNC_BIOS
// 
// .TITLE MSI Message Upper Address Register B8h
// 
// MSI_ADDR2 specifies the upper 32 bits to which a MSI memory write transaction
// should occur.
// 
// .FIELD MSG_ADDR
//    System-specified message address.  When MSI is enabled, this field
// specifies the upper 32-bits of the address for the MSI memory
// write transaction.  The contents of this register only apply
// when T_SATA0_MSI_CTRL_64_ADDR_CAP bit is set.
// 
// 
//  31           24 23           16 15            8 7             0
// .-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-.
// |0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0|               | MSI_ADDR2
// +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
// 
#define SATA0_MSI_ADDR2_0                                  0x000000B8                                                                       // RW-4R
#define SATA0_MSI_ADDR2_0_SECURE                           0
#define SATA0_MSI_ADDR2_0_WORD_COUNT                       1
#define SATA0_MSI_ADDR2_0_RESET_VAL                        0x0
#define SATA0_MSI_ADDR2_0_RESET_MASK                       0x0
#define SATA0_MSI_ADDR2_0_SW_DEFAULT_VAL                   0x0
#define SATA0_MSI_ADDR2_0_SW_DEFAULT_MASK                  0x0
#define SATA0_MSI_ADDR2_0_READ_MASK                        0xffffffff
#define SATA0_MSI_ADDR2_0_WRITE_MASK                       0xffffffff
#define SATA0_MSI_ADDR2_0_MSG_ADDR_SHIFT                    _MK_SHIFT_CONST(0)                                                              // RWWVF
#define SATA0_MSI_ADDR2_0_MSG_ADDR_FIELD                   (_MK_SHIFT_CONST(0xffffffff) << SATA0_MSI_ADDR2_0_MSG_ADDR_SHIFT)
#define SATA0_MSI_ADDR2_0_MSG_ADDR_RANGE                   31:0
#define SATA0_MSI_ADDR2_0_MSG_ADDR_WOFFSET                 0
#define SATA0_MSI_ADDR2_0_MSG_ADDR_DEFAULT                 (_MK_MASK_CONST(0x00000000)
#define SATA0_MSI_ADDR2_0_MSG_ADDR_DEFAULT_MASK            (_MK_MASK_CONST(0xffffffff)
#define SATA0_MSI_ADDR2_0_MSG_ADDR_SW_DEFAULT              (_MK_MASK_CONST(0x00000000)
#define SATA0_MSI_ADDR2_0_MSG_ADDR_SW_DEFAULT_MASK         (_MK_MASK_CONST(0xffffffff)
// 
//                 Figure 10-44
// .LABEL PUBLIC
// 
// .LABEL PRIVATE INT_REL
// .LABEL FUNC_BIOS
// 
// .TITLE MSI Message Data Register BCh
// 
// The MSI_DATA register contains the system-specified message.
// 
// .FIELD MSG_DATA
// System-specified message  When MSI is enabled, the message
// data is driven onto the lower 16-bits of the MSI memory write.
// 
// The MULT_MSG_ENABLE field in configuration register B0h specifies
// the number of low order message data bits that the SATA is permitted
// to modify to generate its system software allocated vectors.
// 
// //Essentially, MSG_DATA contains the base MSI message data for
// //MSI vector 0.  For MSI vector 1, the message data that will be sent
// //out will be (MSG_DATA + 1); for MSI vector 2, message data that
// //will be sent out will be (MSG_DATA + 2), etc.
// 
// 
//  31           24 23           16 15            8 7             0
// .-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-.
// |0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0|                               | MSI_DATA
// +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
// 
#define SATA0_MSI_DATA_0                                   0x000000BC                                                                       // RW-4R
#define SATA0_MSI_DATA_0_SECURE                            0
#define SATA0_MSI_DATA_0_WORD_COUNT                        1
#define SATA0_MSI_DATA_0_RESET_VAL                         0x0
#define SATA0_MSI_DATA_0_RESET_MASK                        0x0
#define SATA0_MSI_DATA_0_SW_DEFAULT_VAL                    0x0
#define SATA0_MSI_DATA_0_SW_DEFAULT_MASK                   0x0
#define SATA0_MSI_DATA_0_READ_MASK                         0xffff
#define SATA0_MSI_DATA_0_WRITE_MASK                        0xffff
#define SATA0_MSI_DATA_0_MSG_DATA_SHIFT                     _MK_SHIFT_CONST(0)                                                              // RWWVF
#define SATA0_MSI_DATA_0_MSG_DATA_FIELD                    (_MK_SHIFT_CONST(0xffff) << SATA0_MSI_DATA_0_MSG_DATA_SHIFT)
#define SATA0_MSI_DATA_0_MSG_DATA_RANGE                    15:0
#define SATA0_MSI_DATA_0_MSG_DATA_WOFFSET                  0
#define SATA0_MSI_DATA_0_MSG_DATA_DEFAULT                  (_MK_MASK_CONST(0x00000000)
#define SATA0_MSI_DATA_0_MSG_DATA_DEFAULT_MASK             (_MK_MASK_CONST(0xffff)
#define SATA0_MSI_DATA_0_MSG_DATA_SW_DEFAULT               (_MK_MASK_CONST(0x00000000)
#define SATA0_MSI_DATA_0_MSG_DATA_SW_DEFAULT_MASK          (_MK_MASK_CONST(0xffff)
// 
//                 Figure 10-45
// 
// .LABEL PUBLIC
// .LABEL INT_REL
// 
// .TITLE MSI Message Queue Configuration Register C0h
// 
// The MSI_QUEUE register is a private register.  It specifies to which
// virtual channel queue (ISO or NON-ISO) that the MSI message will be
// sent to before being sent out on FPCI bus.
// 
// //Note:  When the MSI message is created, the FPCI wrapper won't know
// //       which physical queue to put the MSI message into.  The MSI_QUEUE
// //       setting will determine this on a vector-by-vector basis.  If
// //       the corresponding bit is set to 1, FPCI wrapper will put
// //       that MSI message into the ISO command/data queue; otherwise
// //       by default the message is placed in the NONISO queue.
// //       After the MSI message is popped from the ISO/NONISO queue,
// //       the settings in FPCICFG_ISOCMD, FPCICFG_PASSPW, and FPCICFG_RSPPASSPW
// //       will apply.  Since the MAC FPCI wrapper, physically, only contains
// //       the ISO command/data queues, the MSI_QUEUE bits must be all set to 1 for
// //       all MSI vectors.
// 
// .FIELD BITS
// The BITS field specifies to which VC queue a particular MSI message will be sent to.
// 
//                 bit 0 corresponds to MSI vector 0
//                 bit 1 corresponds to MSI vector 1
//                 bit 2 corresponds to MSI vector 2
//                 bit 3 corresponds to MSI vector 3
// 
// 
//  31           24 23           16 15            8 7             0
// .-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-.
// |0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0        | MSI_QUEUE
// +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
// 
#define SATA0_MSI_QUEUE_0                                  0x000000C0                                                                       // RW-4R
#define SATA0_MSI_QUEUE_0_SECURE                           0
#define SATA0_MSI_QUEUE_0_WORD_COUNT                       1
#define SATA0_MSI_QUEUE_0_RESET_VAL                        0x0
#define SATA0_MSI_QUEUE_0_RESET_MASK                       0x0
#define SATA0_MSI_QUEUE_0_SW_DEFAULT_VAL                   0x0
#define SATA0_MSI_QUEUE_0_SW_DEFAULT_MASK                  0x0
#define SATA0_MSI_QUEUE_0_READ_MASK                        0xf
#define SATA0_MSI_QUEUE_0_WRITE_MASK                       0xf
#define SATA0_MSI_QUEUE_0_BITS_SHIFT                        _MK_SHIFT_CONST(0)                                                              // RWWVF
#define SATA0_MSI_QUEUE_0_BITS_FIELD                       (_MK_SHIFT_CONST(0xf) << SATA0_MSI_QUEUE_0_BITS_SHIFT)
#define SATA0_MSI_QUEUE_0_BITS_RANGE                       3:0
#define SATA0_MSI_QUEUE_0_BITS_WOFFSET                     0
#define SATA0_MSI_QUEUE_0_BITS_DEFAULT                     (_MK_MASK_CONST(0x00000000)
#define SATA0_MSI_QUEUE_0_BITS_DEFAULT_MASK                (_MK_MASK_CONST(0xf)
#define SATA0_MSI_QUEUE_0_BITS_SW_DEFAULT                  (_MK_MASK_CONST(0x00000000)
#define SATA0_MSI_QUEUE_0_BITS_SW_DEFAULT_MASK             (_MK_MASK_CONST(0xf)
// 
//                 Figure 10-48
// .LABEL PUBLIC
// 
// 
// 
// 
// 
// 
// 
// 
// .LABEL PCI_CONFIG
// .LABEL PRIVATE INT_REL
// .TITLE MSI Mapping Capability Register ECh
// 
// The MSI_MAP register is used to tell the OS that MSIs are supported in K8 mode.
// //The register is for S/W information purposes only and doesn't do anything in H/W.
// 
// This is the per-device HT MSI Capability Block.
// 
// //From the HT 2.00a Draft 3 spec:
// //This capability is used by PCI bridges to define the address range where MSIs are
// //mapped to HT interrupt messages.  There must be an MSI mapping capability in each device
// //number that supports MSI mapping, preferably in function 0.  The capability affects
// //MSIs generated in all functions of that device.  It is expected that all MSI mapping
// //capabilities found in a system will be programmed with the same address.
// 
// .FIELD CAP_ID
//    The CAP_ID field identifies that this is an HT capability
// list item. (Read-only as 0x8).
// 
// .FIELD NEXT_PTR
//    The NEXT_PTR field points to the next item in the capabilities list.
// It is a read-only field.
// //In MCP04/CK804/MCP51, this points to NULL (end of list).
// 
// .FIELD EN
//    The EN bit indicates if the mapping is active.  It is cleared upon warm reset.
// 
// .FIELD FIXD
//    The FIXD bit is a read-only bit indicating if the the next 2 dwords
// for programmable address are present in the capability.  If set, the
// address for mapping MSIs is fixed at 0x0000_0000_FEEx_xxxx and that this
// capability block is 1 dword long.
// 
// .FIELD CAP_TYPE
//    The CAP_TYPE field is read only at 0x15 to indicate that this is an MSI
// Mapping Capability block.
// 
// 
//  31           24 23           16 15            8 7             0
// .-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-.
// |          0 0 0|0 0 0 0 0 0    |               |               | MSI_MAP
// +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
// 
#define SATA0_MSI_MAP_0                                    0x000000EC                                                                       // RW-4R
#define SATA0_MSI_MAP_0_SECURE                             0
#define SATA0_MSI_MAP_0_WORD_COUNT                         1
#define SATA0_MSI_MAP_0_RESET_VAL                          0x0
#define SATA0_MSI_MAP_0_RESET_MASK                         0x0
#define SATA0_MSI_MAP_0_SW_DEFAULT_VAL                     0x0
#define SATA0_MSI_MAP_0_SW_DEFAULT_MASK                    0x0
#define SATA0_MSI_MAP_0_READ_MASK                          0xf803ffff
#define SATA0_MSI_MAP_0_WRITE_MASK                         0x10000
#define SATA0_MSI_MAP_0_CAP_TYPE_SHIFT                      _MK_SHIFT_CONST(27)                                                             // C--VF
#define SATA0_MSI_MAP_0_CAP_TYPE_FIELD                     (_MK_SHIFT_CONST(0x1f) << SATA0_MSI_MAP_0_CAP_TYPE_SHIFT)
#define SATA0_MSI_MAP_0_CAP_TYPE_RANGE                     31:27
#define SATA0_MSI_MAP_0_CAP_TYPE_WOFFSET                   0
#define SATA0_MSI_MAP_0_FIXD_SHIFT                          _MK_SHIFT_CONST(17)                                                             // C--VF
#define SATA0_MSI_MAP_0_FIXD_FIELD                         (_MK_SHIFT_CONST(0x1) << SATA0_MSI_MAP_0_FIXD_SHIFT)
#define SATA0_MSI_MAP_0_FIXD_RANGE                         17:17
#define SATA0_MSI_MAP_0_FIXD_WOFFSET                       0
#define SATA0_MSI_MAP_0_FIXD_ON                            _MK_ENUM_CONST(0x00000001)                                                       // C---V
#define SATA0_MSI_MAP_0_EN_SHIFT                            _MK_SHIFT_CONST(16)                                                             // RWWVF
#define SATA0_MSI_MAP_0_EN_FIELD                           (_MK_SHIFT_CONST(0x1) << SATA0_MSI_MAP_0_EN_SHIFT)
#define SATA0_MSI_MAP_0_EN_RANGE                           16:16
#define SATA0_MSI_MAP_0_EN_WOFFSET                         0
#define SATA0_MSI_MAP_0_EN_DEFAULT                         (_MK_MASK_CONST(0x00000000)
#define SATA0_MSI_MAP_0_EN_DEFAULT_MASK                    (_MK_MASK_CONST(0x1)
#define SATA0_MSI_MAP_0_EN_SW_DEFAULT                      (_MK_MASK_CONST(0x00000000)
#define SATA0_MSI_MAP_0_EN_SW_DEFAULT_MASK                 (_MK_MASK_CONST(0x1)
#define SATA0_MSI_MAP_0_EN_OFF                             _MK_ENUM_CONST(0x00000000)                                                       // ----V
#define SATA0_MSI_MAP_0_EN_ON                              _MK_ENUM_CONST(0x00000001)                                                       // ----V
#define SATA0_MSI_MAP_0_NEXT_PTR_SHIFT                      _MK_SHIFT_CONST(8)                                                              // C--VF
#define SATA0_MSI_MAP_0_NEXT_PTR_FIELD                     (_MK_SHIFT_CONST(0xff) << SATA0_MSI_MAP_0_NEXT_PTR_SHIFT)
#define SATA0_MSI_MAP_0_NEXT_PTR_RANGE                     15:8
#define SATA0_MSI_MAP_0_NEXT_PTR_WOFFSET                   0
#define SATA0_MSI_MAP_0_NEXT_PTR_NULL                      _MK_ENUM_CONST(0x00000000)                                                       // ----V
#define SATA0_MSI_MAP_0_CAP_ID_SHIFT                        _MK_SHIFT_CONST(0)                                                              // C--VF
#define SATA0_MSI_MAP_0_CAP_ID_FIELD                       (_MK_SHIFT_CONST(0xff) << SATA0_MSI_MAP_0_CAP_ID_SHIFT)
#define SATA0_MSI_MAP_0_CAP_ID_RANGE                       7:0
#define SATA0_MSI_MAP_0_CAP_ID_WOFFSET                     0
#define SATA0_MSI_MAP_0_CAP_ID_MSI                         _MK_ENUM_CONST(0x00000008)                                                       // C---V
// 
//                 Figure 10-49
// .LABEL PUBLIC
// 
// .LABEL PUBLIC
// .TITLE IDP pair to access  257-4K address space - Address register
// 
// 
// 31           24 23           16 15            8 7             0
// .-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-.
// |                                                               | CFG_35
// +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
// 
#define SATA0_INDIRECT_IDP0_0                              0x000000F0                                                                       // RW-4R
#define SATA0_INDIRECT_IDP0_0_SECURE                       0
#define SATA0_INDIRECT_IDP0_0_WORD_COUNT                   1
#define SATA0_INDIRECT_IDP0_0_RESET_VAL                    0x0
#define SATA0_INDIRECT_IDP0_0_RESET_MASK                   0x0
#define SATA0_INDIRECT_IDP0_0_SW_DEFAULT_VAL               0x0
#define SATA0_INDIRECT_IDP0_0_SW_DEFAULT_MASK              0x0
#define SATA0_INDIRECT_IDP0_0_READ_MASK                    0xffffffff
#define SATA0_INDIRECT_IDP0_0_WRITE_MASK                   0xffc
#define SATA0_INDIRECT_IDP0_0_RESERVED_SHIFT                _MK_SHIFT_CONST(12)                                                             // C---F
#define SATA0_INDIRECT_IDP0_0_RESERVED_FIELD               (_MK_SHIFT_CONST(0xfffff) << SATA0_INDIRECT_IDP0_0_RESERVED_SHIFT)
#define SATA0_INDIRECT_IDP0_0_RESERVED_RANGE               31:12
#define SATA0_INDIRECT_IDP0_0_RESERVED_WOFFSET             0
#define SATA0_INDIRECT_IDP0_0_RESERVED_0                   _MK_ENUM_CONST(0x00000000)                                                       // C---V
#define SATA0_INDIRECT_IDP0_0_IDP_INDEX_SHIFT               _MK_SHIFT_CONST(2)                                                              // RWW-F
#define SATA0_INDIRECT_IDP0_0_IDP_INDEX_FIELD              (_MK_SHIFT_CONST(0x3ff) << SATA0_INDIRECT_IDP0_0_IDP_INDEX_SHIFT)
#define SATA0_INDIRECT_IDP0_0_IDP_INDEX_RANGE              11:2
#define SATA0_INDIRECT_IDP0_0_IDP_INDEX_WOFFSET            0
#define SATA0_INDIRECT_IDP0_0_IDP_INDEX_DEFAULT            (_MK_MASK_CONST(0x00000000)
#define SATA0_INDIRECT_IDP0_0_IDP_INDEX_DEFAULT_MASK       (_MK_MASK_CONST(0x3ff)
#define SATA0_INDIRECT_IDP0_0_IDP_INDEX_SW_DEFAULT         (_MK_MASK_CONST(0x00000000)
#define SATA0_INDIRECT_IDP0_0_IDP_INDEX_SW_DEFAULT_MASK    (_MK_MASK_CONST(0x3ff)
#define SATA0_INDIRECT_IDP0_0_IDP_INDEX_0                  _MK_ENUM_CONST(0x00000000)                                                       // RWW-V
#define SATA0_INDIRECT_IDP0_0_RESERVED1_SHIFT               _MK_SHIFT_CONST(0)                                                              // C---F
#define SATA0_INDIRECT_IDP0_0_RESERVED1_FIELD              (_MK_SHIFT_CONST(0x3) << SATA0_INDIRECT_IDP0_0_RESERVED1_SHIFT)
#define SATA0_INDIRECT_IDP0_0_RESERVED1_RANGE              1:0
#define SATA0_INDIRECT_IDP0_0_RESERVED1_WOFFSET            0
#define SATA0_INDIRECT_IDP0_0_RESERVED1_0                  _MK_ENUM_CONST(0x00000000)                                                       // C---V
// 
// 
// 
// 
// .LABEL PUBLIC
// 
// .LABEL PUBLIC
// .TITLE IDP pair to access  257-4K address space - DATA register
// 
// 31           24 23           16 15            8 7             0
// .-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-.
// |                                                               | CFG_36
// +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
#define SATA0_INDIRECT_IDP1_0                              0x000000F4                                                                       // RW-4R
#define SATA0_INDIRECT_IDP1_0_SECURE                       0
#define SATA0_INDIRECT_IDP1_0_WORD_COUNT                   1
#define SATA0_INDIRECT_IDP1_0_RESET_VAL                    0x0
#define SATA0_INDIRECT_IDP1_0_RESET_MASK                   0x0
#define SATA0_INDIRECT_IDP1_0_SW_DEFAULT_VAL               0x0
#define SATA0_INDIRECT_IDP1_0_SW_DEFAULT_MASK              0x0
#define SATA0_INDIRECT_IDP1_0_READ_MASK                    0xffffffff
#define SATA0_INDIRECT_IDP1_0_WRITE_MASK                   0xffffffff
#define SATA0_INDIRECT_IDP1_0_DATA_SHIFT                    _MK_SHIFT_CONST(0)                                                              // RW--F
#define SATA0_INDIRECT_IDP1_0_DATA_FIELD                   (_MK_SHIFT_CONST(0xffffffff) << SATA0_INDIRECT_IDP1_0_DATA_SHIFT)
#define SATA0_INDIRECT_IDP1_0_DATA_RANGE                   31:0
#define SATA0_INDIRECT_IDP1_0_DATA_WOFFSET                 0
// 
// .LABEL PUBLIC
// 
// .LABEL PRIVATE INT_REL
// .TITLE FPCI Debug register F8h
//     The FPCICFG register is for the config bits that the FPCI wrapper needs.
// 
// .FIELD ISOCMD
//     T_IDE_FPCICFG_ISOCMD indicates that for a master command issued
// from the wrapper to the UFA, it's issued as ISO, NONISO, or whatever it is sent as
// from the toy. These bits only influence commands that have ISO/NONISO counterparts.
// .FIELD PASSPW
//     FPCICFG_PASSPW indicates that for a master command issued
// from the wrapper to the UFA, it's issued with PASSPW set, PASSPW not set, or
// whatever it is sent with from the toy. These bits only influence non-broadcast
// commands.
// .FIELD RSPPASSPW
//     FPCICFG_RSPPASSPW indicates that for a master command issued
// from the wrapper to the UFA, it's issued with RSPPASSPW set, RSPPASSPW not set, or
// whatever it is sent with from the toy. These bits only influence non-posted
// commands.
// .FIELD CREDIT_SYS_ENABLE
//     FPCICFG_CREDIT_SYS_ENABLE is used to enable the read credit system.
// This is a performance feature. When this bit is set to OFF, the wrapper will assert
// fpci2dev_busy when the toy has reached its maximum number of outstanding NONISO or
// ISO read requests (determined by wrapper parameterization). When this bit is set to ON,
// the wrapper will only throttle toy mastered requests when there is contention for wrapper
// resources. This allows the toy bus master to issue writes even when the read credits
// have been exhausted.
//     The T_SATA0_FPCICFG_ISO_READ_CREDITS field is used when the read credit
// system is enabled. This field sets the maximum number of outstanding ISO read requests
// allowed by the toy. The value in this field must NOT exceed ISO_READ_CREDITS_MAX.
//     The T_SATA0_FPCICFG_NONISO_READ_CREDITS field is used when the read credit
// system is enabled. This field sets the maximum number of outstanding NONISO read requests
// allowed by the toy. The value in this field must NOT exceed NONISO_READ_CREDITS_MAX.
// // If user selects legacy in BIOS, BIOS will load __PROD_LEGACY value, otherwise it will load
// // the __PROD_AHCI value
// .LABEL PRIVATE
// SW_INIT -  The PROD settings are 1E for Legacy and 1F for AHCI, T_SATA0_FPCICFG_NONISO_READ_CREDITS.
// SW_INIT - The setting of CREDIT_SYS_ENABLE should be one for performance.
// .LABEL PRIVATE INT_REL
// .FIELD DROP_ON_ERR_ENABLE
// 
// .FIELD DROP_ON_MA_ERR_ENABLE
// 
// .FIELD DROP_ON_TA_ERR_ENABLE
// 
// .FIELD DEVID_OVERRIDE_ENABLE
// This is bit when set indicates a linux system.
// 
// .FIELD DEVID_OVERRIDE_ID
// Use this 4 bit register to program a desired value between 0x580-0x58F on a linux
// system and between 0x550-0x55B on a no linux system.  The default values for NBP
// and non-NBP systems are as listed below.  Non-NBP systems cannot program values of
// 0x2, 0x4 and 0xA.  If one tried to program a value outside the limits listed
// here, then the last value of this field is retained.
// 
//  31           24 23           16 15            8 7             0
// .-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-.
// |0 0 0 0 0 0 0 0 0 0 0|         |         |0 0| |0 0|           | FPCICFG
// +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
// 
// .LABEL INT_REL
#define SATA0_FPCICFG_0                                    0x000000F8                                                                       // RWW4R
#define SATA0_FPCICFG_0_SECURE                             0
#define SATA0_FPCICFG_0_WORD_COUNT                         1
#define SATA0_FPCICFG_0_RESET_VAL                          0x0
#define SATA0_FPCICFG_0_RESET_MASK                         0x0
#define SATA0_FPCICFG_0_SW_DEFAULT_VAL                     0x0
#define SATA0_FPCICFG_0_SW_DEFAULT_MASK                    0x0
#define SATA0_FPCICFG_0_READ_MASK                          0xffffc1ff
#define SATA0_FPCICFG_0_WRITE_MASK                         0xffdfc1ff
#define SATA0_FPCICFG_0_ISOCMD_SHIFT                        _MK_SHIFT_CONST(0)                                                              // RWWUF
#define SATA0_FPCICFG_0_ISOCMD_FIELD                       (_MK_SHIFT_CONST(0x3) << SATA0_FPCICFG_0_ISOCMD_SHIFT)
#define SATA0_FPCICFG_0_ISOCMD_RANGE                       1:0
#define SATA0_FPCICFG_0_ISOCMD_WOFFSET                     0
#define SATA0_FPCICFG_0_ISOCMD_DEFAULT                     (_MK_MASK_CONST(0x00000000)
#define SATA0_FPCICFG_0_ISOCMD_DEFAULT_MASK                (_MK_MASK_CONST(0x3)
#define SATA0_FPCICFG_0_ISOCMD_SW_DEFAULT                  (_MK_MASK_CONST(0x00000000)
#define SATA0_FPCICFG_0_ISOCMD_SW_DEFAULT_MASK             (_MK_MASK_CONST(0x3)
#define SATA0_FPCICFG_0_ISOCMD__NOPRDCHK                   _MK_ENUM_CONST(0x00000001)                                                       // ----V
#define SATA0_FPCICFG_0_ISOCMD_TOY                         _MK_ENUM_CONST(0x00000000)                                                       // RW--V
#define SATA0_FPCICFG_0_ISOCMD_ISO                         _MK_ENUM_CONST(0x00000001)                                                       // RW--V
#define SATA0_FPCICFG_0_ISOCMD_NONISO                      _MK_ENUM_CONST(0x00000002)                                                       // RW--V
#define SATA0_FPCICFG_0_PASSPW_SHIFT                        _MK_SHIFT_CONST(2)                                                              // RWWUF
#define SATA0_FPCICFG_0_PASSPW_FIELD                       (_MK_SHIFT_CONST(0x3) << SATA0_FPCICFG_0_PASSPW_SHIFT)
#define SATA0_FPCICFG_0_PASSPW_RANGE                       3:2
#define SATA0_FPCICFG_0_PASSPW_WOFFSET                     0
#define SATA0_FPCICFG_0_PASSPW_DEFAULT                     (_MK_MASK_CONST(0x00000000)
#define SATA0_FPCICFG_0_PASSPW_DEFAULT_MASK                (_MK_MASK_CONST(0x3)
#define SATA0_FPCICFG_0_PASSPW_SW_DEFAULT                  (_MK_MASK_CONST(0x00000000)
#define SATA0_FPCICFG_0_PASSPW_SW_DEFAULT_MASK             (_MK_MASK_CONST(0x3)
#define SATA0_FPCICFG_0_PASSPW_TOY                         _MK_ENUM_CONST(0x00000000)                                                       // RW--V
#define SATA0_FPCICFG_0_PASSPW_PASS                        _MK_ENUM_CONST(0x00000001)                                                       // RW--V
#define SATA0_FPCICFG_0_PASSPW_NOPASS                      _MK_ENUM_CONST(0x00000002)                                                       // RW--V
#define SATA0_FPCICFG_0_RSPPASSPW_SHIFT                     _MK_SHIFT_CONST(4)                                                              // RWWUF
#define SATA0_FPCICFG_0_RSPPASSPW_FIELD                    (_MK_SHIFT_CONST(0x3) << SATA0_FPCICFG_0_RSPPASSPW_SHIFT)
#define SATA0_FPCICFG_0_RSPPASSPW_RANGE                    5:4
#define SATA0_FPCICFG_0_RSPPASSPW_WOFFSET                  0
#define SATA0_FPCICFG_0_RSPPASSPW_DEFAULT                  (_MK_MASK_CONST(0x00000000)
#define SATA0_FPCICFG_0_RSPPASSPW_DEFAULT_MASK             (_MK_MASK_CONST(0x3)
#define SATA0_FPCICFG_0_RSPPASSPW_SW_DEFAULT               (_MK_MASK_CONST(0x00000000)
#define SATA0_FPCICFG_0_RSPPASSPW_SW_DEFAULT_MASK          (_MK_MASK_CONST(0x3)
#define SATA0_FPCICFG_0_RSPPASSPW_TOY                      _MK_ENUM_CONST(0x00000000)                                                       // RW--V
#define SATA0_FPCICFG_0_RSPPASSPW_PASS                     _MK_ENUM_CONST(0x00000001)                                                       // RW--V
#define SATA0_FPCICFG_0_RSPPASSPW_NOPASS                   _MK_ENUM_CONST(0x00000002)                                                       // RW--V
#define SATA0_FPCICFG_0_COHCMD_SHIFT                        _MK_SHIFT_CONST(6)                                                              // RWWUF
#define SATA0_FPCICFG_0_COHCMD_FIELD                       (_MK_SHIFT_CONST(0x3) << SATA0_FPCICFG_0_COHCMD_SHIFT)
#define SATA0_FPCICFG_0_COHCMD_RANGE                       7:6
#define SATA0_FPCICFG_0_COHCMD_WOFFSET                     0
#define SATA0_FPCICFG_0_COHCMD_DEFAULT                     (_MK_MASK_CONST(0x00000000)
#define SATA0_FPCICFG_0_COHCMD_DEFAULT_MASK                (_MK_MASK_CONST(0x3)
#define SATA0_FPCICFG_0_COHCMD_SW_DEFAULT                  (_MK_MASK_CONST(0x00000000)
#define SATA0_FPCICFG_0_COHCMD_SW_DEFAULT_MASK             (_MK_MASK_CONST(0x3)
#define SATA0_FPCICFG_0_COHCMD_TOY                         _MK_ENUM_CONST(0x00000000)                                                       // RW--V
#define SATA0_FPCICFG_0_COHCMD_COH                         _MK_ENUM_CONST(0x00000001)                                                       // RW--V
#define SATA0_FPCICFG_0_COHCMD_NONCOH                      _MK_ENUM_CONST(0x00000002)                                                       // RW--V
#define SATA0_FPCICFG_0_CREDIT_SYS_ENABLE_SHIFT             _MK_SHIFT_CONST(8)                                                              // RWWUF
#define SATA0_FPCICFG_0_CREDIT_SYS_ENABLE_FIELD            (_MK_SHIFT_CONST(0x1) << SATA0_FPCICFG_0_CREDIT_SYS_ENABLE_SHIFT)
#define SATA0_FPCICFG_0_CREDIT_SYS_ENABLE_RANGE            8:8
#define SATA0_FPCICFG_0_CREDIT_SYS_ENABLE_WOFFSET          0
#define SATA0_FPCICFG_0_CREDIT_SYS_ENABLE_DEFAULT          (_MK_MASK_CONST(0x00000000)
#define SATA0_FPCICFG_0_CREDIT_SYS_ENABLE_DEFAULT_MASK     (_MK_MASK_CONST(0x1)
#define SATA0_FPCICFG_0_CREDIT_SYS_ENABLE_SW_DEFAULT       (_MK_MASK_CONST(0x00000000)
#define SATA0_FPCICFG_0_CREDIT_SYS_ENABLE_SW_DEFAULT_MASK  (_MK_MASK_CONST(0x1)
#define SATA0_FPCICFG_0_CREDIT_SYS_ENABLE_OFF              _MK_ENUM_CONST(0x00000000)                                                       // RW--V
#define SATA0_FPCICFG_0_CREDIT_SYS_ENABLE_ON               _MK_ENUM_CONST(0x00000001)                                                       // RW--V
#define SATA0_FPCICFG_0_TGTDONE_PASSPW_SHIFT                _MK_SHIFT_CONST(14)                                                             // RWWUF
#define SATA0_FPCICFG_0_TGTDONE_PASSPW_FIELD               (_MK_SHIFT_CONST(0x1) << SATA0_FPCICFG_0_TGTDONE_PASSPW_SHIFT)
#define SATA0_FPCICFG_0_TGTDONE_PASSPW_RANGE               14:14
#define SATA0_FPCICFG_0_TGTDONE_PASSPW_WOFFSET             0
#define SATA0_FPCICFG_0_TGTDONE_PASSPW_DEFAULT             (_MK_MASK_CONST(0x00000001)
#define SATA0_FPCICFG_0_TGTDONE_PASSPW_DEFAULT_MASK        (_MK_MASK_CONST(0x1)
#define SATA0_FPCICFG_0_TGTDONE_PASSPW_SW_DEFAULT          (_MK_MASK_CONST(0x00000001)
#define SATA0_FPCICFG_0_TGTDONE_PASSPW_SW_DEFAULT_MASK     (_MK_MASK_CONST(0x1)
#define SATA0_FPCICFG_0_TGTDONE_PASSPW_SET                 _MK_ENUM_CONST(0x00000001)                                                       // RW--V
#define SATA0_FPCICFG_0_TGTDONE_PASSPW_CLR                 _MK_ENUM_CONST(0x00000000)                                                       // RW--V
#define SATA0_FPCICFG_0_ERR_SEVERITY_SHIFT                  _MK_SHIFT_CONST(15)                                                             // RWWUF
#define SATA0_FPCICFG_0_ERR_SEVERITY_FIELD                 (_MK_SHIFT_CONST(0x1) << SATA0_FPCICFG_0_ERR_SEVERITY_SHIFT)
#define SATA0_FPCICFG_0_ERR_SEVERITY_RANGE                 15:15
#define SATA0_FPCICFG_0_ERR_SEVERITY_WOFFSET               0
#define SATA0_FPCICFG_0_ERR_SEVERITY_DEFAULT               (_MK_MASK_CONST(0x00000001)
#define SATA0_FPCICFG_0_ERR_SEVERITY_DEFAULT_MASK          (_MK_MASK_CONST(0x1)
#define SATA0_FPCICFG_0_ERR_SEVERITY_SW_DEFAULT            (_MK_MASK_CONST(0x00000001)
#define SATA0_FPCICFG_0_ERR_SEVERITY_SW_DEFAULT_MASK       (_MK_MASK_CONST(0x1)
#define SATA0_FPCICFG_0_ERR_SEVERITY_NONFATAL              _MK_ENUM_CONST(0x00000000)                                                       // RW--V
#define SATA0_FPCICFG_0_ERR_SEVERITY_FATAL                 _MK_ENUM_CONST(0x00000001)                                                       // RW--V
#define SATA0_FPCICFG_0_NONISO_READ_CREDITS_SHIFT           _MK_SHIFT_CONST(16)                                                             // RWWUF
#define SATA0_FPCICFG_0_NONISO_READ_CREDITS_FIELD          (_MK_SHIFT_CONST(0x1f) << SATA0_FPCICFG_0_NONISO_READ_CREDITS_SHIFT)
#define SATA0_FPCICFG_0_NONISO_READ_CREDITS_RANGE          20:16
#define SATA0_FPCICFG_0_NONISO_READ_CREDITS_WOFFSET        0
#define SATA0_FPCICFG_0_NONISO_READ_CREDITS_DEFAULT        (_MK_MASK_CONST(0x0000000C)
#define SATA0_FPCICFG_0_NONISO_READ_CREDITS_DEFAULT_MASK   (_MK_MASK_CONST(0x1f)
#define SATA0_FPCICFG_0_NONISO_READ_CREDITS_SW_DEFAULT     (_MK_MASK_CONST(0x0000000C)
#define SATA0_FPCICFG_0_NONISO_READ_CREDITS_SW_DEFAULT_MASK (_MK_MASK_CONST(0x1f)
#define SATA0_FPCICFG_0_NONISO_READ_CREDITS_MIN            _MK_ENUM_CONST(0x00000000)                                                       // RW--V
#define SATA0_FPCICFG_0_NONISO_READ_CREDITS_MAX            _MK_ENUM_CONST(0x0000001F)                                                       // RW--V
#define SATA0_FPCICFG_0_PASSIVE_UID_CLMP_SHIFT              _MK_SHIFT_CONST(21)                                                             // R-WUF
#define SATA0_FPCICFG_0_PASSIVE_UID_CLMP_FIELD             (_MK_SHIFT_CONST(0x1) << SATA0_FPCICFG_0_PASSIVE_UID_CLMP_SHIFT)
#define SATA0_FPCICFG_0_PASSIVE_UID_CLMP_RANGE             21:21
#define SATA0_FPCICFG_0_PASSIVE_UID_CLMP_WOFFSET           0
#define SATA0_FPCICFG_0_PASSIVE_UID_CLMP_DEFAULT           (_MK_MASK_CONST(0x00000000)
#define SATA0_FPCICFG_0_PASSIVE_UID_CLMP_DEFAULT_MASK      (_MK_MASK_CONST(0x1)
#define SATA0_FPCICFG_0_PASSIVE_UID_CLMP_SW_DEFAULT        (_MK_MASK_CONST(0x00000000)
#define SATA0_FPCICFG_0_PASSIVE_UID_CLMP_SW_DEFAULT_MASK   (_MK_MASK_CONST(0x1)
#define SATA0_FPCICFG_0_PASSIVE_UID_CLMP_SUPP              _MK_ENUM_CONST(0x00000001)                                                       // R---V
#define SATA0_FPCICFG_0_PASSIVE_UID_CLMP_NOT_SUPP          _MK_ENUM_CONST(0x00000000)                                                       // R---V
#define SATA0_FPCICFG_0_PASSIVE_UID_CLMP_ENABLE_SHIFT       _MK_SHIFT_CONST(22)                                                             // RWWUF
#define SATA0_FPCICFG_0_PASSIVE_UID_CLMP_ENABLE_FIELD      (_MK_SHIFT_CONST(0x1) << SATA0_FPCICFG_0_PASSIVE_UID_CLMP_ENABLE_SHIFT)
#define SATA0_FPCICFG_0_PASSIVE_UID_CLMP_ENABLE_RANGE      22:22
#define SATA0_FPCICFG_0_PASSIVE_UID_CLMP_ENABLE_WOFFSET    0
#define SATA0_FPCICFG_0_PASSIVE_UID_CLMP_ENABLE_DEFAULT    (_MK_MASK_CONST(0x00000000)
#define SATA0_FPCICFG_0_PASSIVE_UID_CLMP_ENABLE_DEFAULT_MASK (_MK_MASK_CONST(0x1)
#define SATA0_FPCICFG_0_PASSIVE_UID_CLMP_ENABLE_SW_DEFAULT (_MK_MASK_CONST(0x00000000)
#define SATA0_FPCICFG_0_PASSIVE_UID_CLMP_ENABLE_SW_DEFAULT_MASK (_MK_MASK_CONST(0x1)
#define SATA0_FPCICFG_0_PASSIVE_UID_CLMP_ENABLE_SET        _MK_ENUM_CONST(0x00000001)                                                       // RW--V
#define SATA0_FPCICFG_0_PASSIVE_UID_CLMP_ENABLE_CLR        _MK_ENUM_CONST(0x00000000)                                                       // RWW-V
#define SATA0_FPCICFG_0_FIX_DEADLOCK_ENABLE_SHIFT           _MK_SHIFT_CONST(23)                                                             // RWWUF
#define SATA0_FPCICFG_0_FIX_DEADLOCK_ENABLE_FIELD          (_MK_SHIFT_CONST(0x1) << SATA0_FPCICFG_0_FIX_DEADLOCK_ENABLE_SHIFT)
#define SATA0_FPCICFG_0_FIX_DEADLOCK_ENABLE_RANGE          23:23
#define SATA0_FPCICFG_0_FIX_DEADLOCK_ENABLE_WOFFSET        0
#define SATA0_FPCICFG_0_FIX_DEADLOCK_ENABLE_DEFAULT        (_MK_MASK_CONST(0x00000001)
#define SATA0_FPCICFG_0_FIX_DEADLOCK_ENABLE_DEFAULT_MASK   (_MK_MASK_CONST(0x1)
#define SATA0_FPCICFG_0_FIX_DEADLOCK_ENABLE_SW_DEFAULT     (_MK_MASK_CONST(0x00000001)
#define SATA0_FPCICFG_0_FIX_DEADLOCK_ENABLE_SW_DEFAULT_MASK (_MK_MASK_CONST(0x1)
#define SATA0_FPCICFG_0_FIX_DEADLOCK_ENABLE_OFF            _MK_ENUM_CONST(0x00000000)                                                       // RW--V
#define SATA0_FPCICFG_0_FIX_DEADLOCK_ENABLE_ON             _MK_ENUM_CONST(0x00000001)                                                       // RW--V
#define SATA0_FPCICFG_0_DROP_ON_ERR_ENABLE_SHIFT            _MK_SHIFT_CONST(24)                                                             // RWWUF
#define SATA0_FPCICFG_0_DROP_ON_ERR_ENABLE_FIELD           (_MK_SHIFT_CONST(0x1) << SATA0_FPCICFG_0_DROP_ON_ERR_ENABLE_SHIFT)
#define SATA0_FPCICFG_0_DROP_ON_ERR_ENABLE_RANGE           24:24
#define SATA0_FPCICFG_0_DROP_ON_ERR_ENABLE_WOFFSET         0
#define SATA0_FPCICFG_0_DROP_ON_ERR_ENABLE_DEFAULT         (_MK_MASK_CONST(0x00000000)
#define SATA0_FPCICFG_0_DROP_ON_ERR_ENABLE_DEFAULT_MASK    (_MK_MASK_CONST(0x1)
#define SATA0_FPCICFG_0_DROP_ON_ERR_ENABLE_SW_DEFAULT      (_MK_MASK_CONST(0x00000000)
#define SATA0_FPCICFG_0_DROP_ON_ERR_ENABLE_SW_DEFAULT_MASK (_MK_MASK_CONST(0x1)
#define SATA0_FPCICFG_0_DROP_ON_ERR_ENABLE_OFF             _MK_ENUM_CONST(0x00000000)                                                       // RW--V
#define SATA0_FPCICFG_0_DROP_ON_ERR_ENABLE_ON              _MK_ENUM_CONST(0x00000001)                                                       // RW--V
#define SATA0_FPCICFG_0_DROP_ON_MA_ERR_ENABLE_SHIFT         _MK_SHIFT_CONST(25)                                                             // RWWUF
#define SATA0_FPCICFG_0_DROP_ON_MA_ERR_ENABLE_FIELD        (_MK_SHIFT_CONST(0x1) << SATA0_FPCICFG_0_DROP_ON_MA_ERR_ENABLE_SHIFT)
#define SATA0_FPCICFG_0_DROP_ON_MA_ERR_ENABLE_RANGE        25:25
#define SATA0_FPCICFG_0_DROP_ON_MA_ERR_ENABLE_WOFFSET      0
#define SATA0_FPCICFG_0_DROP_ON_MA_ERR_ENABLE_DEFAULT      (_MK_MASK_CONST(0x00000000)
#define SATA0_FPCICFG_0_DROP_ON_MA_ERR_ENABLE_DEFAULT_MASK (_MK_MASK_CONST(0x1)
#define SATA0_FPCICFG_0_DROP_ON_MA_ERR_ENABLE_SW_DEFAULT   (_MK_MASK_CONST(0x00000000)
#define SATA0_FPCICFG_0_DROP_ON_MA_ERR_ENABLE_SW_DEFAULT_MASK (_MK_MASK_CONST(0x1)
#define SATA0_FPCICFG_0_DROP_ON_MA_ERR_ENABLE_OFF          _MK_ENUM_CONST(0x00000000)                                                       // RW--V
#define SATA0_FPCICFG_0_DROP_ON_MA_ERR_ENABLE_ON           _MK_ENUM_CONST(0x00000001)                                                       // RW--V
#define SATA0_FPCICFG_0_DROP_ON_TA_ERR_ENABLE_SHIFT         _MK_SHIFT_CONST(26)                                                             // RWWUF
#define SATA0_FPCICFG_0_DROP_ON_TA_ERR_ENABLE_FIELD        (_MK_SHIFT_CONST(0x1) << SATA0_FPCICFG_0_DROP_ON_TA_ERR_ENABLE_SHIFT)
#define SATA0_FPCICFG_0_DROP_ON_TA_ERR_ENABLE_RANGE        26:26
#define SATA0_FPCICFG_0_DROP_ON_TA_ERR_ENABLE_WOFFSET      0
#define SATA0_FPCICFG_0_DROP_ON_TA_ERR_ENABLE_DEFAULT      (_MK_MASK_CONST(0x00000000)
#define SATA0_FPCICFG_0_DROP_ON_TA_ERR_ENABLE_DEFAULT_MASK (_MK_MASK_CONST(0x1)
#define SATA0_FPCICFG_0_DROP_ON_TA_ERR_ENABLE_SW_DEFAULT   (_MK_MASK_CONST(0x00000000)
#define SATA0_FPCICFG_0_DROP_ON_TA_ERR_ENABLE_SW_DEFAULT_MASK (_MK_MASK_CONST(0x1)
#define SATA0_FPCICFG_0_DROP_ON_TA_ERR_ENABLE_OFF          _MK_ENUM_CONST(0x00000000)                                                       // RW--V
#define SATA0_FPCICFG_0_DROP_ON_TA_ERR_ENABLE_ON           _MK_ENUM_CONST(0x00000001)                                                       // RW--V
#define SATA0_FPCICFG_0_DEVID_OVERRIDE_ENABLE_SHIFT         _MK_SHIFT_CONST(27)                                                             // RWWVF
#define SATA0_FPCICFG_0_DEVID_OVERRIDE_ENABLE_FIELD        (_MK_SHIFT_CONST(0x1) << SATA0_FPCICFG_0_DEVID_OVERRIDE_ENABLE_SHIFT)
#define SATA0_FPCICFG_0_DEVID_OVERRIDE_ENABLE_RANGE        27:27
#define SATA0_FPCICFG_0_DEVID_OVERRIDE_ENABLE_WOFFSET      0
#define SATA0_FPCICFG_0_DEVID_OVERRIDE_ENABLE_DEFAULT      (_MK_MASK_CONST(0)
#define SATA0_FPCICFG_0_DEVID_OVERRIDE_ENABLE_DEFAULT_MASK (_MK_MASK_CONST(0x1)
#define SATA0_FPCICFG_0_DEVID_OVERRIDE_ENABLE_SW_DEFAULT   (_MK_MASK_CONST(0)
#define SATA0_FPCICFG_0_DEVID_OVERRIDE_ENABLE_SW_DEFAULT_MASK (_MK_MASK_CONST(0x1)
#define SATA0_FPCICFG_0_DEVID_OVERRIDE_ENABLE_OFF          _MK_ENUM_CONST(0)                                                                // RWW-V
#define SATA0_FPCICFG_0_DEVID_OVERRIDE_ENABLE_ON           _MK_ENUM_CONST(1)                                                                // RW--V
#define SATA0_FPCICFG_0_DEVID_OVERRIDE_ID_SHIFT             _MK_SHIFT_CONST(28)                                                             // RWWUF
#define SATA0_FPCICFG_0_DEVID_OVERRIDE_ID_FIELD            (_MK_SHIFT_CONST(0xf) << SATA0_FPCICFG_0_DEVID_OVERRIDE_ID_SHIFT)
#define SATA0_FPCICFG_0_DEVID_OVERRIDE_ID_RANGE            31:28
#define SATA0_FPCICFG_0_DEVID_OVERRIDE_ID_WOFFSET          0
#define SATA0_FPCICFG_0_DEVID_OVERRIDE_ID_DEFAULT          (_MK_MASK_CONST(0x0)
#define SATA0_FPCICFG_0_DEVID_OVERRIDE_ID_DEFAULT_MASK     (_MK_MASK_CONST(0xf)
#define SATA0_FPCICFG_0_DEVID_OVERRIDE_ID_SW_DEFAULT       (_MK_MASK_CONST(0x0)
#define SATA0_FPCICFG_0_DEVID_OVERRIDE_ID_SW_DEFAULT_MASK  (_MK_MASK_CONST(0xf)
#define SATA0_FPCICFG_0_DEVID_OVERRIDE_ID__NOPRDCHK        _MK_ENUM_CONST(0x00000001)                                                       // ----V
#define SATA0_FPCICFG_0_DEVID_OVERRIDE_ID_DEFAULT_NBP      _MK_ENUM_CONST(0x0)                                                              // RW--V
// 
// 
// 
// 
// 
// 
// 
// 
// .LABEL PRIVATE INT_REL
// 
// .LABEL PUBLIC
// 
// .LABEL FUNC_BIOS
// 
// .TITLE PCI Configuration Register FCh
// 
// This register is a general purpose scratch register to be used for communication
// between the storage SW and the SBIOS.
// 
// .LABEL PRIVATE INT_REL
// This field is designed to be used to allow the SBIOS to communicate to the storage
// SW which ports are enabled for RAID operation.
// 
// .LABEL FUNC_BIOS
//  31           24 23           16 15            8 7             0
// .-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-.
// |0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0| SCRATCH_1
// +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
#define SATA0_SCRATCH_1_0                                  0x000000FC                                                                       // RW-4R
#define SATA0_SCRATCH_1_0_SECURE                           0
#define SATA0_SCRATCH_1_0_WORD_COUNT                       1
#define SATA0_SCRATCH_1_0_RESET_VAL                        0x0
#define SATA0_SCRATCH_1_0_RESET_MASK                       0x0
#define SATA0_SCRATCH_1_0_SW_DEFAULT_VAL                   0x0
#define SATA0_SCRATCH_1_0_SW_DEFAULT_MASK                  0x0
#define SATA0_SCRATCH_1_0_READ_MASK                        0xffffffff
#define SATA0_SCRATCH_1_0_WRITE_MASK                       0xffffffff
#define SATA0_SCRATCH_1_0_SBIOS_SHIFT                       _MK_SHIFT_CONST(0)                                                              // RWCUF
#define SATA0_SCRATCH_1_0_SBIOS_FIELD                      (_MK_SHIFT_CONST(0xffffffff) << SATA0_SCRATCH_1_0_SBIOS_SHIFT)
#define SATA0_SCRATCH_1_0_SBIOS_RANGE                      31:0
#define SATA0_SCRATCH_1_0_SBIOS_WOFFSET                    0
// 
// 
//         Figure 10-50  PCI SCRATCH_1 Register 54h
// .LABEL PRIVATE
// ###########################################################################################
//      257-2K Standard config space, capabilities, Index-data pair to access BAR5 (AHCI), CFG
//             Index-data pair to access beyond 256bytes of config space
//      0X100 - 0X3E4
// ###########################################################################################
// 
// .LABEL PUBLIC
// .LABEL ANALOG_PRIVATE INT_REL
// .TITLE Serial ATA internal phy control register used in nvoob
// 
// 20 + 2*ACTIVE_CNT_HIGH is the max number of 300mhz cycles squelch can be high for oob signaling.
// 20 + 2*ACTIVE_CNT_LOW is the min number of 300mhz cycles squelch can be high for oob signaling.
// 100 + 4*COMINIT_IDLE_CNT_HIGH is the max number of 300mhz cycles squelch can be low for cominit signaling.
// 50 + 4*COMINIT_IDLE_CNT_LOW is the min number of 300mhz cycles squelch can be low for cominit signaling.
// 32 + 2*COMWAKE_IDLE_CNT_HIGH is the max number of 300mhz cycles squelch can be low for comwake signaling.
// 2*COMWAKE_IDLE_CNT_LOW is the min number of 300mhz cycles squelch can be low for comwake signaling.
// .FIELD ACTIVE_CNT_HIGH
// Squelch can be high for a maximum of 20 + 2*ACTIVE_CNT_HIGH cycles at 300MHz for OOB signalling.
// .FIELD ACTIVE_CNT_LOW
// Squelch can be high for a mininum of 20 + 2*ACTIVE_CNT_LOW cycles at 300MHz for OOB signalling.
// .FIELD COMINIT_IDLE_CNT_HIGH
// Squelch can be high for a maximum of 100 + 4*COMINIT_IDLE_CNT_HIGH cycles at 300MHz for COMINIT signalling.
// .FIELD COMINIT_IDLE_CNT_LOW
// Squelch can be high for a minimum of 50 + 4*COMINIT_IDLE_CNT_LOW cycles at 300MHz for COMINIT signalling.
// .FIELD COMWAKE_IDLE_CNT_HIGH
// Squelch can be high for a maximum of 32 + 2*COMWAKE_IDLE_CNT_HIGH cycles at 300MHz for COMWAKE signalling.
// .FIELD COMWAKE_IDLE_CNT_LOW
// Squelch can be high for a minimum of 2*COMWAKE_IDLE_CNT_LOW cycles at 300MHz for COMWAKE signalling.
// .FIELD SQUELCH_FILTER_MODE
// This field selects squelch signal filtering mode.  When FILTER_MODE_LOW is selected, high-low-high glitches
// are filtered out.  When FILTER_MODE_HIGH is selected, low-high-low glitches are filtered out.
// .FIELD SQUELCH_FILTER_LENGTH
// (SQUELCH_FILTER_LENGTH+1)*6.66ns is the amount of glitch duration that are filtered out.
// .FIELD COMMA_CNT
// COMMA_CNT*16 is the number of comma characters seen for the phy_rdy to go high after going through OOB signalling.
// .FIELD RETIMED_FAREND_LOOPBACK_EN
// This field when enabled puts the sata in farend retimed loopback mode.
// 
// 
// .LABEL PRIVATE
// 20 + 2*ACTIVE_CNT_HIGH is the max number of 300mhz cycles squelch can be high for oob signaling.
// 20 + 2*ACTIVE_CNT_LOW is the min number of 300mhz cycles squelch can be high for oob signaling.
// 100 + 4*COMINIT_IDLE_CNT_HIGH is the max number of 300mhz cycles squelch can be low for cominit signaling.
// 50 + 4*COMINIT_IDLE_CNT_LOW is the min number of 300mhz cycles squelch can be low for cominit signaling.
// 32 + 2*COMWAKE_IDLE_CNT_HIGH is the max number of 300mhz cycles squelch can be low for comwake signaling.
// 2*COMWAKE_IDLE_CNT_LOW is the min number of 300mhz cycles squelch can be low for comwake signaling.
// SQUELCH_FILTER_MODE selects squelch signal filtering mode.  When FILTER_MODE_LOW is selcted, high-low-high
// glitches are filtered out.  When FILTER_MODE_HIGH is selected, low-high-low glitches are filtered out.
// SQUELCH_FILTER_LENGTH+1 is the number of bytes (6.66ns) of glitch duration that are filtered out.
// RETIMED_FAREND_LOOPBACK_EN puts the sata in farend retimed loopback mode.
// COMMA_CNT*16 is the number of commas seen for the phy_rdy to go high after going through oob.
// 
// 
// .LABEL ANALOG_PRIVATE INT_REL
//  31           24 23           16 15            8 7             0
// .-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-.
// |0 0 0 0|   |   |       |       |       |       |       |       | NVOOB
// `-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-'
// 
#define SATA0_NVOOB_0                                      0x00000114                                                                       // RWC4R
#define SATA0_NVOOB_0_SECURE                               0
#define SATA0_NVOOB_0_WORD_COUNT                           1
#define SATA0_NVOOB_0_RESET_VAL                            0x0
#define SATA0_NVOOB_0_RESET_MASK                           0x0
#define SATA0_NVOOB_0_SW_DEFAULT_VAL                       0x0
#define SATA0_NVOOB_0_SW_DEFAULT_MASK                      0x0
#define SATA0_NVOOB_0_READ_MASK                            0x8fff0000
#define SATA0_NVOOB_0_WRITE_MASK                           0x8fff0000
#define SATA0_NVOOB_0_COMMA_CNT_SHIFT                       _MK_SHIFT_CONST(16)                                                             // RWCVF
#define SATA0_NVOOB_0_COMMA_CNT_FIELD                      (_MK_SHIFT_CONST(0xff) << SATA0_NVOOB_0_COMMA_CNT_SHIFT)
#define SATA0_NVOOB_0_COMMA_CNT_RANGE                      23:16
#define SATA0_NVOOB_0_COMMA_CNT_WOFFSET                    0
#define SATA0_NVOOB_0_SQUELCH_FILTER_MODE_SHIFT             _MK_SHIFT_CONST(24)                                                             // RWCVF
#define SATA0_NVOOB_0_SQUELCH_FILTER_MODE_FIELD            (_MK_SHIFT_CONST(0x3) << SATA0_NVOOB_0_SQUELCH_FILTER_MODE_SHIFT)
#define SATA0_NVOOB_0_SQUELCH_FILTER_MODE_RANGE            25:24
#define SATA0_NVOOB_0_SQUELCH_FILTER_MODE_WOFFSET          0
#define SATA0_NVOOB_0_SQUELCH_FILTER_MODE_NONE             _MK_ENUM_CONST(0x00000000)                                                       // RW--V
#define SATA0_NVOOB_0_SQUELCH_FILTER_MODE_LOW              _MK_ENUM_CONST(0x00000001)                                                       // RWC-V
#define SATA0_NVOOB_0_SQUELCH_FILTER_MODE_HIGH             _MK_ENUM_CONST(0x00000002)                                                       // RW--V
#define SATA0_NVOOB_0_SQUELCH_FILTER_LENGTH_SHIFT           _MK_SHIFT_CONST(26)                                                             // RWCVF
#define SATA0_NVOOB_0_SQUELCH_FILTER_LENGTH_FIELD          (_MK_SHIFT_CONST(0x3) << SATA0_NVOOB_0_SQUELCH_FILTER_LENGTH_SHIFT)
#define SATA0_NVOOB_0_SQUELCH_FILTER_LENGTH_RANGE          27:26
#define SATA0_NVOOB_0_SQUELCH_FILTER_LENGTH_WOFFSET        0
#define SATA0_NVOOB_0_SQUELCH_FILTER_LENGTH_0              _MK_ENUM_CONST(0x00000003)                                                       // RWC-V
#define SATA0_NVOOB_0_RETIMED_FAREND_LOOPBACK_EN_SHIFT      _MK_SHIFT_CONST(31)                                                             // RWCVF
#define SATA0_NVOOB_0_RETIMED_FAREND_LOOPBACK_EN_FIELD     (_MK_SHIFT_CONST(0x1) << SATA0_NVOOB_0_RETIMED_FAREND_LOOPBACK_EN_SHIFT)
#define SATA0_NVOOB_0_RETIMED_FAREND_LOOPBACK_EN_RANGE     31:31
#define SATA0_NVOOB_0_RETIMED_FAREND_LOOPBACK_EN_WOFFSET   0
#define SATA0_NVOOB_0_RETIMED_FAREND_LOOPBACK_EN_0         _MK_ENUM_CONST(0x00000000)                                                       // RWC-V
// 
// 
//         Figure 10-02  Serial ATA Channel Control Register 114h
// .LABEL PUBLIC
// 
// .LABEL PRIVATE INT_REL
// .TITLE SATA CROSS BAR
// .FIELD PHY_SEL
// This register contains the phy_select - indicates how a Lane(brick) is connected to the port.
//  31           24 23           16 15            8 7             0
// .-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-.
// |0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0| CROSS_BAR
// +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
#define SATA0_CROSS_BAR_0                                  0x00000118                                                                       // RW-4R
#define SATA0_CROSS_BAR_0_SECURE                           0
#define SATA0_CROSS_BAR_0_WORD_COUNT                       1
#define SATA0_CROSS_BAR_0_RESET_VAL                        0x0
#define SATA0_CROSS_BAR_0_RESET_MASK                       0x0
#define SATA0_CROSS_BAR_0_SW_DEFAULT_VAL                   0x0
#define SATA0_CROSS_BAR_0_SW_DEFAULT_MASK                  0x0
#define SATA0_CROSS_BAR_0_READ_MASK                        0xffffffff
#define SATA0_CROSS_BAR_0_WRITE_MASK                       0xffffffff
#define SATA0_CROSS_BAR_0_PHY_SEL_SHIFT                     _MK_SHIFT_CONST(0)                                                              // RWCVF
#define SATA0_CROSS_BAR_0_PHY_SEL_FIELD                    (_MK_SHIFT_CONST(0xffffffff) << SATA0_CROSS_BAR_0_PHY_SEL_SHIFT)
#define SATA0_CROSS_BAR_0_PHY_SEL_RANGE                    31:0
#define SATA0_CROSS_BAR_0_PHY_SEL_WOFFSET                  0
// 
// 
//         Figure 10-03 CROSS BAR for BRICK
// .LABEL PUBLIC
// 
// 
// .LABEL ANALOG_PUBLIC
// .TITLE SATA PHY Control Register
// This register contains various bits to control the PHY.
// 
// FORCE_CORE_CLAMP -- is used to enable core clock clamp.  Software can only set
//                     this bit when the controller is idle.  Any downstream cycle,
//             including a read to this register,
//                     will wake up core clock automatically, and core_act_sts
//                     will change to 0x0.  Software needs no future action to
//                     un-clamp the clock.  But software needs to write 1 to this
//                     bit to re-clamp the clock when the controller is idle.
//     Note: Wake from core clock clamp can be done by a downstream cycle which will
//           trigger the core_wake signal to PMU; or by hotplug event which will
//           trigger the dev_wake signal.
// .LABEL ANALOG_PRIVATE
// FORCE_DEV1_CLAMP -- is used to enable dev clock clamp for Ch1.  This bit can only
//                     be set when the SATA port is disabled.  And no hotplug is
//                     supported when the dev clock is clamped.
// FORCE_DEV2_CLAMP -- is used to enable dev clock clamp for Ch2.
//                     Same as FORCE_DEV1_CLAMP.
// .LABEL ANALOG_PUBLIC
// DEV_STS_HOLD     -- # of txclk cycles to hold the dev_act_tog and dev_act_sts.
// CORE_STS         -- current core_act_sts.
// DEV_STS          -- current dev_act_sts.
// 
// 31           24 23           16 15            8 7             0
// .-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-.
// |0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0| PMUCTL
// `-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-'
// 
#define SATA0_PMUCTL_0                                     0x0000011C                                                                       // RWW4R
#define SATA0_PMUCTL_0_SECURE                              0
#define SATA0_PMUCTL_0_WORD_COUNT                          1
#define SATA0_PMUCTL_0_RESET_VAL                           0x0
#define SATA0_PMUCTL_0_RESET_MASK                          0x0
#define SATA0_PMUCTL_0_SW_DEFAULT_VAL                      0x0
#define SATA0_PMUCTL_0_SW_DEFAULT_MASK                     0x0
#define SATA0_PMUCTL_0_READ_MASK                           0xffff01ff
#define SATA0_PMUCTL_0_WRITE_MASK                          0xff0104
#define SATA0_PMUCTL_0_RSVD_0_1_SHIFT                       _MK_SHIFT_CONST(0)                                                              // C--VF
#define SATA0_PMUCTL_0_RSVD_0_1_FIELD                      (_MK_SHIFT_CONST(0x3) << SATA0_PMUCTL_0_RSVD_0_1_SHIFT)
#define SATA0_PMUCTL_0_RSVD_0_1_RANGE                      1:0
#define SATA0_PMUCTL_0_RSVD_0_1_WOFFSET                    0
#define SATA0_PMUCTL_0_RSVD_0_1_VAL                        _MK_ENUM_CONST(0x00000000)                                                       // C---V
#define SATA0_PMUCTL_0_FORCE_CORE_CLAMP_SHIFT               _MK_SHIFT_CONST(2)                                                              // RWCVF
#define SATA0_PMUCTL_0_FORCE_CORE_CLAMP_FIELD              (_MK_SHIFT_CONST(0x1) << SATA0_PMUCTL_0_FORCE_CORE_CLAMP_SHIFT)
#define SATA0_PMUCTL_0_FORCE_CORE_CLAMP_RANGE              2:2
#define SATA0_PMUCTL_0_FORCE_CORE_CLAMP_WOFFSET            0
#define SATA0_PMUCTL_0_FORCE_CORE_CLAMP_EN                 _MK_ENUM_CONST(0x00000001)                                                       // RW--V
#define SATA0_PMUCTL_0_FORCE_CORE_CLAMP_DIS                _MK_ENUM_CONST(0x00000000)                                                       // RWC-V
#define SATA0_PMUCTL_0_RSVD_3_7_SHIFT                       _MK_SHIFT_CONST(3)                                                              // C--VF
#define SATA0_PMUCTL_0_RSVD_3_7_FIELD                      (_MK_SHIFT_CONST(0x1f) << SATA0_PMUCTL_0_RSVD_3_7_SHIFT)
#define SATA0_PMUCTL_0_RSVD_3_7_RANGE                      7:3
#define SATA0_PMUCTL_0_RSVD_3_7_WOFFSET                    0
#define SATA0_PMUCTL_0_RSVD_3_7_VAL                        _MK_ENUM_CONST(0x00000000)                                                       // C---V
#define SATA0_PMUCTL_0_HOLD_SEND_ALIGN_DIS_SHIFT            _MK_SHIFT_CONST(8)                                                              // RWC-F
#define SATA0_PMUCTL_0_HOLD_SEND_ALIGN_DIS_FIELD           (_MK_SHIFT_CONST(0x1) << SATA0_PMUCTL_0_HOLD_SEND_ALIGN_DIS_SHIFT)
#define SATA0_PMUCTL_0_HOLD_SEND_ALIGN_DIS_RANGE           8:8
#define SATA0_PMUCTL_0_HOLD_SEND_ALIGN_DIS_WOFFSET         0
#define SATA0_PMUCTL_0_HOLD_SEND_ALIGN_DIS_NO              _MK_ENUM_CONST(0x00000000)                                                       // R---V
#define SATA0_PMUCTL_0_HOLD_SEND_ALIGN_DIS_YES             _MK_ENUM_CONST(0x00000001)                                                       // R---V
#define SATA0_PMUCTL_0_DEV_STS_HOLD_SHIFT                   _MK_SHIFT_CONST(16)                                                             // RWC-F
#define SATA0_PMUCTL_0_DEV_STS_HOLD_FIELD                  (_MK_SHIFT_CONST(0xff) << SATA0_PMUCTL_0_DEV_STS_HOLD_SHIFT)
#define SATA0_PMUCTL_0_DEV_STS_HOLD_RANGE                  23:16
#define SATA0_PMUCTL_0_DEV_STS_HOLD_WOFFSET                0
#define SATA0_PMUCTL_0_CORE_STS_SHIFT                       _MK_SHIFT_CONST(24)                                                             // R-W-F
#define SATA0_PMUCTL_0_CORE_STS_FIELD                      (_MK_SHIFT_CONST(0xf) << SATA0_PMUCTL_0_CORE_STS_SHIFT)
#define SATA0_PMUCTL_0_CORE_STS_RANGE                      27:24
#define SATA0_PMUCTL_0_CORE_STS_WOFFSET                    0
#define SATA0_PMUCTL_0_CORE_STS_DEFAULT                    (_MK_MASK_CONST(0x00000000)
#define SATA0_PMUCTL_0_CORE_STS_DEFAULT_MASK               (_MK_MASK_CONST(0xf)
#define SATA0_PMUCTL_0_CORE_STS_SW_DEFAULT                 (_MK_MASK_CONST(0x00000000)
#define SATA0_PMUCTL_0_CORE_STS_SW_DEFAULT_MASK            (_MK_MASK_CONST(0xf)
#define SATA0_PMUCTL_0_RSVD_31_28_SHIFT                     _MK_SHIFT_CONST(28)                                                             // C--VF
#define SATA0_PMUCTL_0_RSVD_31_28_FIELD                    (_MK_SHIFT_CONST(0xf) << SATA0_PMUCTL_0_RSVD_31_28_SHIFT)
#define SATA0_PMUCTL_0_RSVD_31_28_RANGE                    31:28
#define SATA0_PMUCTL_0_RSVD_31_28_WOFFSET                  0
#define SATA0_PMUCTL_0_RSVD_31_28_VAL                      _MK_ENUM_CONST(0x00000000)                                                       // C---V
// 
//         Figure 10-04 PMUCTL of PHY
// .LABEL PUBLIC
// 
// .LABEL INT_REL
// .TITLE CFG_PHY_0
// .LABEL PRIVATE INT_REL
// .FIELD RBC_RESET_DELAY
// RBC_RESET_DELAY is the number of tx_clk ticks (300MHz) between the
// deassertion of sata2phy_ch{1,2}_cdr_reset and the release of
// ch{1,2}_rbc_reset_.
// 
// .LABEL PRIVATE INT_REL
// .FIELD SSTS_DET_1_IN_PART_SLUMBER
// This bit when set indicates that ssts_det will be made one when we goto PARTIAL/ SLUMBER, else zero
// 
// .LABEL PRIVATE INT_REL
// .FIELD DONT_INSERT_ALIGNS_IN_BIST_L
// This bit when set indicates that Aligns will not be inserted when in BIST_L mode to avoid overflow
// 
// .LABEL PRIVATE INT_REL
// .FIELD SEND_COMRESET_ON_WARMRESET
// this bit set indicates that COMRESET will not be sent on a WARM_RESET, it will be sent only when SCTL_DET is written
// 
// .LABEL PRIVATE INT_REL
// 31           24 23           16 15            8 7             0
// .-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-.
// |0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0| CFG_PHY_0
// `-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-'
// 
#define SATA0_CFG_PHY_0_0                                  0x00000120                                                                       // RWC4R
#define SATA0_CFG_PHY_0_0_SECURE                           0
#define SATA0_CFG_PHY_0_0_WORD_COUNT                       1
#define SATA0_CFG_PHY_0_0_RESET_VAL                        0x0
#define SATA0_CFG_PHY_0_0_RESET_MASK                       0x0
#define SATA0_CFG_PHY_0_0_SW_DEFAULT_VAL                   0x0
#define SATA0_CFG_PHY_0_0_SW_DEFAULT_MASK                  0x0
#define SATA0_CFG_PHY_0_0_READ_MASK                        0xffffffff
#define SATA0_CFG_PHY_0_0_WRITE_MASK                       0xffffffff
#define SATA0_CFG_PHY_0_0_RBC_RESET_DELAY_SHIFT             _MK_SHIFT_CONST(0)                                                              // RWCVF
#define SATA0_CFG_PHY_0_0_RBC_RESET_DELAY_FIELD            (_MK_SHIFT_CONST(0x1f) << SATA0_CFG_PHY_0_0_RBC_RESET_DELAY_SHIFT)
#define SATA0_CFG_PHY_0_0_RBC_RESET_DELAY_RANGE            4:0
#define SATA0_CFG_PHY_0_0_RBC_RESET_DELAY_WOFFSET          0
#define SATA0_CFG_PHY_0_0_RBC_RESET_DELAY__WRNPRDCHK       _MK_ENUM_CONST(0x00000001)                                                       // ----V
#define SATA0_CFG_PHY_0_0_PLL_IDDQ_OVERRIDE_SHIFT           _MK_SHIFT_CONST(5)                                                              // RWCVF
#define SATA0_CFG_PHY_0_0_PLL_IDDQ_OVERRIDE_FIELD          (_MK_SHIFT_CONST(0x1) << SATA0_CFG_PHY_0_0_PLL_IDDQ_OVERRIDE_SHIFT)
#define SATA0_CFG_PHY_0_0_PLL_IDDQ_OVERRIDE_RANGE          5:5
#define SATA0_CFG_PHY_0_0_PLL_IDDQ_OVERRIDE_WOFFSET        0
#define SATA0_CFG_PHY_0_0_PLL_IDDQ_OVERRIDE_YES            _MK_ENUM_CONST(0x00000001)                                                       // RWC-V
#define SATA0_CFG_PHY_0_0_PLL_IDDQ_OVERRIDE_NO             _MK_ENUM_CONST(0x00000000)                                                       // RW--V
#define SATA0_CFG_PHY_0_0_PLL_IDDQ_OVERRIDE_VAL_SHIFT       _MK_SHIFT_CONST(6)                                                              // RWCVF
#define SATA0_CFG_PHY_0_0_PLL_IDDQ_OVERRIDE_VAL_FIELD      (_MK_SHIFT_CONST(0x1) << SATA0_CFG_PHY_0_0_PLL_IDDQ_OVERRIDE_VAL_SHIFT)
#define SATA0_CFG_PHY_0_0_PLL_IDDQ_OVERRIDE_VAL_RANGE      6:6
#define SATA0_CFG_PHY_0_0_PLL_IDDQ_OVERRIDE_VAL_WOFFSET    0
#define SATA0_CFG_PHY_0_0_PLL_IDDQ_OVERRIDE_VAL_YES        _MK_ENUM_CONST(0x00000001)                                                       // RW--V
#define SATA0_CFG_PHY_0_0_PLL_IDDQ_OVERRIDE_VAL_NO         _MK_ENUM_CONST(0x00000000)                                                       // RWC-V
#define SATA0_CFG_PHY_0_0_SSTS_DET_1_IN_PART_SLUMBER_SHIFT  _MK_SHIFT_CONST(7)                                                              // RWCVF
#define SATA0_CFG_PHY_0_0_SSTS_DET_1_IN_PART_SLUMBER_FIELD (_MK_SHIFT_CONST(0x1) << SATA0_CFG_PHY_0_0_SSTS_DET_1_IN_PART_SLUMBER_SHIFT)
#define SATA0_CFG_PHY_0_0_SSTS_DET_1_IN_PART_SLUMBER_RANGE 7:7
#define SATA0_CFG_PHY_0_0_SSTS_DET_1_IN_PART_SLUMBER_WOFFSET 0
#define SATA0_CFG_PHY_0_0_SSTS_DET_1_IN_PART_SLUMBER_YES   _MK_ENUM_CONST(0x00000001)                                                       // RWC-V
#define SATA0_CFG_PHY_0_0_SSTS_DET_1_IN_PART_SLUMBER_NO    _MK_ENUM_CONST(0x00000000)                                                       // RW--V
#define SATA0_CFG_PHY_0_0_DONT_INSERT_ALIGNS_IN_BIST_L_SHIFT  _MK_SHIFT_CONST(8)                                                              // RWCVF
#define SATA0_CFG_PHY_0_0_DONT_INSERT_ALIGNS_IN_BIST_L_FIELD (_MK_SHIFT_CONST(0x1) << SATA0_CFG_PHY_0_0_DONT_INSERT_ALIGNS_IN_BIST_L_SHIFT)
#define SATA0_CFG_PHY_0_0_DONT_INSERT_ALIGNS_IN_BIST_L_RANGE 8:8
#define SATA0_CFG_PHY_0_0_DONT_INSERT_ALIGNS_IN_BIST_L_WOFFSET 0
#define SATA0_CFG_PHY_0_0_DONT_INSERT_ALIGNS_IN_BIST_L_YES _MK_ENUM_CONST(0x00000001)                                                       // RWC-V
#define SATA0_CFG_PHY_0_0_DONT_INSERT_ALIGNS_IN_BIST_L_NO  _MK_ENUM_CONST(0x00000000)                                                       // RW--V
#define SATA0_CFG_PHY_0_0_SEND_COMRESET_ON_WARMRESET_SHIFT  _MK_SHIFT_CONST(9)                                                              // RWCVF
#define SATA0_CFG_PHY_0_0_SEND_COMRESET_ON_WARMRESET_FIELD (_MK_SHIFT_CONST(0x1) << SATA0_CFG_PHY_0_0_SEND_COMRESET_ON_WARMRESET_SHIFT)
#define SATA0_CFG_PHY_0_0_SEND_COMRESET_ON_WARMRESET_RANGE 9:9
#define SATA0_CFG_PHY_0_0_SEND_COMRESET_ON_WARMRESET_WOFFSET 0
#define SATA0_CFG_PHY_0_0_SEND_COMRESET_ON_WARMRESET_YES   _MK_ENUM_CONST(0x00000001)                                                       // RW--V
#define SATA0_CFG_PHY_0_0_SEND_COMRESET_ON_WARMRESET_NO    _MK_ENUM_CONST(0x00000000)                                                       // RWC-V
#define SATA0_CFG_PHY_0_0_OOB_COMINIT_UNMASK_SHIFT          _MK_SHIFT_CONST(10)                                                             // RWCVF
#define SATA0_CFG_PHY_0_0_OOB_COMINIT_UNMASK_FIELD         (_MK_SHIFT_CONST(0x1) << SATA0_CFG_PHY_0_0_OOB_COMINIT_UNMASK_SHIFT)
#define SATA0_CFG_PHY_0_0_OOB_COMINIT_UNMASK_RANGE         10:10
#define SATA0_CFG_PHY_0_0_OOB_COMINIT_UNMASK_WOFFSET       0
#define SATA0_CFG_PHY_0_0_OOB_COMINIT_UNMASK_YES           _MK_ENUM_CONST(0x00000001)                                                       // RWC-V
#define SATA0_CFG_PHY_0_0_OOB_COMINIT_UNMASK_NO            _MK_ENUM_CONST(0x00000000)                                                       // RW--V
#define SATA0_CFG_PHY_0_0_USE_7BIT_ALIGN_DET_FOR_SPD_SHIFT  _MK_SHIFT_CONST(11)                                                             // RWCVF
#define SATA0_CFG_PHY_0_0_USE_7BIT_ALIGN_DET_FOR_SPD_FIELD (_MK_SHIFT_CONST(0x1) << SATA0_CFG_PHY_0_0_USE_7BIT_ALIGN_DET_FOR_SPD_SHIFT)
#define SATA0_CFG_PHY_0_0_USE_7BIT_ALIGN_DET_FOR_SPD_RANGE 11:11
#define SATA0_CFG_PHY_0_0_USE_7BIT_ALIGN_DET_FOR_SPD_WOFFSET 0
#define SATA0_CFG_PHY_0_0_USE_7BIT_ALIGN_DET_FOR_SPD_YES   _MK_ENUM_CONST(0x00000001)                                                       // RW--V
#define SATA0_CFG_PHY_0_0_USE_7BIT_ALIGN_DET_FOR_SPD_NO    _MK_ENUM_CONST(0x00000000)                                                       // RWC-V
#define SATA0_CFG_PHY_0_0_TX_SLEEP_SLUMBER_SHIFT            _MK_SHIFT_CONST(12)                                                             // RWCVF
#define SATA0_CFG_PHY_0_0_TX_SLEEP_SLUMBER_FIELD           (_MK_SHIFT_CONST(0x3) << SATA0_CFG_PHY_0_0_TX_SLEEP_SLUMBER_SHIFT)
#define SATA0_CFG_PHY_0_0_TX_SLEEP_SLUMBER_RANGE           13:12
#define SATA0_CFG_PHY_0_0_TX_SLEEP_SLUMBER_WOFFSET         0
#define SATA0_CFG_PHY_0_0_TX_SLEEP_SLUMBER_INIT            _MK_ENUM_CONST(0x00000002)                                                       // RWC-V
#define SATA0_CFG_PHY_0_0_TX_SLEEP_PARTIAL_SHIFT            _MK_SHIFT_CONST(14)                                                             // RWCVF
#define SATA0_CFG_PHY_0_0_TX_SLEEP_PARTIAL_FIELD           (_MK_SHIFT_CONST(0x3) << SATA0_CFG_PHY_0_0_TX_SLEEP_PARTIAL_SHIFT)
#define SATA0_CFG_PHY_0_0_TX_SLEEP_PARTIAL_RANGE           15:14
#define SATA0_CFG_PHY_0_0_TX_SLEEP_PARTIAL_WOFFSET         0
#define SATA0_CFG_PHY_0_0_TX_SLEEP_PARTIAL_INIT            _MK_ENUM_CONST(0x00000002)                                                       // RWC-V
#define SATA0_CFG_PHY_0_0_TX_SLEEP_ACTIVE_SHIFT             _MK_SHIFT_CONST(16)                                                             // RWCVF
#define SATA0_CFG_PHY_0_0_TX_SLEEP_ACTIVE_FIELD            (_MK_SHIFT_CONST(0x3) << SATA0_CFG_PHY_0_0_TX_SLEEP_ACTIVE_SHIFT)
#define SATA0_CFG_PHY_0_0_TX_SLEEP_ACTIVE_RANGE            17:16
#define SATA0_CFG_PHY_0_0_TX_SLEEP_ACTIVE_WOFFSET          0
#define SATA0_CFG_PHY_0_0_TX_SLEEP_ACTIVE_INIT             _MK_ENUM_CONST(0x00000000)                                                       // RWC-V
#define SATA0_CFG_PHY_0_0_RX_SLEEP_SLUMBER_SHIFT            _MK_SHIFT_CONST(18)                                                             // RWCVF
#define SATA0_CFG_PHY_0_0_RX_SLEEP_SLUMBER_FIELD           (_MK_SHIFT_CONST(0x3) << SATA0_CFG_PHY_0_0_RX_SLEEP_SLUMBER_SHIFT)
#define SATA0_CFG_PHY_0_0_RX_SLEEP_SLUMBER_RANGE           19:18
#define SATA0_CFG_PHY_0_0_RX_SLEEP_SLUMBER_WOFFSET         0
#define SATA0_CFG_PHY_0_0_RX_SLEEP_SLUMBER_INIT            _MK_ENUM_CONST(0x00000002)                                                       // RWC-V
#define SATA0_CFG_PHY_0_0_RX_SLEEP_PARTIAL_SHIFT            _MK_SHIFT_CONST(20)                                                             // RWCVF
#define SATA0_CFG_PHY_0_0_RX_SLEEP_PARTIAL_FIELD           (_MK_SHIFT_CONST(0x3) << SATA0_CFG_PHY_0_0_RX_SLEEP_PARTIAL_SHIFT)
#define SATA0_CFG_PHY_0_0_RX_SLEEP_PARTIAL_RANGE           21:20
#define SATA0_CFG_PHY_0_0_RX_SLEEP_PARTIAL_WOFFSET         0
#define SATA0_CFG_PHY_0_0_RX_SLEEP_PARTIAL_INIT            _MK_ENUM_CONST(0x00000002)                                                       // RWC-V
#define SATA0_CFG_PHY_0_0_RX_SLEEP_ACTIVE_SHIFT             _MK_SHIFT_CONST(22)                                                             // RWCVF
#define SATA0_CFG_PHY_0_0_RX_SLEEP_ACTIVE_FIELD            (_MK_SHIFT_CONST(0x3) << SATA0_CFG_PHY_0_0_RX_SLEEP_ACTIVE_SHIFT)
#define SATA0_CFG_PHY_0_0_RX_SLEEP_ACTIVE_RANGE            23:22
#define SATA0_CFG_PHY_0_0_RX_SLEEP_ACTIVE_WOFFSET          0
#define SATA0_CFG_PHY_0_0_RX_SLEEP_ACTIVE_INIT             _MK_ENUM_CONST(0x00000000)                                                       // RWC-V
#define SATA0_CFG_PHY_0_0_MASK_SQUELCH_SHIFT                _MK_SHIFT_CONST(24)                                                             // RWCVF
#define SATA0_CFG_PHY_0_0_MASK_SQUELCH_FIELD               (_MK_SHIFT_CONST(0x1) << SATA0_CFG_PHY_0_0_MASK_SQUELCH_SHIFT)
#define SATA0_CFG_PHY_0_0_MASK_SQUELCH_RANGE               24:24
#define SATA0_CFG_PHY_0_0_MASK_SQUELCH_WOFFSET             0
#define SATA0_CFG_PHY_0_0_MASK_SQUELCH_YES                 _MK_ENUM_CONST(0x00000001)                                                       // RWC-V
#define SATA0_CFG_PHY_0_0_MASK_SQUELCH_NO                  _MK_ENUM_CONST(0x00000000)                                                       // RW--V
#define SATA0_CFG_PHY_0_0_ASSERT_PHYRDY_FOR_BIST_SHIFT      _MK_SHIFT_CONST(25)                                                             // RWCVF
#define SATA0_CFG_PHY_0_0_ASSERT_PHYRDY_FOR_BIST_FIELD     (_MK_SHIFT_CONST(0x1) << SATA0_CFG_PHY_0_0_ASSERT_PHYRDY_FOR_BIST_SHIFT)
#define SATA0_CFG_PHY_0_0_ASSERT_PHYRDY_FOR_BIST_RANGE     25:25
#define SATA0_CFG_PHY_0_0_ASSERT_PHYRDY_FOR_BIST_WOFFSET   0
#define SATA0_CFG_PHY_0_0_ASSERT_PHYRDY_FOR_BIST_YES       _MK_ENUM_CONST(0x00000001)                                                       // RWC-V
#define SATA0_CFG_PHY_0_0_ASSERT_PHYRDY_FOR_BIST_NO        _MK_ENUM_CONST(0x00000000)                                                       // RW--V
#define SATA0_CFG_PHY_0_0_ASSERT_PHYRDY_EVEN_NOT_HRRDY_SHIFT  _MK_SHIFT_CONST(26)                                                             // RWCVF
#define SATA0_CFG_PHY_0_0_ASSERT_PHYRDY_EVEN_NOT_HRRDY_FIELD (_MK_SHIFT_CONST(0x1) << SATA0_CFG_PHY_0_0_ASSERT_PHYRDY_EVEN_NOT_HRRDY_SHIFT)
#define SATA0_CFG_PHY_0_0_ASSERT_PHYRDY_EVEN_NOT_HRRDY_RANGE 26:26
#define SATA0_CFG_PHY_0_0_ASSERT_PHYRDY_EVEN_NOT_HRRDY_WOFFSET 0
#define SATA0_CFG_PHY_0_0_ASSERT_PHYRDY_EVEN_NOT_HRRDY_YES _MK_ENUM_CONST(0x00000001)                                                       // RW--V
#define SATA0_CFG_PHY_0_0_ASSERT_PHYRDY_EVEN_NOT_HRRDY_NO  _MK_ENUM_CONST(0x00000000)                                                       // RWC-V
#define SATA0_CFG_PHY_0_0_RX_STAT_IDLE_SHIFT                _MK_SHIFT_CONST(27)                                                             // RWWVF
#define SATA0_CFG_PHY_0_0_RX_STAT_IDLE_FIELD               (_MK_SHIFT_CONST(0x1) << SATA0_CFG_PHY_0_0_RX_STAT_IDLE_SHIFT)
#define SATA0_CFG_PHY_0_0_RX_STAT_IDLE_RANGE               27:27
#define SATA0_CFG_PHY_0_0_RX_STAT_IDLE_WOFFSET             0
#define SATA0_CFG_PHY_0_0_RX_STAT_IDLE_DEFAULT             (_MK_MASK_CONST(0x0000000)
#define SATA0_CFG_PHY_0_0_RX_STAT_IDLE_DEFAULT_MASK        (_MK_MASK_CONST(0x1)
#define SATA0_CFG_PHY_0_0_RX_STAT_IDLE_SW_DEFAULT          (_MK_MASK_CONST(0x0000000)
#define SATA0_CFG_PHY_0_0_RX_STAT_IDLE_SW_DEFAULT_MASK     (_MK_MASK_CONST(0x1)
#define SATA0_CFG_PHY_0_0_RX_STAT_IDLE_INIT                _MK_ENUM_CONST(0x0000000)                                                        // RWW-V
#define SATA0_CFG_PHY_0_0_USE_STORED_COMWAKE_SHIFT          _MK_SHIFT_CONST(28)                                                             // RWWVF
#define SATA0_CFG_PHY_0_0_USE_STORED_COMWAKE_FIELD         (_MK_SHIFT_CONST(0x1) << SATA0_CFG_PHY_0_0_USE_STORED_COMWAKE_SHIFT)
#define SATA0_CFG_PHY_0_0_USE_STORED_COMWAKE_RANGE         28:28
#define SATA0_CFG_PHY_0_0_USE_STORED_COMWAKE_WOFFSET       0
#define SATA0_CFG_PHY_0_0_USE_STORED_COMWAKE_DEFAULT       (_MK_MASK_CONST(0x0000001)
#define SATA0_CFG_PHY_0_0_USE_STORED_COMWAKE_DEFAULT_MASK  (_MK_MASK_CONST(0x1)
#define SATA0_CFG_PHY_0_0_USE_STORED_COMWAKE_SW_DEFAULT    (_MK_MASK_CONST(0x0000001)
#define SATA0_CFG_PHY_0_0_USE_STORED_COMWAKE_SW_DEFAULT_MASK (_MK_MASK_CONST(0x1)
#define SATA0_CFG_PHY_0_0_USE_STORED_COMWAKE_INIT          _MK_ENUM_CONST(0x0000001)                                                        // RWW-V
#define SATA0_CFG_PHY_0_0_ASSERT_PHYRDY_IN_NVOOB_SM_SHIFT   _MK_SHIFT_CONST(29)                                                             // RWCVF
#define SATA0_CFG_PHY_0_0_ASSERT_PHYRDY_IN_NVOOB_SM_FIELD  (_MK_SHIFT_CONST(0x1) << SATA0_CFG_PHY_0_0_ASSERT_PHYRDY_IN_NVOOB_SM_SHIFT)
#define SATA0_CFG_PHY_0_0_ASSERT_PHYRDY_IN_NVOOB_SM_RANGE  29:29
#define SATA0_CFG_PHY_0_0_ASSERT_PHYRDY_IN_NVOOB_SM_WOFFSET 0
#define SATA0_CFG_PHY_0_0_ASSERT_PHYRDY_IN_NVOOB_SM_YES    _MK_ENUM_CONST(0x00000001)                                                       // RWC-V
#define SATA0_CFG_PHY_0_0_ASSERT_PHYRDY_IN_NVOOB_SM_NO     _MK_ENUM_CONST(0x00000000)                                                       // RW--V
#define SATA0_CFG_PHY_0_0_RESET_SREGS_EVERY_COMRESET_SHIFT  _MK_SHIFT_CONST(30)                                                             // RWCVF
#define SATA0_CFG_PHY_0_0_RESET_SREGS_EVERY_COMRESET_FIELD (_MK_SHIFT_CONST(0x1) << SATA0_CFG_PHY_0_0_RESET_SREGS_EVERY_COMRESET_SHIFT)
#define SATA0_CFG_PHY_0_0_RESET_SREGS_EVERY_COMRESET_RANGE 30:30
#define SATA0_CFG_PHY_0_0_RESET_SREGS_EVERY_COMRESET_WOFFSET 0
#define SATA0_CFG_PHY_0_0_RESET_SREGS_EVERY_COMRESET_INIT  _MK_ENUM_CONST(0x00000000)                                                       // RWC-V
#define SATA0_CFG_PHY_0_0_HOLD_RX_STAT_IDLE_IN_BIST_SHIFT   _MK_SHIFT_CONST(31)                                                             // RWWVF
#define SATA0_CFG_PHY_0_0_HOLD_RX_STAT_IDLE_IN_BIST_FIELD  (_MK_SHIFT_CONST(0x1) << SATA0_CFG_PHY_0_0_HOLD_RX_STAT_IDLE_IN_BIST_SHIFT)
#define SATA0_CFG_PHY_0_0_HOLD_RX_STAT_IDLE_IN_BIST_RANGE  31:31
#define SATA0_CFG_PHY_0_0_HOLD_RX_STAT_IDLE_IN_BIST_WOFFSET 0
#define SATA0_CFG_PHY_0_0_HOLD_RX_STAT_IDLE_IN_BIST_DEFAULT (_MK_MASK_CONST(0x00000000)
#define SATA0_CFG_PHY_0_0_HOLD_RX_STAT_IDLE_IN_BIST_DEFAULT_MASK (_MK_MASK_CONST(0x1)
#define SATA0_CFG_PHY_0_0_HOLD_RX_STAT_IDLE_IN_BIST_SW_DEFAULT (_MK_MASK_CONST(0x00000000)
#define SATA0_CFG_PHY_0_0_HOLD_RX_STAT_IDLE_IN_BIST_SW_DEFAULT_MASK (_MK_MASK_CONST(0x1)
#define SATA0_CFG_PHY_0_0_HOLD_RX_STAT_IDLE_IN_BIST_INIT   _MK_ENUM_CONST(0x00000000)                                                       // RWW-V
// .LABEL PRIVATE INT_REL
// 
// // these two actually go to T_SATA0_glue but are related to PLL, so kept in PHY
// .LABEL INT_REL
// 
// 
// .LABEL PRIVATE INT_REL
// 
// .LABEL PRIVATE INT_REL
// 
// .LABEL PRIVATE INT_REL
// 
// .LABEL PRIVATE INT_REL
// 
// .LABEL PRIVATE INT_REL
// 
// .LABEL PRIVATE INT_REL
// 
// .LABEL PRIVATE INT_REL
// 
// .LABEL PRIVATE INT_REL
// 
// .LABEL PRIVATE INT_REL
// 
// .LABEL PRIVATE INT_REL
// 
// .LABEL PRIVATE INT_REL
// 
// .LABEL PRIVATE INT_REL
// 
// 
// .LABEL PRIVATE INT_REL
// 
// .LABEL PRIVATE INT_REL
// 
// .LABEL PRIVATE INT_REL
// 
// .LABEL PRIVATE INT_REL
// 
// .LABEL PRIVATE INT_REL
// 
// .LABEL PRIVATE INT_REL
// 
// //} SATA0_CTRLR
// 
// 
// .LABEL PUBLIC
// 
// 
// .LABEL PRIVATE INT_REL
// .TITLE CFG_PHY_POWER
// 
// .FIELD TIME_WAIT_IN_PARTIAL
//     indicates the time in ms upto which the PHY SM would wait in PARTIAL before
// going to SLUMBER(AUTO PARTIAL TO SLUMBER feature)
// 
// 31           24 23           16 15            8 7             0
// .-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-.
// |0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0| CFG_PHY_POWER
// `-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-'
#define SATA0_CFG_PHY_POWER_0                              0x00000124                                                                       // RWC4R
#define SATA0_CFG_PHY_POWER_0_SECURE                       0
#define SATA0_CFG_PHY_POWER_0_WORD_COUNT                   1
#define SATA0_CFG_PHY_POWER_0_RESET_VAL                    0x0
#define SATA0_CFG_PHY_POWER_0_RESET_MASK                   0x0
#define SATA0_CFG_PHY_POWER_0_SW_DEFAULT_VAL               0x0
#define SATA0_CFG_PHY_POWER_0_SW_DEFAULT_MASK              0x0
#define SATA0_CFG_PHY_POWER_0_READ_MASK                    0xffffffff
#define SATA0_CFG_PHY_POWER_0_WRITE_MASK                   0xffffffff
#define SATA0_CFG_PHY_POWER_0_TIME_WAIT_IN_PARTIAL_SHIFT    _MK_SHIFT_CONST(0)                                                              // RWWVF
#define SATA0_CFG_PHY_POWER_0_TIME_WAIT_IN_PARTIAL_FIELD   (_MK_SHIFT_CONST(0x3ff) << SATA0_CFG_PHY_POWER_0_TIME_WAIT_IN_PARTIAL_SHIFT)
#define SATA0_CFG_PHY_POWER_0_TIME_WAIT_IN_PARTIAL_RANGE   9:0
#define SATA0_CFG_PHY_POWER_0_TIME_WAIT_IN_PARTIAL_WOFFSET 0
#define SATA0_CFG_PHY_POWER_0_TIME_WAIT_IN_PARTIAL_DEFAULT (_MK_MASK_CONST(0x00000001)
#define SATA0_CFG_PHY_POWER_0_TIME_WAIT_IN_PARTIAL_DEFAULT_MASK (_MK_MASK_CONST(0x3ff)
#define SATA0_CFG_PHY_POWER_0_TIME_WAIT_IN_PARTIAL_SW_DEFAULT (_MK_MASK_CONST(0x00000001)
#define SATA0_CFG_PHY_POWER_0_TIME_WAIT_IN_PARTIAL_SW_DEFAULT_MASK (_MK_MASK_CONST(0x3ff)
#define SATA0_CFG_PHY_POWER_0_TIME_WAIT_IN_PARTIAL_INIT    _MK_ENUM_CONST(0x00000001)                                                       // RWW-V
#define SATA0_CFG_PHY_POWER_0_COUNT_FOR_100_US_SHIFT        _MK_SHIFT_CONST(10)                                                             // RWWVF
#define SATA0_CFG_PHY_POWER_0_COUNT_FOR_100_US_FIELD       (_MK_SHIFT_CONST(0x3fff) << SATA0_CFG_PHY_POWER_0_COUNT_FOR_100_US_SHIFT)
#define SATA0_CFG_PHY_POWER_0_COUNT_FOR_100_US_RANGE       23:10
#define SATA0_CFG_PHY_POWER_0_COUNT_FOR_100_US_WOFFSET     0
#define SATA0_CFG_PHY_POWER_0_COUNT_FOR_100_US_DEFAULT     (_MK_MASK_CONST(0x00003A98)
#define SATA0_CFG_PHY_POWER_0_COUNT_FOR_100_US_DEFAULT_MASK (_MK_MASK_CONST(0x3fff)
#define SATA0_CFG_PHY_POWER_0_COUNT_FOR_100_US_SW_DEFAULT  (_MK_MASK_CONST(0x00003A98)
#define SATA0_CFG_PHY_POWER_0_COUNT_FOR_100_US_SW_DEFAULT_MASK (_MK_MASK_CONST(0x3fff)
#define SATA0_CFG_PHY_POWER_0_COUNT_FOR_100_US_INIT        _MK_ENUM_CONST(0x00003A98)                                                       // RWW-V
#define SATA0_CFG_PHY_POWER_0_COUNT_FOR_1_US_SHIFT          _MK_SHIFT_CONST(24)                                                             // RWWVF
#define SATA0_CFG_PHY_POWER_0_COUNT_FOR_1_US_FIELD         (_MK_SHIFT_CONST(0xff) << SATA0_CFG_PHY_POWER_0_COUNT_FOR_1_US_SHIFT)
#define SATA0_CFG_PHY_POWER_0_COUNT_FOR_1_US_RANGE         31:24
#define SATA0_CFG_PHY_POWER_0_COUNT_FOR_1_US_WOFFSET       0
#define SATA0_CFG_PHY_POWER_0_COUNT_FOR_1_US_DEFAULT       (_MK_MASK_CONST(0x00000096)
#define SATA0_CFG_PHY_POWER_0_COUNT_FOR_1_US_DEFAULT_MASK  (_MK_MASK_CONST(0xff)
#define SATA0_CFG_PHY_POWER_0_COUNT_FOR_1_US_SW_DEFAULT    (_MK_MASK_CONST(0x00000096)
#define SATA0_CFG_PHY_POWER_0_COUNT_FOR_1_US_SW_DEFAULT_MASK (_MK_MASK_CONST(0xff)
#define SATA0_CFG_PHY_POWER_0_COUNT_FOR_1_US_INIT          _MK_ENUM_CONST(0x00000096)                                                       // RWW-V
// 
// 
// 
// .LABEL PUBLIC
// 
// 
// .LABEL PRIVATE INT_REL
// .TITLE CFG_PHY_POWER_1
// .FIELD COUNT_FOR_1_MS
// Indicates the number of clock cycles for one ms at 150MHz(sata_oob_detect_clk)
// Used for Auto Partial to slumber feature
// 
// 31           24 23           16 15            8 7             0
// .-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-.
// |0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0| CFG_PHY_POWER_1
// `-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-'
#define SATA0_CFG_PHY_POWER_1_0                            0x00000128                                                                       // RWC4R
#define SATA0_CFG_PHY_POWER_1_0_SECURE                     0
#define SATA0_CFG_PHY_POWER_1_0_WORD_COUNT                 1
#define SATA0_CFG_PHY_POWER_1_0_RESET_VAL                  0x0
#define SATA0_CFG_PHY_POWER_1_0_RESET_MASK                 0x0
#define SATA0_CFG_PHY_POWER_1_0_SW_DEFAULT_VAL             0x0
#define SATA0_CFG_PHY_POWER_1_0_SW_DEFAULT_MASK            0x0
#define SATA0_CFG_PHY_POWER_1_0_READ_MASK                  0xffffffff
#define SATA0_CFG_PHY_POWER_1_0_WRITE_MASK                 0xffffffff
#define SATA0_CFG_PHY_POWER_1_0_COUNT_FOR_1_MS_SHIFT        _MK_SHIFT_CONST(0)                                                              // RWWVF
#define SATA0_CFG_PHY_POWER_1_0_COUNT_FOR_1_MS_FIELD       (_MK_SHIFT_CONST(0xfffff) << SATA0_CFG_PHY_POWER_1_0_COUNT_FOR_1_MS_SHIFT)
#define SATA0_CFG_PHY_POWER_1_0_COUNT_FOR_1_MS_RANGE       19:0
#define SATA0_CFG_PHY_POWER_1_0_COUNT_FOR_1_MS_WOFFSET     0
#define SATA0_CFG_PHY_POWER_1_0_COUNT_FOR_1_MS_DEFAULT     (_MK_MASK_CONST(0x000249F0)
#define SATA0_CFG_PHY_POWER_1_0_COUNT_FOR_1_MS_DEFAULT_MASK (_MK_MASK_CONST(0xfffff)
#define SATA0_CFG_PHY_POWER_1_0_COUNT_FOR_1_MS_SW_DEFAULT  (_MK_MASK_CONST(0x000249F0)
#define SATA0_CFG_PHY_POWER_1_0_COUNT_FOR_1_MS_SW_DEFAULT_MASK (_MK_MASK_CONST(0xfffff)
#define SATA0_CFG_PHY_POWER_1_0_COUNT_FOR_1_MS_INIT        _MK_ENUM_CONST(0x000249F0)                                                       // RWW-V
#define SATA0_CFG_PHY_POWER_1_0_COUNTER_FOR_PADS_SHIFT      _MK_SHIFT_CONST(20)                                                             // RWWVF
#define SATA0_CFG_PHY_POWER_1_0_COUNTER_FOR_PADS_FIELD     (_MK_SHIFT_CONST(0xfff) << SATA0_CFG_PHY_POWER_1_0_COUNTER_FOR_PADS_SHIFT)
#define SATA0_CFG_PHY_POWER_1_0_COUNTER_FOR_PADS_RANGE     31:20
#define SATA0_CFG_PHY_POWER_1_0_COUNTER_FOR_PADS_WOFFSET   0
#define SATA0_CFG_PHY_POWER_1_0_COUNTER_FOR_PADS_DEFAULT   (_MK_MASK_CONST(0x000000FF)
#define SATA0_CFG_PHY_POWER_1_0_COUNTER_FOR_PADS_DEFAULT_MASK (_MK_MASK_CONST(0xfff)
#define SATA0_CFG_PHY_POWER_1_0_COUNTER_FOR_PADS_SW_DEFAULT (_MK_MASK_CONST(0x000000FF)
#define SATA0_CFG_PHY_POWER_1_0_COUNTER_FOR_PADS_SW_DEFAULT_MASK (_MK_MASK_CONST(0xfff)
#define SATA0_CFG_PHY_POWER_1_0_COUNTER_FOR_PADS_INIT      _MK_ENUM_CONST(0x000000FF)                                                       // RWW-V
// 
// .LABEL PUBLIC
// 
// .LABEL PRIVATE INT_REL
// .TITLE T_SATA0_CFG_PHY_1
// 31           24 23           16 15            8 7             0
// .-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-.
// |0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0| CFG_PHY_1
// `-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-'
// 
#define SATA0_CFG_PHY_1_0                                  0x0000012C                                                                       // RW-4R
#define SATA0_CFG_PHY_1_0_SECURE                           0
#define SATA0_CFG_PHY_1_0_WORD_COUNT                       1
#define SATA0_CFG_PHY_1_0_RESET_VAL                        0x0
#define SATA0_CFG_PHY_1_0_RESET_MASK                       0x0
#define SATA0_CFG_PHY_1_0_SW_DEFAULT_VAL                   0x0
#define SATA0_CFG_PHY_1_0_SW_DEFAULT_MASK                  0x0
#define SATA0_CFG_PHY_1_0_READ_MASK                        0xffffffff
#define SATA0_CFG_PHY_1_0_WRITE_MASK                       0xffffffff
#define SATA0_CFG_PHY_1_0_ASSERT_PHYRDY_FOR_ALL_BIST_SHIFT  _MK_SHIFT_CONST(0)                                                              // RWWVF
#define SATA0_CFG_PHY_1_0_ASSERT_PHYRDY_FOR_ALL_BIST_FIELD (_MK_SHIFT_CONST(0x1) << SATA0_CFG_PHY_1_0_ASSERT_PHYRDY_FOR_ALL_BIST_SHIFT)
#define SATA0_CFG_PHY_1_0_ASSERT_PHYRDY_FOR_ALL_BIST_RANGE 0:0
#define SATA0_CFG_PHY_1_0_ASSERT_PHYRDY_FOR_ALL_BIST_WOFFSET 0
#define SATA0_CFG_PHY_1_0_ASSERT_PHYRDY_FOR_ALL_BIST_DEFAULT (_MK_MASK_CONST(0x00000001)
#define SATA0_CFG_PHY_1_0_ASSERT_PHYRDY_FOR_ALL_BIST_DEFAULT_MASK (_MK_MASK_CONST(0x1)
#define SATA0_CFG_PHY_1_0_ASSERT_PHYRDY_FOR_ALL_BIST_SW_DEFAULT (_MK_MASK_CONST(0x00000001)
#define SATA0_CFG_PHY_1_0_ASSERT_PHYRDY_FOR_ALL_BIST_SW_DEFAULT_MASK (_MK_MASK_CONST(0x1)
#define SATA0_CFG_PHY_1_0_ASSERT_PHYRDY_FOR_ALL_BIST_INIT  _MK_ENUM_CONST(0x00000001)                                                       // RWW-V
#define SATA0_CFG_PHY_1_0_HOLD_RBC_RESET_IN_BIST_SHIFT      _MK_SHIFT_CONST(1)                                                              // RWWVF
#define SATA0_CFG_PHY_1_0_HOLD_RBC_RESET_IN_BIST_FIELD     (_MK_SHIFT_CONST(0x1) << SATA0_CFG_PHY_1_0_HOLD_RBC_RESET_IN_BIST_SHIFT)
#define SATA0_CFG_PHY_1_0_HOLD_RBC_RESET_IN_BIST_RANGE     1:1
#define SATA0_CFG_PHY_1_0_HOLD_RBC_RESET_IN_BIST_WOFFSET   0
#define SATA0_CFG_PHY_1_0_HOLD_RBC_RESET_IN_BIST_DEFAULT   (_MK_MASK_CONST(0x00000001)
#define SATA0_CFG_PHY_1_0_HOLD_RBC_RESET_IN_BIST_DEFAULT_MASK (_MK_MASK_CONST(0x1)
#define SATA0_CFG_PHY_1_0_HOLD_RBC_RESET_IN_BIST_SW_DEFAULT (_MK_MASK_CONST(0x00000001)
#define SATA0_CFG_PHY_1_0_HOLD_RBC_RESET_IN_BIST_SW_DEFAULT_MASK (_MK_MASK_CONST(0x1)
#define SATA0_CFG_PHY_1_0_HOLD_RBC_RESET_IN_BIST_INIT      _MK_ENUM_CONST(0x00000001)                                                       // RWW-V
#define SATA0_CFG_PHY_1_0_EN_ASYNC_REC_ARC_IN_HRRDY_SHIFT   _MK_SHIFT_CONST(2)                                                              // RWCVF
#define SATA0_CFG_PHY_1_0_EN_ASYNC_REC_ARC_IN_HRRDY_FIELD  (_MK_SHIFT_CONST(0x1) << SATA0_CFG_PHY_1_0_EN_ASYNC_REC_ARC_IN_HRRDY_SHIFT)
#define SATA0_CFG_PHY_1_0_EN_ASYNC_REC_ARC_IN_HRRDY_RANGE  2:2
#define SATA0_CFG_PHY_1_0_EN_ASYNC_REC_ARC_IN_HRRDY_WOFFSET 0
#define SATA0_CFG_PHY_1_0_EN_ASYNC_REC_ARC_IN_HRRDY_INIT   _MK_ENUM_CONST(0x00000001)                                                       // RWC-V
#define SATA0_CFG_PHY_1_0_DONT_USE_COMMA_FOR_PHYRDY_LOW_SHIFT  _MK_SHIFT_CONST(3)                                                              // RWCVF
#define SATA0_CFG_PHY_1_0_DONT_USE_COMMA_FOR_PHYRDY_LOW_FIELD (_MK_SHIFT_CONST(0x1) << SATA0_CFG_PHY_1_0_DONT_USE_COMMA_FOR_PHYRDY_LOW_SHIFT)
#define SATA0_CFG_PHY_1_0_DONT_USE_COMMA_FOR_PHYRDY_LOW_RANGE 3:3
#define SATA0_CFG_PHY_1_0_DONT_USE_COMMA_FOR_PHYRDY_LOW_WOFFSET 0
#define SATA0_CFG_PHY_1_0_DONT_USE_COMMA_FOR_PHYRDY_LOW_INIT _MK_ENUM_CONST(0x000000001)                                                      // RWC-V
#define SATA0_CFG_PHY_1_0_COUNT_FOR_COMMA_WAIT_SHIFT        _MK_SHIFT_CONST(4)                                                              // RWCVF
#define SATA0_CFG_PHY_1_0_COUNT_FOR_COMMA_WAIT_FIELD       (_MK_SHIFT_CONST(0xfff) << SATA0_CFG_PHY_1_0_COUNT_FOR_COMMA_WAIT_SHIFT)
#define SATA0_CFG_PHY_1_0_COUNT_FOR_COMMA_WAIT_RANGE       15:4
#define SATA0_CFG_PHY_1_0_COUNT_FOR_COMMA_WAIT_WOFFSET     0
#define SATA0_CFG_PHY_1_0_COUNT_FOR_COMMA_WAIT_INIT        _MK_ENUM_CONST(0x00000400)                                                       // RWC-V
#define SATA0_CFG_PHY_1_0_NUMBER_OF_COMMA_WINDOWS_SHIFT     _MK_SHIFT_CONST(16)                                                             // RWCVF
#define SATA0_CFG_PHY_1_0_NUMBER_OF_COMMA_WINDOWS_FIELD    (_MK_SHIFT_CONST(0xf) << SATA0_CFG_PHY_1_0_NUMBER_OF_COMMA_WINDOWS_SHIFT)
#define SATA0_CFG_PHY_1_0_NUMBER_OF_COMMA_WINDOWS_RANGE    19:16
#define SATA0_CFG_PHY_1_0_NUMBER_OF_COMMA_WINDOWS_WOFFSET  0
#define SATA0_CFG_PHY_1_0_NUMBER_OF_COMMA_WINDOWS_INIT     _MK_ENUM_CONST(0x00000002)                                                       // RWC-V
#define SATA0_CFG_PHY_1_0_NO_OVERRIDE_STAT_IDLE_PHYRDY_SHIFT  _MK_SHIFT_CONST(20)                                                             // RWCVF
#define SATA0_CFG_PHY_1_0_NO_OVERRIDE_STAT_IDLE_PHYRDY_FIELD (_MK_SHIFT_CONST(0x1) << SATA0_CFG_PHY_1_0_NO_OVERRIDE_STAT_IDLE_PHYRDY_SHIFT)
#define SATA0_CFG_PHY_1_0_NO_OVERRIDE_STAT_IDLE_PHYRDY_RANGE 20:20
#define SATA0_CFG_PHY_1_0_NO_OVERRIDE_STAT_IDLE_PHYRDY_WOFFSET 0
#define SATA0_CFG_PHY_1_0_NO_OVERRIDE_STAT_IDLE_PHYRDY_INIT _MK_ENUM_CONST(0x00000001)                                                       // RWC-V
#define SATA0_CFG_PHY_1_0_SEND_OOB_DATA_IN_LOW_POWER_SHIFT  _MK_SHIFT_CONST(21)                                                             // RWCVF
#define SATA0_CFG_PHY_1_0_SEND_OOB_DATA_IN_LOW_POWER_FIELD (_MK_SHIFT_CONST(0x1) << SATA0_CFG_PHY_1_0_SEND_OOB_DATA_IN_LOW_POWER_SHIFT)
#define SATA0_CFG_PHY_1_0_SEND_OOB_DATA_IN_LOW_POWER_RANGE 21:21
#define SATA0_CFG_PHY_1_0_SEND_OOB_DATA_IN_LOW_POWER_WOFFSET 0
#define SATA0_CFG_PHY_1_0_SEND_OOB_DATA_IN_LOW_POWER_INIT  _MK_ENUM_CONST(0x00000001)                                                       // RWC-V
#define SATA0_CFG_PHY_1_0_PAD_PLL_IDDQ_EN_SHIFT             _MK_SHIFT_CONST(22)                                                             // RWCVF
#define SATA0_CFG_PHY_1_0_PAD_PLL_IDDQ_EN_FIELD            (_MK_SHIFT_CONST(0x1) << SATA0_CFG_PHY_1_0_PAD_PLL_IDDQ_EN_SHIFT)
#define SATA0_CFG_PHY_1_0_PAD_PLL_IDDQ_EN_RANGE            22:22
#define SATA0_CFG_PHY_1_0_PAD_PLL_IDDQ_EN_WOFFSET          0
#define SATA0_CFG_PHY_1_0_PAD_PLL_IDDQ_EN_INIT             _MK_ENUM_CONST(0x00000000)                                                       // RWC-V
#define SATA0_CFG_PHY_1_0_PADS_IDDQ_EN_SHIFT                _MK_SHIFT_CONST(23)                                                             // RWCVF
#define SATA0_CFG_PHY_1_0_PADS_IDDQ_EN_FIELD               (_MK_SHIFT_CONST(0x1) << SATA0_CFG_PHY_1_0_PADS_IDDQ_EN_SHIFT)
#define SATA0_CFG_PHY_1_0_PADS_IDDQ_EN_RANGE               23:23
#define SATA0_CFG_PHY_1_0_PADS_IDDQ_EN_WOFFSET             0
#define SATA0_CFG_PHY_1_0_PADS_IDDQ_EN_INIT                _MK_ENUM_CONST(0x00000000)                                                       // RWC-V
#define SATA0_CFG_PHY_1_0_PLL_PD_NO_CMDS_SHIFT              _MK_SHIFT_CONST(24)                                                             // RWWVF
#define SATA0_CFG_PHY_1_0_PLL_PD_NO_CMDS_FIELD             (_MK_SHIFT_CONST(0x1) << SATA0_CFG_PHY_1_0_PLL_PD_NO_CMDS_SHIFT)
#define SATA0_CFG_PHY_1_0_PLL_PD_NO_CMDS_RANGE             24:24
#define SATA0_CFG_PHY_1_0_PLL_PD_NO_CMDS_WOFFSET           0
#define SATA0_CFG_PHY_1_0_PLL_PD_NO_CMDS_DEFAULT           (_MK_MASK_CONST(0x00000001)
#define SATA0_CFG_PHY_1_0_PLL_PD_NO_CMDS_DEFAULT_MASK      (_MK_MASK_CONST(0x1)
#define SATA0_CFG_PHY_1_0_PLL_PD_NO_CMDS_SW_DEFAULT        (_MK_MASK_CONST(0x00000001)
#define SATA0_CFG_PHY_1_0_PLL_PD_NO_CMDS_SW_DEFAULT_MASK   (_MK_MASK_CONST(0x1)
#define SATA0_CFG_PHY_1_0_PLL_PD_NO_CMDS_INIT              _MK_ENUM_CONST(0x00000001)                                                       // RWW-V
#define SATA0_CFG_PHY_1_0_COMWAKE_GLOBAL_SHIFT              _MK_SHIFT_CONST(25)                                                             // RWCVF
#define SATA0_CFG_PHY_1_0_COMWAKE_GLOBAL_FIELD             (_MK_SHIFT_CONST(0x1) << SATA0_CFG_PHY_1_0_COMWAKE_GLOBAL_SHIFT)
#define SATA0_CFG_PHY_1_0_COMWAKE_GLOBAL_RANGE             25:25
#define SATA0_CFG_PHY_1_0_COMWAKE_GLOBAL_WOFFSET           0
#define SATA0_CFG_PHY_1_0_COMWAKE_GLOBAL_INIT              _MK_ENUM_CONST(0x00000001)                                                       // RWC-V
#define SATA0_CFG_PHY_1_0_DONT_CHK_PHY_RESET_SHIFT          _MK_SHIFT_CONST(26)                                                             // RWCVF
#define SATA0_CFG_PHY_1_0_DONT_CHK_PHY_RESET_FIELD         (_MK_SHIFT_CONST(0x1) << SATA0_CFG_PHY_1_0_DONT_CHK_PHY_RESET_SHIFT)
#define SATA0_CFG_PHY_1_0_DONT_CHK_PHY_RESET_RANGE         26:26
#define SATA0_CFG_PHY_1_0_DONT_CHK_PHY_RESET_WOFFSET       0
#define SATA0_CFG_PHY_1_0_DONT_CHK_PHY_RESET_INIT          _MK_ENUM_CONST(0x00000001)                                                       // RWC-V
#define SATA0_CFG_PHY_1_0_CYA_SLEEP_IDDQ_FIX_SHIFT          _MK_SHIFT_CONST(27)                                                             // RWCVF
#define SATA0_CFG_PHY_1_0_CYA_SLEEP_IDDQ_FIX_FIELD         (_MK_SHIFT_CONST(0x1) << SATA0_CFG_PHY_1_0_CYA_SLEEP_IDDQ_FIX_SHIFT)
#define SATA0_CFG_PHY_1_0_CYA_SLEEP_IDDQ_FIX_RANGE         27:27
#define SATA0_CFG_PHY_1_0_CYA_SLEEP_IDDQ_FIX_WOFFSET       0
#define SATA0_CFG_PHY_1_0_CYA_SLEEP_IDDQ_FIX_INIT          _MK_ENUM_CONST(0x00000001)                                                       // RWC-V
#define SATA0_CFG_PHY_1_0_IDDQ_SLEEP_TIMER_SHIFT            _MK_SHIFT_CONST(28)                                                             // RWCVF
#define SATA0_CFG_PHY_1_0_IDDQ_SLEEP_TIMER_FIELD           (_MK_SHIFT_CONST(0xf) << SATA0_CFG_PHY_1_0_IDDQ_SLEEP_TIMER_SHIFT)
#define SATA0_CFG_PHY_1_0_IDDQ_SLEEP_TIMER_RANGE           31:28
#define SATA0_CFG_PHY_1_0_IDDQ_SLEEP_TIMER_WOFFSET         0
#define SATA0_CFG_PHY_1_0_IDDQ_SLEEP_TIMER_INIT            _MK_ENUM_CONST(0x0000000E)                                                       // RWC-V
// 
// 
// 
// 
// 
// 
// 
// 
// 
// 
// 
// 
// 
// 
// 
// .LABEL PUBLIC
// .LABEL ANALOG_PRIVATE INT_REL
// 
// .TITLE T_SATA0_CFG2NVOOB_1
// .FIELD ACTIVE_CNT_HIGH
// Squelch can be high for a maximum of ACTIVE_CNT_HIGH cycles at 216MHz for OOB signalling.
// .FIELD ACTIVE_CNT_LOW
// Squelch can be high for a mininum of ACTIVE_CNT_LOW cycles at 216MHz for OOB signalling.
// .FIELD COMINIT_IDLE_CNT_HIGH
// Squelch can be high for a maximum of COMINIT_IDLE_CNT_HIGH cycles at 216MHz for COMINIT signalling.
// 
// 31           24 23           16 15            8 7             0
// .-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-.
// |0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0| CFG2NVOOB_1
// `-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-'
#define SATA0_CFG2NVOOB_1_0                                0x00000130                                                                       // RW-4R
#define SATA0_CFG2NVOOB_1_0_SECURE                         0
#define SATA0_CFG2NVOOB_1_0_WORD_COUNT                     1
#define SATA0_CFG2NVOOB_1_0_RESET_VAL                      0x0
#define SATA0_CFG2NVOOB_1_0_RESET_MASK                     0x0
#define SATA0_CFG2NVOOB_1_0_SW_DEFAULT_VAL                 0x0
#define SATA0_CFG2NVOOB_1_0_SW_DEFAULT_MASK                0x0
#define SATA0_CFG2NVOOB_1_0_READ_MASK                      0x7ffffff
#define SATA0_CFG2NVOOB_1_0_WRITE_MASK                     0x7ffffff
#define SATA0_CFG2NVOOB_1_0_ACTIVE_CNT_HIGH_SHIFT           _MK_SHIFT_CONST(0)                                                              // RWCVF
#define SATA0_CFG2NVOOB_1_0_ACTIVE_CNT_HIGH_FIELD          (_MK_SHIFT_CONST(0x1ff) << SATA0_CFG2NVOOB_1_0_ACTIVE_CNT_HIGH_SHIFT)
#define SATA0_CFG2NVOOB_1_0_ACTIVE_CNT_HIGH_RANGE          8:0
#define SATA0_CFG2NVOOB_1_0_ACTIVE_CNT_HIGH_WOFFSET        0
#define SATA0_CFG2NVOOB_1_0_ACTIVE_CNT_LOW_SHIFT            _MK_SHIFT_CONST(9)                                                              // RWCVF
#define SATA0_CFG2NVOOB_1_0_ACTIVE_CNT_LOW_FIELD           (_MK_SHIFT_CONST(0x1ff) << SATA0_CFG2NVOOB_1_0_ACTIVE_CNT_LOW_SHIFT)
#define SATA0_CFG2NVOOB_1_0_ACTIVE_CNT_LOW_RANGE           17:9
#define SATA0_CFG2NVOOB_1_0_ACTIVE_CNT_LOW_WOFFSET         0
#define SATA0_CFG2NVOOB_1_0_COMINIT_IDLE_CNT_HIGH_SHIFT     _MK_SHIFT_CONST(18)                                                             // RWCVF
#define SATA0_CFG2NVOOB_1_0_COMINIT_IDLE_CNT_HIGH_FIELD    (_MK_SHIFT_CONST(0x1ff) << SATA0_CFG2NVOOB_1_0_COMINIT_IDLE_CNT_HIGH_SHIFT)
#define SATA0_CFG2NVOOB_1_0_COMINIT_IDLE_CNT_HIGH_RANGE    26:18
#define SATA0_CFG2NVOOB_1_0_COMINIT_IDLE_CNT_HIGH_WOFFSET  0
// 
// .LABEL PUBLIC
// .LABEL ANALOG_PRIVATE INT_REL
// 
// .TITLE T_SATA0_CFG2NVOOB_2
// .FIELD COMINIT_IDLE_CNT_LOW
// Squelch can be high for a minimum of 50 + 4*COMINIT_IDLE_CNT_LOW cycles at 216MHz for COMINIT signalling.
// .FIELD COMWAKE_IDLE_CNT_HIGH
// Squelch can be high for a maximum of 32 + 2*COMWAKE_IDLE_CNT_HIGH cycles at 216MHz for COMWAKE signalling.
// .FIELD COMWAKE_IDLE_CNT_LOW
// Squelch can be high for a minimum of 2*COMWAKE_IDLE_CNT_LOW cycles at 216MHz for COMWAKE signalling.
// 
// 31           24 23           16 15            8 7             0
// .-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-.
// |0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0| CFG2NVOOB_2
// `-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-'
#define SATA0_CFG2NVOOB_2_0                                0x00000134                                                                       // RW-4R
#define SATA0_CFG2NVOOB_2_0_SECURE                         0
#define SATA0_CFG2NVOOB_2_0_WORD_COUNT                     1
#define SATA0_CFG2NVOOB_2_0_RESET_VAL                      0x0
#define SATA0_CFG2NVOOB_2_0_RESET_MASK                     0x0
#define SATA0_CFG2NVOOB_2_0_SW_DEFAULT_VAL                 0x0
#define SATA0_CFG2NVOOB_2_0_SW_DEFAULT_MASK                0x0
#define SATA0_CFG2NVOOB_2_0_READ_MASK                      0x7ffffff
#define SATA0_CFG2NVOOB_2_0_WRITE_MASK                     0x7ffffff
#define SATA0_CFG2NVOOB_2_0_COMINIT_IDLE_CNT_LOW_SHIFT      _MK_SHIFT_CONST(0)                                                              // RWCVF
#define SATA0_CFG2NVOOB_2_0_COMINIT_IDLE_CNT_LOW_FIELD     (_MK_SHIFT_CONST(0x1ff) << SATA0_CFG2NVOOB_2_0_COMINIT_IDLE_CNT_LOW_SHIFT)
#define SATA0_CFG2NVOOB_2_0_COMINIT_IDLE_CNT_LOW_RANGE     8:0
#define SATA0_CFG2NVOOB_2_0_COMINIT_IDLE_CNT_LOW_WOFFSET   0
#define SATA0_CFG2NVOOB_2_0_COMWAKE_IDLE_CNT_HIGH_SHIFT     _MK_SHIFT_CONST(9)                                                              // RWCVF
#define SATA0_CFG2NVOOB_2_0_COMWAKE_IDLE_CNT_HIGH_FIELD    (_MK_SHIFT_CONST(0x1ff) << SATA0_CFG2NVOOB_2_0_COMWAKE_IDLE_CNT_HIGH_SHIFT)
#define SATA0_CFG2NVOOB_2_0_COMWAKE_IDLE_CNT_HIGH_RANGE    17:9
#define SATA0_CFG2NVOOB_2_0_COMWAKE_IDLE_CNT_HIGH_WOFFSET  0
#define SATA0_CFG2NVOOB_2_0_COMWAKE_IDLE_CNT_LOW_SHIFT      _MK_SHIFT_CONST(18)                                                             // RWCVF
#define SATA0_CFG2NVOOB_2_0_COMWAKE_IDLE_CNT_LOW_FIELD     (_MK_SHIFT_CONST(0x1ff) << SATA0_CFG2NVOOB_2_0_COMWAKE_IDLE_CNT_LOW_SHIFT)
#define SATA0_CFG2NVOOB_2_0_COMWAKE_IDLE_CNT_LOW_RANGE     26:18
#define SATA0_CFG2NVOOB_2_0_COMWAKE_IDLE_CNT_LOW_WOFFSET   0
// 
// .LABEL PUBLIC
// 
// .LABEL PRIVATE INT_REL
// .TITLE T_SATA0_CFG_PHY_ACTIVE
// .FIELD ACTIVE_FROM_PARTIAL
// Decides the time to be in PARTIAL state after we receive a COMWAKE from the device or the Link Layer
// lowers the partial flag. To give time for the pads to wakeup before sending the COMWAKE.
// This is for txclk of 300MHZ, will be multiplied by two in the OOB state-machine for 600MHz
// 
// .FIELD ACTIVE_FROM_SLUMBER
// Decides the time to be in SLUMEBR state after we receive a COMWAKE from the device or the Link Layer
// lowers the slumber flag. To give time for the pads to wakeup before sending the COMWAKE.
// This is for txclk of 300MHZ, will be multiplied by two in the OOB state-machine for 600MHz
// Changing the default value of SLUMBER to 0x5C since Partial and Slumber wakeup times are the same.
// 
// 31           24 23           16 15            8 7             0
// .-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-.
// |0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0| CFG_PHY_ACTIVE
// `-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-'
#define SATA0_CFG_PHY_ACTIVE_0                             0x00000138                                                                       // RW-4R
#define SATA0_CFG_PHY_ACTIVE_0_SECURE                      0
#define SATA0_CFG_PHY_ACTIVE_0_WORD_COUNT                  1
#define SATA0_CFG_PHY_ACTIVE_0_RESET_VAL                   0x0
#define SATA0_CFG_PHY_ACTIVE_0_RESET_MASK                  0x0
#define SATA0_CFG_PHY_ACTIVE_0_SW_DEFAULT_VAL              0x0
#define SATA0_CFG_PHY_ACTIVE_0_SW_DEFAULT_MASK             0x0
#define SATA0_CFG_PHY_ACTIVE_0_READ_MASK                   0xffffffff
#define SATA0_CFG_PHY_ACTIVE_0_WRITE_MASK                  0xffffffff
#define SATA0_CFG_PHY_ACTIVE_0_FROM_PARTIAL_SHIFT           _MK_SHIFT_CONST(0)                                                              // RWCVF
#define SATA0_CFG_PHY_ACTIVE_0_FROM_PARTIAL_FIELD          (_MK_SHIFT_CONST(0x3ff) << SATA0_CFG_PHY_ACTIVE_0_FROM_PARTIAL_SHIFT)
#define SATA0_CFG_PHY_ACTIVE_0_FROM_PARTIAL_RANGE          9:0
#define SATA0_CFG_PHY_ACTIVE_0_FROM_PARTIAL_WOFFSET        0
#define SATA0_CFG_PHY_ACTIVE_0_FROM_SLUMBER_SHIFT           _MK_SHIFT_CONST(10)                                                             // RWCVF
#define SATA0_CFG_PHY_ACTIVE_0_FROM_SLUMBER_FIELD          (_MK_SHIFT_CONST(0x3fffff) << SATA0_CFG_PHY_ACTIVE_0_FROM_SLUMBER_SHIFT)
#define SATA0_CFG_PHY_ACTIVE_0_FROM_SLUMBER_RANGE          31:10
#define SATA0_CFG_PHY_ACTIVE_0_FROM_SLUMBER_WOFFSET        0
#define SATA0_CFG_PHY_ACTIVE_0_FROM_SLUMBER_DEFAULT_1      _MK_ENUM_CONST(0x00003AA8)                                                       // RW--V
// 
// 
// .LABEL PUBLIC
// .LABEL PRIVATE INT_REL
// .TITLE SATA_FIFO
// .FIELD L2P_FIFO_DEPTH
// This controls effective depth of l2p fifo. Smaller is better for performance but we can't do
// power optimization (clamping fpci_clk) with smaller depth fifos.
// 
// .FIELD P2L_FIFO_DEPTH
// This controls effective depth of p2l fifo. Smaller is better for performance but we can't do
// power optimization (clamping fpci_clk) with smaller depth fifos.
// 31           24 23           16 15            8 7             0
// .-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-.
// |0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0| FIFO
// `-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-'
#define SATA0_FIFO_0                                       0x00000170                                                                       // RWW4R
#define SATA0_FIFO_0_SECURE                                0
#define SATA0_FIFO_0_WORD_COUNT                            1
#define SATA0_FIFO_0_RESET_VAL                             0x0
#define SATA0_FIFO_0_RESET_MASK                            0x0
#define SATA0_FIFO_0_SW_DEFAULT_VAL                        0x0
#define SATA0_FIFO_0_SW_DEFAULT_MASK                       0x0
#define SATA0_FIFO_0_READ_MASK                             0xff000
#define SATA0_FIFO_0_WRITE_MASK                            0xff000
#define SATA0_FIFO_0_L2P_FIFO_DEPTH_SHIFT                   _MK_SHIFT_CONST(12)                                                             // RWCVF
#define SATA0_FIFO_0_L2P_FIFO_DEPTH_FIELD                  (_MK_SHIFT_CONST(0xf) << SATA0_FIFO_0_L2P_FIFO_DEPTH_SHIFT)
#define SATA0_FIFO_0_L2P_FIFO_DEPTH_RANGE                  15:12
#define SATA0_FIFO_0_L2P_FIFO_DEPTH_WOFFSET                0
#define SATA0_FIFO_0_L2P_FIFO_DEPTH__PROD_C_FPGA           _MK_ENUM_CONST(0x00000004)                                                       // RW--V
#define SATA0_FIFO_0_L2P_FIFO_DEPTH__PROD                  _MK_ENUM_CONST(0x00000007)                                                       // RW--V
#define SATA0_FIFO_0_P2L_FIFO_DEPTH_SHIFT                   _MK_SHIFT_CONST(16)                                                             // RWCVF
#define SATA0_FIFO_0_P2L_FIFO_DEPTH_FIELD                  (_MK_SHIFT_CONST(0xf) << SATA0_FIFO_0_P2L_FIFO_DEPTH_SHIFT)
#define SATA0_FIFO_0_P2L_FIFO_DEPTH_RANGE                  19:16
#define SATA0_FIFO_0_P2L_FIFO_DEPTH_WOFFSET                0
#define SATA0_FIFO_0_P2L_FIFO_DEPTH__PROD_C_FPGA           _MK_ENUM_CONST(0x00000006)                                                       // RW--V
#define SATA0_FIFO_0_P2L_FIFO_DEPTH__PROD                  _MK_ENUM_CONST(0x00000008)                                                       // RW--V
// .LABEL PRIVATE INT_REL
// 
// 
//         Figure 10-05 PHY <-> LINK FIFO depths
// .LABEL PUBLIC
// 
// 
// .TITLE CFG_LINK_0
// 
// .LABEL PRIVATE INT_REL
// .FIELD LED_MIN_ON_TIME
// Used to know the activity based on LED blinking
// 
// .LABEL PRIVATE INT_REL
// .FIELD SET_BSY_BIT_MTHD
// This controls when 8'h80 is loaded into shadow status reg. If the bit is 0 then
// 8'h80 is loaded when cominit is seen otherwise its loaded when phyrdy is seen.
// 
// .LABEL PUBLIC
// .FIELD CFG_LINK_0_DELAY_HOTPLUG_INTR
// This bit is used to control generation of hotplug interrupts.
// If this bit is set to 1, then an interrupt is generated when we get PHYRDY.
// If this bit is set to 0, then an interrupt is generated as soon as cominit is received.
// 
// .LABEL PUBLIC
// .FIELD DEBOUNCE_PHYRDY
// This bit and next bit controls phyrdy debounce behaviour. By default phyrdy is debounced. Once
// bit this is set, bit 5 selects the period of hysteresis.
// 
// .LABEL PUBLIC
// .FIELD DEBOUNCE_PHYRDY_PERIOD
// When set to 1, the hysteresis period is let to LONG mode.  A setting of zero is SHORT mode.
// 
// .LABEL PRIVATE
// .FIELD CFG_LINK_0_AUTO_REPEAT_PRIMS
// This bit should not be changed from its default value. This is an optimization attempt that
// did not work out.
// 
// .LABEL PRIVATE INT_REL
// .FIELD GOTO_SEND_SYNC_P
// This bit set sends Link SM to L_SEND_SYNC_P in BIST
// 
// .LABEL PRIVATE INT_REL
// .FIELD BE_IN_BIST_ON_PHYRDY_LOW
// The default value of this bit is one, Host should come out of BIST only on COMINIT/ COMRESET,
// default to that
// 
// .LABEL PRIVATE INT_REL
// .FIELD SEND_RAW_DATA_IN_BIST_L
// Default to zero, when set sends raw data in BIST_L mode without encoding/ decoding
// 
// .LABEL PRIVATE INT_REL
// .FIELD CFG_LINK_0_PM_OFF_COUNT
// Indicates the number of PMREQ send to the device on Slumber/ PARTIAL
// 
// 31           24 23           16 15            8 7             0
// .-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-.
// |0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0| CFG_LINK_0
// `-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-'
#define SATA0_CFG_LINK_0_0                                 0x00000174                                                                       // RWC4R
#define SATA0_CFG_LINK_0_0_SECURE                          0
#define SATA0_CFG_LINK_0_0_WORD_COUNT                      1
#define SATA0_CFG_LINK_0_0_RESET_VAL                       0x0
#define SATA0_CFG_LINK_0_0_RESET_MASK                      0x0
#define SATA0_CFG_LINK_0_0_SW_DEFAULT_VAL                  0x0
#define SATA0_CFG_LINK_0_0_SW_DEFAULT_MASK                 0x0
#define SATA0_CFG_LINK_0_0_READ_MASK                       0xffffffff
#define SATA0_CFG_LINK_0_0_WRITE_MASK                      0x1ffffff
#define SATA0_CFG_LINK_0_0_LED_MIN_ON_TIME_SHIFT            _MK_SHIFT_CONST(0)                                                              // RWC-F
#define SATA0_CFG_LINK_0_0_LED_MIN_ON_TIME_FIELD           (_MK_SHIFT_CONST(0x3) << SATA0_CFG_LINK_0_0_LED_MIN_ON_TIME_SHIFT)
#define SATA0_CFG_LINK_0_0_LED_MIN_ON_TIME_RANGE           1:0
#define SATA0_CFG_LINK_0_0_LED_MIN_ON_TIME_WOFFSET         0
#define SATA0_CFG_LINK_0_0_LED_MIN_ON_TIME_OFF             _MK_ENUM_CONST(0x00000000)                                                       // RW--V
#define SATA0_CFG_LINK_0_0_LED_MIN_ON_TIME_20MS            _MK_ENUM_CONST(0x00000001)                                                       // RW--V
#define SATA0_CFG_LINK_0_0_LED_MIN_ON_TIME_40MS            _MK_ENUM_CONST(0x00000002)                                                       // RWC-V
#define SATA0_CFG_LINK_0_0_LED_MIN_ON_TIME_80MS            _MK_ENUM_CONST(0x00000003)                                                       // RW--V
#define SATA0_CFG_LINK_0_0_SET_BSY_BIT_MTHD_SHIFT           _MK_SHIFT_CONST(2)                                                              // RWC-F
#define SATA0_CFG_LINK_0_0_SET_BSY_BIT_MTHD_FIELD          (_MK_SHIFT_CONST(0x1) << SATA0_CFG_LINK_0_0_SET_BSY_BIT_MTHD_SHIFT)
#define SATA0_CFG_LINK_0_0_SET_BSY_BIT_MTHD_RANGE          2:2
#define SATA0_CFG_LINK_0_0_SET_BSY_BIT_MTHD_WOFFSET        0
#define SATA0_CFG_LINK_0_0_SET_BSY_BIT_MTHD_PHYRDY         _MK_ENUM_CONST(0x00000001)                                                       // RW--V
#define SATA0_CFG_LINK_0_0_SET_BSY_BIT_MTHD_COMINIT        _MK_ENUM_CONST(0x00000000)                                                       // RWC-V
#define SATA0_CFG_LINK_0_0_DELAY_HOTPLUG_INTR_SHIFT         _MK_SHIFT_CONST(3)                                                              // RWC-F
#define SATA0_CFG_LINK_0_0_DELAY_HOTPLUG_INTR_FIELD        (_MK_SHIFT_CONST(0x1) << SATA0_CFG_LINK_0_0_DELAY_HOTPLUG_INTR_SHIFT)
#define SATA0_CFG_LINK_0_0_DELAY_HOTPLUG_INTR_RANGE        3:3
#define SATA0_CFG_LINK_0_0_DELAY_HOTPLUG_INTR_WOFFSET      0
#define SATA0_CFG_LINK_0_0_DELAY_HOTPLUG_INTR_YES          _MK_ENUM_CONST(0x00000001)                                                       // RWC-V
#define SATA0_CFG_LINK_0_0_DELAY_HOTPLUG_INTR_NO           _MK_ENUM_CONST(0x00000000)                                                       // RW--V
#define SATA0_CFG_LINK_0_0_DEBOUNCE_PHYRDY_SHIFT            _MK_SHIFT_CONST(4)                                                              // RWC-F
#define SATA0_CFG_LINK_0_0_DEBOUNCE_PHYRDY_FIELD           (_MK_SHIFT_CONST(0x1) << SATA0_CFG_LINK_0_0_DEBOUNCE_PHYRDY_SHIFT)
#define SATA0_CFG_LINK_0_0_DEBOUNCE_PHYRDY_RANGE           4:4
#define SATA0_CFG_LINK_0_0_DEBOUNCE_PHYRDY_WOFFSET         0
#define SATA0_CFG_LINK_0_0_DEBOUNCE_PHYRDY_YES             _MK_ENUM_CONST(0x00000001)                                                       // RW--V
#define SATA0_CFG_LINK_0_0_DEBOUNCE_PHYRDY_NO              _MK_ENUM_CONST(0x00000000)                                                       // RW--V
#define SATA0_CFG_LINK_0_0_DEBOUNCE_PHYRDY_INIT            _MK_ENUM_CONST(0x00000001)                                                       // RWC-V
#define SATA0_CFG_LINK_0_0_DEBOUNCE_PHYRDY_PERIOD_SHIFT     _MK_SHIFT_CONST(5)                                                              // RWC-F
#define SATA0_CFG_LINK_0_0_DEBOUNCE_PHYRDY_PERIOD_FIELD    (_MK_SHIFT_CONST(0x1) << SATA0_CFG_LINK_0_0_DEBOUNCE_PHYRDY_PERIOD_SHIFT)
#define SATA0_CFG_LINK_0_0_DEBOUNCE_PHYRDY_PERIOD_RANGE    5:5
#define SATA0_CFG_LINK_0_0_DEBOUNCE_PHYRDY_PERIOD_WOFFSET  0
#define SATA0_CFG_LINK_0_0_DEBOUNCE_PHYRDY_PERIOD_LONG     _MK_ENUM_CONST(0x00000001)                                                       // RW--V
#define SATA0_CFG_LINK_0_0_DEBOUNCE_PHYRDY_PERIOD_SHORT    _MK_ENUM_CONST(0x00000000)                                                       // RW--V
#define SATA0_CFG_LINK_0_0_DEBOUNCE_PHYRDY_PERIOD_INIT     _MK_ENUM_CONST(0x00000000)                                                       // RWC-V
#define SATA0_CFG_LINK_0_0_AUTO_REPEAT_PRIMS_SHIFT          _MK_SHIFT_CONST(6)                                                              // RWC-F
#define SATA0_CFG_LINK_0_0_AUTO_REPEAT_PRIMS_FIELD         (_MK_SHIFT_CONST(0x1) << SATA0_CFG_LINK_0_0_AUTO_REPEAT_PRIMS_SHIFT)
#define SATA0_CFG_LINK_0_0_AUTO_REPEAT_PRIMS_RANGE         6:6
#define SATA0_CFG_LINK_0_0_AUTO_REPEAT_PRIMS_WOFFSET       0
#define SATA0_CFG_LINK_0_0_AUTO_REPEAT_PRIMS_NO            _MK_ENUM_CONST(0x00000000)                                                       // RW--V
#define SATA0_CFG_LINK_0_0_AUTO_REPEAT_PRIMS_YES           _MK_ENUM_CONST(0x00000001)                                                       // RW--V
#define SATA0_CFG_LINK_0_0_AUTO_REPEAT_PRIMS_INIT          _MK_ENUM_CONST(0x00000000)                                                       // RWC-V
#define SATA0_CFG_LINK_0_0_GOTO_SEND_SYNC_P_SHIFT           _MK_SHIFT_CONST(7)                                                              // RWC-F
#define SATA0_CFG_LINK_0_0_GOTO_SEND_SYNC_P_FIELD          (_MK_SHIFT_CONST(0x1) << SATA0_CFG_LINK_0_0_GOTO_SEND_SYNC_P_SHIFT)
#define SATA0_CFG_LINK_0_0_GOTO_SEND_SYNC_P_RANGE          7:7
#define SATA0_CFG_LINK_0_0_GOTO_SEND_SYNC_P_WOFFSET        0
#define SATA0_CFG_LINK_0_0_GOTO_SEND_SYNC_P_NO             _MK_ENUM_CONST(0x00000000)                                                       // RW--V
#define SATA0_CFG_LINK_0_0_GOTO_SEND_SYNC_P_YES            _MK_ENUM_CONST(0x00000001)                                                       // RWC-V
#define SATA0_CFG_LINK_0_0_BE_IN_BIST_ON_PHYRDY_LOW_SHIFT   _MK_SHIFT_CONST(8)                                                              // RWC-F
#define SATA0_CFG_LINK_0_0_BE_IN_BIST_ON_PHYRDY_LOW_FIELD  (_MK_SHIFT_CONST(0x1) << SATA0_CFG_LINK_0_0_BE_IN_BIST_ON_PHYRDY_LOW_SHIFT)
#define SATA0_CFG_LINK_0_0_BE_IN_BIST_ON_PHYRDY_LOW_RANGE  8:8
#define SATA0_CFG_LINK_0_0_BE_IN_BIST_ON_PHYRDY_LOW_WOFFSET 0
#define SATA0_CFG_LINK_0_0_BE_IN_BIST_ON_PHYRDY_LOW_YES    _MK_ENUM_CONST(0x00000001)                                                       // RWC-V
#define SATA0_CFG_LINK_0_0_BE_IN_BIST_ON_PHYRDY_LOW_NO     _MK_ENUM_CONST(0x00000000)                                                       // RW--V
#define SATA0_CFG_LINK_0_0_SEND_RAW_DATA_IN_BIST_L_SHIFT    _MK_SHIFT_CONST(9)                                                              // RWC-F
#define SATA0_CFG_LINK_0_0_SEND_RAW_DATA_IN_BIST_L_FIELD   (_MK_SHIFT_CONST(0x1) << SATA0_CFG_LINK_0_0_SEND_RAW_DATA_IN_BIST_L_SHIFT)
#define SATA0_CFG_LINK_0_0_SEND_RAW_DATA_IN_BIST_L_RANGE   9:9
#define SATA0_CFG_LINK_0_0_SEND_RAW_DATA_IN_BIST_L_WOFFSET 0
#define SATA0_CFG_LINK_0_0_SEND_RAW_DATA_IN_BIST_L_YES     _MK_ENUM_CONST(0x00000001)                                                       // RWC-V
#define SATA0_CFG_LINK_0_0_SEND_RAW_DATA_IN_BIST_L_NO      _MK_ENUM_CONST(0x00000000)                                                       // RW--V
#define SATA0_CFG_LINK_0_0_PM_OFF_COUNT_SHIFT               _MK_SHIFT_CONST(10)                                                             // RWC-F
#define SATA0_CFG_LINK_0_0_PM_OFF_COUNT_FIELD              (_MK_SHIFT_CONST(0x1f) << SATA0_CFG_LINK_0_0_PM_OFF_COUNT_SHIFT)
#define SATA0_CFG_LINK_0_0_PM_OFF_COUNT_RANGE              14:10
#define SATA0_CFG_LINK_0_0_PM_OFF_COUNT_WOFFSET            0
#define SATA0_CFG_LINK_0_0_OLD_BEHAVIOUR_SEND_ALIGNS_SHIFT  _MK_SHIFT_CONST(15)                                                             // RWC-F
#define SATA0_CFG_LINK_0_0_OLD_BEHAVIOUR_SEND_ALIGNS_FIELD (_MK_SHIFT_CONST(0x1) << SATA0_CFG_LINK_0_0_OLD_BEHAVIOUR_SEND_ALIGNS_SHIFT)
#define SATA0_CFG_LINK_0_0_OLD_BEHAVIOUR_SEND_ALIGNS_RANGE 15:15
#define SATA0_CFG_LINK_0_0_OLD_BEHAVIOUR_SEND_ALIGNS_WOFFSET 0
#define SATA0_CFG_LINK_0_0_OLD_BEHAVIOUR_SEND_ALIGNS_YES   _MK_ENUM_CONST(0x00000001)                                                       // RW--V
#define SATA0_CFG_LINK_0_0_OLD_BEHAVIOUR_SEND_ALIGNS_NO    _MK_ENUM_CONST(0x00000000)                                                       // RWC-V
#define SATA0_CFG_LINK_0_0_SEND_NEG_RD_ALIGNS_SHIFT         _MK_SHIFT_CONST(16)                                                             // RWC-F
#define SATA0_CFG_LINK_0_0_SEND_NEG_RD_ALIGNS_FIELD        (_MK_SHIFT_CONST(0x1) << SATA0_CFG_LINK_0_0_SEND_NEG_RD_ALIGNS_SHIFT)
#define SATA0_CFG_LINK_0_0_SEND_NEG_RD_ALIGNS_RANGE        16:16
#define SATA0_CFG_LINK_0_0_SEND_NEG_RD_ALIGNS_WOFFSET      0
#define SATA0_CFG_LINK_0_0_SEND_NEG_RD_ALIGNS_YES          _MK_ENUM_CONST(0x00000001)                                                       // RWC-V
#define SATA0_CFG_LINK_0_0_SEND_NEG_RD_ALIGNS_NO           _MK_ENUM_CONST(0x00000000)                                                       // RW--V
#define SATA0_CFG_LINK_0_0_DONT_CHK_PHYRDY_IN_NO_COMM_SHIFT  _MK_SHIFT_CONST(17)                                                             // RWC-F
#define SATA0_CFG_LINK_0_0_DONT_CHK_PHYRDY_IN_NO_COMM_FIELD (_MK_SHIFT_CONST(0x1) << SATA0_CFG_LINK_0_0_DONT_CHK_PHYRDY_IN_NO_COMM_SHIFT)
#define SATA0_CFG_LINK_0_0_DONT_CHK_PHYRDY_IN_NO_COMM_RANGE 17:17
#define SATA0_CFG_LINK_0_0_DONT_CHK_PHYRDY_IN_NO_COMM_WOFFSET 0
#define SATA0_CFG_LINK_0_0_DONT_CHK_PHYRDY_IN_NO_COMM_YES  _MK_ENUM_CONST(0x00000001)                                                       // RW--V
#define SATA0_CFG_LINK_0_0_DONT_CHK_PHYRDY_IN_NO_COMM_NO   _MK_ENUM_CONST(0x00000000)                                                       // RWC-V
#define SATA0_CFG_LINK_0_0_GOTO_WAKE_UP4_SHIFT              _MK_SHIFT_CONST(18)                                                             // RWC-F
#define SATA0_CFG_LINK_0_0_GOTO_WAKE_UP4_FIELD             (_MK_SHIFT_CONST(0x1) << SATA0_CFG_LINK_0_0_GOTO_WAKE_UP4_SHIFT)
#define SATA0_CFG_LINK_0_0_GOTO_WAKE_UP4_RANGE             18:18
#define SATA0_CFG_LINK_0_0_GOTO_WAKE_UP4_WOFFSET           0
#define SATA0_CFG_LINK_0_0_GOTO_WAKE_UP4_YES               _MK_ENUM_CONST(0x00000001)                                                       // RWC-V
#define SATA0_CFG_LINK_0_0_GOTO_WAKE_UP4_NO                _MK_ENUM_CONST(0x00000000)                                                       // RW--V
#define SATA0_CFG_LINK_0_0_USE_AHCI_MODE_FOR_COMRESET_SHIFT  _MK_SHIFT_CONST(19)                                                             // RWC-F
#define SATA0_CFG_LINK_0_0_USE_AHCI_MODE_FOR_COMRESET_FIELD (_MK_SHIFT_CONST(0x1) << SATA0_CFG_LINK_0_0_USE_AHCI_MODE_FOR_COMRESET_SHIFT)
#define SATA0_CFG_LINK_0_0_USE_AHCI_MODE_FOR_COMRESET_RANGE 19:19
#define SATA0_CFG_LINK_0_0_USE_AHCI_MODE_FOR_COMRESET_WOFFSET 0
#define SATA0_CFG_LINK_0_0_USE_AHCI_MODE_FOR_COMRESET_YES  _MK_ENUM_CONST(0x00000001)                                                       // RWC-V
#define SATA0_CFG_LINK_0_0_WAIT_FOR_PSM_FOR_PMOFF_SHIFT     _MK_SHIFT_CONST(20)                                                             // RWC-F
#define SATA0_CFG_LINK_0_0_WAIT_FOR_PSM_FOR_PMOFF_FIELD    (_MK_SHIFT_CONST(0x1) << SATA0_CFG_LINK_0_0_WAIT_FOR_PSM_FOR_PMOFF_SHIFT)
#define SATA0_CFG_LINK_0_0_WAIT_FOR_PSM_FOR_PMOFF_RANGE    20:20
#define SATA0_CFG_LINK_0_0_WAIT_FOR_PSM_FOR_PMOFF_WOFFSET  0
#define SATA0_CFG_LINK_0_0_WAIT_FOR_PSM_FOR_PMOFF_INIT     _MK_ENUM_CONST(0x00000001)                                                       // RWC-V
#define SATA0_CFG_LINK_0_0_USE_IS_PRIM_FOR_BIST_SHIFT       _MK_SHIFT_CONST(21)                                                             // RWWVF
#define SATA0_CFG_LINK_0_0_USE_IS_PRIM_FOR_BIST_FIELD      (_MK_SHIFT_CONST(0x1) << SATA0_CFG_LINK_0_0_USE_IS_PRIM_FOR_BIST_SHIFT)
#define SATA0_CFG_LINK_0_0_USE_IS_PRIM_FOR_BIST_RANGE      21:21
#define SATA0_CFG_LINK_0_0_USE_IS_PRIM_FOR_BIST_WOFFSET    0
#define SATA0_CFG_LINK_0_0_USE_IS_PRIM_FOR_BIST_DEFAULT    (_MK_MASK_CONST(0x00000000)
#define SATA0_CFG_LINK_0_0_USE_IS_PRIM_FOR_BIST_DEFAULT_MASK (_MK_MASK_CONST(0x1)
#define SATA0_CFG_LINK_0_0_USE_IS_PRIM_FOR_BIST_SW_DEFAULT (_MK_MASK_CONST(0x00000000)
#define SATA0_CFG_LINK_0_0_USE_IS_PRIM_FOR_BIST_SW_DEFAULT_MASK (_MK_MASK_CONST(0x1)
#define SATA0_CFG_LINK_0_0_USE_IS_PRIM_FOR_BIST_INIT       _MK_ENUM_CONST(0x00000000)                                                       // RWW-V
#define SATA0_CFG_LINK_0_0_HARDCODE_DISPARITY_ON_WAKE_SHIFT  _MK_SHIFT_CONST(22)                                                             // RWC-F
#define SATA0_CFG_LINK_0_0_HARDCODE_DISPARITY_ON_WAKE_FIELD (_MK_SHIFT_CONST(0x1) << SATA0_CFG_LINK_0_0_HARDCODE_DISPARITY_ON_WAKE_SHIFT)
#define SATA0_CFG_LINK_0_0_HARDCODE_DISPARITY_ON_WAKE_RANGE 22:22
#define SATA0_CFG_LINK_0_0_HARDCODE_DISPARITY_ON_WAKE_WOFFSET 0
#define SATA0_CFG_LINK_0_0_HARDCODE_DISPARITY_ON_WAKE_YES  _MK_ENUM_CONST(0x00000001)                                                       // RWC-V
#define SATA0_CFG_LINK_0_0_HARDCODE_DISPARITY_ON_WAKE_NO   _MK_ENUM_CONST(0x00000000)                                                       // RW--V
#define SATA0_CFG_LINK_0_0_USE_DET_OR_PSM2LL_RESET_SHIFT    _MK_SHIFT_CONST(23)                                                             // RWCVF
#define SATA0_CFG_LINK_0_0_USE_DET_OR_PSM2LL_RESET_FIELD   (_MK_SHIFT_CONST(0x1) << SATA0_CFG_LINK_0_0_USE_DET_OR_PSM2LL_RESET_SHIFT)
#define SATA0_CFG_LINK_0_0_USE_DET_OR_PSM2LL_RESET_RANGE   23:23
#define SATA0_CFG_LINK_0_0_USE_DET_OR_PSM2LL_RESET_WOFFSET 0
#define SATA0_CFG_LINK_0_0_USE_DET_OR_PSM2LL_RESET_INIT    _MK_ENUM_CONST(0x00000001)                                                       // RWC-V
#define SATA0_CFG_LINK_0_0_USE_POSEDGE_SCTL_DET_SHIFT       _MK_SHIFT_CONST(24)                                                             // RWCVF
#define SATA0_CFG_LINK_0_0_USE_POSEDGE_SCTL_DET_FIELD      (_MK_SHIFT_CONST(0x1) << SATA0_CFG_LINK_0_0_USE_POSEDGE_SCTL_DET_SHIFT)
#define SATA0_CFG_LINK_0_0_USE_POSEDGE_SCTL_DET_RANGE      24:24
#define SATA0_CFG_LINK_0_0_USE_POSEDGE_SCTL_DET_WOFFSET    0
#define SATA0_CFG_LINK_0_0_USE_POSEDGE_SCTL_DET_INIT       _MK_ENUM_CONST(0x00000001)                                                       // RWC-V
#define SATA0_CFG_LINK_0_0_RSVD_SHIFT                       _MK_SHIFT_CONST(25)                                                             // C--VF
#define SATA0_CFG_LINK_0_0_RSVD_FIELD                      (_MK_SHIFT_CONST(0x7f) << SATA0_CFG_LINK_0_0_RSVD_SHIFT)
#define SATA0_CFG_LINK_0_0_RSVD_RANGE                      31:25
#define SATA0_CFG_LINK_0_0_RSVD_WOFFSET                    0
#define SATA0_CFG_LINK_0_0_RSVD_VAL                        _MK_ENUM_CONST(0x00000000)                                                       // C---V
// .LABEL PRIVATE INT_REL
// 
// 
// .LABEL PUBLIC
// 
// 
// .LABEL PUBLIC
// 
// .LABEL PUBLIC
// 
// .LABEL PRIVATE INT_REL
// 
// .LABEL PRIVATE INT_REL
// 
// .LABEL PRIVATE INT_REL
// 
// .LABEL PRIVATE INT_REL
// 
// .LABEL PRIVATE INT_REL
// 
// .LABEL PRIVATE INT_REL
// 
// .LABEL PRIVATE INT_REL
// 
// .LABEL PRIVATE INT_REL
// 
// .LABEL PRIVATE INT_REL
// 
// .LABEL PRIVATE INT_REL
// 
// .LABEL PRIVATE INT_REL
// 
// .LABEL PRIVATE INT_REL
// 
// 
// .LABEL PRIVATE INT_REL
// 
// .LABEL PRIVATE INT_REL
// 
// //} SATA0_CTRLR
// 
// .LABEL PUBLIC
// 
// .LABEL PRIVATE INT_REL
// .TITLE CFG_LINK_1
// .FIELD GEN2_DWRD_WAIT_CNT
// This field is the number of generation2 ALIGN dwords controller sends to drive while
// waiting for gen2 align from drive, before it gives up and switches to gen1 mode of
// operation. It should be set to a value smaller than 2*2048. And, it should also be divisible
// by 2.
// 
// 
// .FIELD GEN3_DWRD_WAIT_CNT
// This field is the number of generation3 ALIGN dwords controller sends to drive while
// waiting for gen3 align from drive, before it gives up and switches to gen2 mode of
// operation. It should be set to a value smaller than 2*2048. And, it should also be divisible
// by 2.
// 
// 
// 31           24 23           16 15            8 7             0
// .-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-.
// |0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0| CFG_LINK_1
// `-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-'
// .LABEL PRIVATE INT_REL
#define SATA0_CFG_LINK_1_0                                 0x00000178                                                                       // RWC4R
#define SATA0_CFG_LINK_1_0_SECURE                          0
#define SATA0_CFG_LINK_1_0_WORD_COUNT                      1
#define SATA0_CFG_LINK_1_0_RESET_VAL                       0x0
#define SATA0_CFG_LINK_1_0_RESET_MASK                      0x0
#define SATA0_CFG_LINK_1_0_SW_DEFAULT_VAL                  0x0
#define SATA0_CFG_LINK_1_0_SW_DEFAULT_MASK                 0x0
#define SATA0_CFG_LINK_1_0_READ_MASK                       0xffffffff
#define SATA0_CFG_LINK_1_0_WRITE_MASK                      0xffffffff
#define SATA0_CFG_LINK_1_0_GEN2_DWRD_WAIT_CNT_SHIFT         _MK_SHIFT_CONST(0)                                                              // RWC-F
#define SATA0_CFG_LINK_1_0_GEN2_DWRD_WAIT_CNT_FIELD        (_MK_SHIFT_CONST(0xffff) << SATA0_CFG_LINK_1_0_GEN2_DWRD_WAIT_CNT_SHIFT)
#define SATA0_CFG_LINK_1_0_GEN2_DWRD_WAIT_CNT_RANGE        15:0
#define SATA0_CFG_LINK_1_0_GEN2_DWRD_WAIT_CNT_WOFFSET      0
#define SATA0_CFG_LINK_1_0_GEN2_DWRD_WAIT_CNT_INIT         _MK_ENUM_CONST(0x00000200)                                                       // RWC-V
#define SATA0_CFG_LINK_1_0_GEN3_DWRD_WAIT_CNT_SHIFT         _MK_SHIFT_CONST(16)                                                             // RWC-F
#define SATA0_CFG_LINK_1_0_GEN3_DWRD_WAIT_CNT_FIELD        (_MK_SHIFT_CONST(0xffff) << SATA0_CFG_LINK_1_0_GEN3_DWRD_WAIT_CNT_SHIFT)
#define SATA0_CFG_LINK_1_0_GEN3_DWRD_WAIT_CNT_RANGE        31:16
#define SATA0_CFG_LINK_1_0_GEN3_DWRD_WAIT_CNT_WOFFSET      0
#define SATA0_CFG_LINK_1_0_GEN3_DWRD_WAIT_CNT_INIT         _MK_ENUM_CONST(0x00000200)                                                       // RWC-V
// 
// 
// .TITLE CFG_LINK_2
// .FIELD PHYRDY_DBNC_MUX
// We have a debounced version of phyrdy which has two options 10ms and 10us (for a clock of around 100MHz - devclk)
// Many issues were observed because of this in MCP79 and MCP89, adding a programibilty to this to overcome such issues
// 31           24 23           16 15            8 7             0
// .-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-.
// |0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0| CFG_LINK_2
// `-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-'
#define SATA0_CFG_LINK_2_0                                 0x0000017C                                                                       // RWC4R
#define SATA0_CFG_LINK_2_0_SECURE                          0
#define SATA0_CFG_LINK_2_0_WORD_COUNT                      1
#define SATA0_CFG_LINK_2_0_RESET_VAL                       0x0
#define SATA0_CFG_LINK_2_0_RESET_MASK                      0x0
#define SATA0_CFG_LINK_2_0_SW_DEFAULT_VAL                  0x0
#define SATA0_CFG_LINK_2_0_SW_DEFAULT_MASK                 0x0
#define SATA0_CFG_LINK_2_0_READ_MASK                       0xffff
#define SATA0_CFG_LINK_2_0_WRITE_MASK                      0xffff
#define SATA0_CFG_LINK_2_0_PHYRDY_DBNC_MUX_SHIFT            _MK_SHIFT_CONST(0)                                                              // RWC-F
#define SATA0_CFG_LINK_2_0_PHYRDY_DBNC_MUX_FIELD           (_MK_SHIFT_CONST(0x7ff) << SATA0_CFG_LINK_2_0_PHYRDY_DBNC_MUX_SHIFT)
#define SATA0_CFG_LINK_2_0_PHYRDY_DBNC_MUX_RANGE           10:0
#define SATA0_CFG_LINK_2_0_PHYRDY_DBNC_MUX_WOFFSET         0
#define SATA0_CFG_LINK_2_0_PHYRDY_DBNC_MUX_INIT            _MK_ENUM_CONST(0x00000080)                                                       // RWC-V
#define SATA0_CFG_LINK_2_0_USE_BIT_FOR_DEBOUNCE_SHIFT       _MK_SHIFT_CONST(11)                                                             // RWC-F
#define SATA0_CFG_LINK_2_0_USE_BIT_FOR_DEBOUNCE_FIELD      (_MK_SHIFT_CONST(0x1) << SATA0_CFG_LINK_2_0_USE_BIT_FOR_DEBOUNCE_SHIFT)
#define SATA0_CFG_LINK_2_0_USE_BIT_FOR_DEBOUNCE_RANGE      11:11
#define SATA0_CFG_LINK_2_0_USE_BIT_FOR_DEBOUNCE_WOFFSET    0
#define SATA0_CFG_LINK_2_0_USE_BIT_FOR_DEBOUNCE_INIT       _MK_ENUM_CONST(0x00000000)                                                       // RWC-V
#define SATA0_CFG_LINK_2_0_PHYRDY_USE_ITH_BIT_SHIFT         _MK_SHIFT_CONST(12)                                                             // RWC-F
#define SATA0_CFG_LINK_2_0_PHYRDY_USE_ITH_BIT_FIELD        (_MK_SHIFT_CONST(0xf) << SATA0_CFG_LINK_2_0_PHYRDY_USE_ITH_BIT_SHIFT)
#define SATA0_CFG_LINK_2_0_PHYRDY_USE_ITH_BIT_RANGE        15:12
#define SATA0_CFG_LINK_2_0_PHYRDY_USE_ITH_BIT_WOFFSET      0
#define SATA0_CFG_LINK_2_0_PHYRDY_USE_ITH_BIT_INIT         _MK_ENUM_CONST(0x00000007)                                                       // RWC-V
// 
// 
// .LABEL PUBLIC
// 
// .LABEL PRIVATE INT_REL
// .TITLE CFG_TRANS_0
// .FIELD F2I_FIFO_FLUSH_FIX
// .LABEL PRIVATE
// //The fix is being reverted because of bug 655485
// .LABEL PRIVATE INT_REL
// 
// 
// // Fix for BUG 432717(to clear F2I_FIFO on sending a command FIS)
// 
// 
// 31           24 23           16 15            8 7             0
// .-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-.
// |0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0| CFG_TRANS_0
// `-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-'
#define SATA0_CFG_TRANS_0_0                                0x000001D0                                                                       // RWC4R
#define SATA0_CFG_TRANS_0_0_SECURE                         0
#define SATA0_CFG_TRANS_0_0_WORD_COUNT                     1
#define SATA0_CFG_TRANS_0_0_RESET_VAL                      0x0
#define SATA0_CFG_TRANS_0_0_RESET_MASK                     0x0
#define SATA0_CFG_TRANS_0_0_SW_DEFAULT_VAL                 0x0
#define SATA0_CFG_TRANS_0_0_SW_DEFAULT_MASK                0x0
#define SATA0_CFG_TRANS_0_0_READ_MASK                      0xffffffff
#define SATA0_CFG_TRANS_0_0_WRITE_MASK                     0x3
#define SATA0_CFG_TRANS_0_0_F2I_FIFO_FLUSH_FIX_SHIFT        _MK_SHIFT_CONST(0)                                                              // RWC-F
#define SATA0_CFG_TRANS_0_0_F2I_FIFO_FLUSH_FIX_FIELD       (_MK_SHIFT_CONST(0x1) << SATA0_CFG_TRANS_0_0_F2I_FIFO_FLUSH_FIX_SHIFT)
#define SATA0_CFG_TRANS_0_0_F2I_FIFO_FLUSH_FIX_RANGE       0:0
#define SATA0_CFG_TRANS_0_0_F2I_FIFO_FLUSH_FIX_WOFFSET     0
#define SATA0_CFG_TRANS_0_0_F2I_FIFO_FLUSH_FIX_YES         _MK_ENUM_CONST(0x00000001)                                                       // RW--V
#define SATA0_CFG_TRANS_0_0_F2I_FIFO_FLUSH_FIX_NO          _MK_ENUM_CONST(0x00000000)                                                       // RWC-V
#define SATA0_CFG_TRANS_0_0_USE_RISE_EDGE_STATUS_RESET_SHIFT  _MK_SHIFT_CONST(1)                                                              // RWC-F
#define SATA0_CFG_TRANS_0_0_USE_RISE_EDGE_STATUS_RESET_FIELD (_MK_SHIFT_CONST(0x1) << SATA0_CFG_TRANS_0_0_USE_RISE_EDGE_STATUS_RESET_SHIFT)
#define SATA0_CFG_TRANS_0_0_USE_RISE_EDGE_STATUS_RESET_RANGE 1:1
#define SATA0_CFG_TRANS_0_0_USE_RISE_EDGE_STATUS_RESET_WOFFSET 0
#define SATA0_CFG_TRANS_0_0_USE_RISE_EDGE_STATUS_RESET_YES _MK_ENUM_CONST(0x00000001)                                                       // RWC-V
#define SATA0_CFG_TRANS_0_0_USE_RISE_EDGE_STATUS_RESET_NO  _MK_ENUM_CONST(0x00000000)                                                       // RW--V
#define SATA0_CFG_TRANS_0_0_RSVD_SHIFT                      _MK_SHIFT_CONST(2)                                                              // C--VF
#define SATA0_CFG_TRANS_0_0_RSVD_FIELD                     (_MK_SHIFT_CONST(0x3fffffff) << SATA0_CFG_TRANS_0_0_RSVD_SHIFT)
#define SATA0_CFG_TRANS_0_0_RSVD_RANGE                     31:2
#define SATA0_CFG_TRANS_0_0_RSVD_WOFFSET                   0
#define SATA0_CFG_TRANS_0_0_RSVD_VAL                       _MK_ENUM_CONST(0x00000000)                                                       // C---V
// 
// 
// 
// 
// .LABEL PUBLIC
// .LABEL PUBLIC
// .LABEL PRIVATE INT_REL
// .TITLE ALPM Controls
// 
// .FIELD THRESHOLD
// This field is used to indicate to HBA as to how much time it should wait before
// going to Partial or Slumber power down states. Its used to load the 16-bit start
// value of a down-counter in RTL. Default value zero indicates that if PxCI and
// PxSACT registers are cleared to zero (implies that if there are no commands outstanding)
// the HBA SM will transition to initiate power down.
//  31           24 23           16 15            8 7             0
// .-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-.
// |0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0| ALPM_CTRL
// +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
#define SATA0_ALPM_CTRL_0                                  0x00000238                                                                       // RW-4R
#define SATA0_ALPM_CTRL_0_SECURE                           0
#define SATA0_ALPM_CTRL_0_WORD_COUNT                       1
#define SATA0_ALPM_CTRL_0_RESET_VAL                        0x0
#define SATA0_ALPM_CTRL_0_RESET_MASK                       0x0
#define SATA0_ALPM_CTRL_0_SW_DEFAULT_VAL                   0x0
#define SATA0_ALPM_CTRL_0_SW_DEFAULT_MASK                  0x0
#define SATA0_ALPM_CTRL_0_READ_MASK                        0xffff0000
#define SATA0_ALPM_CTRL_0_WRITE_MASK                       0xffff0000
#define SATA0_ALPM_CTRL_0_THRESHOLD_SHIFT                   _MK_SHIFT_CONST(16)                                                             // RWCVF
#define SATA0_ALPM_CTRL_0_THRESHOLD_FIELD                  (_MK_SHIFT_CONST(0xffff) << SATA0_ALPM_CTRL_0_THRESHOLD_SHIFT)
#define SATA0_ALPM_CTRL_0_THRESHOLD_RANGE                  31:16
#define SATA0_ALPM_CTRL_0_THRESHOLD_WOFFSET                0
// 
//         Figure 10-07 ALPM CTRL - for Control of Counter
// 
// .TITLE FBS_CONFIG_0
// .LABEL PRIVATE INT_REL
// This register implement settings for FIS based switching implementation.
// 
//  31           24 23           16 15            8 7             0
// .-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-.
// |0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0| FBS_CONFIG_0
// +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
#define SATA0_FBS_CONFIG_0_0                               0x0000023C                                                                       // RW-4R
#define SATA0_FBS_CONFIG_0_0_SECURE                        0
#define SATA0_FBS_CONFIG_0_0_WORD_COUNT                    1
#define SATA0_FBS_CONFIG_0_0_RESET_VAL                     0x0
#define SATA0_FBS_CONFIG_0_0_RESET_MASK                    0x0
#define SATA0_FBS_CONFIG_0_0_SW_DEFAULT_VAL                0x0
#define SATA0_FBS_CONFIG_0_0_SW_DEFAULT_MASK               0x0
#define SATA0_FBS_CONFIG_0_0_READ_MASK                     0xffffffff
#define SATA0_FBS_CONFIG_0_0_WRITE_MASK                    0xffffffff
#define SATA0_FBS_CONFIG_0_0_CYA_00_SHIFT                   _MK_SHIFT_CONST(0)                                                              // RWCVF
#define SATA0_FBS_CONFIG_0_0_CYA_00_FIELD                  (_MK_SHIFT_CONST(0x1) << SATA0_FBS_CONFIG_0_0_CYA_00_SHIFT)
#define SATA0_FBS_CONFIG_0_0_CYA_00_RANGE                  0:0
#define SATA0_FBS_CONFIG_0_0_CYA_00_WOFFSET                0
#define SATA0_FBS_CONFIG_0_0_CYA_00_INIT                   _MK_ENUM_CONST(0x00000001)                                                       // RWC-V
#define SATA0_FBS_CONFIG_0_0_CYA_01_SHIFT                   _MK_SHIFT_CONST(1)                                                              // RWCVF
#define SATA0_FBS_CONFIG_0_0_CYA_01_FIELD                  (_MK_SHIFT_CONST(0x1) << SATA0_FBS_CONFIG_0_0_CYA_01_SHIFT)
#define SATA0_FBS_CONFIG_0_0_CYA_01_RANGE                  1:1
#define SATA0_FBS_CONFIG_0_0_CYA_01_WOFFSET                0
#define SATA0_FBS_CONFIG_0_0_CYA_01_INIT                   _MK_ENUM_CONST(0x00000000)                                                       // RWC-V
#define SATA0_FBS_CONFIG_0_0_CYA_02_RSVD_SHIFT              _MK_SHIFT_CONST(2)                                                              // RWCVF
#define SATA0_FBS_CONFIG_0_0_CYA_02_RSVD_FIELD             (_MK_SHIFT_CONST(0x1) << SATA0_FBS_CONFIG_0_0_CYA_02_RSVD_SHIFT)
#define SATA0_FBS_CONFIG_0_0_CYA_02_RSVD_RANGE             2:2
#define SATA0_FBS_CONFIG_0_0_CYA_02_RSVD_WOFFSET           0
#define SATA0_FBS_CONFIG_0_0_CYA_02_RSVD_INIT              _MK_ENUM_CONST(0x00000000)                                                       // RWC-V
#define SATA0_FBS_CONFIG_0_0_CONTROL_PORT_HAS_PRIORITY_SHIFT  _MK_SHIFT_CONST(3)                                                              // RWCVF
#define SATA0_FBS_CONFIG_0_0_CONTROL_PORT_HAS_PRIORITY_FIELD (_MK_SHIFT_CONST(0x1) << SATA0_FBS_CONFIG_0_0_CONTROL_PORT_HAS_PRIORITY_SHIFT)
#define SATA0_FBS_CONFIG_0_0_CONTROL_PORT_HAS_PRIORITY_RANGE 3:3
#define SATA0_FBS_CONFIG_0_0_CONTROL_PORT_HAS_PRIORITY_WOFFSET 0
#define SATA0_FBS_CONFIG_0_0_CONTROL_PORT_HAS_PRIORITY_INIT _MK_ENUM_CONST(0x00000001)                                                       // RWC-V
#define SATA0_FBS_CONFIG_0_0_CONTROL_PORT_SHIFT             _MK_SHIFT_CONST(4)                                                              // RWCVF
#define SATA0_FBS_CONFIG_0_0_CONTROL_PORT_FIELD            (_MK_SHIFT_CONST(0xf) << SATA0_FBS_CONFIG_0_0_CONTROL_PORT_SHIFT)
#define SATA0_FBS_CONFIG_0_0_CONTROL_PORT_RANGE            7:4
#define SATA0_FBS_CONFIG_0_0_CONTROL_PORT_WOFFSET          0
#define SATA0_FBS_CONFIG_0_0_CONTROL_PORT_INIT             _MK_ENUM_CONST(0x0000000f)                                                       // RWC-V
#define SATA0_FBS_CONFIG_0_0_BKDR_ADO_SHIFT                 _MK_SHIFT_CONST(8)                                                              // RWCVF
#define SATA0_FBS_CONFIG_0_0_BKDR_ADO_FIELD                (_MK_SHIFT_CONST(0xf) << SATA0_FBS_CONFIG_0_0_BKDR_ADO_SHIFT)
#define SATA0_FBS_CONFIG_0_0_BKDR_ADO_RANGE                11:8
#define SATA0_FBS_CONFIG_0_0_BKDR_ADO_WOFFSET              0
#define SATA0_FBS_CONFIG_0_0_BKDR_ADO_INIT                 _MK_ENUM_CONST(0x0000000F)                                                       // RWC-V
#define SATA0_FBS_CONFIG_0_0_CYA_02_SHIFT                   _MK_SHIFT_CONST(12)                                                             // RWCVF
#define SATA0_FBS_CONFIG_0_0_CYA_02_FIELD                  (_MK_SHIFT_CONST(0x1) << SATA0_FBS_CONFIG_0_0_CYA_02_SHIFT)
#define SATA0_FBS_CONFIG_0_0_CYA_02_RANGE                  12:12
#define SATA0_FBS_CONFIG_0_0_CYA_02_WOFFSET                0
#define SATA0_FBS_CONFIG_0_0_CYA_02_INIT                   _MK_ENUM_CONST(0x00000001)                                                       // RWC-V
#define SATA0_FBS_CONFIG_0_0_POST_1ST_REGFIS_SHIFT          _MK_SHIFT_CONST(13)                                                             // RWCVF
#define SATA0_FBS_CONFIG_0_0_POST_1ST_REGFIS_FIELD         (_MK_SHIFT_CONST(0x1) << SATA0_FBS_CONFIG_0_0_POST_1ST_REGFIS_SHIFT)
#define SATA0_FBS_CONFIG_0_0_POST_1ST_REGFIS_RANGE         13:13
#define SATA0_FBS_CONFIG_0_0_POST_1ST_REGFIS_WOFFSET       0
#define SATA0_FBS_CONFIG_0_0_POST_1ST_REGFIS_INIT          _MK_ENUM_CONST(0x00000000)                                                       // RWC-V
#define SATA0_FBS_CONFIG_0_0_PRD_PROCESS_FIX_SHIFT          _MK_SHIFT_CONST(14)                                                             // RWCVF
#define SATA0_FBS_CONFIG_0_0_PRD_PROCESS_FIX_FIELD         (_MK_SHIFT_CONST(0x3) << SATA0_FBS_CONFIG_0_0_PRD_PROCESS_FIX_SHIFT)
#define SATA0_FBS_CONFIG_0_0_PRD_PROCESS_FIX_RANGE         15:14
#define SATA0_FBS_CONFIG_0_0_PRD_PROCESS_FIX_WOFFSET       0
#define SATA0_FBS_CONFIG_0_0_PRD_PROCESS_FIX_INIT          _MK_ENUM_CONST(0x00000003)                                                       // RWC-V
#define SATA0_FBS_CONFIG_0_0_CYA_03_RSVD_SHIFT              _MK_SHIFT_CONST(16)                                                             // RWCVF
#define SATA0_FBS_CONFIG_0_0_CYA_03_RSVD_FIELD             (_MK_SHIFT_CONST(0xffff) << SATA0_FBS_CONFIG_0_0_CYA_03_RSVD_SHIFT)
#define SATA0_FBS_CONFIG_0_0_CYA_03_RSVD_RANGE             31:16
#define SATA0_FBS_CONFIG_0_0_CYA_03_RSVD_WOFFSET           0
#define SATA0_FBS_CONFIG_0_0_CYA_03_RSVD_INIT              _MK_ENUM_CONST(0x0000F0F0)                                                       // RWC-V
// .define T_SATA0_FBS_CONFIG_0_CTL_00                                   0:0 /* RWCVF */
// .define T_SATA0_FBS_CONFIG_0_CTL_00_INIT                       0x00000001 /* RWC-V */
// .define T_SATA0_FBS_CONFIG_0_CTL_01                                   1:1 /* RWCVF */
// .define T_SATA0_FBS_CONFIG_0_CTL_01_INIT                       0x00000000 /* RWC-V */
// .define T_SATA0_FBS_CONFIG_0_CTL_02_RSVD                              2:2 /* RWCVF */
// .define T_SATA0_FBS_CONFIG_0_CTL_02_RSVD_INIT                  0x00000000 /* RWC-V */
// .define T_SATA0_FBS_CONFIG_0_CTL_02                                 12:12 /* RWCVF */
// .define T_SATA0_FBS_CONFIG_0_CTL_02_INIT                       0x00000001 /* RWC-V */
// .define T_SATA0_FBS_CONFIG_0_CTL_03_RSVD                            31:16 /* RWCVF */
// .define T_SATA0_FBS_CONFIG_0_CTL_03_RSVD_INIT                  0x0000F0F0 /* RWC-V */
// 
// 
// .TITLE FBS_CONFIG_1
// .LABEL PRIVATE INT_REL
// This register implement settings for FIS based switching implementation.
// 
//  31           24 23           16 15            8 7             0
// .-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-.
// |0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0| FBS_CONFIG_1
// +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
#define SATA0_CHX_FBS_CONFIG_1_0                           0x00000240                                                                       // RW-4R
#define SATA0_CHX_FBS_CONFIG_1_0_SECURE                    0
#define SATA0_CHX_FBS_CONFIG_1_0_WORD_COUNT                1
#define SATA0_CHX_FBS_CONFIG_1_0_RESET_VAL                 0x0
#define SATA0_CHX_FBS_CONFIG_1_0_RESET_MASK                0x0
#define SATA0_CHX_FBS_CONFIG_1_0_SW_DEFAULT_VAL            0x0
#define SATA0_CHX_FBS_CONFIG_1_0_SW_DEFAULT_MASK           0x0
#define SATA0_CHX_FBS_CONFIG_1_0_READ_MASK                 0xffffffff
#define SATA0_CHX_FBS_CONFIG_1_0_WRITE_MASK                0x1
#define SATA0_CHX_FBS_CONFIG_1_0_PORT_BKDR_FBSCP_SHIFT      _MK_SHIFT_CONST(0)                                                              // RWCVF
#define SATA0_CHX_FBS_CONFIG_1_0_PORT_BKDR_FBSCP_FIELD     (_MK_SHIFT_CONST(0x1) << SATA0_CHX_FBS_CONFIG_1_0_PORT_BKDR_FBSCP_SHIFT)
#define SATA0_CHX_FBS_CONFIG_1_0_PORT_BKDR_FBSCP_RANGE     0:0
#define SATA0_CHX_FBS_CONFIG_1_0_PORT_BKDR_FBSCP_WOFFSET   0
#define SATA0_CHX_FBS_CONFIG_1_0_PORT_BKDR_FBSCP_INIT      _MK_ENUM_CONST(0x00000000)                                                       // RWC-V
#define SATA0_CHX_FBS_CONFIG_1_0_RSVD_1_31_SHIFT            _MK_SHIFT_CONST(1)                                                              // C--VF
#define SATA0_CHX_FBS_CONFIG_1_0_RSVD_1_31_FIELD           (_MK_SHIFT_CONST(0x7fffffff) << SATA0_CHX_FBS_CONFIG_1_0_RSVD_1_31_SHIFT)
#define SATA0_CHX_FBS_CONFIG_1_0_RSVD_1_31_RANGE           31:1
#define SATA0_CHX_FBS_CONFIG_1_0_RSVD_1_31_WOFFSET         0
#define SATA0_CHX_FBS_CONFIG_1_0_RSVD_1_31_VAL             _MK_ENUM_CONST(0x00000000)                                                       // C---V
// 
//         Figure 10-09 FBS Config 1
// .LABEL PUBLIC
// 
// 
// 
// .LABEL PUBLIC
// 
// .LABEL PRIVATE INT_REL
// .TITLE HBA_CAP_BKDR
// This register will have a backdoor field for every bit described in AHCI1.2 spec
// .FIELD EXT_SATA
// This is a backdoor access for enabling external sata.
// 
// .FIELD SUPP_STG_SPUP
// Backdoor field to advertise staggered spin up. BIOS has to write this we are going to support staggered spin up.
// 
// 31           24 23           16 15            8 7             0
// .-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-.
// |0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0| HBA_CAP_BKDR
// `-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-'
// 
#define SATA0_AHCI_HBA_CAP_BKDR_0                          0x00000300                                                                       // RW-4R
#define SATA0_AHCI_HBA_CAP_BKDR_0_SECURE                   0
#define SATA0_AHCI_HBA_CAP_BKDR_0_WORD_COUNT               1
#define SATA0_AHCI_HBA_CAP_BKDR_0_RESET_VAL                0x0
#define SATA0_AHCI_HBA_CAP_BKDR_0_RESET_MASK               0x0
#define SATA0_AHCI_HBA_CAP_BKDR_0_SW_DEFAULT_VAL           0x0
#define SATA0_AHCI_HBA_CAP_BKDR_0_SW_DEFAULT_MASK          0x0
#define SATA0_AHCI_HBA_CAP_BKDR_0_READ_MASK                0xffffffff
#define SATA0_AHCI_HBA_CAP_BKDR_0_WRITE_MASK               0xffffffff
#define SATA0_AHCI_HBA_CAP_BKDR_0_NUM_PORTS_SHIFT           _MK_SHIFT_CONST(0)                                                              // RWCVF
#define SATA0_AHCI_HBA_CAP_BKDR_0_NUM_PORTS_FIELD          (_MK_SHIFT_CONST(0x1f) << SATA0_AHCI_HBA_CAP_BKDR_0_NUM_PORTS_SHIFT)
#define SATA0_AHCI_HBA_CAP_BKDR_0_NUM_PORTS_RANGE          4:0
#define SATA0_AHCI_HBA_CAP_BKDR_0_NUM_PORTS_WOFFSET        0
#define SATA0_AHCI_HBA_CAP_BKDR_0_NUM_PORTS_1              _MK_ENUM_CONST(0x00000000)                                                       // RW--V
#define SATA0_AHCI_HBA_CAP_BKDR_0_NUM_PORTS_2              _MK_ENUM_CONST(0x00000001)                                                       // RW--V
#define SATA0_AHCI_HBA_CAP_BKDR_0_NUM_PORTS_3              _MK_ENUM_CONST(0x00000002)                                                       // RW--V
#define SATA0_AHCI_HBA_CAP_BKDR_0_NUM_PORTS_4              _MK_ENUM_CONST(0x00000003)                                                       // RW--V
#define SATA0_AHCI_HBA_CAP_BKDR_0_NUM_PORTS_DEFUALT        _MK_ENUM_CONST(0x00000001)                                                       // R-C-V
#define SATA0_AHCI_HBA_CAP_BKDR_0_EXT_SATA_SHIFT            _MK_SHIFT_CONST(5)                                                              // RWCVF
#define SATA0_AHCI_HBA_CAP_BKDR_0_EXT_SATA_FIELD           (_MK_SHIFT_CONST(0x1) << SATA0_AHCI_HBA_CAP_BKDR_0_EXT_SATA_SHIFT)
#define SATA0_AHCI_HBA_CAP_BKDR_0_EXT_SATA_RANGE           5:5
#define SATA0_AHCI_HBA_CAP_BKDR_0_EXT_SATA_WOFFSET         0
#define SATA0_AHCI_HBA_CAP_BKDR_0_EXT_SATA_SUPPORTED       _MK_ENUM_CONST(0x00000001)                                                       // RW--V
#define SATA0_AHCI_HBA_CAP_BKDR_0_EXT_SATA_NOT_SUPPORTED   _MK_ENUM_CONST(0x00000000)                                                       // RWC-V
#define SATA0_AHCI_HBA_CAP_BKDR_0_ENCL_MGMT_SUPP_SHIFT      _MK_SHIFT_CONST(6)                                                              // RWCVF
#define SATA0_AHCI_HBA_CAP_BKDR_0_ENCL_MGMT_SUPP_FIELD     (_MK_SHIFT_CONST(0x1) << SATA0_AHCI_HBA_CAP_BKDR_0_ENCL_MGMT_SUPP_SHIFT)
#define SATA0_AHCI_HBA_CAP_BKDR_0_ENCL_MGMT_SUPP_RANGE     6:6
#define SATA0_AHCI_HBA_CAP_BKDR_0_ENCL_MGMT_SUPP_WOFFSET   0
#define SATA0_AHCI_HBA_CAP_BKDR_0_ENCL_MGMT_SUPP_TRUE      _MK_ENUM_CONST(0x00000001)                                                       // RW--V
#define SATA0_AHCI_HBA_CAP_BKDR_0_ENCL_MGMT_SUPP_FALSE     _MK_ENUM_CONST(0x00000000)                                                       // RWC-V
#define SATA0_AHCI_HBA_CAP_BKDR_0_CMD_CMPL_COALESING_SHIFT  _MK_SHIFT_CONST(7)                                                              // RWCVF
#define SATA0_AHCI_HBA_CAP_BKDR_0_CMD_CMPL_COALESING_FIELD (_MK_SHIFT_CONST(0x1) << SATA0_AHCI_HBA_CAP_BKDR_0_CMD_CMPL_COALESING_SHIFT)
#define SATA0_AHCI_HBA_CAP_BKDR_0_CMD_CMPL_COALESING_RANGE 7:7
#define SATA0_AHCI_HBA_CAP_BKDR_0_CMD_CMPL_COALESING_WOFFSET 0
#define SATA0_AHCI_HBA_CAP_BKDR_0_CMD_CMPL_COALESING_TRUE  _MK_ENUM_CONST(0x00000001)                                                       // RW--V
#define SATA0_AHCI_HBA_CAP_BKDR_0_CMD_CMPL_COALESING_FALSE _MK_ENUM_CONST(0x00000000)                                                       // RWC-V
#define SATA0_AHCI_HBA_CAP_BKDR_0_NUM_CMD_SLOTS_SHIFT       _MK_SHIFT_CONST(8)                                                              // RWCVF
#define SATA0_AHCI_HBA_CAP_BKDR_0_NUM_CMD_SLOTS_FIELD      (_MK_SHIFT_CONST(0x1f) << SATA0_AHCI_HBA_CAP_BKDR_0_NUM_CMD_SLOTS_SHIFT)
#define SATA0_AHCI_HBA_CAP_BKDR_0_NUM_CMD_SLOTS_RANGE      12:8
#define SATA0_AHCI_HBA_CAP_BKDR_0_NUM_CMD_SLOTS_WOFFSET    0
#define SATA0_AHCI_HBA_CAP_BKDR_0_NUM_CMD_SLOTS_1          _MK_ENUM_CONST(0x00000000)                                                       // RW--V
#define SATA0_AHCI_HBA_CAP_BKDR_0_NUM_CMD_SLOTS_8          _MK_ENUM_CONST(0x00000007)                                                       // RW--V
#define SATA0_AHCI_HBA_CAP_BKDR_0_NUM_CMD_SLOTS_16         _MK_ENUM_CONST(0x0000000F)                                                       // RW--V
#define SATA0_AHCI_HBA_CAP_BKDR_0_NUM_CMD_SLOTS_32         _MK_ENUM_CONST(0x0000001F)                                                       // RWC-V
#define SATA0_AHCI_HBA_CAP_BKDR_0_PARTIAL_ST_CAP_SHIFT      _MK_SHIFT_CONST(13)                                                             // RWCVF
#define SATA0_AHCI_HBA_CAP_BKDR_0_PARTIAL_ST_CAP_FIELD     (_MK_SHIFT_CONST(0x1) << SATA0_AHCI_HBA_CAP_BKDR_0_PARTIAL_ST_CAP_SHIFT)
#define SATA0_AHCI_HBA_CAP_BKDR_0_PARTIAL_ST_CAP_RANGE     13:13
#define SATA0_AHCI_HBA_CAP_BKDR_0_PARTIAL_ST_CAP_WOFFSET   0
#define SATA0_AHCI_HBA_CAP_BKDR_0_PARTIAL_ST_CAP__WRNPRDCHK _MK_ENUM_CONST(0x00000001)                                                       // ----V
#define SATA0_AHCI_HBA_CAP_BKDR_0_PARTIAL_ST_CAP_TRUE      _MK_ENUM_CONST(0x00000001)                                                       // RWC-V
#define SATA0_AHCI_HBA_CAP_BKDR_0_PARTIAL_ST_CAP_FALSE     _MK_ENUM_CONST(0x00000000)                                                       // RW--V
#define SATA0_AHCI_HBA_CAP_BKDR_0_SLUMBER_ST_CAP_SHIFT      _MK_SHIFT_CONST(14)                                                             // RWCVF
#define SATA0_AHCI_HBA_CAP_BKDR_0_SLUMBER_ST_CAP_FIELD     (_MK_SHIFT_CONST(0x1) << SATA0_AHCI_HBA_CAP_BKDR_0_SLUMBER_ST_CAP_SHIFT)
#define SATA0_AHCI_HBA_CAP_BKDR_0_SLUMBER_ST_CAP_RANGE     14:14
#define SATA0_AHCI_HBA_CAP_BKDR_0_SLUMBER_ST_CAP_WOFFSET   0
#define SATA0_AHCI_HBA_CAP_BKDR_0_SLUMBER_ST_CAP__WRNPRDCHK _MK_ENUM_CONST(0x00000001)                                                       // ----V
#define SATA0_AHCI_HBA_CAP_BKDR_0_SLUMBER_ST_CAP_TRUE      _MK_ENUM_CONST(0x00000001)                                                       // RWC-V
#define SATA0_AHCI_HBA_CAP_BKDR_0_SLUMBER_ST_CAP_FALSE     _MK_ENUM_CONST(0x00000000)                                                       // RW--V
#define SATA0_AHCI_HBA_CAP_BKDR_0_PIO_MULT_DRQ_BLK_SHIFT    _MK_SHIFT_CONST(15)                                                             // RWCVF
#define SATA0_AHCI_HBA_CAP_BKDR_0_PIO_MULT_DRQ_BLK_FIELD   (_MK_SHIFT_CONST(0x1) << SATA0_AHCI_HBA_CAP_BKDR_0_PIO_MULT_DRQ_BLK_SHIFT)
#define SATA0_AHCI_HBA_CAP_BKDR_0_PIO_MULT_DRQ_BLK_RANGE   15:15
#define SATA0_AHCI_HBA_CAP_BKDR_0_PIO_MULT_DRQ_BLK_WOFFSET 0
#define SATA0_AHCI_HBA_CAP_BKDR_0_PIO_MULT_DRQ_BLK_SUPP    _MK_ENUM_CONST(0x00000001)                                                       // RWC-V
#define SATA0_AHCI_HBA_CAP_BKDR_0_PIO_MULT_DRQ_BLK_NOT_SUPP _MK_ENUM_CONST(0x00000000)                                                       // RW--V
#define SATA0_AHCI_HBA_CAP_BKDR_0_FIS_SWITCHING_SHIFT       _MK_SHIFT_CONST(16)                                                             // RWCVF
#define SATA0_AHCI_HBA_CAP_BKDR_0_FIS_SWITCHING_FIELD      (_MK_SHIFT_CONST(0x1) << SATA0_AHCI_HBA_CAP_BKDR_0_FIS_SWITCHING_SHIFT)
#define SATA0_AHCI_HBA_CAP_BKDR_0_FIS_SWITCHING_RANGE      16:16
#define SATA0_AHCI_HBA_CAP_BKDR_0_FIS_SWITCHING_WOFFSET    0
#define SATA0_AHCI_HBA_CAP_BKDR_0_FIS_SWITCHING_TRUE       _MK_ENUM_CONST(0x00000001)                                                       // RW--V
#define SATA0_AHCI_HBA_CAP_BKDR_0_FIS_SWITCHING_FALSE      _MK_ENUM_CONST(0x00000000)                                                       // RWC-V
#define SATA0_AHCI_HBA_CAP_BKDR_0_SUPP_PM_SHIFT             _MK_SHIFT_CONST(17)                                                             // RWCVF
#define SATA0_AHCI_HBA_CAP_BKDR_0_SUPP_PM_FIELD            (_MK_SHIFT_CONST(0x1) << SATA0_AHCI_HBA_CAP_BKDR_0_SUPP_PM_SHIFT)
#define SATA0_AHCI_HBA_CAP_BKDR_0_SUPP_PM_RANGE            17:17
#define SATA0_AHCI_HBA_CAP_BKDR_0_SUPP_PM_WOFFSET          0
#define SATA0_AHCI_HBA_CAP_BKDR_0_SUPP_PM_TRUE             _MK_ENUM_CONST(0x00000001)                                                       // RW--V
#define SATA0_AHCI_HBA_CAP_BKDR_0_SUPP_PM_FALSE            _MK_ENUM_CONST(0x00000000)                                                       // RWC-V
#define SATA0_AHCI_HBA_CAP_BKDR_0_SUPP_AHCI_ONLY_SHIFT      _MK_SHIFT_CONST(18)                                                             // RWCVF
#define SATA0_AHCI_HBA_CAP_BKDR_0_SUPP_AHCI_ONLY_FIELD     (_MK_SHIFT_CONST(0x1) << SATA0_AHCI_HBA_CAP_BKDR_0_SUPP_AHCI_ONLY_SHIFT)
#define SATA0_AHCI_HBA_CAP_BKDR_0_SUPP_AHCI_ONLY_RANGE     18:18
#define SATA0_AHCI_HBA_CAP_BKDR_0_SUPP_AHCI_ONLY_WOFFSET   0
#define SATA0_AHCI_HBA_CAP_BKDR_0_SUPP_AHCI_ONLY_TRUE      _MK_ENUM_CONST(0x00000001)                                                       // RW--V
#define SATA0_AHCI_HBA_CAP_BKDR_0_SUPP_AHCI_ONLY_FALSE     _MK_ENUM_CONST(0x00000000)                                                       // RWC-V
#define SATA0_AHCI_HBA_CAP_BKDR_0_SUPP_NONZERO_OFFSET_SHIFT  _MK_SHIFT_CONST(19)                                                             // RWCVF
#define SATA0_AHCI_HBA_CAP_BKDR_0_SUPP_NONZERO_OFFSET_FIELD (_MK_SHIFT_CONST(0x1) << SATA0_AHCI_HBA_CAP_BKDR_0_SUPP_NONZERO_OFFSET_SHIFT)
#define SATA0_AHCI_HBA_CAP_BKDR_0_SUPP_NONZERO_OFFSET_RANGE 19:19
#define SATA0_AHCI_HBA_CAP_BKDR_0_SUPP_NONZERO_OFFSET_WOFFSET 0
#define SATA0_AHCI_HBA_CAP_BKDR_0_SUPP_NONZERO_OFFSET_TRUE _MK_ENUM_CONST(0x00000001)                                                       // RW--V
#define SATA0_AHCI_HBA_CAP_BKDR_0_SUPP_NONZERO_OFFSET_FALSE _MK_ENUM_CONST(0x00000000)                                                       // RWC-V
#define SATA0_AHCI_HBA_CAP_BKDR_0_INTF_SPD_SUPP_SHIFT       _MK_SHIFT_CONST(20)                                                             // RWCVF
#define SATA0_AHCI_HBA_CAP_BKDR_0_INTF_SPD_SUPP_FIELD      (_MK_SHIFT_CONST(0xf) << SATA0_AHCI_HBA_CAP_BKDR_0_INTF_SPD_SUPP_SHIFT)
#define SATA0_AHCI_HBA_CAP_BKDR_0_INTF_SPD_SUPP_RANGE      23:20
#define SATA0_AHCI_HBA_CAP_BKDR_0_INTF_SPD_SUPP_WOFFSET    0
#define SATA0_AHCI_HBA_CAP_BKDR_0_INTF_SPD_SUPP_RSVD       _MK_ENUM_CONST(0x00000000)                                                       // RW--V
#define SATA0_AHCI_HBA_CAP_BKDR_0_INTF_SPD_SUPP_GEN1       _MK_ENUM_CONST(0x00000001)                                                       // RW--V
#define SATA0_AHCI_HBA_CAP_BKDR_0_INTF_SPD_SUPP_GEN1_2     _MK_ENUM_CONST(0x00000002)                                                       // RWC-V
#define SATA0_AHCI_HBA_CAP_BKDR_0_INTF_SPD_SUPP_GEN3       _MK_ENUM_CONST(0x00000003)                                                       // RW--V
#define SATA0_AHCI_HBA_CAP_BKDR_0_SUPP_CLO_SHIFT            _MK_SHIFT_CONST(24)                                                             // RWCVF
#define SATA0_AHCI_HBA_CAP_BKDR_0_SUPP_CLO_FIELD           (_MK_SHIFT_CONST(0x1) << SATA0_AHCI_HBA_CAP_BKDR_0_SUPP_CLO_SHIFT)
#define SATA0_AHCI_HBA_CAP_BKDR_0_SUPP_CLO_RANGE           24:24
#define SATA0_AHCI_HBA_CAP_BKDR_0_SUPP_CLO_WOFFSET         0
#define SATA0_AHCI_HBA_CAP_BKDR_0_SUPP_CLO_TRUE            _MK_ENUM_CONST(0x00000001)                                                       // RW--V
#define SATA0_AHCI_HBA_CAP_BKDR_0_SUPP_CLO_FALSE           _MK_ENUM_CONST(0x00000000)                                                       // RWC-V
#define SATA0_AHCI_HBA_CAP_BKDR_0_SAL_SHIFT                 _MK_SHIFT_CONST(25)                                                             // RWCVF
#define SATA0_AHCI_HBA_CAP_BKDR_0_SAL_FIELD                (_MK_SHIFT_CONST(0x1) << SATA0_AHCI_HBA_CAP_BKDR_0_SAL_SHIFT)
#define SATA0_AHCI_HBA_CAP_BKDR_0_SAL_RANGE                25:25
#define SATA0_AHCI_HBA_CAP_BKDR_0_SAL_WOFFSET              0
#define SATA0_AHCI_HBA_CAP_BKDR_0_SAL_TRUE                 _MK_ENUM_CONST(0x00000001)                                                       // RWC-V
#define SATA0_AHCI_HBA_CAP_BKDR_0_SAL_FALSE                _MK_ENUM_CONST(0x00000000)                                                       // RW--V
#define SATA0_AHCI_HBA_CAP_BKDR_0_SALP_SHIFT                _MK_SHIFT_CONST(26)                                                             // RWCVF
#define SATA0_AHCI_HBA_CAP_BKDR_0_SALP_FIELD               (_MK_SHIFT_CONST(0x1) << SATA0_AHCI_HBA_CAP_BKDR_0_SALP_SHIFT)
#define SATA0_AHCI_HBA_CAP_BKDR_0_SALP_RANGE               26:26
#define SATA0_AHCI_HBA_CAP_BKDR_0_SALP_WOFFSET             0
#define SATA0_AHCI_HBA_CAP_BKDR_0_SALP_TRUE                _MK_ENUM_CONST(0x00000001)                                                       // RWC-V
#define SATA0_AHCI_HBA_CAP_BKDR_0_SALP_FALSE               _MK_ENUM_CONST(0x00000000)                                                       // RW--V
#define SATA0_AHCI_HBA_CAP_BKDR_0_SUPP_STG_SPUP_SHIFT       _MK_SHIFT_CONST(27)                                                             // RWCVF
#define SATA0_AHCI_HBA_CAP_BKDR_0_SUPP_STG_SPUP_FIELD      (_MK_SHIFT_CONST(0x1) << SATA0_AHCI_HBA_CAP_BKDR_0_SUPP_STG_SPUP_SHIFT)
#define SATA0_AHCI_HBA_CAP_BKDR_0_SUPP_STG_SPUP_RANGE      27:27
#define SATA0_AHCI_HBA_CAP_BKDR_0_SUPP_STG_SPUP_WOFFSET    0
#define SATA0_AHCI_HBA_CAP_BKDR_0_SUPP_STG_SPUP_SET        _MK_ENUM_CONST(0x00000001)                                                       // RW--V
#define SATA0_AHCI_HBA_CAP_BKDR_0_SUPP_STG_SPUP_CLEAR      _MK_ENUM_CONST(0x00000000)                                                       // RWC-V
#define SATA0_AHCI_HBA_CAP_BKDR_0_SMPS_SHIFT                _MK_SHIFT_CONST(28)                                                             // RWCVF
#define SATA0_AHCI_HBA_CAP_BKDR_0_SMPS_FIELD               (_MK_SHIFT_CONST(0x1) << SATA0_AHCI_HBA_CAP_BKDR_0_SMPS_SHIFT)
#define SATA0_AHCI_HBA_CAP_BKDR_0_SMPS_RANGE               28:28
#define SATA0_AHCI_HBA_CAP_BKDR_0_SMPS_WOFFSET             0
#define SATA0_AHCI_HBA_CAP_BKDR_0_SMPS_TRUE                _MK_ENUM_CONST(0x00000001)                                                       // RW--V
#define SATA0_AHCI_HBA_CAP_BKDR_0_SMPS_FALSE               _MK_ENUM_CONST(0x00000000)                                                       // RWC-V
#define SATA0_AHCI_HBA_CAP_BKDR_0_SSNTF_SHIFT               _MK_SHIFT_CONST(29)                                                             // RWCVF
#define SATA0_AHCI_HBA_CAP_BKDR_0_SSNTF_FIELD              (_MK_SHIFT_CONST(0x1) << SATA0_AHCI_HBA_CAP_BKDR_0_SSNTF_SHIFT)
#define SATA0_AHCI_HBA_CAP_BKDR_0_SSNTF_RANGE              29:29
#define SATA0_AHCI_HBA_CAP_BKDR_0_SSNTF_WOFFSET            0
#define SATA0_AHCI_HBA_CAP_BKDR_0_SSNTF_TRUE               _MK_ENUM_CONST(0x00000001)                                                       // RWC-V
#define SATA0_AHCI_HBA_CAP_BKDR_0_SSNTF_FALSE              _MK_ENUM_CONST(0x00000000)                                                       // RW--V
#define SATA0_AHCI_HBA_CAP_BKDR_0_SNCQ_SHIFT                _MK_SHIFT_CONST(30)                                                             // RWCVF
#define SATA0_AHCI_HBA_CAP_BKDR_0_SNCQ_FIELD               (_MK_SHIFT_CONST(0x1) << SATA0_AHCI_HBA_CAP_BKDR_0_SNCQ_SHIFT)
#define SATA0_AHCI_HBA_CAP_BKDR_0_SNCQ_RANGE               30:30
#define SATA0_AHCI_HBA_CAP_BKDR_0_SNCQ_WOFFSET             0
#define SATA0_AHCI_HBA_CAP_BKDR_0_SNCQ_TRUE                _MK_ENUM_CONST(0x00000001)                                                       // RWC-V
#define SATA0_AHCI_HBA_CAP_BKDR_0_SNCQ_FALSE               _MK_ENUM_CONST(0x00000000)                                                       // RW--V
#define SATA0_AHCI_HBA_CAP_BKDR_0_S64A_SHIFT                _MK_SHIFT_CONST(31)                                                             // RWCVF
#define SATA0_AHCI_HBA_CAP_BKDR_0_S64A_FIELD               (_MK_SHIFT_CONST(0x1) << SATA0_AHCI_HBA_CAP_BKDR_0_S64A_SHIFT)
#define SATA0_AHCI_HBA_CAP_BKDR_0_S64A_RANGE               31:31
#define SATA0_AHCI_HBA_CAP_BKDR_0_S64A_WOFFSET             0
#define SATA0_AHCI_HBA_CAP_BKDR_0_S64A_TRUE                _MK_ENUM_CONST(0x00000001)                                                       // RWC-V
#define SATA0_AHCI_HBA_CAP_BKDR_0_S64A_FALSE               _MK_ENUM_CONST(0x00000000)                                                       // RW--V
// 
// 
// 
// .LABEL PUBLIC
// 
// .LABEL PRIVATE INT_REL
// .TITLE HBA_HOLD_GEN
// .FIELD T2P_FIFO_AVAIL
// This field is programmed with a variable water mark for generation of HOLD to drive depending on the depth of T2P fifo. This field indicates the number of lines of the FIFO and not the size in bytes/words.
// .FIELD PRD_SIZE
// This field indicates the minimum value of PRDBC for the last PRD cached below which Port should send a HOLD to drive.
// .FIELD SHARED_DFIFO_AVAIL
// This field is programmed with a variable water mark for generation of HOLD to drive depending on depth of shared DATA FIFO. This field indicates the number of lines of the FIFO and not the size in bytes/words.
// 
// 
// 31           24 23           16 15            8 7             0
// .-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-.
// |0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0| HBA_HOLD_GEN
// `-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-'
// 
#define SATA0_AHCI_HBA_HOLD_GEN_0                          0x00000304                                                                       // RW-4R
#define SATA0_AHCI_HBA_HOLD_GEN_0_SECURE                   0
#define SATA0_AHCI_HBA_HOLD_GEN_0_WORD_COUNT               1
#define SATA0_AHCI_HBA_HOLD_GEN_0_RESET_VAL                0x0
#define SATA0_AHCI_HBA_HOLD_GEN_0_RESET_MASK               0x0
#define SATA0_AHCI_HBA_HOLD_GEN_0_SW_DEFAULT_VAL           0x0
#define SATA0_AHCI_HBA_HOLD_GEN_0_SW_DEFAULT_MASK          0x0
#define SATA0_AHCI_HBA_HOLD_GEN_0_READ_MASK                0xffffffff
#define SATA0_AHCI_HBA_HOLD_GEN_0_WRITE_MASK               0xffffffff
#define SATA0_AHCI_HBA_HOLD_GEN_0_T2P_FIFO_AVAIL_SHIFT      _MK_SHIFT_CONST(0)                                                              // RWCVF
#define SATA0_AHCI_HBA_HOLD_GEN_0_T2P_FIFO_AVAIL_FIELD     (_MK_SHIFT_CONST(0xff) << SATA0_AHCI_HBA_HOLD_GEN_0_T2P_FIFO_AVAIL_SHIFT)
#define SATA0_AHCI_HBA_HOLD_GEN_0_T2P_FIFO_AVAIL_RANGE     7:0
#define SATA0_AHCI_HBA_HOLD_GEN_0_T2P_FIFO_AVAIL_WOFFSET   0
#define SATA0_AHCI_HBA_HOLD_GEN_0_T2P_FIFO_AVAIL_INIT      _MK_ENUM_CONST(0x00000026)                                                       // RWC-V
#define SATA0_AHCI_HBA_HOLD_GEN_0_T2P_FIFO_AVAIL_MAX       _MK_ENUM_CONST(0x0000002E)                                                       // RW--V
#define SATA0_AHCI_HBA_HOLD_GEN_0_T2P_FIFO_AVAIL__PROD_C_FPGA _MK_ENUM_CONST(0x0000003A)                                                       // RW--V
#define SATA0_AHCI_HBA_HOLD_GEN_0_PRD_SIZE_SHIFT            _MK_SHIFT_CONST(8)                                                              // RWCVF
#define SATA0_AHCI_HBA_HOLD_GEN_0_PRD_SIZE_FIELD           (_MK_SHIFT_CONST(0xffff) << SATA0_AHCI_HBA_HOLD_GEN_0_PRD_SIZE_SHIFT)
#define SATA0_AHCI_HBA_HOLD_GEN_0_PRD_SIZE_RANGE           23:8
#define SATA0_AHCI_HBA_HOLD_GEN_0_PRD_SIZE_WOFFSET         0
#define SATA0_AHCI_HBA_HOLD_GEN_0_PRD_SIZE_INIT            _MK_ENUM_CONST(0x00000800)                                                       // RWC-V
#define SATA0_AHCI_HBA_HOLD_GEN_0_SHARED_DFIFO_AVAIL_SHIFT  _MK_SHIFT_CONST(24)                                                             // RWCVF
#define SATA0_AHCI_HBA_HOLD_GEN_0_SHARED_DFIFO_AVAIL_FIELD (_MK_SHIFT_CONST(0xff) << SATA0_AHCI_HBA_HOLD_GEN_0_SHARED_DFIFO_AVAIL_SHIFT)
#define SATA0_AHCI_HBA_HOLD_GEN_0_SHARED_DFIFO_AVAIL_RANGE 31:24
#define SATA0_AHCI_HBA_HOLD_GEN_0_SHARED_DFIFO_AVAIL_WOFFSET 0
#define SATA0_AHCI_HBA_HOLD_GEN_0_SHARED_DFIFO_AVAIL_INIT  _MK_ENUM_CONST(0x00000019)                                                       // RWC-V
// 
// .LABEL PUBLIC
// 
// .LABEL PRIVATE INT_REL
// .TITLE HBA_CTL_0
// 
// .FIELD BKDR_PRDBC_UPDATE
// AHCI spec says that we need to update PRDBC before clearing PXCI for a non-native command. And optionally may update after each data FIS completion.
// 
// 31           24 23           16 15            8 7             0
// .-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-.
// |0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0| CYA Reg 0
// `-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-'
// 
#define SATA0_AHCI_HBA_CYA_0_0                             0x0000030C                                                                       // RW-4R
#define SATA0_AHCI_HBA_CYA_0_0_SECURE                      0
#define SATA0_AHCI_HBA_CYA_0_0_WORD_COUNT                  1
#define SATA0_AHCI_HBA_CYA_0_0_RESET_VAL                   0x0
#define SATA0_AHCI_HBA_CYA_0_0_RESET_MASK                  0x0
#define SATA0_AHCI_HBA_CYA_0_0_SW_DEFAULT_VAL              0x0
#define SATA0_AHCI_HBA_CYA_0_0_SW_DEFAULT_MASK             0x0
#define SATA0_AHCI_HBA_CYA_0_0_READ_MASK                   0xffff00ff
#define SATA0_AHCI_HBA_CYA_0_0_WRITE_MASK                  0xffff00ff
#define SATA0_AHCI_HBA_CYA_0_0_PORTX_OFS_IN_ATAPI_SHIFT     _MK_SHIFT_CONST(0)                                                              // RWW-F
#define SATA0_AHCI_HBA_CYA_0_0_PORTX_OFS_IN_ATAPI_FIELD    (_MK_SHIFT_CONST(0x1) << SATA0_AHCI_HBA_CYA_0_0_PORTX_OFS_IN_ATAPI_SHIFT)
#define SATA0_AHCI_HBA_CYA_0_0_PORTX_OFS_IN_ATAPI_RANGE    0:0
#define SATA0_AHCI_HBA_CYA_0_0_PORTX_OFS_IN_ATAPI_WOFFSET  0
#define SATA0_AHCI_HBA_CYA_0_0_PORTX_OFS_IN_ATAPI_DEFAULT  (_MK_MASK_CONST(0x00000000)
#define SATA0_AHCI_HBA_CYA_0_0_PORTX_OFS_IN_ATAPI_DEFAULT_MASK (_MK_MASK_CONST(0x1)
#define SATA0_AHCI_HBA_CYA_0_0_PORTX_OFS_IN_ATAPI_SW_DEFAULT (_MK_MASK_CONST(0x00000000)
#define SATA0_AHCI_HBA_CYA_0_0_PORTX_OFS_IN_ATAPI_SW_DEFAULT_MASK (_MK_MASK_CONST(0x1)
#define SATA0_AHCI_HBA_CYA_0_0_PORTX_OFS_IN_ATAPI_DISABLE  _MK_ENUM_CONST(0x00000000)                                                       // RWW-V
#define SATA0_AHCI_HBA_CYA_0_0_PORTX_OFS_IN_ATAPI_ENABLE   _MK_ENUM_CONST(0x00000001)                                                       // RW--V
#define SATA0_AHCI_HBA_CYA_0_0_PORTX_PRD_UNDERFLOW_IFS_ATAPI_SHIFT  _MK_SHIFT_CONST(1)                                                              // RWW-F
#define SATA0_AHCI_HBA_CYA_0_0_PORTX_PRD_UNDERFLOW_IFS_ATAPI_FIELD (_MK_SHIFT_CONST(0x1) << SATA0_AHCI_HBA_CYA_0_0_PORTX_PRD_UNDERFLOW_IFS_ATAPI_SHIFT)
#define SATA0_AHCI_HBA_CYA_0_0_PORTX_PRD_UNDERFLOW_IFS_ATAPI_RANGE 1:1
#define SATA0_AHCI_HBA_CYA_0_0_PORTX_PRD_UNDERFLOW_IFS_ATAPI_WOFFSET 0
#define SATA0_AHCI_HBA_CYA_0_0_PORTX_PRD_UNDERFLOW_IFS_ATAPI_DEFAULT (_MK_MASK_CONST(0x00000000)
#define SATA0_AHCI_HBA_CYA_0_0_PORTX_PRD_UNDERFLOW_IFS_ATAPI_DEFAULT_MASK (_MK_MASK_CONST(0x1)
#define SATA0_AHCI_HBA_CYA_0_0_PORTX_PRD_UNDERFLOW_IFS_ATAPI_SW_DEFAULT (_MK_MASK_CONST(0x00000000)
#define SATA0_AHCI_HBA_CYA_0_0_PORTX_PRD_UNDERFLOW_IFS_ATAPI_SW_DEFAULT_MASK (_MK_MASK_CONST(0x1)
#define SATA0_AHCI_HBA_CYA_0_0_PORTX_PRD_UNDERFLOW_IFS_ATAPI_DISABLE _MK_ENUM_CONST(0x00000000)                                                       // RWW-V
#define SATA0_AHCI_HBA_CYA_0_0_PORTX_PRD_UNDERFLOW_IFS_ATAPI_ENABLE _MK_ENUM_CONST(0x00000001)                                                       // RW--V
#define SATA0_AHCI_HBA_CYA_0_0_PORTX_NONNCQ_TX_RX_UNDERFLOW_SHIFT  _MK_SHIFT_CONST(2)                                                              // RWW-F
#define SATA0_AHCI_HBA_CYA_0_0_PORTX_NONNCQ_TX_RX_UNDERFLOW_FIELD (_MK_SHIFT_CONST(0x1) << SATA0_AHCI_HBA_CYA_0_0_PORTX_NONNCQ_TX_RX_UNDERFLOW_SHIFT)
#define SATA0_AHCI_HBA_CYA_0_0_PORTX_NONNCQ_TX_RX_UNDERFLOW_RANGE 2:2
#define SATA0_AHCI_HBA_CYA_0_0_PORTX_NONNCQ_TX_RX_UNDERFLOW_WOFFSET 0
#define SATA0_AHCI_HBA_CYA_0_0_PORTX_NONNCQ_TX_RX_UNDERFLOW_DEFAULT (_MK_MASK_CONST(0x00000001)
#define SATA0_AHCI_HBA_CYA_0_0_PORTX_NONNCQ_TX_RX_UNDERFLOW_DEFAULT_MASK (_MK_MASK_CONST(0x1)
#define SATA0_AHCI_HBA_CYA_0_0_PORTX_NONNCQ_TX_RX_UNDERFLOW_SW_DEFAULT (_MK_MASK_CONST(0x00000001)
#define SATA0_AHCI_HBA_CYA_0_0_PORTX_NONNCQ_TX_RX_UNDERFLOW_SW_DEFAULT_MASK (_MK_MASK_CONST(0x1)
#define SATA0_AHCI_HBA_CYA_0_0_PORTX_NONNCQ_TX_RX_UNDERFLOW_DISABLE _MK_ENUM_CONST(0x00000000)                                                       // RW--V
#define SATA0_AHCI_HBA_CYA_0_0_PORTX_NONNCQ_TX_RX_UNDERFLOW_ENABLE _MK_ENUM_CONST(0x00000001)                                                       // RWW-V
#define SATA0_AHCI_HBA_CYA_0_0_BKDR_PRDBC_UPDATE_SHIFT      _MK_SHIFT_CONST(3)                                                              // RWWVF
#define SATA0_AHCI_HBA_CYA_0_0_BKDR_PRDBC_UPDATE_FIELD     (_MK_SHIFT_CONST(0x1) << SATA0_AHCI_HBA_CYA_0_0_BKDR_PRDBC_UPDATE_SHIFT)
#define SATA0_AHCI_HBA_CYA_0_0_BKDR_PRDBC_UPDATE_RANGE     3:3
#define SATA0_AHCI_HBA_CYA_0_0_BKDR_PRDBC_UPDATE_WOFFSET   0
#define SATA0_AHCI_HBA_CYA_0_0_BKDR_PRDBC_UPDATE_DEFAULT   (_MK_MASK_CONST(0x00000000)
#define SATA0_AHCI_HBA_CYA_0_0_BKDR_PRDBC_UPDATE_DEFAULT_MASK (_MK_MASK_CONST(0x1)
#define SATA0_AHCI_HBA_CYA_0_0_BKDR_PRDBC_UPDATE_SW_DEFAULT (_MK_MASK_CONST(0x00000000)
#define SATA0_AHCI_HBA_CYA_0_0_BKDR_PRDBC_UPDATE_SW_DEFAULT_MASK (_MK_MASK_CONST(0x1)
#define SATA0_AHCI_HBA_CYA_0_0_BKDR_PRDBC_UPDATE_AT_EACH_DATA_FIS _MK_ENUM_CONST(0x00000001)                                                       // RW--V
#define SATA0_AHCI_HBA_CYA_0_0_BKDR_PRDBC_UPDATE_AT_REG_FIS _MK_ENUM_CONST(0x00000000)                                                       // RWW-V
#define SATA0_AHCI_HBA_CYA_0_0_DIS_CCC_TIMEOUT_INT_AT_ZERO_OUTSTD_CMD_SHIFT  _MK_SHIFT_CONST(4)                                                              // RWWVF
#define SATA0_AHCI_HBA_CYA_0_0_DIS_CCC_TIMEOUT_INT_AT_ZERO_OUTSTD_CMD_FIELD (_MK_SHIFT_CONST(0x1) << SATA0_AHCI_HBA_CYA_0_0_DIS_CCC_TIMEOUT_INT_AT_ZERO_OUTSTD_CMD_SHIFT)
#define SATA0_AHCI_HBA_CYA_0_0_DIS_CCC_TIMEOUT_INT_AT_ZERO_OUTSTD_CMD_RANGE 4:4
#define SATA0_AHCI_HBA_CYA_0_0_DIS_CCC_TIMEOUT_INT_AT_ZERO_OUTSTD_CMD_WOFFSET 0
#define SATA0_AHCI_HBA_CYA_0_0_DIS_CCC_TIMEOUT_INT_AT_ZERO_OUTSTD_CMD_DEFAULT (_MK_MASK_CONST(0x00000001)
#define SATA0_AHCI_HBA_CYA_0_0_DIS_CCC_TIMEOUT_INT_AT_ZERO_OUTSTD_CMD_DEFAULT_MASK (_MK_MASK_CONST(0x1)
#define SATA0_AHCI_HBA_CYA_0_0_DIS_CCC_TIMEOUT_INT_AT_ZERO_OUTSTD_CMD_SW_DEFAULT (_MK_MASK_CONST(0x00000001)
#define SATA0_AHCI_HBA_CYA_0_0_DIS_CCC_TIMEOUT_INT_AT_ZERO_OUTSTD_CMD_SW_DEFAULT_MASK (_MK_MASK_CONST(0x1)
#define SATA0_AHCI_HBA_CYA_0_0_DIS_CCC_TIMEOUT_INT_AT_ZERO_OUTSTD_CMD_SET _MK_ENUM_CONST(0x00000001)                                                       // RWW-V
#define SATA0_AHCI_HBA_CYA_0_0_DIS_CCC_TIMEOUT_INT_AT_ZERO_OUTSTD_CMD_CLEAR _MK_ENUM_CONST(0x00000000)                                                       // RW--V
#define SATA0_AHCI_HBA_CYA_0_0_MPIS_SET_AT_ACCEL_SHIFT      _MK_SHIFT_CONST(5)                                                              // RWWVF
#define SATA0_AHCI_HBA_CYA_0_0_MPIS_SET_AT_ACCEL_FIELD     (_MK_SHIFT_CONST(0x1) << SATA0_AHCI_HBA_CYA_0_0_MPIS_SET_AT_ACCEL_SHIFT)
#define SATA0_AHCI_HBA_CYA_0_0_MPIS_SET_AT_ACCEL_RANGE     5:5
#define SATA0_AHCI_HBA_CYA_0_0_MPIS_SET_AT_ACCEL_WOFFSET   0
#define SATA0_AHCI_HBA_CYA_0_0_MPIS_SET_AT_ACCEL_DEFAULT   (_MK_MASK_CONST(0x00000000)
#define SATA0_AHCI_HBA_CYA_0_0_MPIS_SET_AT_ACCEL_DEFAULT_MASK (_MK_MASK_CONST(0x1)
#define SATA0_AHCI_HBA_CYA_0_0_MPIS_SET_AT_ACCEL_SW_DEFAULT (_MK_MASK_CONST(0x00000000)
#define SATA0_AHCI_HBA_CYA_0_0_MPIS_SET_AT_ACCEL_SW_DEFAULT_MASK (_MK_MASK_CONST(0x1)
#define SATA0_AHCI_HBA_CYA_0_0_MPIS_SET_AT_ACCEL_ENABLE    _MK_ENUM_CONST(0x00000001)                                                       // RW--V
#define SATA0_AHCI_HBA_CYA_0_0_MPIS_SET_AT_ACCEL_DISABLE   _MK_ENUM_CONST(0x00000000)                                                       // RWW-V
#define SATA0_AHCI_HBA_CYA_0_0_NO_DHRS_AT_UNLOAD_SHIFT      _MK_SHIFT_CONST(6)                                                              // RWWVF
#define SATA0_AHCI_HBA_CYA_0_0_NO_DHRS_AT_UNLOAD_FIELD     (_MK_SHIFT_CONST(0x1) << SATA0_AHCI_HBA_CYA_0_0_NO_DHRS_AT_UNLOAD_SHIFT)
#define SATA0_AHCI_HBA_CYA_0_0_NO_DHRS_AT_UNLOAD_RANGE     6:6
#define SATA0_AHCI_HBA_CYA_0_0_NO_DHRS_AT_UNLOAD_WOFFSET   0
#define SATA0_AHCI_HBA_CYA_0_0_NO_DHRS_AT_UNLOAD_DEFAULT   (_MK_MASK_CONST(0x00000000)
#define SATA0_AHCI_HBA_CYA_0_0_NO_DHRS_AT_UNLOAD_DEFAULT_MASK (_MK_MASK_CONST(0x1)
#define SATA0_AHCI_HBA_CYA_0_0_NO_DHRS_AT_UNLOAD_SW_DEFAULT (_MK_MASK_CONST(0x00000000)
#define SATA0_AHCI_HBA_CYA_0_0_NO_DHRS_AT_UNLOAD_SW_DEFAULT_MASK (_MK_MASK_CONST(0x1)
#define SATA0_AHCI_HBA_CYA_0_0_NO_DHRS_AT_UNLOAD_ENABLE    _MK_ENUM_CONST(0x00000001)                                                       // RW--V
#define SATA0_AHCI_HBA_CYA_0_0_NO_DHRS_AT_UNLOAD_DISABLE   _MK_ENUM_CONST(0x00000000)                                                       // RWW-V
#define SATA0_AHCI_HBA_CYA_0_0_ACCEL_WAIT_FOR_BSY0_SHIFT    _MK_SHIFT_CONST(7)                                                              // RWWVF
#define SATA0_AHCI_HBA_CYA_0_0_ACCEL_WAIT_FOR_BSY0_FIELD   (_MK_SHIFT_CONST(0x1) << SATA0_AHCI_HBA_CYA_0_0_ACCEL_WAIT_FOR_BSY0_SHIFT)
#define SATA0_AHCI_HBA_CYA_0_0_ACCEL_WAIT_FOR_BSY0_RANGE   7:7
#define SATA0_AHCI_HBA_CYA_0_0_ACCEL_WAIT_FOR_BSY0_WOFFSET 0
#define SATA0_AHCI_HBA_CYA_0_0_ACCEL_WAIT_FOR_BSY0_DEFAULT (_MK_MASK_CONST(0x00000000)
#define SATA0_AHCI_HBA_CYA_0_0_ACCEL_WAIT_FOR_BSY0_DEFAULT_MASK (_MK_MASK_CONST(0x1)
#define SATA0_AHCI_HBA_CYA_0_0_ACCEL_WAIT_FOR_BSY0_SW_DEFAULT (_MK_MASK_CONST(0x00000000)
#define SATA0_AHCI_HBA_CYA_0_0_ACCEL_WAIT_FOR_BSY0_SW_DEFAULT_MASK (_MK_MASK_CONST(0x1)
#define SATA0_AHCI_HBA_CYA_0_0_ACCEL_WAIT_FOR_BSY0_ENABLE  _MK_ENUM_CONST(0x00000001)                                                       // RW--V
#define SATA0_AHCI_HBA_CYA_0_0_ACCEL_WAIT_FOR_BSY0_DISABLE _MK_ENUM_CONST(0x00000000)                                                       // RWW-V
#define SATA0_AHCI_HBA_CYA_0_0_HBFS_ON_BME_RESET_WHILE_ACTIVE_SHIFT  _MK_SHIFT_CONST(16)                                                             // RWW-F
#define SATA0_AHCI_HBA_CYA_0_0_HBFS_ON_BME_RESET_WHILE_ACTIVE_FIELD (_MK_SHIFT_CONST(0x1) << SATA0_AHCI_HBA_CYA_0_0_HBFS_ON_BME_RESET_WHILE_ACTIVE_SHIFT)
#define SATA0_AHCI_HBA_CYA_0_0_HBFS_ON_BME_RESET_WHILE_ACTIVE_RANGE 16:16
#define SATA0_AHCI_HBA_CYA_0_0_HBFS_ON_BME_RESET_WHILE_ACTIVE_WOFFSET 0
#define SATA0_AHCI_HBA_CYA_0_0_HBFS_ON_BME_RESET_WHILE_ACTIVE_DEFAULT (_MK_MASK_CONST(0x00000001)
#define SATA0_AHCI_HBA_CYA_0_0_HBFS_ON_BME_RESET_WHILE_ACTIVE_DEFAULT_MASK (_MK_MASK_CONST(0x1)
#define SATA0_AHCI_HBA_CYA_0_0_HBFS_ON_BME_RESET_WHILE_ACTIVE_SW_DEFAULT (_MK_MASK_CONST(0x00000001)
#define SATA0_AHCI_HBA_CYA_0_0_HBFS_ON_BME_RESET_WHILE_ACTIVE_SW_DEFAULT_MASK (_MK_MASK_CONST(0x1)
#define SATA0_AHCI_HBA_CYA_0_0_HBFS_ON_PRD_ADR_EXCEED_40B_SHIFT  _MK_SHIFT_CONST(17)                                                             // RWW-F
#define SATA0_AHCI_HBA_CYA_0_0_HBFS_ON_PRD_ADR_EXCEED_40B_FIELD (_MK_SHIFT_CONST(0x1) << SATA0_AHCI_HBA_CYA_0_0_HBFS_ON_PRD_ADR_EXCEED_40B_SHIFT)
#define SATA0_AHCI_HBA_CYA_0_0_HBFS_ON_PRD_ADR_EXCEED_40B_RANGE 17:17
#define SATA0_AHCI_HBA_CYA_0_0_HBFS_ON_PRD_ADR_EXCEED_40B_WOFFSET 0
#define SATA0_AHCI_HBA_CYA_0_0_HBFS_ON_PRD_ADR_EXCEED_40B_DEFAULT (_MK_MASK_CONST(0x00000001)
#define SATA0_AHCI_HBA_CYA_0_0_HBFS_ON_PRD_ADR_EXCEED_40B_DEFAULT_MASK (_MK_MASK_CONST(0x1)
#define SATA0_AHCI_HBA_CYA_0_0_HBFS_ON_PRD_ADR_EXCEED_40B_SW_DEFAULT (_MK_MASK_CONST(0x00000001)
#define SATA0_AHCI_HBA_CYA_0_0_HBFS_ON_PRD_ADR_EXCEED_40B_SW_DEFAULT_MASK (_MK_MASK_CONST(0x1)
#define SATA0_AHCI_HBA_CYA_0_0_HBFS_ON_PRD_ADR_EXCEED_40B_INIT _MK_ENUM_CONST(0x00000001)                                                       // RWW-V
#define SATA0_AHCI_HBA_CYA_0_0_RST_AE_ON_HR_SHIFT           _MK_SHIFT_CONST(18)                                                             // RWCVF
#define SATA0_AHCI_HBA_CYA_0_0_RST_AE_ON_HR_FIELD          (_MK_SHIFT_CONST(0x1) << SATA0_AHCI_HBA_CYA_0_0_RST_AE_ON_HR_SHIFT)
#define SATA0_AHCI_HBA_CYA_0_0_RST_AE_ON_HR_RANGE          18:18
#define SATA0_AHCI_HBA_CYA_0_0_RST_AE_ON_HR_WOFFSET        0
#define SATA0_AHCI_HBA_CYA_0_0_RST_AE_WITHOUT_COMRESET_SHIFT  _MK_SHIFT_CONST(19)                                                             // RWC-F
#define SATA0_AHCI_HBA_CYA_0_0_RST_AE_WITHOUT_COMRESET_FIELD (_MK_SHIFT_CONST(0x1) << SATA0_AHCI_HBA_CYA_0_0_RST_AE_WITHOUT_COMRESET_SHIFT)
#define SATA0_AHCI_HBA_CYA_0_0_RST_AE_WITHOUT_COMRESET_RANGE 19:19
#define SATA0_AHCI_HBA_CYA_0_0_RST_AE_WITHOUT_COMRESET_WOFFSET 0
#define SATA0_AHCI_HBA_CYA_0_0_ACCEL_SYNC_ESC_TIMEOUT_SHIFT  _MK_SHIFT_CONST(20)                                                             // RWWVF
#define SATA0_AHCI_HBA_CYA_0_0_ACCEL_SYNC_ESC_TIMEOUT_FIELD (_MK_SHIFT_CONST(0xf) << SATA0_AHCI_HBA_CYA_0_0_ACCEL_SYNC_ESC_TIMEOUT_SHIFT)
#define SATA0_AHCI_HBA_CYA_0_0_ACCEL_SYNC_ESC_TIMEOUT_RANGE 23:20
#define SATA0_AHCI_HBA_CYA_0_0_ACCEL_SYNC_ESC_TIMEOUT_WOFFSET 0
#define SATA0_AHCI_HBA_CYA_0_0_ACCEL_SYNC_ESC_TIMEOUT_DEFAULT (_MK_MASK_CONST(0x00000000)
#define SATA0_AHCI_HBA_CYA_0_0_ACCEL_SYNC_ESC_TIMEOUT_DEFAULT_MASK (_MK_MASK_CONST(0xf)
#define SATA0_AHCI_HBA_CYA_0_0_ACCEL_SYNC_ESC_TIMEOUT_SW_DEFAULT (_MK_MASK_CONST(0x00000000)
#define SATA0_AHCI_HBA_CYA_0_0_ACCEL_SYNC_ESC_TIMEOUT_SW_DEFAULT_MASK (_MK_MASK_CONST(0xf)
#define SATA0_AHCI_HBA_CYA_0_0_RSVD_24_SHIFT                _MK_SHIFT_CONST(24)                                                             // RWC-F
#define SATA0_AHCI_HBA_CYA_0_0_RSVD_24_FIELD               (_MK_SHIFT_CONST(0x1) << SATA0_AHCI_HBA_CYA_0_0_RSVD_24_SHIFT)
#define SATA0_AHCI_HBA_CYA_0_0_RSVD_24_RANGE               24:24
#define SATA0_AHCI_HBA_CYA_0_0_RSVD_24_WOFFSET             0
#define SATA0_AHCI_HBA_CYA_0_0_RSVD_24_ZERO                _MK_ENUM_CONST(0x00000000)                                                       // RWC-V
#define SATA0_AHCI_HBA_CYA_0_0_SUD_OLD_LOGIC_SHIFT          _MK_SHIFT_CONST(25)                                                             // RWC-F
#define SATA0_AHCI_HBA_CYA_0_0_SUD_OLD_LOGIC_FIELD         (_MK_SHIFT_CONST(0x1) << SATA0_AHCI_HBA_CYA_0_0_SUD_OLD_LOGIC_SHIFT)
#define SATA0_AHCI_HBA_CYA_0_0_SUD_OLD_LOGIC_RANGE         25:25
#define SATA0_AHCI_HBA_CYA_0_0_SUD_OLD_LOGIC_WOFFSET       0
#define SATA0_AHCI_HBA_CYA_0_0_SUD_OLD_LOGIC_TRUE          _MK_ENUM_CONST(0x00000001)                                                       // RW--V
#define SATA0_AHCI_HBA_CYA_0_0_SUD_OLD_LOGIC_FALSE         _MK_ENUM_CONST(0x00000000)                                                       // RWC-V
#define SATA0_AHCI_HBA_CYA_0_0_PSM2LL_DENY_PMREQ_SHIFT      _MK_SHIFT_CONST(26)                                                             // RWW-F
#define SATA0_AHCI_HBA_CYA_0_0_PSM2LL_DENY_PMREQ_FIELD     (_MK_SHIFT_CONST(0x1) << SATA0_AHCI_HBA_CYA_0_0_PSM2LL_DENY_PMREQ_SHIFT)
#define SATA0_AHCI_HBA_CYA_0_0_PSM2LL_DENY_PMREQ_RANGE     26:26
#define SATA0_AHCI_HBA_CYA_0_0_PSM2LL_DENY_PMREQ_WOFFSET   0
#define SATA0_AHCI_HBA_CYA_0_0_PSM2LL_DENY_PMREQ_DEFAULT   (_MK_MASK_CONST(0x00000001)
#define SATA0_AHCI_HBA_CYA_0_0_PSM2LL_DENY_PMREQ_DEFAULT_MASK (_MK_MASK_CONST(0x1)
#define SATA0_AHCI_HBA_CYA_0_0_PSM2LL_DENY_PMREQ_SW_DEFAULT (_MK_MASK_CONST(0x00000001)
#define SATA0_AHCI_HBA_CYA_0_0_PSM2LL_DENY_PMREQ_SW_DEFAULT_MASK (_MK_MASK_CONST(0x1)
#define SATA0_AHCI_HBA_CYA_0_0_PSM2LL_DENY_PMREQ_TRUE      _MK_ENUM_CONST(0x00000001)                                                       // RWW-V
#define SATA0_AHCI_HBA_CYA_0_0_PSM2LL_DENY_PMREQ_FALSE     _MK_ENUM_CONST(0x00000000)                                                       // RW--V
#define SATA0_AHCI_HBA_CYA_0_0_TRANSPRT_IGNORE_DMAT_SHIFT   _MK_SHIFT_CONST(27)                                                             // RWW-F
#define SATA0_AHCI_HBA_CYA_0_0_TRANSPRT_IGNORE_DMAT_FIELD  (_MK_SHIFT_CONST(0x1) << SATA0_AHCI_HBA_CYA_0_0_TRANSPRT_IGNORE_DMAT_SHIFT)
#define SATA0_AHCI_HBA_CYA_0_0_TRANSPRT_IGNORE_DMAT_RANGE  27:27
#define SATA0_AHCI_HBA_CYA_0_0_TRANSPRT_IGNORE_DMAT_WOFFSET 0
#define SATA0_AHCI_HBA_CYA_0_0_TRANSPRT_IGNORE_DMAT_DEFAULT (_MK_MASK_CONST(0x00000001)
#define SATA0_AHCI_HBA_CYA_0_0_TRANSPRT_IGNORE_DMAT_DEFAULT_MASK (_MK_MASK_CONST(0x1)
#define SATA0_AHCI_HBA_CYA_0_0_TRANSPRT_IGNORE_DMAT_SW_DEFAULT (_MK_MASK_CONST(0x00000001)
#define SATA0_AHCI_HBA_CYA_0_0_TRANSPRT_IGNORE_DMAT_SW_DEFAULT_MASK (_MK_MASK_CONST(0x1)
#define SATA0_AHCI_HBA_CYA_0_0_TRANSPRT_IGNORE_DMAT_TRUE   _MK_ENUM_CONST(0x00000001)                                                       // RWW-V
#define SATA0_AHCI_HBA_CYA_0_0_TRANSPRT_IGNORE_DMAT_FALSE  _MK_ENUM_CONST(0x00000000)                                                       // RW--V
#define SATA0_AHCI_HBA_CYA_0_0_BKDR_VS_MINOR_9_8_SHIFT      _MK_SHIFT_CONST(28)                                                             // RWW-F
#define SATA0_AHCI_HBA_CYA_0_0_BKDR_VS_MINOR_9_8_FIELD     (_MK_SHIFT_CONST(0x3) << SATA0_AHCI_HBA_CYA_0_0_BKDR_VS_MINOR_9_8_SHIFT)
#define SATA0_AHCI_HBA_CYA_0_0_BKDR_VS_MINOR_9_8_RANGE     29:28
#define SATA0_AHCI_HBA_CYA_0_0_BKDR_VS_MINOR_9_8_WOFFSET   0
#define SATA0_AHCI_HBA_CYA_0_0_BKDR_VS_MINOR_9_8_DEFAULT   (_MK_MASK_CONST(0x00000003)
#define SATA0_AHCI_HBA_CYA_0_0_BKDR_VS_MINOR_9_8_DEFAULT_MASK (_MK_MASK_CONST(0x3)
#define SATA0_AHCI_HBA_CYA_0_0_BKDR_VS_MINOR_9_8_SW_DEFAULT (_MK_MASK_CONST(0x00000003)
#define SATA0_AHCI_HBA_CYA_0_0_BKDR_VS_MINOR_9_8_SW_DEFAULT_MASK (_MK_MASK_CONST(0x3)
#define SATA0_AHCI_HBA_CYA_0_0_USE_AHCI_MODE_IN_FIS_PROCESS_SHIFT  _MK_SHIFT_CONST(30)                                                             // RWW-F
#define SATA0_AHCI_HBA_CYA_0_0_USE_AHCI_MODE_IN_FIS_PROCESS_FIELD (_MK_SHIFT_CONST(0x1) << SATA0_AHCI_HBA_CYA_0_0_USE_AHCI_MODE_IN_FIS_PROCESS_SHIFT)
#define SATA0_AHCI_HBA_CYA_0_0_USE_AHCI_MODE_IN_FIS_PROCESS_RANGE 30:30
#define SATA0_AHCI_HBA_CYA_0_0_USE_AHCI_MODE_IN_FIS_PROCESS_WOFFSET 0
#define SATA0_AHCI_HBA_CYA_0_0_USE_AHCI_MODE_IN_FIS_PROCESS_DEFAULT (_MK_MASK_CONST(0x00000001)
#define SATA0_AHCI_HBA_CYA_0_0_USE_AHCI_MODE_IN_FIS_PROCESS_DEFAULT_MASK (_MK_MASK_CONST(0x1)
#define SATA0_AHCI_HBA_CYA_0_0_USE_AHCI_MODE_IN_FIS_PROCESS_SW_DEFAULT (_MK_MASK_CONST(0x00000001)
#define SATA0_AHCI_HBA_CYA_0_0_USE_AHCI_MODE_IN_FIS_PROCESS_SW_DEFAULT_MASK (_MK_MASK_CONST(0x1)
#define SATA0_AHCI_HBA_CYA_0_0_USE_AHCI_MODE_IN_FIS_PROCESS_YES _MK_ENUM_CONST(0x00000001)                                                       // RWW-V
#define SATA0_AHCI_HBA_CYA_0_0_USE_AHCI_MODE_IN_FIS_PROCESS_NO _MK_ENUM_CONST(0x00000000)                                                       // RW--V
#define SATA0_AHCI_HBA_CYA_0_0_USE_PXCMD_ICC_IF_LINK_IN_IDLE_SHIFT  _MK_SHIFT_CONST(31)                                                             // RWW-F
#define SATA0_AHCI_HBA_CYA_0_0_USE_PXCMD_ICC_IF_LINK_IN_IDLE_FIELD (_MK_SHIFT_CONST(0x1) << SATA0_AHCI_HBA_CYA_0_0_USE_PXCMD_ICC_IF_LINK_IN_IDLE_SHIFT)
#define SATA0_AHCI_HBA_CYA_0_0_USE_PXCMD_ICC_IF_LINK_IN_IDLE_RANGE 31:31
#define SATA0_AHCI_HBA_CYA_0_0_USE_PXCMD_ICC_IF_LINK_IN_IDLE_WOFFSET 0
#define SATA0_AHCI_HBA_CYA_0_0_USE_PXCMD_ICC_IF_LINK_IN_IDLE_DEFAULT (_MK_MASK_CONST(0x00000000)
#define SATA0_AHCI_HBA_CYA_0_0_USE_PXCMD_ICC_IF_LINK_IN_IDLE_DEFAULT_MASK (_MK_MASK_CONST(0x1)
#define SATA0_AHCI_HBA_CYA_0_0_USE_PXCMD_ICC_IF_LINK_IN_IDLE_SW_DEFAULT (_MK_MASK_CONST(0x00000000)
#define SATA0_AHCI_HBA_CYA_0_0_USE_PXCMD_ICC_IF_LINK_IN_IDLE_SW_DEFAULT_MASK (_MK_MASK_CONST(0x1)
#define SATA0_AHCI_HBA_CYA_0_0_USE_PXCMD_ICC_IF_LINK_IN_IDLE_YES _MK_ENUM_CONST(0x00000001)                                                       // RW--V
#define SATA0_AHCI_HBA_CYA_0_0_USE_PXCMD_ICC_IF_LINK_IN_IDLE_NO _MK_ENUM_CONST(0x00000000)                                                       // RWW-V
// .define T_SATA0_AHCI_HBA_CTL_0                                            0x0000030C /* RW-4R */
// 
// 
// .LABEL PUBLIC
// 
// 
// 
// 
// 
// 
// .LABEL PRIVATE INT_REL
// .TITLE AHCI_HBA_BIST_OVERRIDE_CTL
// This register has overrides for various bist modes avialble according to spec
// 31           24 23           16 15            8 7             0
// .-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-.
// |0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0| SPARE Reg B8
// `-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-'
// 
#define SATA0_AHCI_HBA_BIST_OVERRIDE_CTL_0                 0x00000318                                                                       // RWW4R
#define SATA0_AHCI_HBA_BIST_OVERRIDE_CTL_0_SECURE          0
#define SATA0_AHCI_HBA_BIST_OVERRIDE_CTL_0_WORD_COUNT      1
#define SATA0_AHCI_HBA_BIST_OVERRIDE_CTL_0_RESET_VAL       0x0
#define SATA0_AHCI_HBA_BIST_OVERRIDE_CTL_0_RESET_MASK      0x0
#define SATA0_AHCI_HBA_BIST_OVERRIDE_CTL_0_SW_DEFAULT_VAL  0x0
#define SATA0_AHCI_HBA_BIST_OVERRIDE_CTL_0_SW_DEFAULT_MASK 0x0
#define SATA0_AHCI_HBA_BIST_OVERRIDE_CTL_0_READ_MASK       0xffffffff
#define SATA0_AHCI_HBA_BIST_OVERRIDE_CTL_0_WRITE_MASK      0xffffffff
#define SATA0_AHCI_HBA_BIST_OVERRIDE_CTL_0_CLR_SHIFT        _MK_SHIFT_CONST(0)                                                              // RWWVF
#define SATA0_AHCI_HBA_BIST_OVERRIDE_CTL_0_CLR_FIELD       (_MK_SHIFT_CONST(0x1) << SATA0_AHCI_HBA_BIST_OVERRIDE_CTL_0_CLR_SHIFT)
#define SATA0_AHCI_HBA_BIST_OVERRIDE_CTL_0_CLR_RANGE       0:0
#define SATA0_AHCI_HBA_BIST_OVERRIDE_CTL_0_CLR_WOFFSET     0
#define SATA0_AHCI_HBA_BIST_OVERRIDE_CTL_0_CLR_DEFAULT     (_MK_MASK_CONST(0x00000000)
#define SATA0_AHCI_HBA_BIST_OVERRIDE_CTL_0_CLR_DEFAULT_MASK (_MK_MASK_CONST(0x1)
#define SATA0_AHCI_HBA_BIST_OVERRIDE_CTL_0_CLR_SW_DEFAULT  (_MK_MASK_CONST(0x00000000)
#define SATA0_AHCI_HBA_BIST_OVERRIDE_CTL_0_CLR_SW_DEFAULT_MASK (_MK_MASK_CONST(0x1)
#define SATA0_AHCI_HBA_BIST_OVERRIDE_CTL_0_A_SHIFT          _MK_SHIFT_CONST(1)                                                              // RWWVF
#define SATA0_AHCI_HBA_BIST_OVERRIDE_CTL_0_A_FIELD         (_MK_SHIFT_CONST(0x1) << SATA0_AHCI_HBA_BIST_OVERRIDE_CTL_0_A_SHIFT)
#define SATA0_AHCI_HBA_BIST_OVERRIDE_CTL_0_A_RANGE         1:1
#define SATA0_AHCI_HBA_BIST_OVERRIDE_CTL_0_A_WOFFSET       0
#define SATA0_AHCI_HBA_BIST_OVERRIDE_CTL_0_A_DEFAULT       (_MK_MASK_CONST(0x00000000)
#define SATA0_AHCI_HBA_BIST_OVERRIDE_CTL_0_A_DEFAULT_MASK  (_MK_MASK_CONST(0x1)
#define SATA0_AHCI_HBA_BIST_OVERRIDE_CTL_0_A_SW_DEFAULT    (_MK_MASK_CONST(0x00000000)
#define SATA0_AHCI_HBA_BIST_OVERRIDE_CTL_0_A_SW_DEFAULT_MASK (_MK_MASK_CONST(0x1)
#define SATA0_AHCI_HBA_BIST_OVERRIDE_CTL_0_T_SHIFT          _MK_SHIFT_CONST(2)                                                              // RWWVF
#define SATA0_AHCI_HBA_BIST_OVERRIDE_CTL_0_T_FIELD         (_MK_SHIFT_CONST(0x1) << SATA0_AHCI_HBA_BIST_OVERRIDE_CTL_0_T_SHIFT)
#define SATA0_AHCI_HBA_BIST_OVERRIDE_CTL_0_T_RANGE         2:2
#define SATA0_AHCI_HBA_BIST_OVERRIDE_CTL_0_T_WOFFSET       0
#define SATA0_AHCI_HBA_BIST_OVERRIDE_CTL_0_T_DEFAULT       (_MK_MASK_CONST(0x00000000)
#define SATA0_AHCI_HBA_BIST_OVERRIDE_CTL_0_T_DEFAULT_MASK  (_MK_MASK_CONST(0x1)
#define SATA0_AHCI_HBA_BIST_OVERRIDE_CTL_0_T_SW_DEFAULT    (_MK_MASK_CONST(0x00000000)
#define SATA0_AHCI_HBA_BIST_OVERRIDE_CTL_0_T_SW_DEFAULT_MASK (_MK_MASK_CONST(0x1)
#define SATA0_AHCI_HBA_BIST_OVERRIDE_CTL_0_S_SHIFT          _MK_SHIFT_CONST(3)                                                              // RWWVF
#define SATA0_AHCI_HBA_BIST_OVERRIDE_CTL_0_S_FIELD         (_MK_SHIFT_CONST(0x1) << SATA0_AHCI_HBA_BIST_OVERRIDE_CTL_0_S_SHIFT)
#define SATA0_AHCI_HBA_BIST_OVERRIDE_CTL_0_S_RANGE         3:3
#define SATA0_AHCI_HBA_BIST_OVERRIDE_CTL_0_S_WOFFSET       0
#define SATA0_AHCI_HBA_BIST_OVERRIDE_CTL_0_S_DEFAULT       (_MK_MASK_CONST(0x00000000)
#define SATA0_AHCI_HBA_BIST_OVERRIDE_CTL_0_S_DEFAULT_MASK  (_MK_MASK_CONST(0x1)
#define SATA0_AHCI_HBA_BIST_OVERRIDE_CTL_0_S_SW_DEFAULT    (_MK_MASK_CONST(0x00000000)
#define SATA0_AHCI_HBA_BIST_OVERRIDE_CTL_0_S_SW_DEFAULT_MASK (_MK_MASK_CONST(0x1)
#define SATA0_AHCI_HBA_BIST_OVERRIDE_CTL_0_P_SHIFT          _MK_SHIFT_CONST(4)                                                              // RWWVF
#define SATA0_AHCI_HBA_BIST_OVERRIDE_CTL_0_P_FIELD         (_MK_SHIFT_CONST(0x1) << SATA0_AHCI_HBA_BIST_OVERRIDE_CTL_0_P_SHIFT)
#define SATA0_AHCI_HBA_BIST_OVERRIDE_CTL_0_P_RANGE         4:4
#define SATA0_AHCI_HBA_BIST_OVERRIDE_CTL_0_P_WOFFSET       0
#define SATA0_AHCI_HBA_BIST_OVERRIDE_CTL_0_P_DEFAULT       (_MK_MASK_CONST(0x00000000)
#define SATA0_AHCI_HBA_BIST_OVERRIDE_CTL_0_P_DEFAULT_MASK  (_MK_MASK_CONST(0x1)
#define SATA0_AHCI_HBA_BIST_OVERRIDE_CTL_0_P_SW_DEFAULT    (_MK_MASK_CONST(0x00000000)
#define SATA0_AHCI_HBA_BIST_OVERRIDE_CTL_0_P_SW_DEFAULT_MASK (_MK_MASK_CONST(0x1)
#define SATA0_AHCI_HBA_BIST_OVERRIDE_CTL_0_BIST_T_RDY_SHIFT  _MK_SHIFT_CONST(5)                                                              // RWWVF
#define SATA0_AHCI_HBA_BIST_OVERRIDE_CTL_0_BIST_T_RDY_FIELD (_MK_SHIFT_CONST(0x1) << SATA0_AHCI_HBA_BIST_OVERRIDE_CTL_0_BIST_T_RDY_SHIFT)
#define SATA0_AHCI_HBA_BIST_OVERRIDE_CTL_0_BIST_T_RDY_RANGE 5:5
#define SATA0_AHCI_HBA_BIST_OVERRIDE_CTL_0_BIST_T_RDY_WOFFSET 0
#define SATA0_AHCI_HBA_BIST_OVERRIDE_CTL_0_BIST_T_RDY_DEFAULT (_MK_MASK_CONST(0x00000000)
#define SATA0_AHCI_HBA_BIST_OVERRIDE_CTL_0_BIST_T_RDY_DEFAULT_MASK (_MK_MASK_CONST(0x1)
#define SATA0_AHCI_HBA_BIST_OVERRIDE_CTL_0_BIST_T_RDY_SW_DEFAULT (_MK_MASK_CONST(0x00000000)
#define SATA0_AHCI_HBA_BIST_OVERRIDE_CTL_0_BIST_T_RDY_SW_DEFAULT_MASK (_MK_MASK_CONST(0x1)
#define SATA0_AHCI_HBA_BIST_OVERRIDE_CTL_0_BIST_L_RDY_SHIFT  _MK_SHIFT_CONST(6)                                                              // RWWVF
#define SATA0_AHCI_HBA_BIST_OVERRIDE_CTL_0_BIST_L_RDY_FIELD (_MK_SHIFT_CONST(0x1) << SATA0_AHCI_HBA_BIST_OVERRIDE_CTL_0_BIST_L_RDY_SHIFT)
#define SATA0_AHCI_HBA_BIST_OVERRIDE_CTL_0_BIST_L_RDY_RANGE 6:6
#define SATA0_AHCI_HBA_BIST_OVERRIDE_CTL_0_BIST_L_RDY_WOFFSET 0
#define SATA0_AHCI_HBA_BIST_OVERRIDE_CTL_0_BIST_L_RDY_DEFAULT (_MK_MASK_CONST(0x00000000)
#define SATA0_AHCI_HBA_BIST_OVERRIDE_CTL_0_BIST_L_RDY_DEFAULT_MASK (_MK_MASK_CONST(0x1)
#define SATA0_AHCI_HBA_BIST_OVERRIDE_CTL_0_BIST_L_RDY_SW_DEFAULT (_MK_MASK_CONST(0x00000000)
#define SATA0_AHCI_HBA_BIST_OVERRIDE_CTL_0_BIST_L_RDY_SW_DEFAULT_MASK (_MK_MASK_CONST(0x1)
#define SATA0_AHCI_HBA_BIST_OVERRIDE_CTL_0_BIST_DWORD_SHIFT  _MK_SHIFT_CONST(7)                                                              // RWWVF
#define SATA0_AHCI_HBA_BIST_OVERRIDE_CTL_0_BIST_DWORD_FIELD (_MK_SHIFT_CONST(0x1) << SATA0_AHCI_HBA_BIST_OVERRIDE_CTL_0_BIST_DWORD_SHIFT)
#define SATA0_AHCI_HBA_BIST_OVERRIDE_CTL_0_BIST_DWORD_RANGE 7:7
#define SATA0_AHCI_HBA_BIST_OVERRIDE_CTL_0_BIST_DWORD_WOFFSET 0
#define SATA0_AHCI_HBA_BIST_OVERRIDE_CTL_0_BIST_DWORD_DEFAULT (_MK_MASK_CONST(0x00000000)
#define SATA0_AHCI_HBA_BIST_OVERRIDE_CTL_0_BIST_DWORD_DEFAULT_MASK (_MK_MASK_CONST(0x1)
#define SATA0_AHCI_HBA_BIST_OVERRIDE_CTL_0_BIST_DWORD_SW_DEFAULT (_MK_MASK_CONST(0x00000000)
#define SATA0_AHCI_HBA_BIST_OVERRIDE_CTL_0_BIST_DWORD_SW_DEFAULT_MASK (_MK_MASK_CONST(0x1)
#define SATA0_AHCI_HBA_BIST_OVERRIDE_CTL_0_F_SHIFT          _MK_SHIFT_CONST(8)                                                              // RWWVF
#define SATA0_AHCI_HBA_BIST_OVERRIDE_CTL_0_F_FIELD         (_MK_SHIFT_CONST(0x1) << SATA0_AHCI_HBA_BIST_OVERRIDE_CTL_0_F_SHIFT)
#define SATA0_AHCI_HBA_BIST_OVERRIDE_CTL_0_F_RANGE         8:8
#define SATA0_AHCI_HBA_BIST_OVERRIDE_CTL_0_F_WOFFSET       0
#define SATA0_AHCI_HBA_BIST_OVERRIDE_CTL_0_F_DEFAULT       (_MK_MASK_CONST(0x00000000)
#define SATA0_AHCI_HBA_BIST_OVERRIDE_CTL_0_F_DEFAULT_MASK  (_MK_MASK_CONST(0x1)
#define SATA0_AHCI_HBA_BIST_OVERRIDE_CTL_0_F_SW_DEFAULT    (_MK_MASK_CONST(0x00000000)
#define SATA0_AHCI_HBA_BIST_OVERRIDE_CTL_0_F_SW_DEFAULT_MASK (_MK_MASK_CONST(0x1)
#define SATA0_AHCI_HBA_BIST_OVERRIDE_CTL_0_USE_BIST_F_MODE_SHIFT  _MK_SHIFT_CONST(9)                                                              // RWWVF
#define SATA0_AHCI_HBA_BIST_OVERRIDE_CTL_0_USE_BIST_F_MODE_FIELD (_MK_SHIFT_CONST(0x1) << SATA0_AHCI_HBA_BIST_OVERRIDE_CTL_0_USE_BIST_F_MODE_SHIFT)
#define SATA0_AHCI_HBA_BIST_OVERRIDE_CTL_0_USE_BIST_F_MODE_RANGE 9:9
#define SATA0_AHCI_HBA_BIST_OVERRIDE_CTL_0_USE_BIST_F_MODE_WOFFSET 0
#define SATA0_AHCI_HBA_BIST_OVERRIDE_CTL_0_USE_BIST_F_MODE_DEFAULT (_MK_MASK_CONST(0x00000001)
#define SATA0_AHCI_HBA_BIST_OVERRIDE_CTL_0_USE_BIST_F_MODE_DEFAULT_MASK (_MK_MASK_CONST(0x1)
#define SATA0_AHCI_HBA_BIST_OVERRIDE_CTL_0_USE_BIST_F_MODE_SW_DEFAULT (_MK_MASK_CONST(0x00000001)
#define SATA0_AHCI_HBA_BIST_OVERRIDE_CTL_0_USE_BIST_F_MODE_SW_DEFAULT_MASK (_MK_MASK_CONST(0x1)
#define SATA0_AHCI_HBA_BIST_OVERRIDE_CTL_0_USE_BIST_F_MODE_YES _MK_ENUM_CONST(0x00000001)                                                       // RWW-V
#define SATA0_AHCI_HBA_BIST_OVERRIDE_CTL_0_DISABLE_ASYNC_RECOVERY_SHIFT  _MK_SHIFT_CONST(10)                                                             // RWWVF
#define SATA0_AHCI_HBA_BIST_OVERRIDE_CTL_0_DISABLE_ASYNC_RECOVERY_FIELD (_MK_SHIFT_CONST(0x1) << SATA0_AHCI_HBA_BIST_OVERRIDE_CTL_0_DISABLE_ASYNC_RECOVERY_SHIFT)
#define SATA0_AHCI_HBA_BIST_OVERRIDE_CTL_0_DISABLE_ASYNC_RECOVERY_RANGE 10:10
#define SATA0_AHCI_HBA_BIST_OVERRIDE_CTL_0_DISABLE_ASYNC_RECOVERY_WOFFSET 0
#define SATA0_AHCI_HBA_BIST_OVERRIDE_CTL_0_DISABLE_ASYNC_RECOVERY_DEFAULT (_MK_MASK_CONST(0x00000001)
#define SATA0_AHCI_HBA_BIST_OVERRIDE_CTL_0_DISABLE_ASYNC_RECOVERY_DEFAULT_MASK (_MK_MASK_CONST(0x1)
#define SATA0_AHCI_HBA_BIST_OVERRIDE_CTL_0_DISABLE_ASYNC_RECOVERY_SW_DEFAULT (_MK_MASK_CONST(0x00000001)
#define SATA0_AHCI_HBA_BIST_OVERRIDE_CTL_0_DISABLE_ASYNC_RECOVERY_SW_DEFAULT_MASK (_MK_MASK_CONST(0x1)
#define SATA0_AHCI_HBA_BIST_OVERRIDE_CTL_0_DISABLE_ASYNC_RECOVERY_YES _MK_ENUM_CONST(0x00000001)                                                       // RWW-V
#define SATA0_AHCI_HBA_BIST_OVERRIDE_CTL_0_RSVD_SHIFT       _MK_SHIFT_CONST(11)                                                             // RWWVF
#define SATA0_AHCI_HBA_BIST_OVERRIDE_CTL_0_RSVD_FIELD      (_MK_SHIFT_CONST(0x1fff) << SATA0_AHCI_HBA_BIST_OVERRIDE_CTL_0_RSVD_SHIFT)
#define SATA0_AHCI_HBA_BIST_OVERRIDE_CTL_0_RSVD_RANGE      23:11
#define SATA0_AHCI_HBA_BIST_OVERRIDE_CTL_0_RSVD_WOFFSET    0
#define SATA0_AHCI_HBA_BIST_OVERRIDE_CTL_0_RSVD_DEFAULT    (_MK_MASK_CONST(0x00000000)
#define SATA0_AHCI_HBA_BIST_OVERRIDE_CTL_0_RSVD_DEFAULT_MASK (_MK_MASK_CONST(0x1fff)
#define SATA0_AHCI_HBA_BIST_OVERRIDE_CTL_0_RSVD_SW_DEFAULT (_MK_MASK_CONST(0x00000000)
#define SATA0_AHCI_HBA_BIST_OVERRIDE_CTL_0_RSVD_SW_DEFAULT_MASK (_MK_MASK_CONST(0x1fff)
#define SATA0_AHCI_HBA_BIST_OVERRIDE_CTL_0_PORTS_SHIFT      _MK_SHIFT_CONST(24)                                                             // RWWVF
#define SATA0_AHCI_HBA_BIST_OVERRIDE_CTL_0_PORTS_FIELD     (_MK_SHIFT_CONST(0xff) << SATA0_AHCI_HBA_BIST_OVERRIDE_CTL_0_PORTS_SHIFT)
#define SATA0_AHCI_HBA_BIST_OVERRIDE_CTL_0_PORTS_RANGE     31:24
#define SATA0_AHCI_HBA_BIST_OVERRIDE_CTL_0_PORTS_WOFFSET   0
#define SATA0_AHCI_HBA_BIST_OVERRIDE_CTL_0_PORTS_DEFAULT   (_MK_MASK_CONST(0x00000000)
#define SATA0_AHCI_HBA_BIST_OVERRIDE_CTL_0_PORTS_DEFAULT_MASK (_MK_MASK_CONST(0xff)
#define SATA0_AHCI_HBA_BIST_OVERRIDE_CTL_0_PORTS_SW_DEFAULT (_MK_MASK_CONST(0x00000000)
#define SATA0_AHCI_HBA_BIST_OVERRIDE_CTL_0_PORTS_SW_DEFAULT_MASK (_MK_MASK_CONST(0xff)
// 
// 
// .LABEL PUBLIC
// 
// .LABEL PRIVATE INT_REL
// .TITLE AHCI_HBA_BIST_DWORD
// This register has the Dword which is used in 2nd and 3rd Dword of BIST FIS
// 
// 31           24 23           16 15            8 7             0
// .-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-.
// |0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0| SPARE Reg BC
// `-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-'
// 
#define SATA0_AHCI_HBA_BIST_DWORD_0                        0x0000031C                                                                       // RWW4R
#define SATA0_AHCI_HBA_BIST_DWORD_0_SECURE                 0
#define SATA0_AHCI_HBA_BIST_DWORD_0_WORD_COUNT             1
#define SATA0_AHCI_HBA_BIST_DWORD_0_RESET_VAL              0x0
#define SATA0_AHCI_HBA_BIST_DWORD_0_RESET_MASK             0x0
#define SATA0_AHCI_HBA_BIST_DWORD_0_SW_DEFAULT_VAL         0x0
#define SATA0_AHCI_HBA_BIST_DWORD_0_SW_DEFAULT_MASK        0x0
#define SATA0_AHCI_HBA_BIST_DWORD_0_READ_MASK              0xffffffff
#define SATA0_AHCI_HBA_BIST_DWORD_0_WRITE_MASK             0xffffffff
#define SATA0_AHCI_HBA_BIST_DWORD_0_DATA_SHIFT              _MK_SHIFT_CONST(0)                                                              // RWWVF
#define SATA0_AHCI_HBA_BIST_DWORD_0_DATA_FIELD             (_MK_SHIFT_CONST(0xffffffff) << SATA0_AHCI_HBA_BIST_DWORD_0_DATA_SHIFT)
#define SATA0_AHCI_HBA_BIST_DWORD_0_DATA_RANGE             31:0
#define SATA0_AHCI_HBA_BIST_DWORD_0_DATA_WOFFSET           0
#define SATA0_AHCI_HBA_BIST_DWORD_0_DATA_DEFAULT           (_MK_MASK_CONST(0x00000000)
#define SATA0_AHCI_HBA_BIST_DWORD_0_DATA_DEFAULT_MASK      (_MK_MASK_CONST(0xffffffff)
#define SATA0_AHCI_HBA_BIST_DWORD_0_DATA_SW_DEFAULT        (_MK_MASK_CONST(0x00000000)
#define SATA0_AHCI_HBA_BIST_DWORD_0_DATA_SW_DEFAULT_MASK   (_MK_MASK_CONST(0xffffffff)
// 
// 
// .LABEL PUBLIC
// 
// .LABEL PRIVATE INT_REL
// .TITLE HBA_SPARE_1
// .FIELD MS_TIMER_CNT
// This gives the count of fpci_clk for counting to millisecond.
// 
// .LABEL PRIVATE
// .FIELD USE_PMREQ_S
// When set to one will use the normal pmreq_s_rcvd to decide whether to send a PMACK/ PMNACK to the drive
// When set to zero will use a signal generated based on link being in L_IDLE and pmreq_s_rcvd
// BUG 604118
// .LABEL PRIVATE INT_REL
// 
// 31           24 23           16 15            8 7             0
// .-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-.
// |0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0| SPARE Reg 1
// `-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-'
// 
#define SATA0_AHCI_HBA_SPARE_1_0                           0x00000320                                                                       // RW-4R
#define SATA0_AHCI_HBA_SPARE_1_0_SECURE                    0
#define SATA0_AHCI_HBA_SPARE_1_0_WORD_COUNT                1
#define SATA0_AHCI_HBA_SPARE_1_0_RESET_VAL                 0x0
#define SATA0_AHCI_HBA_SPARE_1_0_RESET_MASK                0x0
#define SATA0_AHCI_HBA_SPARE_1_0_SW_DEFAULT_VAL            0x0
#define SATA0_AHCI_HBA_SPARE_1_0_SW_DEFAULT_MASK           0x0
#define SATA0_AHCI_HBA_SPARE_1_0_READ_MASK                 0xffffffff
#define SATA0_AHCI_HBA_SPARE_1_0_WRITE_MASK                0xffffffff
#define SATA0_AHCI_HBA_SPARE_1_0_MS_TIMER_CNT_SHIFT         _MK_SHIFT_CONST(0)                                                              // RWC-F
#define SATA0_AHCI_HBA_SPARE_1_0_MS_TIMER_CNT_FIELD        (_MK_SHIFT_CONST(0xffffff) << SATA0_AHCI_HBA_SPARE_1_0_MS_TIMER_CNT_SHIFT)
#define SATA0_AHCI_HBA_SPARE_1_0_MS_TIMER_CNT_RANGE        23:0
#define SATA0_AHCI_HBA_SPARE_1_0_MS_TIMER_CNT_WOFFSET      0
#define SATA0_AHCI_HBA_SPARE_1_0_MS_TIMER_CNT_200MHZ       _MK_ENUM_CONST(0x00030D40)                                                       // RW--V
#define SATA0_AHCI_HBA_SPARE_1_0_MS_TIMER_CNT_250MHZ       _MK_ENUM_CONST(0x0003D090)                                                       // RW--V
#define SATA0_AHCI_HBA_SPARE_1_0_MS_TIMER_CNT_300MHZ       _MK_ENUM_CONST(0x000493E0)                                                       // RW--V
#define SATA0_AHCI_HBA_SPARE_1_0_MS_TIMER_CNT_350MHZ       _MK_ENUM_CONST(0x00055730)                                                       // RW--V
#define SATA0_AHCI_HBA_SPARE_1_0_MS_TIMER_CNT_400MHZ       _MK_ENUM_CONST(0x00061A80)                                                       // RW--V
#define SATA0_AHCI_HBA_SPARE_1_0_MS_TIMER_CNT_500MHZ       _MK_ENUM_CONST(0x0007A120)                                                       // RW--V
#define SATA0_AHCI_HBA_SPARE_1_0_MS_TIMER_CNT_40MHZ__PROD_C_FPGA _MK_ENUM_CONST(0x00009C40)                                                       // RW--V
#define SATA0_AHCI_HBA_SPARE_1_0_RSVD_SHIFT                 _MK_SHIFT_CONST(24)                                                             // RWC-F
#define SATA0_AHCI_HBA_SPARE_1_0_RSVD_FIELD                (_MK_SHIFT_CONST(0xff) << SATA0_AHCI_HBA_SPARE_1_0_RSVD_SHIFT)
#define SATA0_AHCI_HBA_SPARE_1_0_RSVD_RANGE                31:24
#define SATA0_AHCI_HBA_SPARE_1_0_RSVD_WOFFSET              0
#define SATA0_AHCI_HBA_SPARE_1_0_RSVD_ZERO                 _MK_ENUM_CONST(0x00000000)                                                       // RWC-V
// 
// .LABEL PRIVATE
// .define T_SATA0_AHCI_HBA_SPARE_1_USE_PMREQ_S                      24:24 /* RWC-F */
// .define T_SATA0_AHCI_HBA_SPARE_1_USE_PMREQ_S_DEFAULT         0x00000000 /* RWC-V */
// 
// .LABEL PUBLIC
// 
// 
// .LABEL PRIVATE INT_REL
// .TITLE HBA_SPARE_2
// 
// 31           24 23           16 15            8 7             0
// .-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-.
// |0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0| SPARE Reg 2
// `-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-'
#define SATA0_AHCI_HBA_SPARE_2_0                           0x00000324                                                                       // RW-4R
#define SATA0_AHCI_HBA_SPARE_2_0_SECURE                    0
#define SATA0_AHCI_HBA_SPARE_2_0_WORD_COUNT                1
#define SATA0_AHCI_HBA_SPARE_2_0_RESET_VAL                 0x0
#define SATA0_AHCI_HBA_SPARE_2_0_RESET_MASK                0x0
#define SATA0_AHCI_HBA_SPARE_2_0_SW_DEFAULT_VAL            0x0
#define SATA0_AHCI_HBA_SPARE_2_0_SW_DEFAULT_MASK           0x0
#define SATA0_AHCI_HBA_SPARE_2_0_READ_MASK                 0xffffff00
#define SATA0_AHCI_HBA_SPARE_2_0_WRITE_MASK                0xffffff00
#define SATA0_AHCI_HBA_SPARE_2_0_ASYNC_RECOVERY_TIMER_SEL_SHIFT  _MK_SHIFT_CONST(8)                                                              // RWCVF
#define SATA0_AHCI_HBA_SPARE_2_0_ASYNC_RECOVERY_TIMER_SEL_FIELD (_MK_SHIFT_CONST(0xf) << SATA0_AHCI_HBA_SPARE_2_0_ASYNC_RECOVERY_TIMER_SEL_SHIFT)
#define SATA0_AHCI_HBA_SPARE_2_0_ASYNC_RECOVERY_TIMER_SEL_RANGE 11:8
#define SATA0_AHCI_HBA_SPARE_2_0_ASYNC_RECOVERY_TIMER_SEL_WOFFSET 0
#define SATA0_AHCI_HBA_SPARE_2_0_ASYNC_RECOVERY_ENABLE_SHIFT  _MK_SHIFT_CONST(12)                                                             // RWCVF
#define SATA0_AHCI_HBA_SPARE_2_0_ASYNC_RECOVERY_ENABLE_FIELD (_MK_SHIFT_CONST(0x1) << SATA0_AHCI_HBA_SPARE_2_0_ASYNC_RECOVERY_ENABLE_SHIFT)
#define SATA0_AHCI_HBA_SPARE_2_0_ASYNC_RECOVERY_ENABLE_RANGE 12:12
#define SATA0_AHCI_HBA_SPARE_2_0_ASYNC_RECOVERY_ENABLE_WOFFSET 0
#define SATA0_AHCI_HBA_SPARE_2_0_ASYNC_RECOVERY_ENABLE_TURE _MK_ENUM_CONST(0x00000001)                                                       // RWC-V
#define SATA0_AHCI_HBA_SPARE_2_0_ASYNC_RECOVERY_ENABLE_FALSE _MK_ENUM_CONST(0x00000000)                                                       // RW--V
#define SATA0_AHCI_HBA_SPARE_2_0_SW_COMWAKE_CONTINUOUS_SHIFT  _MK_SHIFT_CONST(13)                                                             // RWCVF
#define SATA0_AHCI_HBA_SPARE_2_0_SW_COMWAKE_CONTINUOUS_FIELD (_MK_SHIFT_CONST(0x1) << SATA0_AHCI_HBA_SPARE_2_0_SW_COMWAKE_CONTINUOUS_SHIFT)
#define SATA0_AHCI_HBA_SPARE_2_0_SW_COMWAKE_CONTINUOUS_RANGE 13:13
#define SATA0_AHCI_HBA_SPARE_2_0_SW_COMWAKE_CONTINUOUS_WOFFSET 0
#define SATA0_AHCI_HBA_SPARE_2_0_SW_COMWAKE_CONTINUOUS_ENABLE _MK_ENUM_CONST(0x00000001)                                                       // RW--V
#define SATA0_AHCI_HBA_SPARE_2_0_SW_COMWAKE_CONTINUOUS_DISABLE _MK_ENUM_CONST(0x00000000)                                                       // RWC-V
#define SATA0_AHCI_HBA_SPARE_2_0_DONT_USE_LD_IN_COUNTER_SHIFT  _MK_SHIFT_CONST(14)                                                             // RWCVF
#define SATA0_AHCI_HBA_SPARE_2_0_DONT_USE_LD_IN_COUNTER_FIELD (_MK_SHIFT_CONST(0x1) << SATA0_AHCI_HBA_SPARE_2_0_DONT_USE_LD_IN_COUNTER_SHIFT)
#define SATA0_AHCI_HBA_SPARE_2_0_DONT_USE_LD_IN_COUNTER_RANGE 14:14
#define SATA0_AHCI_HBA_SPARE_2_0_DONT_USE_LD_IN_COUNTER_WOFFSET 0
#define SATA0_AHCI_HBA_SPARE_2_0_DONT_USE_LD_IN_COUNTER_INIT _MK_ENUM_CONST(0x00000000)                                                       // RWC-V
#define SATA0_AHCI_HBA_SPARE_2_0_LINK_IN_PROCESS_OF_LOW_POWER_SHIFT  _MK_SHIFT_CONST(15)                                                             // RWC-F
#define SATA0_AHCI_HBA_SPARE_2_0_LINK_IN_PROCESS_OF_LOW_POWER_FIELD (_MK_SHIFT_CONST(0x1) << SATA0_AHCI_HBA_SPARE_2_0_LINK_IN_PROCESS_OF_LOW_POWER_SHIFT)
#define SATA0_AHCI_HBA_SPARE_2_0_LINK_IN_PROCESS_OF_LOW_POWER_RANGE 15:15
#define SATA0_AHCI_HBA_SPARE_2_0_LINK_IN_PROCESS_OF_LOW_POWER_WOFFSET 0
#define SATA0_AHCI_HBA_SPARE_2_0_RSVD_SHIFT                 _MK_SHIFT_CONST(16)                                                             // RWC-F
#define SATA0_AHCI_HBA_SPARE_2_0_RSVD_FIELD                (_MK_SHIFT_CONST(0xfff) << SATA0_AHCI_HBA_SPARE_2_0_RSVD_SHIFT)
#define SATA0_AHCI_HBA_SPARE_2_0_RSVD_RANGE                27:16
#define SATA0_AHCI_HBA_SPARE_2_0_RSVD_WOFFSET              0
#define SATA0_AHCI_HBA_SPARE_2_0_RSVD_ZERO                 _MK_ENUM_CONST(0x00000001)                                                       // RWC-V
#define SATA0_AHCI_HBA_SPARE_2_0_CYA_UPHY_TX_EN_DYNAMIC_SHIFT  _MK_SHIFT_CONST(28)                                                             // RWC-F
#define SATA0_AHCI_HBA_SPARE_2_0_CYA_UPHY_TX_EN_DYNAMIC_FIELD (_MK_SHIFT_CONST(0x1) << SATA0_AHCI_HBA_SPARE_2_0_CYA_UPHY_TX_EN_DYNAMIC_SHIFT)
#define SATA0_AHCI_HBA_SPARE_2_0_CYA_UPHY_TX_EN_DYNAMIC_RANGE 28:28
#define SATA0_AHCI_HBA_SPARE_2_0_CYA_UPHY_TX_EN_DYNAMIC_WOFFSET 0
#define SATA0_AHCI_HBA_SPARE_2_0_CYA_UPHY_TX_EN_DYNAMIC_ENABLE _MK_ENUM_CONST(0x00000001)                                                       // RWC-V
#define SATA0_AHCI_HBA_SPARE_2_0_CYA_UPHY_RX_EN_DYNAMIC_SHIFT  _MK_SHIFT_CONST(29)                                                             // RWC-F
#define SATA0_AHCI_HBA_SPARE_2_0_CYA_UPHY_RX_EN_DYNAMIC_FIELD (_MK_SHIFT_CONST(0x1) << SATA0_AHCI_HBA_SPARE_2_0_CYA_UPHY_RX_EN_DYNAMIC_SHIFT)
#define SATA0_AHCI_HBA_SPARE_2_0_CYA_UPHY_RX_EN_DYNAMIC_RANGE 29:29
#define SATA0_AHCI_HBA_SPARE_2_0_CYA_UPHY_RX_EN_DYNAMIC_WOFFSET 0
#define SATA0_AHCI_HBA_SPARE_2_0_CYA_UPHY_RX_EN_DYNAMIC_ENABLE _MK_ENUM_CONST(0x00000001)                                                       // RWC-V
#define SATA0_AHCI_HBA_SPARE_2_0_CYA_ASYNC_REC_RETRY_CLK_SHIFT  _MK_SHIFT_CONST(30)                                                             // RWC-F
#define SATA0_AHCI_HBA_SPARE_2_0_CYA_ASYNC_REC_RETRY_CLK_FIELD (_MK_SHIFT_CONST(0x1) << SATA0_AHCI_HBA_SPARE_2_0_CYA_ASYNC_REC_RETRY_CLK_SHIFT)
#define SATA0_AHCI_HBA_SPARE_2_0_CYA_ASYNC_REC_RETRY_CLK_RANGE 30:30
#define SATA0_AHCI_HBA_SPARE_2_0_CYA_ASYNC_REC_RETRY_CLK_WOFFSET 0
#define SATA0_AHCI_HBA_SPARE_2_0_CYA_ASYNC_REC_RETRY_CLK_TXCLK _MK_ENUM_CONST(0x00000000)                                                       // RW--V
#define SATA0_AHCI_HBA_SPARE_2_0_CYA_ASYNC_REC_RETRY_CLK_OOBCLK _MK_ENUM_CONST(0x00000001)                                                       // RWC-V
#define SATA0_AHCI_HBA_SPARE_2_0_CYA_DEC_ERR_DATA_SHIFT     _MK_SHIFT_CONST(31)                                                             // RWC-F
#define SATA0_AHCI_HBA_SPARE_2_0_CYA_DEC_ERR_DATA_FIELD    (_MK_SHIFT_CONST(0x1) << SATA0_AHCI_HBA_SPARE_2_0_CYA_DEC_ERR_DATA_SHIFT)
#define SATA0_AHCI_HBA_SPARE_2_0_CYA_DEC_ERR_DATA_RANGE    31:31
#define SATA0_AHCI_HBA_SPARE_2_0_CYA_DEC_ERR_DATA_WOFFSET  0
#define SATA0_AHCI_HBA_SPARE_2_0_CYA_DEC_ERR_DATA_ENABLE   _MK_ENUM_CONST(0x00000001)                                                       // RWC-V
// 
// 
// 
// 
// 
// 
// 
// .LABEL PUBLIC
// 
// .LABEL PRIVATE INT_REL
// DYN_CLK_CLAMP_TIMER is used to wait for some time after the transactions on FPCI and CSM are done to shutdown the devclk
// 
// 31           24 23           16 15            8 7             0
// .-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-.
// |0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0| DYN_CLK_CLAMP Reg F8
// `-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-'
// 
#define SATA0_AHCI_HBA_DYN_CLK_CLAMP_0                     0x00000328                                                                       // RW-4R
#define SATA0_AHCI_HBA_DYN_CLK_CLAMP_0_SECURE              0
#define SATA0_AHCI_HBA_DYN_CLK_CLAMP_0_WORD_COUNT          1
#define SATA0_AHCI_HBA_DYN_CLK_CLAMP_0_RESET_VAL           0x0
#define SATA0_AHCI_HBA_DYN_CLK_CLAMP_0_RESET_MASK          0x0
#define SATA0_AHCI_HBA_DYN_CLK_CLAMP_0_SW_DEFAULT_VAL      0x0
#define SATA0_AHCI_HBA_DYN_CLK_CLAMP_0_SW_DEFAULT_MASK     0x0
#define SATA0_AHCI_HBA_DYN_CLK_CLAMP_0_READ_MASK           0xffffffff
#define SATA0_AHCI_HBA_DYN_CLK_CLAMP_0_WRITE_MASK          0xffffffff
#define SATA0_AHCI_HBA_DYN_CLK_CLAMP_0_SPARE_0_2_SHIFT      _MK_SHIFT_CONST(0)                                                              // RWC-F
#define SATA0_AHCI_HBA_DYN_CLK_CLAMP_0_SPARE_0_2_FIELD     (_MK_SHIFT_CONST(0x7) << SATA0_AHCI_HBA_DYN_CLK_CLAMP_0_SPARE_0_2_SHIFT)
#define SATA0_AHCI_HBA_DYN_CLK_CLAMP_0_SPARE_0_2_RANGE     2:0
#define SATA0_AHCI_HBA_DYN_CLK_CLAMP_0_SPARE_0_2_WOFFSET   0
#define SATA0_AHCI_HBA_DYN_CLK_CLAMP_0_SPARE_0_2_INIT      _MK_ENUM_CONST(0x00000007)                                                       // RWC-V
#define SATA0_AHCI_HBA_DYN_CLK_CLAMP_0_SPARE_0_SHIFT        _MK_SHIFT_CONST(3)                                                              // RWC-F
#define SATA0_AHCI_HBA_DYN_CLK_CLAMP_0_SPARE_0_FIELD       (_MK_SHIFT_CONST(0x1f) << SATA0_AHCI_HBA_DYN_CLK_CLAMP_0_SPARE_0_SHIFT)
#define SATA0_AHCI_HBA_DYN_CLK_CLAMP_0_SPARE_0_RANGE       7:3
#define SATA0_AHCI_HBA_DYN_CLK_CLAMP_0_SPARE_0_WOFFSET     0
#define SATA0_AHCI_HBA_DYN_CLK_CLAMP_0_SPARE_0_INIT        _MK_ENUM_CONST(0x00000000)                                                       // RWC-V
#define SATA0_AHCI_HBA_DYN_CLK_CLAMP_0_TIMER_SHIFT          _MK_SHIFT_CONST(8)                                                              // RWC-F
#define SATA0_AHCI_HBA_DYN_CLK_CLAMP_0_TIMER_FIELD         (_MK_SHIFT_CONST(0xff) << SATA0_AHCI_HBA_DYN_CLK_CLAMP_0_TIMER_SHIFT)
#define SATA0_AHCI_HBA_DYN_CLK_CLAMP_0_TIMER_RANGE         15:8
#define SATA0_AHCI_HBA_DYN_CLK_CLAMP_0_TIMER_WOFFSET       0
#define SATA0_AHCI_HBA_DYN_CLK_CLAMP_0_SPARE_1_SHIFT        _MK_SHIFT_CONST(16)                                                             // RWC-F
#define SATA0_AHCI_HBA_DYN_CLK_CLAMP_0_SPARE_1_FIELD       (_MK_SHIFT_CONST(0xff) << SATA0_AHCI_HBA_DYN_CLK_CLAMP_0_SPARE_1_SHIFT)
#define SATA0_AHCI_HBA_DYN_CLK_CLAMP_0_SPARE_1_RANGE       23:16
#define SATA0_AHCI_HBA_DYN_CLK_CLAMP_0_SPARE_1_WOFFSET     0
#define SATA0_AHCI_HBA_DYN_CLK_CLAMP_0_SPARE_1_INIT        _MK_ENUM_CONST(0x00000000)                                                       // RWC-V
#define SATA0_AHCI_HBA_DYN_CLK_CLAMP_0_TIMER_PSM_SHIFT      _MK_SHIFT_CONST(24)                                                             // RWC-F
#define SATA0_AHCI_HBA_DYN_CLK_CLAMP_0_TIMER_PSM_FIELD     (_MK_SHIFT_CONST(0xff) << SATA0_AHCI_HBA_DYN_CLK_CLAMP_0_TIMER_PSM_SHIFT)
#define SATA0_AHCI_HBA_DYN_CLK_CLAMP_0_TIMER_PSM_RANGE     31:24
#define SATA0_AHCI_HBA_DYN_CLK_CLAMP_0_TIMER_PSM_WOFFSET   0
#define SATA0_AHCI_HBA_DYN_CLK_CLAMP_0_TIMER_PSM_INIT      _MK_ENUM_CONST(0x00000002)                                                       // RWC-V
// 
// 
// 
// 
// .LABEL PUBLIC
// 
// 
// .TITLE AHCI_CFG_ERR_CTRL
// .LABEL PRIVATE INT_REL
// This register implement settings for controlling behaviour of AHCI SM
// during error conditions.
// 
//  31           24 23           16 15            8 7             0
// .-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-.
// |0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0| AHCI_CFG_ERR_CTRL
// +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
#define SATA0_AHCI_CFG_ERR_CTRL_0                          0x0000032C                                                                       // RW-4R
#define SATA0_AHCI_CFG_ERR_CTRL_0_SECURE                   0
#define SATA0_AHCI_CFG_ERR_CTRL_0_WORD_COUNT               1
#define SATA0_AHCI_CFG_ERR_CTRL_0_RESET_VAL                0x0
#define SATA0_AHCI_CFG_ERR_CTRL_0_RESET_MASK               0x0
#define SATA0_AHCI_CFG_ERR_CTRL_0_SW_DEFAULT_VAL           0x0
#define SATA0_AHCI_CFG_ERR_CTRL_0_SW_DEFAULT_MASK          0x0
#define SATA0_AHCI_CFG_ERR_CTRL_0_READ_MASK                0x3f
#define SATA0_AHCI_CFG_ERR_CTRL_0_WRITE_MASK               0x3f
#define SATA0_AHCI_CFG_ERR_CTRL_0_CLR_CMD_FIFO_ON_FATAL_ERROR_SHIFT  _MK_SHIFT_CONST(0)                                                              // RWCVF
#define SATA0_AHCI_CFG_ERR_CTRL_0_CLR_CMD_FIFO_ON_FATAL_ERROR_FIELD (_MK_SHIFT_CONST(0x1) << SATA0_AHCI_CFG_ERR_CTRL_0_CLR_CMD_FIFO_ON_FATAL_ERROR_SHIFT)
#define SATA0_AHCI_CFG_ERR_CTRL_0_CLR_CMD_FIFO_ON_FATAL_ERROR_RANGE 0:0
#define SATA0_AHCI_CFG_ERR_CTRL_0_CLR_CMD_FIFO_ON_FATAL_ERROR_WOFFSET 0
#define SATA0_AHCI_CFG_ERR_CTRL_0_CLR_CMD_FIFO_ON_FATAL_ERROR_INIT _MK_ENUM_CONST(0x00000001)                                                       // RWC-V
#define SATA0_AHCI_CFG_ERR_CTRL_0_CLR_P2T_FIFO_ON_FATAL_ERROR_SHIFT  _MK_SHIFT_CONST(1)                                                              // RWCVF
#define SATA0_AHCI_CFG_ERR_CTRL_0_CLR_P2T_FIFO_ON_FATAL_ERROR_FIELD (_MK_SHIFT_CONST(0x1) << SATA0_AHCI_CFG_ERR_CTRL_0_CLR_P2T_FIFO_ON_FATAL_ERROR_SHIFT)
#define SATA0_AHCI_CFG_ERR_CTRL_0_CLR_P2T_FIFO_ON_FATAL_ERROR_RANGE 1:1
#define SATA0_AHCI_CFG_ERR_CTRL_0_CLR_P2T_FIFO_ON_FATAL_ERROR_WOFFSET 0
#define SATA0_AHCI_CFG_ERR_CTRL_0_CLR_P2T_FIFO_ON_FATAL_ERROR_INIT _MK_ENUM_CONST(0x00000001)                                                       // RWC-V
#define SATA0_AHCI_CFG_ERR_CTRL_0_CLR_T2P_FIFO_ON_FATAL_ERROR_SHIFT  _MK_SHIFT_CONST(2)                                                              // RWCVF
#define SATA0_AHCI_CFG_ERR_CTRL_0_CLR_T2P_FIFO_ON_FATAL_ERROR_FIELD (_MK_SHIFT_CONST(0x1) << SATA0_AHCI_CFG_ERR_CTRL_0_CLR_T2P_FIFO_ON_FATAL_ERROR_SHIFT)
#define SATA0_AHCI_CFG_ERR_CTRL_0_CLR_T2P_FIFO_ON_FATAL_ERROR_RANGE 2:2
#define SATA0_AHCI_CFG_ERR_CTRL_0_CLR_T2P_FIFO_ON_FATAL_ERROR_WOFFSET 0
#define SATA0_AHCI_CFG_ERR_CTRL_0_CLR_T2P_FIFO_ON_FATAL_ERROR_INIT _MK_ENUM_CONST(0x00000001)                                                       // RWC-V
#define SATA0_AHCI_CFG_ERR_CTRL_0_CLR_TX_BUFFER_ON_FATAL_ERROR_SHIFT  _MK_SHIFT_CONST(3)                                                              // RWCVF
#define SATA0_AHCI_CFG_ERR_CTRL_0_CLR_TX_BUFFER_ON_FATAL_ERROR_FIELD (_MK_SHIFT_CONST(0x1) << SATA0_AHCI_CFG_ERR_CTRL_0_CLR_TX_BUFFER_ON_FATAL_ERROR_SHIFT)
#define SATA0_AHCI_CFG_ERR_CTRL_0_CLR_TX_BUFFER_ON_FATAL_ERROR_RANGE 3:3
#define SATA0_AHCI_CFG_ERR_CTRL_0_CLR_TX_BUFFER_ON_FATAL_ERROR_WOFFSET 0
#define SATA0_AHCI_CFG_ERR_CTRL_0_CLR_TX_BUFFER_ON_FATAL_ERROR_INIT _MK_ENUM_CONST(0x00000001)                                                       // RWC-V
#define SATA0_AHCI_CFG_ERR_CTRL_0_ENABLE_PXIS_IFS_D2H_SYNC_ESCAPE_SHIFT  _MK_SHIFT_CONST(4)                                                              // RWCVF
#define SATA0_AHCI_CFG_ERR_CTRL_0_ENABLE_PXIS_IFS_D2H_SYNC_ESCAPE_FIELD (_MK_SHIFT_CONST(0x1) << SATA0_AHCI_CFG_ERR_CTRL_0_ENABLE_PXIS_IFS_D2H_SYNC_ESCAPE_SHIFT)
#define SATA0_AHCI_CFG_ERR_CTRL_0_ENABLE_PXIS_IFS_D2H_SYNC_ESCAPE_RANGE 4:4
#define SATA0_AHCI_CFG_ERR_CTRL_0_ENABLE_PXIS_IFS_D2H_SYNC_ESCAPE_WOFFSET 0
#define SATA0_AHCI_CFG_ERR_CTRL_0_ENABLE_PXIS_IFS_D2H_SYNC_ESCAPE_INIT _MK_ENUM_CONST(0x00000001)                                                       // RWC-V
#define SATA0_AHCI_CFG_ERR_CTRL_0_ENABLE_PXIS_IFS_DATA_FIS_CRC_ERROR_SHIFT  _MK_SHIFT_CONST(5)                                                              // RWCVF
#define SATA0_AHCI_CFG_ERR_CTRL_0_ENABLE_PXIS_IFS_DATA_FIS_CRC_ERROR_FIELD (_MK_SHIFT_CONST(0x1) << SATA0_AHCI_CFG_ERR_CTRL_0_ENABLE_PXIS_IFS_DATA_FIS_CRC_ERROR_SHIFT)
#define SATA0_AHCI_CFG_ERR_CTRL_0_ENABLE_PXIS_IFS_DATA_FIS_CRC_ERROR_RANGE 5:5
#define SATA0_AHCI_CFG_ERR_CTRL_0_ENABLE_PXIS_IFS_DATA_FIS_CRC_ERROR_WOFFSET 0
#define SATA0_AHCI_CFG_ERR_CTRL_0_ENABLE_PXIS_IFS_DATA_FIS_CRC_ERROR_INIT _MK_ENUM_CONST(0x00000001)                                                       // RWC-V
// 
// .LABEL PUBLIC
// 
// .LABEL PRIVATE INT_REL
// .TITLE AHCI_HBA_CAP2_BKDR
// .LABEL PRIVATE
// SW_INIT required for this register to enable APS
// .LABEL PRIVATE INT_REL
// This register has bit by bit backdoor fields for CAP2 register according to AHCI1.3 spec
// 31           24 23           16 15            8 7             0
// .-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-.
// |0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0| AHCI_HBA_CAP2_BKDR
// `-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-'
#define SATA0_AHCI_HBA_CAP2_BKDR_0                         0x00000330                                                                       // RW-4R
#define SATA0_AHCI_HBA_CAP2_BKDR_0_SECURE                  0
#define SATA0_AHCI_HBA_CAP2_BKDR_0_WORD_COUNT              1
#define SATA0_AHCI_HBA_CAP2_BKDR_0_RESET_VAL               0x0
#define SATA0_AHCI_HBA_CAP2_BKDR_0_RESET_MASK              0x0
#define SATA0_AHCI_HBA_CAP2_BKDR_0_SW_DEFAULT_VAL          0x0
#define SATA0_AHCI_HBA_CAP2_BKDR_0_SW_DEFAULT_MASK         0x0
#define SATA0_AHCI_HBA_CAP2_BKDR_0_READ_MASK               0xffffffff
#define SATA0_AHCI_HBA_CAP2_BKDR_0_WRITE_MASK              0x3d
#define SATA0_AHCI_HBA_CAP2_BKDR_0_BOH_SHIFT                _MK_SHIFT_CONST(0)                                                              // RWCVF
#define SATA0_AHCI_HBA_CAP2_BKDR_0_BOH_FIELD               (_MK_SHIFT_CONST(0x1) << SATA0_AHCI_HBA_CAP2_BKDR_0_BOH_SHIFT)
#define SATA0_AHCI_HBA_CAP2_BKDR_0_BOH_RANGE               0:0
#define SATA0_AHCI_HBA_CAP2_BKDR_0_BOH_WOFFSET             0
#define SATA0_AHCI_HBA_CAP2_BKDR_0_BOH_TRUE                _MK_ENUM_CONST(0x00000001)                                                       // RW--V
#define SATA0_AHCI_HBA_CAP2_BKDR_0_BOH_FALSE               _MK_ENUM_CONST(0x00000000)                                                       // RWC-V
#define SATA0_AHCI_HBA_CAP2_BKDR_0_RSVD_1_SHIFT             _MK_SHIFT_CONST(1)                                                              // C--VF
#define SATA0_AHCI_HBA_CAP2_BKDR_0_RSVD_1_FIELD            (_MK_SHIFT_CONST(0x1) << SATA0_AHCI_HBA_CAP2_BKDR_0_RSVD_1_SHIFT)
#define SATA0_AHCI_HBA_CAP2_BKDR_0_RSVD_1_RANGE            1:1
#define SATA0_AHCI_HBA_CAP2_BKDR_0_RSVD_1_WOFFSET          0
#define SATA0_AHCI_HBA_CAP2_BKDR_0_RSVD_1_ZERO             _MK_ENUM_CONST(0x00000000)                                                       // C---V
#define SATA0_AHCI_HBA_CAP2_BKDR_0_AUTO_PARTIAL_TO_SLUMBER_SHIFT  _MK_SHIFT_CONST(2)                                                              // RWCVF
#define SATA0_AHCI_HBA_CAP2_BKDR_0_AUTO_PARTIAL_TO_SLUMBER_FIELD (_MK_SHIFT_CONST(0x1) << SATA0_AHCI_HBA_CAP2_BKDR_0_AUTO_PARTIAL_TO_SLUMBER_SHIFT)
#define SATA0_AHCI_HBA_CAP2_BKDR_0_AUTO_PARTIAL_TO_SLUMBER_RANGE 2:2
#define SATA0_AHCI_HBA_CAP2_BKDR_0_AUTO_PARTIAL_TO_SLUMBER_WOFFSET 0
#define SATA0_AHCI_HBA_CAP2_BKDR_0_AUTO_PARTIAL_TO_SLUMBER_TRUE _MK_ENUM_CONST(0x00000001)                                                       // RWC-V
#define SATA0_AHCI_HBA_CAP2_BKDR_0_AUTO_PARTIAL_TO_SLUMBER_FALSE _MK_ENUM_CONST(0x00000000)                                                       // RW--V
#define SATA0_AHCI_HBA_CAP2_BKDR_0_SUPPORTS_DEVSLP_SHIFT    _MK_SHIFT_CONST(3)                                                              // RWCVF
#define SATA0_AHCI_HBA_CAP2_BKDR_0_SUPPORTS_DEVSLP_FIELD   (_MK_SHIFT_CONST(0x1) << SATA0_AHCI_HBA_CAP2_BKDR_0_SUPPORTS_DEVSLP_SHIFT)
#define SATA0_AHCI_HBA_CAP2_BKDR_0_SUPPORTS_DEVSLP_RANGE   3:3
#define SATA0_AHCI_HBA_CAP2_BKDR_0_SUPPORTS_DEVSLP_WOFFSET 0
#define SATA0_AHCI_HBA_CAP2_BKDR_0_SUPPORTS_DEVSLP_TRUE    _MK_ENUM_CONST(0x00000001)                                                       // RWC-V
#define SATA0_AHCI_HBA_CAP2_BKDR_0_SUPPORTS_DEVSLP_FALSE   _MK_ENUM_CONST(0x00000000)                                                       // RW--V
#define SATA0_AHCI_HBA_CAP2_BKDR_0_SUPPORTS_AGGR_DEVSLP_SHIFT  _MK_SHIFT_CONST(4)                                                              // RWCVF
#define SATA0_AHCI_HBA_CAP2_BKDR_0_SUPPORTS_AGGR_DEVSLP_FIELD (_MK_SHIFT_CONST(0x1) << SATA0_AHCI_HBA_CAP2_BKDR_0_SUPPORTS_AGGR_DEVSLP_SHIFT)
#define SATA0_AHCI_HBA_CAP2_BKDR_0_SUPPORTS_AGGR_DEVSLP_RANGE 4:4
#define SATA0_AHCI_HBA_CAP2_BKDR_0_SUPPORTS_AGGR_DEVSLP_WOFFSET 0
#define SATA0_AHCI_HBA_CAP2_BKDR_0_SUPPORTS_AGGR_DEVSLP_TRUE _MK_ENUM_CONST(0x00000001)                                                       // RWC-V
#define SATA0_AHCI_HBA_CAP2_BKDR_0_SUPPORTS_AGGR_DEVSLP_FALSE _MK_ENUM_CONST(0x00000000)                                                       // RW--V
#define SATA0_AHCI_HBA_CAP2_BKDR_0_DEVSLP_ENTRY_FROM_SLUMBER_ONLY_SHIFT  _MK_SHIFT_CONST(5)                                                              // RWCVF
#define SATA0_AHCI_HBA_CAP2_BKDR_0_DEVSLP_ENTRY_FROM_SLUMBER_ONLY_FIELD (_MK_SHIFT_CONST(0x1) << SATA0_AHCI_HBA_CAP2_BKDR_0_DEVSLP_ENTRY_FROM_SLUMBER_ONLY_SHIFT)
#define SATA0_AHCI_HBA_CAP2_BKDR_0_DEVSLP_ENTRY_FROM_SLUMBER_ONLY_RANGE 5:5
#define SATA0_AHCI_HBA_CAP2_BKDR_0_DEVSLP_ENTRY_FROM_SLUMBER_ONLY_WOFFSET 0
#define SATA0_AHCI_HBA_CAP2_BKDR_0_DEVSLP_ENTRY_FROM_SLUMBER_ONLY_TRUE _MK_ENUM_CONST(0x00000001)                                                       // RWC-V
#define SATA0_AHCI_HBA_CAP2_BKDR_0_DEVSLP_ENTRY_FROM_SLUMBER_ONLY_FALSE _MK_ENUM_CONST(0x00000000)                                                       // RW--V
#define SATA0_AHCI_HBA_CAP2_BKDR_0_RSVD_31_6_SHIFT          _MK_SHIFT_CONST(6)                                                              // C--VF
#define SATA0_AHCI_HBA_CAP2_BKDR_0_RSVD_31_6_FIELD         (_MK_SHIFT_CONST(0x3ffffff) << SATA0_AHCI_HBA_CAP2_BKDR_0_RSVD_31_6_SHIFT)
#define SATA0_AHCI_HBA_CAP2_BKDR_0_RSVD_31_6_RANGE         31:6
#define SATA0_AHCI_HBA_CAP2_BKDR_0_RSVD_31_6_WOFFSET       0
#define SATA0_AHCI_HBA_CAP2_BKDR_0_RSVD_31_6_ZERO          _MK_ENUM_CONST(0x00000000)                                                       // C---V
// 
// 
// 
// 
// .LABEL PUBLIC
// 
// .LABEL PRIVATE INT_REL
// .TITLE HBA_CTL_1
// 
// 31           24 23           16 15            8 7             0
// .-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-.
// |0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0| CYA Reg 1
// `-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-'
// 
#define SATA0_AHCI_HBA_CYA_1_0                             0x00000338                                                                       // RW-4R
#define SATA0_AHCI_HBA_CYA_1_0_SECURE                      0
#define SATA0_AHCI_HBA_CYA_1_0_WORD_COUNT                  1
#define SATA0_AHCI_HBA_CYA_1_0_RESET_VAL                   0x0
#define SATA0_AHCI_HBA_CYA_1_0_RESET_MASK                  0x0
#define SATA0_AHCI_HBA_CYA_1_0_SW_DEFAULT_VAL              0x0
#define SATA0_AHCI_HBA_CYA_1_0_SW_DEFAULT_MASK             0x0
#define SATA0_AHCI_HBA_CYA_1_0_READ_MASK                   0xffffffff
#define SATA0_AHCI_HBA_CYA_1_0_WRITE_MASK                  0xffffffff
#define SATA0_AHCI_HBA_CYA_1_0_DISABLE_BKGD_CMD_PREFETCH_1_SHIFT  _MK_SHIFT_CONST(0)                                                              // RWWVF
#define SATA0_AHCI_HBA_CYA_1_0_DISABLE_BKGD_CMD_PREFETCH_1_FIELD (_MK_SHIFT_CONST(0x1) << SATA0_AHCI_HBA_CYA_1_0_DISABLE_BKGD_CMD_PREFETCH_1_SHIFT)
#define SATA0_AHCI_HBA_CYA_1_0_DISABLE_BKGD_CMD_PREFETCH_1_RANGE 0:0
#define SATA0_AHCI_HBA_CYA_1_0_DISABLE_BKGD_CMD_PREFETCH_1_WOFFSET 0
#define SATA0_AHCI_HBA_CYA_1_0_DISABLE_BKGD_CMD_PREFETCH_1_DEFAULT (_MK_MASK_CONST(0x00000000)
#define SATA0_AHCI_HBA_CYA_1_0_DISABLE_BKGD_CMD_PREFETCH_1_DEFAULT_MASK (_MK_MASK_CONST(0x1)
#define SATA0_AHCI_HBA_CYA_1_0_DISABLE_BKGD_CMD_PREFETCH_1_SW_DEFAULT (_MK_MASK_CONST(0x00000000)
#define SATA0_AHCI_HBA_CYA_1_0_DISABLE_BKGD_CMD_PREFETCH_1_SW_DEFAULT_MASK (_MK_MASK_CONST(0x1)
#define SATA0_AHCI_HBA_CYA_1_0_DISABLE_BKGD_CMD_PREFETCH_1_INIT _MK_ENUM_CONST(0x00000000)                                                       // RWW-V
#define SATA0_AHCI_HBA_CYA_1_0_DISABLE_BKGD_PRD_PREFETCH_SHIFT  _MK_SHIFT_CONST(1)                                                              // RWWVF
#define SATA0_AHCI_HBA_CYA_1_0_DISABLE_BKGD_PRD_PREFETCH_FIELD (_MK_SHIFT_CONST(0x1) << SATA0_AHCI_HBA_CYA_1_0_DISABLE_BKGD_PRD_PREFETCH_SHIFT)
#define SATA0_AHCI_HBA_CYA_1_0_DISABLE_BKGD_PRD_PREFETCH_RANGE 1:1
#define SATA0_AHCI_HBA_CYA_1_0_DISABLE_BKGD_PRD_PREFETCH_WOFFSET 0
#define SATA0_AHCI_HBA_CYA_1_0_DISABLE_BKGD_PRD_PREFETCH_DEFAULT (_MK_MASK_CONST(0x00000000)
#define SATA0_AHCI_HBA_CYA_1_0_DISABLE_BKGD_PRD_PREFETCH_DEFAULT_MASK (_MK_MASK_CONST(0x1)
#define SATA0_AHCI_HBA_CYA_1_0_DISABLE_BKGD_PRD_PREFETCH_SW_DEFAULT (_MK_MASK_CONST(0x00000000)
#define SATA0_AHCI_HBA_CYA_1_0_DISABLE_BKGD_PRD_PREFETCH_SW_DEFAULT_MASK (_MK_MASK_CONST(0x1)
#define SATA0_AHCI_HBA_CYA_1_0_DISABLE_BKGD_PRD_PREFETCH_INIT _MK_ENUM_CONST(0x00000000)                                                       // RWW-V
#define SATA0_AHCI_HBA_CYA_1_0_DISABLE_BKGD_DATA_PREFETCH_SHIFT  _MK_SHIFT_CONST(2)                                                              // RWWVF
#define SATA0_AHCI_HBA_CYA_1_0_DISABLE_BKGD_DATA_PREFETCH_FIELD (_MK_SHIFT_CONST(0x1) << SATA0_AHCI_HBA_CYA_1_0_DISABLE_BKGD_DATA_PREFETCH_SHIFT)
#define SATA0_AHCI_HBA_CYA_1_0_DISABLE_BKGD_DATA_PREFETCH_RANGE 2:2
#define SATA0_AHCI_HBA_CYA_1_0_DISABLE_BKGD_DATA_PREFETCH_WOFFSET 0
#define SATA0_AHCI_HBA_CYA_1_0_DISABLE_BKGD_DATA_PREFETCH_DEFAULT (_MK_MASK_CONST(0x00000000)
#define SATA0_AHCI_HBA_CYA_1_0_DISABLE_BKGD_DATA_PREFETCH_DEFAULT_MASK (_MK_MASK_CONST(0x1)
#define SATA0_AHCI_HBA_CYA_1_0_DISABLE_BKGD_DATA_PREFETCH_SW_DEFAULT (_MK_MASK_CONST(0x00000000)
#define SATA0_AHCI_HBA_CYA_1_0_DISABLE_BKGD_DATA_PREFETCH_SW_DEFAULT_MASK (_MK_MASK_CONST(0x1)
#define SATA0_AHCI_HBA_CYA_1_0_DISABLE_BKGD_DATA_PREFETCH_INIT _MK_ENUM_CONST(0x00000000)                                                       // RWW-V
#define SATA0_AHCI_HBA_CYA_1_0_DISABLE_BKGD_ACMD_PREFETCH_SHIFT  _MK_SHIFT_CONST(3)                                                              // RWWVF
#define SATA0_AHCI_HBA_CYA_1_0_DISABLE_BKGD_ACMD_PREFETCH_FIELD (_MK_SHIFT_CONST(0x1) << SATA0_AHCI_HBA_CYA_1_0_DISABLE_BKGD_ACMD_PREFETCH_SHIFT)
#define SATA0_AHCI_HBA_CYA_1_0_DISABLE_BKGD_ACMD_PREFETCH_RANGE 3:3
#define SATA0_AHCI_HBA_CYA_1_0_DISABLE_BKGD_ACMD_PREFETCH_WOFFSET 0
#define SATA0_AHCI_HBA_CYA_1_0_DISABLE_BKGD_ACMD_PREFETCH_DEFAULT (_MK_MASK_CONST(0x00000000)
#define SATA0_AHCI_HBA_CYA_1_0_DISABLE_BKGD_ACMD_PREFETCH_DEFAULT_MASK (_MK_MASK_CONST(0x1)
#define SATA0_AHCI_HBA_CYA_1_0_DISABLE_BKGD_ACMD_PREFETCH_SW_DEFAULT (_MK_MASK_CONST(0x00000000)
#define SATA0_AHCI_HBA_CYA_1_0_DISABLE_BKGD_ACMD_PREFETCH_SW_DEFAULT_MASK (_MK_MASK_CONST(0x1)
#define SATA0_AHCI_HBA_CYA_1_0_DISABLE_BKGD_ACMD_PREFETCH_INIT _MK_ENUM_CONST(0x00000000)                                                       // RWW-V
#define SATA0_AHCI_HBA_CYA_1_0_ENABLE_PRD_SPLIT_IN_CBS_SHIFT  _MK_SHIFT_CONST(4)                                                              // RWWVF
#define SATA0_AHCI_HBA_CYA_1_0_ENABLE_PRD_SPLIT_IN_CBS_FIELD (_MK_SHIFT_CONST(0x1) << SATA0_AHCI_HBA_CYA_1_0_ENABLE_PRD_SPLIT_IN_CBS_SHIFT)
#define SATA0_AHCI_HBA_CYA_1_0_ENABLE_PRD_SPLIT_IN_CBS_RANGE 4:4
#define SATA0_AHCI_HBA_CYA_1_0_ENABLE_PRD_SPLIT_IN_CBS_WOFFSET 0
#define SATA0_AHCI_HBA_CYA_1_0_ENABLE_PRD_SPLIT_IN_CBS_DEFAULT (_MK_MASK_CONST(0x00000000)
#define SATA0_AHCI_HBA_CYA_1_0_ENABLE_PRD_SPLIT_IN_CBS_DEFAULT_MASK (_MK_MASK_CONST(0x1)
#define SATA0_AHCI_HBA_CYA_1_0_ENABLE_PRD_SPLIT_IN_CBS_SW_DEFAULT (_MK_MASK_CONST(0x00000000)
#define SATA0_AHCI_HBA_CYA_1_0_ENABLE_PRD_SPLIT_IN_CBS_SW_DEFAULT_MASK (_MK_MASK_CONST(0x1)
#define SATA0_AHCI_HBA_CYA_1_0_ENABLE_PRD_SPLIT_IN_CBS_INIT _MK_ENUM_CONST(0x00000000)                                                       // RWW-V
#define SATA0_AHCI_HBA_CYA_1_0_SYNC_ESC_IN_ALPM_SHIFT       _MK_SHIFT_CONST(5)                                                              // RWWVF
#define SATA0_AHCI_HBA_CYA_1_0_SYNC_ESC_IN_ALPM_FIELD      (_MK_SHIFT_CONST(0x1) << SATA0_AHCI_HBA_CYA_1_0_SYNC_ESC_IN_ALPM_SHIFT)
#define SATA0_AHCI_HBA_CYA_1_0_SYNC_ESC_IN_ALPM_RANGE      5:5
#define SATA0_AHCI_HBA_CYA_1_0_SYNC_ESC_IN_ALPM_WOFFSET    0
#define SATA0_AHCI_HBA_CYA_1_0_SYNC_ESC_IN_ALPM_DEFAULT    (_MK_MASK_CONST(0x00000000)
#define SATA0_AHCI_HBA_CYA_1_0_SYNC_ESC_IN_ALPM_DEFAULT_MASK (_MK_MASK_CONST(0x1)
#define SATA0_AHCI_HBA_CYA_1_0_SYNC_ESC_IN_ALPM_SW_DEFAULT (_MK_MASK_CONST(0x00000000)
#define SATA0_AHCI_HBA_CYA_1_0_SYNC_ESC_IN_ALPM_SW_DEFAULT_MASK (_MK_MASK_CONST(0x1)
#define SATA0_AHCI_HBA_CYA_1_0_SYNC_ESC_IN_ALPM_INIT       _MK_ENUM_CONST(0x00000000)                                                       // RWW-V
#define SATA0_AHCI_HBA_CYA_1_0_READ_OUT_BM_START_SHIFT      _MK_SHIFT_CONST(6)                                                              // RWWVF
#define SATA0_AHCI_HBA_CYA_1_0_READ_OUT_BM_START_FIELD     (_MK_SHIFT_CONST(0x1) << SATA0_AHCI_HBA_CYA_1_0_READ_OUT_BM_START_SHIFT)
#define SATA0_AHCI_HBA_CYA_1_0_READ_OUT_BM_START_RANGE     6:6
#define SATA0_AHCI_HBA_CYA_1_0_READ_OUT_BM_START_WOFFSET   0
#define SATA0_AHCI_HBA_CYA_1_0_READ_OUT_BM_START_DEFAULT   (_MK_MASK_CONST(0x00000001)
#define SATA0_AHCI_HBA_CYA_1_0_READ_OUT_BM_START_DEFAULT_MASK (_MK_MASK_CONST(0x1)
#define SATA0_AHCI_HBA_CYA_1_0_READ_OUT_BM_START_SW_DEFAULT (_MK_MASK_CONST(0x00000001)
#define SATA0_AHCI_HBA_CYA_1_0_READ_OUT_BM_START_SW_DEFAULT_MASK (_MK_MASK_CONST(0x1)
#define SATA0_AHCI_HBA_CYA_1_0_READ_OUT_BM_START_INIT      _MK_ENUM_CONST(0x00000001)                                                       // RWW-V
#define SATA0_AHCI_HBA_CYA_1_0_INTR_PENDING_ON_CH_SEL_SHIFT  _MK_SHIFT_CONST(7)                                                              // RWWVF
#define SATA0_AHCI_HBA_CYA_1_0_INTR_PENDING_ON_CH_SEL_FIELD (_MK_SHIFT_CONST(0x1) << SATA0_AHCI_HBA_CYA_1_0_INTR_PENDING_ON_CH_SEL_SHIFT)
#define SATA0_AHCI_HBA_CYA_1_0_INTR_PENDING_ON_CH_SEL_RANGE 7:7
#define SATA0_AHCI_HBA_CYA_1_0_INTR_PENDING_ON_CH_SEL_WOFFSET 0
#define SATA0_AHCI_HBA_CYA_1_0_INTR_PENDING_ON_CH_SEL_DEFAULT (_MK_MASK_CONST(0x00000001)
#define SATA0_AHCI_HBA_CYA_1_0_INTR_PENDING_ON_CH_SEL_DEFAULT_MASK (_MK_MASK_CONST(0x1)
#define SATA0_AHCI_HBA_CYA_1_0_INTR_PENDING_ON_CH_SEL_SW_DEFAULT (_MK_MASK_CONST(0x00000001)
#define SATA0_AHCI_HBA_CYA_1_0_INTR_PENDING_ON_CH_SEL_SW_DEFAULT_MASK (_MK_MASK_CONST(0x1)
#define SATA0_AHCI_HBA_CYA_1_0_INTR_PENDING_ON_CH_SEL_INIT _MK_ENUM_CONST(0x00000001)                                                       // RWW-V
#define SATA0_AHCI_HBA_CYA_1_0_ISSUE_ORDER_CMD_SEL_IN_CBS_SHIFT  _MK_SHIFT_CONST(8)                                                              // RWWVF
#define SATA0_AHCI_HBA_CYA_1_0_ISSUE_ORDER_CMD_SEL_IN_CBS_FIELD (_MK_SHIFT_CONST(0x1) << SATA0_AHCI_HBA_CYA_1_0_ISSUE_ORDER_CMD_SEL_IN_CBS_SHIFT)
#define SATA0_AHCI_HBA_CYA_1_0_ISSUE_ORDER_CMD_SEL_IN_CBS_RANGE 8:8
#define SATA0_AHCI_HBA_CYA_1_0_ISSUE_ORDER_CMD_SEL_IN_CBS_WOFFSET 0
#define SATA0_AHCI_HBA_CYA_1_0_ISSUE_ORDER_CMD_SEL_IN_CBS_DEFAULT (_MK_MASK_CONST(0x00000000)
#define SATA0_AHCI_HBA_CYA_1_0_ISSUE_ORDER_CMD_SEL_IN_CBS_DEFAULT_MASK (_MK_MASK_CONST(0x1)
#define SATA0_AHCI_HBA_CYA_1_0_ISSUE_ORDER_CMD_SEL_IN_CBS_SW_DEFAULT (_MK_MASK_CONST(0x00000000)
#define SATA0_AHCI_HBA_CYA_1_0_ISSUE_ORDER_CMD_SEL_IN_CBS_SW_DEFAULT_MASK (_MK_MASK_CONST(0x1)
#define SATA0_AHCI_HBA_CYA_1_0_ISSUE_ORDER_CMD_SEL_IN_CBS_INIT _MK_ENUM_CONST(0x00000000)                                                       // RWW-V
#define SATA0_AHCI_HBA_CYA_1_0_DISABLE_BKGD_CMD_PREFETCH_2_SHIFT  _MK_SHIFT_CONST(9)                                                              // RWWVF
#define SATA0_AHCI_HBA_CYA_1_0_DISABLE_BKGD_CMD_PREFETCH_2_FIELD (_MK_SHIFT_CONST(0x1) << SATA0_AHCI_HBA_CYA_1_0_DISABLE_BKGD_CMD_PREFETCH_2_SHIFT)
#define SATA0_AHCI_HBA_CYA_1_0_DISABLE_BKGD_CMD_PREFETCH_2_RANGE 9:9
#define SATA0_AHCI_HBA_CYA_1_0_DISABLE_BKGD_CMD_PREFETCH_2_WOFFSET 0
#define SATA0_AHCI_HBA_CYA_1_0_DISABLE_BKGD_CMD_PREFETCH_2_DEFAULT (_MK_MASK_CONST(0x00000000)
#define SATA0_AHCI_HBA_CYA_1_0_DISABLE_BKGD_CMD_PREFETCH_2_DEFAULT_MASK (_MK_MASK_CONST(0x1)
#define SATA0_AHCI_HBA_CYA_1_0_DISABLE_BKGD_CMD_PREFETCH_2_SW_DEFAULT (_MK_MASK_CONST(0x00000000)
#define SATA0_AHCI_HBA_CYA_1_0_DISABLE_BKGD_CMD_PREFETCH_2_SW_DEFAULT_MASK (_MK_MASK_CONST(0x1)
#define SATA0_AHCI_HBA_CYA_1_0_DISABLE_BKGD_CMD_PREFETCH_2_INIT _MK_ENUM_CONST(0x00000000)                                                       // RWW-V
#define SATA0_AHCI_HBA_CYA_1_0_WAR_NDR_ACCEPT_ARC1_ISSUE_SHIFT  _MK_SHIFT_CONST(10)                                                             // RWWVF
#define SATA0_AHCI_HBA_CYA_1_0_WAR_NDR_ACCEPT_ARC1_ISSUE_FIELD (_MK_SHIFT_CONST(0x1) << SATA0_AHCI_HBA_CYA_1_0_WAR_NDR_ACCEPT_ARC1_ISSUE_SHIFT)
#define SATA0_AHCI_HBA_CYA_1_0_WAR_NDR_ACCEPT_ARC1_ISSUE_RANGE 10:10
#define SATA0_AHCI_HBA_CYA_1_0_WAR_NDR_ACCEPT_ARC1_ISSUE_WOFFSET 0
#define SATA0_AHCI_HBA_CYA_1_0_WAR_NDR_ACCEPT_ARC1_ISSUE_DEFAULT (_MK_MASK_CONST(0x00000001)
#define SATA0_AHCI_HBA_CYA_1_0_WAR_NDR_ACCEPT_ARC1_ISSUE_DEFAULT_MASK (_MK_MASK_CONST(0x1)
#define SATA0_AHCI_HBA_CYA_1_0_WAR_NDR_ACCEPT_ARC1_ISSUE_SW_DEFAULT (_MK_MASK_CONST(0x00000001)
#define SATA0_AHCI_HBA_CYA_1_0_WAR_NDR_ACCEPT_ARC1_ISSUE_SW_DEFAULT_MASK (_MK_MASK_CONST(0x1)
#define SATA0_AHCI_HBA_CYA_1_0_WAR_NDR_ACCEPT_ARC1_ISSUE_INIT _MK_ENUM_CONST(0x00000001)                                                       // RWW-V
#define SATA0_AHCI_HBA_CYA_1_0_ARB_REVERT_TO_OLD_BHVR_SHIFT  _MK_SHIFT_CONST(11)                                                             // RWWVF
#define SATA0_AHCI_HBA_CYA_1_0_ARB_REVERT_TO_OLD_BHVR_FIELD (_MK_SHIFT_CONST(0x1) << SATA0_AHCI_HBA_CYA_1_0_ARB_REVERT_TO_OLD_BHVR_SHIFT)
#define SATA0_AHCI_HBA_CYA_1_0_ARB_REVERT_TO_OLD_BHVR_RANGE 11:11
#define SATA0_AHCI_HBA_CYA_1_0_ARB_REVERT_TO_OLD_BHVR_WOFFSET 0
#define SATA0_AHCI_HBA_CYA_1_0_ARB_REVERT_TO_OLD_BHVR_DEFAULT (_MK_MASK_CONST(0x00000000)
#define SATA0_AHCI_HBA_CYA_1_0_ARB_REVERT_TO_OLD_BHVR_DEFAULT_MASK (_MK_MASK_CONST(0x1)
#define SATA0_AHCI_HBA_CYA_1_0_ARB_REVERT_TO_OLD_BHVR_SW_DEFAULT (_MK_MASK_CONST(0x00000000)
#define SATA0_AHCI_HBA_CYA_1_0_ARB_REVERT_TO_OLD_BHVR_SW_DEFAULT_MASK (_MK_MASK_CONST(0x1)
#define SATA0_AHCI_HBA_CYA_1_0_ARB_REVERT_TO_OLD_BHVR_INIT _MK_ENUM_CONST(0x00000000)                                                       // RWW-V
#define SATA0_AHCI_HBA_CYA_1_0_ARB_PARK_MODE_SHIFT          _MK_SHIFT_CONST(12)                                                             // RWWVF
#define SATA0_AHCI_HBA_CYA_1_0_ARB_PARK_MODE_FIELD         (_MK_SHIFT_CONST(0x3) << SATA0_AHCI_HBA_CYA_1_0_ARB_PARK_MODE_SHIFT)
#define SATA0_AHCI_HBA_CYA_1_0_ARB_PARK_MODE_RANGE         13:12
#define SATA0_AHCI_HBA_CYA_1_0_ARB_PARK_MODE_WOFFSET       0
#define SATA0_AHCI_HBA_CYA_1_0_ARB_PARK_MODE_DEFAULT       (_MK_MASK_CONST(0x00000001)
#define SATA0_AHCI_HBA_CYA_1_0_ARB_PARK_MODE_DEFAULT_MASK  (_MK_MASK_CONST(0x3)
#define SATA0_AHCI_HBA_CYA_1_0_ARB_PARK_MODE_SW_DEFAULT    (_MK_MASK_CONST(0x00000001)
#define SATA0_AHCI_HBA_CYA_1_0_ARB_PARK_MODE_SW_DEFAULT_MASK (_MK_MASK_CONST(0x3)
#define SATA0_AHCI_HBA_CYA_1_0_ARB_PARK_MODE_LAST_GNTED    _MK_ENUM_CONST(0x00000001)                                                       // RWW-V
#define SATA0_AHCI_HBA_CYA_1_0_ARB_PARK_MODE_PORT0         _MK_ENUM_CONST(0x00000000)                                                       // ----V
#define SATA0_AHCI_HBA_CYA_1_0_NO_PRDBC_UPDATE_SHIFT        _MK_SHIFT_CONST(14)                                                             // RWWVF
#define SATA0_AHCI_HBA_CYA_1_0_NO_PRDBC_UPDATE_FIELD       (_MK_SHIFT_CONST(0x1) << SATA0_AHCI_HBA_CYA_1_0_NO_PRDBC_UPDATE_SHIFT)
#define SATA0_AHCI_HBA_CYA_1_0_NO_PRDBC_UPDATE_RANGE       14:14
#define SATA0_AHCI_HBA_CYA_1_0_NO_PRDBC_UPDATE_WOFFSET     0
#define SATA0_AHCI_HBA_CYA_1_0_NO_PRDBC_UPDATE_DEFAULT     (_MK_MASK_CONST(0x00000000)
#define SATA0_AHCI_HBA_CYA_1_0_NO_PRDBC_UPDATE_DEFAULT_MASK (_MK_MASK_CONST(0x1)
#define SATA0_AHCI_HBA_CYA_1_0_NO_PRDBC_UPDATE_SW_DEFAULT  (_MK_MASK_CONST(0x00000000)
#define SATA0_AHCI_HBA_CYA_1_0_NO_PRDBC_UPDATE_SW_DEFAULT_MASK (_MK_MASK_CONST(0x1)
#define SATA0_AHCI_HBA_CYA_1_0_NO_PRDBC_UPDATE_INIT        _MK_ENUM_CONST(0x00000000)                                                       // RWW-V
#define SATA0_AHCI_HBA_CYA_1_0_DETECT_B2B_NCQ_TAG_REPEAT_SHIFT  _MK_SHIFT_CONST(15)                                                             // RWWVF
#define SATA0_AHCI_HBA_CYA_1_0_DETECT_B2B_NCQ_TAG_REPEAT_FIELD (_MK_SHIFT_CONST(0x1) << SATA0_AHCI_HBA_CYA_1_0_DETECT_B2B_NCQ_TAG_REPEAT_SHIFT)
#define SATA0_AHCI_HBA_CYA_1_0_DETECT_B2B_NCQ_TAG_REPEAT_RANGE 15:15
#define SATA0_AHCI_HBA_CYA_1_0_DETECT_B2B_NCQ_TAG_REPEAT_WOFFSET 0
#define SATA0_AHCI_HBA_CYA_1_0_DETECT_B2B_NCQ_TAG_REPEAT_DEFAULT (_MK_MASK_CONST(0x00000001)
#define SATA0_AHCI_HBA_CYA_1_0_DETECT_B2B_NCQ_TAG_REPEAT_DEFAULT_MASK (_MK_MASK_CONST(0x1)
#define SATA0_AHCI_HBA_CYA_1_0_DETECT_B2B_NCQ_TAG_REPEAT_SW_DEFAULT (_MK_MASK_CONST(0x00000001)
#define SATA0_AHCI_HBA_CYA_1_0_DETECT_B2B_NCQ_TAG_REPEAT_SW_DEFAULT_MASK (_MK_MASK_CONST(0x1)
#define SATA0_AHCI_HBA_CYA_1_0_DETECT_B2B_NCQ_TAG_REPEAT_INIT _MK_ENUM_CONST(0x00000001)                                                       // RWW-V
#define SATA0_AHCI_HBA_CYA_1_0_FIS_SM_USE_RISEDGE_EOF_SHIFT  _MK_SHIFT_CONST(16)                                                             // RWWVF
#define SATA0_AHCI_HBA_CYA_1_0_FIS_SM_USE_RISEDGE_EOF_FIELD (_MK_SHIFT_CONST(0x1) << SATA0_AHCI_HBA_CYA_1_0_FIS_SM_USE_RISEDGE_EOF_SHIFT)
#define SATA0_AHCI_HBA_CYA_1_0_FIS_SM_USE_RISEDGE_EOF_RANGE 16:16
#define SATA0_AHCI_HBA_CYA_1_0_FIS_SM_USE_RISEDGE_EOF_WOFFSET 0
#define SATA0_AHCI_HBA_CYA_1_0_FIS_SM_USE_RISEDGE_EOF_DEFAULT (_MK_MASK_CONST(0x00000001)
#define SATA0_AHCI_HBA_CYA_1_0_FIS_SM_USE_RISEDGE_EOF_DEFAULT_MASK (_MK_MASK_CONST(0x1)
#define SATA0_AHCI_HBA_CYA_1_0_FIS_SM_USE_RISEDGE_EOF_SW_DEFAULT (_MK_MASK_CONST(0x00000001)
#define SATA0_AHCI_HBA_CYA_1_0_FIS_SM_USE_RISEDGE_EOF_SW_DEFAULT_MASK (_MK_MASK_CONST(0x1)
#define SATA0_AHCI_HBA_CYA_1_0_FIS_SM_USE_RISEDGE_EOF_INIT _MK_ENUM_CONST(0x00000001)                                                       // RWW-V
#define SATA0_AHCI_HBA_CYA_1_0_SEND_DATA_HDR_EARLY_SHIFT    _MK_SHIFT_CONST(17)                                                             // RWWVF
#define SATA0_AHCI_HBA_CYA_1_0_SEND_DATA_HDR_EARLY_FIELD   (_MK_SHIFT_CONST(0x1) << SATA0_AHCI_HBA_CYA_1_0_SEND_DATA_HDR_EARLY_SHIFT)
#define SATA0_AHCI_HBA_CYA_1_0_SEND_DATA_HDR_EARLY_RANGE   17:17
#define SATA0_AHCI_HBA_CYA_1_0_SEND_DATA_HDR_EARLY_WOFFSET 0
#define SATA0_AHCI_HBA_CYA_1_0_SEND_DATA_HDR_EARLY_DEFAULT (_MK_MASK_CONST(0x00000000)
#define SATA0_AHCI_HBA_CYA_1_0_SEND_DATA_HDR_EARLY_DEFAULT_MASK (_MK_MASK_CONST(0x1)
#define SATA0_AHCI_HBA_CYA_1_0_SEND_DATA_HDR_EARLY_SW_DEFAULT (_MK_MASK_CONST(0x00000000)
#define SATA0_AHCI_HBA_CYA_1_0_SEND_DATA_HDR_EARLY_SW_DEFAULT_MASK (_MK_MASK_CONST(0x1)
#define SATA0_AHCI_HBA_CYA_1_0_SEND_DATA_HDR_EARLY_INIT    _MK_ENUM_CONST(0x00000000)                                                       // RWW-V
#define SATA0_AHCI_HBA_CYA_1_0_GOTO_PM_AGGR_FROM_P_IDLE_SHIFT  _MK_SHIFT_CONST(18)                                                             // RWWVF
#define SATA0_AHCI_HBA_CYA_1_0_GOTO_PM_AGGR_FROM_P_IDLE_FIELD (_MK_SHIFT_CONST(0x1) << SATA0_AHCI_HBA_CYA_1_0_GOTO_PM_AGGR_FROM_P_IDLE_SHIFT)
#define SATA0_AHCI_HBA_CYA_1_0_GOTO_PM_AGGR_FROM_P_IDLE_RANGE 18:18
#define SATA0_AHCI_HBA_CYA_1_0_GOTO_PM_AGGR_FROM_P_IDLE_WOFFSET 0
#define SATA0_AHCI_HBA_CYA_1_0_GOTO_PM_AGGR_FROM_P_IDLE_DEFAULT (_MK_MASK_CONST(0x00000000)
#define SATA0_AHCI_HBA_CYA_1_0_GOTO_PM_AGGR_FROM_P_IDLE_DEFAULT_MASK (_MK_MASK_CONST(0x1)
#define SATA0_AHCI_HBA_CYA_1_0_GOTO_PM_AGGR_FROM_P_IDLE_SW_DEFAULT (_MK_MASK_CONST(0x00000000)
#define SATA0_AHCI_HBA_CYA_1_0_GOTO_PM_AGGR_FROM_P_IDLE_SW_DEFAULT_MASK (_MK_MASK_CONST(0x1)
#define SATA0_AHCI_HBA_CYA_1_0_GOTO_PM_AGGR_FROM_P_IDLE_YES _MK_ENUM_CONST(0x00000001)                                                       // RW--V
#define SATA0_AHCI_HBA_CYA_1_0_GOTO_PM_AGGR_FROM_P_IDLE_NO _MK_ENUM_CONST(0x00000000)                                                       // RWW-V
#define SATA0_AHCI_HBA_CYA_1_0_PRD_SM_RXDATA_PREMATURE_END_SHIFT  _MK_SHIFT_CONST(19)                                                             // RWWVF
#define SATA0_AHCI_HBA_CYA_1_0_PRD_SM_RXDATA_PREMATURE_END_FIELD (_MK_SHIFT_CONST(0x1) << SATA0_AHCI_HBA_CYA_1_0_PRD_SM_RXDATA_PREMATURE_END_SHIFT)
#define SATA0_AHCI_HBA_CYA_1_0_PRD_SM_RXDATA_PREMATURE_END_RANGE 19:19
#define SATA0_AHCI_HBA_CYA_1_0_PRD_SM_RXDATA_PREMATURE_END_WOFFSET 0
#define SATA0_AHCI_HBA_CYA_1_0_PRD_SM_RXDATA_PREMATURE_END_DEFAULT (_MK_MASK_CONST(0x00000001)
#define SATA0_AHCI_HBA_CYA_1_0_PRD_SM_RXDATA_PREMATURE_END_DEFAULT_MASK (_MK_MASK_CONST(0x1)
#define SATA0_AHCI_HBA_CYA_1_0_PRD_SM_RXDATA_PREMATURE_END_SW_DEFAULT (_MK_MASK_CONST(0x00000001)
#define SATA0_AHCI_HBA_CYA_1_0_PRD_SM_RXDATA_PREMATURE_END_SW_DEFAULT_MASK (_MK_MASK_CONST(0x1)
#define SATA0_AHCI_HBA_CYA_1_0_PRD_SM_RXDATA_PREMATURE_END_INIT _MK_ENUM_CONST(0x00000001)                                                       // RWW-V
#define SATA0_AHCI_HBA_CYA_1_0_BM_HOLD_ACTV_TILL_INTR_SHIFT  _MK_SHIFT_CONST(20)                                                             // RWWVF
#define SATA0_AHCI_HBA_CYA_1_0_BM_HOLD_ACTV_TILL_INTR_FIELD (_MK_SHIFT_CONST(0x1) << SATA0_AHCI_HBA_CYA_1_0_BM_HOLD_ACTV_TILL_INTR_SHIFT)
#define SATA0_AHCI_HBA_CYA_1_0_BM_HOLD_ACTV_TILL_INTR_RANGE 20:20
#define SATA0_AHCI_HBA_CYA_1_0_BM_HOLD_ACTV_TILL_INTR_WOFFSET 0
#define SATA0_AHCI_HBA_CYA_1_0_BM_HOLD_ACTV_TILL_INTR_DEFAULT (_MK_MASK_CONST(0x00000000)
#define SATA0_AHCI_HBA_CYA_1_0_BM_HOLD_ACTV_TILL_INTR_DEFAULT_MASK (_MK_MASK_CONST(0x1)
#define SATA0_AHCI_HBA_CYA_1_0_BM_HOLD_ACTV_TILL_INTR_SW_DEFAULT (_MK_MASK_CONST(0x00000000)
#define SATA0_AHCI_HBA_CYA_1_0_BM_HOLD_ACTV_TILL_INTR_SW_DEFAULT_MASK (_MK_MASK_CONST(0x1)
#define SATA0_AHCI_HBA_CYA_1_0_BM_HOLD_ACTV_TILL_INTR_INIT _MK_ENUM_CONST(0x00000000)                                                       // RWW-V
#define SATA0_AHCI_HBA_CYA_1_0_NON_NCQ_IFS_TEMP_OFF_SHIFT   _MK_SHIFT_CONST(21)                                                             // RWWVF
#define SATA0_AHCI_HBA_CYA_1_0_NON_NCQ_IFS_TEMP_OFF_FIELD  (_MK_SHIFT_CONST(0x1) << SATA0_AHCI_HBA_CYA_1_0_NON_NCQ_IFS_TEMP_OFF_SHIFT)
#define SATA0_AHCI_HBA_CYA_1_0_NON_NCQ_IFS_TEMP_OFF_RANGE  21:21
#define SATA0_AHCI_HBA_CYA_1_0_NON_NCQ_IFS_TEMP_OFF_WOFFSET 0
#define SATA0_AHCI_HBA_CYA_1_0_NON_NCQ_IFS_TEMP_OFF_DEFAULT (_MK_MASK_CONST(0x00000001)
#define SATA0_AHCI_HBA_CYA_1_0_NON_NCQ_IFS_TEMP_OFF_DEFAULT_MASK (_MK_MASK_CONST(0x1)
#define SATA0_AHCI_HBA_CYA_1_0_NON_NCQ_IFS_TEMP_OFF_SW_DEFAULT (_MK_MASK_CONST(0x00000001)
#define SATA0_AHCI_HBA_CYA_1_0_NON_NCQ_IFS_TEMP_OFF_SW_DEFAULT_MASK (_MK_MASK_CONST(0x1)
#define SATA0_AHCI_HBA_CYA_1_0_NON_NCQ_IFS_TEMP_OFF_INIT   _MK_ENUM_CONST(0x00000001)                                                       // RWW-V
#define SATA0_AHCI_HBA_CYA_1_0_FETCH_REQ_TAKEN_SHIFT        _MK_SHIFT_CONST(22)                                                             // RWWVF
#define SATA0_AHCI_HBA_CYA_1_0_FETCH_REQ_TAKEN_FIELD       (_MK_SHIFT_CONST(0x3) << SATA0_AHCI_HBA_CYA_1_0_FETCH_REQ_TAKEN_SHIFT)
#define SATA0_AHCI_HBA_CYA_1_0_FETCH_REQ_TAKEN_RANGE       23:22
#define SATA0_AHCI_HBA_CYA_1_0_FETCH_REQ_TAKEN_WOFFSET     0
#define SATA0_AHCI_HBA_CYA_1_0_FETCH_REQ_TAKEN_DEFAULT     (_MK_MASK_CONST(0x00000000)
#define SATA0_AHCI_HBA_CYA_1_0_FETCH_REQ_TAKEN_DEFAULT_MASK (_MK_MASK_CONST(0x3)
#define SATA0_AHCI_HBA_CYA_1_0_FETCH_REQ_TAKEN_SW_DEFAULT  (_MK_MASK_CONST(0x00000000)
#define SATA0_AHCI_HBA_CYA_1_0_FETCH_REQ_TAKEN_SW_DEFAULT_MASK (_MK_MASK_CONST(0x3)
#define SATA0_AHCI_HBA_CYA_1_0_FETCH_REQ_TAKEN_INIT        _MK_ENUM_CONST(0x00000000)                                                       // RWW-V
#define SATA0_AHCI_HBA_CYA_1_0_SKIP_SCTL_DET_WR_OFFLINE_SHIFT  _MK_SHIFT_CONST(24)                                                             // RWCVF
#define SATA0_AHCI_HBA_CYA_1_0_SKIP_SCTL_DET_WR_OFFLINE_FIELD (_MK_SHIFT_CONST(0x1) << SATA0_AHCI_HBA_CYA_1_0_SKIP_SCTL_DET_WR_OFFLINE_SHIFT)
#define SATA0_AHCI_HBA_CYA_1_0_SKIP_SCTL_DET_WR_OFFLINE_RANGE 24:24
#define SATA0_AHCI_HBA_CYA_1_0_SKIP_SCTL_DET_WR_OFFLINE_WOFFSET 0
#define SATA0_AHCI_HBA_CYA_1_0_SKIP_SCTL_DET_WR_OFFLINE_INIT _MK_ENUM_CONST(0x00000001)                                                       // RWC-V
#define SATA0_AHCI_HBA_CYA_1_0_ALWAYS_DENY_PMREQ_SHIFT      _MK_SHIFT_CONST(25)                                                             // RWWVF
#define SATA0_AHCI_HBA_CYA_1_0_ALWAYS_DENY_PMREQ_FIELD     (_MK_SHIFT_CONST(0x1) << SATA0_AHCI_HBA_CYA_1_0_ALWAYS_DENY_PMREQ_SHIFT)
#define SATA0_AHCI_HBA_CYA_1_0_ALWAYS_DENY_PMREQ_RANGE     25:25
#define SATA0_AHCI_HBA_CYA_1_0_ALWAYS_DENY_PMREQ_WOFFSET   0
#define SATA0_AHCI_HBA_CYA_1_0_ALWAYS_DENY_PMREQ_DEFAULT   (_MK_MASK_CONST(0x00000000)
#define SATA0_AHCI_HBA_CYA_1_0_ALWAYS_DENY_PMREQ_DEFAULT_MASK (_MK_MASK_CONST(0x1)
#define SATA0_AHCI_HBA_CYA_1_0_ALWAYS_DENY_PMREQ_SW_DEFAULT (_MK_MASK_CONST(0x00000000)
#define SATA0_AHCI_HBA_CYA_1_0_ALWAYS_DENY_PMREQ_SW_DEFAULT_MASK (_MK_MASK_CONST(0x1)
#define SATA0_AHCI_HBA_CYA_1_0_ALWAYS_DENY_PMREQ_INIT      _MK_ENUM_CONST(0x00000000)                                                       // RWW-V
#define SATA0_AHCI_HBA_CYA_1_0_SKIP_SCTL_DET_WR_COMRESET_SHIFT  _MK_SHIFT_CONST(26)                                                             // RWCVF
#define SATA0_AHCI_HBA_CYA_1_0_SKIP_SCTL_DET_WR_COMRESET_FIELD (_MK_SHIFT_CONST(0x1) << SATA0_AHCI_HBA_CYA_1_0_SKIP_SCTL_DET_WR_COMRESET_SHIFT)
#define SATA0_AHCI_HBA_CYA_1_0_SKIP_SCTL_DET_WR_COMRESET_RANGE 26:26
#define SATA0_AHCI_HBA_CYA_1_0_SKIP_SCTL_DET_WR_COMRESET_WOFFSET 0
#define SATA0_AHCI_HBA_CYA_1_0_SKIP_SCTL_DET_WR_COMRESET_INIT _MK_ENUM_CONST(0x00000000)                                                       // RWC-V
#define SATA0_AHCI_HBA_CYA_1_0_CHK_L_IDLE_IN_LOW_POWER_SHIFT  _MK_SHIFT_CONST(27)                                                             // RWWVF
#define SATA0_AHCI_HBA_CYA_1_0_CHK_L_IDLE_IN_LOW_POWER_FIELD (_MK_SHIFT_CONST(0x1) << SATA0_AHCI_HBA_CYA_1_0_CHK_L_IDLE_IN_LOW_POWER_SHIFT)
#define SATA0_AHCI_HBA_CYA_1_0_CHK_L_IDLE_IN_LOW_POWER_RANGE 27:27
#define SATA0_AHCI_HBA_CYA_1_0_CHK_L_IDLE_IN_LOW_POWER_WOFFSET 0
#define SATA0_AHCI_HBA_CYA_1_0_CHK_L_IDLE_IN_LOW_POWER_DEFAULT (_MK_MASK_CONST(0x00000000)
#define SATA0_AHCI_HBA_CYA_1_0_CHK_L_IDLE_IN_LOW_POWER_DEFAULT_MASK (_MK_MASK_CONST(0x1)
#define SATA0_AHCI_HBA_CYA_1_0_CHK_L_IDLE_IN_LOW_POWER_SW_DEFAULT (_MK_MASK_CONST(0x00000000)
#define SATA0_AHCI_HBA_CYA_1_0_CHK_L_IDLE_IN_LOW_POWER_SW_DEFAULT_MASK (_MK_MASK_CONST(0x1)
#define SATA0_AHCI_HBA_CYA_1_0_CHK_L_IDLE_IN_LOW_POWER_INIT _MK_ENUM_CONST(0x00000000)                                                       // RWW-V
#define SATA0_AHCI_HBA_CYA_1_0_CHK_L_IDLE_IN_WAKE_LINK_SHIFT  _MK_SHIFT_CONST(28)                                                             // RWWVF
#define SATA0_AHCI_HBA_CYA_1_0_CHK_L_IDLE_IN_WAKE_LINK_FIELD (_MK_SHIFT_CONST(0x1) << SATA0_AHCI_HBA_CYA_1_0_CHK_L_IDLE_IN_WAKE_LINK_SHIFT)
#define SATA0_AHCI_HBA_CYA_1_0_CHK_L_IDLE_IN_WAKE_LINK_RANGE 28:28
#define SATA0_AHCI_HBA_CYA_1_0_CHK_L_IDLE_IN_WAKE_LINK_WOFFSET 0
#define SATA0_AHCI_HBA_CYA_1_0_CHK_L_IDLE_IN_WAKE_LINK_DEFAULT (_MK_MASK_CONST(0x00000000)
#define SATA0_AHCI_HBA_CYA_1_0_CHK_L_IDLE_IN_WAKE_LINK_DEFAULT_MASK (_MK_MASK_CONST(0x1)
#define SATA0_AHCI_HBA_CYA_1_0_CHK_L_IDLE_IN_WAKE_LINK_SW_DEFAULT (_MK_MASK_CONST(0x00000000)
#define SATA0_AHCI_HBA_CYA_1_0_CHK_L_IDLE_IN_WAKE_LINK_SW_DEFAULT_MASK (_MK_MASK_CONST(0x1)
#define SATA0_AHCI_HBA_CYA_1_0_CHK_L_IDLE_IN_WAKE_LINK_INIT _MK_ENUM_CONST(0x00000000)                                                       // RWW-V
#define SATA0_AHCI_HBA_CYA_1_0_PREFETCH_TX_DATA_REVERT_FIX_SHIFT  _MK_SHIFT_CONST(29)                                                             // RWWVF
#define SATA0_AHCI_HBA_CYA_1_0_PREFETCH_TX_DATA_REVERT_FIX_FIELD (_MK_SHIFT_CONST(0x1) << SATA0_AHCI_HBA_CYA_1_0_PREFETCH_TX_DATA_REVERT_FIX_SHIFT)
#define SATA0_AHCI_HBA_CYA_1_0_PREFETCH_TX_DATA_REVERT_FIX_RANGE 29:29
#define SATA0_AHCI_HBA_CYA_1_0_PREFETCH_TX_DATA_REVERT_FIX_WOFFSET 0
#define SATA0_AHCI_HBA_CYA_1_0_PREFETCH_TX_DATA_REVERT_FIX_DEFAULT (_MK_MASK_CONST(0x00000000)
#define SATA0_AHCI_HBA_CYA_1_0_PREFETCH_TX_DATA_REVERT_FIX_DEFAULT_MASK (_MK_MASK_CONST(0x1)
#define SATA0_AHCI_HBA_CYA_1_0_PREFETCH_TX_DATA_REVERT_FIX_SW_DEFAULT (_MK_MASK_CONST(0x00000000)
#define SATA0_AHCI_HBA_CYA_1_0_PREFETCH_TX_DATA_REVERT_FIX_SW_DEFAULT_MASK (_MK_MASK_CONST(0x1)
#define SATA0_AHCI_HBA_CYA_1_0_PREFETCH_TX_DATA_REVERT_FIX_INIT _MK_ENUM_CONST(0x00000000)                                                       // RWW-V
#define SATA0_AHCI_HBA_CYA_1_0_INVALIDATE_PRDS_AT_FETCH_SHIFT  _MK_SHIFT_CONST(30)                                                             // RWWVF
#define SATA0_AHCI_HBA_CYA_1_0_INVALIDATE_PRDS_AT_FETCH_FIELD (_MK_SHIFT_CONST(0x1) << SATA0_AHCI_HBA_CYA_1_0_INVALIDATE_PRDS_AT_FETCH_SHIFT)
#define SATA0_AHCI_HBA_CYA_1_0_INVALIDATE_PRDS_AT_FETCH_RANGE 30:30
#define SATA0_AHCI_HBA_CYA_1_0_INVALIDATE_PRDS_AT_FETCH_WOFFSET 0
#define SATA0_AHCI_HBA_CYA_1_0_INVALIDATE_PRDS_AT_FETCH_DEFAULT (_MK_MASK_CONST(0x00000001)
#define SATA0_AHCI_HBA_CYA_1_0_INVALIDATE_PRDS_AT_FETCH_DEFAULT_MASK (_MK_MASK_CONST(0x1)
#define SATA0_AHCI_HBA_CYA_1_0_INVALIDATE_PRDS_AT_FETCH_SW_DEFAULT (_MK_MASK_CONST(0x00000001)
#define SATA0_AHCI_HBA_CYA_1_0_INVALIDATE_PRDS_AT_FETCH_SW_DEFAULT_MASK (_MK_MASK_CONST(0x1)
#define SATA0_AHCI_HBA_CYA_1_0_INVALIDATE_PRDS_AT_FETCH_INIT _MK_ENUM_CONST(0x00000001)                                                       // RWW-V
#define SATA0_AHCI_HBA_CYA_1_0_UNCLAMP_HBA_CTRLR_SHIFT      _MK_SHIFT_CONST(31)                                                             // RWWVF
#define SATA0_AHCI_HBA_CYA_1_0_UNCLAMP_HBA_CTRLR_FIELD     (_MK_SHIFT_CONST(0x1) << SATA0_AHCI_HBA_CYA_1_0_UNCLAMP_HBA_CTRLR_SHIFT)
#define SATA0_AHCI_HBA_CYA_1_0_UNCLAMP_HBA_CTRLR_RANGE     31:31
#define SATA0_AHCI_HBA_CYA_1_0_UNCLAMP_HBA_CTRLR_WOFFSET   0
#define SATA0_AHCI_HBA_CYA_1_0_UNCLAMP_HBA_CTRLR_DEFAULT   (_MK_MASK_CONST(0x00000001)
#define SATA0_AHCI_HBA_CYA_1_0_UNCLAMP_HBA_CTRLR_DEFAULT_MASK (_MK_MASK_CONST(0x1)
#define SATA0_AHCI_HBA_CYA_1_0_UNCLAMP_HBA_CTRLR_SW_DEFAULT (_MK_MASK_CONST(0x00000001)
#define SATA0_AHCI_HBA_CYA_1_0_UNCLAMP_HBA_CTRLR_SW_DEFAULT_MASK (_MK_MASK_CONST(0x1)
#define SATA0_AHCI_HBA_CYA_1_0_UNCLAMP_HBA_CTRLR_INIT      _MK_ENUM_CONST(0x00000001)                                                       // RWW-V
// .define T_SATA0_AHCI_HBA_CTL_1                                            0x00000338 /* RW-4R */
// 
// .define T_SATA0_AHCI_HBA_CYA_1_ARB_GNT_CFG                                     11:11 /* RWWVF */
// .define T_SATA0_AHCI_HBA_CYA_1_ARB_GNT_CFG_INIT                           0x00000000 /* RWW-V */
// .define T_SATA0_AHCI_HBA_CYA_1_PREFETCH_TX_DATA_NO_DELAY                       29:29 /* RWWVF */
// .define T_SATA0_AHCI_HBA_CYA_1_PREFETCH_TX_DATA_NO_DELAY_INIT             0x00000000 /* RWW-V */
// 
// 
// .LABEL PUBLIC
// 
// .LABEL PRIVATE INT_REL
// .TITLE HBA_PI_BKDR
// 
// 31                                              7             0
// .-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-.
// |0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0| HBA_PI_BKDR
// `-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-'
// 
#define SATA0_AHCI_HBA_PI_BKDR_0                           0x0000033C                                                                       // RW-4R
#define SATA0_AHCI_HBA_PI_BKDR_0_SECURE                    0
#define SATA0_AHCI_HBA_PI_BKDR_0_WORD_COUNT                1
#define SATA0_AHCI_HBA_PI_BKDR_0_RESET_VAL                 0x0
#define SATA0_AHCI_HBA_PI_BKDR_0_RESET_MASK                0x0
#define SATA0_AHCI_HBA_PI_BKDR_0_SW_DEFAULT_VAL            0x0
#define SATA0_AHCI_HBA_PI_BKDR_0_SW_DEFAULT_MASK           0x0
#define SATA0_AHCI_HBA_PI_BKDR_0_READ_MASK                 0xffffffff
#define SATA0_AHCI_HBA_PI_BKDR_0_WRITE_MASK                0xff
#define SATA0_AHCI_HBA_PI_BKDR_0_PORTS_IMPL_SHIFT           _MK_SHIFT_CONST(0)                                                              // RWCVF
#define SATA0_AHCI_HBA_PI_BKDR_0_PORTS_IMPL_FIELD          (_MK_SHIFT_CONST(0xff) << SATA0_AHCI_HBA_PI_BKDR_0_PORTS_IMPL_SHIFT)
#define SATA0_AHCI_HBA_PI_BKDR_0_PORTS_IMPL_RANGE          7:0
#define SATA0_AHCI_HBA_PI_BKDR_0_PORTS_IMPL_WOFFSET        0
#define SATA0_AHCI_HBA_PI_BKDR_0_PORTS_IMPL_ZERO           _MK_ENUM_CONST(0x00000000)                                                       // RW--V
#define SATA0_AHCI_HBA_PI_BKDR_0_PORTS_IMPL_TWO            _MK_ENUM_CONST(0x00000003)                                                       // RW--V
#define SATA0_AHCI_HBA_PI_BKDR_0_PORTS_IMPL_FOUR           _MK_ENUM_CONST(0x0000000F)                                                       // RW--V
#define SATA0_AHCI_HBA_PI_BKDR_0_31_8_RSVD_SHIFT            _MK_SHIFT_CONST(8)                                                              // C--VF
#define SATA0_AHCI_HBA_PI_BKDR_0_31_8_RSVD_FIELD           (_MK_SHIFT_CONST(0xffffff) << SATA0_AHCI_HBA_PI_BKDR_0_31_8_RSVD_SHIFT)
#define SATA0_AHCI_HBA_PI_BKDR_0_31_8_RSVD_RANGE           31:8
#define SATA0_AHCI_HBA_PI_BKDR_0_31_8_RSVD_WOFFSET         0
#define SATA0_AHCI_HBA_PI_BKDR_0_31_8_RSVD_ZERO            _MK_ENUM_CONST(0x00000000)                                                       // C---V
// 
// 
// .LABEL PUBLIC
// 
// .LABEL PRIVATE INT_REL
// .TITLE AHCI_HBA_PRE_STAGING_CONTROL
// 
// 
// 31           24 23           16 15            8 7             0
// .-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-.
// |0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0| PreStaging Control
// `-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-'
// 
#define SATA0_AHCI_HBA_PRE_STAGING_CONTROL_0               0x00000340                                                                       // RW-4R
#define SATA0_AHCI_HBA_PRE_STAGING_CONTROL_0_SECURE        0
#define SATA0_AHCI_HBA_PRE_STAGING_CONTROL_0_WORD_COUNT    1
#define SATA0_AHCI_HBA_PRE_STAGING_CONTROL_0_RESET_VAL     0x0
#define SATA0_AHCI_HBA_PRE_STAGING_CONTROL_0_RESET_MASK    0x0
#define SATA0_AHCI_HBA_PRE_STAGING_CONTROL_0_SW_DEFAULT_VAL 0x0
#define SATA0_AHCI_HBA_PRE_STAGING_CONTROL_0_SW_DEFAULT_MASK 0x0
#define SATA0_AHCI_HBA_PRE_STAGING_CONTROL_0_READ_MASK     0xfff3ffff
#define SATA0_AHCI_HBA_PRE_STAGING_CONTROL_0_WRITE_MASK    0xff03ffff
#define SATA0_AHCI_HBA_PRE_STAGING_CONTROL_0_PRDBC_SHIFT    _MK_SHIFT_CONST(0)                                                              // RWWVF
#define SATA0_AHCI_HBA_PRE_STAGING_CONTROL_0_PRDBC_FIELD   (_MK_SHIFT_CONST(0x3f) << SATA0_AHCI_HBA_PRE_STAGING_CONTROL_0_PRDBC_SHIFT)
#define SATA0_AHCI_HBA_PRE_STAGING_CONTROL_0_PRDBC_RANGE   5:0
#define SATA0_AHCI_HBA_PRE_STAGING_CONTROL_0_PRDBC_WOFFSET 0
#define SATA0_AHCI_HBA_PRE_STAGING_CONTROL_0_PRDBC_DEFAULT (_MK_MASK_CONST(0x00000014)
#define SATA0_AHCI_HBA_PRE_STAGING_CONTROL_0_PRDBC_DEFAULT_MASK (_MK_MASK_CONST(0x3f)
#define SATA0_AHCI_HBA_PRE_STAGING_CONTROL_0_PRDBC_SW_DEFAULT (_MK_MASK_CONST(0x00000014)
#define SATA0_AHCI_HBA_PRE_STAGING_CONTROL_0_PRDBC_SW_DEFAULT_MASK (_MK_MASK_CONST(0x3f)
#define SATA0_AHCI_HBA_PRE_STAGING_CONTROL_0_PRDBC_INIT    _MK_ENUM_CONST(0x00000014)                                                       // RWW-V
#define SATA0_AHCI_HBA_PRE_STAGING_CONTROL_0_ATAPI_EN_SHIFT  _MK_SHIFT_CONST(6)                                                              // RWWVF
#define SATA0_AHCI_HBA_PRE_STAGING_CONTROL_0_ATAPI_EN_FIELD (_MK_SHIFT_CONST(0x1) << SATA0_AHCI_HBA_PRE_STAGING_CONTROL_0_ATAPI_EN_SHIFT)
#define SATA0_AHCI_HBA_PRE_STAGING_CONTROL_0_ATAPI_EN_RANGE 6:6
#define SATA0_AHCI_HBA_PRE_STAGING_CONTROL_0_ATAPI_EN_WOFFSET 0
#define SATA0_AHCI_HBA_PRE_STAGING_CONTROL_0_ATAPI_EN_DEFAULT (_MK_MASK_CONST(0x00000001)
#define SATA0_AHCI_HBA_PRE_STAGING_CONTROL_0_ATAPI_EN_DEFAULT_MASK (_MK_MASK_CONST(0x1)
#define SATA0_AHCI_HBA_PRE_STAGING_CONTROL_0_ATAPI_EN_SW_DEFAULT (_MK_MASK_CONST(0x00000001)
#define SATA0_AHCI_HBA_PRE_STAGING_CONTROL_0_ATAPI_EN_SW_DEFAULT_MASK (_MK_MASK_CONST(0x1)
#define SATA0_AHCI_HBA_PRE_STAGING_CONTROL_0_ATAPI_EN_INIT _MK_ENUM_CONST(0x00000001)                                                       // RWW-V
#define SATA0_AHCI_HBA_PRE_STAGING_CONTROL_0_ENABLE_SHIFT   _MK_SHIFT_CONST(7)                                                              // RWWVF
#define SATA0_AHCI_HBA_PRE_STAGING_CONTROL_0_ENABLE_FIELD  (_MK_SHIFT_CONST(0x1) << SATA0_AHCI_HBA_PRE_STAGING_CONTROL_0_ENABLE_SHIFT)
#define SATA0_AHCI_HBA_PRE_STAGING_CONTROL_0_ENABLE_RANGE  7:7
#define SATA0_AHCI_HBA_PRE_STAGING_CONTROL_0_ENABLE_WOFFSET 0
#define SATA0_AHCI_HBA_PRE_STAGING_CONTROL_0_ENABLE_DEFAULT (_MK_MASK_CONST(0x00000001)
#define SATA0_AHCI_HBA_PRE_STAGING_CONTROL_0_ENABLE_DEFAULT_MASK (_MK_MASK_CONST(0x1)
#define SATA0_AHCI_HBA_PRE_STAGING_CONTROL_0_ENABLE_SW_DEFAULT (_MK_MASK_CONST(0x00000001)
#define SATA0_AHCI_HBA_PRE_STAGING_CONTROL_0_ENABLE_SW_DEFAULT_MASK (_MK_MASK_CONST(0x1)
#define SATA0_AHCI_HBA_PRE_STAGING_CONTROL_0_ENABLE_INIT   _MK_ENUM_CONST(0x00000001)                                                       // RWW-V
#define SATA0_AHCI_HBA_PRE_STAGING_CONTROL_0_FIFO_LEVEL_SHIFT  _MK_SHIFT_CONST(8)                                                              // RWWVF
#define SATA0_AHCI_HBA_PRE_STAGING_CONTROL_0_FIFO_LEVEL_FIELD (_MK_SHIFT_CONST(0xf) << SATA0_AHCI_HBA_PRE_STAGING_CONTROL_0_FIFO_LEVEL_SHIFT)
#define SATA0_AHCI_HBA_PRE_STAGING_CONTROL_0_FIFO_LEVEL_RANGE 11:8
#define SATA0_AHCI_HBA_PRE_STAGING_CONTROL_0_FIFO_LEVEL_WOFFSET 0
#define SATA0_AHCI_HBA_PRE_STAGING_CONTROL_0_FIFO_LEVEL_DEFAULT (_MK_MASK_CONST(0x00000006)
#define SATA0_AHCI_HBA_PRE_STAGING_CONTROL_0_FIFO_LEVEL_DEFAULT_MASK (_MK_MASK_CONST(0xf)
#define SATA0_AHCI_HBA_PRE_STAGING_CONTROL_0_FIFO_LEVEL_SW_DEFAULT (_MK_MASK_CONST(0x00000006)
#define SATA0_AHCI_HBA_PRE_STAGING_CONTROL_0_FIFO_LEVEL_SW_DEFAULT_MASK (_MK_MASK_CONST(0xf)
#define SATA0_AHCI_HBA_PRE_STAGING_CONTROL_0_FIFO_LEVEL_INIT _MK_ENUM_CONST(0x00000006)                                                       // RWW-V
#define SATA0_AHCI_HBA_PRE_STAGING_CONTROL_0_DMA_XFER_CNT_SHIFT  _MK_SHIFT_CONST(12)                                                             // RWWVF
#define SATA0_AHCI_HBA_PRE_STAGING_CONTROL_0_DMA_XFER_CNT_FIELD (_MK_SHIFT_CONST(0x3f) << SATA0_AHCI_HBA_PRE_STAGING_CONTROL_0_DMA_XFER_CNT_SHIFT)
#define SATA0_AHCI_HBA_PRE_STAGING_CONTROL_0_DMA_XFER_CNT_RANGE 17:12
#define SATA0_AHCI_HBA_PRE_STAGING_CONTROL_0_DMA_XFER_CNT_WOFFSET 0
#define SATA0_AHCI_HBA_PRE_STAGING_CONTROL_0_DMA_XFER_CNT_DEFAULT (_MK_MASK_CONST(0x00000000)
#define SATA0_AHCI_HBA_PRE_STAGING_CONTROL_0_DMA_XFER_CNT_DEFAULT_MASK (_MK_MASK_CONST(0x3f)
#define SATA0_AHCI_HBA_PRE_STAGING_CONTROL_0_DMA_XFER_CNT_SW_DEFAULT (_MK_MASK_CONST(0x00000000)
#define SATA0_AHCI_HBA_PRE_STAGING_CONTROL_0_DMA_XFER_CNT_SW_DEFAULT_MASK (_MK_MASK_CONST(0x3f)
#define SATA0_AHCI_HBA_PRE_STAGING_CONTROL_0_DMA_XFER_CNT_INIT _MK_ENUM_CONST(0x00000000)                                                       // RWW-V
#define SATA0_AHCI_HBA_PRE_STAGING_CONTROL_0_ENGAGED_SHIFT  _MK_SHIFT_CONST(20)                                                             // R-WVF
#define SATA0_AHCI_HBA_PRE_STAGING_CONTROL_0_ENGAGED_FIELD (_MK_SHIFT_CONST(0xf) << SATA0_AHCI_HBA_PRE_STAGING_CONTROL_0_ENGAGED_SHIFT)
#define SATA0_AHCI_HBA_PRE_STAGING_CONTROL_0_ENGAGED_RANGE 23:20
#define SATA0_AHCI_HBA_PRE_STAGING_CONTROL_0_ENGAGED_WOFFSET 0
#define SATA0_AHCI_HBA_PRE_STAGING_CONTROL_0_ENGAGED_DEFAULT (_MK_MASK_CONST(0x00000000)
#define SATA0_AHCI_HBA_PRE_STAGING_CONTROL_0_ENGAGED_DEFAULT_MASK (_MK_MASK_CONST(0xf)
#define SATA0_AHCI_HBA_PRE_STAGING_CONTROL_0_ENGAGED_SW_DEFAULT (_MK_MASK_CONST(0x00000000)
#define SATA0_AHCI_HBA_PRE_STAGING_CONTROL_0_ENGAGED_SW_DEFAULT_MASK (_MK_MASK_CONST(0xf)
#define SATA0_AHCI_HBA_PRE_STAGING_CONTROL_0_ENGAGED_INIT  _MK_ENUM_CONST(0x00000000)                                                       // R-W-V
#define SATA0_AHCI_HBA_PRE_STAGING_CONTROL_0_SPARE_SHIFT    _MK_SHIFT_CONST(24)                                                             // RWWVF
#define SATA0_AHCI_HBA_PRE_STAGING_CONTROL_0_SPARE_FIELD   (_MK_SHIFT_CONST(0xff) << SATA0_AHCI_HBA_PRE_STAGING_CONTROL_0_SPARE_SHIFT)
#define SATA0_AHCI_HBA_PRE_STAGING_CONTROL_0_SPARE_RANGE   31:24
#define SATA0_AHCI_HBA_PRE_STAGING_CONTROL_0_SPARE_WOFFSET 0
#define SATA0_AHCI_HBA_PRE_STAGING_CONTROL_0_SPARE_DEFAULT (_MK_MASK_CONST(0x000000AA)
#define SATA0_AHCI_HBA_PRE_STAGING_CONTROL_0_SPARE_DEFAULT_MASK (_MK_MASK_CONST(0xff)
#define SATA0_AHCI_HBA_PRE_STAGING_CONTROL_0_SPARE_SW_DEFAULT (_MK_MASK_CONST(0x000000AA)
#define SATA0_AHCI_HBA_PRE_STAGING_CONTROL_0_SPARE_SW_DEFAULT_MASK (_MK_MASK_CONST(0xff)
#define SATA0_AHCI_HBA_PRE_STAGING_CONTROL_0_SPARE_INIT    _MK_ENUM_CONST(0x000000AA)                                                       // RWW-V
// 
// 
// .LABEL PUBLIC
// 
// .LABEL FUNC_BIOS INT_REL
// .TITLE SATA_CFG
// .FIELD TICKS_FOR_MASTER_TO
// This is used in master slave emulation. Master waits for TICKS_FOR_MASTER_TO * 10**8 fpci_clk_sata
// cycles before timing out while waiting for response from slave drive on a device daignostic command.
// //TODO
// // For mcp65, fpci_clk_sata is running at 250 MHz and hence to get 6s timeout, we need to have this field
// // set to 15.
// 
// .LABEL PRIVATE INT_REL
// .FIELD WR_ALLOWED_SHAD_REG
// This bit when set will allow writes to shadow register even when BSY/ DRQ is one
//  31           24 23           16 15            8 7             0
// .-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-.
// |0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0| MASTER_TO
// +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
// 
// .LABEL INT_REL
#define SATA0_CFG_0                                        0x00000370                                                                       // RWW4R
#define SATA0_CFG_0_SECURE                                 0
#define SATA0_CFG_0_WORD_COUNT                             1
#define SATA0_CFG_0_RESET_VAL                              0x0
#define SATA0_CFG_0_RESET_MASK                             0x0
#define SATA0_CFG_0_SW_DEFAULT_VAL                         0x0
#define SATA0_CFG_0_SW_DEFAULT_MASK                        0x0
#define SATA0_CFG_0_READ_MASK                              0xffffffff
#define SATA0_CFG_0_WRITE_MASK                             0xfff00000
#define SATA0_CFG_0_CTRL_TICKS_FOR_MASTER_TO_SHIFT          _MK_SHIFT_CONST(24)                                                             // RWWVF
#define SATA0_CFG_0_CTRL_TICKS_FOR_MASTER_TO_FIELD         (_MK_SHIFT_CONST(0xff) << SATA0_CFG_0_CTRL_TICKS_FOR_MASTER_TO_SHIFT)
#define SATA0_CFG_0_CTRL_TICKS_FOR_MASTER_TO_RANGE         31:24
#define SATA0_CFG_0_CTRL_TICKS_FOR_MASTER_TO_WOFFSET       0
#define SATA0_CFG_0_CTRL_TICKS_FOR_MASTER_TO_DEFAULT       (_MK_MASK_CONST(0x0000000F)
#define SATA0_CFG_0_CTRL_TICKS_FOR_MASTER_TO_DEFAULT_MASK  (_MK_MASK_CONST(0xff)
#define SATA0_CFG_0_CTRL_TICKS_FOR_MASTER_TO_SW_DEFAULT    (_MK_MASK_CONST(0x0000000F)
#define SATA0_CFG_0_CTRL_TICKS_FOR_MASTER_TO_SW_DEFAULT_MASK (_MK_MASK_CONST(0xff)
#define SATA0_CFG_0_CTRL_TICKS_FOR_MASTER_TO__WRNPRDCHK    _MK_ENUM_CONST(0x00000001)                                                       // ----V
#define SATA0_CFG_0_CTRL_TICKS_FOR_MASTER_TO_250MHZ        _MK_ENUM_CONST(0x0000000F)                                                       // RW--V
#define SATA0_CFG_0_CTRL_TICKS_FOR_MASTER_TO_INIT          _MK_ENUM_CONST(0x0000000F)                                                       // RWW-V
#define SATA0_CFG_0_WR_ALLOWED_SHAD_REG_SHIFT               _MK_SHIFT_CONST(23)                                                             // RWWVF
#define SATA0_CFG_0_WR_ALLOWED_SHAD_REG_FIELD              (_MK_SHIFT_CONST(0x1) << SATA0_CFG_0_WR_ALLOWED_SHAD_REG_SHIFT)
#define SATA0_CFG_0_WR_ALLOWED_SHAD_REG_RANGE              23:23
#define SATA0_CFG_0_WR_ALLOWED_SHAD_REG_WOFFSET            0
#define SATA0_CFG_0_WR_ALLOWED_SHAD_REG_DEFAULT            (_MK_MASK_CONST(0x00000000)
#define SATA0_CFG_0_WR_ALLOWED_SHAD_REG_DEFAULT_MASK       (_MK_MASK_CONST(0x1)
#define SATA0_CFG_0_WR_ALLOWED_SHAD_REG_SW_DEFAULT         (_MK_MASK_CONST(0x00000000)
#define SATA0_CFG_0_WR_ALLOWED_SHAD_REG_SW_DEFAULT_MASK    (_MK_MASK_CONST(0x1)
#define SATA0_CFG_0_WR_ALLOWED_SHAD_REG_INIT               _MK_ENUM_CONST(0x00000000)                                                       // RWW-V
#define SATA0_CFG_0_HOT_RESET_ON_BM_START_ALONE_SHIFT       _MK_SHIFT_CONST(22)                                                             // RWWVF
#define SATA0_CFG_0_HOT_RESET_ON_BM_START_ALONE_FIELD      (_MK_SHIFT_CONST(0x1) << SATA0_CFG_0_HOT_RESET_ON_BM_START_ALONE_SHIFT)
#define SATA0_CFG_0_HOT_RESET_ON_BM_START_ALONE_RANGE      22:22
#define SATA0_CFG_0_HOT_RESET_ON_BM_START_ALONE_WOFFSET    0
#define SATA0_CFG_0_HOT_RESET_ON_BM_START_ALONE_DEFAULT    (_MK_MASK_CONST(0x00000000)
#define SATA0_CFG_0_HOT_RESET_ON_BM_START_ALONE_DEFAULT_MASK (_MK_MASK_CONST(0x1)
#define SATA0_CFG_0_HOT_RESET_ON_BM_START_ALONE_SW_DEFAULT (_MK_MASK_CONST(0x00000000)
#define SATA0_CFG_0_HOT_RESET_ON_BM_START_ALONE_SW_DEFAULT_MASK (_MK_MASK_CONST(0x1)
#define SATA0_CFG_0_HOT_RESET_ON_BM_START_ALONE_INIT       _MK_ENUM_CONST(0x00000000)                                                       // RWW-V
#define SATA0_CFG_0_HOT_RESET_OLD_BEHAVIOUR_SHIFT           _MK_SHIFT_CONST(21)                                                             // RWWVF
#define SATA0_CFG_0_HOT_RESET_OLD_BEHAVIOUR_FIELD          (_MK_SHIFT_CONST(0x1) << SATA0_CFG_0_HOT_RESET_OLD_BEHAVIOUR_SHIFT)
#define SATA0_CFG_0_HOT_RESET_OLD_BEHAVIOUR_RANGE          21:21
#define SATA0_CFG_0_HOT_RESET_OLD_BEHAVIOUR_WOFFSET        0
#define SATA0_CFG_0_HOT_RESET_OLD_BEHAVIOUR_DEFAULT        (_MK_MASK_CONST(0x00000001)
#define SATA0_CFG_0_HOT_RESET_OLD_BEHAVIOUR_DEFAULT_MASK   (_MK_MASK_CONST(0x1)
#define SATA0_CFG_0_HOT_RESET_OLD_BEHAVIOUR_SW_DEFAULT     (_MK_MASK_CONST(0x00000001)
#define SATA0_CFG_0_HOT_RESET_OLD_BEHAVIOUR_SW_DEFAULT_MASK (_MK_MASK_CONST(0x1)
#define SATA0_CFG_0_HOT_RESET_OLD_BEHAVIOUR_INIT           _MK_ENUM_CONST(0x00000001)                                                       // RWW-V
#define SATA0_CFG_0_HOT_RESET_OLD_BEHAVIOUR__PROD          _MK_ENUM_CONST(0x00000001)                                                       // RW--V
#define SATA0_CFG_0_RESET_SREGS_ON_OOB_COMRESET_SHIFT       _MK_SHIFT_CONST(20)                                                             // RWCVF
#define SATA0_CFG_0_RESET_SREGS_ON_OOB_COMRESET_FIELD      (_MK_SHIFT_CONST(0x1) << SATA0_CFG_0_RESET_SREGS_ON_OOB_COMRESET_SHIFT)
#define SATA0_CFG_0_RESET_SREGS_ON_OOB_COMRESET_RANGE      20:20
#define SATA0_CFG_0_RESET_SREGS_ON_OOB_COMRESET_WOFFSET    0
#define SATA0_CFG_0_RESET_SREGS_ON_OOB_COMRESET_TRUE       _MK_ENUM_CONST(0x00000001)                                                       // RWC-V
#define SATA0_CFG_0_RESET_SREGS_ON_OOB_COMRESET_FALSE      _MK_ENUM_CONST(0x00000000)                                                       // RW--V
#define SATA0_CFG_0_RSVD_1_SHIFT                            _MK_SHIFT_CONST(0)                                                              // C--VF
#define SATA0_CFG_0_RSVD_1_FIELD                           (_MK_SHIFT_CONST(0xfffff) << SATA0_CFG_0_RSVD_1_SHIFT)
#define SATA0_CFG_0_RSVD_1_RANGE                           19:0
#define SATA0_CFG_0_RSVD_1_WOFFSET                         0
#define SATA0_CFG_0_RSVD_1_VAL                             _MK_ENUM_CONST(0x00000000)                                                       // C---V
// .LABEL FUNC_BIOS INT_REL
// .LABEL PRIVATE INT_REL
// 
// .LABEL PRIVATE INT_REL
// 
// .LABEL PRIVATE INT_REL
// 
// .LABEL PRIVATE INT_REL
// 
//      Figure 10-24  Serial ATA Control Register 370h
// .LABEL PUBLIC
// 
// .LABEL PRIVATE INT_REL
// .TITLE CTL_SHADOW
// .FIELD PIO_DATA_READ_RETRY
//  31           24 23           16 15            8 7             0
// .-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-.
// |0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0| CYA_SHADOW
// +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
#define SATA0_CYA_SHADOW_0                                 0x00000378                                                                       // RWW4R
#define SATA0_CYA_SHADOW_0_SECURE                          0
#define SATA0_CYA_SHADOW_0_WORD_COUNT                      1
#define SATA0_CYA_SHADOW_0_RESET_VAL                       0x0
#define SATA0_CYA_SHADOW_0_RESET_MASK                      0x0
#define SATA0_CYA_SHADOW_0_SW_DEFAULT_VAL                  0x0
#define SATA0_CYA_SHADOW_0_SW_DEFAULT_MASK                 0x0
#define SATA0_CYA_SHADOW_0_READ_MASK                       0xffffffff
#define SATA0_CYA_SHADOW_0_WRITE_MASK                      0xf8000000
#define SATA0_CYA_SHADOW_0_PIO_DATA_READ_RETRY_SHIFT        _MK_SHIFT_CONST(31)                                                             // RWW-F
#define SATA0_CYA_SHADOW_0_PIO_DATA_READ_RETRY_FIELD       (_MK_SHIFT_CONST(0x1) << SATA0_CYA_SHADOW_0_PIO_DATA_READ_RETRY_SHIFT)
#define SATA0_CYA_SHADOW_0_PIO_DATA_READ_RETRY_RANGE       31:31
#define SATA0_CYA_SHADOW_0_PIO_DATA_READ_RETRY_WOFFSET     0
#define SATA0_CYA_SHADOW_0_PIO_DATA_READ_RETRY_DEFAULT     (_MK_MASK_CONST(0x00000000)
#define SATA0_CYA_SHADOW_0_PIO_DATA_READ_RETRY_DEFAULT_MASK (_MK_MASK_CONST(0x1)
#define SATA0_CYA_SHADOW_0_PIO_DATA_READ_RETRY_SW_DEFAULT  (_MK_MASK_CONST(0x00000000)
#define SATA0_CYA_SHADOW_0_PIO_DATA_READ_RETRY_SW_DEFAULT_MASK (_MK_MASK_CONST(0x1)
#define SATA0_CYA_SHADOW_0_PIO_DATA_READ_RETRY_NEW         _MK_ENUM_CONST(0x00000000)                                                       // RWW-V
#define SATA0_CYA_SHADOW_0_PIO_DATA_READ_RETRY_OLD         _MK_ENUM_CONST(0x00000001)                                                       // RW--V
#define SATA0_CYA_SHADOW_0_ALLOW_CTRL_WR_WHEN_DRIVE_NOT_PRESENT_SHIFT  _MK_SHIFT_CONST(30)                                                             // RWW-F
#define SATA0_CYA_SHADOW_0_ALLOW_CTRL_WR_WHEN_DRIVE_NOT_PRESENT_FIELD (_MK_SHIFT_CONST(0x1) << SATA0_CYA_SHADOW_0_ALLOW_CTRL_WR_WHEN_DRIVE_NOT_PRESENT_SHIFT)
#define SATA0_CYA_SHADOW_0_ALLOW_CTRL_WR_WHEN_DRIVE_NOT_PRESENT_RANGE 30:30
#define SATA0_CYA_SHADOW_0_ALLOW_CTRL_WR_WHEN_DRIVE_NOT_PRESENT_WOFFSET 0
#define SATA0_CYA_SHADOW_0_ALLOW_CTRL_WR_WHEN_DRIVE_NOT_PRESENT_DEFAULT (_MK_MASK_CONST(0x00000000)
#define SATA0_CYA_SHADOW_0_ALLOW_CTRL_WR_WHEN_DRIVE_NOT_PRESENT_DEFAULT_MASK (_MK_MASK_CONST(0x1)
#define SATA0_CYA_SHADOW_0_ALLOW_CTRL_WR_WHEN_DRIVE_NOT_PRESENT_SW_DEFAULT (_MK_MASK_CONST(0x00000000)
#define SATA0_CYA_SHADOW_0_ALLOW_CTRL_WR_WHEN_DRIVE_NOT_PRESENT_SW_DEFAULT_MASK (_MK_MASK_CONST(0x1)
#define SATA0_CYA_SHADOW_0_ALLOW_CTRL_WR_WHEN_DRIVE_NOT_PRESENT_YES _MK_ENUM_CONST(0x00000001)                                                       // RW--V
#define SATA0_CYA_SHADOW_0_ALLOW_CTRL_WR_WHEN_DRIVE_NOT_PRESENT_NO _MK_ENUM_CONST(0x00000000)                                                       // RWW-V
#define SATA0_CYA_SHADOW_0_RET_ERROR_7F_WHEN_MASTER_ABSENT_SHIFT  _MK_SHIFT_CONST(29)                                                             // RWW-F
#define SATA0_CYA_SHADOW_0_RET_ERROR_7F_WHEN_MASTER_ABSENT_FIELD (_MK_SHIFT_CONST(0x1) << SATA0_CYA_SHADOW_0_RET_ERROR_7F_WHEN_MASTER_ABSENT_SHIFT)
#define SATA0_CYA_SHADOW_0_RET_ERROR_7F_WHEN_MASTER_ABSENT_RANGE 29:29
#define SATA0_CYA_SHADOW_0_RET_ERROR_7F_WHEN_MASTER_ABSENT_WOFFSET 0
#define SATA0_CYA_SHADOW_0_RET_ERROR_7F_WHEN_MASTER_ABSENT_DEFAULT (_MK_MASK_CONST(0x00000001)
#define SATA0_CYA_SHADOW_0_RET_ERROR_7F_WHEN_MASTER_ABSENT_DEFAULT_MASK (_MK_MASK_CONST(0x1)
#define SATA0_CYA_SHADOW_0_RET_ERROR_7F_WHEN_MASTER_ABSENT_SW_DEFAULT (_MK_MASK_CONST(0x00000001)
#define SATA0_CYA_SHADOW_0_RET_ERROR_7F_WHEN_MASTER_ABSENT_SW_DEFAULT_MASK (_MK_MASK_CONST(0x1)
#define SATA0_CYA_SHADOW_0_RET_ERROR_7F_WHEN_MASTER_ABSENT_TRUE _MK_ENUM_CONST(0x00000001)                                                       // RWW-V
#define SATA0_CYA_SHADOW_0_RET_ERROR_7F_WHEN_MASTER_ABSENT_NO _MK_ENUM_CONST(0x00000000)                                                       // RW--V
#define SATA0_CYA_SHADOW_0_FIX_SRST_WHEN_ONE_DEVICE_NOT_PRESENT_SHIFT  _MK_SHIFT_CONST(28)                                                             // RWW-F
#define SATA0_CYA_SHADOW_0_FIX_SRST_WHEN_ONE_DEVICE_NOT_PRESENT_FIELD (_MK_SHIFT_CONST(0x1) << SATA0_CYA_SHADOW_0_FIX_SRST_WHEN_ONE_DEVICE_NOT_PRESENT_SHIFT)
#define SATA0_CYA_SHADOW_0_FIX_SRST_WHEN_ONE_DEVICE_NOT_PRESENT_RANGE 28:28
#define SATA0_CYA_SHADOW_0_FIX_SRST_WHEN_ONE_DEVICE_NOT_PRESENT_WOFFSET 0
#define SATA0_CYA_SHADOW_0_FIX_SRST_WHEN_ONE_DEVICE_NOT_PRESENT_DEFAULT (_MK_MASK_CONST(0x00000001)
#define SATA0_CYA_SHADOW_0_FIX_SRST_WHEN_ONE_DEVICE_NOT_PRESENT_DEFAULT_MASK (_MK_MASK_CONST(0x1)
#define SATA0_CYA_SHADOW_0_FIX_SRST_WHEN_ONE_DEVICE_NOT_PRESENT_SW_DEFAULT (_MK_MASK_CONST(0x00000001)
#define SATA0_CYA_SHADOW_0_FIX_SRST_WHEN_ONE_DEVICE_NOT_PRESENT_SW_DEFAULT_MASK (_MK_MASK_CONST(0x1)
#define SATA0_CYA_SHADOW_0_FIX_SRST_WHEN_ONE_DEVICE_NOT_PRESENT_INIT _MK_ENUM_CONST(0x00000001)                                                       // RWW-V
#define SATA0_CYA_SHADOW_0_USE_ELONGATED_FIFO_HOT_RESET_SHIFT  _MK_SHIFT_CONST(27)                                                             // RWWVF
#define SATA0_CYA_SHADOW_0_USE_ELONGATED_FIFO_HOT_RESET_FIELD (_MK_SHIFT_CONST(0x1) << SATA0_CYA_SHADOW_0_USE_ELONGATED_FIFO_HOT_RESET_SHIFT)
#define SATA0_CYA_SHADOW_0_USE_ELONGATED_FIFO_HOT_RESET_RANGE 27:27
#define SATA0_CYA_SHADOW_0_USE_ELONGATED_FIFO_HOT_RESET_WOFFSET 0
#define SATA0_CYA_SHADOW_0_USE_ELONGATED_FIFO_HOT_RESET_DEFAULT (_MK_MASK_CONST(0x00000000)
#define SATA0_CYA_SHADOW_0_USE_ELONGATED_FIFO_HOT_RESET_DEFAULT_MASK (_MK_MASK_CONST(0x1)
#define SATA0_CYA_SHADOW_0_USE_ELONGATED_FIFO_HOT_RESET_SW_DEFAULT (_MK_MASK_CONST(0x00000000)
#define SATA0_CYA_SHADOW_0_USE_ELONGATED_FIFO_HOT_RESET_SW_DEFAULT_MASK (_MK_MASK_CONST(0x1)
#define SATA0_CYA_SHADOW_0_USE_ELONGATED_FIFO_HOT_RESET_INIT _MK_ENUM_CONST(0x00000000)                                                       // RWW-V
#define SATA0_CYA_SHADOW_0_RSVD_SHIFT                       _MK_SHIFT_CONST(0)                                                              // C--VF
#define SATA0_CYA_SHADOW_0_RSVD_FIELD                      (_MK_SHIFT_CONST(0x7ffffff) << SATA0_CYA_SHADOW_0_RSVD_SHIFT)
#define SATA0_CYA_SHADOW_0_RSVD_RANGE                      26:0
#define SATA0_CYA_SHADOW_0_RSVD_WOFFSET                    0
#define SATA0_CYA_SHADOW_0_RSVD_VAL                        _MK_ENUM_CONST(0x00000000)                                                       // C---V
// .define T_SATA0_CTL_SHADOW                                            0x00000378 /* RWW4R */
// 
// .LABEL PUBLIC
// 
// .LABEL PRIVATE INT_REL
// .TITLE CFG_FPCI_0
// .FIELD AHCI_MODE_DEP_ON_EN
// When class code is 0106, ahci_mode will be one
// When class code is 0101, ahci_mode will be zero
// in other cases ahci_mode will depend on ahci_en if this bit is set, if bit is zero ahci_mode will be one
// 
// .FIELD SEND_MSG_ON_NEW_INTR
// This is used in the case of multiple MSI. This is to disbale/ enable sending interrupts when a new bit is written
// in pxis and if a some bits are cleared but not all and there is a posedge on a bit in pxie(see AHCI spec 10.7.2)
// 
// .FIELD SEND_NEW_MSG_IS_NOT_ZERO
// This is used in the case of single MSI to send new message(intr), if the SW comes and clears some bits of IS
// but not all(see AHCI spec 10.7.2)
// 
//  31           24 23           16 15            8 7             0
// .-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-.
// |0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0| CFG_FPCI_0
// +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
#define SATA0_CFG_FPCI_0_0                                 0x00000430                                                                       // RWW4R
#define SATA0_CFG_FPCI_0_0_SECURE                          0
#define SATA0_CFG_FPCI_0_0_WORD_COUNT                      1
#define SATA0_CFG_FPCI_0_0_RESET_VAL                       0x0
#define SATA0_CFG_FPCI_0_0_RESET_MASK                      0x0
#define SATA0_CFG_FPCI_0_0_SW_DEFAULT_VAL                  0x0
#define SATA0_CFG_FPCI_0_0_SW_DEFAULT_MASK                 0x0
#define SATA0_CFG_FPCI_0_0_READ_MASK                       0xffffffff
#define SATA0_CFG_FPCI_0_0_WRITE_MASK                      0xe0000000
#define SATA0_CFG_FPCI_0_0_AHCI_MODE_DEP_ON_EN_SHIFT        _MK_SHIFT_CONST(31)                                                             // RWC-F
#define SATA0_CFG_FPCI_0_0_AHCI_MODE_DEP_ON_EN_FIELD       (_MK_SHIFT_CONST(0x1) << SATA0_CFG_FPCI_0_0_AHCI_MODE_DEP_ON_EN_SHIFT)
#define SATA0_CFG_FPCI_0_0_AHCI_MODE_DEP_ON_EN_RANGE       31:31
#define SATA0_CFG_FPCI_0_0_AHCI_MODE_DEP_ON_EN_WOFFSET     0
#define SATA0_CFG_FPCI_0_0_AHCI_MODE_DEP_ON_EN_YES         _MK_ENUM_CONST(0x00000001)                                                       // RW--V
#define SATA0_CFG_FPCI_0_0_AHCI_MODE_DEP_ON_EN_NO          _MK_ENUM_CONST(0x00000000)                                                       // RWC-V
#define SATA0_CFG_FPCI_0_0_SEND_MSG_ON_NEW_INTR_SHIFT       _MK_SHIFT_CONST(30)                                                             // RWWVF
#define SATA0_CFG_FPCI_0_0_SEND_MSG_ON_NEW_INTR_FIELD      (_MK_SHIFT_CONST(0x1) << SATA0_CFG_FPCI_0_0_SEND_MSG_ON_NEW_INTR_SHIFT)
#define SATA0_CFG_FPCI_0_0_SEND_MSG_ON_NEW_INTR_RANGE      30:30
#define SATA0_CFG_FPCI_0_0_SEND_MSG_ON_NEW_INTR_WOFFSET    0
#define SATA0_CFG_FPCI_0_0_SEND_MSG_ON_NEW_INTR_DEFAULT    (_MK_MASK_CONST(0x00000001)
#define SATA0_CFG_FPCI_0_0_SEND_MSG_ON_NEW_INTR_DEFAULT_MASK (_MK_MASK_CONST(0x1)
#define SATA0_CFG_FPCI_0_0_SEND_MSG_ON_NEW_INTR_SW_DEFAULT (_MK_MASK_CONST(0x00000001)
#define SATA0_CFG_FPCI_0_0_SEND_MSG_ON_NEW_INTR_SW_DEFAULT_MASK (_MK_MASK_CONST(0x1)
#define SATA0_CFG_FPCI_0_0_SEND_MSG_ON_NEW_INTR_INIT       _MK_ENUM_CONST(0x00000001)                                                       // RWW-V
#define SATA0_CFG_FPCI_0_0_SEND_NEW_MSG_IS_NOT_ZERO_SHIFT   _MK_SHIFT_CONST(29)                                                             // RWWVF
#define SATA0_CFG_FPCI_0_0_SEND_NEW_MSG_IS_NOT_ZERO_FIELD  (_MK_SHIFT_CONST(0x1) << SATA0_CFG_FPCI_0_0_SEND_NEW_MSG_IS_NOT_ZERO_SHIFT)
#define SATA0_CFG_FPCI_0_0_SEND_NEW_MSG_IS_NOT_ZERO_RANGE  29:29
#define SATA0_CFG_FPCI_0_0_SEND_NEW_MSG_IS_NOT_ZERO_WOFFSET 0
#define SATA0_CFG_FPCI_0_0_SEND_NEW_MSG_IS_NOT_ZERO_DEFAULT (_MK_MASK_CONST(0x00000001)
#define SATA0_CFG_FPCI_0_0_SEND_NEW_MSG_IS_NOT_ZERO_DEFAULT_MASK (_MK_MASK_CONST(0x1)
#define SATA0_CFG_FPCI_0_0_SEND_NEW_MSG_IS_NOT_ZERO_SW_DEFAULT (_MK_MASK_CONST(0x00000001)
#define SATA0_CFG_FPCI_0_0_SEND_NEW_MSG_IS_NOT_ZERO_SW_DEFAULT_MASK (_MK_MASK_CONST(0x1)
#define SATA0_CFG_FPCI_0_0_SEND_NEW_MSG_IS_NOT_ZERO_INIT   _MK_ENUM_CONST(0x00000001)                                                       // RWW-V
#define SATA0_CFG_FPCI_0_0_RSVD_SHIFT                       _MK_SHIFT_CONST(0)                                                              // C--VF
#define SATA0_CFG_FPCI_0_0_RSVD_FIELD                      (_MK_SHIFT_CONST(0x1fffffff) << SATA0_CFG_FPCI_0_0_RSVD_SHIFT)
#define SATA0_CFG_FPCI_0_0_RSVD_RANGE                      28:0
#define SATA0_CFG_FPCI_0_0_RSVD_WOFFSET                    0
#define SATA0_CFG_FPCI_0_0_RSVD_VAL                        _MK_ENUM_CONST(0x00000000)                                                       // C---V
// 
// 
// 
// 
// .LABEL PUBLIC
// 
// .LABEL PRIVATE INT_REL
// .TITLE IDE1
// .LABEL OLD_IDE_TIMING
// When 40bit addressing mode is enabled, this will load [39:32] of the prd_base
// 
//  31           24 23           16 15            8 7             0
// .-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-.
// |0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0| IDE1
// +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
#define SATA0_IDE1_0                                       0x00000490                                                                       // RW-4R
#define SATA0_IDE1_0_SECURE                                0
#define SATA0_IDE1_0_WORD_COUNT                            1
#define SATA0_IDE1_0_RESET_VAL                             0x0
#define SATA0_IDE1_0_RESET_MASK                            0x0
#define SATA0_IDE1_0_SW_DEFAULT_VAL                        0x0
#define SATA0_IDE1_0_SW_DEFAULT_MASK                       0x0
#define SATA0_IDE1_0_READ_MASK                             0xffffffff
#define SATA0_IDE1_0_WRITE_MASK                            0xffffffff
#define SATA0_IDE1_0_OLD_IDE_TIMING_SHIFT                   _MK_SHIFT_CONST(0)                                                              // RWWUF
#define SATA0_IDE1_0_OLD_IDE_TIMING_FIELD                  (_MK_SHIFT_CONST(0xffffffff) << SATA0_IDE1_0_OLD_IDE_TIMING_SHIFT)
#define SATA0_IDE1_0_OLD_IDE_TIMING_RANGE                  31:0
#define SATA0_IDE1_0_OLD_IDE_TIMING_WOFFSET                0
#define SATA0_IDE1_0_OLD_IDE_TIMING_DEFAULT                (_MK_MASK_CONST(0x00000000)
#define SATA0_IDE1_0_OLD_IDE_TIMING_DEFAULT_MASK           (_MK_MASK_CONST(0xffffffff)
#define SATA0_IDE1_0_OLD_IDE_TIMING_SW_DEFAULT             (_MK_MASK_CONST(0x00000000)
#define SATA0_IDE1_0_OLD_IDE_TIMING_SW_DEFAULT_MASK        (_MK_MASK_CONST(0xffffffff)
#define SATA0_IDE1_0_OLD_IDE_TIMING__NOPRDCHK              _MK_ENUM_CONST(0x00000001)                                                       // ----V
// 
// 
//         Figure 10-21  FPCI Configuration Register 490h
// .LABEL PUBLIC
// 
// .LABEL PRIVATE INT_REL
// .TITLE CFG_ESATA_CTRL
// This register implement settings for controlling behaviour of AHCI SM
// during error conditions.
// 
//  31           24 23           16 15            8 7             0
// .-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-.
// |0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0| CFG_ESATA_CTRL
// +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
#define SATA0_CFG_ESATA_CTRL_0                             0x00000494                                                                       // RW-4R
#define SATA0_CFG_ESATA_CTRL_0_SECURE                      0
#define SATA0_CFG_ESATA_CTRL_0_WORD_COUNT                  1
#define SATA0_CFG_ESATA_CTRL_0_RESET_VAL                   0x0
#define SATA0_CFG_ESATA_CTRL_0_RESET_MASK                  0x0
#define SATA0_CFG_ESATA_CTRL_0_SW_DEFAULT_VAL              0x0
#define SATA0_CFG_ESATA_CTRL_0_SW_DEFAULT_MASK             0x0
#define SATA0_CFG_ESATA_CTRL_0_READ_MASK                   0xffffffff
#define SATA0_CFG_ESATA_CTRL_0_WRITE_MASK                  0xffff
#define SATA0_CFG_ESATA_CTRL_0_TX_AMP_LIMIT_SHIFT           _MK_SHIFT_CONST(0)                                                              // RWCVF
#define SATA0_CFG_ESATA_CTRL_0_TX_AMP_LIMIT_FIELD          (_MK_SHIFT_CONST(0xff) << SATA0_CFG_ESATA_CTRL_0_TX_AMP_LIMIT_SHIFT)
#define SATA0_CFG_ESATA_CTRL_0_TX_AMP_LIMIT_RANGE          7:0
#define SATA0_CFG_ESATA_CTRL_0_TX_AMP_LIMIT_WOFFSET        0
#define SATA0_CFG_ESATA_CTRL_0_TX_AMP_LIMIT_INIT           _MK_ENUM_CONST(0x00000000)                                                       // RWC-V
#define SATA0_CFG_ESATA_CTRL_0_TX_PEAK_LIMIT_SHIFT          _MK_SHIFT_CONST(8)                                                              // RWCVF
#define SATA0_CFG_ESATA_CTRL_0_TX_PEAK_LIMIT_FIELD         (_MK_SHIFT_CONST(0xff) << SATA0_CFG_ESATA_CTRL_0_TX_PEAK_LIMIT_SHIFT)
#define SATA0_CFG_ESATA_CTRL_0_TX_PEAK_LIMIT_RANGE         15:8
#define SATA0_CFG_ESATA_CTRL_0_TX_PEAK_LIMIT_WOFFSET       0
#define SATA0_CFG_ESATA_CTRL_0_TX_PEAK_LIMIT_INIT          _MK_ENUM_CONST(0x00000000)                                                       // RWC-V
#define SATA0_CFG_ESATA_CTRL_0_RSVD_SHIFT                   _MK_SHIFT_CONST(16)                                                             // C--VF
#define SATA0_CFG_ESATA_CTRL_0_RSVD_FIELD                  (_MK_SHIFT_CONST(0xffff) << SATA0_CFG_ESATA_CTRL_0_RSVD_SHIFT)
#define SATA0_CFG_ESATA_CTRL_0_RSVD_RANGE                  31:16
#define SATA0_CFG_ESATA_CTRL_0_RSVD_WOFFSET                0
#define SATA0_CFG_ESATA_CTRL_0_RSVD_VAL                    _MK_ENUM_CONST(0x00000000)                                                       // C---V
// 
// .LABEL PUBLIC
// 
// 
// .LABEL PRIVATE INT_REL
// 
// //.TITLE Fuse status Register 78h
// .TITLE Feature Register 78h
//   Status for each of the feature options:
//     Bit  Feature
//     ---  -------
//      31  NBP enable
//   30:13  Reserved
//   12:11  RAID function by SW programming
//      10  Reserved
//       9  Only 4 SATA ports supported
// //    8  FUSE SW - Programmable via `NV_PROJ_MISC_COMMON_FUSE_ADDRESS/DATA
//       8  Software feature
//       7  Only 2 SATA ports supported
//       6  AHCI disabled
//       5  eSATA disabled
//       4  Aggressive power management disabled
//       3  Staggered spin-up disabled
//       2  iSCSI disabled
//       1  SATA Gen2 enabled
//       0  Advanced storage features disabled
//   Other bits are reserved.
// 
// 
// 
//  31           24 23           16 15            8 7             0
// .-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-.
// |                                                               | FUSE
// `-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-'
// 
#define SATA0_FUSE_0                                       0x00000498                                                                       // RW-4R
#define SATA0_FUSE_0_SECURE                                0
#define SATA0_FUSE_0_WORD_COUNT                            1
#define SATA0_FUSE_0_RESET_VAL                             0x0
#define SATA0_FUSE_0_RESET_MASK                            0x0
#define SATA0_FUSE_0_SW_DEFAULT_VAL                        0x0
#define SATA0_FUSE_0_SW_DEFAULT_MASK                       0x0
#define SATA0_FUSE_0_READ_MASK                             0xffffffff
#define SATA0_FUSE_0_WRITE_MASK                            0x0
#define SATA0_FUSE_0_RSVD_0_SHIFT                           _MK_SHIFT_CONST(0)                                                              // C---F
#define SATA0_FUSE_0_RSVD_0_FIELD                          (_MK_SHIFT_CONST(0x1) << SATA0_FUSE_0_RSVD_0_SHIFT)
#define SATA0_FUSE_0_RSVD_0_RANGE                          0:0
#define SATA0_FUSE_0_RSVD_0_WOFFSET                        0
#define SATA0_FUSE_0_RSVD_0_VAL                            _MK_ENUM_CONST(0x00000000)                                                       // C---V
#define SATA0_FUSE_0_GEN2_EN_SHIFT                          _MK_SHIFT_CONST(1)                                                              // R-W-F
#define SATA0_FUSE_0_GEN2_EN_FIELD                         (_MK_SHIFT_CONST(0x1) << SATA0_FUSE_0_GEN2_EN_SHIFT)
#define SATA0_FUSE_0_GEN2_EN_RANGE                         1:1
#define SATA0_FUSE_0_GEN2_EN_WOFFSET                       0
#define SATA0_FUSE_0_GEN2_EN_DEFAULT                       (_MK_MASK_CONST(0x00000001)
#define SATA0_FUSE_0_GEN2_EN_DEFAULT_MASK                  (_MK_MASK_CONST(0x1)
#define SATA0_FUSE_0_GEN2_EN_SW_DEFAULT                    (_MK_MASK_CONST(0x00000001)
#define SATA0_FUSE_0_GEN2_EN_SW_DEFAULT_MASK               (_MK_MASK_CONST(0x1)
#define SATA0_FUSE_0_GEN2_EN_YES                           _MK_ENUM_CONST(0x00000001)                                                       // R-W-V
#define SATA0_FUSE_0_GEN2_EN_NO                            _MK_ENUM_CONST(0x00000000)                                                       // R---V
#define SATA0_FUSE_0_GEN3_EN_SHIFT                          _MK_SHIFT_CONST(2)                                                              // R-W-F
#define SATA0_FUSE_0_GEN3_EN_FIELD                         (_MK_SHIFT_CONST(0x1) << SATA0_FUSE_0_GEN3_EN_SHIFT)
#define SATA0_FUSE_0_GEN3_EN_RANGE                         2:2
#define SATA0_FUSE_0_GEN3_EN_WOFFSET                       0
#define SATA0_FUSE_0_GEN3_EN_DEFAULT                       (_MK_MASK_CONST(0x00000000)
#define SATA0_FUSE_0_GEN3_EN_DEFAULT_MASK                  (_MK_MASK_CONST(0x1)
#define SATA0_FUSE_0_GEN3_EN_SW_DEFAULT                    (_MK_MASK_CONST(0x00000000)
#define SATA0_FUSE_0_GEN3_EN_SW_DEFAULT_MASK               (_MK_MASK_CONST(0x1)
#define SATA0_FUSE_0_GEN3_EN_YES                           _MK_ENUM_CONST(0x00000001)                                                       // R---V
#define SATA0_FUSE_0_GEN3_EN_NO                            _MK_ENUM_CONST(0x00000000)                                                       // R-W-V
#define SATA0_FUSE_0_FBS_DIS_SHIFT                          _MK_SHIFT_CONST(3)                                                              // R-W-F
#define SATA0_FUSE_0_FBS_DIS_FIELD                         (_MK_SHIFT_CONST(0x1) << SATA0_FUSE_0_FBS_DIS_SHIFT)
#define SATA0_FUSE_0_FBS_DIS_RANGE                         3:3
#define SATA0_FUSE_0_FBS_DIS_WOFFSET                       0
#define SATA0_FUSE_0_FBS_DIS_DEFAULT                       (_MK_MASK_CONST(0x00000000)
#define SATA0_FUSE_0_FBS_DIS_DEFAULT_MASK                  (_MK_MASK_CONST(0x1)
#define SATA0_FUSE_0_FBS_DIS_SW_DEFAULT                    (_MK_MASK_CONST(0x00000000)
#define SATA0_FUSE_0_FBS_DIS_SW_DEFAULT_MASK               (_MK_MASK_CONST(0x1)
#define SATA0_FUSE_0_FBS_DIS_YES                           _MK_ENUM_CONST(0x00000001)                                                       // R---V
#define SATA0_FUSE_0_FBS_DIS_NO                            _MK_ENUM_CONST(0x00000000)                                                       // R-W-V
#define SATA0_FUSE_0_AHCI_POWER_DIS_SHIFT                   _MK_SHIFT_CONST(4)                                                              // R-W-F
#define SATA0_FUSE_0_AHCI_POWER_DIS_FIELD                  (_MK_SHIFT_CONST(0x1) << SATA0_FUSE_0_AHCI_POWER_DIS_SHIFT)
#define SATA0_FUSE_0_AHCI_POWER_DIS_RANGE                  4:4
#define SATA0_FUSE_0_AHCI_POWER_DIS_WOFFSET                0
#define SATA0_FUSE_0_AHCI_POWER_DIS_DEFAULT                (_MK_MASK_CONST(0x00000000)
#define SATA0_FUSE_0_AHCI_POWER_DIS_DEFAULT_MASK           (_MK_MASK_CONST(0x1)
#define SATA0_FUSE_0_AHCI_POWER_DIS_SW_DEFAULT             (_MK_MASK_CONST(0x00000000)
#define SATA0_FUSE_0_AHCI_POWER_DIS_SW_DEFAULT_MASK        (_MK_MASK_CONST(0x1)
#define SATA0_FUSE_0_AHCI_POWER_DIS_YES                    _MK_ENUM_CONST(0x00000001)                                                       // R---V
#define SATA0_FUSE_0_AHCI_POWER_DIS_NO                     _MK_ENUM_CONST(0x00000000)                                                       // R-W-V
#define SATA0_FUSE_0_RSVD_5_SHIFT                           _MK_SHIFT_CONST(5)                                                              // C---F
#define SATA0_FUSE_0_RSVD_5_FIELD                          (_MK_SHIFT_CONST(0x1) << SATA0_FUSE_0_RSVD_5_SHIFT)
#define SATA0_FUSE_0_RSVD_5_RANGE                          5:5
#define SATA0_FUSE_0_RSVD_5_WOFFSET                        0
#define SATA0_FUSE_0_RSVD_5_VAL                            _MK_ENUM_CONST(0x00000000)                                                       // C---V
#define SATA0_FUSE_0_RSVD_6_SHIFT                           _MK_SHIFT_CONST(6)                                                              // C---F
#define SATA0_FUSE_0_RSVD_6_FIELD                          (_MK_SHIFT_CONST(0x1) << SATA0_FUSE_0_RSVD_6_SHIFT)
#define SATA0_FUSE_0_RSVD_6_RANGE                          6:6
#define SATA0_FUSE_0_RSVD_6_WOFFSET                        0
#define SATA0_FUSE_0_RSVD_6_VAL                            _MK_ENUM_CONST(0x00000000)                                                       // C---V
#define SATA0_FUSE_0_RSVD_7_SHIFT                           _MK_SHIFT_CONST(7)                                                              // C---F
#define SATA0_FUSE_0_RSVD_7_FIELD                          (_MK_SHIFT_CONST(0x1) << SATA0_FUSE_0_RSVD_7_SHIFT)
#define SATA0_FUSE_0_RSVD_7_RANGE                          7:7
#define SATA0_FUSE_0_RSVD_7_WOFFSET                        0
#define SATA0_FUSE_0_RSVD_7_VAL                            _MK_ENUM_CONST(0x00000000)                                                       // C---V
#define SATA0_FUSE_0_PORTS_0_1_DIS_SHIFT                    _MK_SHIFT_CONST(8)                                                              // R-W-F
#define SATA0_FUSE_0_PORTS_0_1_DIS_FIELD                   (_MK_SHIFT_CONST(0x1) << SATA0_FUSE_0_PORTS_0_1_DIS_SHIFT)
#define SATA0_FUSE_0_PORTS_0_1_DIS_RANGE                   8:8
#define SATA0_FUSE_0_PORTS_0_1_DIS_WOFFSET                 0
#define SATA0_FUSE_0_PORTS_0_1_DIS_DEFAULT                 (_MK_MASK_CONST(0x00000000)
#define SATA0_FUSE_0_PORTS_0_1_DIS_DEFAULT_MASK            (_MK_MASK_CONST(0x1)
#define SATA0_FUSE_0_PORTS_0_1_DIS_SW_DEFAULT              (_MK_MASK_CONST(0x00000000)
#define SATA0_FUSE_0_PORTS_0_1_DIS_SW_DEFAULT_MASK         (_MK_MASK_CONST(0x1)
#define SATA0_FUSE_0_PORTS_0_1_DIS_YES                     _MK_ENUM_CONST(0x00000001)                                                       // R---V
#define SATA0_FUSE_0_PORTS_0_1_DIS_NO                      _MK_ENUM_CONST(0x00000000)                                                       // R-W-V
#define SATA0_FUSE_0_PORTS_2_3_DIS_SHIFT                    _MK_SHIFT_CONST(9)                                                              // R-W-F
#define SATA0_FUSE_0_PORTS_2_3_DIS_FIELD                   (_MK_SHIFT_CONST(0x1) << SATA0_FUSE_0_PORTS_2_3_DIS_SHIFT)
#define SATA0_FUSE_0_PORTS_2_3_DIS_RANGE                   9:9
#define SATA0_FUSE_0_PORTS_2_3_DIS_WOFFSET                 0
#define SATA0_FUSE_0_PORTS_2_3_DIS_DEFAULT                 (_MK_MASK_CONST(0x00000000)
#define SATA0_FUSE_0_PORTS_2_3_DIS_DEFAULT_MASK            (_MK_MASK_CONST(0x1)
#define SATA0_FUSE_0_PORTS_2_3_DIS_SW_DEFAULT              (_MK_MASK_CONST(0x00000000)
#define SATA0_FUSE_0_PORTS_2_3_DIS_SW_DEFAULT_MASK         (_MK_MASK_CONST(0x1)
#define SATA0_FUSE_0_PORTS_2_3_DIS_YES                     _MK_ENUM_CONST(0x00000001)                                                       // R---V
#define SATA0_FUSE_0_PORTS_2_3_DIS_NO                      _MK_ENUM_CONST(0x00000000)                                                       // R-W-V
#define SATA0_FUSE_0_RAID_FUNCTION_DIS_SHIFT                _MK_SHIFT_CONST(10)                                                             // R---F
#define SATA0_FUSE_0_RAID_FUNCTION_DIS_FIELD               (_MK_SHIFT_CONST(0x7) << SATA0_FUSE_0_RAID_FUNCTION_DIS_SHIFT)
#define SATA0_FUSE_0_RAID_FUNCTION_DIS_RANGE               12:10
#define SATA0_FUSE_0_RAID_FUNCTION_DIS_WOFFSET             0
#define SATA0_FUSE_0_RSVD_13_SHIFT                          _MK_SHIFT_CONST(13)                                                             // C---F
#define SATA0_FUSE_0_RSVD_13_FIELD                         (_MK_SHIFT_CONST(0x1) << SATA0_FUSE_0_RSVD_13_SHIFT)
#define SATA0_FUSE_0_RSVD_13_RANGE                         13:13
#define SATA0_FUSE_0_RSVD_13_WOFFSET                       0
#define SATA0_FUSE_0_RSVD_13_VAL                           _MK_ENUM_CONST(0x00000000)                                                       // C---V
#define SATA0_FUSE_0_AHCI_SW_SHIFT                          _MK_SHIFT_CONST(14)                                                             // R---F
#define SATA0_FUSE_0_AHCI_SW_FIELD                         (_MK_SHIFT_CONST(0xf) << SATA0_FUSE_0_AHCI_SW_SHIFT)
#define SATA0_FUSE_0_AHCI_SW_RANGE                         17:14
#define SATA0_FUSE_0_AHCI_SW_WOFFSET                       0
#define SATA0_FUSE_0_AHCI_ESATA_DIS_SHIFT                   _MK_SHIFT_CONST(18)                                                             // R-W-F
#define SATA0_FUSE_0_AHCI_ESATA_DIS_FIELD                  (_MK_SHIFT_CONST(0x3f) << SATA0_FUSE_0_AHCI_ESATA_DIS_SHIFT)
#define SATA0_FUSE_0_AHCI_ESATA_DIS_RANGE                  23:18
#define SATA0_FUSE_0_AHCI_ESATA_DIS_WOFFSET                0
#define SATA0_FUSE_0_AHCI_ESATA_DIS_DEFAULT                (_MK_MASK_CONST(0x00000000)
#define SATA0_FUSE_0_AHCI_ESATA_DIS_DEFAULT_MASK           (_MK_MASK_CONST(0x3f)
#define SATA0_FUSE_0_AHCI_ESATA_DIS_SW_DEFAULT             (_MK_MASK_CONST(0x00000000)
#define SATA0_FUSE_0_AHCI_ESATA_DIS_SW_DEFAULT_MASK        (_MK_MASK_CONST(0x3f)
#define SATA0_FUSE_0_AHCI_ESATA_DIS_YES                    _MK_ENUM_CONST(0x0000003F)                                                       // R---V
#define SATA0_FUSE_0_AHCI_ESATA_DIS_NO                     _MK_ENUM_CONST(0x00000000)                                                       // R-W-V
#define SATA0_FUSE_0_RSVD_31_24_SHIFT                       _MK_SHIFT_CONST(24)                                                             // C---F
#define SATA0_FUSE_0_RSVD_31_24_FIELD                      (_MK_SHIFT_CONST(0xff) << SATA0_FUSE_0_RSVD_31_24_SHIFT)
#define SATA0_FUSE_0_RSVD_31_24_RANGE                      31:24
#define SATA0_FUSE_0_RSVD_31_24_WOFFSET                    0
#define SATA0_FUSE_0_RSVD_31_24_VAL                        _MK_ENUM_CONST(0x00000000)                                                       // C---V
// .define T_SATA0_FEATURE                                  0x00000498 /* RW-4R */
// /*SATA_INCLUDES_AES*/
// /*SATA_INCLUDES_AES*/
// 
// .LABEL PUBLIC
// 
// 
// .LABEL PRIVATE INT_REL
// .TITLE MISC CTL1
// 
// .FIELD ADNVCD_SPD_NEGO
// ADNVCD_SPD_NEGO turns on an advanced way of detecting sata speeds. SATA will mix detecting
// the two supported speeds. Otherwise it detects gen2 first and then gen1.
// 
// .FIELD BLK_NONPIO_IDP
// BLK_NONPIO_IDP is used to suppress the nonpio read in the case of idp read. At default 1
// value the second read will be blocked. At 0 both reads will occur.
// 
// 31           24 23           16 15            8 7             0
// .-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-.
// |                                                               | CYA1
// +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
// 
#define SATA0_CYA1_0                                       0x000004A0                                                                       // RWW4R
#define SATA0_CYA1_0_SECURE                                0
#define SATA0_CYA1_0_WORD_COUNT                            1
#define SATA0_CYA1_0_RESET_VAL                             0x0
#define SATA0_CYA1_0_RESET_MASK                            0x0
#define SATA0_CYA1_0_SW_DEFAULT_VAL                        0x0
#define SATA0_CYA1_0_SW_DEFAULT_MASK                       0x0
#define SATA0_CYA1_0_READ_MASK                             0x7ffffe01
#define SATA0_CYA1_0_WRITE_MASK                            0x201
#define SATA0_CYA1_0_SATA_ADNVCD_SPD_NEGO_SHIFT             _MK_SHIFT_CONST(0)                                                              // RWCVF
#define SATA0_CYA1_0_SATA_ADNVCD_SPD_NEGO_FIELD            (_MK_SHIFT_CONST(0x1) << SATA0_CYA1_0_SATA_ADNVCD_SPD_NEGO_SHIFT)
#define SATA0_CYA1_0_SATA_ADNVCD_SPD_NEGO_RANGE            0:0
#define SATA0_CYA1_0_SATA_ADNVCD_SPD_NEGO_WOFFSET          0
#define SATA0_CYA1_0_SATA_ADNVCD_SPD_NEGO_YES              _MK_ENUM_CONST(0x00000001)                                                       // RWC-V
#define SATA0_CYA1_0_SATA_ADNVCD_SPD_NEGO_NO               _MK_ENUM_CONST(0x00000000)                                                       // RW--V
#define SATA0_CYA1_0_BLK_NONPIO_IDP_SHIFT                   _MK_SHIFT_CONST(9)                                                              // RWWVF
#define SATA0_CYA1_0_BLK_NONPIO_IDP_FIELD                  (_MK_SHIFT_CONST(0x1) << SATA0_CYA1_0_BLK_NONPIO_IDP_SHIFT)
#define SATA0_CYA1_0_BLK_NONPIO_IDP_RANGE                  9:9
#define SATA0_CYA1_0_BLK_NONPIO_IDP_WOFFSET                0
#define SATA0_CYA1_0_BLK_NONPIO_IDP_DEFAULT                (_MK_MASK_CONST(0x00000001)
#define SATA0_CYA1_0_BLK_NONPIO_IDP_DEFAULT_MASK           (_MK_MASK_CONST(0x1)
#define SATA0_CYA1_0_BLK_NONPIO_IDP_SW_DEFAULT             (_MK_MASK_CONST(0x00000001)
#define SATA0_CYA1_0_BLK_NONPIO_IDP_SW_DEFAULT_MASK        (_MK_MASK_CONST(0x1)
#define SATA0_CYA1_0_RSVD_30_10_SHIFT                       _MK_SHIFT_CONST(10)                                                             // C--VF
#define SATA0_CYA1_0_RSVD_30_10_FIELD                      (_MK_SHIFT_CONST(0x1fffff) << SATA0_CYA1_0_RSVD_30_10_SHIFT)
#define SATA0_CYA1_0_RSVD_30_10_RANGE                      30:10
#define SATA0_CYA1_0_RSVD_30_10_WOFFSET                    0
#define SATA0_CYA1_0_RSVD_30_10_VAL                        _MK_ENUM_CONST(0x00000000)                                                       // C---V
// .define T_SATA0_CTL1                                   0x000004A0 /* RWW4R */
// 
// // SATA0_CTRLR
// 
// 
// 
// 
// 
// .LABEL PUBLIC INT_REL
// .LABEL PRIVATE INT_REL
// 
// .TITLE BKDOOR_CC
// This reg is used to backdoor update programming interface field and class code of
// reg at address 0x8 (T_SATA0_CFG_2[15:8]).
// Note that default value of the programming interface field is 0x85 for SATA0 and
// 0x8A for SATA1.
// 
// To update the programming interface field, this is what needs to be done by BIOS:
// 1. Read T_SATA0_CFG_SATA_BACKDOOR_PROG_IF_EN - Address 54C
// 2. Write 1 to T_SATA0_CFG_SATA_BACKDOOR_PROG_IF_EN
// 3. Write the desired programming interface value to T_SATA0_BKDOOR_CC[15:8]
// 4. Restore T_SATA0_CFG_SATA_BACKDOOR_PROG_IF_EN to the value read in step#1
// 
// 31           24 23           16 15            8 7             0
// .-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-.
// |                                                               | BKDOOR_CC
// +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
#define SATA0_BKDOOR_CC_0                                  0x000004A4                                                                       // RWC4R
#define SATA0_BKDOOR_CC_0_SECURE                           0
#define SATA0_BKDOOR_CC_0_WORD_COUNT                       1
#define SATA0_BKDOOR_CC_0_RESET_VAL                        0x0
#define SATA0_BKDOOR_CC_0_RESET_MASK                       0x0
#define SATA0_BKDOOR_CC_0_SW_DEFAULT_VAL                   0x0
#define SATA0_BKDOOR_CC_0_SW_DEFAULT_MASK                  0x0
#define SATA0_BKDOOR_CC_0_READ_MASK                        0xffffffff
#define SATA0_BKDOOR_CC_0_WRITE_MASK                       0xffffff00
#define SATA0_BKDOOR_CC_0_CLASS_CODE_SHIFT                  _MK_SHIFT_CONST(16)                                                             // RWC-F
#define SATA0_BKDOOR_CC_0_CLASS_CODE_FIELD                 (_MK_SHIFT_CONST(0xffff) << SATA0_BKDOOR_CC_0_CLASS_CODE_SHIFT)
#define SATA0_BKDOOR_CC_0_CLASS_CODE_RANGE                 31:16
#define SATA0_BKDOOR_CC_0_CLASS_CODE_WOFFSET               0
#define SATA0_BKDOOR_CC_0_CLASS_CODE__NOPRDCHK             _MK_ENUM_CONST(0x00000001)                                                       // ----V
#define SATA0_BKDOOR_CC_0_CLASS_CODE_INIT                  _MK_ENUM_CONST(0x00000101)                                                       // RWC-V
#define SATA0_BKDOOR_CC_0_PROG_IF_SHIFT                     _MK_SHIFT_CONST(8)                                                              // RWC-F
#define SATA0_BKDOOR_CC_0_PROG_IF_FIELD                    (_MK_SHIFT_CONST(0xff) << SATA0_BKDOOR_CC_0_PROG_IF_SHIFT)
#define SATA0_BKDOOR_CC_0_PROG_IF_RANGE                    15:8
#define SATA0_BKDOOR_CC_0_PROG_IF_WOFFSET                  0
#define SATA0_BKDOOR_CC_0_PROG_IF__NOPRDCHK                _MK_ENUM_CONST(0x00000001)                                                       // ----V
#define SATA0_BKDOOR_CC_0_PROG_IF_INIT                     _MK_ENUM_CONST(0x00000085)                                                       // RWC-V
#define SATA0_BKDOOR_CC_0_RSVD_0_SHIFT                      _MK_SHIFT_CONST(0)                                                              // C--VF
#define SATA0_BKDOOR_CC_0_RSVD_0_FIELD                     (_MK_SHIFT_CONST(0xff) << SATA0_BKDOOR_CC_0_RSVD_0_SHIFT)
#define SATA0_BKDOOR_CC_0_RSVD_0_RANGE                     7:0
#define SATA0_BKDOOR_CC_0_RSVD_0_WOFFSET                   0
#define SATA0_BKDOOR_CC_0_RSVD_0_VAL                       _MK_ENUM_CONST(0x00000000)                                                       // C---V
// 
// .LABEL PUBLIC
// .LABEL INT_REL
// .TITLE SATA_CFG_CTRL_1
// .FIELD 48BIT_ADDRESS_DISABLE
// 48BIT_ADDRESS_DISABLE is used to disable 48-bit addressing mode.
// The SATA implementation of 48-bit addressing is such that this bit is no longer needed.
// It can be removed safely and is currently ignored in SATA.
// 
// .FIELD SATA_CAP
// This bit controls whether or not SATA capability is enabled or not. By default its enabled.
// 
// 31           24 23           16 15            8 7             0
// .-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-.
// |                                                               | SATA_CFG_CTRL_1
// +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
// .LABEL INT_REL
#define SATA0_CFG_CTRL_1_0                                 0x000004A8                                                                       // RWC4R
#define SATA0_CFG_CTRL_1_0_SECURE                          0
#define SATA0_CFG_CTRL_1_0_WORD_COUNT                      1
#define SATA0_CFG_CTRL_1_0_RESET_VAL                       0x0
#define SATA0_CFG_CTRL_1_0_RESET_MASK                      0x0
#define SATA0_CFG_CTRL_1_0_SW_DEFAULT_VAL                  0x0
#define SATA0_CFG_CTRL_1_0_SW_DEFAULT_MASK                 0x0
#define SATA0_CFG_CTRL_1_0_READ_MASK                       0x3
#define SATA0_CFG_CTRL_1_0_WRITE_MASK                      0x3
#define SATA0_CFG_CTRL_1_0_48BIT_ADDRESS_DISABLE_SHIFT      _MK_SHIFT_CONST(0)                                                              // RWCVF
#define SATA0_CFG_CTRL_1_0_48BIT_ADDRESS_DISABLE_FIELD     (_MK_SHIFT_CONST(0x1) << SATA0_CFG_CTRL_1_0_48BIT_ADDRESS_DISABLE_SHIFT)
#define SATA0_CFG_CTRL_1_0_48BIT_ADDRESS_DISABLE_RANGE     0:0
#define SATA0_CFG_CTRL_1_0_48BIT_ADDRESS_DISABLE_WOFFSET   0
#define SATA0_CFG_CTRL_1_0_48BIT_ADDRESS_DISABLE_NO        _MK_ENUM_CONST(0x00000000)                                                       // RWC-V
#define SATA0_CFG_CTRL_1_0_48BIT_ADDRESS_DISABLE_YES       _MK_ENUM_CONST(0x00000001)                                                       // RW--V
#define SATA0_CFG_CTRL_1_0_SATA_CAP_SHIFT                   _MK_SHIFT_CONST(1)                                                              // RWCVF
#define SATA0_CFG_CTRL_1_0_SATA_CAP_FIELD                  (_MK_SHIFT_CONST(0x1) << SATA0_CFG_CTRL_1_0_SATA_CAP_SHIFT)
#define SATA0_CFG_CTRL_1_0_SATA_CAP_RANGE                  1:1
#define SATA0_CFG_CTRL_1_0_SATA_CAP_WOFFSET                0
#define SATA0_CFG_CTRL_1_0_SATA_CAP_DISABLE                _MK_ENUM_CONST(0x0000001)                                                        // RW--V
#define SATA0_CFG_CTRL_1_0_SATA_CAP_ENABLE                 _MK_ENUM_CONST(0x0000000)                                                        // RWC-V
// 
// 
// 
// .LABEL PUBLIC
// 
// 
// .LABEL PRIVATE INT_REL
// .TITLE CFG_POWER_GATE
// .FIELD ENTER_PG
// SW writes this bit to one when it wants the controller to enter Power Gating
// HW will write it back to zero
// 
// .FIELD POWER_UNGATE_COMP
// SW writes this bit to one when SW has restored all the registers necessary
// HW will write it back to zero
// 
// .LABEL PRIVATE INT_REL
// .FIELD SM2SATA_PG_INFO
// Indicates the data stored in SM unit - for now it has nothing
// 
//  31                           16 15                            0
// .-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-.
// |0                           0|                                 | CFG_POWER_GATE
// +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
#define SATA0_CFG_POWER_GATE_0                             0x000004AC                                                                       // RWW4R
#define SATA0_CFG_POWER_GATE_0_SECURE                      0
#define SATA0_CFG_POWER_GATE_0_WORD_COUNT                  1
#define SATA0_CFG_POWER_GATE_0_RESET_VAL                   0x0
#define SATA0_CFG_POWER_GATE_0_RESET_MASK                  0x0
#define SATA0_CFG_POWER_GATE_0_SW_DEFAULT_VAL              0x0
#define SATA0_CFG_POWER_GATE_0_SW_DEFAULT_MASK             0x0
#define SATA0_CFG_POWER_GATE_0_READ_MASK                   0xffffffff
#define SATA0_CFG_POWER_GATE_0_WRITE_MASK                  0xac0003
#define SATA0_CFG_POWER_GATE_0_ENTER_PG_SHIFT               _MK_SHIFT_CONST(0)                                                              // RWWVF
#define SATA0_CFG_POWER_GATE_0_ENTER_PG_FIELD              (_MK_SHIFT_CONST(0x1) << SATA0_CFG_POWER_GATE_0_ENTER_PG_SHIFT)
#define SATA0_CFG_POWER_GATE_0_ENTER_PG_RANGE              0:0
#define SATA0_CFG_POWER_GATE_0_ENTER_PG_WOFFSET            0
#define SATA0_CFG_POWER_GATE_0_ENTER_PG_DEFAULT            (_MK_MASK_CONST(0x00000000)
#define SATA0_CFG_POWER_GATE_0_ENTER_PG_DEFAULT_MASK       (_MK_MASK_CONST(0x1)
#define SATA0_CFG_POWER_GATE_0_ENTER_PG_SW_DEFAULT         (_MK_MASK_CONST(0x00000000)
#define SATA0_CFG_POWER_GATE_0_ENTER_PG_SW_DEFAULT_MASK    (_MK_MASK_CONST(0x1)
#define SATA0_CFG_POWER_GATE_0_ENTER_PG_YES                _MK_ENUM_CONST(0x00000001)                                                       // RW--V
#define SATA0_CFG_POWER_GATE_0_ENTER_PG_NO                 _MK_ENUM_CONST(0x00000000)                                                       // RWW-V
#define SATA0_CFG_POWER_GATE_0_ENTER_PG_SET                _MK_ENUM_CONST(0x00000001)                                                       // -W--T
#define SATA0_CFG_POWER_GATE_0_POWER_UNGATE_COMP_SHIFT      _MK_SHIFT_CONST(1)                                                              // RWW-F
#define SATA0_CFG_POWER_GATE_0_POWER_UNGATE_COMP_FIELD     (_MK_SHIFT_CONST(0x1) << SATA0_CFG_POWER_GATE_0_POWER_UNGATE_COMP_SHIFT)
#define SATA0_CFG_POWER_GATE_0_POWER_UNGATE_COMP_RANGE     1:1
#define SATA0_CFG_POWER_GATE_0_POWER_UNGATE_COMP_WOFFSET   0
#define SATA0_CFG_POWER_GATE_0_POWER_UNGATE_COMP_DEFAULT   (_MK_MASK_CONST(0x00000000)
#define SATA0_CFG_POWER_GATE_0_POWER_UNGATE_COMP_DEFAULT_MASK (_MK_MASK_CONST(0x1)
#define SATA0_CFG_POWER_GATE_0_POWER_UNGATE_COMP_SW_DEFAULT (_MK_MASK_CONST(0x00000000)
#define SATA0_CFG_POWER_GATE_0_POWER_UNGATE_COMP_SW_DEFAULT_MASK (_MK_MASK_CONST(0x1)
#define SATA0_CFG_POWER_GATE_0_POWER_UNGATE_COMP_YES       _MK_ENUM_CONST(0x00000001)                                                       // RW--V
#define SATA0_CFG_POWER_GATE_0_POWER_UNGATE_COMP_NO        _MK_ENUM_CONST(0x00000000)                                                       // RWW-V
#define SATA0_CFG_POWER_GATE_0_POWER_UNGATE_COMP_SET       _MK_ENUM_CONST(0x00000001)                                                       // -W--T
#define SATA0_CFG_POWER_GATE_0_SM2SATA_PG_INFO_SHIFT        _MK_SHIFT_CONST(2)                                                              // R-W-F
#define SATA0_CFG_POWER_GATE_0_SM2SATA_PG_INFO_FIELD       (_MK_SHIFT_CONST(0xffff) << SATA0_CFG_POWER_GATE_0_SM2SATA_PG_INFO_SHIFT)
#define SATA0_CFG_POWER_GATE_0_SM2SATA_PG_INFO_RANGE       17:2
#define SATA0_CFG_POWER_GATE_0_SM2SATA_PG_INFO_WOFFSET     0
#define SATA0_CFG_POWER_GATE_0_SM2SATA_PG_INFO_DEFAULT     (_MK_MASK_CONST(0x00000000)
#define SATA0_CFG_POWER_GATE_0_SM2SATA_PG_INFO_DEFAULT_MASK (_MK_MASK_CONST(0xffff)
#define SATA0_CFG_POWER_GATE_0_SM2SATA_PG_INFO_SW_DEFAULT  (_MK_MASK_CONST(0x00000000)
#define SATA0_CFG_POWER_GATE_0_SM2SATA_PG_INFO_SW_DEFAULT_MASK (_MK_MASK_CONST(0xffff)
#define SATA0_CFG_POWER_GATE_0_HW_WAKEUP_SUPPORT_SHIFT      _MK_SHIFT_CONST(18)                                                             // RWW-F
#define SATA0_CFG_POWER_GATE_0_HW_WAKEUP_SUPPORT_FIELD     (_MK_SHIFT_CONST(0x1) << SATA0_CFG_POWER_GATE_0_HW_WAKEUP_SUPPORT_SHIFT)
#define SATA0_CFG_POWER_GATE_0_HW_WAKEUP_SUPPORT_RANGE     18:18
#define SATA0_CFG_POWER_GATE_0_HW_WAKEUP_SUPPORT_WOFFSET   0
#define SATA0_CFG_POWER_GATE_0_HW_WAKEUP_SUPPORT_DEFAULT   (_MK_MASK_CONST(0x00000000)
#define SATA0_CFG_POWER_GATE_0_HW_WAKEUP_SUPPORT_DEFAULT_MASK (_MK_MASK_CONST(0x1)
#define SATA0_CFG_POWER_GATE_0_HW_WAKEUP_SUPPORT_SW_DEFAULT (_MK_MASK_CONST(0x00000000)
#define SATA0_CFG_POWER_GATE_0_HW_WAKEUP_SUPPORT_SW_DEFAULT_MASK (_MK_MASK_CONST(0x1)
#define SATA0_CFG_POWER_GATE_0_HW_WAKEUP_SUPPORT_YES       _MK_ENUM_CONST(0x00000001)                                                       // RW--V
#define SATA0_CFG_POWER_GATE_0_HW_WAKEUP_SUPPORT_NO        _MK_ENUM_CONST(0x00000000)                                                       // RWW-V
#define SATA0_CFG_POWER_GATE_0_PADS_POWER_DOWN_SHIFT        _MK_SHIFT_CONST(19)                                                             // RWW-F
#define SATA0_CFG_POWER_GATE_0_PADS_POWER_DOWN_FIELD       (_MK_SHIFT_CONST(0x1) << SATA0_CFG_POWER_GATE_0_PADS_POWER_DOWN_SHIFT)
#define SATA0_CFG_POWER_GATE_0_PADS_POWER_DOWN_RANGE       19:19
#define SATA0_CFG_POWER_GATE_0_PADS_POWER_DOWN_WOFFSET     0
#define SATA0_CFG_POWER_GATE_0_PADS_POWER_DOWN_DEFAULT     (_MK_MASK_CONST(0x00000000)
#define SATA0_CFG_POWER_GATE_0_PADS_POWER_DOWN_DEFAULT_MASK (_MK_MASK_CONST(0x1)
#define SATA0_CFG_POWER_GATE_0_PADS_POWER_DOWN_SW_DEFAULT  (_MK_MASK_CONST(0x00000000)
#define SATA0_CFG_POWER_GATE_0_PADS_POWER_DOWN_SW_DEFAULT_MASK (_MK_MASK_CONST(0x1)
#define SATA0_CFG_POWER_GATE_0_PADS_POWER_DOWN_INIT        _MK_ENUM_CONST(0x00000000)                                                       // RWW-V
#define SATA0_CFG_POWER_GATE_0_COUNT_FOR_PADS_DONE_SHIFT    _MK_SHIFT_CONST(20)                                                             // R-W-F
#define SATA0_CFG_POWER_GATE_0_COUNT_FOR_PADS_DONE_FIELD   (_MK_SHIFT_CONST(0x1) << SATA0_CFG_POWER_GATE_0_COUNT_FOR_PADS_DONE_SHIFT)
#define SATA0_CFG_POWER_GATE_0_COUNT_FOR_PADS_DONE_RANGE   20:20
#define SATA0_CFG_POWER_GATE_0_COUNT_FOR_PADS_DONE_WOFFSET 0
#define SATA0_CFG_POWER_GATE_0_COUNT_FOR_PADS_DONE_DEFAULT (_MK_MASK_CONST(0x00000000)
#define SATA0_CFG_POWER_GATE_0_COUNT_FOR_PADS_DONE_DEFAULT_MASK (_MK_MASK_CONST(0x1)
#define SATA0_CFG_POWER_GATE_0_COUNT_FOR_PADS_DONE_SW_DEFAULT (_MK_MASK_CONST(0x00000000)
#define SATA0_CFG_POWER_GATE_0_COUNT_FOR_PADS_DONE_SW_DEFAULT_MASK (_MK_MASK_CONST(0x1)
#define SATA0_CFG_POWER_GATE_0_COUNT_FOR_PADS_DONE_INIT    _MK_ENUM_CONST(0x00000000)                                                       // R-W-V
#define SATA0_CFG_POWER_GATE_0_STOP_INTERRUPTS_SHIFT        _MK_SHIFT_CONST(21)                                                             // RWWVF
#define SATA0_CFG_POWER_GATE_0_STOP_INTERRUPTS_FIELD       (_MK_SHIFT_CONST(0x1) << SATA0_CFG_POWER_GATE_0_STOP_INTERRUPTS_SHIFT)
#define SATA0_CFG_POWER_GATE_0_STOP_INTERRUPTS_RANGE       21:21
#define SATA0_CFG_POWER_GATE_0_STOP_INTERRUPTS_WOFFSET     0
#define SATA0_CFG_POWER_GATE_0_STOP_INTERRUPTS_DEFAULT     (_MK_MASK_CONST(0x000000000)
#define SATA0_CFG_POWER_GATE_0_STOP_INTERRUPTS_DEFAULT_MASK (_MK_MASK_CONST(0x1)
#define SATA0_CFG_POWER_GATE_0_STOP_INTERRUPTS_SW_DEFAULT  (_MK_MASK_CONST(0x000000000)
#define SATA0_CFG_POWER_GATE_0_STOP_INTERRUPTS_SW_DEFAULT_MASK (_MK_MASK_CONST(0x1)
#define SATA0_CFG_POWER_GATE_0_STOP_INTERRUPTS_INIT        _MK_ENUM_CONST(0x000000000)                                                      // RWW-V
#define SATA0_CFG_POWER_GATE_0_PHY_NOT_IN_SLUMBER_SHIFT     _MK_SHIFT_CONST(22)                                                             // R-WVF
#define SATA0_CFG_POWER_GATE_0_PHY_NOT_IN_SLUMBER_FIELD    (_MK_SHIFT_CONST(0x1) << SATA0_CFG_POWER_GATE_0_PHY_NOT_IN_SLUMBER_SHIFT)
#define SATA0_CFG_POWER_GATE_0_PHY_NOT_IN_SLUMBER_RANGE    22:22
#define SATA0_CFG_POWER_GATE_0_PHY_NOT_IN_SLUMBER_WOFFSET  0
#define SATA0_CFG_POWER_GATE_0_PHY_NOT_IN_SLUMBER_DEFAULT  (_MK_MASK_CONST(0x000000000)
#define SATA0_CFG_POWER_GATE_0_PHY_NOT_IN_SLUMBER_DEFAULT_MASK (_MK_MASK_CONST(0x1)
#define SATA0_CFG_POWER_GATE_0_PHY_NOT_IN_SLUMBER_SW_DEFAULT (_MK_MASK_CONST(0x000000000)
#define SATA0_CFG_POWER_GATE_0_PHY_NOT_IN_SLUMBER_SW_DEFAULT_MASK (_MK_MASK_CONST(0x1)
#define SATA0_CFG_POWER_GATE_0_PHY_NOT_IN_SLUMBER_INIT     _MK_ENUM_CONST(0x000000000)                                                      // R-W-V
#define SATA0_CFG_POWER_GATE_0_SSTS_RESTORED_SHIFT          _MK_SHIFT_CONST(23)                                                             // RWWVF
#define SATA0_CFG_POWER_GATE_0_SSTS_RESTORED_FIELD         (_MK_SHIFT_CONST(0x1) << SATA0_CFG_POWER_GATE_0_SSTS_RESTORED_SHIFT)
#define SATA0_CFG_POWER_GATE_0_SSTS_RESTORED_RANGE         23:23
#define SATA0_CFG_POWER_GATE_0_SSTS_RESTORED_WOFFSET       0
#define SATA0_CFG_POWER_GATE_0_SSTS_RESTORED_DEFAULT       (_MK_MASK_CONST(0x000000000)
#define SATA0_CFG_POWER_GATE_0_SSTS_RESTORED_DEFAULT_MASK  (_MK_MASK_CONST(0x1)
#define SATA0_CFG_POWER_GATE_0_SSTS_RESTORED_SW_DEFAULT    (_MK_MASK_CONST(0x000000000)
#define SATA0_CFG_POWER_GATE_0_SSTS_RESTORED_SW_DEFAULT_MASK (_MK_MASK_CONST(0x1)
#define SATA0_CFG_POWER_GATE_0_SSTS_RESTORED_YES           _MK_ENUM_CONST(0x000000001)                                                      // RW--V
#define SATA0_CFG_POWER_GATE_0_RSVD_SHIFT                   _MK_SHIFT_CONST(24)                                                             // C---F
#define SATA0_CFG_POWER_GATE_0_RSVD_FIELD                  (_MK_SHIFT_CONST(0xff) << SATA0_CFG_POWER_GATE_0_RSVD_SHIFT)
#define SATA0_CFG_POWER_GATE_0_RSVD_RANGE                  31:24
#define SATA0_CFG_POWER_GATE_0_RSVD_WOFFSET                0
#define SATA0_CFG_POWER_GATE_0_RSVD_VAL                    _MK_ENUM_CONST(0x00000000)                                                       // C---V
// 
// .LABEL PRIVATE INT_REL
// .LABEL PRIVATE INT_REL
// 
// .LABEL PRIVATE INT_REL
// 
// .LABEL PRIVATE INT_REL
// 
// .LABEL PRIVATE INT_REL
// 
// .LABEL PRIVATE INT_REL
// 
// 
// .LABEL PUBLIC
// 
// .LABEL PRIVATE INT_REL
// .TITLE CFG_CTL_GLUE
// .FIELD FIX_FPCI_WRDAT
// When set to one adds a clock delay which is necessary for correct operation
// This bit will be removed once the platform emulation could do writes to BAR5 space
// 
// .FIELD SATA0_FPCI_CLK_SLCG_OVERRIDE
// Program this bit before enabling the DEVCLK SHUTDOWN/CLAMPING Feature.
// 
// .FIELD SATA_FPCI_ALWAYS_CLK_SLCG_OVERRIDE
// Program this bit before enabling the DEVCLK SHUTDOWN/CLAMPING Feature.
// 
// .FIELD SATA_FPCI_CLK_SLCG_OVERRIDE
// Program this bit before enabling the DEVCLK SHUTDOWN/CLAMPING Feature.
// 
// .FIELD SATA_FPCI_CH1_CLK_SLCG_OVERRIDE
// Program this bit before enabling the DEVCLK SHUTDOWN/CLAMPING Feature.
// 
//  31                           16 15                            0
// .-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-.
// |0                           0|                                 | CFG_CTL_GLUE
// +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
#define SATA0_CFG_CTL_GLUE_0                               0x000004B0                                                                       // RWC4R
#define SATA0_CFG_CTL_GLUE_0_SECURE                        0
#define SATA0_CFG_CTL_GLUE_0_WORD_COUNT                    1
#define SATA0_CFG_CTL_GLUE_0_RESET_VAL                     0x0
#define SATA0_CFG_CTL_GLUE_0_RESET_MASK                    0x0
#define SATA0_CFG_CTL_GLUE_0_SW_DEFAULT_VAL                0x0
#define SATA0_CFG_CTL_GLUE_0_SW_DEFAULT_MASK               0x0
#define SATA0_CFG_CTL_GLUE_0_READ_MASK                     0xffffffff
#define SATA0_CFG_CTL_GLUE_0_WRITE_MASK                    0xffffffff
#define SATA0_CFG_CTL_GLUE_0_FIX_FPCI_WRDAT_SHIFT           _MK_SHIFT_CONST(0)                                                              // RWCVF
#define SATA0_CFG_CTL_GLUE_0_FIX_FPCI_WRDAT_FIELD          (_MK_SHIFT_CONST(0x1) << SATA0_CFG_CTL_GLUE_0_FIX_FPCI_WRDAT_SHIFT)
#define SATA0_CFG_CTL_GLUE_0_FIX_FPCI_WRDAT_RANGE          0:0
#define SATA0_CFG_CTL_GLUE_0_FIX_FPCI_WRDAT_WOFFSET        0
#define SATA0_CFG_CTL_GLUE_0_FIX_FPCI_WRDAT_YES            _MK_ENUM_CONST(0x00000001)                                                       // RWC-V
#define SATA0_CFG_CTL_GLUE_0_FIX_FPCI_WRDAT_NO             _MK_ENUM_CONST(0x00000000)                                                       // RW--V
#define SATA0_CFG_CTL_GLUE_0_USE_OVERRIDE_LOCKDET_SHIFT     _MK_SHIFT_CONST(1)                                                              // RWCVF
#define SATA0_CFG_CTL_GLUE_0_USE_OVERRIDE_LOCKDET_FIELD    (_MK_SHIFT_CONST(0x1) << SATA0_CFG_CTL_GLUE_0_USE_OVERRIDE_LOCKDET_SHIFT)
#define SATA0_CFG_CTL_GLUE_0_USE_OVERRIDE_LOCKDET_RANGE    1:1
#define SATA0_CFG_CTL_GLUE_0_USE_OVERRIDE_LOCKDET_WOFFSET  0
#define SATA0_CFG_CTL_GLUE_0_USE_OVERRIDE_LOCKDET_YES      _MK_ENUM_CONST(0x00000001)                                                       // RWC-V
#define SATA0_CFG_CTL_GLUE_0_USE_OVERRIDE_LOCKDET_NO       _MK_ENUM_CONST(0x00000000)                                                       // RW--V
#define SATA0_CFG_CTL_GLUE_0_OVERRIDE_LOCKDET_FOR_NVA_SHIFT  _MK_SHIFT_CONST(2)                                                              // RWCVF
#define SATA0_CFG_CTL_GLUE_0_OVERRIDE_LOCKDET_FOR_NVA_FIELD (_MK_SHIFT_CONST(0x1) << SATA0_CFG_CTL_GLUE_0_OVERRIDE_LOCKDET_FOR_NVA_SHIFT)
#define SATA0_CFG_CTL_GLUE_0_OVERRIDE_LOCKDET_FOR_NVA_RANGE 2:2
#define SATA0_CFG_CTL_GLUE_0_OVERRIDE_LOCKDET_FOR_NVA_WOFFSET 0
#define SATA0_CFG_CTL_GLUE_0_OVERRIDE_LOCKDET_FOR_NVA_INIT _MK_ENUM_CONST(0x00000000)                                                       // RWC-V
#define SATA0_CFG_CTL_GLUE_0_LOCKDET_OVR_LOGIC_FIX_SHIFT    _MK_SHIFT_CONST(3)                                                              // RWCVF
#define SATA0_CFG_CTL_GLUE_0_LOCKDET_OVR_LOGIC_FIX_FIELD   (_MK_SHIFT_CONST(0x1) << SATA0_CFG_CTL_GLUE_0_LOCKDET_OVR_LOGIC_FIX_SHIFT)
#define SATA0_CFG_CTL_GLUE_0_LOCKDET_OVR_LOGIC_FIX_RANGE   3:3
#define SATA0_CFG_CTL_GLUE_0_LOCKDET_OVR_LOGIC_FIX_WOFFSET 0
#define SATA0_CFG_CTL_GLUE_0_LOCKDET_OVR_LOGIC_FIX_INIT    _MK_ENUM_CONST(0x00000001)                                                       // RWC-V
#define SATA0_CFG_CTL_GLUE_0_HOLD_REQ_DEVCLK_CLAMP_1_SHIFT  _MK_SHIFT_CONST(4)                                                              // RWCVF
#define SATA0_CFG_CTL_GLUE_0_HOLD_REQ_DEVCLK_CLAMP_1_FIELD (_MK_SHIFT_CONST(0x1) << SATA0_CFG_CTL_GLUE_0_HOLD_REQ_DEVCLK_CLAMP_1_SHIFT)
#define SATA0_CFG_CTL_GLUE_0_HOLD_REQ_DEVCLK_CLAMP_1_RANGE 4:4
#define SATA0_CFG_CTL_GLUE_0_HOLD_REQ_DEVCLK_CLAMP_1_WOFFSET 0
#define SATA0_CFG_CTL_GLUE_0_HOLD_REQ_DEVCLK_CLAMP_1_INIT  _MK_ENUM_CONST(0x00000000)                                                       // RWC-V
#define SATA0_CFG_CTL_GLUE_0_HOLD_REQ_DEVCLK_CLAMP_2_SHIFT  _MK_SHIFT_CONST(5)                                                              // RWCVF
#define SATA0_CFG_CTL_GLUE_0_HOLD_REQ_DEVCLK_CLAMP_2_FIELD (_MK_SHIFT_CONST(0x1) << SATA0_CFG_CTL_GLUE_0_HOLD_REQ_DEVCLK_CLAMP_2_SHIFT)
#define SATA0_CFG_CTL_GLUE_0_HOLD_REQ_DEVCLK_CLAMP_2_RANGE 5:5
#define SATA0_CFG_CTL_GLUE_0_HOLD_REQ_DEVCLK_CLAMP_2_WOFFSET 0
#define SATA0_CFG_CTL_GLUE_0_HOLD_REQ_DEVCLK_CLAMP_2_INIT  _MK_ENUM_CONST(0x00000000)                                                       // RWC-V
#define SATA0_CFG_CTL_GLUE_0_RESET_COMMA_DETECTION_CNTR_SHIFT  _MK_SHIFT_CONST(6)                                                              // RWCVF
#define SATA0_CFG_CTL_GLUE_0_RESET_COMMA_DETECTION_CNTR_FIELD (_MK_SHIFT_CONST(0x1) << SATA0_CFG_CTL_GLUE_0_RESET_COMMA_DETECTION_CNTR_SHIFT)
#define SATA0_CFG_CTL_GLUE_0_RESET_COMMA_DETECTION_CNTR_RANGE 6:6
#define SATA0_CFG_CTL_GLUE_0_RESET_COMMA_DETECTION_CNTR_WOFFSET 0
#define SATA0_CFG_CTL_GLUE_0_RESET_COMMA_DETECTION_CNTR_INIT _MK_ENUM_CONST(0x00000001)                                                       // RWC-V
#define SATA0_CFG_CTL_GLUE_0_DEVSLP_WITH_GHC_HR_PXCMD_ST_SHIFT  _MK_SHIFT_CONST(7)                                                              // RWCVF
#define SATA0_CFG_CTL_GLUE_0_DEVSLP_WITH_GHC_HR_PXCMD_ST_FIELD (_MK_SHIFT_CONST(0x1) << SATA0_CFG_CTL_GLUE_0_DEVSLP_WITH_GHC_HR_PXCMD_ST_SHIFT)
#define SATA0_CFG_CTL_GLUE_0_DEVSLP_WITH_GHC_HR_PXCMD_ST_RANGE 7:7
#define SATA0_CFG_CTL_GLUE_0_DEVSLP_WITH_GHC_HR_PXCMD_ST_WOFFSET 0
#define SATA0_CFG_CTL_GLUE_0_DEVSLP_WITH_GHC_HR_PXCMD_ST_INIT _MK_ENUM_CONST(0x00000001)                                                       // RWC-V
#define SATA0_CFG_CTL_GLUE_0_ODD_DWORD_ALIGNMENT_FIX_SHIFT  _MK_SHIFT_CONST(8)                                                              // RWCVF
#define SATA0_CFG_CTL_GLUE_0_ODD_DWORD_ALIGNMENT_FIX_FIELD (_MK_SHIFT_CONST(0x1) << SATA0_CFG_CTL_GLUE_0_ODD_DWORD_ALIGNMENT_FIX_SHIFT)
#define SATA0_CFG_CTL_GLUE_0_ODD_DWORD_ALIGNMENT_FIX_RANGE 8:8
#define SATA0_CFG_CTL_GLUE_0_ODD_DWORD_ALIGNMENT_FIX_WOFFSET 0
#define SATA0_CFG_CTL_GLUE_0_ODD_DWORD_ALIGNMENT_FIX_INIT  _MK_ENUM_CONST(0x00000000)                                                       // RWC-V
#define SATA0_CFG_CTL_GLUE_0_SATA0_FPCI_CLK_SLCG_OVERRIDE_SHIFT  _MK_SHIFT_CONST(9)                                                              // RWCVF
#define SATA0_CFG_CTL_GLUE_0_SATA0_FPCI_CLK_SLCG_OVERRIDE_FIELD (_MK_SHIFT_CONST(0x1) << SATA0_CFG_CTL_GLUE_0_SATA0_FPCI_CLK_SLCG_OVERRIDE_SHIFT)
#define SATA0_CFG_CTL_GLUE_0_SATA0_FPCI_CLK_SLCG_OVERRIDE_RANGE 9:9
#define SATA0_CFG_CTL_GLUE_0_SATA0_FPCI_CLK_SLCG_OVERRIDE_WOFFSET 0
#define SATA0_CFG_CTL_GLUE_0_SATA0_FPCI_CLK_SLCG_OVERRIDE_INIT _MK_ENUM_CONST(0x00000000)                                                       // RWC-V
#define SATA0_CFG_CTL_GLUE_0_SATA_CH1_RX_CLK_SLCG_OVERRIDE_SHIFT  _MK_SHIFT_CONST(10)                                                             // RWCVF
#define SATA0_CFG_CTL_GLUE_0_SATA_CH1_RX_CLK_SLCG_OVERRIDE_FIELD (_MK_SHIFT_CONST(0x1) << SATA0_CFG_CTL_GLUE_0_SATA_CH1_RX_CLK_SLCG_OVERRIDE_SHIFT)
#define SATA0_CFG_CTL_GLUE_0_SATA_CH1_RX_CLK_SLCG_OVERRIDE_RANGE 10:10
#define SATA0_CFG_CTL_GLUE_0_SATA_CH1_RX_CLK_SLCG_OVERRIDE_WOFFSET 0
#define SATA0_CFG_CTL_GLUE_0_SATA_CH1_RX_CLK_SLCG_OVERRIDE_INIT _MK_ENUM_CONST(0x00000000)                                                       // RWC-V
#define SATA0_CFG_CTL_GLUE_0_SATA_CH1_TX_CLK_SLCG_OVERRIDE_SHIFT  _MK_SHIFT_CONST(11)                                                             // RWCVF
#define SATA0_CFG_CTL_GLUE_0_SATA_CH1_TX_CLK_SLCG_OVERRIDE_FIELD (_MK_SHIFT_CONST(0x1) << SATA0_CFG_CTL_GLUE_0_SATA_CH1_TX_CLK_SLCG_OVERRIDE_SHIFT)
#define SATA0_CFG_CTL_GLUE_0_SATA_CH1_TX_CLK_SLCG_OVERRIDE_RANGE 11:11
#define SATA0_CFG_CTL_GLUE_0_SATA_CH1_TX_CLK_SLCG_OVERRIDE_WOFFSET 0
#define SATA0_CFG_CTL_GLUE_0_SATA_CH1_TX_CLK_SLCG_OVERRIDE_INIT _MK_ENUM_CONST(0x00000000)                                                       // RWC-V
#define SATA0_CFG_CTL_GLUE_0_SATA_TX_CLK_SLCG_OVERRIDE_SHIFT  _MK_SHIFT_CONST(12)                                                             // RWCVF
#define SATA0_CFG_CTL_GLUE_0_SATA_TX_CLK_SLCG_OVERRIDE_FIELD (_MK_SHIFT_CONST(0x1) << SATA0_CFG_CTL_GLUE_0_SATA_TX_CLK_SLCG_OVERRIDE_SHIFT)
#define SATA0_CFG_CTL_GLUE_0_SATA_TX_CLK_SLCG_OVERRIDE_RANGE 12:12
#define SATA0_CFG_CTL_GLUE_0_SATA_TX_CLK_SLCG_OVERRIDE_WOFFSET 0
#define SATA0_CFG_CTL_GLUE_0_SATA_TX_CLK_SLCG_OVERRIDE_INIT _MK_ENUM_CONST(0x00000000)                                                       // RWC-V
#define SATA0_CFG_CTL_GLUE_0_SATA_FPCI_ALWAYS_CLK_SLCG_OVERRIDE_SHIFT  _MK_SHIFT_CONST(13)                                                             // RWCVF
#define SATA0_CFG_CTL_GLUE_0_SATA_FPCI_ALWAYS_CLK_SLCG_OVERRIDE_FIELD (_MK_SHIFT_CONST(0x1) << SATA0_CFG_CTL_GLUE_0_SATA_FPCI_ALWAYS_CLK_SLCG_OVERRIDE_SHIFT)
#define SATA0_CFG_CTL_GLUE_0_SATA_FPCI_ALWAYS_CLK_SLCG_OVERRIDE_RANGE 13:13
#define SATA0_CFG_CTL_GLUE_0_SATA_FPCI_ALWAYS_CLK_SLCG_OVERRIDE_WOFFSET 0
#define SATA0_CFG_CTL_GLUE_0_SATA_FPCI_ALWAYS_CLK_SLCG_OVERRIDE_INIT _MK_ENUM_CONST(0x00000000)                                                       // RWC-V
#define SATA0_CFG_CTL_GLUE_0_SATA_FPCI_CLK_SLCG_OVERRIDE_SHIFT  _MK_SHIFT_CONST(14)                                                             // RWCVF
#define SATA0_CFG_CTL_GLUE_0_SATA_FPCI_CLK_SLCG_OVERRIDE_FIELD (_MK_SHIFT_CONST(0x1) << SATA0_CFG_CTL_GLUE_0_SATA_FPCI_CLK_SLCG_OVERRIDE_SHIFT)
#define SATA0_CFG_CTL_GLUE_0_SATA_FPCI_CLK_SLCG_OVERRIDE_RANGE 14:14
#define SATA0_CFG_CTL_GLUE_0_SATA_FPCI_CLK_SLCG_OVERRIDE_WOFFSET 0
#define SATA0_CFG_CTL_GLUE_0_SATA_FPCI_CLK_SLCG_OVERRIDE_INIT _MK_ENUM_CONST(0x00000000)                                                       // RWC-V
#define SATA0_CFG_CTL_GLUE_0_SATA_FPCI_CH1_CLK_SLCG_OVERRIDE_SHIFT  _MK_SHIFT_CONST(15)                                                             // RWCVF
#define SATA0_CFG_CTL_GLUE_0_SATA_FPCI_CH1_CLK_SLCG_OVERRIDE_FIELD (_MK_SHIFT_CONST(0x1) << SATA0_CFG_CTL_GLUE_0_SATA_FPCI_CH1_CLK_SLCG_OVERRIDE_SHIFT)
#define SATA0_CFG_CTL_GLUE_0_SATA_FPCI_CH1_CLK_SLCG_OVERRIDE_RANGE 15:15
#define SATA0_CFG_CTL_GLUE_0_SATA_FPCI_CH1_CLK_SLCG_OVERRIDE_WOFFSET 0
#define SATA0_CFG_CTL_GLUE_0_SATA_FPCI_CH1_CLK_SLCG_OVERRIDE_INIT _MK_ENUM_CONST(0x00000000)                                                       // RWC-V
#define SATA0_CFG_CTL_GLUE_0_SATA_IPFS_CLK_SLCG_OVERRIDE_SHIFT  _MK_SHIFT_CONST(16)                                                             // RWCVF
#define SATA0_CFG_CTL_GLUE_0_SATA_IPFS_CLK_SLCG_OVERRIDE_FIELD (_MK_SHIFT_CONST(0x1) << SATA0_CFG_CTL_GLUE_0_SATA_IPFS_CLK_SLCG_OVERRIDE_SHIFT)
#define SATA0_CFG_CTL_GLUE_0_SATA_IPFS_CLK_SLCG_OVERRIDE_RANGE 16:16
#define SATA0_CFG_CTL_GLUE_0_SATA_IPFS_CLK_SLCG_OVERRIDE_WOFFSET 0
#define SATA0_CFG_CTL_GLUE_0_SATA_IPFS_CLK_SLCG_OVERRIDE_INIT _MK_ENUM_CONST(0x00000000)                                                       // RWC-V
#define SATA0_CFG_CTL_GLUE_0_SATA_UFPCI_CLK_SLCG_OVERRIDE_SHIFT  _MK_SHIFT_CONST(17)                                                             // RWCVF
#define SATA0_CFG_CTL_GLUE_0_SATA_UFPCI_CLK_SLCG_OVERRIDE_FIELD (_MK_SHIFT_CONST(0x1) << SATA0_CFG_CTL_GLUE_0_SATA_UFPCI_CLK_SLCG_OVERRIDE_SHIFT)
#define SATA0_CFG_CTL_GLUE_0_SATA_UFPCI_CLK_SLCG_OVERRIDE_RANGE 17:17
#define SATA0_CFG_CTL_GLUE_0_SATA_UFPCI_CLK_SLCG_OVERRIDE_WOFFSET 0
#define SATA0_CFG_CTL_GLUE_0_SATA_UFPCI_CLK_SLCG_OVERRIDE_INIT _MK_ENUM_CONST(0x00000000)                                                       // RWC-V
#define SATA0_CFG_CTL_GLUE_0_SATA_DFPCI_CLK_SLCG_OVERRIDE_SHIFT  _MK_SHIFT_CONST(18)                                                             // RWCVF
#define SATA0_CFG_CTL_GLUE_0_SATA_DFPCI_CLK_SLCG_OVERRIDE_FIELD (_MK_SHIFT_CONST(0x1) << SATA0_CFG_CTL_GLUE_0_SATA_DFPCI_CLK_SLCG_OVERRIDE_SHIFT)
#define SATA0_CFG_CTL_GLUE_0_SATA_DFPCI_CLK_SLCG_OVERRIDE_RANGE 18:18
#define SATA0_CFG_CTL_GLUE_0_SATA_DFPCI_CLK_SLCG_OVERRIDE_WOFFSET 0
#define SATA0_CFG_CTL_GLUE_0_SATA_DFPCI_CLK_SLCG_OVERRIDE_INIT _MK_ENUM_CONST(0x00000000)                                                       // RWC-V
#define SATA0_CFG_CTL_GLUE_0_SATA_12M_CLK_SLCG_OVERRIDE_SHIFT  _MK_SHIFT_CONST(19)                                                             // RWCVF
#define SATA0_CFG_CTL_GLUE_0_SATA_12M_CLK_SLCG_OVERRIDE_FIELD (_MK_SHIFT_CONST(0x1) << SATA0_CFG_CTL_GLUE_0_SATA_12M_CLK_SLCG_OVERRIDE_SHIFT)
#define SATA0_CFG_CTL_GLUE_0_SATA_12M_CLK_SLCG_OVERRIDE_RANGE 19:19
#define SATA0_CFG_CTL_GLUE_0_SATA_12M_CLK_SLCG_OVERRIDE_WOFFSET 0
#define SATA0_CFG_CTL_GLUE_0_SATA_12M_CLK_SLCG_OVERRIDE_INIT _MK_ENUM_CONST(0x00000000)                                                       // RWC-V
#define SATA0_CFG_CTL_GLUE_0_TX_SYNC_PULSE_WIDTH_SHIFT      _MK_SHIFT_CONST(20)                                                             // RWCVF
#define SATA0_CFG_CTL_GLUE_0_TX_SYNC_PULSE_WIDTH_FIELD     (_MK_SHIFT_CONST(0x1f) << SATA0_CFG_CTL_GLUE_0_TX_SYNC_PULSE_WIDTH_SHIFT)
#define SATA0_CFG_CTL_GLUE_0_TX_SYNC_PULSE_WIDTH_RANGE     24:20
#define SATA0_CFG_CTL_GLUE_0_TX_SYNC_PULSE_WIDTH_WOFFSET   0
#define SATA0_CFG_CTL_GLUE_0_TX_SYNC_PULSE_WIDTH_INIT      _MK_ENUM_CONST(0x00000019)                                                       // RWC-V
#define SATA0_CFG_CTL_GLUE_0_RX_CDR_PULSE_WIDTH_SHIFT       _MK_SHIFT_CONST(25)                                                             // RWCVF
#define SATA0_CFG_CTL_GLUE_0_RX_CDR_PULSE_WIDTH_FIELD      (_MK_SHIFT_CONST(0x1f) << SATA0_CFG_CTL_GLUE_0_RX_CDR_PULSE_WIDTH_SHIFT)
#define SATA0_CFG_CTL_GLUE_0_RX_CDR_PULSE_WIDTH_RANGE      29:25
#define SATA0_CFG_CTL_GLUE_0_RX_CDR_PULSE_WIDTH_WOFFSET    0
#define SATA0_CFG_CTL_GLUE_0_RX_CDR_PULSE_WIDTH_INIT       _MK_ENUM_CONST(0x0000000F)                                                       // RWC-V
#define SATA0_CFG_CTL_GLUE_0_RX_EN_DYNAMIC_OOB_CYA_SHIFT    _MK_SHIFT_CONST(30)                                                             // RWCVF
#define SATA0_CFG_CTL_GLUE_0_RX_EN_DYNAMIC_OOB_CYA_FIELD   (_MK_SHIFT_CONST(0x1) << SATA0_CFG_CTL_GLUE_0_RX_EN_DYNAMIC_OOB_CYA_SHIFT)
#define SATA0_CFG_CTL_GLUE_0_RX_EN_DYNAMIC_OOB_CYA_RANGE   30:30
#define SATA0_CFG_CTL_GLUE_0_RX_EN_DYNAMIC_OOB_CYA_WOFFSET 0
#define SATA0_CFG_CTL_GLUE_0_RX_EN_DYNAMIC_OOB_CYA_INIT    _MK_ENUM_CONST(0x00000001)                                                       // RWC-V
#define SATA0_CFG_CTL_GLUE_0_UPHY_TX_SLEEP_DEVSLP_SHIFT     _MK_SHIFT_CONST(31)                                                             // RWCVF
#define SATA0_CFG_CTL_GLUE_0_UPHY_TX_SLEEP_DEVSLP_FIELD    (_MK_SHIFT_CONST(0x1) << SATA0_CFG_CTL_GLUE_0_UPHY_TX_SLEEP_DEVSLP_SHIFT)
#define SATA0_CFG_CTL_GLUE_0_UPHY_TX_SLEEP_DEVSLP_RANGE    31:31
#define SATA0_CFG_CTL_GLUE_0_UPHY_TX_SLEEP_DEVSLP_WOFFSET  0
#define SATA0_CFG_CTL_GLUE_0_UPHY_TX_SLEEP_DEVSLP_INIT     _MK_ENUM_CONST(0x00000001)                                                       // RWC-V
// 
// 
// 
// 
// 
// 
// 
// 
// 
// 
// 
// 
// 
// 
// 
// 
// 
// 
// 
// 
// 
// 
// 
// 
// .LABEL PUBLIC
// 
// .LABEL PRIVATE INT_REL
// .TITLE CFG_CTL_FA
//  31                           16 15                            0
// .-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-.
// |0                           0|                                 | CFG_CTL_FA
// +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
#define SATA0_CFG_CTL_FA_0                                 0x000004BC                                                                       // RWC4R
#define SATA0_CFG_CTL_FA_0_SECURE                          0
#define SATA0_CFG_CTL_FA_0_WORD_COUNT                      1
#define SATA0_CFG_CTL_FA_0_RESET_VAL                       0x0
#define SATA0_CFG_CTL_FA_0_RESET_MASK                      0x0
#define SATA0_CFG_CTL_FA_0_SW_DEFAULT_VAL                  0x0
#define SATA0_CFG_CTL_FA_0_SW_DEFAULT_MASK                 0x0
#define SATA0_CFG_CTL_FA_0_READ_MASK                       0xff
#define SATA0_CFG_CTL_FA_0_WRITE_MASK                      0xff
#define SATA0_CFG_CTL_FA_0_FPCI_CLK_IS_128MHZ_SHIFT         _MK_SHIFT_CONST(0)                                                              // RWCVF
#define SATA0_CFG_CTL_FA_0_FPCI_CLK_IS_128MHZ_FIELD        (_MK_SHIFT_CONST(0x1) << SATA0_CFG_CTL_FA_0_FPCI_CLK_IS_128MHZ_SHIFT)
#define SATA0_CFG_CTL_FA_0_FPCI_CLK_IS_128MHZ_RANGE        0:0
#define SATA0_CFG_CTL_FA_0_FPCI_CLK_IS_128MHZ_WOFFSET      0
#define SATA0_CFG_CTL_FA_0_FPCI_CLK_IS_128MHZ_YES          _MK_ENUM_CONST(0x00000001)                                                       // RWC-V
#define SATA0_CFG_CTL_FA_0_FPCI_CLK_IS_128MHZ_NO           _MK_ENUM_CONST(0x00000000)                                                       // RW--V
#define SATA0_CFG_CTL_FA_0_EAT_CLK_SHIFT                    _MK_SHIFT_CONST(1)                                                              // RWCVF
#define SATA0_CFG_CTL_FA_0_EAT_CLK_FIELD                   (_MK_SHIFT_CONST(0x1) << SATA0_CFG_CTL_FA_0_EAT_CLK_SHIFT)
#define SATA0_CFG_CTL_FA_0_EAT_CLK_RANGE                   1:1
#define SATA0_CFG_CTL_FA_0_EAT_CLK_WOFFSET                 0
#define SATA0_CFG_CTL_FA_0_EAT_CLK_YES                     _MK_ENUM_CONST(0x00000001)                                                       // RWC-V
#define SATA0_CFG_CTL_FA_0_EAT_CLK_NO                      _MK_ENUM_CONST(0x00000000)                                                       // RW--V
#define SATA0_CFG_CTL_FA_0_USE_CFG_EATER_SHIFT              _MK_SHIFT_CONST(2)                                                              // RWCVF
#define SATA0_CFG_CTL_FA_0_USE_CFG_EATER_FIELD             (_MK_SHIFT_CONST(0x1) << SATA0_CFG_CTL_FA_0_USE_CFG_EATER_SHIFT)
#define SATA0_CFG_CTL_FA_0_USE_CFG_EATER_RANGE             2:2
#define SATA0_CFG_CTL_FA_0_USE_CFG_EATER_WOFFSET           0
#define SATA0_CFG_CTL_FA_0_USE_CFG_EATER_YES               _MK_ENUM_CONST(0x00000001)                                                       // RW--V
#define SATA0_CFG_CTL_FA_0_USE_CFG_EATER_NO                _MK_ENUM_CONST(0x00000000)                                                       // RWC-V
#define SATA0_CFG_CTL_FA_0_CFG_EATER_SHIFT                  _MK_SHIFT_CONST(3)                                                              // RWCVF
#define SATA0_CFG_CTL_FA_0_CFG_EATER_FIELD                 (_MK_SHIFT_CONST(0x1f) << SATA0_CFG_CTL_FA_0_CFG_EATER_SHIFT)
#define SATA0_CFG_CTL_FA_0_CFG_EATER_RANGE                 7:3
#define SATA0_CFG_CTL_FA_0_CFG_EATER_WOFFSET               0
// 
// 
// 
// .LABEL PUBLIC
// 
// 
// .LABEL INT_REL
// .TITLE PERF0
// .LABEL PRIVATE INT_REL
// .FIELD DONT_DELAY_ROK
// Setting DONT_DELAY_ROK turns on an optimization feature that should help performance on DMA reads.
// Transport layer then completes the current transfer even when busmaster has not yet drained all
// of recieve fifo. Setting this bit to _TRUE should result in better performance and therefore it
// is the preferred mode of operation. This is not the default POR value and it is expected that BIOS
// or Driver will enable this feature.
// 
// 
// .FIELD MIN_FPCI_CLK_FREQ
// This field set the minimum frequyency at which the fpci_clk should run in increments of 1/16th.
// It provides SW to override value set by frequency adjuster unit. Note that the actual frequency
// level is max of all the controllers.
// 31           24 23           16 15            8 7             0
// .-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-.
// |                                                               | PERF0
// +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
// 
// .LABEL INT_REL
#define SATA0_PERF0_0                                      0x000004F0                                                                       // RW-4R
#define SATA0_PERF0_0_SECURE                               0
#define SATA0_PERF0_0_WORD_COUNT                           1
#define SATA0_PERF0_0_RESET_VAL                            0x0
#define SATA0_PERF0_0_RESET_MASK                           0x0
#define SATA0_PERF0_0_SW_DEFAULT_VAL                       0x0
#define SATA0_PERF0_0_SW_DEFAULT_MASK                      0x0
#define SATA0_PERF0_0_READ_MASK                            0x16000f80
#define SATA0_PERF0_0_WRITE_MASK                           0x16000f80
#define SATA0_PERF0_0_MIN_FPCI_CLK_FREQ_SHIFT               _MK_SHIFT_CONST(7)                                                              // RWCVF
#define SATA0_PERF0_0_MIN_FPCI_CLK_FREQ_FIELD              (_MK_SHIFT_CONST(0x1f) << SATA0_PERF0_0_MIN_FPCI_CLK_FREQ_SHIFT)
#define SATA0_PERF0_0_MIN_FPCI_CLK_FREQ_RANGE              11:7
#define SATA0_PERF0_0_MIN_FPCI_CLK_FREQ_WOFFSET            0
#define SATA0_PERF0_0_MIN_FPCI_CLK_FREQ_16                 _MK_ENUM_CONST(0x00000010)                                                       // RWC-V
#define SATA0_PERF0_0_SATA_PLL_POWERDOWN_SHIFT              _MK_SHIFT_CONST(25)                                                             // RWC-F
#define SATA0_PERF0_0_SATA_PLL_POWERDOWN_FIELD             (_MK_SHIFT_CONST(0x3) << SATA0_PERF0_0_SATA_PLL_POWERDOWN_SHIFT)
#define SATA0_PERF0_0_SATA_PLL_POWERDOWN_RANGE             26:25
#define SATA0_PERF0_0_SATA_PLL_POWERDOWN_WOFFSET           0
#define SATA0_PERF0_0_SATA_PLL_POWERDOWN_YES               _MK_ENUM_CONST(0x00000001)                                                       // RW--V
#define SATA0_PERF0_0_SATA_PLL_POWERDOWN_NO                _MK_ENUM_CONST(0x00000000)                                                       // RWC-V
#define SATA0_PERF0_0_DONT_DELAY_ROK_SHIFT                  _MK_SHIFT_CONST(28)                                                             // RWCVF
#define SATA0_PERF0_0_DONT_DELAY_ROK_FIELD                 (_MK_SHIFT_CONST(0x1) << SATA0_PERF0_0_DONT_DELAY_ROK_SHIFT)
#define SATA0_PERF0_0_DONT_DELAY_ROK_RANGE                 28:28
#define SATA0_PERF0_0_DONT_DELAY_ROK_WOFFSET               0
#define SATA0_PERF0_0_DONT_DELAY_ROK_FALSE                 _MK_ENUM_CONST(0x00000000)                                                       // RWC-V
#define SATA0_PERF0_0_DONT_DELAY_ROK_TRUE                  _MK_ENUM_CONST(0x00000001)                                                       // RW--V
// .LABEL PRIVATE INT_REL
// .LABEL POWER_TUNING_AVG
// 
// .LABEL INT_REL
// 
// 
// .LABEL PRIVATE INT_REL
// 
// .LABEL PUBLIC
// 
// 
// .LABEL PRIVATE INT_REL
// .TITLE PERF1
// 
// This register is used to configure some of the SATA implementation options.
// 
// .FIELD HIGH_WATER_MARK
// This field configures the read fifo limit at which point the
// host starts sending HOLD primitives to back-off the data transfer from device. This
// field is only relevant during READs and should typically be set to as high a value
// without running the risk of overflowing the Fifo.
// 
// Bit5:0 of the register is used for DMA read high water mark. For DMA reads, fifo
// depth is 48. And, each entry is 64bit, that is it contains two dwords. So, if the
// watermark is set at X then there is headroom for (48-X)*2 dwords for drive to react
// to controller sending HOLD.
// 
// .FIELD HIGH_WATER_MARK_PIO
// Bit 13:8 of the register  is used for PIO reads high water mark.
// For PIO reads, fifo depth is 48. But each entry is 32bit, that is it contains only
// one dword. So, if mark is set at Y, there is headroom for (48-Y) dwords for drive to
// react to us sending HOLD.
// 
// 
// .FIELD MAX_WATER_MARK
// The MAX_WATER_MARK field tracks the maximum occupancy of the two i2f_fifos.
// The purpose of this field is to give us guidance on the setting of HIGH_WATER_MARK
// field. Ideally, the HIGH_WATER_MARK field should be set so that the MAX_WATER_MARK
// field almost hit full.
// 
// Note that MAX_WATER_MARK field is only 8 bits wide, so it can only track the lower
// 8 bits of the fifo level. The MSB value can be inferred from the MSB value of
// the 9 bit HIGH_WATER_MARK field.
// 
// T_SATA0_CFG_39_RXDATA_IB_DELAY[0] enables resetting SSTATUS_DET and SSTATUS_SPD
// fields to 0 when channels enter into partial or slumber low power modes. By default this
// bit is 0 and we dont reset these fields.
// 
// 31           24 23           16 15            8 7             0
// .-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-.
// |                                                               | PERF1
// +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
#define SATA0_PERF1_0                                      0x000004F4                                                                       // RWW4R
#define SATA0_PERF1_0_SECURE                               0
#define SATA0_PERF1_0_WORD_COUNT                           1
#define SATA0_PERF1_0_RESET_VAL                            0x0
#define SATA0_PERF1_0_RESET_MASK                           0x0
#define SATA0_PERF1_0_SW_DEFAULT_VAL                       0x0
#define SATA0_PERF1_0_SW_DEFAULT_MASK                      0x0
#define SATA0_PERF1_0_READ_MASK                            0xff00ffff
#define SATA0_PERF1_0_WRITE_MASK                           0xff00ffff
#define SATA0_PERF1_0_HIGH_WATER_MARK_SHIFT                 _MK_SHIFT_CONST(0)                                                              // RWW-F
#define SATA0_PERF1_0_HIGH_WATER_MARK_FIELD                (_MK_SHIFT_CONST(0xff) << SATA0_PERF1_0_HIGH_WATER_MARK_SHIFT)
#define SATA0_PERF1_0_HIGH_WATER_MARK_RANGE                7:0
#define SATA0_PERF1_0_HIGH_WATER_MARK_WOFFSET              0
#define SATA0_PERF1_0_HIGH_WATER_MARK_DEFAULT              (_MK_MASK_CONST(0x0000006E)
#define SATA0_PERF1_0_HIGH_WATER_MARK_DEFAULT_MASK         (_MK_MASK_CONST(0xff)
#define SATA0_PERF1_0_HIGH_WATER_MARK_SW_DEFAULT           (_MK_MASK_CONST(0x0000006E)
#define SATA0_PERF1_0_HIGH_WATER_MARK_SW_DEFAULT_MASK      (_MK_MASK_CONST(0xff)
#define SATA0_PERF1_0_HIGH_WATER_MARK_INIT                 _MK_ENUM_CONST(0x0000006E)                                                       // RWW-V
#define SATA0_PERF1_0_HIGH_WATER_MARK_PIO_SHIFT             _MK_SHIFT_CONST(8)                                                              // RWW-F
#define SATA0_PERF1_0_HIGH_WATER_MARK_PIO_FIELD            (_MK_SHIFT_CONST(0xff) << SATA0_PERF1_0_HIGH_WATER_MARK_PIO_SHIFT)
#define SATA0_PERF1_0_HIGH_WATER_MARK_PIO_RANGE            15:8
#define SATA0_PERF1_0_HIGH_WATER_MARK_PIO_WOFFSET          0
#define SATA0_PERF1_0_HIGH_WATER_MARK_PIO_DEFAULT          (_MK_MASK_CONST(0x0000005A)
#define SATA0_PERF1_0_HIGH_WATER_MARK_PIO_DEFAULT_MASK     (_MK_MASK_CONST(0xff)
#define SATA0_PERF1_0_HIGH_WATER_MARK_PIO_SW_DEFAULT       (_MK_MASK_CONST(0x0000005A)
#define SATA0_PERF1_0_HIGH_WATER_MARK_PIO_SW_DEFAULT_MASK  (_MK_MASK_CONST(0xff)
#define SATA0_PERF1_0_HIGH_WATER_MARK_PIO_INIT             _MK_ENUM_CONST(0x0000005A)                                                       // RWW-V
#define SATA0_PERF1_0_MAX_WATER_MARK_SHIFT                  _MK_SHIFT_CONST(24)                                                             // RWC-F
#define SATA0_PERF1_0_MAX_WATER_MARK_FIELD                 (_MK_SHIFT_CONST(0xff) << SATA0_PERF1_0_MAX_WATER_MARK_SHIFT)
#define SATA0_PERF1_0_MAX_WATER_MARK_RANGE                 31:24
#define SATA0_PERF1_0_MAX_WATER_MARK_WOFFSET               0
#define SATA0_PERF1_0_MAX_WATER_MARK__NOPRDCHK             _MK_ENUM_CONST(0x00000001)                                                       // ----V
#define SATA0_PERF1_0_MAX_WATER_MARK_0                     _MK_ENUM_CONST(0x00000000)                                                       // RWC-V
// 
// 
// 
// 
// 
//         Figure 10-39 Serial ATA Implementation Options Register A0h
// .LABEL PUBLIC
// 
// 
// 
// .LABEL PRIVATE INT_REL
// .TITLE SPARE_0
// spare register on cold reset with zero as the default value
// 31           24 23           16 15            8 7             0
// .-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-.
// |                                                               | SPARE_0
// +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
#define SATA0_SPARE_0_0                                    0x00000520                                                                       // RW-4R
#define SATA0_SPARE_0_0_SECURE                             0
#define SATA0_SPARE_0_0_WORD_COUNT                         1
#define SATA0_SPARE_0_0_RESET_VAL                          0x0
#define SATA0_SPARE_0_0_RESET_MASK                         0x0
#define SATA0_SPARE_0_0_SW_DEFAULT_VAL                     0x0
#define SATA0_SPARE_0_0_SW_DEFAULT_MASK                    0x0
#define SATA0_SPARE_0_0_READ_MASK                          0xffffffff
#define SATA0_SPARE_0_0_WRITE_MASK                         0xffffffff
#define SATA0_SPARE_0_0_RSVD_SHIFT                          _MK_SHIFT_CONST(0)                                                              // RWCVF
#define SATA0_SPARE_0_0_RSVD_FIELD                         (_MK_SHIFT_CONST(0xffffffff) << SATA0_SPARE_0_0_RSVD_SHIFT)
#define SATA0_SPARE_0_0_RSVD_RANGE                         31:0
#define SATA0_SPARE_0_0_RSVD_WOFFSET                       0
// 
// 
// .LABEL PUBLIC
// 
// .LABEL PRIVATE INT_REL
// .TITLE SPARE_1
// spare register on warm reset with zero as the default value
// 31           24 23           16 15            8 7             0
// .-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-.
// |                                                               | SPARE_1
// +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
#define SATA0_SPARE_1_0                                    0x00000524                                                                       // RW-4R
#define SATA0_SPARE_1_0_SECURE                             0
#define SATA0_SPARE_1_0_WORD_COUNT                         1
#define SATA0_SPARE_1_0_RESET_VAL                          0x0
#define SATA0_SPARE_1_0_RESET_MASK                         0x0
#define SATA0_SPARE_1_0_SW_DEFAULT_VAL                     0x0
#define SATA0_SPARE_1_0_SW_DEFAULT_MASK                    0x0
#define SATA0_SPARE_1_0_READ_MASK                          0xffffffff
#define SATA0_SPARE_1_0_WRITE_MASK                         0xffffffff
#define SATA0_SPARE_1_0_RSVD_SHIFT                          _MK_SHIFT_CONST(0)                                                              // RWWVF
#define SATA0_SPARE_1_0_RSVD_FIELD                         (_MK_SHIFT_CONST(0xffffffff) << SATA0_SPARE_1_0_RSVD_SHIFT)
#define SATA0_SPARE_1_0_RSVD_RANGE                         31:0
#define SATA0_SPARE_1_0_RSVD_WOFFSET                       0
#define SATA0_SPARE_1_0_RSVD_DEFAULT                       (_MK_MASK_CONST(0x00000000)
#define SATA0_SPARE_1_0_RSVD_DEFAULT_MASK                  (_MK_MASK_CONST(0xffffffff)
#define SATA0_SPARE_1_0_RSVD_SW_DEFAULT                    (_MK_MASK_CONST(0x00000000)
#define SATA0_SPARE_1_0_RSVD_SW_DEFAULT_MASK               (_MK_MASK_CONST(0xffffffff)
// .LABEL PUBLIC
// 
// .LABEL PRIVATE INT_REL
// .TITLE SPARE_2
// spare register on cold reset with one as the default value
// 31           24 23           16 15            8 7             0
// .-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-.
// |                                                               | SPARE_2
// +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
#define SATA0_SPARE_2_0                                    0x00000528                                                                       // RW-4R
#define SATA0_SPARE_2_0_SECURE                             0
#define SATA0_SPARE_2_0_WORD_COUNT                         1
#define SATA0_SPARE_2_0_RESET_VAL                          0x0
#define SATA0_SPARE_2_0_RESET_MASK                         0x0
#define SATA0_SPARE_2_0_SW_DEFAULT_VAL                     0x0
#define SATA0_SPARE_2_0_SW_DEFAULT_MASK                    0x0
#define SATA0_SPARE_2_0_READ_MASK                          0xffffffff
#define SATA0_SPARE_2_0_WRITE_MASK                         0xffffffff
#define SATA0_SPARE_2_0_REM_TWO_ALIGNS_IN_BIST_L_SHIFT      _MK_SHIFT_CONST(0)                                                              // RWCVF
#define SATA0_SPARE_2_0_REM_TWO_ALIGNS_IN_BIST_L_FIELD     (_MK_SHIFT_CONST(0x1) << SATA0_SPARE_2_0_REM_TWO_ALIGNS_IN_BIST_L_SHIFT)
#define SATA0_SPARE_2_0_REM_TWO_ALIGNS_IN_BIST_L_RANGE     0:0
#define SATA0_SPARE_2_0_REM_TWO_ALIGNS_IN_BIST_L_WOFFSET   0
#define SATA0_SPARE_2_0_WAIT_DATA_DFIFO_POP_SHIFT           _MK_SHIFT_CONST(1)                                                              // RWCVF
#define SATA0_SPARE_2_0_WAIT_DATA_DFIFO_POP_FIELD          (_MK_SHIFT_CONST(0x1) << SATA0_SPARE_2_0_WAIT_DATA_DFIFO_POP_SHIFT)
#define SATA0_SPARE_2_0_WAIT_DATA_DFIFO_POP_RANGE          1:1
#define SATA0_SPARE_2_0_WAIT_DATA_DFIFO_POP_WOFFSET        0
#define SATA0_SPARE_2_0_FIS_PRO_WAIT_P_IDLE_SHIFT           _MK_SHIFT_CONST(2)                                                              // RWCVF
#define SATA0_SPARE_2_0_FIS_PRO_WAIT_P_IDLE_FIELD          (_MK_SHIFT_CONST(0x1) << SATA0_SPARE_2_0_FIS_PRO_WAIT_P_IDLE_SHIFT)
#define SATA0_SPARE_2_0_FIS_PRO_WAIT_P_IDLE_RANGE          2:2
#define SATA0_SPARE_2_0_FIS_PRO_WAIT_P_IDLE_WOFFSET        0
#define SATA0_SPARE_2_0_ERR_CLEANUP_WAIT_P_IDLE_SHIFT       _MK_SHIFT_CONST(3)                                                              // RWCVF
#define SATA0_SPARE_2_0_ERR_CLEANUP_WAIT_P_IDLE_FIELD      (_MK_SHIFT_CONST(0x1) << SATA0_SPARE_2_0_ERR_CLEANUP_WAIT_P_IDLE_SHIFT)
#define SATA0_SPARE_2_0_ERR_CLEANUP_WAIT_P_IDLE_RANGE      3:3
#define SATA0_SPARE_2_0_ERR_CLEANUP_WAIT_P_IDLE_WOFFSET    0
#define SATA0_SPARE_2_0_SET_PXCMD_FR_ON_FRE_SHIFT           _MK_SHIFT_CONST(4)                                                              // RWCVF
#define SATA0_SPARE_2_0_SET_PXCMD_FR_ON_FRE_FIELD          (_MK_SHIFT_CONST(0x1) << SATA0_SPARE_2_0_SET_PXCMD_FR_ON_FRE_SHIFT)
#define SATA0_SPARE_2_0_SET_PXCMD_FR_ON_FRE_RANGE          4:4
#define SATA0_SPARE_2_0_SET_PXCMD_FR_ON_FRE_WOFFSET        0
#define SATA0_SPARE_2_0_LATCH_PXCMD_FRE_SHIFT               _MK_SHIFT_CONST(5)                                                              // RWCVF
#define SATA0_SPARE_2_0_LATCH_PXCMD_FRE_FIELD              (_MK_SHIFT_CONST(0x1) << SATA0_SPARE_2_0_LATCH_PXCMD_FRE_SHIFT)
#define SATA0_SPARE_2_0_LATCH_PXCMD_FRE_RANGE              5:5
#define SATA0_SPARE_2_0_LATCH_PXCMD_FRE_WOFFSET            0
#define SATA0_SPARE_2_0_SPLIT_D2H_REG_FIS_SHIFT             _MK_SHIFT_CONST(6)                                                              // RWCVF
#define SATA0_SPARE_2_0_SPLIT_D2H_REG_FIS_FIELD            (_MK_SHIFT_CONST(0x1) << SATA0_SPARE_2_0_SPLIT_D2H_REG_FIS_SHIFT)
#define SATA0_SPARE_2_0_SPLIT_D2H_REG_FIS_RANGE            6:6
#define SATA0_SPARE_2_0_SPLIT_D2H_REG_FIS_WOFFSET          0
#define SATA0_SPARE_2_0_RSVD_SHIFT                          _MK_SHIFT_CONST(7)                                                              // RWCVF
#define SATA0_SPARE_2_0_RSVD_FIELD                         (_MK_SHIFT_CONST(0x1ffffff) << SATA0_SPARE_2_0_RSVD_SHIFT)
#define SATA0_SPARE_2_0_RSVD_RANGE                         31:7
#define SATA0_SPARE_2_0_RSVD_WOFFSET                       0
// 
// .LABEL PUBLIC
// 
// .LABEL PRIVATE INT_REL
// .TITLE SPARE_3
// spare register on warm reset with one as the default value
// 31           24 23           16 15            8 7             0
// .-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-.
// |                                                               | SPARE_3
// +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
#define SATA0_SPARE_3_0                                    0x0000052C                                                                       // RW-4R
#define SATA0_SPARE_3_0_SECURE                             0
#define SATA0_SPARE_3_0_WORD_COUNT                         1
#define SATA0_SPARE_3_0_RESET_VAL                          0x0
#define SATA0_SPARE_3_0_RESET_MASK                         0x0
#define SATA0_SPARE_3_0_SW_DEFAULT_VAL                     0x0
#define SATA0_SPARE_3_0_SW_DEFAULT_MASK                    0x0
#define SATA0_SPARE_3_0_READ_MASK                          0xffffffff
#define SATA0_SPARE_3_0_WRITE_MASK                         0xffffffff
#define SATA0_SPARE_3_0_COUNT_FOR_1_MS_SHIFT                _MK_SHIFT_CONST(0)                                                              // RWCVF
#define SATA0_SPARE_3_0_COUNT_FOR_1_MS_FIELD               (_MK_SHIFT_CONST(0x7ffff) << SATA0_SPARE_3_0_COUNT_FOR_1_MS_SHIFT)
#define SATA0_SPARE_3_0_COUNT_FOR_1_MS_RANGE               18:0
#define SATA0_SPARE_3_0_COUNT_FOR_1_MS_WOFFSET             0
#define SATA0_SPARE_3_0_RSVD_SHIFT                          _MK_SHIFT_CONST(19)                                                             // RWCVF
#define SATA0_SPARE_3_0_RSVD_FIELD                         (_MK_SHIFT_CONST(0x1fff) << SATA0_SPARE_3_0_RSVD_SHIFT)
#define SATA0_SPARE_3_0_RSVD_RANGE                         31:19
#define SATA0_SPARE_3_0_RSVD_WOFFSET                       0
// .LABEL PUBLIC
// 
// .LABEL PRIVATE INT_REL
// .TITLE CHXCFG1
// .FIELD CHX_RESET
// This can be used to reset the port in IDE mode of SATA controller.
// It is not advisable to use it in AHCI mode.
// 31           24 23           16 15            8 7             0
// .-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-.
// |                                                               | CHXCFG1
// +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
#define SATA0_CHXCFG1_0                                    0x00000530                                                                       // RWW4R
#define SATA0_CHXCFG1_0_SECURE                             0
#define SATA0_CHXCFG1_0_WORD_COUNT                         1
#define SATA0_CHXCFG1_0_RESET_VAL                          0x0
#define SATA0_CHXCFG1_0_RESET_MASK                         0x0
#define SATA0_CHXCFG1_0_SW_DEFAULT_VAL                     0x0
#define SATA0_CHXCFG1_0_SW_DEFAULT_MASK                    0x0
#define SATA0_CHXCFG1_0_READ_MASK                          0xffffffff
#define SATA0_CHXCFG1_0_WRITE_MASK                         0xff03
#define SATA0_CHXCFG1_0_CHX_RESET_SHIFT                     _MK_SHIFT_CONST(0)                                                              // RWC-F
#define SATA0_CHXCFG1_0_CHX_RESET_FIELD                    (_MK_SHIFT_CONST(0x1) << SATA0_CHXCFG1_0_CHX_RESET_SHIFT)
#define SATA0_CHXCFG1_0_CHX_RESET_RANGE                    0:0
#define SATA0_CHXCFG1_0_CHX_RESET_WOFFSET                  0
#define SATA0_CHXCFG1_0_CHX_RESET_INACTIVE                 _MK_ENUM_CONST(0x00000000)                                                       // RW--V
#define SATA0_CHXCFG1_0_CHX_RESET_ACTIVE                   _MK_ENUM_CONST(0x00000001)                                                       // RW--V
#define SATA0_CHXCFG1_0_CHX_NEAR_LOOP_BACK_SHIFT            _MK_SHIFT_CONST(1)                                                              // RWC-F
#define SATA0_CHXCFG1_0_CHX_NEAR_LOOP_BACK_FIELD           (_MK_SHIFT_CONST(0x1) << SATA0_CHXCFG1_0_CHX_NEAR_LOOP_BACK_SHIFT)
#define SATA0_CHXCFG1_0_CHX_NEAR_LOOP_BACK_RANGE           1:1
#define SATA0_CHXCFG1_0_CHX_NEAR_LOOP_BACK_WOFFSET         0
#define SATA0_CHXCFG1_0_CHX_NEAR_LOOP_BACK_INACTIVE        _MK_ENUM_CONST(0x00000000)                                                       // RW--V
#define SATA0_CHXCFG1_0_CHX_NEAR_LOOP_BACK_ACTIVE          _MK_ENUM_CONST(0x00000001)                                                       // RW--V
#define SATA0_CHXCFG1_0_RSVD_0_SHIFT                        _MK_SHIFT_CONST(2)                                                              // C--VF
#define SATA0_CHXCFG1_0_RSVD_0_FIELD                       (_MK_SHIFT_CONST(0x3f) << SATA0_CHXCFG1_0_RSVD_0_SHIFT)
#define SATA0_CHXCFG1_0_RSVD_0_RANGE                       7:2
#define SATA0_CHXCFG1_0_RSVD_0_WOFFSET                     0
#define SATA0_CHXCFG1_0_RSVD_0_VAL                         _MK_ENUM_CONST(0x00000000)                                                       // C---V
#define SATA0_CHXCFG1_0_PHY_CHX_TX_CYA_SHIFT                _MK_SHIFT_CONST(8)                                                              // RWC-F
#define SATA0_CHXCFG1_0_PHY_CHX_TX_CYA_FIELD               (_MK_SHIFT_CONST(0xf) << SATA0_CHXCFG1_0_PHY_CHX_TX_CYA_SHIFT)
#define SATA0_CHXCFG1_0_PHY_CHX_TX_CYA_RANGE               11:8
#define SATA0_CHXCFG1_0_PHY_CHX_TX_CYA_WOFFSET             0
#define SATA0_CHXCFG1_0_PHY_CHX_TX_CYA_INIT                _MK_ENUM_CONST(0x00000000)                                                       // RWC-V
#define SATA0_CHXCFG1_0_PHY_CHX_TX_CYA_VAL_0               _MK_ENUM_CONST(0x00000000)                                                       // RW--V
#define SATA0_CHXCFG1_0_PHY_CHX_TX_CYA_VAL_1               _MK_ENUM_CONST(0x00000001)                                                       // RW--V
#define SATA0_CHXCFG1_0_PHY_CHX_TX_CYA_VAL_2               _MK_ENUM_CONST(0x00000002)                                                       // RW--V
#define SATA0_CHXCFG1_0_PHY_CHX_TX_CYA_VAL_3               _MK_ENUM_CONST(0x00000003)                                                       // RW--V
#define SATA0_CHXCFG1_0_PHY_CHX_TX_CYA_VAL_F               _MK_ENUM_CONST(0x0000000F)                                                       // RW--V
#define SATA0_CHXCFG1_0_PHY_CHX_RX_CYA_SHIFT                _MK_SHIFT_CONST(12)                                                             // RWC-F
#define SATA0_CHXCFG1_0_PHY_CHX_RX_CYA_FIELD               (_MK_SHIFT_CONST(0xf) << SATA0_CHXCFG1_0_PHY_CHX_RX_CYA_SHIFT)
#define SATA0_CHXCFG1_0_PHY_CHX_RX_CYA_RANGE               15:12
#define SATA0_CHXCFG1_0_PHY_CHX_RX_CYA_WOFFSET             0
#define SATA0_CHXCFG1_0_PHY_CHX_RX_CYA_INIT                _MK_ENUM_CONST(0x00000000)                                                       // RWC-V
#define SATA0_CHXCFG1_0_PHY_CHX_RX_CYA_VAL_0               _MK_ENUM_CONST(0x00000000)                                                       // RW--V
#define SATA0_CHXCFG1_0_PHY_CHX_RX_CYA_VAL_1               _MK_ENUM_CONST(0x00000001)                                                       // RW--V
#define SATA0_CHXCFG1_0_PHY_CHX_RX_CYA_VAL_2               _MK_ENUM_CONST(0x00000002)                                                       // RW--V
#define SATA0_CHXCFG1_0_PHY_CHX_RX_CYA_VAL_3               _MK_ENUM_CONST(0x00000003)                                                       // RW--V
#define SATA0_CHXCFG1_0_PHY_CHX_RX_CYA_VAL_F               _MK_ENUM_CONST(0x0000000F)                                                       // RW--V
#define SATA0_CHXCFG1_0_RSVD_1_SHIFT                        _MK_SHIFT_CONST(16)                                                             // C--VF
#define SATA0_CHXCFG1_0_RSVD_1_FIELD                       (_MK_SHIFT_CONST(0xffff) << SATA0_CHXCFG1_0_RSVD_1_SHIFT)
#define SATA0_CHXCFG1_0_RSVD_1_RANGE                       31:16
#define SATA0_CHXCFG1_0_RSVD_1_WOFFSET                     0
#define SATA0_CHXCFG1_0_RSVD_1_VAL                         _MK_ENUM_CONST(0x00000000)                                                       // C---V
// 
// 
// 
// .define T_SATA0_CHXCFG1_PHY_CHX_TX_CTL                          11:8 /* RWC-F */
// .define T_SATA0_CHXCFG1_PHY_CHX_TX_CTL_INIT               0x00000000 /* RWC-V */
// .define T_SATA0_CHXCFG1_PHY_CHX_TX_CTL_VAL_0              0x00000000 /* RW--V */
// .define T_SATA0_CHXCFG1_PHY_CHX_TX_CTL_VAL_1              0x00000001 /* RW--V */
// .define T_SATA0_CHXCFG1_PHY_CHX_TX_CTL_VAL_2              0x00000002 /* RW--V */
// .define T_SATA0_CHXCFG1_PHY_CHX_TX_CTL_VAL_3              0x00000003 /* RW--V */
// .define T_SATA0_CHXCFG1_PHY_CHX_TX_CTL_VAL_F              0x0000000F /* RW--V */
// 
// .define T_SATA0_CHXCFG1_PHY_CHX_RX_CTL                         15:12 /* RWC-F */
// .define T_SATA0_CHXCFG1_PHY_CHX_RX_CTL_INIT               0x00000000 /* RWC-V */
// .define T_SATA0_CHXCFG1_PHY_CHX_RX_CTL_VAL_0              0x00000000 /* RW--V */
// .define T_SATA0_CHXCFG1_PHY_CHX_RX_CTL_VAL_1              0x00000001 /* RW--V */
// .define T_SATA0_CHXCFG1_PHY_CHX_RX_CTL_VAL_2              0x00000002 /* RW--V */
// .define T_SATA0_CHXCFG1_PHY_CHX_RX_CTL_VAL_3              0x00000003 /* RW--V */
// .define T_SATA0_CHXCFG1_PHY_CHX_RX_CTL_VAL_F              0x0000000F /* RW--V */
// 
// 
// .LABEL PUBLIC
// 
// 
// .LABEL PRIVATE INT_REL
// .TITLE PHY_CTRL
// PLL_SLEEP describes power setting of SATA2 internal phy. Input to PHY is actually
// most active power setting from two sata controllers. TX/RX power states are per port.
// 
// 31           24 23           16 15            8 7             0
// .-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-.
// |                                                               | PHY_CTRL
// +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
// 
#define SATA0_PHY_CTRL_0                                   0x00000534                                                                       // RWW4R
#define SATA0_PHY_CTRL_0_SECURE                            0
#define SATA0_PHY_CTRL_0_WORD_COUNT                        1
#define SATA0_PHY_CTRL_0_RESET_VAL                         0x0
#define SATA0_PHY_CTRL_0_RESET_MASK                        0x0
#define SATA0_PHY_CTRL_0_SW_DEFAULT_VAL                    0x0
#define SATA0_PHY_CTRL_0_SW_DEFAULT_MASK                   0x0
#define SATA0_PHY_CTRL_0_READ_MASK                         0xffffffff
#define SATA0_PHY_CTRL_0_WRITE_MASK                        0x19
#define SATA0_PHY_CTRL_0_RSVD_1_SHIFT                       _MK_SHIFT_CONST(5)                                                              // C--VF
#define SATA0_PHY_CTRL_0_RSVD_1_FIELD                      (_MK_SHIFT_CONST(0x7ffffff) << SATA0_PHY_CTRL_0_RSVD_1_SHIFT)
#define SATA0_PHY_CTRL_0_RSVD_1_RANGE                      31:5
#define SATA0_PHY_CTRL_0_RSVD_1_WOFFSET                    0
#define SATA0_PHY_CTRL_0_RSVD_1_VAL                        _MK_ENUM_CONST(0x00000000)                                                       // C---V
#define SATA0_PHY_CTRL_0_PLL_SLEEP_SHIFT                    _MK_SHIFT_CONST(3)                                                              // RWC-F
#define SATA0_PHY_CTRL_0_PLL_SLEEP_FIELD                   (_MK_SHIFT_CONST(0x3) << SATA0_PHY_CTRL_0_PLL_SLEEP_SHIFT)
#define SATA0_PHY_CTRL_0_PLL_SLEEP_RANGE                   4:3
#define SATA0_PHY_CTRL_0_PLL_SLEEP_WOFFSET                 0
#define SATA0_PHY_CTRL_0_PLL_SLEEP_INIT                    _MK_ENUM_CONST(0x00000000)                                                       // RWC-V
#define SATA0_PHY_CTRL_0_PLL_SLEEP_ACTIVE                  _MK_ENUM_CONST(0x00000000)                                                       // RW--V
#define SATA0_PHY_CTRL_0_PLL_SLEEP_3G_DISABLED             _MK_ENUM_CONST(0x00000001)                                                       // RW--V
#define SATA0_PHY_CTRL_0_PLL_SLEEP_ALL_CLKS_DISABLED       _MK_ENUM_CONST(0x00000002)                                                       // RW--V
#define SATA0_PHY_CTRL_0_PLL_SLEEP_PLL_DISABLED            _MK_ENUM_CONST(0x00000003)                                                       // RW--V
#define SATA0_PHY_CTRL_0_RSVD_0_SHIFT                       _MK_SHIFT_CONST(1)                                                              // C--VF
#define SATA0_PHY_CTRL_0_RSVD_0_FIELD                      (_MK_SHIFT_CONST(0x3) << SATA0_PHY_CTRL_0_RSVD_0_SHIFT)
#define SATA0_PHY_CTRL_0_RSVD_0_RANGE                      2:1
#define SATA0_PHY_CTRL_0_RSVD_0_WOFFSET                    0
#define SATA0_PHY_CTRL_0_RSVD_0_VAL                        _MK_ENUM_CONST(0x00000000)                                                       // C---V
#define SATA0_PHY_CTRL_0_SLUMBER_DURING_D3_SHIFT            _MK_SHIFT_CONST(0)                                                              // RWC-F
#define SATA0_PHY_CTRL_0_SLUMBER_DURING_D3_FIELD           (_MK_SHIFT_CONST(0x1) << SATA0_PHY_CTRL_0_SLUMBER_DURING_D3_SHIFT)
#define SATA0_PHY_CTRL_0_SLUMBER_DURING_D3_RANGE           0:0
#define SATA0_PHY_CTRL_0_SLUMBER_DURING_D3_WOFFSET         0
#define SATA0_PHY_CTRL_0_SLUMBER_DURING_D3_ENABLE          _MK_ENUM_CONST(0x00000001)                                                       // RWC-V
#define SATA0_PHY_CTRL_0_SLUMBER_DURING_D3_DISABLE         _MK_ENUM_CONST(0x00000000)                                                       // RW--V
// 
// 
// 
// 
// 
// .LABEL INT_REL
// 
// .TITLE LDT UNIT ID Register 4Ch
//       The CFG_19 register contains the LDT Unit ID(s) for the Device.
// The Unit IDs are used by the device as a transaction ID on the LDT interface
// to uniquely identify where the request originated. Some devices will support
// 2 Unit IDs, 1 for isonchronous requests and the other for non-isonchronous
// requests.
// 
// .FIELD NON_ISO_UNIT_ID
// Non-ISO Unit ID.
// 
// .FIELD ISO_UNIT_ID
// ISO Unit ID. Hard-wired to 0.
// 
//  31           24 23           16 15            8 7             0
// .-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-.
// |0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0|0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0| LDT
// `-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-'
// 
#define SATA0_LDT_0                                        0x0000053C                                                                       // RW-4R
#define SATA0_LDT_0_SECURE                                 0
#define SATA0_LDT_0_WORD_COUNT                             1
#define SATA0_LDT_0_RESET_VAL                              0x0
#define SATA0_LDT_0_RESET_MASK                             0x0
#define SATA0_LDT_0_SW_DEFAULT_VAL                         0x0
#define SATA0_LDT_0_SW_DEFAULT_MASK                        0x0
#define SATA0_LDT_0_READ_MASK                              0x1f1f
#define SATA0_LDT_0_WRITE_MASK                             0x1f00
#define SATA0_LDT_0_ISO_UNIT_ID_SHIFT                       _MK_SHIFT_CONST(0)                                                              // C--VF
#define SATA0_LDT_0_ISO_UNIT_ID_FIELD                      (_MK_SHIFT_CONST(0x1f) << SATA0_LDT_0_ISO_UNIT_ID_SHIFT)
#define SATA0_LDT_0_ISO_UNIT_ID_RANGE                      4:0
#define SATA0_LDT_0_ISO_UNIT_ID_WOFFSET                    0
#define SATA0_LDT_0_ISO_UNIT_ID_0                          _MK_ENUM_CONST(0x00000000)                                                       // C---V
#define SATA0_LDT_0_ISO_UNIT_ID_1                          _MK_ENUM_CONST(0x00000001)                                                       // ----V
#define SATA0_LDT_0_ISO_UNIT_ID_2                          _MK_ENUM_CONST(0x00000002)                                                       // ----V
#define SATA0_LDT_0_ISO_UNIT_ID_31                         _MK_ENUM_CONST(0x0000001F)                                                       // ----V
#define SATA0_LDT_0_NON_ISO_UNIT_ID_SHIFT                   _MK_SHIFT_CONST(8)                                                              // RWWVF
#define SATA0_LDT_0_NON_ISO_UNIT_ID_FIELD                  (_MK_SHIFT_CONST(0x1f) << SATA0_LDT_0_NON_ISO_UNIT_ID_SHIFT)
#define SATA0_LDT_0_NON_ISO_UNIT_ID_RANGE                  12:8
#define SATA0_LDT_0_NON_ISO_UNIT_ID_WOFFSET                0
#define SATA0_LDT_0_NON_ISO_UNIT_ID_DEFAULT                (_MK_MASK_CONST(0x00000000)
#define SATA0_LDT_0_NON_ISO_UNIT_ID_DEFAULT_MASK           (_MK_MASK_CONST(0x1f)
#define SATA0_LDT_0_NON_ISO_UNIT_ID_SW_DEFAULT             (_MK_MASK_CONST(0x00000000)
#define SATA0_LDT_0_NON_ISO_UNIT_ID_SW_DEFAULT_MASK        (_MK_MASK_CONST(0x1f)
#define SATA0_LDT_0_NON_ISO_UNIT_ID_0                      _MK_ENUM_CONST(0x00000000)                                                       // RWW-V
#define SATA0_LDT_0_NON_ISO_UNIT_ID_9                      _MK_ENUM_CONST(0x00000009)                                                       // RW--V
#define SATA0_LDT_0_NON_ISO_UNIT_ID_1                      _MK_ENUM_CONST(0x00000001)                                                       // RW--V
#define SATA0_LDT_0_NON_ISO_UNIT_ID_2                      _MK_ENUM_CONST(0x00000002)                                                       // RW--V
#define SATA0_LDT_0_NON_ISO_UNIT_ID_31                     _MK_ENUM_CONST(0x0000001F)                                                       // RW--V
// 
// 
//                 Figure 10-19  PCI Configuration Register 53Ch
// .LABEL PUBLIC
// 
// 
// .TITLE SATA_CTRL
// .LABEL FUNC_BIOS
// .FIELD PRI_CHANNEL_EN
// Enables the primary SATA channel.  Value 1 denotes that the respective channel
// is enabled and 0 indicates disabled channel.
// 
// .FIELD SEC_CHANNEL_EN
// Enables the secondary SATA channel.  Value 1 denotes that the respective channel
// is enabled and 0 indicates disabled channel.
// 
// .LABEL FUNC_DRIVER
// .LABEL PUBLIC
// .FIELD BAR5_SPACE_EN
//     BAR5_SPACE_EN bit enables use of BAR5 space. So, if this bit is written with zero then
// SATA will not accept any cycles to BAR5 (starting from 1KB to 4KB). By default this bit
// is low.
// 
// .LABEL INT_REL
// .FIELD INTF_ERR_HANDLING_EN
// This is used to enable an advanced feature to handle sata interface errors. It includes
// detecting premature CRC in non-AHCI mode and resetting transport layer on comreset.
// The interface errors are mostly seen on emulation system and are not expected on silicon.
// 
//  31           24 23           16 15            8 7             0
// .-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-.
// |0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0|0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0| CTRL
// `-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-'
// 
// .LABEL FUNC_BIOS
#define SATA0_CTRL_0                                       0x00000540                                                                       // RW-4R
#define SATA0_CTRL_0_SECURE                                0
#define SATA0_CTRL_0_WORD_COUNT                            1
#define SATA0_CTRL_0_RESET_VAL                             0x0
#define SATA0_CTRL_0_RESET_MASK                            0x0
#define SATA0_CTRL_0_SW_DEFAULT_VAL                        0x0
#define SATA0_CTRL_0_SW_DEFAULT_MASK                       0x0
#define SATA0_CTRL_0_READ_MASK                             0x6f30000f
#define SATA0_CTRL_0_WRITE_MASK                            0x6f30000f
#define SATA0_CTRL_0_SEC_CHANNEL_EN_SHIFT                   _MK_SHIFT_CONST(0)                                                              // RWCVF
#define SATA0_CTRL_0_SEC_CHANNEL_EN_FIELD                  (_MK_SHIFT_CONST(0x1) << SATA0_CTRL_0_SEC_CHANNEL_EN_SHIFT)
#define SATA0_CTRL_0_SEC_CHANNEL_EN_RANGE                  0:0
#define SATA0_CTRL_0_SEC_CHANNEL_EN_WOFFSET                0
#define SATA0_CTRL_0_SEC_CHANNEL_EN_NO                     _MK_ENUM_CONST(0x00000000)                                                       // RW--V
#define SATA0_CTRL_0_SEC_CHANNEL_EN_YES                    _MK_ENUM_CONST(0x00000001)                                                       // RWC-V
#define SATA0_CTRL_0_PRI_CHANNEL_EN_SHIFT                   _MK_SHIFT_CONST(1)                                                              // RWCVF
#define SATA0_CTRL_0_PRI_CHANNEL_EN_FIELD                  (_MK_SHIFT_CONST(0x1) << SATA0_CTRL_0_PRI_CHANNEL_EN_SHIFT)
#define SATA0_CTRL_0_PRI_CHANNEL_EN_RANGE                  1:1
#define SATA0_CTRL_0_PRI_CHANNEL_EN_WOFFSET                0
#define SATA0_CTRL_0_PRI_CHANNEL_EN_NO                     _MK_ENUM_CONST(0x00000000)                                                       // RW--V
#define SATA0_CTRL_0_PRI_CHANNEL_EN_YES                    _MK_ENUM_CONST(0x00000001)                                                       // RWC-V
#define SATA0_CTRL_0_ADMA_SPACE_EN_SHIFT                    _MK_SHIFT_CONST(2)                                                              // RWCVF
#define SATA0_CTRL_0_ADMA_SPACE_EN_FIELD                   (_MK_SHIFT_CONST(0x1) << SATA0_CTRL_0_ADMA_SPACE_EN_SHIFT)
#define SATA0_CTRL_0_ADMA_SPACE_EN_RANGE                   2:2
#define SATA0_CTRL_0_ADMA_SPACE_EN_WOFFSET                 0
#define SATA0_CTRL_0_ADMA_SPACE_EN_NO                      _MK_ENUM_CONST(0x00000000)                                                       // RW--V
#define SATA0_CTRL_0_ADMA_SPACE_EN_YES                     _MK_ENUM_CONST(0x00000001)                                                       // RWC-V
#define SATA0_CTRL_0_INTF_ERR_HANDLING_EN_SHIFT             _MK_SHIFT_CONST(3)                                                              // RWCVF
#define SATA0_CTRL_0_INTF_ERR_HANDLING_EN_FIELD            (_MK_SHIFT_CONST(0x1) << SATA0_CTRL_0_INTF_ERR_HANDLING_EN_SHIFT)
#define SATA0_CTRL_0_INTF_ERR_HANDLING_EN_RANGE            3:3
#define SATA0_CTRL_0_INTF_ERR_HANDLING_EN_WOFFSET          0
#define SATA0_CTRL_0_INTF_ERR_HANDLING_EN_YES              _MK_ENUM_CONST(0x00000001)                                                       // RW--V
#define SATA0_CTRL_0_INTF_ERR_HANDLING_EN_NO               _MK_ENUM_CONST(0x00000000)                                                       // RWC-V
#define SATA0_CTRL_0_CH3_EN_SHIFT                           _MK_SHIFT_CONST(20)                                                             // RWCVF
#define SATA0_CTRL_0_CH3_EN_FIELD                          (_MK_SHIFT_CONST(0x1) << SATA0_CTRL_0_CH3_EN_SHIFT)
#define SATA0_CTRL_0_CH3_EN_RANGE                          20:20
#define SATA0_CTRL_0_CH3_EN_WOFFSET                        0
#define SATA0_CTRL_0_CH3_EN_YES                            _MK_ENUM_CONST(0x00000001)                                                       // RWC-V
#define SATA0_CTRL_0_CH3_EN_NO                             _MK_ENUM_CONST(0x00000000)                                                       // RW--V
#define SATA0_CTRL_0_CH4_EN_SHIFT                           _MK_SHIFT_CONST(21)                                                             // RWCVF
#define SATA0_CTRL_0_CH4_EN_FIELD                          (_MK_SHIFT_CONST(0x1) << SATA0_CTRL_0_CH4_EN_SHIFT)
#define SATA0_CTRL_0_CH4_EN_RANGE                          21:21
#define SATA0_CTRL_0_CH4_EN_WOFFSET                        0
#define SATA0_CTRL_0_CH4_EN_YES                            _MK_ENUM_CONST(0x00000001)                                                       // RWC-V
#define SATA0_CTRL_0_CH4_EN_NO                             _MK_ENUM_CONST(0x00000000)                                                       // RW--V
#define SATA0_CTRL_0_PW_CMD_ERROR_INTR_EN_SHIFT             _MK_SHIFT_CONST(24)                                                             // RWCVF
#define SATA0_CTRL_0_PW_CMD_ERROR_INTR_EN_FIELD            (_MK_SHIFT_CONST(0x1) << SATA0_CTRL_0_PW_CMD_ERROR_INTR_EN_SHIFT)
#define SATA0_CTRL_0_PW_CMD_ERROR_INTR_EN_RANGE            24:24
#define SATA0_CTRL_0_PW_CMD_ERROR_INTR_EN_WOFFSET          0
#define SATA0_CTRL_0_PW_CMD_ERROR_INTR_EN_YES              _MK_ENUM_CONST(0x00000001)                                                       // RW--V
#define SATA0_CTRL_0_PW_CMD_ERROR_INTR_EN_NO               _MK_ENUM_CONST(0x00000000)                                                       // RWC-V
#define SATA0_CTRL_0_NP_RSP_ERROR_INTR_EN_SHIFT             _MK_SHIFT_CONST(25)                                                             // RWCVF
#define SATA0_CTRL_0_NP_RSP_ERROR_INTR_EN_FIELD            (_MK_SHIFT_CONST(0x1) << SATA0_CTRL_0_NP_RSP_ERROR_INTR_EN_SHIFT)
#define SATA0_CTRL_0_NP_RSP_ERROR_INTR_EN_RANGE            25:25
#define SATA0_CTRL_0_NP_RSP_ERROR_INTR_EN_WOFFSET          0
#define SATA0_CTRL_0_NP_RSP_ERROR_INTR_EN_YES              _MK_ENUM_CONST(0x00000001)                                                       // RW--V
#define SATA0_CTRL_0_NP_RSP_ERROR_INTR_EN_NO               _MK_ENUM_CONST(0x00000000)                                                       // RWC-V
#define SATA0_CTRL_0_PW_CMD_ERROR_INTR_SHIFT                _MK_SHIFT_CONST(26)                                                             // RWCVF
#define SATA0_CTRL_0_PW_CMD_ERROR_INTR_FIELD               (_MK_SHIFT_CONST(0x1) << SATA0_CTRL_0_PW_CMD_ERROR_INTR_SHIFT)
#define SATA0_CTRL_0_PW_CMD_ERROR_INTR_RANGE               26:26
#define SATA0_CTRL_0_PW_CMD_ERROR_INTR_WOFFSET             0
#define SATA0_CTRL_0_PW_CMD_ERROR_INTR_YES                 _MK_ENUM_CONST(0x00000001)                                                       // RW--V
#define SATA0_CTRL_0_PW_CMD_ERROR_INTR_NO                  _MK_ENUM_CONST(0x00000000)                                                       // RWC-V
#define SATA0_CTRL_0_NP_RSP_ERROR_INTR_SHIFT                _MK_SHIFT_CONST(27)                                                             // RWCVF
#define SATA0_CTRL_0_NP_RSP_ERROR_INTR_FIELD               (_MK_SHIFT_CONST(0x1) << SATA0_CTRL_0_NP_RSP_ERROR_INTR_SHIFT)
#define SATA0_CTRL_0_NP_RSP_ERROR_INTR_RANGE               27:27
#define SATA0_CTRL_0_NP_RSP_ERROR_INTR_WOFFSET             0
#define SATA0_CTRL_0_NP_RSP_ERROR_INTR_YES                 _MK_ENUM_CONST(0x00000001)                                                       // RW--V
#define SATA0_CTRL_0_NP_RSP_ERROR_INTR_NO                  _MK_ENUM_CONST(0x00000000)                                                       // RWC-V
#define SATA0_CTRL_0_ENABLE_CH1_CH3_INTR_SHIFT              _MK_SHIFT_CONST(29)                                                             // RWCVF
#define SATA0_CTRL_0_ENABLE_CH1_CH3_INTR_FIELD             (_MK_SHIFT_CONST(0x1) << SATA0_CTRL_0_ENABLE_CH1_CH3_INTR_SHIFT)
#define SATA0_CTRL_0_ENABLE_CH1_CH3_INTR_RANGE             29:29
#define SATA0_CTRL_0_ENABLE_CH1_CH3_INTR_WOFFSET           0
#define SATA0_CTRL_0_ENABLE_CH1_CH3_INTR_YES               _MK_ENUM_CONST(0x00000001)                                                       // RWC-V
#define SATA0_CTRL_0_ENABLE_CH1_CH3_INTR_NO                _MK_ENUM_CONST(0x00000000)                                                       // RW--V
#define SATA0_CTRL_0_ENABLE_CH2_CH4_INTR_SHIFT              _MK_SHIFT_CONST(30)                                                             // RWCVF
#define SATA0_CTRL_0_ENABLE_CH2_CH4_INTR_FIELD             (_MK_SHIFT_CONST(0x1) << SATA0_CTRL_0_ENABLE_CH2_CH4_INTR_SHIFT)
#define SATA0_CTRL_0_ENABLE_CH2_CH4_INTR_RANGE             30:30
#define SATA0_CTRL_0_ENABLE_CH2_CH4_INTR_WOFFSET           0
#define SATA0_CTRL_0_ENABLE_CH2_CH4_INTR_YES               _MK_ENUM_CONST(0x00000001)                                                       // RWC-V
#define SATA0_CTRL_0_ENABLE_CH2_CH4_INTR_NO                _MK_ENUM_CONST(0x00000000)                                                       // RW--V
// 
// 
// .LABEL FUNC_DRIVER
// .LABEL PUBLIC
// .LABEL INT_REL
// .define T_SATA0_CTRL_BAR5_SPACE_EN                            2:2 /* RWCVF */
// .define T_SATA0_CTRL_BAR5_SPACE_EN_NO                  0x00000000 /* RW--V */
// .define T_SATA0_CTRL_BAR5_SPACE_EN_YES                 0x00000001 /* RWC-V */
// 
// .LABEL INT_REL
// 
// 
// .LABEL FUNC_BIOS
// .LABEL INT_REL
// 
// .LABEL INT_REL
// 
// 
// .LABEL PRIVATE INT_REL
// 
// 
// 
// 
// .LABEL FUNC_BIOS
// 
// 
// .LABEL PUBLIC INT_REL
// 
// .TITLE CFG_SATA
// .FIELD MSI_CAP_DISABLE
// Normally, the T_SATA0_CFG_17_NEXT_PTR field points to
// T_SATA0_MSI_CTRL (0xB0). However, if SATA_MSI_CAP_DISABLE is set to _YES, then the
// T_SATA0_CFG_17_NEXT_PTR field would point to _NULL. If future capabilities are added
// beyond the MSI pinter, then care should be taken to ensure that CFG_17_NEXT_PTR bypasses
// the T_SATA0_MSI_CTRL address and points to the next capabilities pointer instead of
// _NULL.
// 
// .FIELD USE_40B_ADDR
// If this bit is set then sata uses NVIDIA style 40b addressing while DMAing data. It gets
// upper 8 bits from the 23:16 bits of the prd count associated with the prd address.
// 
// 
// .LABEL PRIVATE INT_REL
// .FIELD RAID_MODE_CTRL
// CTRL_RAID_MODE was originally intended to allow customers to downgrade their RAID capability
// in the SBIOS.  Setting this bit to 0 would allow only RAID 0 and RAID 1 support in the driver
// while setting to 1 would allow all RAID support.  Setting this bit to 1 modifies the DeviceID
// of the SATA controller which would be a key to the driver.
// 
// // The reason this bit was added was so that OEM customers could provide full solutions that can be
// // upgraded to MS in-the-box drivers without having to undo the RAID configurations.  But MS
// // later changed their plan and allowed RAID support in the in-the-box drivers, so this feature
// // is no longer needed.  Now the STORAGE_FEATURE option, controlled by fuses, is the sole
// // controlling HW bit for RAID support.
// 
// .LABEL FUNC_DRIVER INT_REL
// .FIELD STORAGE_FEATURE
// STORAGE_FEATURE goes to both Sata and IDE config spaces. This is a general
// purpose bit that SW can use to distinguish between Advanced and Basic storage controller modes.
// // Comes from a fuse.
// 
// This bit will be interpreted to either allow or not allow RAID 0+1 or 5 mode.  ADVANCED
// mode will allow all RAID modes and BASIC will allow only RAID 0 and RAID 1 modes.
// 
// It is strongly encouraged to keep the meaning of this STORAGE_FEATURE bit the same for future
// chips and to create new bits if necessary.  This will allow SW compatibility.
// 
// .LABEL FUNC_BIOS
// .FIELD SATA_GEN2_CAPABLE
// SATA_GEN2_CAPABLE is read-only register that reflects the value of bond_sata2.  If high,
// GEN2 speed is enabled, if low, only GEN1 speed is available.
// 
// .LABEL PRIVATE INT_REL
// This register is also used to send near end loopback and reset the channels.
// The MIN_ON_TIME bits set the additional time the activity led remains lit
// after a transaction.  This keeps the LED from being a dim flicker during
// short burst.
// 
// .LABEL INT_REL
// .LABEL PUBLIC
#define SATA0_CFG_SATA_0                                   0x0000054C                                                                       // RW-4R
#define SATA0_CFG_SATA_0_SECURE                            0
#define SATA0_CFG_SATA_0_WORD_COUNT                        1
#define SATA0_CFG_SATA_0_RESET_VAL                         0x0
#define SATA0_CFG_SATA_0_RESET_MASK                        0x0
#define SATA0_CFG_SATA_0_SW_DEFAULT_VAL                    0x0
#define SATA0_CFG_SATA_0_SW_DEFAULT_MASK                   0x0
#define SATA0_CFG_SATA_0_READ_MASK                         0xffffffff
#define SATA0_CFG_SATA_0_WRITE_MASK                        0x19ffc
#define SATA0_CFG_SATA_0_RSVD_1_SHIFT                       _MK_SHIFT_CONST(17)                                                             // C--VF
#define SATA0_CFG_SATA_0_RSVD_1_FIELD                      (_MK_SHIFT_CONST(0x7fff) << SATA0_CFG_SATA_0_RSVD_1_SHIFT)
#define SATA0_CFG_SATA_0_RSVD_1_RANGE                      31:17
#define SATA0_CFG_SATA_0_RSVD_1_WOFFSET                    0
#define SATA0_CFG_SATA_0_RSVD_1_VAL                        _MK_ENUM_CONST(0x00000000)                                                       // C---V
#define SATA0_CFG_SATA_0_FORCE_NATIVE_SHIFT                 _MK_SHIFT_CONST(16)                                                             // RWC-F
#define SATA0_CFG_SATA_0_FORCE_NATIVE_FIELD                (_MK_SHIFT_CONST(0x1) << SATA0_CFG_SATA_0_FORCE_NATIVE_SHIFT)
#define SATA0_CFG_SATA_0_FORCE_NATIVE_RANGE                16:16
#define SATA0_CFG_SATA_0_FORCE_NATIVE_WOFFSET              0
#define SATA0_CFG_SATA_0_FORCE_NATIVE_ENABLED              _MK_ENUM_CONST(0x00000001)                                                       // RWC-V
#define SATA0_CFG_SATA_0_FORCE_NATIVE_DISABLED             _MK_ENUM_CONST(0x00000000)                                                       // RW--V
#define SATA0_CFG_SATA_0_CTRL_ALT_UID_SCHEME_SHIFT          _MK_SHIFT_CONST(15)                                                             // RWC-F
#define SATA0_CFG_SATA_0_CTRL_ALT_UID_SCHEME_FIELD         (_MK_SHIFT_CONST(0x1) << SATA0_CFG_SATA_0_CTRL_ALT_UID_SCHEME_SHIFT)
#define SATA0_CFG_SATA_0_CTRL_ALT_UID_SCHEME_RANGE         15:15
#define SATA0_CFG_SATA_0_CTRL_ALT_UID_SCHEME_WOFFSET       0
#define SATA0_CFG_SATA_0_CTRL_ALT_UID_SCHEME_INIT          _MK_ENUM_CONST(0x00000000)                                                       // RWC-V
#define SATA0_CFG_SATA_0_CTRL_SATA_GEN3_CAPABLE_SHIFT       _MK_SHIFT_CONST(14)                                                             // R-XVF
#define SATA0_CFG_SATA_0_CTRL_SATA_GEN3_CAPABLE_FIELD      (_MK_SHIFT_CONST(0x1) << SATA0_CFG_SATA_0_CTRL_SATA_GEN3_CAPABLE_SHIFT)
#define SATA0_CFG_SATA_0_CTRL_SATA_GEN3_CAPABLE_RANGE      14:14
#define SATA0_CFG_SATA_0_CTRL_SATA_GEN3_CAPABLE_WOFFSET    0
#define SATA0_CFG_SATA_0_CTRL_SATA_GEN3_CAPABLE_YES        _MK_ENUM_CONST(0x1)                                                              // ----V
#define SATA0_CFG_SATA_0_CTRL_SATA_GEN3_CAPABLE_NO         _MK_ENUM_CONST(0x0)                                                              // ----V
#define SATA0_CFG_SATA_0_CTRL_SATA_GEN2_CAPABLE_SHIFT       _MK_SHIFT_CONST(13)                                                             // R-XVF
#define SATA0_CFG_SATA_0_CTRL_SATA_GEN2_CAPABLE_FIELD      (_MK_SHIFT_CONST(0x1) << SATA0_CFG_SATA_0_CTRL_SATA_GEN2_CAPABLE_SHIFT)
#define SATA0_CFG_SATA_0_CTRL_SATA_GEN2_CAPABLE_RANGE      13:13
#define SATA0_CFG_SATA_0_CTRL_SATA_GEN2_CAPABLE_WOFFSET    0
#define SATA0_CFG_SATA_0_CTRL_SATA_GEN2_CAPABLE_YES        _MK_ENUM_CONST(0x1)                                                              // ----V
#define SATA0_CFG_SATA_0_CTRL_SATA_GEN2_CAPABLE_NO         _MK_ENUM_CONST(0x0)                                                              // ----V
#define SATA0_CFG_SATA_0_BACKDOOR_PROG_IF_EN_SHIFT          _MK_SHIFT_CONST(12)                                                             // RWC-F
#define SATA0_CFG_SATA_0_BACKDOOR_PROG_IF_EN_FIELD         (_MK_SHIFT_CONST(0x1) << SATA0_CFG_SATA_0_BACKDOOR_PROG_IF_EN_SHIFT)
#define SATA0_CFG_SATA_0_BACKDOOR_PROG_IF_EN_RANGE         12:12
#define SATA0_CFG_SATA_0_BACKDOOR_PROG_IF_EN_WOFFSET       0
#define SATA0_CFG_SATA_0_BACKDOOR_PROG_IF_EN_YES           _MK_ENUM_CONST(0x00000001)                                                       // RW--V
#define SATA0_CFG_SATA_0_BACKDOOR_PROG_IF_EN_NO            _MK_ENUM_CONST(0x00000000)                                                       // RWC-V
#define SATA0_CFG_SATA_0_PORT2UNITID_MAPPING_SHIFT          _MK_SHIFT_CONST(7)                                                              // RWC-F
#define SATA0_CFG_SATA_0_PORT2UNITID_MAPPING_FIELD         (_MK_SHIFT_CONST(0x1f) << SATA0_CFG_SATA_0_PORT2UNITID_MAPPING_SHIFT)
#define SATA0_CFG_SATA_0_PORT2UNITID_MAPPING_RANGE         11:7
#define SATA0_CFG_SATA_0_PORT2UNITID_MAPPING_WOFFSET       0
#define SATA0_CFG_SATA_0_MSI_CAP_DISABLE_SHIFT              _MK_SHIFT_CONST(6)                                                              // RWCVF
#define SATA0_CFG_SATA_0_MSI_CAP_DISABLE_FIELD             (_MK_SHIFT_CONST(0x1) << SATA0_CFG_SATA_0_MSI_CAP_DISABLE_SHIFT)
#define SATA0_CFG_SATA_0_MSI_CAP_DISABLE_RANGE             6:6
#define SATA0_CFG_SATA_0_MSI_CAP_DISABLE_WOFFSET           0
#define SATA0_CFG_SATA_0_MSI_CAP_DISABLE_NO                _MK_ENUM_CONST(0x00000000)                                                       // RWC-V
#define SATA0_CFG_SATA_0_MSI_CAP_DISABLE_YES               _MK_ENUM_CONST(0x00000001)                                                       // RW--V
#define SATA0_CFG_SATA_0_MSIX_CAP_DISABLE_SHIFT             _MK_SHIFT_CONST(5)                                                              // RWWVF
#define SATA0_CFG_SATA_0_MSIX_CAP_DISABLE_FIELD            (_MK_SHIFT_CONST(0x1) << SATA0_CFG_SATA_0_MSIX_CAP_DISABLE_SHIFT)
#define SATA0_CFG_SATA_0_MSIX_CAP_DISABLE_RANGE            5:5
#define SATA0_CFG_SATA_0_MSIX_CAP_DISABLE_WOFFSET          0
#define SATA0_CFG_SATA_0_MSIX_CAP_DISABLE_DEFAULT          (_MK_MASK_CONST(0x00000001)
#define SATA0_CFG_SATA_0_MSIX_CAP_DISABLE_DEFAULT_MASK     (_MK_MASK_CONST(0x1)
#define SATA0_CFG_SATA_0_MSIX_CAP_DISABLE_SW_DEFAULT       (_MK_MASK_CONST(0x00000001)
#define SATA0_CFG_SATA_0_MSIX_CAP_DISABLE_SW_DEFAULT_MASK  (_MK_MASK_CONST(0x1)
#define SATA0_CFG_SATA_0_MSIX_CAP_DISABLE_NO               _MK_ENUM_CONST(0x00000000)                                                       // RW--V
#define SATA0_CFG_SATA_0_MSIX_CAP_DISABLE_YES              _MK_ENUM_CONST(0x00000001)                                                       // RWW-V
#define SATA0_CFG_SATA_0_USE_40B_ADDR_SHIFT                 _MK_SHIFT_CONST(4)                                                              // RWCVF
#define SATA0_CFG_SATA_0_USE_40B_ADDR_FIELD                (_MK_SHIFT_CONST(0x1) << SATA0_CFG_SATA_0_USE_40B_ADDR_SHIFT)
#define SATA0_CFG_SATA_0_USE_40B_ADDR_RANGE                4:4
#define SATA0_CFG_SATA_0_USE_40B_ADDR_WOFFSET              0
#define SATA0_CFG_SATA_0_USE_40B_ADDR_NO                   _MK_ENUM_CONST(0x00000000)                                                       // RWC-V
#define SATA0_CFG_SATA_0_USE_40B_ADDR_YES                  _MK_ENUM_CONST(0x00000001)                                                       // RW--V
#define SATA0_CFG_SATA_0_ERROR_HANDLING_SHIFT               _MK_SHIFT_CONST(3)                                                              // RWCVF
#define SATA0_CFG_SATA_0_ERROR_HANDLING_FIELD              (_MK_SHIFT_CONST(0x1) << SATA0_CFG_SATA_0_ERROR_HANDLING_SHIFT)
#define SATA0_CFG_SATA_0_ERROR_HANDLING_RANGE              3:3
#define SATA0_CFG_SATA_0_ERROR_HANDLING_WOFFSET            0
#define SATA0_CFG_SATA_0_ERROR_HANDLING_NO                 _MK_ENUM_CONST(0x00000000)                                                       // RWC-V
#define SATA0_CFG_SATA_0_ERROR_HANDLING_YES                _MK_ENUM_CONST(0x00000001)                                                       // RW--V
#define SATA0_CFG_SATA_0_CTRL_RAID_MODE_CTRL_SHIFT          _MK_SHIFT_CONST(2)                                                              // RWCVF
#define SATA0_CFG_SATA_0_CTRL_RAID_MODE_CTRL_FIELD         (_MK_SHIFT_CONST(0x1) << SATA0_CFG_SATA_0_CTRL_RAID_MODE_CTRL_SHIFT)
#define SATA0_CFG_SATA_0_CTRL_RAID_MODE_CTRL_RANGE         2:2
#define SATA0_CFG_SATA_0_CTRL_RAID_MODE_CTRL_WOFFSET       0
#define SATA0_CFG_SATA_0_CTRL_RAID_MODE_CTRL_OEM           _MK_ENUM_CONST(0x00000000)                                                       // RWC-V
#define SATA0_CFG_SATA_0_CTRL_RAID_MODE_CTRL_CHANNEL       _MK_ENUM_CONST(0x00000001)                                                       // RW--V
#define SATA0_CFG_SATA_0_CTRL_STORAGE_FEATURE_SHIFT         _MK_SHIFT_CONST(1)                                                              // R-XVF
#define SATA0_CFG_SATA_0_CTRL_STORAGE_FEATURE_FIELD        (_MK_SHIFT_CONST(0x1) << SATA0_CFG_SATA_0_CTRL_STORAGE_FEATURE_SHIFT)
#define SATA0_CFG_SATA_0_CTRL_STORAGE_FEATURE_RANGE        1:1
#define SATA0_CFG_SATA_0_CTRL_STORAGE_FEATURE_WOFFSET      0
#define SATA0_CFG_SATA_0_CTRL_STORAGE_FEATURE_BASIC        _MK_ENUM_CONST(0x00000001)                                                       // ----V
#define SATA0_CFG_SATA_0_CTRL_STORAGE_FEATURE_ADVANCED     _MK_ENUM_CONST(0x00000000)                                                       // ----V
#define SATA0_CFG_SATA_0_RSVD_0_SHIFT                       _MK_SHIFT_CONST(0)                                                              // C--VF
#define SATA0_CFG_SATA_0_RSVD_0_FIELD                      (_MK_SHIFT_CONST(0x1) << SATA0_CFG_SATA_0_RSVD_0_SHIFT)
#define SATA0_CFG_SATA_0_RSVD_0_RANGE                      0:0
#define SATA0_CFG_SATA_0_RSVD_0_WOFFSET                    0
#define SATA0_CFG_SATA_0_RSVD_0_VAL                        _MK_ENUM_CONST(0x00000000)                                                       // C---V
// 
// .LABEL PRIVATE INT_REL
// 
// 
// .LABEL INT_REL
// 
// .LABEL PRIVATE INT_REL
// 
// 
// .LABEL FUNC_BIOS
// .LABEL PRIVATE INT_REL
// 
// .LABEL FUNC_BIOS
// .LABEL PRIVATE INT_REL
// 
// .LABEL INT_REL
// 
// .LABEL PRIVATE INT_REL
// 
// .LABEL INT_REL
// .LABEL PUBLIC
// 
// .LABEL INT_REL
// 
// .LABEL PUBLIC
// 
// .LABEL PUBLIC
// 
// .LABEL PRIVATE INT_REL
// 
// .LABEL FUNC_DRIVER INT_REL
// 
// .LABEL PRIVATE INT_REL
// 
// .LABEL PUBLIC
// 
// .LABEL PRIVATE
// .TITLE CFG_MISC
// This register controls various aspects of the SATA/PHY interaction.
// 
// .FIELD CFG_OOB_SM_DEBUG
// Bit 1 is used to control our comreset behaviour.
// If this bit is set to 1 then we send only one COMRESET to drive when scontrol_det[0] bit
// is written. If this bit is 0 then we keep sending COMRESET sequences as long as scontrol_det bit
// is active.
// 
// .FIELD CFG_LINK_SM_DEBUG
// Bit 0 enables holda bypass.
// Bits 3 and 2 control l_idle features.
// 
// .FIELD CFG_TRNSPRT_SM_DEBUG
// Bit 0 controls use of lockdet as phy reset.
// Bit 1 when high lets us update ata status reg quickly during pio-writes. By default its high.
// Bit 2 controls pi_reset.
// .LABEL PRIVATE
// By default let the POR be one, which indicates lockdet will be used for reset and change it to
// 4 whenever PLL shutdown is enabled in driver.
// SW_INIT needed
// 
// DEBUG* goes to dbg; rest to cfg
// .LABEL PRIVATE INT_REL
// .FIELD PHY_OOB_SEQ_MODE
//   bit 0 controls whether we need to back off sending comwake when we receive comwake from drive
//   Bit 1 is used to control our comreset behaviour.
//   If this bit is set to 1 then we send only one COMRESET to drive when scontrol_det[0] bit
//   is written. If this bit is 0 then we keep sending COMRESET sequences as long as scontrol_det bit
//   is active.
// 
// .FIELD LINK_SM_MODE
//   Bit 0 enables holda bypass.
//   Bits 3 and 2 control l_idle features.
// 
// .FIELD PHY_RESET_USAGE_MODE
// Bit 0 controls use of lockdet as phy reset.
// Bit 1 when high lets us update ata status reg quickly during pio-writes. By default its high.
// Bit 2 controls pi_reset, it controls whether to use lockdet or a cfg bit to use as reset
// .LABEL PRIVATE
// By default let the POR be one, which indicates lockdet will be used for reset and change it to
// 4 whenever PLL shutdown is enabled in driver.
// SW_INIT needed
// .LABEL PRIVATE INT_REL
// 
// 
//  31           24 23           16 15            8 7             0
// .-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-.
// |0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0|       |       |       | CFG_PHY_RESET
// +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
#define SATA0_DBG0_0                                       0x00000550                                                                       // RWW4R
#define SATA0_DBG0_0_SECURE                                0
#define SATA0_DBG0_0_WORD_COUNT                            1
#define SATA0_DBG0_0_RESET_VAL                             0x0
#define SATA0_DBG0_0_RESET_MASK                            0x0
#define SATA0_DBG0_0_SW_DEFAULT_VAL                        0x0
#define SATA0_DBG0_0_SW_DEFAULT_MASK                       0x0
#define SATA0_DBG0_0_READ_MASK                             0xfff
#define SATA0_DBG0_0_WRITE_MASK                            0xfff
#define SATA0_DBG0_0_CFG_OOB_SM_DEBUG_SHIFT                 _MK_SHIFT_CONST(0)                                                              // RWC-F
#define SATA0_DBG0_0_CFG_OOB_SM_DEBUG_FIELD                (_MK_SHIFT_CONST(0xf) << SATA0_DBG0_0_CFG_OOB_SM_DEBUG_SHIFT)
#define SATA0_DBG0_0_CFG_OOB_SM_DEBUG_RANGE                3:0
#define SATA0_DBG0_0_CFG_OOB_SM_DEBUG_WOFFSET              0
#define SATA0_DBG0_0_CFG_OOB_SM_DEBUG_INIT                 _MK_ENUM_CONST(0x00000003)                                                       // RWC-V
#define SATA0_DBG0_0_CFG_LINK_SM_DEBUG_SHIFT                _MK_SHIFT_CONST(4)                                                              // RWC-F
#define SATA0_DBG0_0_CFG_LINK_SM_DEBUG_FIELD               (_MK_SHIFT_CONST(0xf) << SATA0_DBG0_0_CFG_LINK_SM_DEBUG_SHIFT)
#define SATA0_DBG0_0_CFG_LINK_SM_DEBUG_RANGE               7:4
#define SATA0_DBG0_0_CFG_LINK_SM_DEBUG_WOFFSET             0
#define SATA0_DBG0_0_CFG_LINK_SM_DEBUG__WRNPRDCHK          _MK_ENUM_CONST(0x00000001)                                                       // ----V
#define SATA0_DBG0_0_CFG_LINK_SM_DEBUG_INIT                _MK_ENUM_CONST(0x00000006)                                                       // RWC-V
#define SATA0_DBG0_0_CFG_TRNSPRT_SM_DEBUG_SHIFT             _MK_SHIFT_CONST(8)                                                              // RWC-F
#define SATA0_DBG0_0_CFG_TRNSPRT_SM_DEBUG_FIELD            (_MK_SHIFT_CONST(0xf) << SATA0_DBG0_0_CFG_TRNSPRT_SM_DEBUG_SHIFT)
#define SATA0_DBG0_0_CFG_TRNSPRT_SM_DEBUG_RANGE            11:8
#define SATA0_DBG0_0_CFG_TRNSPRT_SM_DEBUG_WOFFSET          0
#define SATA0_DBG0_0_CFG_TRNSPRT_SM_DEBUG_INIT             _MK_ENUM_CONST(0x00000001)                                                       // RWC-V
// .define T_SATA0_CFG_MISC                               0x00000550 /* RWW4R */
// .LABEL PRIVATE INT_REL
// 
// .define T_SATA0_CFG__PHY_OOB_SEQ_MODE                     3:0 /* RWC-F */
// .define T_SATA0_CFG__PHY_OOB_SEQ_MODE_INIT         0x00000003 /* RWC-V */
// 
// .define T_SATA0_CFG__LINK_SM_MODE                         7:4 /* RWC-F */
// .define T_SATA0_CFG__LINK_SM_MODE__WRNPRDCHK       0x00000001 /* ----V */
// .define T_SATA0_CFG__LINK_SM_MODE_INIT             0x00000006 /* RWC-V */
// 
// .LABEL PRIVATE INT_REL
// .define T_SATA0_CFG__PHY_RESET_USAGE_MODE                11:8 /* RWC-F */
// .define T_SATA0_CFG__PHY_RESET_USAGE_MODE_INIT     0x00000001 /* RWC-V */
// 
// .LABEL PRIVATE INT_REL
// 
//  31           24 23           16 15            8 7             0
// .-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-.
// |                                                           |100| CFG_26
// +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
// 
#define SATA0_LOWPOWER_COUNT_0                             0x00000554                                                                       // RWW4R
#define SATA0_LOWPOWER_COUNT_0_SECURE                      0
#define SATA0_LOWPOWER_COUNT_0_WORD_COUNT                  1
#define SATA0_LOWPOWER_COUNT_0_RESET_VAL                   0x0
#define SATA0_LOWPOWER_COUNT_0_RESET_MASK                  0x0
#define SATA0_LOWPOWER_COUNT_0_SW_DEFAULT_VAL              0x0
#define SATA0_LOWPOWER_COUNT_0_SW_DEFAULT_MASK             0x0
#define SATA0_LOWPOWER_COUNT_0_READ_MASK                   0xffffffff
#define SATA0_LOWPOWER_COUNT_0_WRITE_MASK                  0xff
#define SATA0_LOWPOWER_COUNT_0_PARTIAL_SHIFT                _MK_SHIFT_CONST(0)                                                              // RWW-F
#define SATA0_LOWPOWER_COUNT_0_PARTIAL_FIELD               (_MK_SHIFT_CONST(0xf) << SATA0_LOWPOWER_COUNT_0_PARTIAL_SHIFT)
#define SATA0_LOWPOWER_COUNT_0_PARTIAL_RANGE               3:0
#define SATA0_LOWPOWER_COUNT_0_PARTIAL_WOFFSET             0
#define SATA0_LOWPOWER_COUNT_0_PARTIAL_DEFAULT             (_MK_MASK_CONST(0x00000004)
#define SATA0_LOWPOWER_COUNT_0_PARTIAL_DEFAULT_MASK        (_MK_MASK_CONST(0xf)
#define SATA0_LOWPOWER_COUNT_0_PARTIAL_SW_DEFAULT          (_MK_MASK_CONST(0x00000004)
#define SATA0_LOWPOWER_COUNT_0_PARTIAL_SW_DEFAULT_MASK     (_MK_MASK_CONST(0xf)
#define SATA0_LOWPOWER_COUNT_0_PARTIAL_INIT                _MK_ENUM_CONST(0x00000004)                                                       // RWW-V
#define SATA0_LOWPOWER_COUNT_0_SLUMBER_SHIFT                _MK_SHIFT_CONST(4)                                                              // RWW-F
#define SATA0_LOWPOWER_COUNT_0_SLUMBER_FIELD               (_MK_SHIFT_CONST(0xf) << SATA0_LOWPOWER_COUNT_0_SLUMBER_SHIFT)
#define SATA0_LOWPOWER_COUNT_0_SLUMBER_RANGE               7:4
#define SATA0_LOWPOWER_COUNT_0_SLUMBER_WOFFSET             0
#define SATA0_LOWPOWER_COUNT_0_SLUMBER_DEFAULT             (_MK_MASK_CONST(0x00000004)
#define SATA0_LOWPOWER_COUNT_0_SLUMBER_DEFAULT_MASK        (_MK_MASK_CONST(0xf)
#define SATA0_LOWPOWER_COUNT_0_SLUMBER_SW_DEFAULT          (_MK_MASK_CONST(0x00000004)
#define SATA0_LOWPOWER_COUNT_0_SLUMBER_SW_DEFAULT_MASK     (_MK_MASK_CONST(0xf)
#define SATA0_LOWPOWER_COUNT_0_SLUMBER_INIT                _MK_ENUM_CONST(0x00000004)                                                       // RWW-V
#define SATA0_LOWPOWER_COUNT_0_RSVD_SHIFT                   _MK_SHIFT_CONST(8)                                                              // C--VF
#define SATA0_LOWPOWER_COUNT_0_RSVD_FIELD                  (_MK_SHIFT_CONST(0xffffff) << SATA0_LOWPOWER_COUNT_0_RSVD_SHIFT)
#define SATA0_LOWPOWER_COUNT_0_RSVD_RANGE                  31:8
#define SATA0_LOWPOWER_COUNT_0_RSVD_WOFFSET                0
#define SATA0_LOWPOWER_COUNT_0_RSVD_31_8                   _MK_ENUM_CONST(0x00000000)                                                       // C---V
// 
// 
//         Figure 10-26  Serial ATA Control Register 6Ch
// .LABEL PUBLIC
// 
// .LABEL PRIVATE INT_REL
// This register contains various bits to control the phy
//  31           24 23           16 15            8 7             0
// .-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-.
// |               | | |   | | | | |   |   |   |   | |             | DEVSLP_CTRL0
// +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
#define SATA0_DEVSLP_CTRL0_0                               0x00000558                                                                       // R--4R
#define SATA0_DEVSLP_CTRL0_0_SECURE                        0
#define SATA0_DEVSLP_CTRL0_0_WORD_COUNT                    1
#define SATA0_DEVSLP_CTRL0_0_RESET_VAL                     0x0
#define SATA0_DEVSLP_CTRL0_0_RESET_MASK                    0x0
#define SATA0_DEVSLP_CTRL0_0_SW_DEFAULT_VAL                0x0
#define SATA0_DEVSLP_CTRL0_0_SW_DEFAULT_MASK               0x0
#define SATA0_DEVSLP_CTRL0_0_READ_MASK                     0x1
#define SATA0_DEVSLP_CTRL0_0_WRITE_MASK                    0x0
#define SATA0_DEVSLP_CTRL0_0_PORT0_INTFC_IN_PARTIAL_OR_SLUMBER_SHIFT  _MK_SHIFT_CONST(0)                                                              // R--VF
#define SATA0_DEVSLP_CTRL0_0_PORT0_INTFC_IN_PARTIAL_OR_SLUMBER_FIELD (_MK_SHIFT_CONST(0x1) << SATA0_DEVSLP_CTRL0_0_PORT0_INTFC_IN_PARTIAL_OR_SLUMBER_SHIFT)
#define SATA0_DEVSLP_CTRL0_0_PORT0_INTFC_IN_PARTIAL_OR_SLUMBER_RANGE 0:0
#define SATA0_DEVSLP_CTRL0_0_PORT0_INTFC_IN_PARTIAL_OR_SLUMBER_WOFFSET 0
// 
// .LABEL PUBLIC
// 
// 
// .LABEL PRIVATE INT_REL
// .TITLE SPARE_0
// spare register on cold reset with zero as the default value
// 31           24 23           16 15            8 7             0
// .-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-.
// |                                                               | AO_SPARE_0
// +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
#define SATA0_AO_SPARE_0_0                                 0x00000580                                                                       // RW-4R
#define SATA0_AO_SPARE_0_0_SECURE                          0
#define SATA0_AO_SPARE_0_0_WORD_COUNT                      1
#define SATA0_AO_SPARE_0_0_RESET_VAL                       0x0
#define SATA0_AO_SPARE_0_0_RESET_MASK                      0x0
#define SATA0_AO_SPARE_0_0_SW_DEFAULT_VAL                  0x0
#define SATA0_AO_SPARE_0_0_SW_DEFAULT_MASK                 0x0
#define SATA0_AO_SPARE_0_0_READ_MASK                       0xffffffff
#define SATA0_AO_SPARE_0_0_WRITE_MASK                      0xffffffff
#define SATA0_AO_SPARE_0_0_RSVD_SHIFT                       _MK_SHIFT_CONST(0)                                                              // RWCVF
#define SATA0_AO_SPARE_0_0_RSVD_FIELD                      (_MK_SHIFT_CONST(0xffffffff) << SATA0_AO_SPARE_0_0_RSVD_SHIFT)
#define SATA0_AO_SPARE_0_0_RSVD_RANGE                      31:0
#define SATA0_AO_SPARE_0_0_RSVD_WOFFSET                    0
// 
// 
// .LABEL PRIVATE INT_REL
// .TITLE SPARE_1
// spare register on cold reset with zero as the default value
// 31           24 23           16 15            8 7             0
// .-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-.
// |                                                               | AO_SPARE_1
// +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
#define SATA0_AO_SPARE_1_0                                 0x00000584                                                                       // RW-4R
#define SATA0_AO_SPARE_1_0_SECURE                          0
#define SATA0_AO_SPARE_1_0_WORD_COUNT                      1
#define SATA0_AO_SPARE_1_0_RESET_VAL                       0x0
#define SATA0_AO_SPARE_1_0_RESET_MASK                      0x0
#define SATA0_AO_SPARE_1_0_SW_DEFAULT_VAL                  0x0
#define SATA0_AO_SPARE_1_0_SW_DEFAULT_MASK                 0x0
#define SATA0_AO_SPARE_1_0_READ_MASK                       0xffffffff
#define SATA0_AO_SPARE_1_0_WRITE_MASK                      0xffffffff
#define SATA0_AO_SPARE_1_0_RSVD_SHIFT                       _MK_SHIFT_CONST(0)                                                              // RWWVF
#define SATA0_AO_SPARE_1_0_RSVD_FIELD                      (_MK_SHIFT_CONST(0xffffffff) << SATA0_AO_SPARE_1_0_RSVD_SHIFT)
#define SATA0_AO_SPARE_1_0_RSVD_RANGE                      31:0
#define SATA0_AO_SPARE_1_0_RSVD_WOFFSET                    0
#define SATA0_AO_SPARE_1_0_RSVD_DEFAULT                    (_MK_MASK_CONST(0xF0F0F0F0)
#define SATA0_AO_SPARE_1_0_RSVD_DEFAULT_MASK               (_MK_MASK_CONST(0xffffffff)
#define SATA0_AO_SPARE_1_0_RSVD_SW_DEFAULT                 (_MK_MASK_CONST(0xF0F0F0F0)
#define SATA0_AO_SPARE_1_0_RSVD_SW_DEFAULT_MASK            (_MK_MASK_CONST(0xffffffff)
// .LABEL PUBLIC
// 
// 
// .LABEL ANALOG_PUBLIC
// .LABEL ANALOG_PRIVATE
// .LABEL INT_REL
// 
// .TITLE Index Mask register E8h
// 
// This register implements mask to select writes to channel specific registers.
// A write to any CHX field in this manual will affect corresponding register for channel n
// if the nth bit is set in this mask register. If mask register has no bits set then the
// write will not change any register.
// 
// A read from a CHX field will return data corresponding to the channel which has its
// mask set. If more than one bits are set in mask, then the returned data will be logical OR
// of register values corresponding to the channels which have mask bits set. If no mask bit
// is set then the returned value will be 0x00.
// 
// The following comment is no longer valid, separate registers are implemented for GEN[1,2,3]
// Further PEAK and AMP fields can be set differently for gen1 and gen2. A write to these fields
// will affect setting for genx if bit corresponding to genx is set in this register.
// 
// 
// 31           24 23           16 15            8 7             0
// .-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-.
// |0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0| INDEX
// `-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-'
// 
#define SATA0_INDEX_0                                      0x00000680                                                                       // RWC4R
#define SATA0_INDEX_0_SECURE                               0
#define SATA0_INDEX_0_WORD_COUNT                           1
#define SATA0_INDEX_0_RESET_VAL                            0x0
#define SATA0_INDEX_0_RESET_MASK                           0x0
#define SATA0_INDEX_0_SW_DEFAULT_VAL                       0x0
#define SATA0_INDEX_0_SW_DEFAULT_MASK                      0x0
#define SATA0_INDEX_0_READ_MASK                            0xffffffff
#define SATA0_INDEX_0_WRITE_MASK                           0xffffffff
#define SATA0_INDEX_0_CH1_SHIFT                             _MK_SHIFT_CONST(0)                                                              // RWC-F
#define SATA0_INDEX_0_CH1_FIELD                            (_MK_SHIFT_CONST(0x1) << SATA0_INDEX_0_CH1_SHIFT)
#define SATA0_INDEX_0_CH1_RANGE                            0:0
#define SATA0_INDEX_0_CH1_WOFFSET                          0
#define SATA0_INDEX_0_CH1__NOPRDCHK                        _MK_ENUM_CONST(0x00000001)                                                       // ----V
#define SATA0_INDEX_0_CH1_UNSELECTED                       _MK_ENUM_CONST(0x00000000)                                                       // RWC-V
#define SATA0_INDEX_0_CH1_SELECTED                         _MK_ENUM_CONST(0x00000001)                                                       // RW--V
#define SATA0_INDEX_0_CH2_SHIFT                             _MK_SHIFT_CONST(1)                                                              // RWC-F
#define SATA0_INDEX_0_CH2_FIELD                            (_MK_SHIFT_CONST(0x1) << SATA0_INDEX_0_CH2_SHIFT)
#define SATA0_INDEX_0_CH2_RANGE                            1:1
#define SATA0_INDEX_0_CH2_WOFFSET                          0
#define SATA0_INDEX_0_CH2__NOPRDCHK                        _MK_ENUM_CONST(0x00000001)                                                       // ----V
#define SATA0_INDEX_0_CH2_UNSELECTED                       _MK_ENUM_CONST(0x00000000)                                                       // RWC-V
#define SATA0_INDEX_0_CH2_SELECTED                         _MK_ENUM_CONST(0x00000001)                                                       // RW--V
#define SATA0_INDEX_0_CH3_SHIFT                             _MK_SHIFT_CONST(2)                                                              // RWC-F
#define SATA0_INDEX_0_CH3_FIELD                            (_MK_SHIFT_CONST(0x1) << SATA0_INDEX_0_CH3_SHIFT)
#define SATA0_INDEX_0_CH3_RANGE                            2:2
#define SATA0_INDEX_0_CH3_WOFFSET                          0
#define SATA0_INDEX_0_CH3__NOPRDCHK                        _MK_ENUM_CONST(0x00000001)                                                       // ----V
#define SATA0_INDEX_0_CH3_UNSELECTED                       _MK_ENUM_CONST(0x00000000)                                                       // RWC-V
#define SATA0_INDEX_0_CH3_SELECTED                         _MK_ENUM_CONST(0x00000001)                                                       // RW--V
#define SATA0_INDEX_0_CH4_SHIFT                             _MK_SHIFT_CONST(3)                                                              // RWC-F
#define SATA0_INDEX_0_CH4_FIELD                            (_MK_SHIFT_CONST(0x1) << SATA0_INDEX_0_CH4_SHIFT)
#define SATA0_INDEX_0_CH4_RANGE                            3:3
#define SATA0_INDEX_0_CH4_WOFFSET                          0
#define SATA0_INDEX_0_CH4__NOPRDCHK                        _MK_ENUM_CONST(0x00000001)                                                       // ----V
#define SATA0_INDEX_0_CH4_UNSELECTED                       _MK_ENUM_CONST(0x00000000)                                                       // RWC-V
#define SATA0_INDEX_0_CH4_SELECTED                         _MK_ENUM_CONST(0x00000001)                                                       // RW--V
#define SATA0_INDEX_0_CH5_SHIFT                             _MK_SHIFT_CONST(4)                                                              // RWC-F
#define SATA0_INDEX_0_CH5_FIELD                            (_MK_SHIFT_CONST(0x1) << SATA0_INDEX_0_CH5_SHIFT)
#define SATA0_INDEX_0_CH5_RANGE                            4:4
#define SATA0_INDEX_0_CH5_WOFFSET                          0
#define SATA0_INDEX_0_CH5_UNSELECTED                       _MK_ENUM_CONST(0x00000000)                                                       // RWC-V
#define SATA0_INDEX_0_CH5_SELECTED                         _MK_ENUM_CONST(0x00000001)                                                       // RW--V
#define SATA0_INDEX_0_CH6_SHIFT                             _MK_SHIFT_CONST(5)                                                              // RWC-F
#define SATA0_INDEX_0_CH6_FIELD                            (_MK_SHIFT_CONST(0x1) << SATA0_INDEX_0_CH6_SHIFT)
#define SATA0_INDEX_0_CH6_RANGE                            5:5
#define SATA0_INDEX_0_CH6_WOFFSET                          0
#define SATA0_INDEX_0_CH6_UNSELECTED                       _MK_ENUM_CONST(0x00000000)                                                       // RWC-V
#define SATA0_INDEX_0_CH6_SELECTED                         _MK_ENUM_CONST(0x00000001)                                                       // RW--V
#define SATA0_INDEX_0_CH7_SHIFT                             _MK_SHIFT_CONST(6)                                                              // RWC-F
#define SATA0_INDEX_0_CH7_FIELD                            (_MK_SHIFT_CONST(0x1) << SATA0_INDEX_0_CH7_SHIFT)
#define SATA0_INDEX_0_CH7_RANGE                            6:6
#define SATA0_INDEX_0_CH7_WOFFSET                          0
#define SATA0_INDEX_0_CH7_UNSELECTED                       _MK_ENUM_CONST(0x00000000)                                                       // RWC-V
#define SATA0_INDEX_0_CH7_SELECTED                         _MK_ENUM_CONST(0x00000001)                                                       // RW--V
#define SATA0_INDEX_0_CH8_SHIFT                             _MK_SHIFT_CONST(7)                                                              // RWC-F
#define SATA0_INDEX_0_CH8_FIELD                            (_MK_SHIFT_CONST(0x1) << SATA0_INDEX_0_CH8_SHIFT)
#define SATA0_INDEX_0_CH8_RANGE                            7:7
#define SATA0_INDEX_0_CH8_WOFFSET                          0
#define SATA0_INDEX_0_CH8_UNSELECTED                       _MK_ENUM_CONST(0x00000000)                                                       // RWC-V
#define SATA0_INDEX_0_CH8_SELECTED                         _MK_ENUM_CONST(0x00000001)                                                       // RW--V
#define SATA0_INDEX_0_RESERVED_SHIFT                        _MK_SHIFT_CONST(8)                                                              // RWC-F
#define SATA0_INDEX_0_RESERVED_FIELD                       (_MK_SHIFT_CONST(0xffffff) << SATA0_INDEX_0_RESERVED_SHIFT)
#define SATA0_INDEX_0_RESERVED_RANGE                       31:8
#define SATA0_INDEX_0_RESERVED_WOFFSET                     0
#define SATA0_INDEX_0_RESERVED_0                           _MK_ENUM_CONST(0x00000000)                                                       // RWC-V
// 
// 
// 
// 
// 
// .LABEL PRIVATE
// 
// 
// 
// 
// .LABEL PUBLIC
// .LABEL ANALOG_PRIVATE INT_REL
// .TITLE SATA MISC CONTROL REGISTER
// 
//  31           24 23           16 15            8 7             0
// .-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-.
// |0 0 0 0 0 0 0 0| | |   | | | | |   |   |0 0|   |0|     |0|     | MISC
// +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
// 
#define SATA0_CHX_MISC_0                                   0x00000684                                                                       // RWW4R
#define SATA0_CHX_MISC_0_SECURE                            0
#define SATA0_CHX_MISC_0_WORD_COUNT                        1
#define SATA0_CHX_MISC_0_RESET_VAL                         0x0
#define SATA0_CHX_MISC_0_RESET_MASK                        0x0
#define SATA0_CHX_MISC_0_SW_DEFAULT_VAL                    0x0
#define SATA0_CHX_MISC_0_SW_DEFAULT_MASK                   0x0
#define SATA0_CHX_MISC_0_READ_MASK                         0x1
#define SATA0_CHX_MISC_0_WRITE_MASK                        0x1
#define SATA0_CHX_MISC_0_LED_DISABLE_SHIFT                  _MK_SHIFT_CONST(0)                                                              // RWCVF
#define SATA0_CHX_MISC_0_LED_DISABLE_FIELD                 (_MK_SHIFT_CONST(0x1) << SATA0_CHX_MISC_0_LED_DISABLE_SHIFT)
#define SATA0_CHX_MISC_0_LED_DISABLE_RANGE                 0:0
#define SATA0_CHX_MISC_0_LED_DISABLE_WOFFSET               0
// 
// 
// .LABEL PUBLIC
// 
// .LABEL ANALOG_PUBLIC
// .LABEL ANALOG_PRIVATE INT_REL
// .TITLE SATA PHY Control Register(GEN1)
// .FIELD AMP
// This field contains the AMP values for gen1
// This register may have different values based on port usage (esata,gen1,gen)
// 
// .FIELD PEAK
// This field contains the PEAK values for gen1.
// 
//  31           24 23           16 15            8 7             0
// .-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-.
// |     |     | |  |   | |     | | | | ||     | | | | |   |   |   | CHX_PHY_CTRL1_GEN1
// +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
#define SATA0_CHX_PHY_CTRL1_GEN1_0                         0x00000690                                                                       // RWW4R
#define SATA0_CHX_PHY_CTRL1_GEN1_0_SECURE                  0
#define SATA0_CHX_PHY_CTRL1_GEN1_0_WORD_COUNT              1
#define SATA0_CHX_PHY_CTRL1_GEN1_0_RESET_VAL               0x0
#define SATA0_CHX_PHY_CTRL1_GEN1_0_RESET_MASK              0x0
#define SATA0_CHX_PHY_CTRL1_GEN1_0_SW_DEFAULT_VAL          0x0
#define SATA0_CHX_PHY_CTRL1_GEN1_0_SW_DEFAULT_MASK         0x0
#define SATA0_CHX_PHY_CTRL1_GEN1_0_READ_MASK               0x3fffffff
#define SATA0_CHX_PHY_CTRL1_GEN1_0_WRITE_MASK              0x3fffffff
#define SATA0_CHX_PHY_CTRL1_GEN1_0_TX_AMP_SHIFT             _MK_SHIFT_CONST(0)                                                              // RWCVF
#define SATA0_CHX_PHY_CTRL1_GEN1_0_TX_AMP_FIELD            (_MK_SHIFT_CONST(0xff) << SATA0_CHX_PHY_CTRL1_GEN1_0_TX_AMP_SHIFT)
#define SATA0_CHX_PHY_CTRL1_GEN1_0_TX_AMP_RANGE            7:0
#define SATA0_CHX_PHY_CTRL1_GEN1_0_TX_AMP_WOFFSET          0
#define SATA0_CHX_PHY_CTRL1_GEN1_0_TX_AMP__WRNPRDCHK       _MK_ENUM_CONST(0x00000001)                                                       // ----V
#define SATA0_CHX_PHY_CTRL1_GEN1_0_TX_AMP_DEFAULT2         _MK_ENUM_CONST(0x00000012)                                                       // RW--V
#define SATA0_CHX_PHY_CTRL1_GEN1_0_TX_AMP_DEFAULT3         _MK_ENUM_CONST(0x0000000F)                                                       // RW--V
#define SATA0_CHX_PHY_CTRL1_GEN1_0_TX_AMP_DEFAULT4         _MK_ENUM_CONST(0x00000018)                                                       // RW--V
#define SATA0_CHX_PHY_CTRL1_GEN1_0_TX_AMP_ESATA            _MK_ENUM_CONST(0x00000014)                                                       // RW--V
#define SATA0_CHX_PHY_CTRL1_GEN1_0_TX_PEAK_SHIFT            _MK_SHIFT_CONST(8)                                                              // RWCVF
#define SATA0_CHX_PHY_CTRL1_GEN1_0_TX_PEAK_FIELD           (_MK_SHIFT_CONST(0xff) << SATA0_CHX_PHY_CTRL1_GEN1_0_TX_PEAK_SHIFT)
#define SATA0_CHX_PHY_CTRL1_GEN1_0_TX_PEAK_RANGE           15:8
#define SATA0_CHX_PHY_CTRL1_GEN1_0_TX_PEAK_WOFFSET         0
#define SATA0_CHX_PHY_CTRL1_GEN1_0_TX_PEAK__WRNPRDCHK      _MK_ENUM_CONST(0x00000001)                                                       // ----V
#define SATA0_CHX_PHY_CTRL1_GEN1_0_TX_PEAK_DEFAULT2        _MK_ENUM_CONST(0x00000005)                                                       // RW--V
#define SATA0_CHX_PHY_CTRL1_GEN1_0_TX_PEAK_DEFAULT3        _MK_ENUM_CONST(0x00000004)                                                       // RW--V
#define SATA0_CHX_PHY_CTRL1_GEN1_0_TX_PEAK_DEFAULT4        _MK_ENUM_CONST(0x0000000A)                                                       // RW--V
#define SATA0_CHX_PHY_CTRL1_GEN1_0_TX_PEAK_ESATA           _MK_ENUM_CONST(0x0000000E)                                                       // RW--V
#define SATA0_CHX_PHY_CTRL1_GEN1_0_TX_CMADJ_SHIFT           _MK_SHIFT_CONST(16)                                                             // RWCVF
#define SATA0_CHX_PHY_CTRL1_GEN1_0_TX_CMADJ_FIELD          (_MK_SHIFT_CONST(0xf) << SATA0_CHX_PHY_CTRL1_GEN1_0_TX_CMADJ_SHIFT)
#define SATA0_CHX_PHY_CTRL1_GEN1_0_TX_CMADJ_RANGE          19:16
#define SATA0_CHX_PHY_CTRL1_GEN1_0_TX_CMADJ_WOFFSET        0
#define SATA0_CHX_PHY_CTRL1_GEN1_0_TX_PEAK_PRE_SHIFT        _MK_SHIFT_CONST(20)                                                             // RWCVF
#define SATA0_CHX_PHY_CTRL1_GEN1_0_TX_PEAK_PRE_FIELD       (_MK_SHIFT_CONST(0x3f) << SATA0_CHX_PHY_CTRL1_GEN1_0_TX_PEAK_PRE_SHIFT)
#define SATA0_CHX_PHY_CTRL1_GEN1_0_TX_PEAK_PRE_RANGE       25:20
#define SATA0_CHX_PHY_CTRL1_GEN1_0_TX_PEAK_PRE_WOFFSET     0
#define SATA0_CHX_PHY_CTRL1_GEN1_0_TX_DRV_CNTL_SHIFT        _MK_SHIFT_CONST(26)                                                             // RWCVF
#define SATA0_CHX_PHY_CTRL1_GEN1_0_TX_DRV_CNTL_FIELD       (_MK_SHIFT_CONST(0xf) << SATA0_CHX_PHY_CTRL1_GEN1_0_TX_DRV_CNTL_SHIFT)
#define SATA0_CHX_PHY_CTRL1_GEN1_0_TX_DRV_CNTL_RANGE       29:26
#define SATA0_CHX_PHY_CTRL1_GEN1_0_TX_DRV_CNTL_WOFFSET     0
// 
// .LABEL ANALOG_PUBLIC
// .LABEL ANALOG_PRIVATE INT_REL
// 
// .LABEL ANALOG_PUBLIC
// .LABEL ANALOG_PRIVATE INT_REL
// 
// .LABEL ANALOG_PRIVATE INT_REL
// 
// .LABEL ANALOG_PRIVATE INT_REL
// 
// 
// 
//         Figure 10-44  Serial ATA Channel 1 PHY Control register
// .LABEL PUBLIC
// 
// // GEN1 and GEN2 values can now be used separately, no need of writing T_SATA0_CH1_PHY_CTRL_INDEX
// //  prior to this for AMP and PEAK, however to select a channel, we need to still write
// //  T_SATA0_CH1_PHY_CTRL_INDEX prior to writing this register
// 
// // Setting the GEN1 and GEN2 values above involves appropriate programming
// // of the T_SATA0_CH1_PHY_CTRL_INDEX field prior to setting this value.
// // This is best done by writing in the byte-mode(one byte at a time).
// // Please note that a 32-bit write will write to both INDEX and PEAK/AMP
// // at the same time, which is NOT RECCOMMENDED.
// //
// 
// .LABEL ANALOG_PUBLIC
// .LABEL ANALOG_PRIVATE INT_REL
// .TITLE SATA PHY Control Register(GEN2)
// .FIELD AMP
// This field contains the AMP values for gen1
// This register may have different values based on port usage (esata,gen1,gen)
// 
// .FIELD PEAK
// This field contains the PEAK values for gen1.
// 
//  31           24 23           16 15            8 7             0
// .-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-.
// |     |     | |  |   | |     | | | | ||     | | | | |   |   |   | CHX_PHY_CTRL1_GEN2
// +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
#define SATA0_CHX_PHY_CTRL1_GEN2_0                         0x00000694                                                                       // RWW4R
#define SATA0_CHX_PHY_CTRL1_GEN2_0_SECURE                  0
#define SATA0_CHX_PHY_CTRL1_GEN2_0_WORD_COUNT              1
#define SATA0_CHX_PHY_CTRL1_GEN2_0_RESET_VAL               0x0
#define SATA0_CHX_PHY_CTRL1_GEN2_0_RESET_MASK              0x0
#define SATA0_CHX_PHY_CTRL1_GEN2_0_SW_DEFAULT_VAL          0x0
#define SATA0_CHX_PHY_CTRL1_GEN2_0_SW_DEFAULT_MASK         0x0
#define SATA0_CHX_PHY_CTRL1_GEN2_0_READ_MASK               0x3fffffff
#define SATA0_CHX_PHY_CTRL1_GEN2_0_WRITE_MASK              0x3fffffff
#define SATA0_CHX_PHY_CTRL1_GEN2_0_TX_AMP_SHIFT             _MK_SHIFT_CONST(0)                                                              // RWCVF
#define SATA0_CHX_PHY_CTRL1_GEN2_0_TX_AMP_FIELD            (_MK_SHIFT_CONST(0xff) << SATA0_CHX_PHY_CTRL1_GEN2_0_TX_AMP_SHIFT)
#define SATA0_CHX_PHY_CTRL1_GEN2_0_TX_AMP_RANGE            7:0
#define SATA0_CHX_PHY_CTRL1_GEN2_0_TX_AMP_WOFFSET          0
#define SATA0_CHX_PHY_CTRL1_GEN2_0_TX_AMP__WRNPRDCHK       _MK_ENUM_CONST(0x00000001)                                                       // ----V
#define SATA0_CHX_PHY_CTRL1_GEN2_0_TX_AMP_DEFAULT2         _MK_ENUM_CONST(0x00000015)                                                       // RW--V
#define SATA0_CHX_PHY_CTRL1_GEN2_0_TX_AMP_DEFAULT3         _MK_ENUM_CONST(0x00000012)                                                       // RW--V
#define SATA0_CHX_PHY_CTRL1_GEN2_0_TX_AMP_DEFAULT4         _MK_ENUM_CONST(0x0000001B)                                                       // RW--V
#define SATA0_CHX_PHY_CTRL1_GEN2_0_TX_AMP_ESATA            _MK_ENUM_CONST(0x0000001A)                                                       // RW--V
#define SATA0_CHX_PHY_CTRL1_GEN2_0_TX_CMADJ_SHIFT           _MK_SHIFT_CONST(8)                                                              // RWCVF
#define SATA0_CHX_PHY_CTRL1_GEN2_0_TX_CMADJ_FIELD          (_MK_SHIFT_CONST(0xf) << SATA0_CHX_PHY_CTRL1_GEN2_0_TX_CMADJ_SHIFT)
#define SATA0_CHX_PHY_CTRL1_GEN2_0_TX_CMADJ_RANGE          11:8
#define SATA0_CHX_PHY_CTRL1_GEN2_0_TX_CMADJ_WOFFSET        0
#define SATA0_CHX_PHY_CTRL1_GEN2_0_TX_PEAK_SHIFT            _MK_SHIFT_CONST(12)                                                             // RWCVF
#define SATA0_CHX_PHY_CTRL1_GEN2_0_TX_PEAK_FIELD           (_MK_SHIFT_CONST(0xff) << SATA0_CHX_PHY_CTRL1_GEN2_0_TX_PEAK_SHIFT)
#define SATA0_CHX_PHY_CTRL1_GEN2_0_TX_PEAK_RANGE           19:12
#define SATA0_CHX_PHY_CTRL1_GEN2_0_TX_PEAK_WOFFSET         0
#define SATA0_CHX_PHY_CTRL1_GEN2_0_TX_PEAK__WRNPRDCHK      _MK_ENUM_CONST(0x00000001)                                                       // ----V
#define SATA0_CHX_PHY_CTRL1_GEN2_0_TX_PEAK_DEFAULT2        _MK_ENUM_CONST(0x0000000A)                                                       // RW--V
#define SATA0_CHX_PHY_CTRL1_GEN2_0_TX_PEAK_DEFAULT3        _MK_ENUM_CONST(0x0000000A)                                                       // RW--V
#define SATA0_CHX_PHY_CTRL1_GEN2_0_TX_PEAK_DEFAULT4        _MK_ENUM_CONST(0x0000000E)                                                       // RW--V
#define SATA0_CHX_PHY_CTRL1_GEN2_0_TX_PEAK_ESATA           _MK_ENUM_CONST(0x0000000E)                                                       // RW--V
#define SATA0_CHX_PHY_CTRL1_GEN2_0_TX_PEAK_PRE_SHIFT        _MK_SHIFT_CONST(20)                                                             // RWCVF
#define SATA0_CHX_PHY_CTRL1_GEN2_0_TX_PEAK_PRE_FIELD       (_MK_SHIFT_CONST(0x3f) << SATA0_CHX_PHY_CTRL1_GEN2_0_TX_PEAK_PRE_SHIFT)
#define SATA0_CHX_PHY_CTRL1_GEN2_0_TX_PEAK_PRE_RANGE       25:20
#define SATA0_CHX_PHY_CTRL1_GEN2_0_TX_PEAK_PRE_WOFFSET     0
#define SATA0_CHX_PHY_CTRL1_GEN2_0_TX_DRV_CNTL_SHIFT        _MK_SHIFT_CONST(26)                                                             // RWCVF
#define SATA0_CHX_PHY_CTRL1_GEN2_0_TX_DRV_CNTL_FIELD       (_MK_SHIFT_CONST(0xf) << SATA0_CHX_PHY_CTRL1_GEN2_0_TX_DRV_CNTL_SHIFT)
#define SATA0_CHX_PHY_CTRL1_GEN2_0_TX_DRV_CNTL_RANGE       29:26
#define SATA0_CHX_PHY_CTRL1_GEN2_0_TX_DRV_CNTL_WOFFSET     0
// .LABEL ANALOG_PUBLIC
// .LABEL ANALOG_PRIVATE INT_REL
// 
// .LABEL ANALOG_PRIVATE INT_REL
// 
// .LABEL ANALOG_PUBLIC
// .LABEL ANALOG_PRIVATE INT_REL
// 
// .LABEL ANALOG_PRIVATE INT_REL
// 
// 
// 
//         Figure 10-44  Serial ATA Channel 1 PHY Control register
// .LABEL PUBLIC
// 
// .LABEL ANALOG_PUBLIC
// .LABEL ANALOG_PRIVATE INT_REL
// .LABEL PRIVATE INT_REL
// .TITLE SATA PHY Control Register(GEN3)
// .FIELD AMP
// This field contains the AMP values for gen1
// This register may have different values based on port usage (esata,gen1,gen)
// 
// .FIELD PEAK
// This field contains the PEAK values for gen1.
// 
//  31           24 23           16 15            8 7             0
// .-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-.
// |     |     | |  |   | |     | | | | ||     | | | | |   |   |   | CHX_PHY_CTRL1_GEN3
// +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
#define SATA0_CHX_PHY_CTRL1_GEN3_0                         0x00000698                                                                       // RWW4R
#define SATA0_CHX_PHY_CTRL1_GEN3_0_SECURE                  0
#define SATA0_CHX_PHY_CTRL1_GEN3_0_WORD_COUNT              1
#define SATA0_CHX_PHY_CTRL1_GEN3_0_RESET_VAL               0x0
#define SATA0_CHX_PHY_CTRL1_GEN3_0_RESET_MASK              0x0
#define SATA0_CHX_PHY_CTRL1_GEN3_0_SW_DEFAULT_VAL          0x0
#define SATA0_CHX_PHY_CTRL1_GEN3_0_SW_DEFAULT_MASK         0x0
#define SATA0_CHX_PHY_CTRL1_GEN3_0_READ_MASK               0x3fffffff
#define SATA0_CHX_PHY_CTRL1_GEN3_0_WRITE_MASK              0x3fffffff
#define SATA0_CHX_PHY_CTRL1_GEN3_0_TX_AMP_SHIFT             _MK_SHIFT_CONST(0)                                                              // RWCVF
#define SATA0_CHX_PHY_CTRL1_GEN3_0_TX_AMP_FIELD            (_MK_SHIFT_CONST(0xff) << SATA0_CHX_PHY_CTRL1_GEN3_0_TX_AMP_SHIFT)
#define SATA0_CHX_PHY_CTRL1_GEN3_0_TX_AMP_RANGE            7:0
#define SATA0_CHX_PHY_CTRL1_GEN3_0_TX_AMP_WOFFSET          0
#define SATA0_CHX_PHY_CTRL1_GEN3_0_TX_AMP__WRNPRDCHK       _MK_ENUM_CONST(0x00000001)                                                       // ----V
#define SATA0_CHX_PHY_CTRL1_GEN3_0_TX_AMP_ESATA            _MK_ENUM_CONST(0x00000020)                                                       // RW--V
#define SATA0_CHX_PHY_CTRL1_GEN3_0_TX_CMADJ_SHIFT           _MK_SHIFT_CONST(8)                                                              // RWCVF
#define SATA0_CHX_PHY_CTRL1_GEN3_0_TX_CMADJ_FIELD          (_MK_SHIFT_CONST(0xf) << SATA0_CHX_PHY_CTRL1_GEN3_0_TX_CMADJ_SHIFT)
#define SATA0_CHX_PHY_CTRL1_GEN3_0_TX_CMADJ_RANGE          11:8
#define SATA0_CHX_PHY_CTRL1_GEN3_0_TX_CMADJ_WOFFSET        0
#define SATA0_CHX_PHY_CTRL1_GEN3_0_TX_PEAK_SHIFT            _MK_SHIFT_CONST(12)                                                             // RWCVF
#define SATA0_CHX_PHY_CTRL1_GEN3_0_TX_PEAK_FIELD           (_MK_SHIFT_CONST(0xff) << SATA0_CHX_PHY_CTRL1_GEN3_0_TX_PEAK_SHIFT)
#define SATA0_CHX_PHY_CTRL1_GEN3_0_TX_PEAK_RANGE           19:12
#define SATA0_CHX_PHY_CTRL1_GEN3_0_TX_PEAK_WOFFSET         0
#define SATA0_CHX_PHY_CTRL1_GEN3_0_TX_PEAK__WRNPRDCHK      _MK_ENUM_CONST(0x00000001)                                                       // ----V
#define SATA0_CHX_PHY_CTRL1_GEN3_0_TX_PEAK_ESATA           _MK_ENUM_CONST(0x00000014)                                                       // RW--V
#define SATA0_CHX_PHY_CTRL1_GEN3_0_TX_PEAK_PRE_SHIFT        _MK_SHIFT_CONST(20)                                                             // RWCVF
#define SATA0_CHX_PHY_CTRL1_GEN3_0_TX_PEAK_PRE_FIELD       (_MK_SHIFT_CONST(0x3f) << SATA0_CHX_PHY_CTRL1_GEN3_0_TX_PEAK_PRE_SHIFT)
#define SATA0_CHX_PHY_CTRL1_GEN3_0_TX_PEAK_PRE_RANGE       25:20
#define SATA0_CHX_PHY_CTRL1_GEN3_0_TX_PEAK_PRE_WOFFSET     0
#define SATA0_CHX_PHY_CTRL1_GEN3_0_TX_DRV_CNTL_SHIFT        _MK_SHIFT_CONST(26)                                                             // RWCVF
#define SATA0_CHX_PHY_CTRL1_GEN3_0_TX_DRV_CNTL_FIELD       (_MK_SHIFT_CONST(0xf) << SATA0_CHX_PHY_CTRL1_GEN3_0_TX_DRV_CNTL_SHIFT)
#define SATA0_CHX_PHY_CTRL1_GEN3_0_TX_DRV_CNTL_RANGE       29:26
#define SATA0_CHX_PHY_CTRL1_GEN3_0_TX_DRV_CNTL_WOFFSET     0
// .LABEL ANALOG_PUBLIC
// .LABEL ANALOG_PRIVATE INT_REL
// .LABEL PRIVATE INT_REL
// 
// .LABEL ANALOG_PRIVATE INT_REL
// .LABEL PRIVATE INT_REL
// 
// .LABEL ANALOG_PUBLIC
// .LABEL ANALOG_PRIVATE INT_REL
// .LABEL PRIVATE INT_REL
// 
// .LABEL ANALOG_PRIVATE INT_REL
// .LABEL PRIVATE INT_REL
// 
// 
//         Figure 10-44  Serial ATA Channel 1 PHY Control register
// .LABEL PUBLIC
// .LABEL ANALOG_PRIVATE INT_REL
// .TITLE SATA PHY Control Register
// This register contains various bits to control the phy
// 
//  31           24 23           16 15            8 7             0
// .-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-.
// |0 0 0 0 0 0 0 0| | |   | | | | |   |   |0 0|   |0|     |0|     | CHX_PHY_CTRL2
// +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
// 
#define SATA0_CHX_PHY_CTRL2_0                              0x0000069C                                                                       // RWW4R
#define SATA0_CHX_PHY_CTRL2_0_SECURE                       0
#define SATA0_CHX_PHY_CTRL2_0_WORD_COUNT                   1
#define SATA0_CHX_PHY_CTRL2_0_RESET_VAL                    0x0
#define SATA0_CHX_PHY_CTRL2_0_RESET_MASK                   0x0
#define SATA0_CHX_PHY_CTRL2_0_SW_DEFAULT_VAL               0x0
#define SATA0_CHX_PHY_CTRL2_0_SW_DEFAULT_MASK              0x0
#define SATA0_CHX_PHY_CTRL2_0_READ_MASK                    0xffffffff
#define SATA0_CHX_PHY_CTRL2_0_WRITE_MASK                   0xffffffff
#define SATA0_CHX_PHY_CTRL2_0_CDR_CNTL_GEN1_SHIFT           _MK_SHIFT_CONST(0)                                                              // RWCVF
#define SATA0_CHX_PHY_CTRL2_0_CDR_CNTL_GEN1_FIELD          (_MK_SHIFT_CONST(0xffff) << SATA0_CHX_PHY_CTRL2_0_CDR_CNTL_GEN1_SHIFT)
#define SATA0_CHX_PHY_CTRL2_0_CDR_CNTL_GEN1_RANGE          15:0
#define SATA0_CHX_PHY_CTRL2_0_CDR_CNTL_GEN1_WOFFSET        0
#define SATA0_CHX_PHY_CTRL2_0_CDR_CNTL_GEN2_SHIFT           _MK_SHIFT_CONST(16)                                                             // RWCVF
#define SATA0_CHX_PHY_CTRL2_0_CDR_CNTL_GEN2_FIELD          (_MK_SHIFT_CONST(0xffff) << SATA0_CHX_PHY_CTRL2_0_CDR_CNTL_GEN2_SHIFT)
#define SATA0_CHX_PHY_CTRL2_0_CDR_CNTL_GEN2_RANGE          31:16
#define SATA0_CHX_PHY_CTRL2_0_CDR_CNTL_GEN2_WOFFSET        0
// 
// 
// .LABEL PRIVATE INT_REL
// 
//         Figure 10-44  Serial ATA Channel 1 PHY Control register
// .LABEL PUBLIC
// .LABEL ANALOG_PRIVATE INT_REL
// .TITLE SATA PHY Control Register
// This register contains various bits to control the phy
// 
//  31           24 23           16 15            8 7             0
// .-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-.
// |0 0 0 0 0 0 0 0| | |   | | | | |   |   |0 0|   |0|     |0|     | CHX_PHY_CTRL24
// +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
// 
#define SATA0_CHX_PHY_CTRL24_0                             0x000006A0                                                                       // RWW4R
#define SATA0_CHX_PHY_CTRL24_0_SECURE                      0
#define SATA0_CHX_PHY_CTRL24_0_WORD_COUNT                  1
#define SATA0_CHX_PHY_CTRL24_0_RESET_VAL                   0x0
#define SATA0_CHX_PHY_CTRL24_0_RESET_MASK                  0x0
#define SATA0_CHX_PHY_CTRL24_0_SW_DEFAULT_VAL              0x0
#define SATA0_CHX_PHY_CTRL24_0_SW_DEFAULT_MASK             0x0
#define SATA0_CHX_PHY_CTRL24_0_READ_MASK                   0xffff
#define SATA0_CHX_PHY_CTRL24_0_WRITE_MASK                  0xffff
#define SATA0_CHX_PHY_CTRL24_0_CDR_CNTL_GEN3_SHIFT          _MK_SHIFT_CONST(0)                                                              // RWCVF
#define SATA0_CHX_PHY_CTRL24_0_CDR_CNTL_GEN3_FIELD         (_MK_SHIFT_CONST(0xffff) << SATA0_CHX_PHY_CTRL24_0_CDR_CNTL_GEN3_SHIFT)
#define SATA0_CHX_PHY_CTRL24_0_CDR_CNTL_GEN3_RANGE         15:0
#define SATA0_CHX_PHY_CTRL24_0_CDR_CNTL_GEN3_WOFFSET       0
// 
// 
// 
//         Figure 10-44  Serial ATA Channel 1 PHY Control register
// .LABEL PUBLIC
// .LABEL ANALOG_PRIVATE INT_REL
// .TITLE SATA PHY Control Register
// This register contains various bits to control the phy
// 
//  31           24 23           16 15            8 7             0
// .-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-.
// |0 0 0 0 0 0 0 0| | |   | | | | |   |   |0 0|   |0|     |0|     | CHX_PHY_CTRL25
// +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
// 
#define SATA0_CHX_PHY_CTRL25_0                             0x000006A4                                                                       // RWW4R
#define SATA0_CHX_PHY_CTRL25_0_SECURE                      0
#define SATA0_CHX_PHY_CTRL25_0_WORD_COUNT                  1
#define SATA0_CHX_PHY_CTRL25_0_RESET_VAL                   0x0
#define SATA0_CHX_PHY_CTRL25_0_RESET_MASK                  0x0
#define SATA0_CHX_PHY_CTRL25_0_SW_DEFAULT_VAL              0x0
#define SATA0_CHX_PHY_CTRL25_0_SW_DEFAULT_MASK             0x0
#define SATA0_CHX_PHY_CTRL25_0_READ_MASK                   0xffffffff
#define SATA0_CHX_PHY_CTRL25_0_WRITE_MASK                  0xffffffff
#define SATA0_CHX_PHY_CTRL25_0_DFE_CNTL_GEN2_SHIFT          _MK_SHIFT_CONST(0)                                                              // RWCVF
#define SATA0_CHX_PHY_CTRL25_0_DFE_CNTL_GEN2_FIELD         (_MK_SHIFT_CONST(0xffffffff) << SATA0_CHX_PHY_CTRL25_0_DFE_CNTL_GEN2_SHIFT)
#define SATA0_CHX_PHY_CTRL25_0_DFE_CNTL_GEN2_RANGE         31:0
#define SATA0_CHX_PHY_CTRL25_0_DFE_CNTL_GEN2_WOFFSET       0
// 
// 
// 
//         Figure 10-44  Serial ATA Channel 1 PHY Control register
// .LABEL PUBLIC
// .LABEL ANALOG_PRIVATE INT_REL
// .TITLE SATA PHY Control Register
// This register contains various bits to control the phy
// 
//  31           24 23           16 15            8 7             0
// .-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-.
// |0 0 0 0 0 0 0 0| | |   | | | | |   |   |0 0|   |0|     |0|     | CHX_PHY_CTRL26
// +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
// 
#define SATA0_CHX_PHY_CTRL26_0                             0x000006A8                                                                       // RWW4R
#define SATA0_CHX_PHY_CTRL26_0_SECURE                      0
#define SATA0_CHX_PHY_CTRL26_0_WORD_COUNT                  1
#define SATA0_CHX_PHY_CTRL26_0_RESET_VAL                   0x0
#define SATA0_CHX_PHY_CTRL26_0_RESET_MASK                  0x0
#define SATA0_CHX_PHY_CTRL26_0_SW_DEFAULT_VAL              0x0
#define SATA0_CHX_PHY_CTRL26_0_SW_DEFAULT_MASK             0x0
#define SATA0_CHX_PHY_CTRL26_0_READ_MASK                   0xffffffff
#define SATA0_CHX_PHY_CTRL26_0_WRITE_MASK                  0xffffffff
#define SATA0_CHX_PHY_CTRL26_0_DFE_CNTL_GEN3_SHIFT          _MK_SHIFT_CONST(0)                                                              // RWCVF
#define SATA0_CHX_PHY_CTRL26_0_DFE_CNTL_GEN3_FIELD         (_MK_SHIFT_CONST(0xffffffff) << SATA0_CHX_PHY_CTRL26_0_DFE_CNTL_GEN3_SHIFT)
#define SATA0_CHX_PHY_CTRL26_0_DFE_CNTL_GEN3_RANGE         31:0
#define SATA0_CHX_PHY_CTRL26_0_DFE_CNTL_GEN3_WOFFSET       0
// 
// 
// 
// 
//         Figure 10-44  Serial ATA Channel 1 Misc register
// .LABEL PUBLIC
// .LABEL ANALOG_PRIVATE INT_REL
// .TITLE SATA PHY Control Register
// This register contains various bits to control the phy
// 
// .FIELD PHY_CTRL3_RX_SLEEP
// Select a sleep mode on the SATA port, used for debug of the sleep modes.
// 
// 00 = Active
// 01 = Partial Slumber
// 10 = Slumber
// 11 = Disabled
// 
// .FIELD PHY_CTRL3_RX_SLEEP_OVERRIDE
// Enable a forced sleep mode on the SATA port, used for debug of the sleep modes.
// _NO = Normal Operation
// _YES = Forced sleep mode
// Note: The associated SLEEP_MODE register bits select the sleep mode forced.
// 
// .FIELD PHY_CTRL3_TX_SLEEP
// Select a sleep mode on the SATA port, used for debug of the sleep modes.
// 
// 00 = Active
// 01 = Partial Slumber
// 10 = Slumber
// 11 = Disabled
// 
// .FIELD PHY_CTRL3_TX_SLEEP_OVERRIDE
// Enable a forced sleep mode on the SATA port, used for debug of the sleep modes.
// _NO = Normal Operation
// _YES = Forced sleep mode
// Note: The associated SLEEP_MODE register bits select the sleep mode forced.
// 
// .FIELD TX_DATA_EN
// TXDATA_EN and TXDATA_EN_OVERRIDE are used to enable/disable txd_en manually.
// 
// PHY_CTRL3_TXD_EN and PHY_CTRL3_TXD_EN_OVERRIDE are used to enable/disable txd_en manually.
// 
// 
//  31           24 23           16 15            8 7             0
// .-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-.
// |0 0 0 0 0 0 0 0| | |   | | | | |   |   |0 0|   |0|     |0|     | CHX_PHY_CTRL3
// +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
// 
#define SATA0_CHX_PHY_CTRL3_0                              0x000006B0                                                                       // RWC4R
#define SATA0_CHX_PHY_CTRL3_0_SECURE                       0
#define SATA0_CHX_PHY_CTRL3_0_WORD_COUNT                   1
#define SATA0_CHX_PHY_CTRL3_0_RESET_VAL                    0x0
#define SATA0_CHX_PHY_CTRL3_0_RESET_MASK                   0x0
#define SATA0_CHX_PHY_CTRL3_0_SW_DEFAULT_VAL               0x0
#define SATA0_CHX_PHY_CTRL3_0_SW_DEFAULT_MASK              0x0
#define SATA0_CHX_PHY_CTRL3_0_READ_MASK                    0x3fbbffbd
#define SATA0_CHX_PHY_CTRL3_0_WRITE_MASK                   0xbbffbd
#define SATA0_CHX_PHY_CTRL3_0_IDDQ_SHIFT                    _MK_SHIFT_CONST(0)                                                              // RWCVF
#define SATA0_CHX_PHY_CTRL3_0_IDDQ_FIELD                   (_MK_SHIFT_CONST(0x1) << SATA0_CHX_PHY_CTRL3_0_IDDQ_SHIFT)
#define SATA0_CHX_PHY_CTRL3_0_IDDQ_RANGE                   0:0
#define SATA0_CHX_PHY_CTRL3_0_IDDQ_WOFFSET                 0
#define SATA0_CHX_PHY_CTRL3_0_IDDQ_INIT                    _MK_ENUM_CONST(0x00000000)                                                       // RWC-V
#define SATA0_CHX_PHY_CTRL3_0_CKBUFPD_SHIFT                 _MK_SHIFT_CONST(2)                                                              // RWCVF
#define SATA0_CHX_PHY_CTRL3_0_CKBUFPD_FIELD                (_MK_SHIFT_CONST(0x1) << SATA0_CHX_PHY_CTRL3_0_CKBUFPD_SHIFT)
#define SATA0_CHX_PHY_CTRL3_0_CKBUFPD_RANGE                2:2
#define SATA0_CHX_PHY_CTRL3_0_CKBUFPD_WOFFSET              0
#define SATA0_CHX_PHY_CTRL3_0_CKBUFPD_OVRD_SHIFT            _MK_SHIFT_CONST(3)                                                              // RWCVF
#define SATA0_CHX_PHY_CTRL3_0_CKBUFPD_OVRD_FIELD           (_MK_SHIFT_CONST(0x1) << SATA0_CHX_PHY_CTRL3_0_CKBUFPD_OVRD_SHIFT)
#define SATA0_CHX_PHY_CTRL3_0_CKBUFPD_OVRD_RANGE           3:3
#define SATA0_CHX_PHY_CTRL3_0_CKBUFPD_OVRD_WOFFSET         0
#define SATA0_CHX_PHY_CTRL3_0_TX_SLEEP_SHIFT                _MK_SHIFT_CONST(4)                                                              // RWCVF
#define SATA0_CHX_PHY_CTRL3_0_TX_SLEEP_FIELD               (_MK_SHIFT_CONST(0x3) << SATA0_CHX_PHY_CTRL3_0_TX_SLEEP_SHIFT)
#define SATA0_CHX_PHY_CTRL3_0_TX_SLEEP_RANGE               5:4
#define SATA0_CHX_PHY_CTRL3_0_TX_SLEEP_WOFFSET             0
#define SATA0_CHX_PHY_CTRL3_0_TX_SLEEP__WRNPRDCHK          _MK_ENUM_CONST(0x00000001)                                                       // ----V
#define SATA0_CHX_PHY_CTRL3_0_TX_SLEEP_INIT                _MK_ENUM_CONST(0x00000002)                                                       // RWC-V
#define SATA0_CHX_PHY_CTRL3_0_TX_SLEEP_ACTIVE              _MK_ENUM_CONST(0x00000000)                                                       // RW--V
#define SATA0_CHX_PHY_CTRL3_0_TX_SLEEP_PARTIAL             _MK_ENUM_CONST(0x00000001)                                                       // RW--V
#define SATA0_CHX_PHY_CTRL3_0_TX_SLEEP_SLUMBER             _MK_ENUM_CONST(0x00000002)                                                       // RW--V
#define SATA0_CHX_PHY_CTRL3_0_TX_SLEEP_DISABLED            _MK_ENUM_CONST(0x00000003)                                                       // RW--V
#define SATA0_CHX_PHY_CTRL3_0_TX_SLEEP_OVERRIDE_SHIFT       _MK_SHIFT_CONST(7)                                                              // RWCVF
#define SATA0_CHX_PHY_CTRL3_0_TX_SLEEP_OVERRIDE_FIELD      (_MK_SHIFT_CONST(0x1) << SATA0_CHX_PHY_CTRL3_0_TX_SLEEP_OVERRIDE_SHIFT)
#define SATA0_CHX_PHY_CTRL3_0_TX_SLEEP_OVERRIDE_RANGE      7:7
#define SATA0_CHX_PHY_CTRL3_0_TX_SLEEP_OVERRIDE_WOFFSET    0
#define SATA0_CHX_PHY_CTRL3_0_TX_SLEEP_OVERRIDE_YES        _MK_ENUM_CONST(0x00000001)                                                       // RW--V
#define SATA0_CHX_PHY_CTRL3_0_TX_SLEEP_OVERRIDE_NO         _MK_ENUM_CONST(0x00000000)                                                       // RWC-V
#define SATA0_CHX_PHY_CTRL3_0_RX_SLEEP_SHIFT                _MK_SHIFT_CONST(8)                                                              // RWCVF
#define SATA0_CHX_PHY_CTRL3_0_RX_SLEEP_FIELD               (_MK_SHIFT_CONST(0x3) << SATA0_CHX_PHY_CTRL3_0_RX_SLEEP_SHIFT)
#define SATA0_CHX_PHY_CTRL3_0_RX_SLEEP_RANGE               9:8
#define SATA0_CHX_PHY_CTRL3_0_RX_SLEEP_WOFFSET             0
#define SATA0_CHX_PHY_CTRL3_0_RX_SLEEP__WRNPRDCHK          _MK_ENUM_CONST(0x00000001)                                                       // ----V
#define SATA0_CHX_PHY_CTRL3_0_RX_SLEEP_INIT                _MK_ENUM_CONST(0x00000002)                                                       // RWC-V
#define SATA0_CHX_PHY_CTRL3_0_RX_SLEEP_ACTIVE              _MK_ENUM_CONST(0x00000000)                                                       // RW--V
#define SATA0_CHX_PHY_CTRL3_0_RX_SLEEP_PARTIAL             _MK_ENUM_CONST(0x00000001)                                                       // RW--V
#define SATA0_CHX_PHY_CTRL3_0_RX_SLEEP_SLUMBER             _MK_ENUM_CONST(0x00000002)                                                       // RW--V
#define SATA0_CHX_PHY_CTRL3_0_RX_SLEEP_DISABLED            _MK_ENUM_CONST(0x00000003)                                                       // RW--V
#define SATA0_CHX_PHY_CTRL3_0_TX_DATA_READY_SHIFT           _MK_SHIFT_CONST(10)                                                             // RWCVF
#define SATA0_CHX_PHY_CTRL3_0_TX_DATA_READY_FIELD          (_MK_SHIFT_CONST(0x1) << SATA0_CHX_PHY_CTRL3_0_TX_DATA_READY_SHIFT)
#define SATA0_CHX_PHY_CTRL3_0_TX_DATA_READY_RANGE          10:10
#define SATA0_CHX_PHY_CTRL3_0_TX_DATA_READY_WOFFSET        0
#define SATA0_CHX_PHY_CTRL3_0_TX_DATA_READY_YES            _MK_ENUM_CONST(0x00000001)                                                       // RW--V
#define SATA0_CHX_PHY_CTRL3_0_TX_DATA_READY_NO             _MK_ENUM_CONST(0x00000000)                                                       // RWC-V
#define SATA0_CHX_PHY_CTRL3_0_RX_SLEEP_OVERRIDE_SHIFT       _MK_SHIFT_CONST(11)                                                             // RWCVF
#define SATA0_CHX_PHY_CTRL3_0_RX_SLEEP_OVERRIDE_FIELD      (_MK_SHIFT_CONST(0x1) << SATA0_CHX_PHY_CTRL3_0_RX_SLEEP_OVERRIDE_SHIFT)
#define SATA0_CHX_PHY_CTRL3_0_RX_SLEEP_OVERRIDE_RANGE      11:11
#define SATA0_CHX_PHY_CTRL3_0_RX_SLEEP_OVERRIDE_WOFFSET    0
#define SATA0_CHX_PHY_CTRL3_0_RX_SLEEP_OVERRIDE_YES        _MK_ENUM_CONST(0x00000001)                                                       // RW--V
#define SATA0_CHX_PHY_CTRL3_0_RX_SLEEP_OVERRIDE_NO         _MK_ENUM_CONST(0x00000000)                                                       // RWC-V
#define SATA0_CHX_PHY_CTRL3_0_TX_DATA_EN_SHIFT              _MK_SHIFT_CONST(12)                                                             // RWCVF
#define SATA0_CHX_PHY_CTRL3_0_TX_DATA_EN_FIELD             (_MK_SHIFT_CONST(0x1) << SATA0_CHX_PHY_CTRL3_0_TX_DATA_EN_SHIFT)
#define SATA0_CHX_PHY_CTRL3_0_TX_DATA_EN_RANGE             12:12
#define SATA0_CHX_PHY_CTRL3_0_TX_DATA_EN_WOFFSET           0
#define SATA0_CHX_PHY_CTRL3_0_TX_DATA_EN_YES               _MK_ENUM_CONST(0x00000001)                                                       // RW--V
#define SATA0_CHX_PHY_CTRL3_0_TX_DATA_EN_NO                _MK_ENUM_CONST(0x00000000)                                                       // RWC-V
#define SATA0_CHX_PHY_CTRL3_0_TX_DATA_EN_OVERRIDE_SHIFT     _MK_SHIFT_CONST(13)                                                             // RWCVF
#define SATA0_CHX_PHY_CTRL3_0_TX_DATA_EN_OVERRIDE_FIELD    (_MK_SHIFT_CONST(0x1) << SATA0_CHX_PHY_CTRL3_0_TX_DATA_EN_OVERRIDE_SHIFT)
#define SATA0_CHX_PHY_CTRL3_0_TX_DATA_EN_OVERRIDE_RANGE    13:13
#define SATA0_CHX_PHY_CTRL3_0_TX_DATA_EN_OVERRIDE_WOFFSET  0
#define SATA0_CHX_PHY_CTRL3_0_TX_DATA_EN_OVERRIDE_YES      _MK_ENUM_CONST(0x00000001)                                                       // RW--V
#define SATA0_CHX_PHY_CTRL3_0_TX_DATA_EN_OVERRIDE_NO       _MK_ENUM_CONST(0x00000000)                                                       // RWC-V
#define SATA0_CHX_PHY_CTRL3_0_RX_DATA_EN_SHIFT              _MK_SHIFT_CONST(14)                                                             // RWCVF
#define SATA0_CHX_PHY_CTRL3_0_RX_DATA_EN_FIELD             (_MK_SHIFT_CONST(0x1) << SATA0_CHX_PHY_CTRL3_0_RX_DATA_EN_SHIFT)
#define SATA0_CHX_PHY_CTRL3_0_RX_DATA_EN_RANGE             14:14
#define SATA0_CHX_PHY_CTRL3_0_RX_DATA_EN_WOFFSET           0
#define SATA0_CHX_PHY_CTRL3_0_RX_DATA_EN__WRNPRDCHK        _MK_ENUM_CONST(0x00000001)                                                       // ----V
#define SATA0_CHX_PHY_CTRL3_0_RX_DATA_READY_SHIFT           _MK_SHIFT_CONST(15)                                                             // RWCVF
#define SATA0_CHX_PHY_CTRL3_0_RX_DATA_READY_FIELD          (_MK_SHIFT_CONST(0x1) << SATA0_CHX_PHY_CTRL3_0_RX_DATA_READY_SHIFT)
#define SATA0_CHX_PHY_CTRL3_0_RX_DATA_READY_RANGE          15:15
#define SATA0_CHX_PHY_CTRL3_0_RX_DATA_READY_WOFFSET        0
#define SATA0_CHX_PHY_CTRL3_0_RX_DATA_READY_YES            _MK_ENUM_CONST(0x00000001)                                                       // RW--V
#define SATA0_CHX_PHY_CTRL3_0_RX_DATA_READY_NO             _MK_ENUM_CONST(0x00000000)                                                       // RWC-V
#define SATA0_CHX_PHY_CTRL3_0_TX_RATE_SHIFT                 _MK_SHIFT_CONST(16)                                                             // RWCVF
#define SATA0_CHX_PHY_CTRL3_0_TX_RATE_FIELD                (_MK_SHIFT_CONST(0x3) << SATA0_CHX_PHY_CTRL3_0_TX_RATE_SHIFT)
#define SATA0_CHX_PHY_CTRL3_0_TX_RATE_RANGE                17:16
#define SATA0_CHX_PHY_CTRL3_0_TX_RATE_WOFFSET              0
#define SATA0_CHX_PHY_CTRL3_0_TX_RATE_GEN1                 _MK_ENUM_CONST(0x00000000)                                                       // RWC-V
#define SATA0_CHX_PHY_CTRL3_0_TX_RATE_GEN2                 _MK_ENUM_CONST(0x00000001)                                                       // RW--V
#define SATA0_CHX_PHY_CTRL3_0_TX_RATE_GEN3                 _MK_ENUM_CONST(0x00000002)                                                       // RW--V
#define SATA0_CHX_PHY_CTRL3_0_TX_RATE_OVERRIDE_SHIFT        _MK_SHIFT_CONST(19)                                                             // RWCVF
#define SATA0_CHX_PHY_CTRL3_0_TX_RATE_OVERRIDE_FIELD       (_MK_SHIFT_CONST(0x1) << SATA0_CHX_PHY_CTRL3_0_TX_RATE_OVERRIDE_SHIFT)
#define SATA0_CHX_PHY_CTRL3_0_TX_RATE_OVERRIDE_RANGE       19:19
#define SATA0_CHX_PHY_CTRL3_0_TX_RATE_OVERRIDE_WOFFSET     0
#define SATA0_CHX_PHY_CTRL3_0_TX_RATE_OVERRIDE_DISABLE     _MK_ENUM_CONST(0x00000000)                                                       // RWC-V
#define SATA0_CHX_PHY_CTRL3_0_TX_RATE_OVERRIDE_ENABLE      _MK_ENUM_CONST(0x00000001)                                                       // RW--V
#define SATA0_CHX_PHY_CTRL3_0_RX_RATE_SHIFT                 _MK_SHIFT_CONST(20)                                                             // RWCVF
#define SATA0_CHX_PHY_CTRL3_0_RX_RATE_FIELD                (_MK_SHIFT_CONST(0x3) << SATA0_CHX_PHY_CTRL3_0_RX_RATE_SHIFT)
#define SATA0_CHX_PHY_CTRL3_0_RX_RATE_RANGE                21:20
#define SATA0_CHX_PHY_CTRL3_0_RX_RATE_WOFFSET              0
#define SATA0_CHX_PHY_CTRL3_0_RX_RATE_GEN1                 _MK_ENUM_CONST(0x00000000)                                                       // RWC-V
#define SATA0_CHX_PHY_CTRL3_0_RX_RATE_GEN2                 _MK_ENUM_CONST(0x00000001)                                                       // RW--V
#define SATA0_CHX_PHY_CTRL3_0_RX_RATE_GEN3                 _MK_ENUM_CONST(0x00000002)                                                       // RW--V
#define SATA0_CHX_PHY_CTRL3_0_RX_RATE_OVERRIDE_SHIFT        _MK_SHIFT_CONST(23)                                                             // RWCVF
#define SATA0_CHX_PHY_CTRL3_0_RX_RATE_OVERRIDE_FIELD       (_MK_SHIFT_CONST(0x1) << SATA0_CHX_PHY_CTRL3_0_RX_RATE_OVERRIDE_SHIFT)
#define SATA0_CHX_PHY_CTRL3_0_RX_RATE_OVERRIDE_RANGE       23:23
#define SATA0_CHX_PHY_CTRL3_0_RX_RATE_OVERRIDE_WOFFSET     0
#define SATA0_CHX_PHY_CTRL3_0_RX_RATE_OVERRIDE_DISABLE     _MK_ENUM_CONST(0x00000000)                                                       // RWC-V
#define SATA0_CHX_PHY_CTRL3_0_RX_RATE_OVERRIDE_ENABLE      _MK_ENUM_CONST(0x00000001)                                                       // RW--V
#define SATA0_CHX_PHY_CTRL3_0_STATUS_TX_RATE_SHIFT          _MK_SHIFT_CONST(24)                                                             // R-CVF
#define SATA0_CHX_PHY_CTRL3_0_STATUS_TX_RATE_FIELD         (_MK_SHIFT_CONST(0x3) << SATA0_CHX_PHY_CTRL3_0_STATUS_TX_RATE_SHIFT)
#define SATA0_CHX_PHY_CTRL3_0_STATUS_TX_RATE_RANGE         25:24
#define SATA0_CHX_PHY_CTRL3_0_STATUS_TX_RATE_WOFFSET       0
#define SATA0_CHX_PHY_CTRL3_0_STATUS_TX_RATE_GEN1          _MK_ENUM_CONST(0x00000000)                                                       // R---V
#define SATA0_CHX_PHY_CTRL3_0_STATUS_TX_RATE_GEN2          _MK_ENUM_CONST(0x00000001)                                                       // R---V
#define SATA0_CHX_PHY_CTRL3_0_STATUS_TX_RATE_GEN3          _MK_ENUM_CONST(0x00000002)                                                       // R---V
#define SATA0_CHX_PHY_CTRL3_0_STATUS_RX_RATE_SHIFT          _MK_SHIFT_CONST(26)                                                             // R-CVF
#define SATA0_CHX_PHY_CTRL3_0_STATUS_RX_RATE_FIELD         (_MK_SHIFT_CONST(0x3) << SATA0_CHX_PHY_CTRL3_0_STATUS_RX_RATE_SHIFT)
#define SATA0_CHX_PHY_CTRL3_0_STATUS_RX_RATE_RANGE         27:26
#define SATA0_CHX_PHY_CTRL3_0_STATUS_RX_RATE_WOFFSET       0
#define SATA0_CHX_PHY_CTRL3_0_STATUS_RX_RATE_GEN1          _MK_ENUM_CONST(0x00000000)                                                       // R---V
#define SATA0_CHX_PHY_CTRL3_0_STATUS_RX_RATE_GEN2          _MK_ENUM_CONST(0x00000001)                                                       // R---V
#define SATA0_CHX_PHY_CTRL3_0_STATUS_RX_RATE_GEN3          _MK_ENUM_CONST(0x00000002)                                                       // R---V
#define SATA0_CHX_PHY_CTRL3_0_STATUS_TX_STAT_PRESENT_SHIFT  _MK_SHIFT_CONST(28)                                                             // R-CVF
#define SATA0_CHX_PHY_CTRL3_0_STATUS_TX_STAT_PRESENT_FIELD (_MK_SHIFT_CONST(0x1) << SATA0_CHX_PHY_CTRL3_0_STATUS_TX_STAT_PRESENT_SHIFT)
#define SATA0_CHX_PHY_CTRL3_0_STATUS_TX_STAT_PRESENT_RANGE 28:28
#define SATA0_CHX_PHY_CTRL3_0_STATUS_TX_STAT_PRESENT_WOFFSET 0
#define SATA0_CHX_PHY_CTRL3_0_STATUS_RX_STAT_IDLE_SHIFT     _MK_SHIFT_CONST(29)                                                             // R-CVF
#define SATA0_CHX_PHY_CTRL3_0_STATUS_RX_STAT_IDLE_FIELD    (_MK_SHIFT_CONST(0x1) << SATA0_CHX_PHY_CTRL3_0_STATUS_RX_STAT_IDLE_SHIFT)
#define SATA0_CHX_PHY_CTRL3_0_STATUS_RX_STAT_IDLE_RANGE    29:29
#define SATA0_CHX_PHY_CTRL3_0_STATUS_RX_STAT_IDLE_WOFFSET  0
// 
// 
// 
// 
// 
// 
// 
// 
// 
// 
// 
// 
// 
// .LABEL PRIVATE INT_REL
// .LABEL ANALOG_PRIVATE INT_REL
// 
// 
// .LABEL PRIVATE INT_REL
// .LABEL ANALOG_PRIVATE INT_REL
// 
// 
// .LABEL PRIVATE INT_REL
// .LABEL ANALOG_PRIVATE INT_REL
// 
// .LABEL PRIVATE INT_REL
// .LABEL ANALOG_PRIVATE INT_REL
// 
// 
// 
//         Figure 10-44  Serial ATA Channel 1 Misc register
// .LABEL PUBLIC
// .LABEL ANALOG_PRIVATE INT_REL
// .TITLE SATA PHY Control Register
// This register contains various bits to control the phy
// 
//  31           24 23           16 15            8 7             0
// .-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-.
// |0 0 0 0 0 0 0 0| | |   | | | | |   |   |0 0|   |0|     |0|     | CHX_PHY_CTRL4
// +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
// 
#define SATA0_CHX_PHY_CTRL4_0                              0x000006B4                                                                       // RWC4R
#define SATA0_CHX_PHY_CTRL4_0_SECURE                       0
#define SATA0_CHX_PHY_CTRL4_0_WORD_COUNT                   1
#define SATA0_CHX_PHY_CTRL4_0_RESET_VAL                    0x0
#define SATA0_CHX_PHY_CTRL4_0_RESET_MASK                   0x0
#define SATA0_CHX_PHY_CTRL4_0_SW_DEFAULT_VAL               0x0
#define SATA0_CHX_PHY_CTRL4_0_SW_DEFAULT_MASK              0x0
#define SATA0_CHX_PHY_CTRL4_0_READ_MASK                    0xfd333fff
#define SATA0_CHX_PHY_CTRL4_0_WRITE_MASK                   0x3d333fff
#define SATA0_CHX_PHY_CTRL4_0_NED_MODE_SHIFT                _MK_SHIFT_CONST(0)                                                              // RWCVF
#define SATA0_CHX_PHY_CTRL4_0_NED_MODE_FIELD               (_MK_SHIFT_CONST(0x3) << SATA0_CHX_PHY_CTRL4_0_NED_MODE_SHIFT)
#define SATA0_CHX_PHY_CTRL4_0_NED_MODE_RANGE               1:0
#define SATA0_CHX_PHY_CTRL4_0_NED_MODE_WOFFSET             0
#define SATA0_CHX_PHY_CTRL4_0_NED_LOOP_SHIFT                _MK_SHIFT_CONST(2)                                                              // RWCVF
#define SATA0_CHX_PHY_CTRL4_0_NED_LOOP_FIELD               (_MK_SHIFT_CONST(0x1) << SATA0_CHX_PHY_CTRL4_0_NED_LOOP_SHIFT)
#define SATA0_CHX_PHY_CTRL4_0_NED_LOOP_RANGE               2:2
#define SATA0_CHX_PHY_CTRL4_0_NED_LOOP_WOFFSET             0
#define SATA0_CHX_PHY_CTRL4_0_NEA_LOOP_SHIFT                _MK_SHIFT_CONST(3)                                                              // RWCVF
#define SATA0_CHX_PHY_CTRL4_0_NEA_LOOP_FIELD               (_MK_SHIFT_CONST(0x1) << SATA0_CHX_PHY_CTRL4_0_NEA_LOOP_SHIFT)
#define SATA0_CHX_PHY_CTRL4_0_NEA_LOOP_RANGE               3:3
#define SATA0_CHX_PHY_CTRL4_0_NEA_LOOP_WOFFSET             0
#define SATA0_CHX_PHY_CTRL4_0_FEA_MODE_SHIFT                _MK_SHIFT_CONST(4)                                                              // RWCVF
#define SATA0_CHX_PHY_CTRL4_0_FEA_MODE_FIELD               (_MK_SHIFT_CONST(0x7) << SATA0_CHX_PHY_CTRL4_0_FEA_MODE_SHIFT)
#define SATA0_CHX_PHY_CTRL4_0_FEA_MODE_RANGE               6:4
#define SATA0_CHX_PHY_CTRL4_0_FEA_MODE_WOFFSET             0
#define SATA0_CHX_PHY_CTRL4_0_FEA_LOOP_SHIFT                _MK_SHIFT_CONST(7)                                                              // RWCVF
#define SATA0_CHX_PHY_CTRL4_0_FEA_LOOP_FIELD               (_MK_SHIFT_CONST(0x1) << SATA0_CHX_PHY_CTRL4_0_FEA_LOOP_SHIFT)
#define SATA0_CHX_PHY_CTRL4_0_FEA_LOOP_RANGE               7:7
#define SATA0_CHX_PHY_CTRL4_0_FEA_LOOP_WOFFSET             0
#define SATA0_CHX_PHY_CTRL4_0_TX_DATA_MODE_SHIFT            _MK_SHIFT_CONST(8)                                                              // RWCVF
#define SATA0_CHX_PHY_CTRL4_0_TX_DATA_MODE_FIELD           (_MK_SHIFT_CONST(0x7) << SATA0_CHX_PHY_CTRL4_0_TX_DATA_MODE_SHIFT)
#define SATA0_CHX_PHY_CTRL4_0_TX_DATA_MODE_RANGE           10:8
#define SATA0_CHX_PHY_CTRL4_0_TX_DATA_MODE_WOFFSET         0
#define SATA0_CHX_PHY_CTRL4_0_TX_DATA_MODE_NORMAL          _MK_ENUM_CONST(0x00000000)                                                       // RWC-V
#define SATA0_CHX_PHY_CTRL4_0_TX_DATA_MODE_PRBS_2_7        _MK_ENUM_CONST(0x00000001)                                                       // RW--V
#define SATA0_CHX_PHY_CTRL4_0_TX_DATA_MODE_0101010101      _MK_ENUM_CONST(0x00000002)                                                       // RW--V
#define SATA0_CHX_PHY_CTRL4_0_TX_DATA_MODE_1100110011      _MK_ENUM_CONST(0x00000003)                                                       // RW--V
#define SATA0_CHX_PHY_CTRL4_0_TX_DATA_MODE_0000011111      _MK_ENUM_CONST(0x00000004)                                                       // RW--V
#define SATA0_CHX_PHY_CTRL4_0_TX_DATA_MODE_0101111100      _MK_ENUM_CONST(0x00000005)                                                       // RW--V
#define SATA0_CHX_PHY_CTRL4_0_FED_LOOP_SHIFT                _MK_SHIFT_CONST(11)                                                             // RWCVF
#define SATA0_CHX_PHY_CTRL4_0_FED_LOOP_FIELD               (_MK_SHIFT_CONST(0x1) << SATA0_CHX_PHY_CTRL4_0_FED_LOOP_SHIFT)
#define SATA0_CHX_PHY_CTRL4_0_FED_LOOP_RANGE               11:11
#define SATA0_CHX_PHY_CTRL4_0_FED_LOOP_WOFFSET             0
#define SATA0_CHX_PHY_CTRL4_0_TX_SYNC_SHIFT                 _MK_SHIFT_CONST(12)                                                             // RWCVF
#define SATA0_CHX_PHY_CTRL4_0_TX_SYNC_FIELD                (_MK_SHIFT_CONST(0x1) << SATA0_CHX_PHY_CTRL4_0_TX_SYNC_SHIFT)
#define SATA0_CHX_PHY_CTRL4_0_TX_SYNC_RANGE                12:12
#define SATA0_CHX_PHY_CTRL4_0_TX_SYNC_WOFFSET              0
#define SATA0_CHX_PHY_CTRL4_0_TX_SYNC_IDLE                 _MK_ENUM_CONST(0x00000000)                                                       // RWC-V
#define SATA0_CHX_PHY_CTRL4_0_TX_SYNC_NOW                  _MK_ENUM_CONST(0x00000001)                                                       // RW--V
#define SATA0_CHX_PHY_CTRL4_0_RX_CDR_RESET_SHIFT            _MK_SHIFT_CONST(13)                                                             // RWCVF
#define SATA0_CHX_PHY_CTRL4_0_RX_CDR_RESET_FIELD           (_MK_SHIFT_CONST(0x1) << SATA0_CHX_PHY_CTRL4_0_RX_CDR_RESET_SHIFT)
#define SATA0_CHX_PHY_CTRL4_0_RX_CDR_RESET_RANGE           13:13
#define SATA0_CHX_PHY_CTRL4_0_RX_CDR_RESET_WOFFSET         0
#define SATA0_CHX_PHY_CTRL4_0_TX_DIV_SHIFT                  _MK_SHIFT_CONST(16)                                                             // RWCVF
#define SATA0_CHX_PHY_CTRL4_0_TX_DIV_FIELD                 (_MK_SHIFT_CONST(0x3) << SATA0_CHX_PHY_CTRL4_0_TX_DIV_SHIFT)
#define SATA0_CHX_PHY_CTRL4_0_TX_DIV_RANGE                 17:16
#define SATA0_CHX_PHY_CTRL4_0_TX_DIV_WOFFSET               0
#define SATA0_CHX_PHY_CTRL4_0_RX_DIV_SHIFT                  _MK_SHIFT_CONST(20)                                                             // RWCVF
#define SATA0_CHX_PHY_CTRL4_0_RX_DIV_FIELD                 (_MK_SHIFT_CONST(0x3) << SATA0_CHX_PHY_CTRL4_0_RX_DIV_SHIFT)
#define SATA0_CHX_PHY_CTRL4_0_RX_DIV_RANGE                 21:20
#define SATA0_CHX_PHY_CTRL4_0_RX_DIV_WOFFSET               0
#define SATA0_CHX_PHY_CTRL4_0_RATE_MODE_SHIFT               _MK_SHIFT_CONST(24)                                                             // RWCVF
#define SATA0_CHX_PHY_CTRL4_0_RATE_MODE_FIELD              (_MK_SHIFT_CONST(0x1) << SATA0_CHX_PHY_CTRL4_0_RATE_MODE_SHIFT)
#define SATA0_CHX_PHY_CTRL4_0_RATE_MODE_RANGE              24:24
#define SATA0_CHX_PHY_CTRL4_0_RATE_MODE_WOFFSET            0
#define SATA0_CHX_PHY_CTRL4_0_TEST_EN_SHIFT                 _MK_SHIFT_CONST(26)                                                             // RWCVF
#define SATA0_CHX_PHY_CTRL4_0_TEST_EN_FIELD                (_MK_SHIFT_CONST(0x1) << SATA0_CHX_PHY_CTRL4_0_TEST_EN_SHIFT)
#define SATA0_CHX_PHY_CTRL4_0_TEST_EN_RANGE                26:26
#define SATA0_CHX_PHY_CTRL4_0_TEST_EN_WOFFSET              0
#define SATA0_CHX_PHY_CTRL4_0_PRBS_CHK_EN_SHIFT             _MK_SHIFT_CONST(27)                                                             // RWCVF
#define SATA0_CHX_PHY_CTRL4_0_PRBS_CHK_EN_FIELD            (_MK_SHIFT_CONST(0x1) << SATA0_CHX_PHY_CTRL4_0_PRBS_CHK_EN_SHIFT)
#define SATA0_CHX_PHY_CTRL4_0_PRBS_CHK_EN_RANGE            27:27
#define SATA0_CHX_PHY_CTRL4_0_PRBS_CHK_EN_WOFFSET          0
#define SATA0_CHX_PHY_CTRL4_0_SPARE_IN_SHIFT                _MK_SHIFT_CONST(28)                                                             // RWCVF
#define SATA0_CHX_PHY_CTRL4_0_SPARE_IN_FIELD               (_MK_SHIFT_CONST(0x3) << SATA0_CHX_PHY_CTRL4_0_SPARE_IN_SHIFT)
#define SATA0_CHX_PHY_CTRL4_0_SPARE_IN_RANGE               29:28
#define SATA0_CHX_PHY_CTRL4_0_SPARE_IN_WOFFSET             0
#define SATA0_CHX_PHY_CTRL4_0_SPARE_OUT_SHIFT               _MK_SHIFT_CONST(30)                                                             // R-CVF
#define SATA0_CHX_PHY_CTRL4_0_SPARE_OUT_FIELD              (_MK_SHIFT_CONST(0x3) << SATA0_CHX_PHY_CTRL4_0_SPARE_OUT_SHIFT)
#define SATA0_CHX_PHY_CTRL4_0_SPARE_OUT_RANGE              31:30
#define SATA0_CHX_PHY_CTRL4_0_SPARE_OUT_WOFFSET            0
// 
// 
// 
// 
// 
// 
// 
// 
// 
// 
// 
// 
// 
// 
// 
// 
// 
// 
//         Figure 10-44  Serial ATA Channel 1 Misc register
// .LABEL PUBLIC
// 
// .LABEL ANALOG_PRIVATE INT_REL
// .TITLE SATA PHY Control Register
// This register contains various bits to control the phy
// 
//  31           24 23           16 15            8 7             0
// .-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-.
// |0 0 0 0 0 0 0 0| | |   | | | | |   |   |0 0|   |0|     |0|     | CHX_PHY_CTRL5
// +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
#define SATA0_CHX_PHY_CTRL5_0                              0x000006B8                                                                       // RWC4R
#define SATA0_CHX_PHY_CTRL5_0_SECURE                       0
#define SATA0_CHX_PHY_CTRL5_0_WORD_COUNT                   1
#define SATA0_CHX_PHY_CTRL5_0_RESET_VAL                    0x0
#define SATA0_CHX_PHY_CTRL5_0_RESET_MASK                   0x0
#define SATA0_CHX_PHY_CTRL5_0_SW_DEFAULT_VAL               0x0
#define SATA0_CHX_PHY_CTRL5_0_SW_DEFAULT_MASK              0x0
#define SATA0_CHX_PHY_CTRL5_0_READ_MASK                    0xf0fff0f
#define SATA0_CHX_PHY_CTRL5_0_WRITE_MASK                   0xf0fff0f
#define SATA0_CHX_PHY_CTRL5_0_MISC_CNTL_SHIFT               _MK_SHIFT_CONST(0)                                                              // RWCVF
#define SATA0_CHX_PHY_CTRL5_0_MISC_CNTL_FIELD              (_MK_SHIFT_CONST(0xf) << SATA0_CHX_PHY_CTRL5_0_MISC_CNTL_SHIFT)
#define SATA0_CHX_PHY_CTRL5_0_MISC_CNTL_RANGE              3:0
#define SATA0_CHX_PHY_CTRL5_0_MISC_CNTL_WOFFSET            0
#define SATA0_CHX_PHY_CTRL5_0_TX_SEL_LOAD_SHIFT             _MK_SHIFT_CONST(8)                                                              // RWCVF
#define SATA0_CHX_PHY_CTRL5_0_TX_SEL_LOAD_FIELD            (_MK_SHIFT_CONST(0xf) << SATA0_CHX_PHY_CTRL5_0_TX_SEL_LOAD_SHIFT)
#define SATA0_CHX_PHY_CTRL5_0_TX_SEL_LOAD_RANGE            11:8
#define SATA0_CHX_PHY_CTRL5_0_TX_SEL_LOAD_WOFFSET          0
#define SATA0_CHX_PHY_CTRL5_0_TX_RDET_T_SHIFT               _MK_SHIFT_CONST(12)                                                             // RWCVF
#define SATA0_CHX_PHY_CTRL5_0_TX_RDET_T_FIELD              (_MK_SHIFT_CONST(0x3) << SATA0_CHX_PHY_CTRL5_0_TX_RDET_T_SHIFT)
#define SATA0_CHX_PHY_CTRL5_0_TX_RDET_T_RANGE              13:12
#define SATA0_CHX_PHY_CTRL5_0_TX_RDET_T_WOFFSET            0
#define SATA0_CHX_PHY_CTRL5_0_RX_IDLE_T_SHIFT               _MK_SHIFT_CONST(14)                                                             // RWCVF
#define SATA0_CHX_PHY_CTRL5_0_RX_IDLE_T_FIELD              (_MK_SHIFT_CONST(0x3) << SATA0_CHX_PHY_CTRL5_0_RX_IDLE_T_SHIFT)
#define SATA0_CHX_PHY_CTRL5_0_RX_IDLE_T_RANGE              15:14
#define SATA0_CHX_PHY_CTRL5_0_RX_IDLE_T_WOFFSET            0
#define SATA0_CHX_PHY_CTRL5_0_TX_RDET_BYP_SHIFT             _MK_SHIFT_CONST(16)                                                             // RWCVF
#define SATA0_CHX_PHY_CTRL5_0_TX_RDET_BYP_FIELD            (_MK_SHIFT_CONST(0x1) << SATA0_CHX_PHY_CTRL5_0_TX_RDET_BYP_SHIFT)
#define SATA0_CHX_PHY_CTRL5_0_TX_RDET_BYP_RANGE            16:16
#define SATA0_CHX_PHY_CTRL5_0_TX_RDET_BYP_WOFFSET          0
#define SATA0_CHX_PHY_CTRL5_0_TX_RDET_BYP_DISABLE          _MK_ENUM_CONST(0x00000000)                                                       // RWC-V
#define SATA0_CHX_PHY_CTRL5_0_TX_RDET_BYP_ENABLE           _MK_ENUM_CONST(0x00000001)                                                       // RW--V
#define SATA0_CHX_PHY_CTRL5_0_RX_IDLE_BYP_SHIFT             _MK_SHIFT_CONST(17)                                                             // RWCVF
#define SATA0_CHX_PHY_CTRL5_0_RX_IDLE_BYP_FIELD            (_MK_SHIFT_CONST(0x1) << SATA0_CHX_PHY_CTRL5_0_RX_IDLE_BYP_SHIFT)
#define SATA0_CHX_PHY_CTRL5_0_RX_IDLE_BYP_RANGE            17:17
#define SATA0_CHX_PHY_CTRL5_0_RX_IDLE_BYP_WOFFSET          0
#define SATA0_CHX_PHY_CTRL5_0_RX_IDLE_BYP_DISABLE          _MK_ENUM_CONST(0x00000000)                                                       // RWC-V
#define SATA0_CHX_PHY_CTRL5_0_RX_IDLE_BYP_ENABLE           _MK_ENUM_CONST(0x00000001)                                                       // RW--V
#define SATA0_CHX_PHY_CTRL5_0_RX_IDLE_MODE_SHIFT            _MK_SHIFT_CONST(18)                                                             // RWCVF
#define SATA0_CHX_PHY_CTRL5_0_RX_IDLE_MODE_FIELD           (_MK_SHIFT_CONST(0x1) << SATA0_CHX_PHY_CTRL5_0_RX_IDLE_MODE_SHIFT)
#define SATA0_CHX_PHY_CTRL5_0_RX_IDLE_MODE_RANGE           18:18
#define SATA0_CHX_PHY_CTRL5_0_RX_IDLE_MODE_WOFFSET         0
#define SATA0_CHX_PHY_CTRL5_0_TX_RDET_SHIFT                 _MK_SHIFT_CONST(19)                                                             // RWCVF
#define SATA0_CHX_PHY_CTRL5_0_TX_RDET_FIELD                (_MK_SHIFT_CONST(0x1) << SATA0_CHX_PHY_CTRL5_0_TX_RDET_SHIFT)
#define SATA0_CHX_PHY_CTRL5_0_TX_RDET_RANGE                19:19
#define SATA0_CHX_PHY_CTRL5_0_TX_RDET_WOFFSET              0
#define SATA0_CHX_PHY_CTRL5_0_TX_RDET_IDLE                 _MK_ENUM_CONST(0x00000000)                                                       // RWC-V
#define SATA0_CHX_PHY_CTRL5_0_TX_RDET_START                _MK_ENUM_CONST(0x00000001)                                                       // RW--V
#define SATA0_CHX_PHY_CTRL5_0_CDR_MODE_SHIFT                _MK_SHIFT_CONST(24)                                                             // RWCVF
#define SATA0_CHX_PHY_CTRL5_0_CDR_MODE_FIELD               (_MK_SHIFT_CONST(0xf) << SATA0_CHX_PHY_CTRL5_0_CDR_MODE_SHIFT)
#define SATA0_CHX_PHY_CTRL5_0_CDR_MODE_RANGE               27:24
#define SATA0_CHX_PHY_CTRL5_0_CDR_MODE_WOFFSET             0
// 
// 
// 
// 
// 
// 
// 
// 
// 
// 
// .LABEL PUBLIC
// 
// .LABEL ANALOG_PRIVATE INT_REL
// .TITLE SATA PHY Control Register
// This register contains various bits to control the phy
// 
//  31           24 23           16 15            8 7             0
// .-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-.
// |0 0 0 0 0 0 0 0| | |   | | | | |   |   |0 0|   |0|     |0|     | CHX_PHY_CTRL6
// +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
// 
#define SATA0_CHX_PHY_CTRL6_0                              0x000006BC                                                                       // RWC4R
#define SATA0_CHX_PHY_CTRL6_0_SECURE                       0
#define SATA0_CHX_PHY_CTRL6_0_WORD_COUNT                   1
#define SATA0_CHX_PHY_CTRL6_0_RESET_VAL                    0x0
#define SATA0_CHX_PHY_CTRL6_0_RESET_MASK                   0x0
#define SATA0_CHX_PHY_CTRL6_0_SW_DEFAULT_VAL               0x0
#define SATA0_CHX_PHY_CTRL6_0_SW_DEFAULT_MASK              0x0
#define SATA0_CHX_PHY_CTRL6_0_READ_MASK                    0x1fff7edf
#define SATA0_CHX_PHY_CTRL6_0_WRITE_MASK                   0x7001edf
#define SATA0_CHX_PHY_CTRL6_0_TX_BYP_OUT_SHIFT              _MK_SHIFT_CONST(0)                                                              // RWCVF
#define SATA0_CHX_PHY_CTRL6_0_TX_BYP_OUT_FIELD             (_MK_SHIFT_CONST(0x3) << SATA0_CHX_PHY_CTRL6_0_TX_BYP_OUT_SHIFT)
#define SATA0_CHX_PHY_CTRL6_0_TX_BYP_OUT_RANGE             1:0
#define SATA0_CHX_PHY_CTRL6_0_TX_BYP_OUT_WOFFSET           0
#define SATA0_CHX_PHY_CTRL6_0_TX_BYP_OUT_FALSE             _MK_ENUM_CONST(0x00000000)                                                       // RWC-V
#define SATA0_CHX_PHY_CTRL6_0_TX_BYP_OUT_TRUE              _MK_ENUM_CONST(0x00000001)                                                       // RW--V
#define SATA0_CHX_PHY_CTRL6_0_TX_BYP_DIR_SHIFT              _MK_SHIFT_CONST(2)                                                              // RWCVF
#define SATA0_CHX_PHY_CTRL6_0_TX_BYP_DIR_FIELD             (_MK_SHIFT_CONST(0x1) << SATA0_CHX_PHY_CTRL6_0_TX_BYP_DIR_SHIFT)
#define SATA0_CHX_PHY_CTRL6_0_TX_BYP_DIR_RANGE             2:2
#define SATA0_CHX_PHY_CTRL6_0_TX_BYP_DIR_WOFFSET           0
#define SATA0_CHX_PHY_CTRL6_0_TX_BYP_DIR_FALSE             _MK_ENUM_CONST(0x00000000)                                                       // RWC-V
#define SATA0_CHX_PHY_CTRL6_0_TX_BYP_DIR_TRUE              _MK_ENUM_CONST(0x00000001)                                                       // RW--V
#define SATA0_CHX_PHY_CTRL6_0_TX_BYP_EN_SHIFT               _MK_SHIFT_CONST(3)                                                              // RWCVF
#define SATA0_CHX_PHY_CTRL6_0_TX_BYP_EN_FIELD              (_MK_SHIFT_CONST(0x1) << SATA0_CHX_PHY_CTRL6_0_TX_BYP_EN_SHIFT)
#define SATA0_CHX_PHY_CTRL6_0_TX_BYP_EN_RANGE              3:3
#define SATA0_CHX_PHY_CTRL6_0_TX_BYP_EN_WOFFSET            0
#define SATA0_CHX_PHY_CTRL6_0_TX_BYP_EN_FALSE              _MK_ENUM_CONST(0x00000000)                                                       // RWC-V
#define SATA0_CHX_PHY_CTRL6_0_TX_BYP_EN_TRUE               _MK_ENUM_CONST(0x00000001)                                                       // RW--V
#define SATA0_CHX_PHY_CTRL6_0_RX_BYP_OUT_SHIFT              _MK_SHIFT_CONST(4)                                                              // RWCVF
#define SATA0_CHX_PHY_CTRL6_0_RX_BYP_OUT_FIELD             (_MK_SHIFT_CONST(0x1) << SATA0_CHX_PHY_CTRL6_0_RX_BYP_OUT_SHIFT)
#define SATA0_CHX_PHY_CTRL6_0_RX_BYP_OUT_RANGE             4:4
#define SATA0_CHX_PHY_CTRL6_0_RX_BYP_OUT_WOFFSET           0
#define SATA0_CHX_PHY_CTRL6_0_RX_BYP_OUT_FALSE             _MK_ENUM_CONST(0x00000000)                                                       // RWC-V
#define SATA0_CHX_PHY_CTRL6_0_RX_BYP_OUT_TRUE              _MK_ENUM_CONST(0x00000001)                                                       // RW--V
#define SATA0_CHX_PHY_CTRL6_0_RX_BYP_DIR_SHIFT              _MK_SHIFT_CONST(6)                                                              // RWCVF
#define SATA0_CHX_PHY_CTRL6_0_RX_BYP_DIR_FIELD             (_MK_SHIFT_CONST(0x1) << SATA0_CHX_PHY_CTRL6_0_RX_BYP_DIR_SHIFT)
#define SATA0_CHX_PHY_CTRL6_0_RX_BYP_DIR_RANGE             6:6
#define SATA0_CHX_PHY_CTRL6_0_RX_BYP_DIR_WOFFSET           0
#define SATA0_CHX_PHY_CTRL6_0_RX_BYP_DIR_FALSE             _MK_ENUM_CONST(0x00000000)                                                       // RWC-V
#define SATA0_CHX_PHY_CTRL6_0_RX_BYP_DIR_TRUE              _MK_ENUM_CONST(0x00000001)                                                       // RW--V
#define SATA0_CHX_PHY_CTRL6_0_RX_BYP_EN_SHIFT               _MK_SHIFT_CONST(7)                                                              // RWCVF
#define SATA0_CHX_PHY_CTRL6_0_RX_BYP_EN_FIELD              (_MK_SHIFT_CONST(0x1) << SATA0_CHX_PHY_CTRL6_0_RX_BYP_EN_SHIFT)
#define SATA0_CHX_PHY_CTRL6_0_RX_BYP_EN_RANGE              7:7
#define SATA0_CHX_PHY_CTRL6_0_RX_BYP_EN_WOFFSET            0
#define SATA0_CHX_PHY_CTRL6_0_RX_BYP_EN_FALSE              _MK_ENUM_CONST(0x00000000)                                                       // RWC-V
#define SATA0_CHX_PHY_CTRL6_0_RX_BYP_EN_TRUE               _MK_ENUM_CONST(0x00000001)                                                       // RW--V
#define SATA0_CHX_PHY_CTRL6_0_RX_BYP_MODE_SHIFT             _MK_SHIFT_CONST(9)                                                              // RWCVF
#define SATA0_CHX_PHY_CTRL6_0_RX_BYP_MODE_FIELD            (_MK_SHIFT_CONST(0x3) << SATA0_CHX_PHY_CTRL6_0_RX_BYP_MODE_SHIFT)
#define SATA0_CHX_PHY_CTRL6_0_RX_BYP_MODE_RANGE            10:9
#define SATA0_CHX_PHY_CTRL6_0_RX_BYP_MODE_WOFFSET          0
#define SATA0_CHX_PHY_CTRL6_0_RX_BYP_MODE_FALSE            _MK_ENUM_CONST(0x00000000)                                                       // RWC-V
#define SATA0_CHX_PHY_CTRL6_0_RX_BYP_MODE_TRUE             _MK_ENUM_CONST(0x00000001)                                                       // RW--V
#define SATA0_CHX_PHY_CTRL6_0_TX_BYP_MODE_SHIFT             _MK_SHIFT_CONST(11)                                                             // RWCVF
#define SATA0_CHX_PHY_CTRL6_0_TX_BYP_MODE_FIELD            (_MK_SHIFT_CONST(0x3) << SATA0_CHX_PHY_CTRL6_0_TX_BYP_MODE_SHIFT)
#define SATA0_CHX_PHY_CTRL6_0_TX_BYP_MODE_RANGE            12:11
#define SATA0_CHX_PHY_CTRL6_0_TX_BYP_MODE_WOFFSET          0
#define SATA0_CHX_PHY_CTRL6_0_TX_BYP_MODE_FALSE            _MK_ENUM_CONST(0x00000000)                                                       // RWC-V
#define SATA0_CHX_PHY_CTRL6_0_TX_BYP_MODE_TRUE             _MK_ENUM_CONST(0x00000001)                                                       // RW--V
#define SATA0_CHX_PHY_CTRL6_0_TX_BYP_IN_SHIFT               _MK_SHIFT_CONST(13)                                                             // R-CVF
#define SATA0_CHX_PHY_CTRL6_0_TX_BYP_IN_FIELD              (_MK_SHIFT_CONST(0x1) << SATA0_CHX_PHY_CTRL6_0_TX_BYP_IN_SHIFT)
#define SATA0_CHX_PHY_CTRL6_0_TX_BYP_IN_RANGE              13:13
#define SATA0_CHX_PHY_CTRL6_0_TX_BYP_IN_WOFFSET            0
#define SATA0_CHX_PHY_CTRL6_0_RX_BYP_IN_SHIFT               _MK_SHIFT_CONST(14)                                                             // R-CVF
#define SATA0_CHX_PHY_CTRL6_0_RX_BYP_IN_FIELD              (_MK_SHIFT_CONST(0x1) << SATA0_CHX_PHY_CTRL6_0_RX_BYP_IN_SHIFT)
#define SATA0_CHX_PHY_CTRL6_0_RX_BYP_IN_RANGE              14:14
#define SATA0_CHX_PHY_CTRL6_0_RX_BYP_IN_WOFFSET            0
#define SATA0_CHX_PHY_CTRL6_0_MISC_OUT_SHIFT                _MK_SHIFT_CONST(16)                                                             // R-CVF
#define SATA0_CHX_PHY_CTRL6_0_MISC_OUT_FIELD               (_MK_SHIFT_CONST(0xff) << SATA0_CHX_PHY_CTRL6_0_MISC_OUT_SHIFT)
#define SATA0_CHX_PHY_CTRL6_0_MISC_OUT_RANGE               23:16
#define SATA0_CHX_PHY_CTRL6_0_MISC_OUT_WOFFSET             0
#define SATA0_CHX_PHY_CTRL6_0_TX_TERM_MODE_SHIFT            _MK_SHIFT_CONST(24)                                                             // RWCVF
#define SATA0_CHX_PHY_CTRL6_0_TX_TERM_MODE_FIELD           (_MK_SHIFT_CONST(0x1) << SATA0_CHX_PHY_CTRL6_0_TX_TERM_MODE_SHIFT)
#define SATA0_CHX_PHY_CTRL6_0_TX_TERM_MODE_RANGE           24:24
#define SATA0_CHX_PHY_CTRL6_0_TX_TERM_MODE_WOFFSET         0
#define SATA0_CHX_PHY_CTRL6_0_TX_TERM_MODE_FALSE           _MK_ENUM_CONST(0x00000000)                                                       // RWC-V
#define SATA0_CHX_PHY_CTRL6_0_TX_TERM_MODE_TRUE            _MK_ENUM_CONST(0x00000001)                                                       // RW--V
#define SATA0_CHX_PHY_CTRL6_0_RX_TERM_EN_SHIFT              _MK_SHIFT_CONST(25)                                                             // RWCVF
#define SATA0_CHX_PHY_CTRL6_0_RX_TERM_EN_FIELD             (_MK_SHIFT_CONST(0x1) << SATA0_CHX_PHY_CTRL6_0_RX_TERM_EN_SHIFT)
#define SATA0_CHX_PHY_CTRL6_0_RX_TERM_EN_RANGE             25:25
#define SATA0_CHX_PHY_CTRL6_0_RX_TERM_EN_WOFFSET           0
#define SATA0_CHX_PHY_CTRL6_0_RX_TERM_EN_FALSE             _MK_ENUM_CONST(0x00000000)                                                       // RWC-V
#define SATA0_CHX_PHY_CTRL6_0_RX_TERM_EN_TRUE              _MK_ENUM_CONST(0x00000001)                                                       // RW--V
#define SATA0_CHX_PHY_CTRL6_0_RX_TERM_MODE_SHIFT            _MK_SHIFT_CONST(26)                                                             // RWCVF
#define SATA0_CHX_PHY_CTRL6_0_RX_TERM_MODE_FIELD           (_MK_SHIFT_CONST(0x1) << SATA0_CHX_PHY_CTRL6_0_RX_TERM_MODE_SHIFT)
#define SATA0_CHX_PHY_CTRL6_0_RX_TERM_MODE_RANGE           26:26
#define SATA0_CHX_PHY_CTRL6_0_RX_TERM_MODE_WOFFSET         0
#define SATA0_CHX_PHY_CTRL6_0_RX_TERM_MODE_FALSE           _MK_ENUM_CONST(0x00000000)                                                       // RWC-V
#define SATA0_CHX_PHY_CTRL6_0_RX_TERM_MODE_TRUE            _MK_ENUM_CONST(0x00000001)                                                       // RW--V
#define SATA0_CHX_PHY_CTRL6_0_RX_BYP_DATA_SHIFT             _MK_SHIFT_CONST(27)                                                             // R-CVF
#define SATA0_CHX_PHY_CTRL6_0_RX_BYP_DATA_FIELD            (_MK_SHIFT_CONST(0x3) << SATA0_CHX_PHY_CTRL6_0_RX_BYP_DATA_SHIFT)
#define SATA0_CHX_PHY_CTRL6_0_RX_BYP_DATA_RANGE            28:27
#define SATA0_CHX_PHY_CTRL6_0_RX_BYP_DATA_WOFFSET          0
// 
// 
// 
// 
// 
// 
// 
// 
// 
// 
// 
// 
// 
// 
// 
// 
// 
// .LABEL PUBLIC
// 
// .LABEL ANALOG_PRIVATE INT_REL
// .TITLE SATA PHY Control Register
// This register contains various bits to control the phy
//  31           24 23           16 15            8 7             0
// .-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-.
// |0 0 0 0 0 0 0 0| | |   | | | | |   |   |0 0|   |0|     |0|     | CHX_PHY_CTRL7
// +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
#define SATA0_CHX_PHY_CTRL7_0                              0x000006C0                                                                       // RWW4R
#define SATA0_CHX_PHY_CTRL7_0_SECURE                       0
#define SATA0_CHX_PHY_CTRL7_0_WORD_COUNT                   1
#define SATA0_CHX_PHY_CTRL7_0_RESET_VAL                    0x0
#define SATA0_CHX_PHY_CTRL7_0_RESET_MASK                   0x0
#define SATA0_CHX_PHY_CTRL7_0_SW_DEFAULT_VAL               0x0
#define SATA0_CHX_PHY_CTRL7_0_SW_DEFAULT_MASK              0x0
#define SATA0_CHX_PHY_CTRL7_0_READ_MASK                    0xffffff
#define SATA0_CHX_PHY_CTRL7_0_WRITE_MASK                   0xffffff
#define SATA0_CHX_PHY_CTRL7_0_TX_TERM_CNTL_GEN1_SHIFT       _MK_SHIFT_CONST(0)                                                              // RWCVF
#define SATA0_CHX_PHY_CTRL7_0_TX_TERM_CNTL_GEN1_FIELD      (_MK_SHIFT_CONST(0x3) << SATA0_CHX_PHY_CTRL7_0_TX_TERM_CNTL_GEN1_SHIFT)
#define SATA0_CHX_PHY_CTRL7_0_TX_TERM_CNTL_GEN1_RANGE      1:0
#define SATA0_CHX_PHY_CTRL7_0_TX_TERM_CNTL_GEN1_WOFFSET    0
#define SATA0_CHX_PHY_CTRL7_0_RX_TERM_CNTL_GEN1_SHIFT       _MK_SHIFT_CONST(2)                                                              // RWCVF
#define SATA0_CHX_PHY_CTRL7_0_RX_TERM_CNTL_GEN1_FIELD      (_MK_SHIFT_CONST(0x3) << SATA0_CHX_PHY_CTRL7_0_RX_TERM_CNTL_GEN1_SHIFT)
#define SATA0_CHX_PHY_CTRL7_0_RX_TERM_CNTL_GEN1_RANGE      3:2
#define SATA0_CHX_PHY_CTRL7_0_RX_TERM_CNTL_GEN1_WOFFSET    0
#define SATA0_CHX_PHY_CTRL7_0_RX_WANDER_GEN1_SHIFT          _MK_SHIFT_CONST(4)                                                              // RWCVF
#define SATA0_CHX_PHY_CTRL7_0_RX_WANDER_GEN1_FIELD         (_MK_SHIFT_CONST(0xf) << SATA0_CHX_PHY_CTRL7_0_RX_WANDER_GEN1_SHIFT)
#define SATA0_CHX_PHY_CTRL7_0_RX_WANDER_GEN1_RANGE         7:4
#define SATA0_CHX_PHY_CTRL7_0_RX_WANDER_GEN1_WOFFSET       0
#define SATA0_CHX_PHY_CTRL7_0_TX_TERM_CNTL_GEN2_SHIFT       _MK_SHIFT_CONST(8)                                                              // RWCVF
#define SATA0_CHX_PHY_CTRL7_0_TX_TERM_CNTL_GEN2_FIELD      (_MK_SHIFT_CONST(0x3) << SATA0_CHX_PHY_CTRL7_0_TX_TERM_CNTL_GEN2_SHIFT)
#define SATA0_CHX_PHY_CTRL7_0_TX_TERM_CNTL_GEN2_RANGE      9:8
#define SATA0_CHX_PHY_CTRL7_0_TX_TERM_CNTL_GEN2_WOFFSET    0
#define SATA0_CHX_PHY_CTRL7_0_RX_TERM_CNTL_GEN2_SHIFT       _MK_SHIFT_CONST(10)                                                             // RWCVF
#define SATA0_CHX_PHY_CTRL7_0_RX_TERM_CNTL_GEN2_FIELD      (_MK_SHIFT_CONST(0x3) << SATA0_CHX_PHY_CTRL7_0_RX_TERM_CNTL_GEN2_SHIFT)
#define SATA0_CHX_PHY_CTRL7_0_RX_TERM_CNTL_GEN2_RANGE      11:10
#define SATA0_CHX_PHY_CTRL7_0_RX_TERM_CNTL_GEN2_WOFFSET    0
#define SATA0_CHX_PHY_CTRL7_0_RX_WANDER_GEN2_SHIFT          _MK_SHIFT_CONST(12)                                                             // RWCVF
#define SATA0_CHX_PHY_CTRL7_0_RX_WANDER_GEN2_FIELD         (_MK_SHIFT_CONST(0xf) << SATA0_CHX_PHY_CTRL7_0_RX_WANDER_GEN2_SHIFT)
#define SATA0_CHX_PHY_CTRL7_0_RX_WANDER_GEN2_RANGE         15:12
#define SATA0_CHX_PHY_CTRL7_0_RX_WANDER_GEN2_WOFFSET       0
#define SATA0_CHX_PHY_CTRL7_0_TX_TERM_CNTL_GEN3_SHIFT       _MK_SHIFT_CONST(16)                                                             // RWCVF
#define SATA0_CHX_PHY_CTRL7_0_TX_TERM_CNTL_GEN3_FIELD      (_MK_SHIFT_CONST(0x3) << SATA0_CHX_PHY_CTRL7_0_TX_TERM_CNTL_GEN3_SHIFT)
#define SATA0_CHX_PHY_CTRL7_0_TX_TERM_CNTL_GEN3_RANGE      17:16
#define SATA0_CHX_PHY_CTRL7_0_TX_TERM_CNTL_GEN3_WOFFSET    0
#define SATA0_CHX_PHY_CTRL7_0_RX_TERM_CNTL_GEN3_SHIFT       _MK_SHIFT_CONST(18)                                                             // RWCVF
#define SATA0_CHX_PHY_CTRL7_0_RX_TERM_CNTL_GEN3_FIELD      (_MK_SHIFT_CONST(0x3) << SATA0_CHX_PHY_CTRL7_0_RX_TERM_CNTL_GEN3_SHIFT)
#define SATA0_CHX_PHY_CTRL7_0_RX_TERM_CNTL_GEN3_RANGE      19:18
#define SATA0_CHX_PHY_CTRL7_0_RX_TERM_CNTL_GEN3_WOFFSET    0
#define SATA0_CHX_PHY_CTRL7_0_RX_WANDER_GEN3_SHIFT          _MK_SHIFT_CONST(20)                                                             // RWCVF
#define SATA0_CHX_PHY_CTRL7_0_RX_WANDER_GEN3_FIELD         (_MK_SHIFT_CONST(0xf) << SATA0_CHX_PHY_CTRL7_0_RX_WANDER_GEN3_SHIFT)
#define SATA0_CHX_PHY_CTRL7_0_RX_WANDER_GEN3_RANGE         23:20
#define SATA0_CHX_PHY_CTRL7_0_RX_WANDER_GEN3_WOFFSET       0
// 
// 
// 
// .LABEL PRIVATE INT_REL
// .LABEL PUBLIC
// 
// .LABEL ANALOG_PRIVATE INT_REL
// .TITLE SATA PHY Control Register
// This register contains various bits to control the phy
//  31           24 23           16 15            8 7             0
// .-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-.
// |0 0 0 0 0 0 0 0| | |   | | | | |   |   |0 0|   |0|     |0|     | CHX_PHY_CTRL7
// +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
#define SATA0_CHX_PHY_CTRL8_0                              0x000006C4                                                                       // RWW4R
#define SATA0_CHX_PHY_CTRL8_0_SECURE                       0
#define SATA0_CHX_PHY_CTRL8_0_WORD_COUNT                   1
#define SATA0_CHX_PHY_CTRL8_0_RESET_VAL                    0x0
#define SATA0_CHX_PHY_CTRL8_0_RESET_MASK                   0x0
#define SATA0_CHX_PHY_CTRL8_0_SW_DEFAULT_VAL               0x0
#define SATA0_CHX_PHY_CTRL8_0_SW_DEFAULT_MASK              0x0
#define SATA0_CHX_PHY_CTRL8_0_READ_MASK                    0x3f0111
#define SATA0_CHX_PHY_CTRL8_0_WRITE_MASK                   0x111
#define SATA0_CHX_PHY_CTRL8_0_RX_QEYE_EN_GEN1_SHIFT         _MK_SHIFT_CONST(0)                                                              // RWCVF
#define SATA0_CHX_PHY_CTRL8_0_RX_QEYE_EN_GEN1_FIELD        (_MK_SHIFT_CONST(0x1) << SATA0_CHX_PHY_CTRL8_0_RX_QEYE_EN_GEN1_SHIFT)
#define SATA0_CHX_PHY_CTRL8_0_RX_QEYE_EN_GEN1_RANGE        0:0
#define SATA0_CHX_PHY_CTRL8_0_RX_QEYE_EN_GEN1_WOFFSET      0
#define SATA0_CHX_PHY_CTRL8_0_RX_QEYE_EN_GEN2_SHIFT         _MK_SHIFT_CONST(4)                                                              // RWCVF
#define SATA0_CHX_PHY_CTRL8_0_RX_QEYE_EN_GEN2_FIELD        (_MK_SHIFT_CONST(0x1) << SATA0_CHX_PHY_CTRL8_0_RX_QEYE_EN_GEN2_SHIFT)
#define SATA0_CHX_PHY_CTRL8_0_RX_QEYE_EN_GEN2_RANGE        4:4
#define SATA0_CHX_PHY_CTRL8_0_RX_QEYE_EN_GEN2_WOFFSET      0
#define SATA0_CHX_PHY_CTRL8_0_RX_QEYE_EN_GEN3_SHIFT         _MK_SHIFT_CONST(8)                                                              // RWCVF
#define SATA0_CHX_PHY_CTRL8_0_RX_QEYE_EN_GEN3_FIELD        (_MK_SHIFT_CONST(0x1) << SATA0_CHX_PHY_CTRL8_0_RX_QEYE_EN_GEN3_SHIFT)
#define SATA0_CHX_PHY_CTRL8_0_RX_QEYE_EN_GEN3_RANGE        8:8
#define SATA0_CHX_PHY_CTRL8_0_RX_QEYE_EN_GEN3_WOFFSET      0
#define SATA0_CHX_PHY_CTRL8_0_RX_QEYE_OUT_SHIFT             _MK_SHIFT_CONST(16)                                                             // R-CVF
#define SATA0_CHX_PHY_CTRL8_0_RX_QEYE_OUT_FIELD            (_MK_SHIFT_CONST(0x3f) << SATA0_CHX_PHY_CTRL8_0_RX_QEYE_OUT_SHIFT)
#define SATA0_CHX_PHY_CTRL8_0_RX_QEYE_OUT_RANGE            21:16
#define SATA0_CHX_PHY_CTRL8_0_RX_QEYE_OUT_WOFFSET          0
// 
// 
// 
// .LABEL PRIVATE INT_REL
// .LABEL ANALOG_PRIVATE INT_REL
// 
// .LABEL PUBLIC
// 
// .LABEL ANALOG_PRIVATE INT_REL
// .TITLE SATA PHY Control Register
// This register contains various bits to control the phy
//  31           24 23           16 15            8 7             0
// .-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-.
// |0 0 0 0 0 0 0 0| | |   | | | | |   |   |0 0|   |0|     |0|     | CHX_PHY_CTRL9
// +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
#define SATA0_CHX_PHY_CTRL9_0                              0x000006C8                                                                       // RWW4R
#define SATA0_CHX_PHY_CTRL9_0_SECURE                       0
#define SATA0_CHX_PHY_CTRL9_0_WORD_COUNT                   1
#define SATA0_CHX_PHY_CTRL9_0_RESET_VAL                    0x0
#define SATA0_CHX_PHY_CTRL9_0_RESET_MASK                   0x0
#define SATA0_CHX_PHY_CTRL9_0_SW_DEFAULT_VAL               0x0
#define SATA0_CHX_PHY_CTRL9_0_SW_DEFAULT_MASK              0x0
#define SATA0_CHX_PHY_CTRL9_0_READ_MASK                    0xffffff07
#define SATA0_CHX_PHY_CTRL9_0_WRITE_MASK                   0xffffff05
#define SATA0_CHX_PHY_CTRL9_0_DFE_TRAIN_EN_SHIFT            _MK_SHIFT_CONST(0)                                                              // RWCVF
#define SATA0_CHX_PHY_CTRL9_0_DFE_TRAIN_EN_FIELD           (_MK_SHIFT_CONST(0x1) << SATA0_CHX_PHY_CTRL9_0_DFE_TRAIN_EN_SHIFT)
#define SATA0_CHX_PHY_CTRL9_0_DFE_TRAIN_EN_RANGE           0:0
#define SATA0_CHX_PHY_CTRL9_0_DFE_TRAIN_EN_WOFFSET         0
#define SATA0_CHX_PHY_CTRL9_0_DFE_TRAIN_DONE_SHIFT          _MK_SHIFT_CONST(1)                                                              // R-CVF
#define SATA0_CHX_PHY_CTRL9_0_DFE_TRAIN_DONE_FIELD         (_MK_SHIFT_CONST(0x1) << SATA0_CHX_PHY_CTRL9_0_DFE_TRAIN_DONE_SHIFT)
#define SATA0_CHX_PHY_CTRL9_0_DFE_TRAIN_DONE_RANGE         1:1
#define SATA0_CHX_PHY_CTRL9_0_DFE_TRAIN_DONE_WOFFSET       0
#define SATA0_CHX_PHY_CTRL9_0_DFE_RESET_SHIFT               _MK_SHIFT_CONST(2)                                                              // RWCVF
#define SATA0_CHX_PHY_CTRL9_0_DFE_RESET_FIELD              (_MK_SHIFT_CONST(0x1) << SATA0_CHX_PHY_CTRL9_0_DFE_RESET_SHIFT)
#define SATA0_CHX_PHY_CTRL9_0_DFE_RESET_RANGE              2:2
#define SATA0_CHX_PHY_CTRL9_0_DFE_RESET_WOFFSET            0
#define SATA0_CHX_PHY_CTRL9_0_MISC_OUT_SEL_SHIFT            _MK_SHIFT_CONST(8)                                                              // RWCVF
#define SATA0_CHX_PHY_CTRL9_0_MISC_OUT_SEL_FIELD           (_MK_SHIFT_CONST(0xff) << SATA0_CHX_PHY_CTRL9_0_MISC_OUT_SEL_SHIFT)
#define SATA0_CHX_PHY_CTRL9_0_MISC_OUT_SEL_RANGE           15:8
#define SATA0_CHX_PHY_CTRL9_0_MISC_OUT_SEL_WOFFSET         0
#define SATA0_CHX_PHY_CTRL9_0_MISC_TEST_SHIFT               _MK_SHIFT_CONST(16)                                                             // RWCVF
#define SATA0_CHX_PHY_CTRL9_0_MISC_TEST_FIELD              (_MK_SHIFT_CONST(0xffff) << SATA0_CHX_PHY_CTRL9_0_MISC_TEST_SHIFT)
#define SATA0_CHX_PHY_CTRL9_0_MISC_TEST_RANGE              31:16
#define SATA0_CHX_PHY_CTRL9_0_MISC_TEST_WOFFSET            0
// 
// 
// 
// 
// 
// 
// .LABEL PUBLIC
// 
// .LABEL ANALOG_PRIVATE INT_REL
// .TITLE SATA PHY Control Register
// This register contains various bits to control the phy
//  31           24 23           16 15            8 7             0
// .-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-.
// |0 0 0 0 0 0 0 0| | |   | | | | |   |   |0 0|   |0|     |0|     | CHX_PHY_CTRL10
// +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
#define SATA0_CHX_PHY_CTRL10_0                             0x000006CC                                                                       // RWW4R
#define SATA0_CHX_PHY_CTRL10_0_SECURE                      0
#define SATA0_CHX_PHY_CTRL10_0_WORD_COUNT                  1
#define SATA0_CHX_PHY_CTRL10_0_RESET_VAL                   0x0
#define SATA0_CHX_PHY_CTRL10_0_RESET_MASK                  0x0
#define SATA0_CHX_PHY_CTRL10_0_SW_DEFAULT_VAL              0x0
#define SATA0_CHX_PHY_CTRL10_0_SW_DEFAULT_MASK             0x0
#define SATA0_CHX_PHY_CTRL10_0_READ_MASK                   0xffff0107
#define SATA0_CHX_PHY_CTRL10_0_WRITE_MASK                  0xffff0105
#define SATA0_CHX_PHY_CTRL10_0_EOM_TRAIN_EN_SHIFT           _MK_SHIFT_CONST(0)                                                              // RWCVF
#define SATA0_CHX_PHY_CTRL10_0_EOM_TRAIN_EN_FIELD          (_MK_SHIFT_CONST(0x1) << SATA0_CHX_PHY_CTRL10_0_EOM_TRAIN_EN_SHIFT)
#define SATA0_CHX_PHY_CTRL10_0_EOM_TRAIN_EN_RANGE          0:0
#define SATA0_CHX_PHY_CTRL10_0_EOM_TRAIN_EN_WOFFSET        0
#define SATA0_CHX_PHY_CTRL10_0_EOM_TRAIN_DONE_SHIFT         _MK_SHIFT_CONST(1)                                                              // R-CVF
#define SATA0_CHX_PHY_CTRL10_0_EOM_TRAIN_DONE_FIELD        (_MK_SHIFT_CONST(0x1) << SATA0_CHX_PHY_CTRL10_0_EOM_TRAIN_DONE_SHIFT)
#define SATA0_CHX_PHY_CTRL10_0_EOM_TRAIN_DONE_RANGE        1:1
#define SATA0_CHX_PHY_CTRL10_0_EOM_TRAIN_DONE_WOFFSET      0
#define SATA0_CHX_PHY_CTRL10_0_EOM_EN_SHIFT                 _MK_SHIFT_CONST(2)                                                              // RWCVF
#define SATA0_CHX_PHY_CTRL10_0_EOM_EN_FIELD                (_MK_SHIFT_CONST(0x1) << SATA0_CHX_PHY_CTRL10_0_EOM_EN_SHIFT)
#define SATA0_CHX_PHY_CTRL10_0_EOM_EN_RANGE                2:2
#define SATA0_CHX_PHY_CTRL10_0_EOM_EN_WOFFSET              0
#define SATA0_CHX_PHY_CTRL10_0_OOB_RX_CAL_EN_SHIFT          _MK_SHIFT_CONST(8)                                                              // RWCVF
#define SATA0_CHX_PHY_CTRL10_0_OOB_RX_CAL_EN_FIELD         (_MK_SHIFT_CONST(0x1) << SATA0_CHX_PHY_CTRL10_0_OOB_RX_CAL_EN_SHIFT)
#define SATA0_CHX_PHY_CTRL10_0_OOB_RX_CAL_EN_RANGE         8:8
#define SATA0_CHX_PHY_CTRL10_0_OOB_RX_CAL_EN_WOFFSET       0
#define SATA0_CHX_PHY_CTRL10_0_EOM_CNTL_SHIFT               _MK_SHIFT_CONST(16)                                                             // RWCVF
#define SATA0_CHX_PHY_CTRL10_0_EOM_CNTL_FIELD              (_MK_SHIFT_CONST(0xffff) << SATA0_CHX_PHY_CTRL10_0_EOM_CNTL_SHIFT)
#define SATA0_CHX_PHY_CTRL10_0_EOM_CNTL_RANGE              31:16
#define SATA0_CHX_PHY_CTRL10_0_EOM_CNTL_WOFFSET            0
// 
// 
// 
// 
// 
// .LABEL PUBLIC
// 
// 
// .LABEL ANALOG_PRIVATE INT_REL
// .TITLE SATA PHY Control Register
// This register contains various bits to control the phy
//  31           24 23           16 15            8 7             0
// .-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-.
// |0 0 0 0 0 0 0 0| | |   | | | | |   |   |0 0|   |0|     |0|     | CHX_PHY_CTRL11
// +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
#define SATA0_CHX_PHY_CTRL11_0                             0x000006D0                                                                       // RWW4R
#define SATA0_CHX_PHY_CTRL11_0_SECURE                      0
#define SATA0_CHX_PHY_CTRL11_0_WORD_COUNT                  1
#define SATA0_CHX_PHY_CTRL11_0_RESET_VAL                   0x0
#define SATA0_CHX_PHY_CTRL11_0_RESET_MASK                  0x0
#define SATA0_CHX_PHY_CTRL11_0_SW_DEFAULT_VAL              0x0
#define SATA0_CHX_PHY_CTRL11_0_SW_DEFAULT_MASK             0x0
#define SATA0_CHX_PHY_CTRL11_0_READ_MASK                   0xffffffff
#define SATA0_CHX_PHY_CTRL11_0_WRITE_MASK                  0xffffffff
#define SATA0_CHX_PHY_CTRL11_0_GEN1_RX_EQ_SHIFT             _MK_SHIFT_CONST(0)                                                              // RWCVF
#define SATA0_CHX_PHY_CTRL11_0_GEN1_RX_EQ_FIELD            (_MK_SHIFT_CONST(0xffff) << SATA0_CHX_PHY_CTRL11_0_GEN1_RX_EQ_SHIFT)
#define SATA0_CHX_PHY_CTRL11_0_GEN1_RX_EQ_RANGE            15:0
#define SATA0_CHX_PHY_CTRL11_0_GEN1_RX_EQ_WOFFSET          0
#define SATA0_CHX_PHY_CTRL11_0_GEN1_RX_EQ_DEFAULT2         _MK_ENUM_CONST(0x0000000F)                                                       // RW--V
#define SATA0_CHX_PHY_CTRL11_0_GEN1_RX_EQ_DEFAULT3         _MK_ENUM_CONST(0x0000000F)                                                       // RW--V
#define SATA0_CHX_PHY_CTRL11_0_GEN1_RX_EQ_DEFAULT4         _MK_ENUM_CONST(0x0000000F)                                                       // RW--V
#define SATA0_CHX_PHY_CTRL11_0_GEN2_RX_EQ_SHIFT             _MK_SHIFT_CONST(16)                                                             // RWCVF
#define SATA0_CHX_PHY_CTRL11_0_GEN2_RX_EQ_FIELD            (_MK_SHIFT_CONST(0xffff) << SATA0_CHX_PHY_CTRL11_0_GEN2_RX_EQ_SHIFT)
#define SATA0_CHX_PHY_CTRL11_0_GEN2_RX_EQ_RANGE            31:16
#define SATA0_CHX_PHY_CTRL11_0_GEN2_RX_EQ_WOFFSET          0
#define SATA0_CHX_PHY_CTRL11_0_GEN2_RX_EQ_DEFAULT2         _MK_ENUM_CONST(0x0000004F)                                                       // RW--V
#define SATA0_CHX_PHY_CTRL11_0_GEN2_RX_EQ_DEFAULT3         _MK_ENUM_CONST(0x0000000F)                                                       // RW--V
#define SATA0_CHX_PHY_CTRL11_0_GEN2_RX_EQ_DEFAULT4         _MK_ENUM_CONST(0x000000CD)                                                       // RW--V
// 
// 
// .LABEL PUBLIC
// 
// .LABEL ANALOG_PRIVATE INT_REL
// .TITLE SATA PHY Control Register
// This register contains various bits to control the phy
//  31           24 23           16 15            8 7             0
// .-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-.
// |0 0 0 0 0 0 0 0| | |   | | | | |   |   |0 0|   |0|     |0|     | CHX_PHY_CTRL12
// +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
#define SATA0_CHX_PHY_CTRL12_0                             0x000006D4                                                                       // RWW4R
#define SATA0_CHX_PHY_CTRL12_0_SECURE                      0
#define SATA0_CHX_PHY_CTRL12_0_WORD_COUNT                  1
#define SATA0_CHX_PHY_CTRL12_0_RESET_VAL                   0x0
#define SATA0_CHX_PHY_CTRL12_0_RESET_MASK                  0x0
#define SATA0_CHX_PHY_CTRL12_0_SW_DEFAULT_VAL              0x0
#define SATA0_CHX_PHY_CTRL12_0_SW_DEFAULT_MASK             0x0
#define SATA0_CHX_PHY_CTRL12_0_READ_MASK                   0xffff
#define SATA0_CHX_PHY_CTRL12_0_WRITE_MASK                  0xffff
#define SATA0_CHX_PHY_CTRL12_0_GEN3_RX_EQ_SHIFT             _MK_SHIFT_CONST(0)                                                              // RWCVF
#define SATA0_CHX_PHY_CTRL12_0_GEN3_RX_EQ_FIELD            (_MK_SHIFT_CONST(0xffff) << SATA0_CHX_PHY_CTRL12_0_GEN3_RX_EQ_SHIFT)
#define SATA0_CHX_PHY_CTRL12_0_GEN3_RX_EQ_RANGE            15:0
#define SATA0_CHX_PHY_CTRL12_0_GEN3_RX_EQ_WOFFSET          0
// 
// .LABEL PUBLIC
// 
// 
// .LABEL ANALOG_PRIVATE INT_REL
// .TITLE SATA PHY Control Register
// This register contains various bits to control the phy
//  31           24 23           16 15            8 7             0
// .-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-.
// |0 0 0 0 0 0 0 0| | |   | | | | |   |   |0 0|   |0|     |0|     | CHX_PHY_CTRL13
// +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
#define SATA0_CHX_PHY_CTRL13_0                             0x000006D8                                                                       // RWW4R
#define SATA0_CHX_PHY_CTRL13_0_SECURE                      0
#define SATA0_CHX_PHY_CTRL13_0_WORD_COUNT                  1
#define SATA0_CHX_PHY_CTRL13_0_RESET_VAL                   0x0
#define SATA0_CHX_PHY_CTRL13_0_RESET_MASK                  0x0
#define SATA0_CHX_PHY_CTRL13_0_SW_DEFAULT_VAL              0x0
#define SATA0_CHX_PHY_CTRL13_0_SW_DEFAULT_MASK             0x0
#define SATA0_CHX_PHY_CTRL13_0_READ_MASK                   0xffffff
#define SATA0_CHX_PHY_CTRL13_0_WRITE_MASK                  0xffffff
#define SATA0_CHX_PHY_CTRL13_0_CDR_TEST_SHIFT               _MK_SHIFT_CONST(0)                                                              // RWCVF
#define SATA0_CHX_PHY_CTRL13_0_CDR_TEST_FIELD              (_MK_SHIFT_CONST(0xfff) << SATA0_CHX_PHY_CTRL13_0_CDR_TEST_SHIFT)
#define SATA0_CHX_PHY_CTRL13_0_CDR_TEST_RANGE              11:0
#define SATA0_CHX_PHY_CTRL13_0_CDR_TEST_WOFFSET            0
#define SATA0_CHX_PHY_CTRL13_0_RX_IQ_CTRL_GEN1_SHIFT        _MK_SHIFT_CONST(12)                                                             // RWCVF
#define SATA0_CHX_PHY_CTRL13_0_RX_IQ_CTRL_GEN1_FIELD       (_MK_SHIFT_CONST(0xf) << SATA0_CHX_PHY_CTRL13_0_RX_IQ_CTRL_GEN1_SHIFT)
#define SATA0_CHX_PHY_CTRL13_0_RX_IQ_CTRL_GEN1_RANGE       15:12
#define SATA0_CHX_PHY_CTRL13_0_RX_IQ_CTRL_GEN1_WOFFSET     0
#define SATA0_CHX_PHY_CTRL13_0_RX_IQ_CTRL_GEN2_SHIFT        _MK_SHIFT_CONST(16)                                                             // RWCVF
#define SATA0_CHX_PHY_CTRL13_0_RX_IQ_CTRL_GEN2_FIELD       (_MK_SHIFT_CONST(0xf) << SATA0_CHX_PHY_CTRL13_0_RX_IQ_CTRL_GEN2_SHIFT)
#define SATA0_CHX_PHY_CTRL13_0_RX_IQ_CTRL_GEN2_RANGE       19:16
#define SATA0_CHX_PHY_CTRL13_0_RX_IQ_CTRL_GEN2_WOFFSET     0
#define SATA0_CHX_PHY_CTRL13_0_RX_IQ_CTRL_GEN3_SHIFT        _MK_SHIFT_CONST(20)                                                             // RWCVF
#define SATA0_CHX_PHY_CTRL13_0_RX_IQ_CTRL_GEN3_FIELD       (_MK_SHIFT_CONST(0xf) << SATA0_CHX_PHY_CTRL13_0_RX_IQ_CTRL_GEN3_SHIFT)
#define SATA0_CHX_PHY_CTRL13_0_RX_IQ_CTRL_GEN3_RANGE       23:20
#define SATA0_CHX_PHY_CTRL13_0_RX_IQ_CTRL_GEN3_WOFFSET     0
// 
// 
// .LABEL PUBLIC
// 
// .LABEL ANALOG_PRIVATE INT_REL
// .TITLE SATA PHY Control Register
// This register contains various bits to control the phy
//  31           24 23           16 15            8 7             0
// .-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-.
// |0 0 0 0 0 0 0 0| | |   | | | | |   |   |0 0|   |0|     |0|     | CHX_PHY_CTRL14
// +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
#define SATA0_CHX_PHY_CTRL14_0                             0x000006DC                                                                       // RWW4R
#define SATA0_CHX_PHY_CTRL14_0_SECURE                      0
#define SATA0_CHX_PHY_CTRL14_0_WORD_COUNT                  1
#define SATA0_CHX_PHY_CTRL14_0_RESET_VAL                   0x0
#define SATA0_CHX_PHY_CTRL14_0_RESET_MASK                  0x0
#define SATA0_CHX_PHY_CTRL14_0_SW_DEFAULT_VAL              0x0
#define SATA0_CHX_PHY_CTRL14_0_SW_DEFAULT_MASK             0x0
#define SATA0_CHX_PHY_CTRL14_0_READ_MASK                   0xffffffff
#define SATA0_CHX_PHY_CTRL14_0_WRITE_MASK                  0xffffffff
#define SATA0_CHX_PHY_CTRL14_0_DFE_CNTL_GEN1_SHIFT          _MK_SHIFT_CONST(0)                                                              // RWCVF
#define SATA0_CHX_PHY_CTRL14_0_DFE_CNTL_GEN1_FIELD         (_MK_SHIFT_CONST(0xffffffff) << SATA0_CHX_PHY_CTRL14_0_DFE_CNTL_GEN1_SHIFT)
#define SATA0_CHX_PHY_CTRL14_0_DFE_CNTL_GEN1_RANGE         31:0
#define SATA0_CHX_PHY_CTRL14_0_DFE_CNTL_GEN1_WOFFSET       0
// 
// .LABEL PUBLIC
// 
// .LABEL PUBLIC
// .LABEL ANALOG_PRIVATE INT_REL
// .TITLE SATA PHY Control Register
// This register contains various bits to control the phy
// 
//  31           24 23           16 15            8 7             0
// .-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-.
// |0 0 0 0 0 0 0 0| | |   | | | | |   |   |0 0|   |0|     |0|     | CHX_PHY_CTRL15
// +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
// 
#define SATA0_CHX_PHY_CTRL15_0                             0x000006E0                                                                       // RWW4R
#define SATA0_CHX_PHY_CTRL15_0_SECURE                      0
#define SATA0_CHX_PHY_CTRL15_0_WORD_COUNT                  1
#define SATA0_CHX_PHY_CTRL15_0_RESET_VAL                   0x0
#define SATA0_CHX_PHY_CTRL15_0_RESET_MASK                  0x0
#define SATA0_CHX_PHY_CTRL15_0_SW_DEFAULT_VAL              0x0
#define SATA0_CHX_PHY_CTRL15_0_SW_DEFAULT_MASK             0x0
#define SATA0_CHX_PHY_CTRL15_0_READ_MASK                   0xffffff
#define SATA0_CHX_PHY_CTRL15_0_WRITE_MASK                  0xffffff
#define SATA0_CHX_PHY_CTRL15_0_TX_DRV_SLEW_GEN1_SHIFT       _MK_SHIFT_CONST(0)                                                              // RWCVF
#define SATA0_CHX_PHY_CTRL15_0_TX_DRV_SLEW_GEN1_FIELD      (_MK_SHIFT_CONST(0xf) << SATA0_CHX_PHY_CTRL15_0_TX_DRV_SLEW_GEN1_SHIFT)
#define SATA0_CHX_PHY_CTRL15_0_TX_DRV_SLEW_GEN1_RANGE      3:0
#define SATA0_CHX_PHY_CTRL15_0_TX_DRV_SLEW_GEN1_WOFFSET    0
#define SATA0_CHX_PHY_CTRL15_0_TX_DRV_SLEW_GEN2_SHIFT       _MK_SHIFT_CONST(4)                                                              // RWCVF
#define SATA0_CHX_PHY_CTRL15_0_TX_DRV_SLEW_GEN2_FIELD      (_MK_SHIFT_CONST(0xf) << SATA0_CHX_PHY_CTRL15_0_TX_DRV_SLEW_GEN2_SHIFT)
#define SATA0_CHX_PHY_CTRL15_0_TX_DRV_SLEW_GEN2_RANGE      7:4
#define SATA0_CHX_PHY_CTRL15_0_TX_DRV_SLEW_GEN2_WOFFSET    0
#define SATA0_CHX_PHY_CTRL15_0_TX_DRV_SLEW_GEN3_SHIFT       _MK_SHIFT_CONST(8)                                                              // RWCVF
#define SATA0_CHX_PHY_CTRL15_0_TX_DRV_SLEW_GEN3_FIELD      (_MK_SHIFT_CONST(0xf) << SATA0_CHX_PHY_CTRL15_0_TX_DRV_SLEW_GEN3_SHIFT)
#define SATA0_CHX_PHY_CTRL15_0_TX_DRV_SLEW_GEN3_RANGE      11:8
#define SATA0_CHX_PHY_CTRL15_0_TX_DRV_SLEW_GEN3_WOFFSET    0
#define SATA0_CHX_PHY_CTRL15_0_RX_FELS_GEN1_SHIFT           _MK_SHIFT_CONST(12)                                                             // RWCVF
#define SATA0_CHX_PHY_CTRL15_0_RX_FELS_GEN1_FIELD          (_MK_SHIFT_CONST(0xf) << SATA0_CHX_PHY_CTRL15_0_RX_FELS_GEN1_SHIFT)
#define SATA0_CHX_PHY_CTRL15_0_RX_FELS_GEN1_RANGE          15:12
#define SATA0_CHX_PHY_CTRL15_0_RX_FELS_GEN1_WOFFSET        0
#define SATA0_CHX_PHY_CTRL15_0_RX_FELS_GEN2_SHIFT           _MK_SHIFT_CONST(16)                                                             // RWCVF
#define SATA0_CHX_PHY_CTRL15_0_RX_FELS_GEN2_FIELD          (_MK_SHIFT_CONST(0xf) << SATA0_CHX_PHY_CTRL15_0_RX_FELS_GEN2_SHIFT)
#define SATA0_CHX_PHY_CTRL15_0_RX_FELS_GEN2_RANGE          19:16
#define SATA0_CHX_PHY_CTRL15_0_RX_FELS_GEN2_WOFFSET        0
#define SATA0_CHX_PHY_CTRL15_0_RX_FELS_GEN3_SHIFT           _MK_SHIFT_CONST(20)                                                             // RWCVF
#define SATA0_CHX_PHY_CTRL15_0_RX_FELS_GEN3_FIELD          (_MK_SHIFT_CONST(0xf) << SATA0_CHX_PHY_CTRL15_0_RX_FELS_GEN3_SHIFT)
#define SATA0_CHX_PHY_CTRL15_0_RX_FELS_GEN3_RANGE          23:20
#define SATA0_CHX_PHY_CTRL15_0_RX_FELS_GEN3_WOFFSET        0
// 
// 
// 
// 
// 
// 
// 
// 
// .LABEL PUBLIC
// .LABEL ANALOG_PRIVATE INT_REL
// .TITLE SATA PHY Control Register
// This register contains various bits to control the phy
// 
//  31           24 23           16 15            8 7             0
// .-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-.
// |0 0 0 0 0 0 0 0| | |   | | | | |   |   |0 0|   |0|     |0|     | CHX_PHY_CTRL16
// +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
// 
#define SATA0_CHX_PHY_CTRL16_0                             0x000006E4                                                                       // RWW4R
#define SATA0_CHX_PHY_CTRL16_0_SECURE                      0
#define SATA0_CHX_PHY_CTRL16_0_WORD_COUNT                  1
#define SATA0_CHX_PHY_CTRL16_0_RESET_VAL                   0x0
#define SATA0_CHX_PHY_CTRL16_0_RESET_MASK                  0x0
#define SATA0_CHX_PHY_CTRL16_0_SW_DEFAULT_VAL              0x0
#define SATA0_CHX_PHY_CTRL16_0_SW_DEFAULT_MASK             0x0
#define SATA0_CHX_PHY_CTRL16_0_READ_MASK                   0xffffff
#define SATA0_CHX_PHY_CTRL16_0_WRITE_MASK                  0xffffff
#define SATA0_CHX_PHY_CTRL16_0_RX_PI_CTRL_GEN1_SHIFT        _MK_SHIFT_CONST(0)                                                              // RWCVF
#define SATA0_CHX_PHY_CTRL16_0_RX_PI_CTRL_GEN1_FIELD       (_MK_SHIFT_CONST(0xff) << SATA0_CHX_PHY_CTRL16_0_RX_PI_CTRL_GEN1_SHIFT)
#define SATA0_CHX_PHY_CTRL16_0_RX_PI_CTRL_GEN1_RANGE       7:0
#define SATA0_CHX_PHY_CTRL16_0_RX_PI_CTRL_GEN1_WOFFSET     0
#define SATA0_CHX_PHY_CTRL16_0_RX_PI_CTRL_GEN2_SHIFT        _MK_SHIFT_CONST(8)                                                              // RWCVF
#define SATA0_CHX_PHY_CTRL16_0_RX_PI_CTRL_GEN2_FIELD       (_MK_SHIFT_CONST(0xff) << SATA0_CHX_PHY_CTRL16_0_RX_PI_CTRL_GEN2_SHIFT)
#define SATA0_CHX_PHY_CTRL16_0_RX_PI_CTRL_GEN2_RANGE       15:8
#define SATA0_CHX_PHY_CTRL16_0_RX_PI_CTRL_GEN2_WOFFSET     0
#define SATA0_CHX_PHY_CTRL16_0_RX_PI_CTRL_GEN3_SHIFT        _MK_SHIFT_CONST(16)                                                             // RWCVF
#define SATA0_CHX_PHY_CTRL16_0_RX_PI_CTRL_GEN3_FIELD       (_MK_SHIFT_CONST(0xff) << SATA0_CHX_PHY_CTRL16_0_RX_PI_CTRL_GEN3_SHIFT)
#define SATA0_CHX_PHY_CTRL16_0_RX_PI_CTRL_GEN3_RANGE       23:16
#define SATA0_CHX_PHY_CTRL16_0_RX_PI_CTRL_GEN3_WOFFSET     0
// 
// 
// 
// 
// 
// .LABEL PUBLIC
// .LABEL ANALOG_PRIVATE INT_REL
// .TITLE SATA PHY Control Register
// This register contains various bits to control the phy
// 
//  31           24 23           16 15            8 7             0
// .-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-.
// |0 0 0 0 0 0 0 0| | |   | | | | |   |   |0 0|   |0|     |0|     | CHX_PHY_CTRL17
// +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
// 
#define SATA0_CHX_PHY_CTRL17_0                             0x000006E8                                                                       // RWW4R
#define SATA0_CHX_PHY_CTRL17_0_SECURE                      0
#define SATA0_CHX_PHY_CTRL17_0_WORD_COUNT                  1
#define SATA0_CHX_PHY_CTRL17_0_RESET_VAL                   0x0
#define SATA0_CHX_PHY_CTRL17_0_RESET_MASK                  0x0
#define SATA0_CHX_PHY_CTRL17_0_SW_DEFAULT_VAL              0x0
#define SATA0_CHX_PHY_CTRL17_0_SW_DEFAULT_MASK             0x0
#define SATA0_CHX_PHY_CTRL17_0_READ_MASK                   0xffffffff
#define SATA0_CHX_PHY_CTRL17_0_WRITE_MASK                  0xffffffff
#define SATA0_CHX_PHY_CTRL17_0_RX_EQ_CTRL_L_GEN1_SHIFT      _MK_SHIFT_CONST(0)                                                              // RWCVF
#define SATA0_CHX_PHY_CTRL17_0_RX_EQ_CTRL_L_GEN1_FIELD     (_MK_SHIFT_CONST(0xffffffff) << SATA0_CHX_PHY_CTRL17_0_RX_EQ_CTRL_L_GEN1_SHIFT)
#define SATA0_CHX_PHY_CTRL17_0_RX_EQ_CTRL_L_GEN1_RANGE     31:0
#define SATA0_CHX_PHY_CTRL17_0_RX_EQ_CTRL_L_GEN1_WOFFSET   0
// 
// 
// 
// .LABEL PUBLIC
// .LABEL ANALOG_PRIVATE INT_REL
// .TITLE SATA PHY Control Register
// This register contains various bits to control the phy
// 
//  31           24 23           16 15            8 7             0
// .-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-.
// |0 0 0 0 0 0 0 0| | |   | | | | |   |   |0 0|   |0|     |0|     | CHX_PHY_CTRL18
// +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
// 
#define SATA0_CHX_PHY_CTRL18_0                             0x000006EC                                                                       // RWW4R
#define SATA0_CHX_PHY_CTRL18_0_SECURE                      0
#define SATA0_CHX_PHY_CTRL18_0_WORD_COUNT                  1
#define SATA0_CHX_PHY_CTRL18_0_RESET_VAL                   0x0
#define SATA0_CHX_PHY_CTRL18_0_RESET_MASK                  0x0
#define SATA0_CHX_PHY_CTRL18_0_SW_DEFAULT_VAL              0x0
#define SATA0_CHX_PHY_CTRL18_0_SW_DEFAULT_MASK             0x0
#define SATA0_CHX_PHY_CTRL18_0_READ_MASK                   0xffffffff
#define SATA0_CHX_PHY_CTRL18_0_WRITE_MASK                  0xffffffff
#define SATA0_CHX_PHY_CTRL18_0_RX_EQ_CTRL_L_GEN2_SHIFT      _MK_SHIFT_CONST(0)                                                              // RWCVF
#define SATA0_CHX_PHY_CTRL18_0_RX_EQ_CTRL_L_GEN2_FIELD     (_MK_SHIFT_CONST(0xffffffff) << SATA0_CHX_PHY_CTRL18_0_RX_EQ_CTRL_L_GEN2_SHIFT)
#define SATA0_CHX_PHY_CTRL18_0_RX_EQ_CTRL_L_GEN2_RANGE     31:0
#define SATA0_CHX_PHY_CTRL18_0_RX_EQ_CTRL_L_GEN2_WOFFSET   0
// 
// 
// 
// .LABEL PUBLIC
// .LABEL ANALOG_PRIVATE INT_REL
// .TITLE SATA PHY Control Register
// This register contains various bits to control the phy
// 
//  31           24 23           16 15            8 7             0
// .-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-.
// |0 0 0 0 0 0 0 0| | |   | | | | |   |   |0 0|   |0|     |0|     | CHX_PHY_CTRL19
// +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
// 
#define SATA0_CHX_PHY_CTRL19_0                             0x000006F0                                                                       // RWW4R
#define SATA0_CHX_PHY_CTRL19_0_SECURE                      0
#define SATA0_CHX_PHY_CTRL19_0_WORD_COUNT                  1
#define SATA0_CHX_PHY_CTRL19_0_RESET_VAL                   0x0
#define SATA0_CHX_PHY_CTRL19_0_RESET_MASK                  0x0
#define SATA0_CHX_PHY_CTRL19_0_SW_DEFAULT_VAL              0x0
#define SATA0_CHX_PHY_CTRL19_0_SW_DEFAULT_MASK             0x0
#define SATA0_CHX_PHY_CTRL19_0_READ_MASK                   0xffffffff
#define SATA0_CHX_PHY_CTRL19_0_WRITE_MASK                  0xffffffff
#define SATA0_CHX_PHY_CTRL19_0_RX_EQ_CTRL_L_GEN3_SHIFT      _MK_SHIFT_CONST(0)                                                              // RWCVF
#define SATA0_CHX_PHY_CTRL19_0_RX_EQ_CTRL_L_GEN3_FIELD     (_MK_SHIFT_CONST(0xffffffff) << SATA0_CHX_PHY_CTRL19_0_RX_EQ_CTRL_L_GEN3_SHIFT)
#define SATA0_CHX_PHY_CTRL19_0_RX_EQ_CTRL_L_GEN3_RANGE     31:0
#define SATA0_CHX_PHY_CTRL19_0_RX_EQ_CTRL_L_GEN3_WOFFSET   0
// 
// 
// 
// .LABEL PUBLIC
// .LABEL ANALOG_PRIVATE INT_REL
// .TITLE SATA PHY Control Register
// This register contains various bits to control the phy
// 
//  31           24 23           16 15            8 7             0
// .-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-.
// |0 0 0 0 0 0 0 0| | |   | | | | |   |   |0 0|   |0|     |0|     | CHX_PHY_CTRL20
// +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
// 
#define SATA0_CHX_PHY_CTRL20_0                             0x000006F4                                                                       // RWW4R
#define SATA0_CHX_PHY_CTRL20_0_SECURE                      0
#define SATA0_CHX_PHY_CTRL20_0_WORD_COUNT                  1
#define SATA0_CHX_PHY_CTRL20_0_RESET_VAL                   0x0
#define SATA0_CHX_PHY_CTRL20_0_RESET_MASK                  0x0
#define SATA0_CHX_PHY_CTRL20_0_SW_DEFAULT_VAL              0x0
#define SATA0_CHX_PHY_CTRL20_0_SW_DEFAULT_MASK             0x0
#define SATA0_CHX_PHY_CTRL20_0_READ_MASK                   0xffffffff
#define SATA0_CHX_PHY_CTRL20_0_WRITE_MASK                  0xffffffff
#define SATA0_CHX_PHY_CTRL20_0_RX_EQ_CTRL_H_GEN1_SHIFT      _MK_SHIFT_CONST(0)                                                              // RWCVF
#define SATA0_CHX_PHY_CTRL20_0_RX_EQ_CTRL_H_GEN1_FIELD     (_MK_SHIFT_CONST(0xffffffff) << SATA0_CHX_PHY_CTRL20_0_RX_EQ_CTRL_H_GEN1_SHIFT)
#define SATA0_CHX_PHY_CTRL20_0_RX_EQ_CTRL_H_GEN1_RANGE     31:0
#define SATA0_CHX_PHY_CTRL20_0_RX_EQ_CTRL_H_GEN1_WOFFSET   0
// 
// 
// 
// .LABEL PUBLIC
// .LABEL ANALOG_PRIVATE INT_REL
// .TITLE SATA PHY Control Register
// This register contains various bits to control the phy
// 
//  31           24 23           16 15            8 7             0
// .-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-.
// |0 0 0 0 0 0 0 0| | |   | | | | |   |   |0 0|   |0|     |0|     | CHX_PHY_CTRL21
// +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
// 
#define SATA0_CHX_PHY_CTRL21_0                             0x000006F8                                                                       // RWW4R
#define SATA0_CHX_PHY_CTRL21_0_SECURE                      0
#define SATA0_CHX_PHY_CTRL21_0_WORD_COUNT                  1
#define SATA0_CHX_PHY_CTRL21_0_RESET_VAL                   0x0
#define SATA0_CHX_PHY_CTRL21_0_RESET_MASK                  0x0
#define SATA0_CHX_PHY_CTRL21_0_SW_DEFAULT_VAL              0x0
#define SATA0_CHX_PHY_CTRL21_0_SW_DEFAULT_MASK             0x0
#define SATA0_CHX_PHY_CTRL21_0_READ_MASK                   0xffffffff
#define SATA0_CHX_PHY_CTRL21_0_WRITE_MASK                  0xffffffff
#define SATA0_CHX_PHY_CTRL21_0_RX_EQ_CTRL_H_GEN2_SHIFT      _MK_SHIFT_CONST(0)                                                              // RWCVF
#define SATA0_CHX_PHY_CTRL21_0_RX_EQ_CTRL_H_GEN2_FIELD     (_MK_SHIFT_CONST(0xffffffff) << SATA0_CHX_PHY_CTRL21_0_RX_EQ_CTRL_H_GEN2_SHIFT)
#define SATA0_CHX_PHY_CTRL21_0_RX_EQ_CTRL_H_GEN2_RANGE     31:0
#define SATA0_CHX_PHY_CTRL21_0_RX_EQ_CTRL_H_GEN2_WOFFSET   0
// 
// 
// 
// .LABEL PUBLIC
// .LABEL ANALOG_PRIVATE INT_REL
// .TITLE SATA PHY Control Register
// This register contains various bits to control the phy
// 
//  31           24 23           16 15            8 7             0
// .-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-.
// |0 0 0 0 0 0 0 0| | |   | | | | |   |   |0 0|   |0|     |0|     | CHX_PHY_CTRL22
// +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
// 
#define SATA0_CHX_PHY_CTRL22_0                             0x000006FC                                                                       // RWW4R
#define SATA0_CHX_PHY_CTRL22_0_SECURE                      0
#define SATA0_CHX_PHY_CTRL22_0_WORD_COUNT                  1
#define SATA0_CHX_PHY_CTRL22_0_RESET_VAL                   0x0
#define SATA0_CHX_PHY_CTRL22_0_RESET_MASK                  0x0
#define SATA0_CHX_PHY_CTRL22_0_SW_DEFAULT_VAL              0x0
#define SATA0_CHX_PHY_CTRL22_0_SW_DEFAULT_MASK             0x0
#define SATA0_CHX_PHY_CTRL22_0_READ_MASK                   0xffffffff
#define SATA0_CHX_PHY_CTRL22_0_WRITE_MASK                  0xffffffff
#define SATA0_CHX_PHY_CTRL22_0_RX_EQ_CTRL_H_GEN3_SHIFT      _MK_SHIFT_CONST(0)                                                              // RWCVF
#define SATA0_CHX_PHY_CTRL22_0_RX_EQ_CTRL_H_GEN3_FIELD     (_MK_SHIFT_CONST(0xffffffff) << SATA0_CHX_PHY_CTRL22_0_RX_EQ_CTRL_H_GEN3_SHIFT)
#define SATA0_CHX_PHY_CTRL22_0_RX_EQ_CTRL_H_GEN3_RANGE     31:0
#define SATA0_CHX_PHY_CTRL22_0_RX_EQ_CTRL_H_GEN3_WOFFSET   0
// 
// 
// 
// .LABEL DFT INT_REL
// 
//     This register is used to send the SATA bist activate command
// to the SATA device.  The bist code (byte) is loaded then a '1' is written to
// bit zero.
// 
//  31           24 23           16 15            8 7             0
// .-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-.
// |0 0 0 0 0 0 0 0|           |0| |0 0 0 0 0 0 0 0|           |0|    | CFG_26
// +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
// 
#define SATA0_CHXCFG3_0                                    0x00000700                                                                       // RWC4R
#define SATA0_CHXCFG3_0_SECURE                             0
#define SATA0_CHXCFG3_0_WORD_COUNT                         1
#define SATA0_CHXCFG3_0_RESET_VAL                          0x0
#define SATA0_CHXCFG3_0_RESET_MASK                         0x0
#define SATA0_CHXCFG3_0_SW_DEFAULT_VAL                     0x0
#define SATA0_CHXCFG3_0_SW_DEFAULT_MASK                    0x0
#define SATA0_CHXCFG3_0_READ_MASK                          0xffffff02
#define SATA0_CHXCFG3_0_WRITE_MASK                         0xff01
#define SATA0_CHXCFG3_0_CHX_BIST_SEND_SHIFT                 _MK_SHIFT_CONST(0)                                                              // -WCVF
#define SATA0_CHXCFG3_0_CHX_BIST_SEND_FIELD                (_MK_SHIFT_CONST(0x1) << SATA0_CHXCFG3_0_CHX_BIST_SEND_SHIFT)
#define SATA0_CHXCFG3_0_CHX_BIST_SEND_RANGE                0:0
#define SATA0_CHXCFG3_0_CHX_BIST_SEND_WOFFSET              0
#define SATA0_CHXCFG3_0_CHX_BIST_SEND_NOW                  _MK_ENUM_CONST(0x00000001)                                                       // -W--V
#define SATA0_CHXCFG3_0_CHX_BIST_SEND_INIT                 _MK_ENUM_CONST(0x00000000)                                                       // -WC-V
#define SATA0_CHXCFG3_0_CHX_BIST_STAT_SHIFT                 _MK_SHIFT_CONST(1)                                                              // R-CVF
#define SATA0_CHXCFG3_0_CHX_BIST_STAT_FIELD                (_MK_SHIFT_CONST(0x1) << SATA0_CHXCFG3_0_CHX_BIST_STAT_SHIFT)
#define SATA0_CHXCFG3_0_CHX_BIST_STAT_RANGE                1:1
#define SATA0_CHXCFG3_0_CHX_BIST_STAT_WOFFSET              0
#define SATA0_CHXCFG3_0_CHX_BIST_STAT_BUSY                 _MK_ENUM_CONST(0x00000001)                                                       // R---V
#define SATA0_CHXCFG3_0_CHX_BIST_STAT_NOT_BUSY             _MK_ENUM_CONST(0x00000000)                                                       // R-C-V
#define SATA0_CHXCFG3_0_CHX_BIST_CODE_SHIFT                 _MK_SHIFT_CONST(8)                                                              // RWCVF
#define SATA0_CHXCFG3_0_CHX_BIST_CODE_FIELD                (_MK_SHIFT_CONST(0xff) << SATA0_CHXCFG3_0_CHX_BIST_CODE_SHIFT)
#define SATA0_CHXCFG3_0_CHX_BIST_CODE_RANGE                15:8
#define SATA0_CHXCFG3_0_CHX_BIST_CODE_WOFFSET              0
#define SATA0_CHXCFG3_0_CHX_PRBS_ERROR_CNT_SHIFT            _MK_SHIFT_CONST(16)                                                             // R---F
#define SATA0_CHXCFG3_0_CHX_PRBS_ERROR_CNT_FIELD           (_MK_SHIFT_CONST(0xffff) << SATA0_CHXCFG3_0_CHX_PRBS_ERROR_CNT_SHIFT)
#define SATA0_CHXCFG3_0_CHX_PRBS_ERROR_CNT_RANGE           31:16
#define SATA0_CHXCFG3_0_CHX_PRBS_ERROR_CNT_WOFFSET         0
#define SATA0_CHXCFG3_0_CHX_PRBS_ERROR_CNT_0               _MK_ENUM_CONST(0x00000000)                                                       // R---V
// .LABEL PRIVATE INT_REL
// 
//         Figure 10-26  Serial ATA Control Register 6Ch
// .LABEL PUBLIC
// 
// 
// 
// .LABEL PERF_TUNING
// .LABEL PRIVATE INT_REL
// .TITLE CHXCFG4_CHX
// 
// .FIELD CHX_PHY_ALIGN_DWORD_CNT
// The PHY_ALIGN_DWORD_CNT field configures the number of DWORDs sent before the
// required (PHY_ALIGN_NUM_CNT + 1) number of ALIGN primitive pairs are inserted by the
// phy-interface block into the output stream. For example, the default PHY_ALIGN_DWORD_CNT
// setting of 254 and default PHY_ALIGN_NUM_CNT of 0 implies an output stream of
// 254 DWORDs, 2 ALIGNs, 254 DWORDs, 2 ALIGNs, and so on. To disable insertion of
// ALIGN primitives, set this field to zero.
// 
// .FIELD CHX_PHY_ALIGN_NUM_CNT
// The PHY_ALIGN_NUM_CNT field configures the number of ALIGN primitive pairs that are
// inserted by the phy interface block into the output stream. The field value
// represents a number which is one less than the number of ALIGN pairs to send.
// So, for eg, a value of 0 (default) would send 1 ALIGN pair (i.e 2 ALIGNs) every
// PHY_ALIGN_DWORD_CNT DWORDs. In other words, every PHY_ALIGN_DWORD_CNT DWORDs,
// the phy-interface sends out (PHY_ALIGN_NUM_CNT+1)*2 ALIGNs
// 
// .FIELD SW_COMWAKE_PI1_CH1
// This register is to be used by SW to manually issue addtional COMWAKE commands to be issued by
// SATA Controller to its connected phy devices.  This is a write only register and will always return
// a zero value when read.  For each value of 1 written to this register's bit a COMWAKE command is
// issued.  SW need not clear the written bit value as it is automatically clearly internally.
// A write of value 1 to bit 0 of this register forces a COMWAKE command to be issued from host to
// phy 1 channel 1 device.  For phy 1 channel 2 use bit # 1 and so on.
// .FIELD SW_COMWAKE_PI1_CH2
// 
//  31           24 23           16 15            8 7             0
// .-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-.
// |0 0 0 0|       |               |0 0 0 0|       |               | CHXCFG4_CHX
// +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
// 
#define SATA0_CHXCFG4_CHX_0                                0x00000704                                                                       // RWC4R
#define SATA0_CHXCFG4_CHX_0_SECURE                         0
#define SATA0_CHXCFG4_CHX_0_WORD_COUNT                     1
#define SATA0_CHXCFG4_CHX_0_RESET_VAL                      0x0
#define SATA0_CHXCFG4_CHX_0_RESET_MASK                     0x0
#define SATA0_CHXCFG4_CHX_0_SW_DEFAULT_VAL                 0x0
#define SATA0_CHXCFG4_CHX_0_SW_DEFAULT_MASK                0x0
#define SATA0_CHXCFG4_CHX_0_READ_MASK                      0x1fff
#define SATA0_CHXCFG4_CHX_0_WRITE_MASK                     0x1fff
#define SATA0_CHXCFG4_CHX_0_PHY_ALIGN_DWORD_CNT_SHIFT       _MK_SHIFT_CONST(0)                                                              // RWC-F
#define SATA0_CHXCFG4_CHX_0_PHY_ALIGN_DWORD_CNT_FIELD      (_MK_SHIFT_CONST(0xff) << SATA0_CHXCFG4_CHX_0_PHY_ALIGN_DWORD_CNT_SHIFT)
#define SATA0_CHXCFG4_CHX_0_PHY_ALIGN_DWORD_CNT_RANGE      7:0
#define SATA0_CHXCFG4_CHX_0_PHY_ALIGN_DWORD_CNT_WOFFSET    0
#define SATA0_CHXCFG4_CHX_0_PHY_ALIGN_DWORD_CNT__WRNPRDCHK _MK_ENUM_CONST(0x00000001)                                                       // ----V
#define SATA0_CHXCFG4_CHX_0_PHY_ALIGN_DWORD_CNT_INIT       _MK_ENUM_CONST(0x0000000A)                                                       // RWC-V
#define SATA0_CHXCFG4_CHX_0_PHY_ALIGN_NUM_CNT_SHIFT         _MK_SHIFT_CONST(8)                                                              // RWC-F
#define SATA0_CHXCFG4_CHX_0_PHY_ALIGN_NUM_CNT_FIELD        (_MK_SHIFT_CONST(0xf) << SATA0_CHXCFG4_CHX_0_PHY_ALIGN_NUM_CNT_SHIFT)
#define SATA0_CHXCFG4_CHX_0_PHY_ALIGN_NUM_CNT_RANGE        11:8
#define SATA0_CHXCFG4_CHX_0_PHY_ALIGN_NUM_CNT_WOFFSET      0
#define SATA0_CHXCFG4_CHX_0_PHY_ALIGN_NUM_CNT_INIT         _MK_ENUM_CONST(0x00000000)                                                       // RWC-V
#define SATA0_CHXCFG4_CHX_0_SW_COMWAKE_PI_SHIFT             _MK_SHIFT_CONST(12)                                                             // RWC-F
#define SATA0_CHXCFG4_CHX_0_SW_COMWAKE_PI_FIELD            (_MK_SHIFT_CONST(0x1) << SATA0_CHXCFG4_CHX_0_SW_COMWAKE_PI_SHIFT)
#define SATA0_CHXCFG4_CHX_0_SW_COMWAKE_PI_RANGE            12:12
#define SATA0_CHXCFG4_CHX_0_SW_COMWAKE_PI_WOFFSET          0
#define SATA0_CHXCFG4_CHX_0_SW_COMWAKE_PI_INIT             _MK_ENUM_CONST(0x00000000)                                                       // RWC-V
// 
// .LABEL PUBLIC
// 
// .LABEL ANALOG_PRIVATE INT_REL
// .TITLE PRBS_CHX
// This register contains control bits for the IOBIST PRBS generator
// and checker. Setting PI_LOOPBACK will select the PRBS as the TX data
// source. Setting PRBS_EN will cause the PRBS to start running.
// PRBS_SEED contains the 10-bit initial value for the PRBS.
// 
//  31           24 23           16 15            8 7             0
// .-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-.
// |                               | | |0| | | |                   | PRBS_CHX
// `-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-'
// 
#define SATA0_PRBS_CHX_0                                   0x00000714                                                                       // RWC4R
#define SATA0_PRBS_CHX_0_SECURE                            0
#define SATA0_PRBS_CHX_0_WORD_COUNT                        1
#define SATA0_PRBS_CHX_0_RESET_VAL                         0x0
#define SATA0_PRBS_CHX_0_RESET_MASK                        0x0
#define SATA0_PRBS_CHX_0_SW_DEFAULT_VAL                    0x0
#define SATA0_PRBS_CHX_0_SW_DEFAULT_MASK                   0x0
#define SATA0_PRBS_CHX_0_READ_MASK                         0xffffdfff
#define SATA0_PRBS_CHX_0_WRITE_MASK                        0x17ff
#define SATA0_PRBS_CHX_0_SEED_SHIFT                         _MK_SHIFT_CONST(0)                                                              // RWC-F
#define SATA0_PRBS_CHX_0_SEED_FIELD                        (_MK_SHIFT_CONST(0x3ff) << SATA0_PRBS_CHX_0_SEED_SHIFT)
#define SATA0_PRBS_CHX_0_SEED_RANGE                        9:0
#define SATA0_PRBS_CHX_0_SEED_WOFFSET                      0
#define SATA0_PRBS_CHX_0_SEED__WRNPRDCHK                   _MK_ENUM_CONST(0x00000001)                                                       // ----V
#define SATA0_PRBS_CHX_0_PI_LOOPBACK_SHIFT                  _MK_SHIFT_CONST(10)                                                             // RWC-F
#define SATA0_PRBS_CHX_0_PI_LOOPBACK_FIELD                 (_MK_SHIFT_CONST(0x1) << SATA0_PRBS_CHX_0_PI_LOOPBACK_SHIFT)
#define SATA0_PRBS_CHX_0_PI_LOOPBACK_RANGE                 10:10
#define SATA0_PRBS_CHX_0_PI_LOOPBACK_WOFFSET               0
#define SATA0_PRBS_CHX_0_RSVD_SHIFT                         _MK_SHIFT_CONST(11)                                                             // C--VF
#define SATA0_PRBS_CHX_0_RSVD_FIELD                        (_MK_SHIFT_CONST(0x1) << SATA0_PRBS_CHX_0_RSVD_SHIFT)
#define SATA0_PRBS_CHX_0_RSVD_RANGE                        11:11
#define SATA0_PRBS_CHX_0_RSVD_WOFFSET                      0
#define SATA0_PRBS_CHX_0_HOT_RESET_SHIFT                    _MK_SHIFT_CONST(12)                                                             // RWC-F
#define SATA0_PRBS_CHX_0_HOT_RESET_FIELD                   (_MK_SHIFT_CONST(0x1) << SATA0_PRBS_CHX_0_HOT_RESET_SHIFT)
#define SATA0_PRBS_CHX_0_HOT_RESET_RANGE                   12:12
#define SATA0_PRBS_CHX_0_HOT_RESET_WOFFSET                 0
#define SATA0_PRBS_CHX_0_HOT_RESET__WRNPRDCHK              _MK_ENUM_CONST(0x00000001)                                                       // ----V
#define SATA0_PRBS_CHX_0_ERROR_SHIFT                        _MK_SHIFT_CONST(14)                                                             // R---F
#define SATA0_PRBS_CHX_0_ERROR_FIELD                       (_MK_SHIFT_CONST(0x1) << SATA0_PRBS_CHX_0_ERROR_SHIFT)
#define SATA0_PRBS_CHX_0_ERROR_RANGE                       14:14
#define SATA0_PRBS_CHX_0_ERROR_WOFFSET                     0
#define SATA0_PRBS_CHX_0_LOCKED_SHIFT                       _MK_SHIFT_CONST(15)                                                             // R---F
#define SATA0_PRBS_CHX_0_LOCKED_FIELD                      (_MK_SHIFT_CONST(0x1) << SATA0_PRBS_CHX_0_LOCKED_SHIFT)
#define SATA0_PRBS_CHX_0_LOCKED_RANGE                      15:15
#define SATA0_PRBS_CHX_0_LOCKED_WOFFSET                    0
#define SATA0_PRBS_CHX_0_ERROR_COUNT_SHIFT                  _MK_SHIFT_CONST(16)                                                             // R---F
#define SATA0_PRBS_CHX_0_ERROR_COUNT_FIELD                 (_MK_SHIFT_CONST(0xffff) << SATA0_PRBS_CHX_0_ERROR_COUNT_SHIFT)
#define SATA0_PRBS_CHX_0_ERROR_COUNT_RANGE                 31:16
#define SATA0_PRBS_CHX_0_ERROR_COUNT_WOFFSET               0
// 
// .LABEL PUBLIC
// .LABEL ANALOG_PRIVATE INT_REL
// .TITLE SATA PHY Control Register
// This register contains various bits to control the phy
// 
//  31           24 23           16 15            8 7             0
// .-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-.
// |0 0 0 0 0 0 0 0| | |   | | | | |   |   |0 0|   |0|     |0|     | CHX_PHY_CTRL23
// +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
// 
#define SATA0_CHX_PHY_CTRL23_0                             0x00000718                                                                       // RWW4R
#define SATA0_CHX_PHY_CTRL23_0_SECURE                      0
#define SATA0_CHX_PHY_CTRL23_0_WORD_COUNT                  1
#define SATA0_CHX_PHY_CTRL23_0_RESET_VAL                   0x0
#define SATA0_CHX_PHY_CTRL23_0_RESET_MASK                  0x0
#define SATA0_CHX_PHY_CTRL23_0_SW_DEFAULT_VAL              0x0
#define SATA0_CHX_PHY_CTRL23_0_SW_DEFAULT_MASK             0x0
#define SATA0_CHX_PHY_CTRL23_0_READ_MASK                   0x1ffff
#define SATA0_CHX_PHY_CTRL23_0_WRITE_MASK                  0x0
#define SATA0_CHX_PHY_CTRL23_0_RX_EOM_STATUS_SHIFT          _MK_SHIFT_CONST(0)                                                              // R-CVF
#define SATA0_CHX_PHY_CTRL23_0_RX_EOM_STATUS_FIELD         (_MK_SHIFT_CONST(0xffff) << SATA0_CHX_PHY_CTRL23_0_RX_EOM_STATUS_SHIFT)
#define SATA0_CHX_PHY_CTRL23_0_RX_EOM_STATUS_RANGE         15:0
#define SATA0_CHX_PHY_CTRL23_0_RX_EOM_STATUS_WOFFSET       0
#define SATA0_CHX_PHY_CTRL23_0_RX_EOM_DONE_SHIFT            _MK_SHIFT_CONST(16)                                                             // R-CVF
#define SATA0_CHX_PHY_CTRL23_0_RX_EOM_DONE_FIELD           (_MK_SHIFT_CONST(0x1) << SATA0_CHX_PHY_CTRL23_0_RX_EOM_DONE_SHIFT)
#define SATA0_CHX_PHY_CTRL23_0_RX_EOM_DONE_RANGE           16:16
#define SATA0_CHX_PHY_CTRL23_0_RX_EOM_DONE_WOFFSET         0
// 
// 
// 
// 
// 
// 
//         Figure 10-28  Serial ATA Ch x IOBIST PRBS control register
// .LABEL PUBLIC INT_REL
// .TITLE CHX_LINK0
// .LABEL FUNC_BIOS
// .LABEL PRIVATE INT_REL
// .FIELD SCRAM_DIS
// SCRAM_DIS is used to disable data scrambling in the SATA Link layer. This bit
// is provided for each channel.
// 
// .FIELD CONT_DISABLE
// .LABEL CYA_PUBLIC
// CONT_DISABLE is used to disable using CONT primitive in the SATA tx. This bit
// is provided for each channel.
// 
// .LABEL INT_REL
// .FIELD LANE_IDDQ_ON_OFFLINE
// SW writes this bit for iddq
// 
//  31           24 23           16 15            8 7             0
// .-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-.
// |                               | | |0| | | |                   | CHX_LINK0
// `-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-'
#define SATA0_CHX_LINK0_0                                  0x00000750                                                                       // RWC4R
#define SATA0_CHX_LINK0_0_SECURE                           0
#define SATA0_CHX_LINK0_0_WORD_COUNT                       1
#define SATA0_CHX_LINK0_0_RESET_VAL                        0x0
#define SATA0_CHX_LINK0_0_RESET_MASK                       0x0
#define SATA0_CHX_LINK0_0_SW_DEFAULT_VAL                   0x0
#define SATA0_CHX_LINK0_0_SW_DEFAULT_MASK                  0x0
#define SATA0_CHX_LINK0_0_READ_MASK                        0xffffffff
#define SATA0_CHX_LINK0_0_WRITE_MASK                       0x7
#define SATA0_CHX_LINK0_0_SCRAM_DIS_SHIFT                   _MK_SHIFT_CONST(0)                                                              // RWCVF
#define SATA0_CHX_LINK0_0_SCRAM_DIS_FIELD                  (_MK_SHIFT_CONST(0x1) << SATA0_CHX_LINK0_0_SCRAM_DIS_SHIFT)
#define SATA0_CHX_LINK0_0_SCRAM_DIS_RANGE                  0:0
#define SATA0_CHX_LINK0_0_SCRAM_DIS_WOFFSET                0
#define SATA0_CHX_LINK0_0_SCRAM_DIS_NO                     _MK_ENUM_CONST(0x00000000)                                                       // RW--V
#define SATA0_CHX_LINK0_0_SCRAM_DIS_YES                    _MK_ENUM_CONST(0x00000001)                                                       // RW--V
#define SATA0_CHX_LINK0_0_CONT_DISABLE_SHIFT                _MK_SHIFT_CONST(1)                                                              // RWCVF
#define SATA0_CHX_LINK0_0_CONT_DISABLE_FIELD               (_MK_SHIFT_CONST(0x1) << SATA0_CHX_LINK0_0_CONT_DISABLE_SHIFT)
#define SATA0_CHX_LINK0_0_CONT_DISABLE_RANGE               1:1
#define SATA0_CHX_LINK0_0_CONT_DISABLE_WOFFSET             0
#define SATA0_CHX_LINK0_0_CONT_DISABLE_NO                  _MK_ENUM_CONST(0x00000000)                                                       // RW--V
#define SATA0_CHX_LINK0_0_CONT_DISABLE_YES                 _MK_ENUM_CONST(0x00000001)                                                       // RW--V
#define SATA0_CHX_LINK0_0_LANE_IDDQ_ON_OFFLINE_SHIFT        _MK_SHIFT_CONST(2)                                                              // RWCVF
#define SATA0_CHX_LINK0_0_LANE_IDDQ_ON_OFFLINE_FIELD       (_MK_SHIFT_CONST(0x1) << SATA0_CHX_LINK0_0_LANE_IDDQ_ON_OFFLINE_SHIFT)
#define SATA0_CHX_LINK0_0_LANE_IDDQ_ON_OFFLINE_RANGE       2:2
#define SATA0_CHX_LINK0_0_LANE_IDDQ_ON_OFFLINE_WOFFSET     0
#define SATA0_CHX_LINK0_0_LANE_IDDQ_ON_OFFLINE__WRNPRDCHK  _MK_ENUM_CONST(0x00000001)                                                       // ----V
#define SATA0_CHX_LINK0_0_LANE_IDDQ_ON_OFFLINE_YES         _MK_ENUM_CONST(0x00000001)                                                       // RWC-V
#define SATA0_CHX_LINK0_0_LANE_IDDQ_ON_OFFLINE_NO          _MK_ENUM_CONST(0x00000000)                                                       // RW--V
#define SATA0_CHX_LINK0_0_RSVD_0_SHIFT                      _MK_SHIFT_CONST(3)                                                              // C--VF
#define SATA0_CHX_LINK0_0_RSVD_0_FIELD                     (_MK_SHIFT_CONST(0x1fffffff) << SATA0_CHX_LINK0_0_RSVD_0_SHIFT)
#define SATA0_CHX_LINK0_0_RSVD_0_RANGE                     31:3
#define SATA0_CHX_LINK0_0_RSVD_0_WOFFSET                   0
#define SATA0_CHX_LINK0_0_RSVD_0_VAL                       _MK_ENUM_CONST(0x00000000)                                                       // C---V
// .LABEL FUNC_BIOS
// .LABEL PRIVATE INT_REL
// 
// .LABEL CYA_PUBLIC
// 
// .LABEL INT_REL
// 
// .LABEL PRIVATE INT_REL
// 
// 
// 
// .LABEL PUBLIC
// 
// .LABEL PUBLIC
// .LABEL PRIVATE INT_REL
// .TITLE CHX_AHCI_PORT_PXTFD_BKDR
// . This register is the backdoor register for PXTFD of the PSM registers
// . Used for the purpose of Power Ungating - SAVE and RESTORE vis BKDOOR
// . Need to write CHX_INDEX to select the channel specific register
//  31           24 23           16 15            8 7             0
// .-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-.
// |                               | | |0| | | |                   | CHX_AHCI_PORT_PXTFD_BKDR
// `-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-'
#define SATA0_CHX_AHCI_PORT_PXTFD_BKDR_0                   0x00000790                                                                       // RWW4R
#define SATA0_CHX_AHCI_PORT_PXTFD_BKDR_0_SECURE            0
#define SATA0_CHX_AHCI_PORT_PXTFD_BKDR_0_WORD_COUNT        1
#define SATA0_CHX_AHCI_PORT_PXTFD_BKDR_0_RESET_VAL         0x0
#define SATA0_CHX_AHCI_PORT_PXTFD_BKDR_0_RESET_MASK        0x0
#define SATA0_CHX_AHCI_PORT_PXTFD_BKDR_0_SW_DEFAULT_VAL    0x0
#define SATA0_CHX_AHCI_PORT_PXTFD_BKDR_0_SW_DEFAULT_MASK   0x0
#define SATA0_CHX_AHCI_PORT_PXTFD_BKDR_0_READ_MASK         0xffffffff
#define SATA0_CHX_AHCI_PORT_PXTFD_BKDR_0_WRITE_MASK        0xffff
#define SATA0_CHX_AHCI_PORT_PXTFD_BKDR_0_STS_ERR_SHIFT      _MK_SHIFT_CONST(0)                                                              // RWWVF
#define SATA0_CHX_AHCI_PORT_PXTFD_BKDR_0_STS_ERR_FIELD     (_MK_SHIFT_CONST(0x1) << SATA0_CHX_AHCI_PORT_PXTFD_BKDR_0_STS_ERR_SHIFT)
#define SATA0_CHX_AHCI_PORT_PXTFD_BKDR_0_STS_ERR_RANGE     0:0
#define SATA0_CHX_AHCI_PORT_PXTFD_BKDR_0_STS_ERR_WOFFSET   0
#define SATA0_CHX_AHCI_PORT_PXTFD_BKDR_0_STS_ERR_DEFAULT   (_MK_MASK_CONST(0x00000001)
#define SATA0_CHX_AHCI_PORT_PXTFD_BKDR_0_STS_ERR_DEFAULT_MASK (_MK_MASK_CONST(0x1)
#define SATA0_CHX_AHCI_PORT_PXTFD_BKDR_0_STS_ERR_SW_DEFAULT (_MK_MASK_CONST(0x00000001)
#define SATA0_CHX_AHCI_PORT_PXTFD_BKDR_0_STS_ERR_SW_DEFAULT_MASK (_MK_MASK_CONST(0x1)
#define SATA0_CHX_AHCI_PORT_PXTFD_BKDR_0_STS_ERR_CLEAR     _MK_ENUM_CONST(0x00000000)                                                       // RW--V
#define SATA0_CHX_AHCI_PORT_PXTFD_BKDR_0_STS_ERR_SET       _MK_ENUM_CONST(0x00000001)                                                       // RWW-V
#define SATA0_CHX_AHCI_PORT_PXTFD_BKDR_0_STS_2_1_SHIFT      _MK_SHIFT_CONST(1)                                                              // RWWVF
#define SATA0_CHX_AHCI_PORT_PXTFD_BKDR_0_STS_2_1_FIELD     (_MK_SHIFT_CONST(0x3) << SATA0_CHX_AHCI_PORT_PXTFD_BKDR_0_STS_2_1_SHIFT)
#define SATA0_CHX_AHCI_PORT_PXTFD_BKDR_0_STS_2_1_RANGE     2:1
#define SATA0_CHX_AHCI_PORT_PXTFD_BKDR_0_STS_2_1_WOFFSET   0
#define SATA0_CHX_AHCI_PORT_PXTFD_BKDR_0_STS_2_1_DEFAULT   (_MK_MASK_CONST(0x00000003)
#define SATA0_CHX_AHCI_PORT_PXTFD_BKDR_0_STS_2_1_DEFAULT_MASK (_MK_MASK_CONST(0x3)
#define SATA0_CHX_AHCI_PORT_PXTFD_BKDR_0_STS_2_1_SW_DEFAULT (_MK_MASK_CONST(0x00000003)
#define SATA0_CHX_AHCI_PORT_PXTFD_BKDR_0_STS_2_1_SW_DEFAULT_MASK (_MK_MASK_CONST(0x3)
#define SATA0_CHX_AHCI_PORT_PXTFD_BKDR_0_STS_2_1_INIT      _MK_ENUM_CONST(0x00000003)                                                       // RWW-V
#define SATA0_CHX_AHCI_PORT_PXTFD_BKDR_0_STS_DRQ_SHIFT      _MK_SHIFT_CONST(3)                                                              // RWWVF
#define SATA0_CHX_AHCI_PORT_PXTFD_BKDR_0_STS_DRQ_FIELD     (_MK_SHIFT_CONST(0x1) << SATA0_CHX_AHCI_PORT_PXTFD_BKDR_0_STS_DRQ_SHIFT)
#define SATA0_CHX_AHCI_PORT_PXTFD_BKDR_0_STS_DRQ_RANGE     3:3
#define SATA0_CHX_AHCI_PORT_PXTFD_BKDR_0_STS_DRQ_WOFFSET   0
#define SATA0_CHX_AHCI_PORT_PXTFD_BKDR_0_STS_DRQ_DEFAULT   (_MK_MASK_CONST(0x00000001)
#define SATA0_CHX_AHCI_PORT_PXTFD_BKDR_0_STS_DRQ_DEFAULT_MASK (_MK_MASK_CONST(0x1)
#define SATA0_CHX_AHCI_PORT_PXTFD_BKDR_0_STS_DRQ_SW_DEFAULT (_MK_MASK_CONST(0x00000001)
#define SATA0_CHX_AHCI_PORT_PXTFD_BKDR_0_STS_DRQ_SW_DEFAULT_MASK (_MK_MASK_CONST(0x1)
#define SATA0_CHX_AHCI_PORT_PXTFD_BKDR_0_STS_DRQ_CLEAR     _MK_ENUM_CONST(0x00000000)                                                       // RW--V
#define SATA0_CHX_AHCI_PORT_PXTFD_BKDR_0_STS_DRQ_SET       _MK_ENUM_CONST(0x00000001)                                                       // RWW-V
#define SATA0_CHX_AHCI_PORT_PXTFD_BKDR_0_STS_CS_SHIFT       _MK_SHIFT_CONST(4)                                                              // RWWVF
#define SATA0_CHX_AHCI_PORT_PXTFD_BKDR_0_STS_CS_FIELD      (_MK_SHIFT_CONST(0x1) << SATA0_CHX_AHCI_PORT_PXTFD_BKDR_0_STS_CS_SHIFT)
#define SATA0_CHX_AHCI_PORT_PXTFD_BKDR_0_STS_CS_RANGE      4:4
#define SATA0_CHX_AHCI_PORT_PXTFD_BKDR_0_STS_CS_WOFFSET    0
#define SATA0_CHX_AHCI_PORT_PXTFD_BKDR_0_STS_CS_DEFAULT    (_MK_MASK_CONST(0x00000001)
#define SATA0_CHX_AHCI_PORT_PXTFD_BKDR_0_STS_CS_DEFAULT_MASK (_MK_MASK_CONST(0x1)
#define SATA0_CHX_AHCI_PORT_PXTFD_BKDR_0_STS_CS_SW_DEFAULT (_MK_MASK_CONST(0x00000001)
#define SATA0_CHX_AHCI_PORT_PXTFD_BKDR_0_STS_CS_SW_DEFAULT_MASK (_MK_MASK_CONST(0x1)
#define SATA0_CHX_AHCI_PORT_PXTFD_BKDR_0_STS_CS_CLEAR      _MK_ENUM_CONST(0x00000000)                                                       // RW--V
#define SATA0_CHX_AHCI_PORT_PXTFD_BKDR_0_STS_CS_SET        _MK_ENUM_CONST(0x00000001)                                                       // RWW-V
#define SATA0_CHX_AHCI_PORT_PXTFD_BKDR_0_STS_DF_SHIFT       _MK_SHIFT_CONST(5)                                                              // RWWVF
#define SATA0_CHX_AHCI_PORT_PXTFD_BKDR_0_STS_DF_FIELD      (_MK_SHIFT_CONST(0x1) << SATA0_CHX_AHCI_PORT_PXTFD_BKDR_0_STS_DF_SHIFT)
#define SATA0_CHX_AHCI_PORT_PXTFD_BKDR_0_STS_DF_RANGE      5:5
#define SATA0_CHX_AHCI_PORT_PXTFD_BKDR_0_STS_DF_WOFFSET    0
#define SATA0_CHX_AHCI_PORT_PXTFD_BKDR_0_STS_DF_DEFAULT    (_MK_MASK_CONST(0x00000001)
#define SATA0_CHX_AHCI_PORT_PXTFD_BKDR_0_STS_DF_DEFAULT_MASK (_MK_MASK_CONST(0x1)
#define SATA0_CHX_AHCI_PORT_PXTFD_BKDR_0_STS_DF_SW_DEFAULT (_MK_MASK_CONST(0x00000001)
#define SATA0_CHX_AHCI_PORT_PXTFD_BKDR_0_STS_DF_SW_DEFAULT_MASK (_MK_MASK_CONST(0x1)
#define SATA0_CHX_AHCI_PORT_PXTFD_BKDR_0_STS_DF_CLEAR      _MK_ENUM_CONST(0x00000000)                                                       // RW--V
#define SATA0_CHX_AHCI_PORT_PXTFD_BKDR_0_STS_DF_SET        _MK_ENUM_CONST(0x00000001)                                                       // RWW-V
#define SATA0_CHX_AHCI_PORT_PXTFD_BKDR_0_STS_DRDY_SHIFT     _MK_SHIFT_CONST(6)                                                              // RWWVF
#define SATA0_CHX_AHCI_PORT_PXTFD_BKDR_0_STS_DRDY_FIELD    (_MK_SHIFT_CONST(0x1) << SATA0_CHX_AHCI_PORT_PXTFD_BKDR_0_STS_DRDY_SHIFT)
#define SATA0_CHX_AHCI_PORT_PXTFD_BKDR_0_STS_DRDY_RANGE    6:6
#define SATA0_CHX_AHCI_PORT_PXTFD_BKDR_0_STS_DRDY_WOFFSET  0
#define SATA0_CHX_AHCI_PORT_PXTFD_BKDR_0_STS_DRDY_DEFAULT  (_MK_MASK_CONST(0x00000001)
#define SATA0_CHX_AHCI_PORT_PXTFD_BKDR_0_STS_DRDY_DEFAULT_MASK (_MK_MASK_CONST(0x1)
#define SATA0_CHX_AHCI_PORT_PXTFD_BKDR_0_STS_DRDY_SW_DEFAULT (_MK_MASK_CONST(0x00000001)
#define SATA0_CHX_AHCI_PORT_PXTFD_BKDR_0_STS_DRDY_SW_DEFAULT_MASK (_MK_MASK_CONST(0x1)
#define SATA0_CHX_AHCI_PORT_PXTFD_BKDR_0_STS_DRDY_CLEAR    _MK_ENUM_CONST(0x00000000)                                                       // RW--V
#define SATA0_CHX_AHCI_PORT_PXTFD_BKDR_0_STS_DRDY_SET      _MK_ENUM_CONST(0x00000001)                                                       // RWW-V
#define SATA0_CHX_AHCI_PORT_PXTFD_BKDR_0_STS_BSY_SHIFT      _MK_SHIFT_CONST(7)                                                              // RWWVF
#define SATA0_CHX_AHCI_PORT_PXTFD_BKDR_0_STS_BSY_FIELD     (_MK_SHIFT_CONST(0x1) << SATA0_CHX_AHCI_PORT_PXTFD_BKDR_0_STS_BSY_SHIFT)
#define SATA0_CHX_AHCI_PORT_PXTFD_BKDR_0_STS_BSY_RANGE     7:7
#define SATA0_CHX_AHCI_PORT_PXTFD_BKDR_0_STS_BSY_WOFFSET   0
#define SATA0_CHX_AHCI_PORT_PXTFD_BKDR_0_STS_BSY_DEFAULT   (_MK_MASK_CONST(0x00000000)
#define SATA0_CHX_AHCI_PORT_PXTFD_BKDR_0_STS_BSY_DEFAULT_MASK (_MK_MASK_CONST(0x1)
#define SATA0_CHX_AHCI_PORT_PXTFD_BKDR_0_STS_BSY_SW_DEFAULT (_MK_MASK_CONST(0x00000000)
#define SATA0_CHX_AHCI_PORT_PXTFD_BKDR_0_STS_BSY_SW_DEFAULT_MASK (_MK_MASK_CONST(0x1)
#define SATA0_CHX_AHCI_PORT_PXTFD_BKDR_0_STS_BSY_CLEAR     _MK_ENUM_CONST(0x00000000)                                                       // RWW-V
#define SATA0_CHX_AHCI_PORT_PXTFD_BKDR_0_STS_BSY_SET       _MK_ENUM_CONST(0x00000001)                                                       // RW--V
#define SATA0_CHX_AHCI_PORT_PXTFD_BKDR_0_ERR_SHIFT          _MK_SHIFT_CONST(8)                                                              // RWCVF
#define SATA0_CHX_AHCI_PORT_PXTFD_BKDR_0_ERR_FIELD         (_MK_SHIFT_CONST(0xff) << SATA0_CHX_AHCI_PORT_PXTFD_BKDR_0_ERR_SHIFT)
#define SATA0_CHX_AHCI_PORT_PXTFD_BKDR_0_ERR_RANGE         15:8
#define SATA0_CHX_AHCI_PORT_PXTFD_BKDR_0_ERR_WOFFSET       0
#define SATA0_CHX_AHCI_PORT_PXTFD_BKDR_0_ERR_00            _MK_ENUM_CONST(0x00000000)                                                       // RWW-V
#define SATA0_CHX_AHCI_PORT_PXTFD_BKDR_0_RSVD_SHIFT         _MK_SHIFT_CONST(16)                                                             // C--VF
#define SATA0_CHX_AHCI_PORT_PXTFD_BKDR_0_RSVD_FIELD        (_MK_SHIFT_CONST(0xffff) << SATA0_CHX_AHCI_PORT_PXTFD_BKDR_0_RSVD_SHIFT)
#define SATA0_CHX_AHCI_PORT_PXTFD_BKDR_0_RSVD_RANGE        31:16
#define SATA0_CHX_AHCI_PORT_PXTFD_BKDR_0_RSVD_WOFFSET      0
#define SATA0_CHX_AHCI_PORT_PXTFD_BKDR_0_RSVD_00           _MK_ENUM_CONST(0x00000000)                                                       // C---V
// 
// 
// .LABEL PUBLIC
// 
// .LABEL PUBLIC
// .LABEL PRIVATE INT_REL
// .TITLE CHX_AHCI_PORT_PXSIG_BKDR
// This register is the backdoor register for PXSIG of the PSM registers.
// Used for the purpose of Power Ungating - SAVE and RESTORE vis BKDOOR.
// Need to write CHX_INDEX to select the channel specific register.
// 
//  31           24 23           16 15            8 7             0
// .-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-.
// |                               | | |0| | | |                   | CHX_AHCI_PORT_PXSIG_BKDR
// `-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-'
#define SATA0_CHX_AHCI_PORT_PXSIG_BKDR_0                   0x00000794                                                                       // RWW4R
#define SATA0_CHX_AHCI_PORT_PXSIG_BKDR_0_SECURE            0
#define SATA0_CHX_AHCI_PORT_PXSIG_BKDR_0_WORD_COUNT        1
#define SATA0_CHX_AHCI_PORT_PXSIG_BKDR_0_RESET_VAL         0x0
#define SATA0_CHX_AHCI_PORT_PXSIG_BKDR_0_RESET_MASK        0x0
#define SATA0_CHX_AHCI_PORT_PXSIG_BKDR_0_SW_DEFAULT_VAL    0x0
#define SATA0_CHX_AHCI_PORT_PXSIG_BKDR_0_SW_DEFAULT_MASK   0x0
#define SATA0_CHX_AHCI_PORT_PXSIG_BKDR_0_READ_MASK         0xffffffff
#define SATA0_CHX_AHCI_PORT_PXSIG_BKDR_0_WRITE_MASK        0xffffffff
#define SATA0_CHX_AHCI_PORT_PXSIG_BKDR_0_SECTOR_CNT_SHIFT   _MK_SHIFT_CONST(0)                                                              // RWWVF
#define SATA0_CHX_AHCI_PORT_PXSIG_BKDR_0_SECTOR_CNT_FIELD  (_MK_SHIFT_CONST(0xff) << SATA0_CHX_AHCI_PORT_PXSIG_BKDR_0_SECTOR_CNT_SHIFT)
#define SATA0_CHX_AHCI_PORT_PXSIG_BKDR_0_SECTOR_CNT_RANGE  7:0
#define SATA0_CHX_AHCI_PORT_PXSIG_BKDR_0_SECTOR_CNT_WOFFSET 0
#define SATA0_CHX_AHCI_PORT_PXSIG_BKDR_0_SECTOR_CNT_DEFAULT (_MK_MASK_CONST(0x000000FF)
#define SATA0_CHX_AHCI_PORT_PXSIG_BKDR_0_SECTOR_CNT_DEFAULT_MASK (_MK_MASK_CONST(0xff)
#define SATA0_CHX_AHCI_PORT_PXSIG_BKDR_0_SECTOR_CNT_SW_DEFAULT (_MK_MASK_CONST(0x000000FF)
#define SATA0_CHX_AHCI_PORT_PXSIG_BKDR_0_SECTOR_CNT_SW_DEFAULT_MASK (_MK_MASK_CONST(0xff)
#define SATA0_CHX_AHCI_PORT_PXSIG_BKDR_0_SECTOR_CNT_INIT   _MK_ENUM_CONST(0x000000FF)                                                       // RWW-V
#define SATA0_CHX_AHCI_PORT_PXSIG_BKDR_0_SECTOR_CNT_00     _MK_ENUM_CONST(0x00000000)                                                       // RW--V
#define SATA0_CHX_AHCI_PORT_PXSIG_BKDR_0_LBA_LOW_SHIFT      _MK_SHIFT_CONST(8)                                                              // RWWVF
#define SATA0_CHX_AHCI_PORT_PXSIG_BKDR_0_LBA_LOW_FIELD     (_MK_SHIFT_CONST(0xff) << SATA0_CHX_AHCI_PORT_PXSIG_BKDR_0_LBA_LOW_SHIFT)
#define SATA0_CHX_AHCI_PORT_PXSIG_BKDR_0_LBA_LOW_RANGE     15:8
#define SATA0_CHX_AHCI_PORT_PXSIG_BKDR_0_LBA_LOW_WOFFSET   0
#define SATA0_CHX_AHCI_PORT_PXSIG_BKDR_0_LBA_LOW_DEFAULT   (_MK_MASK_CONST(0x000000FF)
#define SATA0_CHX_AHCI_PORT_PXSIG_BKDR_0_LBA_LOW_DEFAULT_MASK (_MK_MASK_CONST(0xff)
#define SATA0_CHX_AHCI_PORT_PXSIG_BKDR_0_LBA_LOW_SW_DEFAULT (_MK_MASK_CONST(0x000000FF)
#define SATA0_CHX_AHCI_PORT_PXSIG_BKDR_0_LBA_LOW_SW_DEFAULT_MASK (_MK_MASK_CONST(0xff)
#define SATA0_CHX_AHCI_PORT_PXSIG_BKDR_0_LBA_LOW_INIT      _MK_ENUM_CONST(0x000000FF)                                                       // RWW-V
#define SATA0_CHX_AHCI_PORT_PXSIG_BKDR_0_LBA_LOW_00        _MK_ENUM_CONST(0x00000000)                                                       // RW--V
#define SATA0_CHX_AHCI_PORT_PXSIG_BKDR_0_LBA_MID_SHIFT      _MK_SHIFT_CONST(16)                                                             // RWWVF
#define SATA0_CHX_AHCI_PORT_PXSIG_BKDR_0_LBA_MID_FIELD     (_MK_SHIFT_CONST(0xff) << SATA0_CHX_AHCI_PORT_PXSIG_BKDR_0_LBA_MID_SHIFT)
#define SATA0_CHX_AHCI_PORT_PXSIG_BKDR_0_LBA_MID_RANGE     23:16
#define SATA0_CHX_AHCI_PORT_PXSIG_BKDR_0_LBA_MID_WOFFSET   0
#define SATA0_CHX_AHCI_PORT_PXSIG_BKDR_0_LBA_MID_DEFAULT   (_MK_MASK_CONST(0x000000FF)
#define SATA0_CHX_AHCI_PORT_PXSIG_BKDR_0_LBA_MID_DEFAULT_MASK (_MK_MASK_CONST(0xff)
#define SATA0_CHX_AHCI_PORT_PXSIG_BKDR_0_LBA_MID_SW_DEFAULT (_MK_MASK_CONST(0x000000FF)
#define SATA0_CHX_AHCI_PORT_PXSIG_BKDR_0_LBA_MID_SW_DEFAULT_MASK (_MK_MASK_CONST(0xff)
#define SATA0_CHX_AHCI_PORT_PXSIG_BKDR_0_LBA_MID_INIT      _MK_ENUM_CONST(0x000000FF)                                                       // RWW-V
#define SATA0_CHX_AHCI_PORT_PXSIG_BKDR_0_LBA_MID_00        _MK_ENUM_CONST(0x00000000)                                                       // RW--V
#define SATA0_CHX_AHCI_PORT_PXSIG_BKDR_0_LBA_HIGH_SHIFT     _MK_SHIFT_CONST(24)                                                             // RWWVF
#define SATA0_CHX_AHCI_PORT_PXSIG_BKDR_0_LBA_HIGH_FIELD    (_MK_SHIFT_CONST(0xff) << SATA0_CHX_AHCI_PORT_PXSIG_BKDR_0_LBA_HIGH_SHIFT)
#define SATA0_CHX_AHCI_PORT_PXSIG_BKDR_0_LBA_HIGH_RANGE    31:24
#define SATA0_CHX_AHCI_PORT_PXSIG_BKDR_0_LBA_HIGH_WOFFSET  0
#define SATA0_CHX_AHCI_PORT_PXSIG_BKDR_0_LBA_HIGH_DEFAULT  (_MK_MASK_CONST(0x000000FF)
#define SATA0_CHX_AHCI_PORT_PXSIG_BKDR_0_LBA_HIGH_DEFAULT_MASK (_MK_MASK_CONST(0xff)
#define SATA0_CHX_AHCI_PORT_PXSIG_BKDR_0_LBA_HIGH_SW_DEFAULT (_MK_MASK_CONST(0x000000FF)
#define SATA0_CHX_AHCI_PORT_PXSIG_BKDR_0_LBA_HIGH_SW_DEFAULT_MASK (_MK_MASK_CONST(0xff)
#define SATA0_CHX_AHCI_PORT_PXSIG_BKDR_0_LBA_HIGH_INIT     _MK_ENUM_CONST(0x000000FF)                                                       // RWW-V
#define SATA0_CHX_AHCI_PORT_PXSIG_BKDR_0_LBA_HIGH_00       _MK_ENUM_CONST(0x00000000)                                                       // RW--V
// 
// 
// .LABEL PUBLIC
// 
// .LABEL PUBLIC
// .LABEL PRIVATE INT_REL
// .TITLE CHX_AHCI_PORT_PXSSTS_BKDR
// This register is the backdoor register for PXSSTS_SPD of the PSM registers.
// Only STS_DPD is restored by SW, else will be driven by the HW.
// Used for the purpose of Power Ungating - SAVE and RESTORE vis BKDOOR.
// Need to write CHX_INDEX to select the channel specific register.
// 
//  31           24 23           16 15            8 7             0
// .-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-.
// |                               | | |0| | | |                   | CHX_AHCI_PORT_PXSSTS_BKDR
// `-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-'
#define SATA0_CHX_AHCI_PORT_PXSSTS_BKDR_0                  0x00000798                                                                       // RWW4R
#define SATA0_CHX_AHCI_PORT_PXSSTS_BKDR_0_SECURE           0
#define SATA0_CHX_AHCI_PORT_PXSSTS_BKDR_0_WORD_COUNT       1
#define SATA0_CHX_AHCI_PORT_PXSSTS_BKDR_0_RESET_VAL        0x0
#define SATA0_CHX_AHCI_PORT_PXSSTS_BKDR_0_RESET_MASK       0x0
#define SATA0_CHX_AHCI_PORT_PXSSTS_BKDR_0_SW_DEFAULT_VAL   0x0
#define SATA0_CHX_AHCI_PORT_PXSSTS_BKDR_0_SW_DEFAULT_MASK  0x0
#define SATA0_CHX_AHCI_PORT_PXSSTS_BKDR_0_READ_MASK        0xffffffff
#define SATA0_CHX_AHCI_PORT_PXSSTS_BKDR_0_WRITE_MASK       0xfff
#define SATA0_CHX_AHCI_PORT_PXSSTS_BKDR_0_DET_SHIFT         _MK_SHIFT_CONST(0)                                                              // RWWVF
#define SATA0_CHX_AHCI_PORT_PXSSTS_BKDR_0_DET_FIELD        (_MK_SHIFT_CONST(0xf) << SATA0_CHX_AHCI_PORT_PXSSTS_BKDR_0_DET_SHIFT)
#define SATA0_CHX_AHCI_PORT_PXSSTS_BKDR_0_DET_RANGE        3:0
#define SATA0_CHX_AHCI_PORT_PXSSTS_BKDR_0_DET_WOFFSET      0
#define SATA0_CHX_AHCI_PORT_PXSSTS_BKDR_0_DET_DEFAULT      (_MK_MASK_CONST(0x00000000)
#define SATA0_CHX_AHCI_PORT_PXSSTS_BKDR_0_DET_DEFAULT_MASK (_MK_MASK_CONST(0xf)
#define SATA0_CHX_AHCI_PORT_PXSSTS_BKDR_0_DET_SW_DEFAULT   (_MK_MASK_CONST(0x00000000)
#define SATA0_CHX_AHCI_PORT_PXSSTS_BKDR_0_DET_SW_DEFAULT_MASK (_MK_MASK_CONST(0xf)
#define SATA0_CHX_AHCI_PORT_PXSSTS_BKDR_0_DET_NO_DEV       _MK_ENUM_CONST(0x00000000)                                                       // RWW-V
#define SATA0_CHX_AHCI_PORT_PXSSTS_BKDR_0_SPD_SHIFT         _MK_SHIFT_CONST(4)                                                              // RWWVF
#define SATA0_CHX_AHCI_PORT_PXSSTS_BKDR_0_SPD_FIELD        (_MK_SHIFT_CONST(0xf) << SATA0_CHX_AHCI_PORT_PXSSTS_BKDR_0_SPD_SHIFT)
#define SATA0_CHX_AHCI_PORT_PXSSTS_BKDR_0_SPD_RANGE        7:4
#define SATA0_CHX_AHCI_PORT_PXSSTS_BKDR_0_SPD_WOFFSET      0
#define SATA0_CHX_AHCI_PORT_PXSSTS_BKDR_0_SPD_DEFAULT      (_MK_MASK_CONST(0x00000000)
#define SATA0_CHX_AHCI_PORT_PXSSTS_BKDR_0_SPD_DEFAULT_MASK (_MK_MASK_CONST(0xf)
#define SATA0_CHX_AHCI_PORT_PXSSTS_BKDR_0_SPD_SW_DEFAULT   (_MK_MASK_CONST(0x00000000)
#define SATA0_CHX_AHCI_PORT_PXSSTS_BKDR_0_SPD_SW_DEFAULT_MASK (_MK_MASK_CONST(0xf)
#define SATA0_CHX_AHCI_PORT_PXSSTS_BKDR_0_SPD_NO_DEV       _MK_ENUM_CONST(0x00000000)                                                       // RWW-V
#define SATA0_CHX_AHCI_PORT_PXSSTS_BKDR_0_SPD_GEN1         _MK_ENUM_CONST(0x00000001)                                                       // RW--V
#define SATA0_CHX_AHCI_PORT_PXSSTS_BKDR_0_SPD_GEN2         _MK_ENUM_CONST(0x00000002)                                                       // RW--V
#define SATA0_CHX_AHCI_PORT_PXSSTS_BKDR_0_SPD_GEN3         _MK_ENUM_CONST(0x00000003)                                                       // RW--V
#define SATA0_CHX_AHCI_PORT_PXSSTS_BKDR_0_IPM_SHIFT         _MK_SHIFT_CONST(8)                                                              // RWWVF
#define SATA0_CHX_AHCI_PORT_PXSSTS_BKDR_0_IPM_FIELD        (_MK_SHIFT_CONST(0xf) << SATA0_CHX_AHCI_PORT_PXSSTS_BKDR_0_IPM_SHIFT)
#define SATA0_CHX_AHCI_PORT_PXSSTS_BKDR_0_IPM_RANGE        11:8
#define SATA0_CHX_AHCI_PORT_PXSSTS_BKDR_0_IPM_WOFFSET      0
#define SATA0_CHX_AHCI_PORT_PXSSTS_BKDR_0_IPM_DEFAULT      (_MK_MASK_CONST(0x00000000)
#define SATA0_CHX_AHCI_PORT_PXSSTS_BKDR_0_IPM_DEFAULT_MASK (_MK_MASK_CONST(0xf)
#define SATA0_CHX_AHCI_PORT_PXSSTS_BKDR_0_IPM_SW_DEFAULT   (_MK_MASK_CONST(0x00000000)
#define SATA0_CHX_AHCI_PORT_PXSSTS_BKDR_0_IPM_SW_DEFAULT_MASK (_MK_MASK_CONST(0xf)
#define SATA0_CHX_AHCI_PORT_PXSSTS_BKDR_0_IPM_NO_DEV       _MK_ENUM_CONST(0x00000000)                                                       // RWW-V
#define SATA0_CHX_AHCI_PORT_PXSSTS_BKDR_0_IPM_DEVSLEEP     _MK_ENUM_CONST(0x00000008)                                                       // RW--V
#define SATA0_CHX_AHCI_PORT_PXSSTS_BKDR_0_IPM_SLUMBER      _MK_ENUM_CONST(0x00000006)                                                       // RW--V
#define SATA0_CHX_AHCI_PORT_PXSSTS_BKDR_0_RSVD_31_12_SHIFT  _MK_SHIFT_CONST(12)                                                             // C--VF
#define SATA0_CHX_AHCI_PORT_PXSSTS_BKDR_0_RSVD_31_12_FIELD (_MK_SHIFT_CONST(0xfffff) << SATA0_CHX_AHCI_PORT_PXSSTS_BKDR_0_RSVD_31_12_SHIFT)
#define SATA0_CHX_AHCI_PORT_PXSSTS_BKDR_0_RSVD_31_12_RANGE 31:12
#define SATA0_CHX_AHCI_PORT_PXSSTS_BKDR_0_RSVD_31_12_WOFFSET 0
#define SATA0_CHX_AHCI_PORT_PXSSTS_BKDR_0_RSVD_31_12_VAL   _MK_ENUM_CONST(0x00000000)                                                       // C---V
// 
// .LABEL PUBLIC
// 
// 
// 
// 
// .LABEL PRIVATE INT_REL
// .TITLE CHX_GLUE
// .FIELD ATAPI_BLINK_EN
// qualifier for led_active signal
// 31           24 23           16 15            8 7             0
// .-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-.
// |0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0| CHX_GLUE
// `-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-'
// .LABEL PRIVATE INT_REL
#define SATA0_CHX_GLUE_0                                   0x000007F0                                                                       // RWC4R
#define SATA0_CHX_GLUE_0_SECURE                            0
#define SATA0_CHX_GLUE_0_WORD_COUNT                        1
#define SATA0_CHX_GLUE_0_RESET_VAL                         0x0
#define SATA0_CHX_GLUE_0_RESET_MASK                        0x0
#define SATA0_CHX_GLUE_0_SW_DEFAULT_VAL                    0x0
#define SATA0_CHX_GLUE_0_SW_DEFAULT_MASK                   0x0
#define SATA0_CHX_GLUE_0_READ_MASK                         0xffffffff
#define SATA0_CHX_GLUE_0_WRITE_MASK                        0x1
#define SATA0_CHX_GLUE_0_ATAPI_BLINK_EN_SHIFT               _MK_SHIFT_CONST(0)                                                              // RWC-F
#define SATA0_CHX_GLUE_0_ATAPI_BLINK_EN_FIELD              (_MK_SHIFT_CONST(0x1) << SATA0_CHX_GLUE_0_ATAPI_BLINK_EN_SHIFT)
#define SATA0_CHX_GLUE_0_ATAPI_BLINK_EN_RANGE              0:0
#define SATA0_CHX_GLUE_0_ATAPI_BLINK_EN_WOFFSET            0
#define SATA0_CHX_GLUE_0_ATAPI_BLINK_EN_0                  _MK_ENUM_CONST(0x00000000)                                                       // RW--V
#define SATA0_CHX_GLUE_0_ATAPI_BLINK_EN_1                  _MK_ENUM_CONST(0x00000001)                                                       // RW--V
#define SATA0_CHX_GLUE_0_RSVD_0_SHIFT                       _MK_SHIFT_CONST(1)                                                              // C--VF
#define SATA0_CHX_GLUE_0_RSVD_0_FIELD                      (_MK_SHIFT_CONST(0x7fffffff) << SATA0_CHX_GLUE_0_RSVD_0_SHIFT)
#define SATA0_CHX_GLUE_0_RSVD_0_RANGE                      31:1
#define SATA0_CHX_GLUE_0_RSVD_0_WOFFSET                    0
#define SATA0_CHX_GLUE_0_RSVD_0_VAL                        _MK_ENUM_CONST(0x00000000)                                                       // C---V
// 
// 
// .LABEL PUBLIC
// ###########################################################################################
//     2K to 3K - Debug registers. We can add readouts of various state machines, counters,
//                address pointers etc.
//     0X7D0 - 0XBB4
// ###########################################################################################
// .LABEL DEBUG_BUS
// 
// .LABEL PRIVATE
// 
//   The T_SATA0_CFG_44 register is used to select which signals are
// muxed onto the debug bus. The debug bus crossbar is generated by
// mk_debug_logic.pl. The bus consists of 4 bundles of 8 bits. See
// T_SATA0_dbg.vx/T_SATA_dbg.cfg for details.
// 
// 
//  31           24 23           16 15            8 7             0
// .-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-.
// |0 0 0 0|                                                       | SATA_DBG_31_0
// +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
// 
#define SATA0_DBG_31_0_0                                   0x00000800                                                                       // RW-4R
#define SATA0_DBG_31_0_0_SECURE                            0
#define SATA0_DBG_31_0_0_WORD_COUNT                        1
#define SATA0_DBG_31_0_0_RESET_VAL                         0x0
#define SATA0_DBG_31_0_0_RESET_MASK                        0x0
#define SATA0_DBG_31_0_0_SW_DEFAULT_VAL                    0x0
#define SATA0_DBG_31_0_0_SW_DEFAULT_MASK                   0x0
#define SATA0_DBG_31_0_0_READ_MASK                         0xffffffff
#define SATA0_DBG_31_0_0_WRITE_MASK                        0xffffffff
#define SATA0_DBG_31_0_0_SEL_SHIFT                          _MK_SHIFT_CONST(0)                                                              // RWCVF
#define SATA0_DBG_31_0_0_SEL_FIELD                         (_MK_SHIFT_CONST(0xffffffff) << SATA0_DBG_31_0_0_SEL_SHIFT)
#define SATA0_DBG_31_0_0_SEL_RANGE                         31:0
#define SATA0_DBG_31_0_0_SEL_WOFFSET                       0
#define SATA0_DBG_31_0_0_SEL_INIT                          _MK_ENUM_CONST(0x00000000)                                                       // RWC-V
// 
//         Figure 10-44  Serial ATA DBG Sel register
// 
// 
// .LABEL PRIVATE
// .TITLE AHCI Debug register 63:32
// This register was put here becuase of lack of space in AHCI vendor specific register space.
// 
// .BUS_SEL
// 
// 31           24 23           16 15            8 7             0
// .-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-.
// |0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0| SATA_DBG_63_32
// `-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-'
// 
#define SATA0_DBG_63_32_0                                  0x00000804                                                                       // RW-4R
#define SATA0_DBG_63_32_0_SECURE                           0
#define SATA0_DBG_63_32_0_WORD_COUNT                       1
#define SATA0_DBG_63_32_0_RESET_VAL                        0x0
#define SATA0_DBG_63_32_0_RESET_MASK                       0x0
#define SATA0_DBG_63_32_0_SW_DEFAULT_VAL                   0x0
#define SATA0_DBG_63_32_0_SW_DEFAULT_MASK                  0x0
#define SATA0_DBG_63_32_0_READ_MASK                        0xffffffff
#define SATA0_DBG_63_32_0_WRITE_MASK                       0xffffffff
#define SATA0_DBG_63_32_0_SEL_SHIFT                         _MK_SHIFT_CONST(0)                                                              // RWCVF
#define SATA0_DBG_63_32_0_SEL_FIELD                        (_MK_SHIFT_CONST(0xffffffff) << SATA0_DBG_63_32_0_SEL_SHIFT)
#define SATA0_DBG_63_32_0_SEL_RANGE                        31:0
#define SATA0_DBG_63_32_0_SEL_WOFFSET                      0
#define SATA0_DBG_63_32_0_SEL_INIT                         _MK_ENUM_CONST(0x00000000)                                                       // RWC-V
// 
// .LABEL PRIVATE
// .TITLE AHCI Debug register 95:64
// This register was put here becuase of lack of space in AHCI vendor specific register space.
// 
// .BUS_SEL
// 
// 31           24 23           16 15            8 7             0
// .-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-.
// |0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0| SATA_DBG_95_64
// `-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-'
// 
#define SATA0_DBG_95_64_0                                  0x00000808                                                                       // RW-4R
#define SATA0_DBG_95_64_0_SECURE                           0
#define SATA0_DBG_95_64_0_WORD_COUNT                       1
#define SATA0_DBG_95_64_0_RESET_VAL                        0x0
#define SATA0_DBG_95_64_0_RESET_MASK                       0x0
#define SATA0_DBG_95_64_0_SW_DEFAULT_VAL                   0x0
#define SATA0_DBG_95_64_0_SW_DEFAULT_MASK                  0x0
#define SATA0_DBG_95_64_0_READ_MASK                        0xffffffff
#define SATA0_DBG_95_64_0_WRITE_MASK                       0xffffffff
#define SATA0_DBG_95_64_0_SEL_SHIFT                         _MK_SHIFT_CONST(0)                                                              // RWCVF
#define SATA0_DBG_95_64_0_SEL_FIELD                        (_MK_SHIFT_CONST(0xffffffff) << SATA0_DBG_95_64_0_SEL_SHIFT)
#define SATA0_DBG_95_64_0_SEL_RANGE                        31:0
#define SATA0_DBG_95_64_0_SEL_WOFFSET                      0
#define SATA0_DBG_95_64_0_SEL_INIT                         _MK_ENUM_CONST(0x00000000)                                                       // RWC-V
// 
// .LABEL PRIVATE
// .TITLE AHCI Debug register 127:96
// This register was put here becuase of lack of space in AHCI vendor specific register space.
// 
// .BUS_SEL
// 
// 31           24 23           16 15            8 7             0
// .-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-.
// |0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0| SATA_DBG_127_96
// `-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-'
// 
#define SATA0_DBG_127_96_0                                 0x0000080C                                                                       // RW-4R
#define SATA0_DBG_127_96_0_SECURE                          0
#define SATA0_DBG_127_96_0_WORD_COUNT                      1
#define SATA0_DBG_127_96_0_RESET_VAL                       0x0
#define SATA0_DBG_127_96_0_RESET_MASK                      0x0
#define SATA0_DBG_127_96_0_SW_DEFAULT_VAL                  0x0
#define SATA0_DBG_127_96_0_SW_DEFAULT_MASK                 0x0
#define SATA0_DBG_127_96_0_READ_MASK                       0xffffffff
#define SATA0_DBG_127_96_0_WRITE_MASK                      0xffffffff
#define SATA0_DBG_127_96_0_SEL_SHIFT                        _MK_SHIFT_CONST(0)                                                              // RWCVF
#define SATA0_DBG_127_96_0_SEL_FIELD                       (_MK_SHIFT_CONST(0xffffffff) << SATA0_DBG_127_96_0_SEL_SHIFT)
#define SATA0_DBG_127_96_0_SEL_RANGE                       31:0
#define SATA0_DBG_127_96_0_SEL_WOFFSET                     0
#define SATA0_DBG_127_96_0_SEL_INIT                        _MK_ENUM_CONST(0x00000000)                                                       // RWC-V
// 
// .LABEL PRIVATE
// .TITLE AHCI Debug register 159:128
// This register was put here becuase of lack of space in AHCI vendor specific register space.
// 
// .BUS_SEL
// 
// 31           24 23           16 15            8 7             0
// .-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-.
// |0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0| SATA_DBG_159_128
// `-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-'
// 
#define SATA0_DBG_CH_SELECT_0                              0x00000810                                                                       // RW-4R
#define SATA0_DBG_CH_SELECT_0_SECURE                       0
#define SATA0_DBG_CH_SELECT_0_WORD_COUNT                   1
#define SATA0_DBG_CH_SELECT_0_RESET_VAL                    0x0
#define SATA0_DBG_CH_SELECT_0_RESET_MASK                   0x0
#define SATA0_DBG_CH_SELECT_0_SW_DEFAULT_VAL               0x0
#define SATA0_DBG_CH_SELECT_0_SW_DEFAULT_MASK              0x0
#define SATA0_DBG_CH_SELECT_0_READ_MASK                    0xffffffff
#define SATA0_DBG_CH_SELECT_0_WRITE_MASK                   0x7
#define SATA0_DBG_CH_SELECT_0_SEL_SHIFT                     _MK_SHIFT_CONST(0)                                                              // RWCVF
#define SATA0_DBG_CH_SELECT_0_SEL_FIELD                    (_MK_SHIFT_CONST(0x3) << SATA0_DBG_CH_SELECT_0_SEL_SHIFT)
#define SATA0_DBG_CH_SELECT_0_SEL_RANGE                    1:0
#define SATA0_DBG_CH_SELECT_0_SEL_WOFFSET                  0
#define SATA0_DBG_CH_SELECT_0_SEL_INIT                     _MK_ENUM_CONST(0x00000000)                                                       // RWC-V
#define SATA0_DBG_CH_SELECT_0_PRIMARY_SHIFT                 _MK_SHIFT_CONST(2)                                                              // RWCVF
#define SATA0_DBG_CH_SELECT_0_PRIMARY_FIELD                (_MK_SHIFT_CONST(0x1) << SATA0_DBG_CH_SELECT_0_PRIMARY_SHIFT)
#define SATA0_DBG_CH_SELECT_0_PRIMARY_RANGE                2:2
#define SATA0_DBG_CH_SELECT_0_PRIMARY_WOFFSET              0
#define SATA0_DBG_CH_SELECT_0_PRIMARY_INIT                 _MK_ENUM_CONST(0x00000001)                                                       // RWC-V
#define SATA0_DBG_CH_SELECT_0_RSVD_SHIFT                    _MK_SHIFT_CONST(3)                                                              // C--VF
#define SATA0_DBG_CH_SELECT_0_RSVD_FIELD                   (_MK_SHIFT_CONST(0x1fffffff) << SATA0_DBG_CH_SELECT_0_RSVD_SHIFT)
#define SATA0_DBG_CH_SELECT_0_RSVD_RANGE                   31:3
#define SATA0_DBG_CH_SELECT_0_RSVD_WOFFSET                 0
#define SATA0_DBG_CH_SELECT_0_RSVD_VAL                     _MK_ENUM_CONST(0x00000000)                                                       // C---V
// 
// 
// 
// .LABEL PRIVATE
// .TITLE AHCI Debug Register 31:0
// This register will be used to select the SATA debug bus mux
// 
// 31           24 23           16 15            8 7             0
// .-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-.
// |0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0| AHCI_DBG_31_0
// `-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-'
#define SATA0_AHCI_DBG_31_0_0                              0x00000820                                                                       // RWC4R
#define SATA0_AHCI_DBG_31_0_0_SECURE                       0
#define SATA0_AHCI_DBG_31_0_0_WORD_COUNT                   1
#define SATA0_AHCI_DBG_31_0_0_RESET_VAL                    0x0
#define SATA0_AHCI_DBG_31_0_0_RESET_MASK                   0x0
#define SATA0_AHCI_DBG_31_0_0_SW_DEFAULT_VAL               0x0
#define SATA0_AHCI_DBG_31_0_0_SW_DEFAULT_MASK              0x0
#define SATA0_AHCI_DBG_31_0_0_READ_MASK                    0xffffffff
#define SATA0_AHCI_DBG_31_0_0_WRITE_MASK                   0xffffffff
#define SATA0_AHCI_DBG_31_0_0_SEL_SHIFT                     _MK_SHIFT_CONST(0)                                                              // RWCVF
#define SATA0_AHCI_DBG_31_0_0_SEL_FIELD                    (_MK_SHIFT_CONST(0xffffffff) << SATA0_AHCI_DBG_31_0_0_SEL_SHIFT)
#define SATA0_AHCI_DBG_31_0_0_SEL_RANGE                    31:0
#define SATA0_AHCI_DBG_31_0_0_SEL_WOFFSET                  0
#define SATA0_AHCI_DBG_31_0_0_SEL_INIT                     _MK_ENUM_CONST(0x00000000)                                                       // RWC-V
// 
// 31           24 23           16 15            8 7             0
// .-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-.
// |0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0| AHCI_DBG_63_32
// `-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-'
// 
#define SATA0_AHCI_DBG_63_32_0                             0x00000824                                                                       // RWC4R
#define SATA0_AHCI_DBG_63_32_0_SECURE                      0
#define SATA0_AHCI_DBG_63_32_0_WORD_COUNT                  1
#define SATA0_AHCI_DBG_63_32_0_RESET_VAL                   0x0
#define SATA0_AHCI_DBG_63_32_0_RESET_MASK                  0x0
#define SATA0_AHCI_DBG_63_32_0_SW_DEFAULT_VAL              0x0
#define SATA0_AHCI_DBG_63_32_0_SW_DEFAULT_MASK             0x0
#define SATA0_AHCI_DBG_63_32_0_READ_MASK                   0xffffffff
#define SATA0_AHCI_DBG_63_32_0_WRITE_MASK                  0xffffffff
#define SATA0_AHCI_DBG_63_32_0_SEL_SHIFT                    _MK_SHIFT_CONST(0)                                                              // RWCVF
#define SATA0_AHCI_DBG_63_32_0_SEL_FIELD                   (_MK_SHIFT_CONST(0xffffffff) << SATA0_AHCI_DBG_63_32_0_SEL_SHIFT)
#define SATA0_AHCI_DBG_63_32_0_SEL_RANGE                   31:0
#define SATA0_AHCI_DBG_63_32_0_SEL_WOFFSET                 0
#define SATA0_AHCI_DBG_63_32_0_SEL_INIT                    _MK_ENUM_CONST(0x00000000)                                                       // RWC-V
// 
// 31           24 23           16 15            8 7             0
// .-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-.
// |0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0| AHCI_DBG_95_64
// `-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-'
#define SATA0_AHCI_DBG_95_64_0                             0x00000828                                                                       // RWC4R
#define SATA0_AHCI_DBG_95_64_0_SECURE                      0
#define SATA0_AHCI_DBG_95_64_0_WORD_COUNT                  1
#define SATA0_AHCI_DBG_95_64_0_RESET_VAL                   0x0
#define SATA0_AHCI_DBG_95_64_0_RESET_MASK                  0x0
#define SATA0_AHCI_DBG_95_64_0_SW_DEFAULT_VAL              0x0
#define SATA0_AHCI_DBG_95_64_0_SW_DEFAULT_MASK             0x0
#define SATA0_AHCI_DBG_95_64_0_READ_MASK                   0xffffffff
#define SATA0_AHCI_DBG_95_64_0_WRITE_MASK                  0xffffffff
#define SATA0_AHCI_DBG_95_64_0_SEL_SHIFT                    _MK_SHIFT_CONST(0)                                                              // RWCVF
#define SATA0_AHCI_DBG_95_64_0_SEL_FIELD                   (_MK_SHIFT_CONST(0xffffffff) << SATA0_AHCI_DBG_95_64_0_SEL_SHIFT)
#define SATA0_AHCI_DBG_95_64_0_SEL_RANGE                   31:0
#define SATA0_AHCI_DBG_95_64_0_SEL_WOFFSET                 0
#define SATA0_AHCI_DBG_95_64_0_SEL_INIT                    _MK_ENUM_CONST(0x00000000)                                                       // RWC-V
// 
// // #ifdef SATA0_CTRLR
// // #ifndef UNIT_SATA_EMULATION
// 
// .LABEL PRIVATE
// Counter to track 8b10b error on a selected channel. Writing enable to zero will clear
// the count.
// 31           24 23           16 15            8 7             0
// .-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-.
// |0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0| PHY_DBG_0
// `-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-'
#define SATA0_PHY_DBG_0_0                                  0x00000830                                                                       // RWC4R
#define SATA0_PHY_DBG_0_0_SECURE                           0
#define SATA0_PHY_DBG_0_0_WORD_COUNT                       1
#define SATA0_PHY_DBG_0_0_RESET_VAL                        0x0
#define SATA0_PHY_DBG_0_0_RESET_MASK                       0x0
#define SATA0_PHY_DBG_0_0_SW_DEFAULT_VAL                   0x0
#define SATA0_PHY_DBG_0_0_SW_DEFAULT_MASK                  0x0
#define SATA0_PHY_DBG_0_0_READ_MASK                        0x7ffff
#define SATA0_PHY_DBG_0_0_WRITE_MASK                       0x70000
#define SATA0_PHY_DBG_0_0_8B10B_ERR_COUNT_SHIFT             _MK_SHIFT_CONST(0)                                                              // R--VF
#define SATA0_PHY_DBG_0_0_8B10B_ERR_COUNT_FIELD            (_MK_SHIFT_CONST(0xffff) << SATA0_PHY_DBG_0_0_8B10B_ERR_COUNT_SHIFT)
#define SATA0_PHY_DBG_0_0_8B10B_ERR_COUNT_RANGE            15:0
#define SATA0_PHY_DBG_0_0_8B10B_ERR_COUNT_WOFFSET          0
#define SATA0_PHY_DBG_0_0_8B10B_ERR_COUNT_CH_SEL_SHIFT      _MK_SHIFT_CONST(16)                                                             // RWCVF
#define SATA0_PHY_DBG_0_0_8B10B_ERR_COUNT_CH_SEL_FIELD     (_MK_SHIFT_CONST(0x3) << SATA0_PHY_DBG_0_0_8B10B_ERR_COUNT_CH_SEL_SHIFT)
#define SATA0_PHY_DBG_0_0_8B10B_ERR_COUNT_CH_SEL_RANGE     17:16
#define SATA0_PHY_DBG_0_0_8B10B_ERR_COUNT_CH_SEL_WOFFSET   0
#define SATA0_PHY_DBG_0_0_8B10B_ERR_COUNT_CH_SEL_INIT      _MK_ENUM_CONST(0x00000000)                                                       // RWC-V
#define SATA0_PHY_DBG_0_0_8B10B_ERR_COUNT_EN_SHIFT          _MK_SHIFT_CONST(18)                                                             // RWCVF
#define SATA0_PHY_DBG_0_0_8B10B_ERR_COUNT_EN_FIELD         (_MK_SHIFT_CONST(0x1) << SATA0_PHY_DBG_0_0_8B10B_ERR_COUNT_EN_SHIFT)
#define SATA0_PHY_DBG_0_0_8B10B_ERR_COUNT_EN_RANGE         18:18
#define SATA0_PHY_DBG_0_0_8B10B_ERR_COUNT_EN_WOFFSET       0
#define SATA0_PHY_DBG_0_0_8B10B_ERR_COUNT_EN_INIT          _MK_ENUM_CONST(0x00000000)                                                       // RWC-V
// 
// .LABEL PRIVATE
// Counter to track LPM transitions. this is primarily used in debug to see if we are
// doing the required transitions.
// 
// 31           24 23           16 15            8 7             0
// .-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-.
// |0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0| PHY_LPM_TRACKER_CTRL
// `-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-'
#define SATA0_PHY_LPM_TRACKER_CTRL_0                       0x00000834                                                                       // RWC4R
#define SATA0_PHY_LPM_TRACKER_CTRL_0_SECURE                0
#define SATA0_PHY_LPM_TRACKER_CTRL_0_WORD_COUNT            1
#define SATA0_PHY_LPM_TRACKER_CTRL_0_RESET_VAL             0x0
#define SATA0_PHY_LPM_TRACKER_CTRL_0_RESET_MASK            0x0
#define SATA0_PHY_LPM_TRACKER_CTRL_0_SW_DEFAULT_VAL        0x0
#define SATA0_PHY_LPM_TRACKER_CTRL_0_SW_DEFAULT_MASK       0x0
#define SATA0_PHY_LPM_TRACKER_CTRL_0_READ_MASK             0x13
#define SATA0_PHY_LPM_TRACKER_CTRL_0_WRITE_MASK            0x13
#define SATA0_PHY_LPM_TRACKER_CTRL_0_PORT_SEL_SHIFT         _MK_SHIFT_CONST(0)                                                              // RWCVF
#define SATA0_PHY_LPM_TRACKER_CTRL_0_PORT_SEL_FIELD        (_MK_SHIFT_CONST(0x3) << SATA0_PHY_LPM_TRACKER_CTRL_0_PORT_SEL_SHIFT)
#define SATA0_PHY_LPM_TRACKER_CTRL_0_PORT_SEL_RANGE        1:0
#define SATA0_PHY_LPM_TRACKER_CTRL_0_PORT_SEL_WOFFSET      0
#define SATA0_PHY_LPM_TRACKER_CTRL_0_PORT_SEL_INIT         _MK_ENUM_CONST(0x00000000)                                                       // RWC-V
#define SATA0_PHY_LPM_TRACKER_CTRL_0_COUNT_EN_SHIFT         _MK_SHIFT_CONST(4)                                                              // RWCVF
#define SATA0_PHY_LPM_TRACKER_CTRL_0_COUNT_EN_FIELD        (_MK_SHIFT_CONST(0x1) << SATA0_PHY_LPM_TRACKER_CTRL_0_COUNT_EN_SHIFT)
#define SATA0_PHY_LPM_TRACKER_CTRL_0_COUNT_EN_RANGE        4:4
#define SATA0_PHY_LPM_TRACKER_CTRL_0_COUNT_EN_WOFFSET      0
#define SATA0_PHY_LPM_TRACKER_CTRL_0_COUNT_EN_INIT         _MK_ENUM_CONST(0x00000000)                                                       // RWC-V
// 
// 31           24 23           16 15            8 7             0
// .-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-.
// |0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0| PHY_LPM_TRACKER_COUNT
// `-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-'
#define SATA0_PHY_LPM_TRACKER_COUNT_0                      0x00000838                                                                       // R--4R
#define SATA0_PHY_LPM_TRACKER_COUNT_0_SECURE               0
#define SATA0_PHY_LPM_TRACKER_COUNT_0_WORD_COUNT           1
#define SATA0_PHY_LPM_TRACKER_COUNT_0_RESET_VAL            0x0
#define SATA0_PHY_LPM_TRACKER_COUNT_0_RESET_MASK           0x0
#define SATA0_PHY_LPM_TRACKER_COUNT_0_SW_DEFAULT_VAL       0x0
#define SATA0_PHY_LPM_TRACKER_COUNT_0_SW_DEFAULT_MASK      0x0
#define SATA0_PHY_LPM_TRACKER_COUNT_0_READ_MASK            0xffffffff
#define SATA0_PHY_LPM_TRACKER_COUNT_0_WRITE_MASK           0x0
#define SATA0_PHY_LPM_TRACKER_COUNT_0_DIPM_PARTIAL_SHIFT    _MK_SHIFT_CONST(0)                                                              // R--VF
#define SATA0_PHY_LPM_TRACKER_COUNT_0_DIPM_PARTIAL_FIELD   (_MK_SHIFT_CONST(0xff) << SATA0_PHY_LPM_TRACKER_COUNT_0_DIPM_PARTIAL_SHIFT)
#define SATA0_PHY_LPM_TRACKER_COUNT_0_DIPM_PARTIAL_RANGE   7:0
#define SATA0_PHY_LPM_TRACKER_COUNT_0_DIPM_PARTIAL_WOFFSET 0
#define SATA0_PHY_LPM_TRACKER_COUNT_0_DIPM_SLUMBER_SHIFT    _MK_SHIFT_CONST(8)                                                              // R--VF
#define SATA0_PHY_LPM_TRACKER_COUNT_0_DIPM_SLUMBER_FIELD   (_MK_SHIFT_CONST(0xff) << SATA0_PHY_LPM_TRACKER_COUNT_0_DIPM_SLUMBER_SHIFT)
#define SATA0_PHY_LPM_TRACKER_COUNT_0_DIPM_SLUMBER_RANGE   15:8
#define SATA0_PHY_LPM_TRACKER_COUNT_0_DIPM_SLUMBER_WOFFSET 0
#define SATA0_PHY_LPM_TRACKER_COUNT_0_HIPM_PARTIAL_SHIFT    _MK_SHIFT_CONST(16)                                                             // R--VF
#define SATA0_PHY_LPM_TRACKER_COUNT_0_HIPM_PARTIAL_FIELD   (_MK_SHIFT_CONST(0xff) << SATA0_PHY_LPM_TRACKER_COUNT_0_HIPM_PARTIAL_SHIFT)
#define SATA0_PHY_LPM_TRACKER_COUNT_0_HIPM_PARTIAL_RANGE   23:16
#define SATA0_PHY_LPM_TRACKER_COUNT_0_HIPM_PARTIAL_WOFFSET 0
#define SATA0_PHY_LPM_TRACKER_COUNT_0_HIPM_SLUMBER_SHIFT    _MK_SHIFT_CONST(24)                                                             // R--VF
#define SATA0_PHY_LPM_TRACKER_COUNT_0_HIPM_SLUMBER_FIELD   (_MK_SHIFT_CONST(0xff) << SATA0_PHY_LPM_TRACKER_COUNT_0_HIPM_SLUMBER_SHIFT)
#define SATA0_PHY_LPM_TRACKER_COUNT_0_HIPM_SLUMBER_RANGE   31:24
#define SATA0_PHY_LPM_TRACKER_COUNT_0_HIPM_SLUMBER_WOFFSET 0
// 
// 31           24 23           16 15            8 7             0
// .-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-.
// |0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0| FBS_DBG_0
// `-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-'
#define SATA0_AHCI_FBS_DBG_0_0                             0x00000910                                                                       // RWC4R
#define SATA0_AHCI_FBS_DBG_0_0_SECURE                      0
#define SATA0_AHCI_FBS_DBG_0_0_WORD_COUNT                  1
#define SATA0_AHCI_FBS_DBG_0_0_RESET_VAL                   0x0
#define SATA0_AHCI_FBS_DBG_0_0_RESET_MASK                  0x0
#define SATA0_AHCI_FBS_DBG_0_0_SW_DEFAULT_VAL              0x0
#define SATA0_AHCI_FBS_DBG_0_0_SW_DEFAULT_MASK             0x0
#define SATA0_AHCI_FBS_DBG_0_0_READ_MASK                   0x3ff
#define SATA0_AHCI_FBS_DBG_0_0_WRITE_MASK                  0x3ff
#define SATA0_AHCI_FBS_DBG_0_0_PMP_SEL_0_SHIFT              _MK_SHIFT_CONST(0)                                                              // RWXVF
#define SATA0_AHCI_FBS_DBG_0_0_PMP_SEL_0_FIELD             (_MK_SHIFT_CONST(0xf) << SATA0_AHCI_FBS_DBG_0_0_PMP_SEL_0_SHIFT)
#define SATA0_AHCI_FBS_DBG_0_0_PMP_SEL_0_RANGE             3:0
#define SATA0_AHCI_FBS_DBG_0_0_PMP_SEL_0_WOFFSET           0
#define SATA0_AHCI_FBS_DBG_0_0_PMP_SEL_1_SHIFT              _MK_SHIFT_CONST(4)                                                              // RWXVF
#define SATA0_AHCI_FBS_DBG_0_0_PMP_SEL_1_FIELD             (_MK_SHIFT_CONST(0xf) << SATA0_AHCI_FBS_DBG_0_0_PMP_SEL_1_SHIFT)
#define SATA0_AHCI_FBS_DBG_0_0_PMP_SEL_1_RANGE             7:4
#define SATA0_AHCI_FBS_DBG_0_0_PMP_SEL_1_WOFFSET           0
#define SATA0_AHCI_FBS_DBG_0_0_PMP_MUXSEL_SHIFT             _MK_SHIFT_CONST(8)                                                              // RWXVF
#define SATA0_AHCI_FBS_DBG_0_0_PMP_MUXSEL_FIELD            (_MK_SHIFT_CONST(0x3) << SATA0_AHCI_FBS_DBG_0_0_PMP_MUXSEL_SHIFT)
#define SATA0_AHCI_FBS_DBG_0_0_PMP_MUXSEL_RANGE            9:8
#define SATA0_AHCI_FBS_DBG_0_0_PMP_MUXSEL_WOFFSET          0
// 
// .LABEL DEBUG_BUS
// 
// .LABEL PRIVATE
// Registers CFG_31, CFG_32, CFG_33 and CFG_34 are debug registers used
// to get the status of DMA engines in SATA controller through software
// means while DMA is in progress. Through these registers, it can be
// determined to what memory address SATA is DMAing to, what is byte
// count of data to be transfered and current pointer in PRD table.
// First two registers are for Primary channel and last two are for
// secondary channel.
// 
// 
// .TITLE PCI Configuration Register 84h
// Registers CFG_31, is a debug register used to get the status of DMA engines
// in SATA controller through software means while DMA is in progress.
// Through this register, it can be determined to what memory address SATA is DMAing to.
// This register is for Primary channel.
// 
// 
// 
//  31           24 23           16 15            8 7             0
// .-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-.
// |                                                               | BM0
// +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
#define SATA0_BM0_0                                        0x000009D0                                                                       // R--4R
#define SATA0_BM0_0_SECURE                                 0
#define SATA0_BM0_0_WORD_COUNT                             1
#define SATA0_BM0_0_RESET_VAL                              0x0
#define SATA0_BM0_0_RESET_MASK                             0x0
#define SATA0_BM0_0_SW_DEFAULT_VAL                         0x0
#define SATA0_BM0_0_SW_DEFAULT_MASK                        0x0
#define SATA0_BM0_0_READ_MASK                              0xffffffff
#define SATA0_BM0_0_WRITE_MASK                             0x0
#define SATA0_BM0_0_DBG_CHX_BM_ADDRESS_SHIFT                _MK_SHIFT_CONST(0)                                                              // R--VF
#define SATA0_BM0_0_DBG_CHX_BM_ADDRESS_FIELD               (_MK_SHIFT_CONST(0xffffffff) << SATA0_BM0_0_DBG_CHX_BM_ADDRESS_SHIFT)
#define SATA0_BM0_0_DBG_CHX_BM_ADDRESS_RANGE               31:0
#define SATA0_BM0_0_DBG_CHX_BM_ADDRESS_WOFFSET             0
#define SATA0_BM0_0_DBG_CHX_BM_ADDRESS_0                   _MK_ENUM_CONST(0x00000000)                                                       // R---V
// Warning: unsupported define: #define T_SATA0_BM0__NO_CHECK                                0x0 /*       */
// 
// 
#define SATA0_BM1_0                                        0x000009D4                                                                       // R--4R
#define SATA0_BM1_0_SECURE                                 0
#define SATA0_BM1_0_WORD_COUNT                             1
#define SATA0_BM1_0_RESET_VAL                              0x0
#define SATA0_BM1_0_RESET_MASK                             0x0
#define SATA0_BM1_0_SW_DEFAULT_VAL                         0x0
#define SATA0_BM1_0_SW_DEFAULT_MASK                        0x0
#define SATA0_BM1_0_READ_MASK                              0xffffffff
#define SATA0_BM1_0_WRITE_MASK                             0x0
#define SATA0_BM1_0_REG_SHIFT                               _MK_SHIFT_CONST(0)                                                              // R--VF
#define SATA0_BM1_0_REG_FIELD                              (_MK_SHIFT_CONST(0xffffffff) << SATA0_BM1_0_REG_SHIFT)
#define SATA0_BM1_0_REG_RANGE                              31:0
#define SATA0_BM1_0_REG_WOFFSET                            0
#define SATA0_BM1_0_REG_VAL                                _MK_ENUM_CONST(0x00000000)                                                       // R---V
// 
// 
#define SATA0_BM2_0                                        0x000009D8                                                                       // R--4R
#define SATA0_BM2_0_SECURE                                 0
#define SATA0_BM2_0_WORD_COUNT                             1
#define SATA0_BM2_0_RESET_VAL                              0x0
#define SATA0_BM2_0_RESET_MASK                             0x0
#define SATA0_BM2_0_SW_DEFAULT_VAL                         0x0
#define SATA0_BM2_0_SW_DEFAULT_MASK                        0x0
#define SATA0_BM2_0_READ_MASK                              0xffffffff
#define SATA0_BM2_0_WRITE_MASK                             0x0
#define SATA0_BM2_0_REG_SHIFT                               _MK_SHIFT_CONST(0)                                                              // R--VF
#define SATA0_BM2_0_REG_FIELD                              (_MK_SHIFT_CONST(0xffffffff) << SATA0_BM2_0_REG_SHIFT)
#define SATA0_BM2_0_REG_RANGE                              31:0
#define SATA0_BM2_0_REG_WOFFSET                            0
#define SATA0_BM2_0_REG_VAL                                _MK_ENUM_CONST(0x00000000)                                                       // R---V
// 
// 
#define SATA0_BM3_0                                        0x000009DC                                                                       // R--4R
#define SATA0_BM3_0_SECURE                                 0
#define SATA0_BM3_0_WORD_COUNT                             1
#define SATA0_BM3_0_RESET_VAL                              0x0
#define SATA0_BM3_0_RESET_MASK                             0x0
#define SATA0_BM3_0_SW_DEFAULT_VAL                         0x0
#define SATA0_BM3_0_SW_DEFAULT_MASK                        0x0
#define SATA0_BM3_0_READ_MASK                              0xffffffff
#define SATA0_BM3_0_WRITE_MASK                             0x0
#define SATA0_BM3_0_REG_SHIFT                               _MK_SHIFT_CONST(0)                                                              // R--VF
#define SATA0_BM3_0_REG_FIELD                              (_MK_SHIFT_CONST(0xffffffff) << SATA0_BM3_0_REG_SHIFT)
#define SATA0_BM3_0_REG_RANGE                              31:0
#define SATA0_BM3_0_REG_WOFFSET                            0
#define SATA0_BM3_0_REG_VAL                                _MK_ENUM_CONST(0x00000000)                                                       // R---V
// 
// 
#define SATA0_BM4_0                                        0x000009E0                                                                       // R--4R
#define SATA0_BM4_0_SECURE                                 0
#define SATA0_BM4_0_WORD_COUNT                             1
#define SATA0_BM4_0_RESET_VAL                              0x0
#define SATA0_BM4_0_RESET_MASK                             0x0
#define SATA0_BM4_0_SW_DEFAULT_VAL                         0x0
#define SATA0_BM4_0_SW_DEFAULT_MASK                        0x0
#define SATA0_BM4_0_READ_MASK                              0xffffffff
#define SATA0_BM4_0_WRITE_MASK                             0x0
#define SATA0_BM4_0_REG_SHIFT                               _MK_SHIFT_CONST(0)                                                              // R--VF
#define SATA0_BM4_0_REG_FIELD                              (_MK_SHIFT_CONST(0xffffffff) << SATA0_BM4_0_REG_SHIFT)
#define SATA0_BM4_0_REG_RANGE                              31:0
#define SATA0_BM4_0_REG_WOFFSET                            0
#define SATA0_BM4_0_REG_VAL                                _MK_ENUM_CONST(0x00000000)                                                       // R---V
// 
// 
#define SATA0_BM5_0                                        0x000009E4                                                                       // R--4R
#define SATA0_BM5_0_SECURE                                 0
#define SATA0_BM5_0_WORD_COUNT                             1
#define SATA0_BM5_0_RESET_VAL                              0x0
#define SATA0_BM5_0_RESET_MASK                             0x0
#define SATA0_BM5_0_SW_DEFAULT_VAL                         0x0
#define SATA0_BM5_0_SW_DEFAULT_MASK                        0x0
#define SATA0_BM5_0_READ_MASK                              0xffffffff
#define SATA0_BM5_0_WRITE_MASK                             0x0
#define SATA0_BM5_0_REG_SHIFT                               _MK_SHIFT_CONST(0)                                                              // R--VF
#define SATA0_BM5_0_REG_FIELD                              (_MK_SHIFT_CONST(0xffffffff) << SATA0_BM5_0_REG_SHIFT)
#define SATA0_BM5_0_REG_RANGE                              31:0
#define SATA0_BM5_0_REG_WOFFSET                            0
#define SATA0_BM5_0_REG_VAL                                _MK_ENUM_CONST(0x00000000)                                                       // R---V
// 
// 
#define SATA0_BM6_0                                        0x000009E8                                                                       // R--4R
#define SATA0_BM6_0_SECURE                                 0
#define SATA0_BM6_0_WORD_COUNT                             1
#define SATA0_BM6_0_RESET_VAL                              0x0
#define SATA0_BM6_0_RESET_MASK                             0x0
#define SATA0_BM6_0_SW_DEFAULT_VAL                         0x0
#define SATA0_BM6_0_SW_DEFAULT_MASK                        0x0
#define SATA0_BM6_0_READ_MASK                              0xffffffff
#define SATA0_BM6_0_WRITE_MASK                             0x0
#define SATA0_BM6_0_REG_SHIFT                               _MK_SHIFT_CONST(0)                                                              // R--VF
#define SATA0_BM6_0_REG_FIELD                              (_MK_SHIFT_CONST(0xffffffff) << SATA0_BM6_0_REG_SHIFT)
#define SATA0_BM6_0_REG_RANGE                              31:0
#define SATA0_BM6_0_REG_WOFFSET                            0
#define SATA0_BM6_0_REG_VAL                                _MK_ENUM_CONST(0x00000000)                                                       // R---V
// 
// 
#define SATA0_BM7_0                                        0x000009EC                                                                       // R--4R
#define SATA0_BM7_0_SECURE                                 0
#define SATA0_BM7_0_WORD_COUNT                             1
#define SATA0_BM7_0_RESET_VAL                              0x0
#define SATA0_BM7_0_RESET_MASK                             0x0
#define SATA0_BM7_0_SW_DEFAULT_VAL                         0x0
#define SATA0_BM7_0_SW_DEFAULT_MASK                        0x0
#define SATA0_BM7_0_READ_MASK                              0xffffffff
#define SATA0_BM7_0_WRITE_MASK                             0x0
#define SATA0_BM7_0_REG_SHIFT                               _MK_SHIFT_CONST(0)                                                              // R--VF
#define SATA0_BM7_0_REG_FIELD                              (_MK_SHIFT_CONST(0xffffffff) << SATA0_BM7_0_REG_SHIFT)
#define SATA0_BM7_0_REG_RANGE                              31:0
#define SATA0_BM7_0_REG_WOFFSET                            0
#define SATA0_BM7_0_REG_VAL                                _MK_ENUM_CONST(0x00000000)                                                       // R---V
// 
// 
#define SATA0_BM8_0                                        0x000009F0                                                                       // R--4R
#define SATA0_BM8_0_SECURE                                 0
#define SATA0_BM8_0_WORD_COUNT                             1
#define SATA0_BM8_0_RESET_VAL                              0x0
#define SATA0_BM8_0_RESET_MASK                             0x0
#define SATA0_BM8_0_SW_DEFAULT_VAL                         0x0
#define SATA0_BM8_0_SW_DEFAULT_MASK                        0x0
#define SATA0_BM8_0_READ_MASK                              0xffffffff
#define SATA0_BM8_0_WRITE_MASK                             0x0
#define SATA0_BM8_0_REG_SHIFT                               _MK_SHIFT_CONST(0)                                                              // R--VF
#define SATA0_BM8_0_REG_FIELD                              (_MK_SHIFT_CONST(0xffffffff) << SATA0_BM8_0_REG_SHIFT)
#define SATA0_BM8_0_REG_RANGE                              31:0
#define SATA0_BM8_0_REG_WOFFSET                            0
#define SATA0_BM8_0_REG_VAL                                _MK_ENUM_CONST(0x00000000)                                                       // R---V
// 
//         Figure 10-31  FPCI Configuration Register 84h
// 
// 
// 
// .TITLE PCI Configuration Register 88h
// 
// Registers CFG_32 is a debug register used to get the status of DMA engines
// in SATA controller through software means while DMA is in progress.
// Through this register, we can determine what is byte count of data to be
// transfered and current pointer in PRD table. This register is for Primary channel.
// 
// 
// 31           24 23           16 15            8 7             0
// .-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-.
// |                                                               | CFG_32
// +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
// .LABEL PRIVATE
#define SATA0_CHXCFG2_0                                    0x000009F4                                                                       // R--4R
#define SATA0_CHXCFG2_0_SECURE                             0
#define SATA0_CHXCFG2_0_WORD_COUNT                         1
#define SATA0_CHXCFG2_0_RESET_VAL                          0x0
#define SATA0_CHXCFG2_0_RESET_MASK                         0x0
#define SATA0_CHXCFG2_0_SW_DEFAULT_VAL                     0x0
#define SATA0_CHXCFG2_0_SW_DEFAULT_MASK                    0x0
#define SATA0_CHXCFG2_0_READ_MASK                          0xbfffffff
#define SATA0_CHXCFG2_0_WRITE_MASK                         0x0
#define SATA0_CHXCFG2_0_DBG_CHX_BM_COUNT_SHIFT              _MK_SHIFT_CONST(0)                                                              // R--VF
#define SATA0_CHXCFG2_0_DBG_CHX_BM_COUNT_FIELD             (_MK_SHIFT_CONST(0xffff) << SATA0_CHXCFG2_0_DBG_CHX_BM_COUNT_SHIFT)
#define SATA0_CHXCFG2_0_DBG_CHX_BM_COUNT_RANGE             15:0
#define SATA0_CHXCFG2_0_DBG_CHX_BM_COUNT_WOFFSET           0
#define SATA0_CHXCFG2_0_DBG_CHX_BM_COUNT_0                 _MK_ENUM_CONST(0x00000000)                                                       // R---V
#define SATA0_CHXCFG2_0_DBG_CHX_PRD_ADDRESS_SHIFT           _MK_SHIFT_CONST(16)                                                             // R--VF
#define SATA0_CHXCFG2_0_DBG_CHX_PRD_ADDRESS_FIELD          (_MK_SHIFT_CONST(0x3fff) << SATA0_CHXCFG2_0_DBG_CHX_PRD_ADDRESS_SHIFT)
#define SATA0_CHXCFG2_0_DBG_CHX_PRD_ADDRESS_RANGE          29:16
#define SATA0_CHXCFG2_0_DBG_CHX_PRD_ADDRESS_WOFFSET        0
#define SATA0_CHXCFG2_0_DBG_CHX_PRD_ADDRESS_0              _MK_ENUM_CONST(0x00000000)                                                       // R---V
#define SATA0_CHXCFG2_0_DBG_CHX_PRD_LAST_SHIFT              _MK_SHIFT_CONST(31)                                                             // R--VF
#define SATA0_CHXCFG2_0_DBG_CHX_PRD_LAST_FIELD             (_MK_SHIFT_CONST(0x1) << SATA0_CHXCFG2_0_DBG_CHX_PRD_LAST_SHIFT)
#define SATA0_CHXCFG2_0_DBG_CHX_PRD_LAST_RANGE             31:31
#define SATA0_CHXCFG2_0_DBG_CHX_PRD_LAST_WOFFSET           0
#define SATA0_CHXCFG2_0_DBG_CHX_PRD_LAST_0                 _MK_ENUM_CONST(0x00000000)                                                       // R---V
// 
//         Figure 10-32  FPCI Configuration Register 88h
// 
// 
// .LABEL DEBUG_BUS
// .LABEL PRIVATE
// 
//    This is a Serial ATA Reserved register. This register is used for
// SATA emulation revision in sata_emulation compile. This is also used for exporting some
// debug signals in non-emulation case.
// 
// .LABEL INT_REL
// .FIELD PRI_INTR
// PRI_INTR is a status bit for Primary Interrupt pending. Used for debug and emulation
// purpose.
// 
// .FIELD SEC_INTR
// SEC_INTR is a status bit for Secondary Interrupt pending. Used for debug and emulation
// purpose.
// 
// .LABEL PRIVATE
// NOTE:  Not to be used for emulation any more. Use emu related registers for emulation.
//        23:22 bits are also used for reading intr status, as was in older code.
//        This should be cleaned up once we are sure that no-one is using these registers.
// 
// 
// 
//  31           24 23           16 15            8 7             0
// .-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-.
// |0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0|       |       |       | INTR
// +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
// 
// 
// .LABEL INT_REL
#define SATA0_INTR_0                                       0x00000AC0                                                                       // RWC4R
#define SATA0_INTR_0_SECURE                                0
#define SATA0_INTR_0_WORD_COUNT                            1
#define SATA0_INTR_0_RESET_VAL                             0x0
#define SATA0_INTR_0_RESET_MASK                            0x0
#define SATA0_INTR_0_SW_DEFAULT_VAL                        0x0
#define SATA0_INTR_0_SW_DEFAULT_MASK                       0x0
#define SATA0_INTR_0_READ_MASK                             0xc0c00000
#define SATA0_INTR_0_WRITE_MASK                            0x0
#define SATA0_INTR_0_SEC_INTR_SHIFT                         _MK_SHIFT_CONST(31)                                                             // R-C-F
#define SATA0_INTR_0_SEC_INTR_FIELD                        (_MK_SHIFT_CONST(0x1) << SATA0_INTR_0_SEC_INTR_SHIFT)
#define SATA0_INTR_0_SEC_INTR_RANGE                        31:31
#define SATA0_INTR_0_SEC_INTR_WOFFSET                      0
#define SATA0_INTR_0_SEC_INTR__WRNPRDCHK                   _MK_ENUM_CONST(0x00000001)                                                       // ----V
#define SATA0_INTR_0_SEC_INTR_PENDING                      _MK_ENUM_CONST(0x00000001)                                                       // R---V
#define SATA0_INTR_0_SEC_INTR_NOT_PENDING                  _MK_ENUM_CONST(0x00000000)                                                       // R-C-V
#define SATA0_INTR_0_PRI_INTR_SHIFT                         _MK_SHIFT_CONST(30)                                                             // R-C-F
#define SATA0_INTR_0_PRI_INTR_FIELD                        (_MK_SHIFT_CONST(0x1) << SATA0_INTR_0_PRI_INTR_SHIFT)
#define SATA0_INTR_0_PRI_INTR_RANGE                        30:30
#define SATA0_INTR_0_PRI_INTR_WOFFSET                      0
#define SATA0_INTR_0_PRI_INTR__WRNPRDCHK                   _MK_ENUM_CONST(0x00000001)                                                       // ----V
#define SATA0_INTR_0_PRI_INTR_PENDING                      _MK_ENUM_CONST(0x00000001)                                                       // R---V
#define SATA0_INTR_0_PRI_INTR_NOT_PENDING                  _MK_ENUM_CONST(0x00000000)                                                       // R-C-V
#define SATA0_INTR_0_SEC_INTR1_SHIFT                        _MK_SHIFT_CONST(23)                                                             // R-C-F
#define SATA0_INTR_0_SEC_INTR1_FIELD                       (_MK_SHIFT_CONST(0x1) << SATA0_INTR_0_SEC_INTR1_SHIFT)
#define SATA0_INTR_0_SEC_INTR1_RANGE                       23:23
#define SATA0_INTR_0_SEC_INTR1_WOFFSET                     0
#define SATA0_INTR_0_SEC_INTR1__WRNPRDCHK                  _MK_ENUM_CONST(0x00000001)                                                       // ----V
#define SATA0_INTR_0_SEC_INTR1_PENDING                     _MK_ENUM_CONST(0x00000001)                                                       // R---V
#define SATA0_INTR_0_SEC_INTR1_NOT_PENDING                 _MK_ENUM_CONST(0x00000000)                                                       // R-C-V
#define SATA0_INTR_0_PRI_INTR1_SHIFT                        _MK_SHIFT_CONST(22)                                                             // R-C-F
#define SATA0_INTR_0_PRI_INTR1_FIELD                       (_MK_SHIFT_CONST(0x1) << SATA0_INTR_0_PRI_INTR1_SHIFT)
#define SATA0_INTR_0_PRI_INTR1_RANGE                       22:22
#define SATA0_INTR_0_PRI_INTR1_WOFFSET                     0
#define SATA0_INTR_0_PRI_INTR1__WRNPRDCHK                  _MK_ENUM_CONST(0x00000001)                                                       // ----V
#define SATA0_INTR_0_PRI_INTR1_PENDING                     _MK_ENUM_CONST(0x00000001)                                                       // R---V
#define SATA0_INTR_0_PRI_INTR1_NOT_PENDING                 _MK_ENUM_CONST(0x00000000)                                                       // R-C-V
// 
// 
// 
// .LABEL PRIVATE
// 
// 
//         Figure 10-30  Serial ATA Reserved Register 80h
// 
// 
// 31           24 23           16 15            8 7             0
// .-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-.
// |0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0|       |       |       | PORT0_STATES
// +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
// 
#define SATA0_CHX_PORT_STATES_0                            0x00000AC4                                                                       // R-C4R
#define SATA0_CHX_PORT_STATES_0_SECURE                     0
#define SATA0_CHX_PORT_STATES_0_WORD_COUNT                 1
#define SATA0_CHX_PORT_STATES_0_RESET_VAL                  0x0
#define SATA0_CHX_PORT_STATES_0_RESET_MASK                 0x0
#define SATA0_CHX_PORT_STATES_0_SW_DEFAULT_VAL             0x0
#define SATA0_CHX_PORT_STATES_0_SW_DEFAULT_MASK            0x0
#define SATA0_CHX_PORT_STATES_0_READ_MASK                  0xffff7f3f
#define SATA0_CHX_PORT_STATES_0_WRITE_MASK                 0x0
#define SATA0_CHX_PORT_STATES_0_LINK_SHIFT                  _MK_SHIFT_CONST(0)                                                              // R-C-F
#define SATA0_CHX_PORT_STATES_0_LINK_FIELD                 (_MK_SHIFT_CONST(0x3f) << SATA0_CHX_PORT_STATES_0_LINK_SHIFT)
#define SATA0_CHX_PORT_STATES_0_LINK_RANGE                 5:0
#define SATA0_CHX_PORT_STATES_0_LINK_WOFFSET               0
#define SATA0_CHX_PORT_STATES_0_LINK_INIT                  _MK_ENUM_CONST(0x00000000)                                                       // R-C-V
#define SATA0_CHX_PORT_STATES_0_TPRT_SHIFT                  _MK_SHIFT_CONST(8)                                                              // R-C-F
#define SATA0_CHX_PORT_STATES_0_TPRT_FIELD                 (_MK_SHIFT_CONST(0x7f) << SATA0_CHX_PORT_STATES_0_TPRT_SHIFT)
#define SATA0_CHX_PORT_STATES_0_TPRT_RANGE                 14:8
#define SATA0_CHX_PORT_STATES_0_TPRT_WOFFSET               0
#define SATA0_CHX_PORT_STATES_0_TPRT_INIT                  _MK_ENUM_CONST(0x00000000)                                                       // R-C-V
#define SATA0_CHX_PORT_STATES_0_H_AHCI_SHIFT                _MK_SHIFT_CONST(16)                                                             // R-C-F
#define SATA0_CHX_PORT_STATES_0_H_AHCI_FIELD               (_MK_SHIFT_CONST(0x7f) << SATA0_CHX_PORT_STATES_0_H_AHCI_SHIFT)
#define SATA0_CHX_PORT_STATES_0_H_AHCI_RANGE               22:16
#define SATA0_CHX_PORT_STATES_0_H_AHCI_WOFFSET             0
#define SATA0_CHX_PORT_STATES_0_H_AHCI_INIT                _MK_ENUM_CONST(0x00000000)                                                       // R-C-V
#define SATA0_CHX_PORT_STATES_0_P_AHCI_SHIFT                _MK_SHIFT_CONST(23)                                                             // R-C-F
#define SATA0_CHX_PORT_STATES_0_P_AHCI_FIELD               (_MK_SHIFT_CONST(0x1ff) << SATA0_CHX_PORT_STATES_0_P_AHCI_SHIFT)
#define SATA0_CHX_PORT_STATES_0_P_AHCI_RANGE               31:23
#define SATA0_CHX_PORT_STATES_0_P_AHCI_WOFFSET             0
#define SATA0_CHX_PORT_STATES_0_P_AHCI_INIT                _MK_ENUM_CONST(0x00000000)                                                       // R-C-V
// 
// 
// ###########################################################################################
//     3K to 4K - Emulation specific setting, debug registers
//     0XBB8 - 0XF9C
// ###########################################################################################
// 
// 
// .LABEL EMULATION PRIVATE INT_REL
// /*
//     T_SATA0_CFG_25 configures the SATA phy-interface layer.
// The phy-interface layer sits between the SATA link layer in the south-bridge chip, and
// the external SATA phy chips. Its job is to abstract the different external PHY chips so that the
// link layer can talk to a common interface.
// 
// RESET_ON_COMRESET bit causes SATA controller to hard reset the PHY whenever SW wants to send
// a comreset to ***any*** of the two channels. This was done to workaround an issue found on
// mcp65 emulation.
// 
// The PHY_SEL field is a read only field to determine which PHY was selected by the ROM bits.
// The DATA_EARLY field adjusts the outbound timing of the tx-data signals. DATA_EARLY_YES pushes
// the data a quarter cycle early, where one cycle is the period of txclk.
// The TXCLK_EARLY field adjusts the outbound timing of the txclk signals. TXCLK_EARLY_YES pushes
// the txclk a quarter cycle early.
// The PM_EN field turns on and off the power management feature.
// The UART_DIV field adjusts the clock divider used to generate the serial clock used for communicating
// with the Marvell external PHY chip. The reference clock is 150MHz ( the frequency of the transmit
// clock ). The default value for the divider is 15, which gives us 10 MHz serial clock ( baud rate )
// The UART_SAMPLE field adjusts the sampling position of the serial line. It should be set to
// int(UART_DIV/2) - 1
// The BYPASS field tells the phy-interface block to ignore control-signals information,
// normally present as an OOB information along with the data signals. This field should only
// be used during debug.
// The ABSORB_ALIGN_PRIM field toggles the behaviour of the phy-interface block to filter
// ALIGN primitives
// in the received data stream. Link layer does not care about ALIGN primitives.
// The USE_RBC1 field affects whether the received data on channel 2 is sampled on
// falling edge of rbc0, or sampled on rising edge of rbc1. SiliconImage uses two
// receive clock, each 180 degree apart with each other.
// The UART_TIMEOUT field is a 4-bits field signifying the amount of time the uart block wait for response
// from the Marvell PHY. The default value of 2 indicates waiting for 2*128 clock cycles, where the clock
// is a 150MHz clock. The unit of 128 clock cyles is used here because a 10-bit serial data transmission
// takes 150 clock cyles. ( baud rate is 10 MHz ) */
// 
//  31           24 23           16 15            8 7             0
// .-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-.
// |0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0|    | EMU_1
// +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
// 
#define SATA0_EMU1_0                                       0x00000C00                                                                       // RWW4R
#define SATA0_EMU1_0_SECURE                                0
#define SATA0_EMU1_0_WORD_COUNT                            1
#define SATA0_EMU1_0_RESET_VAL                             0x0
#define SATA0_EMU1_0_RESET_MASK                            0x0
#define SATA0_EMU1_0_SW_DEFAULT_VAL                        0x0
#define SATA0_EMU1_0_SW_DEFAULT_MASK                       0x0
#define SATA0_EMU1_0_READ_MASK                             0xf7ffff7f
#define SATA0_EMU1_0_WRITE_MASK                            0xf7ffff71
#define SATA0_EMU1_0_RESET_ON_COMRESET_SHIFT                _MK_SHIFT_CONST(0)                                                              // RWCVF
#define SATA0_EMU1_0_RESET_ON_COMRESET_FIELD               (_MK_SHIFT_CONST(0x1) << SATA0_EMU1_0_RESET_ON_COMRESET_SHIFT)
#define SATA0_EMU1_0_RESET_ON_COMRESET_RANGE               0:0
#define SATA0_EMU1_0_RESET_ON_COMRESET_WOFFSET             0
#define SATA0_EMU1_0_RESET_ON_COMRESET__WRNPRDCHK          _MK_ENUM_CONST(0x00000001)                                                       // ----V
#define SATA0_EMU1_0_RESET_ON_COMRESET_YES                 _MK_ENUM_CONST(0x00000001)                                                       // RWC-V
#define SATA0_EMU1_0_RESET_ON_COMRESET_NO                  _MK_ENUM_CONST(0x00000000)                                                       // RW--V
#define SATA0_EMU1_0_PHY_SEL_SHIFT                          _MK_SHIFT_CONST(1)                                                              // R-XVF
#define SATA0_EMU1_0_PHY_SEL_FIELD                         (_MK_SHIFT_CONST(0x7) << SATA0_EMU1_0_PHY_SEL_SHIFT)
#define SATA0_EMU1_0_PHY_SEL_RANGE                         3:1
#define SATA0_EMU1_0_PHY_SEL_WOFFSET                       0
#define SATA0_EMU1_0_PHY_SEL_NOTHING                       _MK_ENUM_CONST(0x00000000)                                                       // R---V
#define SATA0_EMU1_0_PHY_SEL_MARVELL                       _MK_ENUM_CONST(0x00000001)                                                       // R---V
#define SATA0_EMU1_0_PHY_SEL_SI                            _MK_ENUM_CONST(0x00000002)                                                       // R---V
#define SATA0_EMU1_0_PHY_SEL_NVDA_EXT                      _MK_ENUM_CONST(0x00000003)                                                       // R---V
#define SATA0_EMU1_0_PHY_SEL_NVDA_INT                      _MK_ENUM_CONST(0x00000004)                                                       // R---V
#define SATA0_EMU1_0_PHY_DATA_EARLY_SHIFT                   _MK_SHIFT_CONST(4)                                                              // RWCVF
#define SATA0_EMU1_0_PHY_DATA_EARLY_FIELD                  (_MK_SHIFT_CONST(0x1) << SATA0_EMU1_0_PHY_DATA_EARLY_SHIFT)
#define SATA0_EMU1_0_PHY_DATA_EARLY_RANGE                  4:4
#define SATA0_EMU1_0_PHY_DATA_EARLY_WOFFSET                0
#define SATA0_EMU1_0_PHY_DATA_EARLY_NO                     _MK_ENUM_CONST(0x00000000)                                                       // RWC-V
#define SATA0_EMU1_0_PHY_DATA_EARLY_YES                    _MK_ENUM_CONST(0x00000001)                                                       // RW--V
#define SATA0_EMU1_0_PHY_TXCLK_EARLY_SHIFT                  _MK_SHIFT_CONST(5)                                                              // RWWVF
#define SATA0_EMU1_0_PHY_TXCLK_EARLY_FIELD                 (_MK_SHIFT_CONST(0x1) << SATA0_EMU1_0_PHY_TXCLK_EARLY_SHIFT)
#define SATA0_EMU1_0_PHY_TXCLK_EARLY_RANGE                 5:5
#define SATA0_EMU1_0_PHY_TXCLK_EARLY_WOFFSET               0
#define SATA0_EMU1_0_PHY_TXCLK_EARLY_DEFAULT               (_MK_MASK_CONST(0x00000000)
#define SATA0_EMU1_0_PHY_TXCLK_EARLY_DEFAULT_MASK          (_MK_MASK_CONST(0x1)
#define SATA0_EMU1_0_PHY_TXCLK_EARLY_SW_DEFAULT            (_MK_MASK_CONST(0x00000000)
#define SATA0_EMU1_0_PHY_TXCLK_EARLY_SW_DEFAULT_MASK       (_MK_MASK_CONST(0x1)
#define SATA0_EMU1_0_PHY_TXCLK_EARLY_NO                    _MK_ENUM_CONST(0x00000000)                                                       // RWW-V
#define SATA0_EMU1_0_PHY_TXCLK_EARLY_YES                   _MK_ENUM_CONST(0x00000001)                                                       // RW--V
#define SATA0_EMU1_0_PHY_PM_EN_SHIFT                        _MK_SHIFT_CONST(6)                                                              // RWCVF
#define SATA0_EMU1_0_PHY_PM_EN_FIELD                       (_MK_SHIFT_CONST(0x1) << SATA0_EMU1_0_PHY_PM_EN_SHIFT)
#define SATA0_EMU1_0_PHY_PM_EN_RANGE                       6:6
#define SATA0_EMU1_0_PHY_PM_EN_WOFFSET                     0
#define SATA0_EMU1_0_PHY_PM_EN_NO                          _MK_ENUM_CONST(0x00000000)                                                       // RWC-V
#define SATA0_EMU1_0_PHY_PM_EN_YES                         _MK_ENUM_CONST(0x00000001)                                                       // RW--V
#define SATA0_EMU1_0_PHY_UART_DIV_SHIFT                     _MK_SHIFT_CONST(8)                                                              // RWCVF
#define SATA0_EMU1_0_PHY_UART_DIV_FIELD                    (_MK_SHIFT_CONST(0xff) << SATA0_EMU1_0_PHY_UART_DIV_SHIFT)
#define SATA0_EMU1_0_PHY_UART_DIV_RANGE                    15:8
#define SATA0_EMU1_0_PHY_UART_DIV_WOFFSET                  0
#define SATA0_EMU1_0_PHY_UART_SAMPLE_SHIFT                  _MK_SHIFT_CONST(16)                                                             // RWCVF
#define SATA0_EMU1_0_PHY_UART_SAMPLE_FIELD                 (_MK_SHIFT_CONST(0xff) << SATA0_EMU1_0_PHY_UART_SAMPLE_SHIFT)
#define SATA0_EMU1_0_PHY_UART_SAMPLE_RANGE                 23:16
#define SATA0_EMU1_0_PHY_UART_SAMPLE_WOFFSET               0
#define SATA0_EMU1_0_PHY_BYPASS_EN_SHIFT                    _MK_SHIFT_CONST(24)                                                             // RWCVF
#define SATA0_EMU1_0_PHY_BYPASS_EN_FIELD                   (_MK_SHIFT_CONST(0x1) << SATA0_EMU1_0_PHY_BYPASS_EN_SHIFT)
#define SATA0_EMU1_0_PHY_BYPASS_EN_RANGE                   24:24
#define SATA0_EMU1_0_PHY_BYPASS_EN_WOFFSET                 0
#define SATA0_EMU1_0_PHY_BYPASS_EN_NO                      _MK_ENUM_CONST(0x00000000)                                                       // RWC-V
#define SATA0_EMU1_0_PHY_BYPASS_EN_YES                     _MK_ENUM_CONST(0x00000001)                                                       // RW--V
#define SATA0_EMU1_0_PHY_ABSORB_ALIGN_PRIM_SHIFT            _MK_SHIFT_CONST(25)                                                             // RWCVF
#define SATA0_EMU1_0_PHY_ABSORB_ALIGN_PRIM_FIELD           (_MK_SHIFT_CONST(0x1) << SATA0_EMU1_0_PHY_ABSORB_ALIGN_PRIM_SHIFT)
#define SATA0_EMU1_0_PHY_ABSORB_ALIGN_PRIM_RANGE           25:25
#define SATA0_EMU1_0_PHY_ABSORB_ALIGN_PRIM_WOFFSET         0
#define SATA0_EMU1_0_PHY_ABSORB_ALIGN_PRIM_NO              _MK_ENUM_CONST(0x00000000)                                                       // RW--V
#define SATA0_EMU1_0_PHY_ABSORB_ALIGN_PRIM_YES             _MK_ENUM_CONST(0x00000001)                                                       // RWC-V
#define SATA0_EMU1_0_PHY_USE_RBC1_SHIFT                     _MK_SHIFT_CONST(26)                                                             // RWCVF
#define SATA0_EMU1_0_PHY_USE_RBC1_FIELD                    (_MK_SHIFT_CONST(0x1) << SATA0_EMU1_0_PHY_USE_RBC1_SHIFT)
#define SATA0_EMU1_0_PHY_USE_RBC1_RANGE                    26:26
#define SATA0_EMU1_0_PHY_USE_RBC1_WOFFSET                  0
#define SATA0_EMU1_0_PHY_USE_RBC1_NO                       _MK_ENUM_CONST(0x00000000)                                                       // RWC-V
#define SATA0_EMU1_0_PHY_USE_RBC1_YES                      _MK_ENUM_CONST(0x00000001)                                                       // RW--V
#define SATA0_EMU1_0_PHY_UART_TIMEOUT_SHIFT                 _MK_SHIFT_CONST(28)                                                             // RWCVF
#define SATA0_EMU1_0_PHY_UART_TIMEOUT_FIELD                (_MK_SHIFT_CONST(0xf) << SATA0_EMU1_0_PHY_UART_TIMEOUT_SHIFT)
#define SATA0_EMU1_0_PHY_UART_TIMEOUT_RANGE                31:28
#define SATA0_EMU1_0_PHY_UART_TIMEOUT_WOFFSET              0
#define SATA0_EMU1_0_PHY_UART_TIMEOUT_INIT                 _MK_ENUM_CONST(0x00000004)                                                       // RWC-V
// 
// 
//         Figure 10-25  Serial ATA Control Register 68h
// 
// 
// .LABEL PRIVATE INT_REL
// 
//    This register changes the SATA device PCI class code register via a backdoor write. This
// could be used by SBIOS to update the class code before OS sees it.
// 
// .FIELD AHCI_DEBUG_PORT_SEL
// These bits will be used to select the particular port to debug.
// It is a zero based number used to select the port.
// 
//  31                           16 15                            0
// .-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-.
// |0                           0|                                 | EMU_2
// +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
// 
#define SATA0_EMU2_0                                       0x00000C04                                                                       // RWW4R
#define SATA0_EMU2_0_SECURE                                0
#define SATA0_EMU2_0_WORD_COUNT                            1
#define SATA0_EMU2_0_RESET_VAL                             0x0
#define SATA0_EMU2_0_RESET_MASK                            0x0
#define SATA0_EMU2_0_SW_DEFAULT_VAL                        0x0
#define SATA0_EMU2_0_SW_DEFAULT_MASK                       0x0
#define SATA0_EMU2_0_READ_MASK                             0xff01ffff
#define SATA0_EMU2_0_WRITE_MASK                            0xff000000
#define SATA0_EMU2_0_RSVD_SHIFT                             _MK_SHIFT_CONST(0)                                                              // C--VF
#define SATA0_EMU2_0_RSVD_FIELD                            (_MK_SHIFT_CONST(0x1ffff) << SATA0_EMU2_0_RSVD_SHIFT)
#define SATA0_EMU2_0_RSVD_RANGE                            16:0
#define SATA0_EMU2_0_RSVD_WOFFSET                          0
#define SATA0_EMU2_0_RSVD_INIT                             _MK_ENUM_CONST(0x0)                                                              // C---V
#define SATA0_EMU2_0_AHCI_DEBUG_PORT_SEL_SHIFT              _MK_SHIFT_CONST(24)                                                             // RWCVF
#define SATA0_EMU2_0_AHCI_DEBUG_PORT_SEL_FIELD             (_MK_SHIFT_CONST(0x7) << SATA0_EMU2_0_AHCI_DEBUG_PORT_SEL_SHIFT)
#define SATA0_EMU2_0_AHCI_DEBUG_PORT_SEL_RANGE             26:24
#define SATA0_EMU2_0_AHCI_DEBUG_PORT_SEL_WOFFSET           0
#define SATA0_EMU2_0_AHCI_DEBUG_PORT_SEL_ZERO              _MK_ENUM_CONST(0x00000000)                                                       // RWC-V
#define SATA0_EMU2_0_AHCI_DEBUG_PORT_SEL_ONE               _MK_ENUM_CONST(0x00000001)                                                       // RW--V
#define SATA0_EMU2_0_AHCI_DEBUG_PORT_SEL_TWO               _MK_ENUM_CONST(0x00000002)                                                       // RW--V
#define SATA0_EMU2_0_AHCI_DEBUG_PORT_SEL_THREE             _MK_ENUM_CONST(0x00000003)                                                       // RW--V
#define SATA0_EMU2_0_AHCI_DEBUG_PORT_SEL_RESERVED_SHIFT     _MK_SHIFT_CONST(27)                                                             // RWCVF
#define SATA0_EMU2_0_AHCI_DEBUG_PORT_SEL_RESERVED_FIELD    (_MK_SHIFT_CONST(0xf) << SATA0_EMU2_0_AHCI_DEBUG_PORT_SEL_RESERVED_SHIFT)
#define SATA0_EMU2_0_AHCI_DEBUG_PORT_SEL_RESERVED_RANGE    30:27
#define SATA0_EMU2_0_AHCI_DEBUG_PORT_SEL_RESERVED_WOFFSET  0
#define SATA0_EMU2_0_AHCI_DEBUG_PORT_SEL_RESERVED_ZERO     _MK_ENUM_CONST(0x00000000)                                                       // RWC-V
#define SATA0_EMU2_0_RETRY_CTL_FIS_SRST_SHIFT               _MK_SHIFT_CONST(31)                                                             // RWCVF
#define SATA0_EMU2_0_RETRY_CTL_FIS_SRST_FIELD              (_MK_SHIFT_CONST(0x1) << SATA0_EMU2_0_RETRY_CTL_FIS_SRST_SHIFT)
#define SATA0_EMU2_0_RETRY_CTL_FIS_SRST_RANGE              31:31
#define SATA0_EMU2_0_RETRY_CTL_FIS_SRST_WOFFSET            0
#define SATA0_EMU2_0_RETRY_CTL_FIS_SRST_INIT               _MK_ENUM_CONST(0x00000000)                                                       // RWC-V
// 
// 
//         Figure 10-38  Serial ATA Backdoor class code Register 9Ch
// 
// 
// 
// .LABEL UNUSED
// 
// This register contains command, address and status for Marvell UART transmission.
// 
//  31           24 23           16 15            8 7             0
// .-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-.
// |                                                               | EMU_3
// +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
// 
#define SATA0_EMU3_0                                       0x00000C08                                                                       // RWW4R
#define SATA0_EMU3_0_SECURE                                0
#define SATA0_EMU3_0_WORD_COUNT                            1
#define SATA0_EMU3_0_RESET_VAL                             0x0
#define SATA0_EMU3_0_RESET_MASK                            0x0
#define SATA0_EMU3_0_SW_DEFAULT_VAL                        0x0
#define SATA0_EMU3_0_SW_DEFAULT_MASK                       0x0
#define SATA0_EMU3_0_READ_MASK                             0xffffffff
#define SATA0_EMU3_0_WRITE_MASK                            0x1ff
#define SATA0_EMU3_0_UART_ADDR_SHIFT                        _MK_SHIFT_CONST(0)                                                              // RWC-F
#define SATA0_EMU3_0_UART_ADDR_FIELD                       (_MK_SHIFT_CONST(0xff) << SATA0_EMU3_0_UART_ADDR_SHIFT)
#define SATA0_EMU3_0_UART_ADDR_RANGE                       7:0
#define SATA0_EMU3_0_UART_ADDR_WOFFSET                     0
#define SATA0_EMU3_0_UART_ADDR__NOPRDCHK                   _MK_ENUM_CONST(0x00000001)                                                       // ----V
#define SATA0_EMU3_0_UART_ADDR_0                           _MK_ENUM_CONST(0x00000000)                                                       // RWC-V
#define SATA0_EMU3_0_UART_CMD_SHIFT                         _MK_SHIFT_CONST(8)                                                              // RWC-F
#define SATA0_EMU3_0_UART_CMD_FIELD                        (_MK_SHIFT_CONST(0x1) << SATA0_EMU3_0_UART_CMD_SHIFT)
#define SATA0_EMU3_0_UART_CMD_RANGE                        8:8
#define SATA0_EMU3_0_UART_CMD_WOFFSET                      0
#define SATA0_EMU3_0_UART_CMD__NOPRDCHK                    _MK_ENUM_CONST(0x00000001)                                                       // ----V
#define SATA0_EMU3_0_UART_CMD_READ                         _MK_ENUM_CONST(0x00000000)                                                       // RWC-V
#define SATA0_EMU3_0_UART_CMD_WRITE                        _MK_ENUM_CONST(0x00000001)                                                       // RW--V
#define SATA0_EMU3_0_UART_RESERVED1_SHIFT                   _MK_SHIFT_CONST(9)                                                              // C---F
#define SATA0_EMU3_0_UART_RESERVED1_FIELD                  (_MK_SHIFT_CONST(0x7) << SATA0_EMU3_0_UART_RESERVED1_SHIFT)
#define SATA0_EMU3_0_UART_RESERVED1_RANGE                  11:9
#define SATA0_EMU3_0_UART_RESERVED1_WOFFSET                0
#define SATA0_EMU3_0_UART_RESERVED1_0                      _MK_ENUM_CONST(0x00000000)                                                       // C---V
#define SATA0_EMU3_0_UART_STATUS_SHIFT                      _MK_SHIFT_CONST(12)                                                             // R-W-F
#define SATA0_EMU3_0_UART_STATUS_FIELD                     (_MK_SHIFT_CONST(0x1) << SATA0_EMU3_0_UART_STATUS_SHIFT)
#define SATA0_EMU3_0_UART_STATUS_RANGE                     12:12
#define SATA0_EMU3_0_UART_STATUS_WOFFSET                   0
#define SATA0_EMU3_0_UART_STATUS_DEFAULT                   (_MK_MASK_CONST(0x00000001)
#define SATA0_EMU3_0_UART_STATUS_DEFAULT_MASK              (_MK_MASK_CONST(0x1)
#define SATA0_EMU3_0_UART_STATUS_SW_DEFAULT                (_MK_MASK_CONST(0x00000001)
#define SATA0_EMU3_0_UART_STATUS_SW_DEFAULT_MASK           (_MK_MASK_CONST(0x1)
#define SATA0_EMU3_0_UART_STATUS_BUSY                      _MK_ENUM_CONST(0x00000000)                                                       // R---V
#define SATA0_EMU3_0_UART_STATUS_DONE                      _MK_ENUM_CONST(0x00000001)                                                       // R-W-V
#define SATA0_EMU3_0_UART_RESERVED_SHIFT                    _MK_SHIFT_CONST(13)                                                             // C---F
#define SATA0_EMU3_0_UART_RESERVED_FIELD                   (_MK_SHIFT_CONST(0x7ffff) << SATA0_EMU3_0_UART_RESERVED_SHIFT)
#define SATA0_EMU3_0_UART_RESERVED_RANGE                   31:13
#define SATA0_EMU3_0_UART_RESERVED_WOFFSET                 0
#define SATA0_EMU3_0_UART_RESERVED_0                       _MK_ENUM_CONST(0x00000000)                                                       // C---V
// 
// Warning: unsupported define: #define T_SATA0_EMU3_UART_STATUS__NO_CHECK                    0x0 /*       */
// 
//         Figure 10-35  Serial ATA Reserved Register A4h
// 
// 
//    This register contains the read/write data for Marvell UART transmission
// 
//  31           24 23           16 15            8 7             0
// .-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-.
// |                                                               | EMU_4
// +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
// 
#define SATA0_EMU4_0                                       0x00000C0C                                                                       // R-W4R
#define SATA0_EMU4_0_SECURE                                0
#define SATA0_EMU4_0_WORD_COUNT                            1
#define SATA0_EMU4_0_RESET_VAL                             0x0
#define SATA0_EMU4_0_RESET_MASK                            0x0
#define SATA0_EMU4_0_SW_DEFAULT_VAL                        0x0
#define SATA0_EMU4_0_SW_DEFAULT_MASK                       0x0
#define SATA0_EMU4_0_READ_MASK                             0xffffffff
#define SATA0_EMU4_0_WRITE_MASK                            0x0
#define SATA0_EMU4_0_UART_DATA_SHIFT                        _MK_SHIFT_CONST(0)                                                              // R-W-F
#define SATA0_EMU4_0_UART_DATA_FIELD                       (_MK_SHIFT_CONST(0xffffffff) << SATA0_EMU4_0_UART_DATA_SHIFT)
#define SATA0_EMU4_0_UART_DATA_RANGE                       31:0
#define SATA0_EMU4_0_UART_DATA_WOFFSET                     0
#define SATA0_EMU4_0_UART_DATA_DEFAULT                     (_MK_MASK_CONST(0x00000000)
#define SATA0_EMU4_0_UART_DATA_DEFAULT_MASK                (_MK_MASK_CONST(0xffffffff)
#define SATA0_EMU4_0_UART_DATA_SW_DEFAULT                  (_MK_MASK_CONST(0x00000000)
#define SATA0_EMU4_0_UART_DATA_SW_DEFAULT_MASK             (_MK_MASK_CONST(0xffffffff)
#define SATA0_EMU4_0_UART_DATA_0                           _MK_ENUM_CONST(0x00000000)                                                       // R-W-V
// 
//         Figure 10-41  Serial ATA Reserved Register 7Ch
// 
//  31           24 23           16 15            8 7             0
// .-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-.
// |                                                               | EMU_5
// +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
// 
#define SATA0_EMU5_0                                       0x00000C10                                                                       // RWW4R
#define SATA0_EMU5_0_SECURE                                0
#define SATA0_EMU5_0_WORD_COUNT                            1
#define SATA0_EMU5_0_RESET_VAL                             0x0
#define SATA0_EMU5_0_RESET_MASK                            0x0
#define SATA0_EMU5_0_SW_DEFAULT_VAL                        0x0
#define SATA0_EMU5_0_SW_DEFAULT_MASK                       0x0
#define SATA0_EMU5_0_READ_MASK                             0xff0000
#define SATA0_EMU5_0_WRITE_MASK                            0x7f0000
#define SATA0_EMU5_0_RXDATA_IB_DELAY_SHIFT                  _MK_SHIFT_CONST(16)                                                             // RWW-F
#define SATA0_EMU5_0_RXDATA_IB_DELAY_FIELD                 (_MK_SHIFT_CONST(0x7) << SATA0_EMU5_0_RXDATA_IB_DELAY_SHIFT)
#define SATA0_EMU5_0_RXDATA_IB_DELAY_RANGE                 18:16
#define SATA0_EMU5_0_RXDATA_IB_DELAY_WOFFSET               0
#define SATA0_EMU5_0_RXDATA_IB_DELAY_DEFAULT               (_MK_MASK_CONST(0x00000000)
#define SATA0_EMU5_0_RXDATA_IB_DELAY_DEFAULT_MASK          (_MK_MASK_CONST(0x7)
#define SATA0_EMU5_0_RXDATA_IB_DELAY_SW_DEFAULT            (_MK_MASK_CONST(0x00000000)
#define SATA0_EMU5_0_RXDATA_IB_DELAY_SW_DEFAULT_MASK       (_MK_MASK_CONST(0x7)
#define SATA0_EMU5_0_RXDATA_IB_DELAY_INIT                  _MK_ENUM_CONST(0x00000000)                                                       // RWW-V
#define SATA0_EMU5_0_IMP_19_SHIFT                           _MK_SHIFT_CONST(19)                                                             // RWW-F
#define SATA0_EMU5_0_IMP_19_FIELD                          (_MK_SHIFT_CONST(0x1) << SATA0_EMU5_0_IMP_19_SHIFT)
#define SATA0_EMU5_0_IMP_19_RANGE                          19:19
#define SATA0_EMU5_0_IMP_19_WOFFSET                        0
#define SATA0_EMU5_0_IMP_19_DEFAULT                        (_MK_MASK_CONST(0x00000000)
#define SATA0_EMU5_0_IMP_19_DEFAULT_MASK                   (_MK_MASK_CONST(0x1)
#define SATA0_EMU5_0_IMP_19_SW_DEFAULT                     (_MK_MASK_CONST(0x00000000)
#define SATA0_EMU5_0_IMP_19_SW_DEFAULT_MASK                (_MK_MASK_CONST(0x1)
#define SATA0_EMU5_0_IMP_19_INIT                           _MK_ENUM_CONST(0x00000000)                                                       // RWW-V
#define SATA0_EMU5_0_RXCLK_IB_DELAY_SHIFT                   _MK_SHIFT_CONST(20)                                                             // RWW-F
#define SATA0_EMU5_0_RXCLK_IB_DELAY_FIELD                  (_MK_SHIFT_CONST(0x7) << SATA0_EMU5_0_RXCLK_IB_DELAY_SHIFT)
#define SATA0_EMU5_0_RXCLK_IB_DELAY_RANGE                  22:20
#define SATA0_EMU5_0_RXCLK_IB_DELAY_WOFFSET                0
#define SATA0_EMU5_0_RXCLK_IB_DELAY_DEFAULT                (_MK_MASK_CONST(0x00000000)
#define SATA0_EMU5_0_RXCLK_IB_DELAY_DEFAULT_MASK           (_MK_MASK_CONST(0x7)
#define SATA0_EMU5_0_RXCLK_IB_DELAY_SW_DEFAULT             (_MK_MASK_CONST(0x00000000)
#define SATA0_EMU5_0_RXCLK_IB_DELAY_SW_DEFAULT_MASK        (_MK_MASK_CONST(0x7)
#define SATA0_EMU5_0_RXCLK_IB_DELAY_INIT                   _MK_ENUM_CONST(0x00000000)                                                       // RWW-V
#define SATA0_EMU5_0_RESERVED2_SHIFT                        _MK_SHIFT_CONST(23)                                                             // C---F
#define SATA0_EMU5_0_RESERVED2_FIELD                       (_MK_SHIFT_CONST(0x1) << SATA0_EMU5_0_RESERVED2_SHIFT)
#define SATA0_EMU5_0_RESERVED2_RANGE                       23:23
#define SATA0_EMU5_0_RESERVED2_WOFFSET                     0
#define SATA0_EMU5_0_RESERVED2_0                           _MK_ENUM_CONST(0x00000000)                                                       // C---V
// .LABEL EMULATION
// 
// 
//  31           24 23           16 15            8 7             0
// .-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-.
// |                                                               | EMU_6
// +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
// 
#define SATA0_EMU6_0                                       0x00000C14                                                                       // RW-4R
#define SATA0_EMU6_0_SECURE                                0
#define SATA0_EMU6_0_WORD_COUNT                            1
#define SATA0_EMU6_0_RESET_VAL                             0x0
#define SATA0_EMU6_0_RESET_MASK                            0x0
#define SATA0_EMU6_0_SW_DEFAULT_VAL                        0x0
#define SATA0_EMU6_0_SW_DEFAULT_MASK                       0x0
#define SATA0_EMU6_0_READ_MASK                             0xffffffff
#define SATA0_EMU6_0_WRITE_MASK                            0xffffffff
#define SATA0_EMU6_0_EMU_BUS_3_SEL_SHIFT                    _MK_SHIFT_CONST(24)                                                             // RW--F
#define SATA0_EMU6_0_EMU_BUS_3_SEL_FIELD                   (_MK_SHIFT_CONST(0xff) << SATA0_EMU6_0_EMU_BUS_3_SEL_SHIFT)
#define SATA0_EMU6_0_EMU_BUS_3_SEL_RANGE                   31:24
#define SATA0_EMU6_0_EMU_BUS_3_SEL_WOFFSET                 0
#define SATA0_EMU6_0_EMU_BUS_3_SEL_INIT                    _MK_ENUM_CONST(0x00000003)                                                       // RW--V
#define SATA0_EMU6_0_EMU_BUS_2_SEL_SHIFT                    _MK_SHIFT_CONST(16)                                                             // RW--F
#define SATA0_EMU6_0_EMU_BUS_2_SEL_FIELD                   (_MK_SHIFT_CONST(0xff) << SATA0_EMU6_0_EMU_BUS_2_SEL_SHIFT)
#define SATA0_EMU6_0_EMU_BUS_2_SEL_RANGE                   23:16
#define SATA0_EMU6_0_EMU_BUS_2_SEL_WOFFSET                 0
#define SATA0_EMU6_0_EMU_BUS_2_SEL_INIT                    _MK_ENUM_CONST(0x00000002)                                                       // RW--V
#define SATA0_EMU6_0_EMU_BUS_1_SEL_SHIFT                    _MK_SHIFT_CONST(8)                                                              // RW--F
#define SATA0_EMU6_0_EMU_BUS_1_SEL_FIELD                   (_MK_SHIFT_CONST(0xff) << SATA0_EMU6_0_EMU_BUS_1_SEL_SHIFT)
#define SATA0_EMU6_0_EMU_BUS_1_SEL_RANGE                   15:8
#define SATA0_EMU6_0_EMU_BUS_1_SEL_WOFFSET                 0
#define SATA0_EMU6_0_EMU_BUS_1_SEL_INIT                    _MK_ENUM_CONST(0x00000000)                                                       // RW--V
#define SATA0_EMU6_0_EMU_BUS_0_SEL_SHIFT                    _MK_SHIFT_CONST(0)                                                              // RW--F
#define SATA0_EMU6_0_EMU_BUS_0_SEL_FIELD                   (_MK_SHIFT_CONST(0xff) << SATA0_EMU6_0_EMU_BUS_0_SEL_SHIFT)
#define SATA0_EMU6_0_EMU_BUS_0_SEL_RANGE                   7:0
#define SATA0_EMU6_0_EMU_BUS_0_SEL_WOFFSET                 0
#define SATA0_EMU6_0_EMU_BUS_0_SEL_INIT                    _MK_ENUM_CONST(0x00000000)                                                       // RW--V
// .LABEL EMULATION
// 
// 
//  31           24 23           16 15            8 7             0
// .-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-.
// |                                                               | EMU_7
// +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
// 
#define SATA0_EMU7_0                                       0x00000C18                                                                       // R-W4R
#define SATA0_EMU7_0_SECURE                                0
#define SATA0_EMU7_0_WORD_COUNT                            1
#define SATA0_EMU7_0_RESET_VAL                             0x0
#define SATA0_EMU7_0_RESET_MASK                            0x0
#define SATA0_EMU7_0_SW_DEFAULT_VAL                        0x0
#define SATA0_EMU7_0_SW_DEFAULT_MASK                       0x0
#define SATA0_EMU7_0_READ_MASK                             0xffffffff
#define SATA0_EMU7_0_WRITE_MASK                            0x0
#define SATA0_EMU7_0_RESERVED_SHIFT                         _MK_SHIFT_CONST(0)                                                              // C---F
#define SATA0_EMU7_0_RESERVED_FIELD                        (_MK_SHIFT_CONST(0xffffffff) << SATA0_EMU7_0_RESERVED_SHIFT)
#define SATA0_EMU7_0_RESERVED_RANGE                        31:0
#define SATA0_EMU7_0_RESERVED_WOFFSET                      0
#define SATA0_EMU7_0_RESERVED_0                            _MK_ENUM_CONST(0x00000000)                                                       // C---V
// 
//  31           24 23           16 15            8 7             0
// .-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-.
// |                                                               | EMU_8
// +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
// 
#define SATA0_EMU8_0                                       0x00000C1C                                                                       // R-W4R
#define SATA0_EMU8_0_SECURE                                0
#define SATA0_EMU8_0_WORD_COUNT                            1
#define SATA0_EMU8_0_RESET_VAL                             0x0
#define SATA0_EMU8_0_RESET_MASK                            0x0
#define SATA0_EMU8_0_SW_DEFAULT_VAL                        0x0
#define SATA0_EMU8_0_SW_DEFAULT_MASK                       0x0
#define SATA0_EMU8_0_READ_MASK                             0xffffffff
#define SATA0_EMU8_0_WRITE_MASK                            0x0
#define SATA0_EMU8_0_RESERVED_SHIFT                         _MK_SHIFT_CONST(0)                                                              // C---F
#define SATA0_EMU8_0_RESERVED_FIELD                        (_MK_SHIFT_CONST(0xffffffff) << SATA0_EMU8_0_RESERVED_SHIFT)
#define SATA0_EMU8_0_RESERVED_RANGE                        31:0
#define SATA0_EMU8_0_RESERVED_WOFFSET                      0
#define SATA0_EMU8_0_RESERVED_0                            _MK_ENUM_CONST(0x00000000)                                                       // C---V
// 
//  31           24 23           16 15            8 7             0
// .-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-.
// |                                                               | EMU_9
// +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
// 
#define SATA0_EMU9_0                                       0x00000C20                                                                       // R-W4R
#define SATA0_EMU9_0_SECURE                                0
#define SATA0_EMU9_0_WORD_COUNT                            1
#define SATA0_EMU9_0_RESET_VAL                             0x0
#define SATA0_EMU9_0_RESET_MASK                            0x0
#define SATA0_EMU9_0_SW_DEFAULT_VAL                        0x0
#define SATA0_EMU9_0_SW_DEFAULT_MASK                       0x0
#define SATA0_EMU9_0_READ_MASK                             0xffffffff
#define SATA0_EMU9_0_WRITE_MASK                            0x0
#define SATA0_EMU9_0_RESERVED_SHIFT                         _MK_SHIFT_CONST(0)                                                              // C---F
#define SATA0_EMU9_0_RESERVED_FIELD                        (_MK_SHIFT_CONST(0xffffffff) << SATA0_EMU9_0_RESERVED_SHIFT)
#define SATA0_EMU9_0_RESERVED_RANGE                        31:0
#define SATA0_EMU9_0_RESERVED_WOFFSET                      0
#define SATA0_EMU9_0_RESERVED_0                            _MK_ENUM_CONST(0x00000000)                                                       // C---V
// 
// 
// APPENDIX A  -  PCI CONFIGURATION SPACE MEMORY MAP
// This is device specific. Any legacy registers or memory will need to be
// added by modifying the PCI block.
// 
// CONFIG space is accessed via the PCI Configuration access mechanism.
// 
// Address Name        Description
// Range:    0x000 - 255(0FFh) standard config space
// ------- --------------- -----------------------------------------------------
// 0x000    CFG_0        PCI Vendor and Device ID register            S
// 0x004    CFG_1        PCI Device Control Register                  S
// 0x008    CFG_2        PCI Revision ID and Class Code Register            S
// 0x00C    CFG_3        PCI Configuration Register 0Ch               S
// ----
// 0x010    CFG_4        I/O Base Address Register                     S
// 0x014    CFG_5        I/O Base Address Register                    S
// 0x018    CFG_6        I/O Base Address Register                   S
// 0x01C    CFG_7        I/O Base Address Register                   S
// ----
// 0x020    CFG_8        I/O Base Address Register                     S
// 0x024    CFG_9        Memory Base Address Register                 S
// 0x028    CFG_10        Usused Cardbus CIS pointer                         S
// 0x02C    CFG_11        PCI Subsystem Vendor ID and Subsystem ID Register     S
// ----
// 0x030    CFG_12        Expansion ROM Base Address Configuration Register     S
// 0x034    CFG_13        PCI Capability Pointer Register              S
// 0x038    CFG_14        PCI Configuration Register 38h               S
// 0x03C    CFG_15        PCI Configuration Register 3Ch              S
// ----
// 0x040    CFG_16        Write Subsystem Vendor ID and Subsystem ID register    PRIV
// 0x044    CFG_17        PCI Power Management Capabilities Register        PWR
// 0x048    CFG_18        PCI Power Management Control/Status Register        PWR
// 0x04C
// ----
// 0x050   PCIE_CAP        The PCI Express Capability List Register                PCIE
// 0x054   DEV_CAP         Device Capabilities Register                            PCIE
// 0x058   DEV_CTRL_STAT   Device Control and Status Register                      PCIE
// 0x05C   LINK_CAP        The Link Capabilities Register                          PCIE
// ----
// 0x060   LINK_CTRL_STAT  Link Control and Status Register                        PCIE
// 0x064
// .....    Reserved    Unused reserved registers from the PCIE Cap List    PCIE
// 0x06C
// ----
// 0x070
// .....    Reserved        Unused reserved registers from the PCIE Cap List        PCIE
// 0x07C
// ----
// 0x080   Reserved        Unused reserved registers from the PCIE Cap List        PCIE
// 0x084   Reserved        Unused reserved registers from the PCIE Cap List        PCIE
// 0x088   Reserved        Unused reserved registers from the PCIE Cap List        PCIE
// 0x08C   ATACAP0        Serial ATA Capability Register 0            ATA
// ----
// 0x090   ATACAP1       Serial ATA Capability Register 1            ATA
// 0x094   CFG_35        Serial ATA IDP Index register                ATA
// 0x098   AHCI_IDP1    Serial ATA IDP Data register                ATA
// 0x09C   CYA1                                    PRIV
// ----
// 0x0B0   MSI_CTRL    MSI Message Control and Capability Register         MSI
// 0x0B4    MSI_ADDR1    MSI Message Address Register                        MSI
// 0x0B8    MSI_ADDR2    MSI Message Upper Address Register                 MSI
// 0x0BC    MSI_DATA    MSI Message Data Register                MSI
// ----
// 0x0C0    MSI_QUEUE    MSI Queue control Register                             MSI
// 0x0C4    MSIX_CTL    MSI-X Message Control and Capability Register           MSIX
// 0x0C8    MSIX_TBL    MSI-X Table Offset and BIR Register                     MSIX
// 0x0CC    MSIX_PBA    MSI-X Pending Bit Array (PBA) Offset and BIR Register   MSIX
// ----
// 0x0E0
// 0x0E4
// 0x0E8
// 0x0EC   MSI_MAP        MSI Mapping Capability Register                         MAP
// ----
// 0x0F0   INDIRECT_IDP0                                                           PRIV
// 0x0F4   INDIRECT_IDP1                                                           PRIV
// 0x0F8   PXBCFG        PXB Wrapper config register                PRIV
// 0x0FC   SCRATCH_1                                                               PRIV
// ----
// 0x100   PCIE_ECAP       PCI Express Extended Capability Register        PCIE
// 
// ------- --------------- -----------------------------------------------------
// 
// ###########################################################################################
//      257-2K   Standard config space, capabilities, Index-data pair to access BAR5 (AHCI), CYA
//      104-7FC  Index-data pair to access beyond 256bytes of config space,
//     we start adding registers from 0X110h
//             -0X110 - 0X278 - 91 DWORDS - for config, perf
//             -0X27C - 0X3FC - 97 Dwords for CHX, signals to pads
// ###########################################################################################
// 0x110 - 0x16C - CFG,CYA PHY registers - 24 DWords
// 0x114 - NVOOB             - comwake/cominit/squelch
// 0x118 - CROSS_BAR         - phy_sel of cross bar
// 0x11C - PMUCTL
// 0x120 - CFG_PHY_0
// -------
// 0x124 - CFG_PHY_POWER
// 0x128 - CFG_PHY_POWER_1
// ------- --------------- -----------------------------------------------------
// 0x170 - 0x1CC - CFG,CYA LINK registers - 24 DWords
// 0x170 - FIFO             - link<->PHY fifo depths
// 0x174 - CFG_LINK_0
// 0x178 - CFG_LINK_1
// ------- --------------- -----------------------------------------------------
// 0x1D0 - 0x22C - CFG, CYA TRANS registers - 24 DWords
// 0x1D0 - CFG_TRANS_0
// ------- --------------- -----------------------------------------------------
// 0x230 - 0x36C - CFG, CYA AHCI registers - 80 DWords
// 0x230 - AES_CTRL         - bypass control for CH1/2
// 0x234 - ALPM_CTRL         - HIPM control
// 0x238 - FBS_CONFIG_0    - FBS related register
// 0x23C - FBS_CONFIG_1    - FBS related register
// -------
// 0x240 - AES_EN_OPCODES_0
// 0x244 - AES_EN_OPCODES_1
// 0x248 - AES_EN_OPCODES_2
// 0x24C - AES_EN_OPCODES_3
// ------
// 0x250 - AES_EN_OPCODES_4
// 0x254 - AES_EN_OPCODES_5
// 0x258 - AES_EN_OPCODES_6
// 0x25C - AES_EN_OPCODES_7
// -------
// 0x260 - AES_KEY1_0
// 0x264 - AES_KEY1_1
// 0x268 - AES_KEY1_2
// 0x26C - AES_KEY1_3
// -------
// 0x270 - AES_KEY1_4
// 0x274 - AES_KEY1_5
// 0x278 - AES_KEY1_6
// 0x27C - AES_KEY1_7
// -------
// 0x280 - AES_KEY2_0
// 0x284 - AES_KEY2_1
// 0x288 - AES_KEY2_2
// 0x28C - AES_KEY2_3
// -------
// 0x290 - AES_KEY2_4
// 0x294 - AES_KEY2_5
// 0x298 - AES_KEY2_6
// 0x29C - AES_KEY2_7
// -------
// 0x300 - AHCI_HBA_CAP_BKDR
// 0x304 - AHCI_HBA_HOLD_GEN
// 0x308 - AHCI_HBA_PER_PRT_RESET
// 0x30C - AHCI_HBA_CTL_0
// -------
// 0x310 - AHCI_HBA_NVMHCI_CAP_BKDR
// 0x314 - HBA_NVMHCI_CYA_0
// 0x318 - HBA_BIST_OVERRIDE_CTL
// 0x31C - HBA_BIST_DWORD
// -------
// 0x320 - HBA_SPARE_1
// 0x324 - HBA_SPARE_2
// 0x328 - HBA_DYN_CLAMP
// 0x32C - AHCI_CFG_ERR_CTRL - AHCI SM error conditions
// -------
// 0x330 - AHCI_HBA_CAP2_BKDR
// 0x338 - AHCI_HBA_CTL_1
// 0x33C - AHCI_HBA_PI_BKDR
// ------- --------------- -----------------------------------------------------
// 0x370 - 0x3CC - CFG, CYA SHADOW registers - 24 DWords
// 0x370 - CFG             - timeout for MASTER - used in Shadow register
// 0x374 - CFG_ATAPI
// 0x378 - CYA_SHADOW
// ------- --------------- -----------------------------------------------------
// 0x3D0 - 0x42C - CFG, CYA BM registers - 24 DWords
// ------- --------------- -----------------------------------------------------
// 0x430 - 0x48C - CFG, CYA FPCI registers - 24 DWords
// 0x430 - CFG_FPCI_0
// ------- --------------- -----------------------------------------------------
// 0x490 - 0x4EC - CFG, CYA Common registers - 24 DWords
// 0x490 - IDE1
// 0x494 - CFG_ESATA_CTRL
// 0x498 - FUSE
// 0x49C - BKDOOR_CYA_0     - class code for DMI controller
// -----
// -------
// 0x4A0 - CYA1
// 0x4A4 - BKDOOR_CC
// 0x4A8 -
// 0x4AC - CFG_POWER_GATE
// -----
// 0x4B0 - CFG_CTL_GLUE
// )x4BC - CFG_CTL_FA
// ------- --------------- -----------------------------------------------------
// 0x4F0 - 0x50C - CFG PERF registers - 8 DWords
// 0x4F0 - PERF0             - performance related to power tuning
// 0x4F4 - PERF1             - related to FIFOs
// ------- --------------- -----------------------------------------------------
// 0x510 - 0x51C - CFG PARITY registers - 4 DWords
// 0x510 - FPCI_PERR_STS
// ------- --------------- -----------------------------------------------------
// 0x520 - 0x52C - SPARE registers - 4 DWords
// 0x520 - SPARE_0
// 0x524 - SPARE_1
// 0x528 - SPARE_2
// 0x52C - SPARE_3
// ------- --------------- -----------------------------------------------------
// 0X530 - 0X57C - others - 20 DWords
// 0x530 - CHXCFG1 - needs to broken up - moved some, others dangling
// 0x534 - PHY_CTRL - needs to be broken up - moved some, others dangling
// 0x538 - LINK0 - needs to be broken up, removed
// 0x53C - LDT - to be removed
// -------
// 0x540 - CTRL - needs to be broken up, will be done in next checkin
// 0x544 - IDE2 - to be removed
// 0x548 - IDE3 - to be removed
// 0x54C - SATA - to be combined/broken with others - in next checkin
// -------
// 0x550 - CFG_MISC - contains link/phy/trans - this is cfg register
// ------- --------------- -----------------------------------------------------
// 0x580 - 0x67C - REMAINING - 64 DWords
// 0x580 - AO_SPARE_0
// 0x584 - AO_SPARE_1
// ------- --------------- -----------------------------------------------------
// #############################################################################
// FROM here pad controls/ CHX registers start
// #############################################################################
// 0x680 - 0x6AC - MISC registers - 12 DWords
// 0x680 - CHX_MISC         - pad controls
// ------- --------------- -----------------------------------------------------
// 0x6B0 - 0x6DC - PHY CTRL_PAIR2LANE registers - 12 DWords
// 0x6B0 - PHY COMMON        - pad controls
// ------- --------------- -----------------------------------------------------
// 0x6E0 - 0x698 - REMAINING - 7 DWords
// ------- --------------- -----------------------------------------------------
// 0x69C - Masks to channel specific - 1 DWord
// 0x69C - INDEX
// ------- --------------- -----------------------------------------------------
// 0x700 - 0x74C - CHX PHY registers - 20 DWords
// 0x700 - CHXCFG3         - BIST related
// 0x704 - CHXCFG4_CHX     - PHY ALIGN count
// 0x708 - CHX_PHY_CTRL         - pad control signals
// 0x70C - CHX_PHY_CTRL1_GEN1   - TX_AMP, TX_PEAK - pad controls
// -------
// 0x710 - CHX_PHY_CTRL_NEW    - pad controls
// 0x714 - PRBS_CHX         - IOBIST
// 0x718 - CH_PHY_CTRL1_GEN2   - TX_AMP, TX_PEAK - pad controls
// 0x71C - CHX_PHY_CTRL1_GEN3   - TX_AMP, TX_PEAK - pad controls
// ------- --------------- -----------------------------------------------------
// 0x750 - 0x76C - CHX LINK registers - 8 DWords
// 0x750 - CHX_LINK0
// ------- --------------- -----------------------------------------------------
// 0x770 - 0x78C - CHX TRANS registers - 8 DWords
// ------- --------------- -----------------------------------------------------
// 0x790 - 0x7AC - CHX AHCI registers - 8 DWords
// 0x790 - CHX_AHCI_PORT_PXTFD_BKDR
// 0x794 - CHX_AHCI_PORT_PXSIG_BKDR
// 0x798 - CHX_AHCI_PORT_PXSSTS_BKDR
// ------- --------------- -----------------------------------------------------
// 0x7B0 - 0x7CC - CHX SHADOW registers - 8 DWords
// ------- --------------- -----------------------------------------------------
// 0x7D0 - 0x7EC - CHX BM registers - 8 DWords
// ------- --------------- -----------------------------------------------------
// 0x7F0 - 0x7FC - Remaining registers - 4 DWords
// 0x7F0 - CHX_GLUE
// ------- --------------- -----------------------------------------------------
// 
// ##########################END of 256 - 2k##################################################
// 
// ########################## 2K - 3K - DEBUG ##################################################
// ------- --------------- -----------------------------------------------------
// 0x800 - 0x80C - Final Debug bus output selects - 4DWords
// ------- --------------- -----------------------------------------------------
// 0x820 - 0x828 DEBUG selects - 3 DWords
// ------- --------------- -----------------------------------------------------
// 0x830 - 0x87C - PHY DEBUG registers - 20 DWords
// ------- --------------- -----------------------------------------------------
// 0x880 - 0x8CC - LINK DEBUG registers - 20 DWords
// ------- --------------- -----------------------------------------------------
// 0x8D0 - 0x91C - TRANS DEBUG registers - 20 DWords
// ------- --------------- -----------------------------------------------------
// 0x910 - 0x9CC - AHCI DEBUG registers - 48 DWords
// ------- --------------- -----------------------------------------------------
// 0x9D0 - 0xA1C - BM DEBUG registers - 20 DWords
// 0x9D0 - BM0
// 0x9D4 - BM1
// 0x9F0 - BM8
// 0X9F4 - CHXCFG2
// ------- --------------- -----------------------------------------------------
// 0xA20 - 0xA6C - SHAD DEBUG registers - 20 DWords
// ------- --------------- -----------------------------------------------------
// 0xA70 - 0xABC - PXB DEBUG registers - 20 DWords
// ------- --------------- -----------------------------------------------------
// 0xAC0 - 0xB84 - DEBUG other registers - 50 DWords
// 0xAC0 - INTR             - to be removed
// 0xAC4 - PORT0_STATES
// 0xAC8 - PORT1_STATES
// ------- --------------- -----------------------------------------------------
// 0xB88 - 0xB8C - DEBUG SPARE registers - 2 DWords
// ------- --------------- -----------------------------------------------------
// 0xB90 - 0xBFC - DEBUG REM registers - 28 DWords
// ------- --------------- -----------------------------------------------------
// ##########################END of 2K - 3K - DEBUG#############################################
// 
// ##########################2K - 3K - EMULATION ###############################################
// RANGE : 3K(C00) - 4K(9FF) - Emulation specific, Debug registers
// 0xC00   EMU1
// 0xC04   EMU2
// 0xC08   EMU3
// 0xC0C   EMU4
// 0xC10   EMU5
// 0xC14   EMU6
// 0xC18   EMU7
// 0xC1C   EMU8
// 0xC20   EMU9
// ##########################END OF 2K - 3K - EMULATION ########################################
// 
// 
// 
// 
// S    = PCI base standard configuration registers
// PWR  = PCI Power management configuration registers
// MSI  = PCI MSI Configuration Registers
// MAP  = HT MSI Mapping Registers
// MSIX = PCI MSI-X Configuration Registers
// PCIE = PCI Express Configuration Registers
// PRIV = Device Specific Registers
// D    = Debug Registers
// 
// 
// 
// 
// 
// 
// 
// 
// 
// 
// 
// 
// 
// 
// 
// 
// 
// 
// 
// 
// 
// 
// 
// 
// 
// 
// 
// 
// 
// 
// 
// 
// 
// 
// 
// 
// 

// REGISTER LIST

#define LIST_SATA0_REGS(_op_) \
  _op_(SATA0_CFG_0_0) \
  _op_(SATA0_CFG_1_0) \
  _op_(SATA0_CFG_2_0) \
  _op_(SATA0_CFG_3_0) \
  _op_(SATA0_CFG_4_0) \
  _op_(SATA0_CFG_5_0) \
  _op_(SATA0_CFG_6_0) \
  _op_(SATA0_CFG_7_0) \
  _op_(SATA0_CFG_8_0) \
  _op_(SATA0_CFG_9_0) \
  _op_(SATA0_CFG_10_0) \
  _op_(SATA0_CFG_11_0) \
  _op_(SATA0_CFG_12_0) \
  _op_(SATA0_CFG_13_0) \
  _op_(SATA0_CFG_14_0) \
  _op_(SATA0_CFG_15_0) \
  _op_(SATA0_CFG_16_0) \
  _op_(SATA0_CFG_17_0) \
  _op_(SATA0_CFG_18_0) \
  _op_(SATA0_FPCI_DBG_0_0) \
  _op_(SATA0_FPCI_DBG_1_0) \
  _op_(SATA0_FPCI_SW_0) \
  _op_(SATA0_ATACAP0_0) \
  _op_(SATA0_ATACAP1_0) \
  _op_(SATA0_CFG_35_0) \
  _op_(SATA0_AHCI_IDP1_0) \
  _op_(SATA0_MSI_CTRL_0) \
  _op_(SATA0_MSI_ADDR1_0) \
  _op_(SATA0_MSI_ADDR2_0) \
  _op_(SATA0_MSI_DATA_0) \
  _op_(SATA0_MSI_QUEUE_0) \
  _op_(SATA0_MSI_MAP_0) \
  _op_(SATA0_INDIRECT_IDP0_0) \
  _op_(SATA0_INDIRECT_IDP1_0) \
  _op_(SATA0_FPCICFG_0) \
  _op_(SATA0_SCRATCH_1_0) \
  _op_(SATA0_NVOOB_0) \
  _op_(SATA0_CROSS_BAR_0) \
  _op_(SATA0_PMUCTL_0) \
  _op_(SATA0_CFG_PHY_0_0) \
  _op_(SATA0_CFG_PHY_POWER_0) \
  _op_(SATA0_CFG_PHY_POWER_1_0) \
  _op_(SATA0_CFG_PHY_1_0) \
  _op_(SATA0_CFG2NVOOB_1_0) \
  _op_(SATA0_CFG2NVOOB_2_0) \
  _op_(SATA0_CFG_PHY_ACTIVE_0) \
  _op_(SATA0_FIFO_0) \
  _op_(SATA0_CFG_LINK_0_0) \
  _op_(SATA0_CFG_LINK_1_0) \
  _op_(SATA0_CFG_LINK_2_0) \
  _op_(SATA0_CFG_TRANS_0_0) \
  _op_(SATA0_ALPM_CTRL_0) \
  _op_(SATA0_FBS_CONFIG_0_0) \
  _op_(SATA0_CHX_FBS_CONFIG_1_0) \
  _op_(SATA0_AHCI_HBA_CAP_BKDR_0) \
  _op_(SATA0_AHCI_HBA_HOLD_GEN_0) \
  _op_(SATA0_AHCI_HBA_CYA_0_0) \
  _op_(SATA0_AHCI_HBA_BIST_OVERRIDE_CTL_0) \
  _op_(SATA0_AHCI_HBA_BIST_DWORD_0) \
  _op_(SATA0_AHCI_HBA_SPARE_1_0) \
  _op_(SATA0_AHCI_HBA_SPARE_2_0) \
  _op_(SATA0_AHCI_HBA_DYN_CLK_CLAMP_0) \
  _op_(SATA0_AHCI_CFG_ERR_CTRL_0) \
  _op_(SATA0_AHCI_HBA_CAP2_BKDR_0) \
  _op_(SATA0_AHCI_HBA_CYA_1_0) \
  _op_(SATA0_AHCI_HBA_PI_BKDR_0) \
  _op_(SATA0_AHCI_HBA_PRE_STAGING_CONTROL_0) \
  _op_(SATA0_CFG_0) \
  _op_(SATA0_CYA_SHADOW_0) \
  _op_(SATA0_CFG_FPCI_0_0) \
  _op_(SATA0_IDE1_0) \
  _op_(SATA0_CFG_ESATA_CTRL_0) \
  _op_(SATA0_FUSE_0) \
  _op_(SATA0_CYA1_0) \
  _op_(SATA0_BKDOOR_CC_0) \
  _op_(SATA0_CFG_CTRL_1_0) \
  _op_(SATA0_CFG_POWER_GATE_0) \
  _op_(SATA0_CFG_CTL_GLUE_0) \
  _op_(SATA0_CFG_CTL_FA_0) \
  _op_(SATA0_PERF0_0) \
  _op_(SATA0_PERF1_0) \
  _op_(SATA0_SPARE_0_0) \
  _op_(SATA0_SPARE_1_0) \
  _op_(SATA0_SPARE_2_0) \
  _op_(SATA0_SPARE_3_0) \
  _op_(SATA0_CHXCFG1_0) \
  _op_(SATA0_PHY_CTRL_0) \
  _op_(SATA0_LDT_0) \
  _op_(SATA0_CTRL_0) \
  _op_(SATA0_CFG_SATA_0) \
  _op_(SATA0_DBG0_0) \
  _op_(SATA0_LOWPOWER_COUNT_0) \
  _op_(SATA0_DEVSLP_CTRL0_0) \
  _op_(SATA0_AO_SPARE_0_0) \
  _op_(SATA0_AO_SPARE_1_0) \
  _op_(SATA0_INDEX_0) \
  _op_(SATA0_CHX_MISC_0) \
  _op_(SATA0_CHX_PHY_CTRL1_GEN1_0) \
  _op_(SATA0_CHX_PHY_CTRL1_GEN2_0) \
  _op_(SATA0_CHX_PHY_CTRL1_GEN3_0) \
  _op_(SATA0_CHX_PHY_CTRL2_0) \
  _op_(SATA0_CHX_PHY_CTRL24_0) \
  _op_(SATA0_CHX_PHY_CTRL25_0) \
  _op_(SATA0_CHX_PHY_CTRL26_0) \
  _op_(SATA0_CHX_PHY_CTRL3_0) \
  _op_(SATA0_CHX_PHY_CTRL4_0) \
  _op_(SATA0_CHX_PHY_CTRL5_0) \
  _op_(SATA0_CHX_PHY_CTRL6_0) \
  _op_(SATA0_CHX_PHY_CTRL7_0) \
  _op_(SATA0_CHX_PHY_CTRL8_0) \
  _op_(SATA0_CHX_PHY_CTRL9_0) \
  _op_(SATA0_CHX_PHY_CTRL10_0) \
  _op_(SATA0_CHX_PHY_CTRL11_0) \
  _op_(SATA0_CHX_PHY_CTRL12_0) \
  _op_(SATA0_CHX_PHY_CTRL13_0) \
  _op_(SATA0_CHX_PHY_CTRL14_0) \
  _op_(SATA0_CHX_PHY_CTRL15_0) \
  _op_(SATA0_CHX_PHY_CTRL16_0) \
  _op_(SATA0_CHX_PHY_CTRL17_0) \
  _op_(SATA0_CHX_PHY_CTRL18_0) \
  _op_(SATA0_CHX_PHY_CTRL19_0) \
  _op_(SATA0_CHX_PHY_CTRL20_0) \
  _op_(SATA0_CHX_PHY_CTRL21_0) \
  _op_(SATA0_CHX_PHY_CTRL22_0) \
  _op_(SATA0_CHXCFG3_0) \
  _op_(SATA0_CHXCFG4_CHX_0) \
  _op_(SATA0_PRBS_CHX_0) \
  _op_(SATA0_CHX_PHY_CTRL23_0) \
  _op_(SATA0_CHX_LINK0_0) \
  _op_(SATA0_CHX_AHCI_PORT_PXTFD_BKDR_0) \
  _op_(SATA0_CHX_AHCI_PORT_PXSIG_BKDR_0) \
  _op_(SATA0_CHX_AHCI_PORT_PXSSTS_BKDR_0) \
  _op_(SATA0_CHX_GLUE_0) \
  _op_(SATA0_DBG_31_0_0) \
  _op_(SATA0_DBG_63_32_0) \
  _op_(SATA0_DBG_95_64_0) \
  _op_(SATA0_DBG_127_96_0) \
  _op_(SATA0_DBG_CH_SELECT_0) \
  _op_(SATA0_AHCI_DBG_31_0_0) \
  _op_(SATA0_AHCI_DBG_63_32_0) \
  _op_(SATA0_AHCI_DBG_95_64_0) \
  _op_(SATA0_PHY_DBG_0_0) \
  _op_(SATA0_PHY_LPM_TRACKER_CTRL_0) \
  _op_(SATA0_PHY_LPM_TRACKER_COUNT_0) \
  _op_(SATA0_AHCI_FBS_DBG_0_0) \
  _op_(SATA0_BM0_0) \
  _op_(SATA0_BM1_0) \
  _op_(SATA0_BM2_0) \
  _op_(SATA0_BM3_0) \
  _op_(SATA0_BM4_0) \
  _op_(SATA0_BM5_0) \
  _op_(SATA0_BM6_0) \
  _op_(SATA0_BM7_0) \
  _op_(SATA0_BM8_0) \
  _op_(SATA0_CHXCFG2_0) \
  _op_(SATA0_INTR_0) \
  _op_(SATA0_CHX_PORT_STATES_0) \
  _op_(SATA0_EMU1_0) \
  _op_(SATA0_EMU2_0) \
  _op_(SATA0_EMU3_0) \
  _op_(SATA0_EMU4_0) \
  _op_(SATA0_EMU5_0) \
  _op_(SATA0_EMU6_0) \
  _op_(SATA0_EMU7_0) \
  _op_(SATA0_EMU8_0) \
  _op_(SATA0_EMU9_0) 


#ifndef _MK_SHIFT_CONST
  #define _MK_SHIFT_CONST(_constant_) _constant_
#endif
#ifndef _MK_MASK_CONST
  #define _MK_MASK_CONST(_constant_) _constant_
#endif
#ifndef _MK_ENUM_CONST
  #define _MK_ENUM_CONST(_constant_) (_constant_ ## UL)
#endif
#ifndef _MK_ADDR_CONST
  #define _MK_ADDR_CONST(_constant_) _constant_
#endif

#endif
