//
// Copyright (c) 2018 NVIDIA Corporation.
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are met:
//
// Redistributions of source code must retain the above copyright notice,
// this list of conditions and the following disclaimer.
//
// Redistributions in binary form must reproduce the above copyright notice,
// this list of conditions and the following disclaimer in the documentation
// and/or other materials provided with the distribution.
//
// Neither the name of the NVIDIA Corporation nor the names of its contributors
// may be used to endorse or promote products derived from this software
// without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
// POSSIBILITY OF SUCH DAMAGE.
//

//
// DO NOT EDIT - generated by simspec!
//

#ifndef ___ARMISCREG_H_INC_
#define ___ARMISCREG_H_INC_
#define NV_MOBILE_ARMISCREG_H_UNIT_OF_OFFSET 1B


// Register MISCREG_MODS_REDIRCT_0
#define MISCREG_MODS_REDIRCT_0                  _MK_ADDR_CONST(0x0)
#define MISCREG_MODS_REDIRCT_0_SECURE                   0x0
#define MISCREG_MODS_REDIRCT_0_DUAL                     0x0
#define MISCREG_MODS_REDIRCT_0_SCR                      0
#define MISCREG_MODS_REDIRCT_0_WORD_COUNT                       0x1
#define MISCREG_MODS_REDIRCT_0_RESET_VAL                        _MK_MASK_CONST(0xe7f000f0)
#define MISCREG_MODS_REDIRCT_0_RESET_MASK                       _MK_MASK_CONST(0xffffffff)
#define MISCREG_MODS_REDIRCT_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define MISCREG_MODS_REDIRCT_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define MISCREG_MODS_REDIRCT_0_READ_MASK                        _MK_MASK_CONST(0xffffffff)
#define MISCREG_MODS_REDIRCT_0_WRITE_MASK                       _MK_MASK_CONST(0x0)
#define MISCREG_MODS_REDIRCT_0_VAL_SHIFT                        _MK_SHIFT_CONST(0)
#define MISCREG_MODS_REDIRCT_0_VAL_FIELD                        _MK_FIELD_CONST(0xffffffff, MISCREG_MODS_REDIRCT_0_VAL_SHIFT)
#define MISCREG_MODS_REDIRCT_0_VAL_RANGE                        31:0
#define MISCREG_MODS_REDIRCT_0_VAL_WOFFSET                      0x0
#define MISCREG_MODS_REDIRCT_0_VAL_DEFAULT                      _MK_MASK_CONST(0xe7f000f0)
#define MISCREG_MODS_REDIRCT_0_VAL_DEFAULT_MASK                 _MK_MASK_CONST(0xffffffff)
#define MISCREG_MODS_REDIRCT_0_VAL_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define MISCREG_MODS_REDIRCT_0_VAL_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define MISCREG_MODS_REDIRCT_0_VAL_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define MISCREG_MODS_REDIRCT_0_VAL_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)
#define MISCREG_MODS_REDIRCT_0_VAL_INIT_ENUM                    -403701520


// Register MISCREG_HIDREV_0
#define MISCREG_HIDREV_0                        _MK_ADDR_CONST(0x4)
#define MISCREG_HIDREV_0_SECURE                         0x0
#define MISCREG_HIDREV_0_DUAL                   0x0
#define MISCREG_HIDREV_0_SCR                    0
#define MISCREG_HIDREV_0_WORD_COUNT                     0x1
#define MISCREG_HIDREV_0_RESET_VAL                      _MK_MASK_CONST(0x21917)
#define MISCREG_HIDREV_0_RESET_MASK                     _MK_MASK_CONST(0xffffff)
#define MISCREG_HIDREV_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define MISCREG_HIDREV_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define MISCREG_HIDREV_0_READ_MASK                      _MK_MASK_CONST(0xffffff)
#define MISCREG_HIDREV_0_WRITE_MASK                     _MK_MASK_CONST(0x0)
#define MISCREG_HIDREV_0_HIDFAM_SHIFT                   _MK_SHIFT_CONST(0)
#define MISCREG_HIDREV_0_HIDFAM_FIELD                   _MK_FIELD_CONST(0xf, MISCREG_HIDREV_0_HIDFAM_SHIFT)
#define MISCREG_HIDREV_0_HIDFAM_RANGE                   3:0
#define MISCREG_HIDREV_0_HIDFAM_WOFFSET                 0x0
#define MISCREG_HIDREV_0_HIDFAM_DEFAULT                 _MK_MASK_CONST(0x7)
#define MISCREG_HIDREV_0_HIDFAM_DEFAULT_MASK                    _MK_MASK_CONST(0xf)
#define MISCREG_HIDREV_0_HIDFAM_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define MISCREG_HIDREV_0_HIDFAM_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define MISCREG_HIDREV_0_HIDFAM_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define MISCREG_HIDREV_0_HIDFAM_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define MISCREG_HIDREV_0_HIDFAM_GPU                     _MK_ENUM_CONST(0)
#define MISCREG_HIDREV_0_HIDFAM_HANDHELD                        _MK_ENUM_CONST(1)
#define MISCREG_HIDREV_0_HIDFAM_BR_CHIPS                        _MK_ENUM_CONST(2)
#define MISCREG_HIDREV_0_HIDFAM_CRUSH                   _MK_ENUM_CONST(3)
#define MISCREG_HIDREV_0_HIDFAM_MCP                     _MK_ENUM_CONST(4)
#define MISCREG_HIDREV_0_HIDFAM_CK                      _MK_ENUM_CONST(5)
#define MISCREG_HIDREV_0_HIDFAM_VAIO                    _MK_ENUM_CONST(6)
#define MISCREG_HIDREV_0_HIDFAM_APXX_TXX                        _MK_ENUM_CONST(7)

#define MISCREG_HIDREV_0_MAJORREV_SHIFT                 _MK_SHIFT_CONST(4)
#define MISCREG_HIDREV_0_MAJORREV_FIELD                 _MK_FIELD_CONST(0xf, MISCREG_HIDREV_0_MAJORREV_SHIFT)
#define MISCREG_HIDREV_0_MAJORREV_RANGE                 7:4
#define MISCREG_HIDREV_0_MAJORREV_WOFFSET                       0x0
#define MISCREG_HIDREV_0_MAJORREV_DEFAULT                       _MK_MASK_CONST(0x1)
#define MISCREG_HIDREV_0_MAJORREV_DEFAULT_MASK                  _MK_MASK_CONST(0xf)
#define MISCREG_HIDREV_0_MAJORREV_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define MISCREG_HIDREV_0_MAJORREV_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define MISCREG_HIDREV_0_MAJORREV_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define MISCREG_HIDREV_0_MAJORREV_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)
#define MISCREG_HIDREV_0_MAJORREV_RESERVED                      _MK_ENUM_CONST(0)
#define MISCREG_HIDREV_0_MAJORREV_A                     _MK_ENUM_CONST(1)
#define MISCREG_HIDREV_0_MAJORREV_B                     _MK_ENUM_CONST(2)
#define MISCREG_HIDREV_0_MAJORREV_C                     _MK_ENUM_CONST(3)
#define MISCREG_HIDREV_0_MAJORREV_D                     _MK_ENUM_CONST(4)
#define MISCREG_HIDREV_0_MAJORREV_E                     _MK_ENUM_CONST(5)
#define MISCREG_HIDREV_0_MAJORREV_F                     _MK_ENUM_CONST(6)
#define MISCREG_HIDREV_0_MAJORREV_G                     _MK_ENUM_CONST(7)
#define MISCREG_HIDREV_0_MAJORREV_H                     _MK_ENUM_CONST(8)
#define MISCREG_HIDREV_0_MAJORREV_I                     _MK_ENUM_CONST(9)
#define MISCREG_HIDREV_0_MAJORREV_J                     _MK_ENUM_CONST(10)
#define MISCREG_HIDREV_0_MAJORREV_K                     _MK_ENUM_CONST(11)
#define MISCREG_HIDREV_0_MAJORREV_L                     _MK_ENUM_CONST(12)
#define MISCREG_HIDREV_0_MAJORREV_M                     _MK_ENUM_CONST(13)
#define MISCREG_HIDREV_0_MAJORREV_N                     _MK_ENUM_CONST(14)
#define MISCREG_HIDREV_0_MAJORREV_O                     _MK_ENUM_CONST(15)

#define MISCREG_HIDREV_0_CHIPID_SHIFT                   _MK_SHIFT_CONST(8)
#define MISCREG_HIDREV_0_CHIPID_FIELD                   _MK_FIELD_CONST(0xff, MISCREG_HIDREV_0_CHIPID_SHIFT)
#define MISCREG_HIDREV_0_CHIPID_RANGE                   15:8
#define MISCREG_HIDREV_0_CHIPID_WOFFSET                 0x0
#define MISCREG_HIDREV_0_CHIPID_DEFAULT                 _MK_MASK_CONST(0x19)
#define MISCREG_HIDREV_0_CHIPID_DEFAULT_MASK                    _MK_MASK_CONST(0xff)
#define MISCREG_HIDREV_0_CHIPID_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define MISCREG_HIDREV_0_CHIPID_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define MISCREG_HIDREV_0_CHIPID_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define MISCREG_HIDREV_0_CHIPID_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define MISCREG_HIDREV_0_MINORREV_SHIFT                 _MK_SHIFT_CONST(16)
#define MISCREG_HIDREV_0_MINORREV_FIELD                 _MK_FIELD_CONST(0xf, MISCREG_HIDREV_0_MINORREV_SHIFT)
#define MISCREG_HIDREV_0_MINORREV_RANGE                 19:16
#define MISCREG_HIDREV_0_MINORREV_WOFFSET                       0x0
#define MISCREG_HIDREV_0_MINORREV_DEFAULT                       _MK_MASK_CONST(0x2)
#define MISCREG_HIDREV_0_MINORREV_DEFAULT_MASK                  _MK_MASK_CONST(0xf)
#define MISCREG_HIDREV_0_MINORREV_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define MISCREG_HIDREV_0_MINORREV_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define MISCREG_HIDREV_0_MINORREV_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define MISCREG_HIDREV_0_MINORREV_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)
#define MISCREG_HIDREV_0_MINORREV_RESERVED                      _MK_ENUM_CONST(0)
#define MISCREG_HIDREV_0_MINORREV_X01                   _MK_ENUM_CONST(1)
#define MISCREG_HIDREV_0_MINORREV_X02                   _MK_ENUM_CONST(2)
#define MISCREG_HIDREV_0_MINORREV_X03                   _MK_ENUM_CONST(3)
#define MISCREG_HIDREV_0_MINORREV_X04                   _MK_ENUM_CONST(4)
#define MISCREG_HIDREV_0_MINORREV_X05                   _MK_ENUM_CONST(5)
#define MISCREG_HIDREV_0_MINORREV_X06                   _MK_ENUM_CONST(6)
#define MISCREG_HIDREV_0_MINORREV_X07                   _MK_ENUM_CONST(7)
#define MISCREG_HIDREV_0_MINORREV_X08                   _MK_ENUM_CONST(8)
#define MISCREG_HIDREV_0_MINORREV_X09                   _MK_ENUM_CONST(9)
#define MISCREG_HIDREV_0_MINORREV_X10                   _MK_ENUM_CONST(10)
#define MISCREG_HIDREV_0_MINORREV_X11                   _MK_ENUM_CONST(11)
#define MISCREG_HIDREV_0_MINORREV_X12                   _MK_ENUM_CONST(12)
#define MISCREG_HIDREV_0_MINORREV_X13                   _MK_ENUM_CONST(13)
#define MISCREG_HIDREV_0_MINORREV_X14                   _MK_ENUM_CONST(14)
#define MISCREG_HIDREV_0_MINORREV_X15                   _MK_ENUM_CONST(15)

#define MISCREG_HIDREV_0_PRE_SI_PLATFORM_SHIFT                  _MK_SHIFT_CONST(20)
#define MISCREG_HIDREV_0_PRE_SI_PLATFORM_FIELD                  _MK_FIELD_CONST(0xf, MISCREG_HIDREV_0_PRE_SI_PLATFORM_SHIFT)
#define MISCREG_HIDREV_0_PRE_SI_PLATFORM_RANGE                  23:20
#define MISCREG_HIDREV_0_PRE_SI_PLATFORM_WOFFSET                        0x0
#define MISCREG_HIDREV_0_PRE_SI_PLATFORM_DEFAULT                        _MK_MASK_CONST(0x0)
#define MISCREG_HIDREV_0_PRE_SI_PLATFORM_DEFAULT_MASK                   _MK_MASK_CONST(0xf)
#define MISCREG_HIDREV_0_PRE_SI_PLATFORM_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define MISCREG_HIDREV_0_PRE_SI_PLATFORM_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define MISCREG_HIDREV_0_PRE_SI_PLATFORM_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define MISCREG_HIDREV_0_PRE_SI_PLATFORM_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define MISCREG_HIDREV_0_PRE_SI_PLATFORM_SILICON                        _MK_ENUM_CONST(0)
#define MISCREG_HIDREV_0_PRE_SI_PLATFORM_QT                     _MK_ENUM_CONST(1)
#define MISCREG_HIDREV_0_PRE_SI_PLATFORM_SYSTEM_FPGA                    _MK_ENUM_CONST(2)
#define MISCREG_HIDREV_0_PRE_SI_PLATFORM_UNIT_FPGA                      _MK_ENUM_CONST(3)
#define MISCREG_HIDREV_0_PRE_SI_PLATFORM_ASIM_QT                        _MK_ENUM_CONST(4)
#define MISCREG_HIDREV_0_PRE_SI_PLATFORM_ASIM_LINSIM                    _MK_ENUM_CONST(5)
#define MISCREG_HIDREV_0_PRE_SI_PLATFORM_DSIM_ASIM_LINSIM                       _MK_ENUM_CONST(6)
#define MISCREG_HIDREV_0_PRE_SI_PLATFORM_VERIFICATION_SIMULATION                        _MK_ENUM_CONST(7)
#define MISCREG_HIDREV_0_PRE_SI_PLATFORM_VDK                    _MK_ENUM_CONST(8)


// Reserved address 0x8

// Reserved address 0xc

// Register MISCREG_NVDEC1_HS_SECURITY_0
#define MISCREG_NVDEC1_HS_SECURITY_0                    _MK_ADDR_CONST(0xffc)
#define MISCREG_NVDEC1_HS_SECURITY_0_SECURE                     0x0
#define MISCREG_NVDEC1_HS_SECURITY_0_DUAL                       0x0
#define MISCREG_NVDEC1_HS_SECURITY_0_SCR                        SCRNVDEC_0
#define MISCREG_NVDEC1_HS_SECURITY_0_WORD_COUNT                         0x1
#define MISCREG_NVDEC1_HS_SECURITY_0_RESET_VAL                  _MK_MASK_CONST(0xfffff)
#define MISCREG_NVDEC1_HS_SECURITY_0_RESET_MASK                         _MK_MASK_CONST(0xfffff)
#define MISCREG_NVDEC1_HS_SECURITY_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define MISCREG_NVDEC1_HS_SECURITY_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define MISCREG_NVDEC1_HS_SECURITY_0_READ_MASK                  _MK_MASK_CONST(0xfffff)
#define MISCREG_NVDEC1_HS_SECURITY_0_WRITE_MASK                         _MK_MASK_CONST(0xffff)
#define MISCREG_NVDEC1_HS_SECURITY_0_MSTR_ID_SHIFT                      _MK_SHIFT_CONST(16)
#define MISCREG_NVDEC1_HS_SECURITY_0_MSTR_ID_FIELD                      _MK_FIELD_CONST(0xf, MISCREG_NVDEC1_HS_SECURITY_0_MSTR_ID_SHIFT)
#define MISCREG_NVDEC1_HS_SECURITY_0_MSTR_ID_RANGE                      19:16
#define MISCREG_NVDEC1_HS_SECURITY_0_MSTR_ID_WOFFSET                    0x0
#define MISCREG_NVDEC1_HS_SECURITY_0_MSTR_ID_DEFAULT                    _MK_MASK_CONST(0xf)
#define MISCREG_NVDEC1_HS_SECURITY_0_MSTR_ID_DEFAULT_MASK                       _MK_MASK_CONST(0xf)
#define MISCREG_NVDEC1_HS_SECURITY_0_MSTR_ID_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define MISCREG_NVDEC1_HS_SECURITY_0_MSTR_ID_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define MISCREG_NVDEC1_HS_SECURITY_0_MSTR_ID_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define MISCREG_NVDEC1_HS_SECURITY_0_MSTR_ID_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define MISCREG_NVDEC1_HS_SECURITY_0_MSTR_ID_CCPLEX                     _MK_ENUM_CONST(1)
#define MISCREG_NVDEC1_HS_SECURITY_0_MSTR_ID_CCPLEX_DPMU                        _MK_ENUM_CONST(2)
#define MISCREG_NVDEC1_HS_SECURITY_0_MSTR_ID_BPMP                       _MK_ENUM_CONST(3)
#define MISCREG_NVDEC1_HS_SECURITY_0_MSTR_ID_SPE                        _MK_ENUM_CONST(4)
#define MISCREG_NVDEC1_HS_SECURITY_0_MSTR_ID_SCE                        _MK_ENUM_CONST(5)
#define MISCREG_NVDEC1_HS_SECURITY_0_MSTR_ID_DMA_PER                    _MK_ENUM_CONST(6)
#define MISCREG_NVDEC1_HS_SECURITY_0_MSTR_ID_TSECA                      _MK_ENUM_CONST(7)
#define MISCREG_NVDEC1_HS_SECURITY_0_MSTR_ID_TSECB                      _MK_ENUM_CONST(8)
#define MISCREG_NVDEC1_HS_SECURITY_0_MSTR_ID_JTAGM                      _MK_ENUM_CONST(9)
#define MISCREG_NVDEC1_HS_SECURITY_0_MSTR_ID_CSITE                      _MK_ENUM_CONST(10)
#define MISCREG_NVDEC1_HS_SECURITY_0_MSTR_ID_APE                        _MK_ENUM_CONST(11)
#define MISCREG_NVDEC1_HS_SECURITY_0_MSTR_ID_Peatrans                   _MK_ENUM_CONST(12)
#define MISCREG_NVDEC1_HS_SECURITY_0_MSTR_ID_NVDEC                      _MK_ENUM_CONST(13)
#define MISCREG_NVDEC1_HS_SECURITY_0_MSTR_ID_RCE                        _MK_ENUM_CONST(14)
#define MISCREG_NVDEC1_HS_SECURITY_0_MSTR_ID_NVDEC1                     _MK_ENUM_CONST(15)

#define MISCREG_NVDEC1_HS_SECURITY_0_G7W_SHIFT                  _MK_SHIFT_CONST(15)
#define MISCREG_NVDEC1_HS_SECURITY_0_G7W_FIELD                  _MK_FIELD_CONST(0x1, MISCREG_NVDEC1_HS_SECURITY_0_G7W_SHIFT)
#define MISCREG_NVDEC1_HS_SECURITY_0_G7W_RANGE                  15:15
#define MISCREG_NVDEC1_HS_SECURITY_0_G7W_WOFFSET                        0x0
#define MISCREG_NVDEC1_HS_SECURITY_0_G7W_DEFAULT                        _MK_MASK_CONST(0x1)
#define MISCREG_NVDEC1_HS_SECURITY_0_G7W_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define MISCREG_NVDEC1_HS_SECURITY_0_G7W_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define MISCREG_NVDEC1_HS_SECURITY_0_G7W_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define MISCREG_NVDEC1_HS_SECURITY_0_G7W_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define MISCREG_NVDEC1_HS_SECURITY_0_G7W_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)

#define MISCREG_NVDEC1_HS_SECURITY_0_G6W_SHIFT                  _MK_SHIFT_CONST(14)
#define MISCREG_NVDEC1_HS_SECURITY_0_G6W_FIELD                  _MK_FIELD_CONST(0x1, MISCREG_NVDEC1_HS_SECURITY_0_G6W_SHIFT)
#define MISCREG_NVDEC1_HS_SECURITY_0_G6W_RANGE                  14:14
#define MISCREG_NVDEC1_HS_SECURITY_0_G6W_WOFFSET                        0x0
#define MISCREG_NVDEC1_HS_SECURITY_0_G6W_DEFAULT                        _MK_MASK_CONST(0x1)
#define MISCREG_NVDEC1_HS_SECURITY_0_G6W_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define MISCREG_NVDEC1_HS_SECURITY_0_G6W_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define MISCREG_NVDEC1_HS_SECURITY_0_G6W_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define MISCREG_NVDEC1_HS_SECURITY_0_G6W_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define MISCREG_NVDEC1_HS_SECURITY_0_G6W_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)

#define MISCREG_NVDEC1_HS_SECURITY_0_G5W_SHIFT                  _MK_SHIFT_CONST(13)
#define MISCREG_NVDEC1_HS_SECURITY_0_G5W_FIELD                  _MK_FIELD_CONST(0x1, MISCREG_NVDEC1_HS_SECURITY_0_G5W_SHIFT)
#define MISCREG_NVDEC1_HS_SECURITY_0_G5W_RANGE                  13:13
#define MISCREG_NVDEC1_HS_SECURITY_0_G5W_WOFFSET                        0x0
#define MISCREG_NVDEC1_HS_SECURITY_0_G5W_DEFAULT                        _MK_MASK_CONST(0x1)
#define MISCREG_NVDEC1_HS_SECURITY_0_G5W_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define MISCREG_NVDEC1_HS_SECURITY_0_G5W_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define MISCREG_NVDEC1_HS_SECURITY_0_G5W_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define MISCREG_NVDEC1_HS_SECURITY_0_G5W_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define MISCREG_NVDEC1_HS_SECURITY_0_G5W_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)

#define MISCREG_NVDEC1_HS_SECURITY_0_G4W_SHIFT                  _MK_SHIFT_CONST(12)
#define MISCREG_NVDEC1_HS_SECURITY_0_G4W_FIELD                  _MK_FIELD_CONST(0x1, MISCREG_NVDEC1_HS_SECURITY_0_G4W_SHIFT)
#define MISCREG_NVDEC1_HS_SECURITY_0_G4W_RANGE                  12:12
#define MISCREG_NVDEC1_HS_SECURITY_0_G4W_WOFFSET                        0x0
#define MISCREG_NVDEC1_HS_SECURITY_0_G4W_DEFAULT                        _MK_MASK_CONST(0x1)
#define MISCREG_NVDEC1_HS_SECURITY_0_G4W_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define MISCREG_NVDEC1_HS_SECURITY_0_G4W_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define MISCREG_NVDEC1_HS_SECURITY_0_G4W_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define MISCREG_NVDEC1_HS_SECURITY_0_G4W_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define MISCREG_NVDEC1_HS_SECURITY_0_G4W_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)

#define MISCREG_NVDEC1_HS_SECURITY_0_G3W_SHIFT                  _MK_SHIFT_CONST(11)
#define MISCREG_NVDEC1_HS_SECURITY_0_G3W_FIELD                  _MK_FIELD_CONST(0x1, MISCREG_NVDEC1_HS_SECURITY_0_G3W_SHIFT)
#define MISCREG_NVDEC1_HS_SECURITY_0_G3W_RANGE                  11:11
#define MISCREG_NVDEC1_HS_SECURITY_0_G3W_WOFFSET                        0x0
#define MISCREG_NVDEC1_HS_SECURITY_0_G3W_DEFAULT                        _MK_MASK_CONST(0x1)
#define MISCREG_NVDEC1_HS_SECURITY_0_G3W_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define MISCREG_NVDEC1_HS_SECURITY_0_G3W_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define MISCREG_NVDEC1_HS_SECURITY_0_G3W_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define MISCREG_NVDEC1_HS_SECURITY_0_G3W_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define MISCREG_NVDEC1_HS_SECURITY_0_G3W_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)

#define MISCREG_NVDEC1_HS_SECURITY_0_G2W_SHIFT                  _MK_SHIFT_CONST(10)
#define MISCREG_NVDEC1_HS_SECURITY_0_G2W_FIELD                  _MK_FIELD_CONST(0x1, MISCREG_NVDEC1_HS_SECURITY_0_G2W_SHIFT)
#define MISCREG_NVDEC1_HS_SECURITY_0_G2W_RANGE                  10:10
#define MISCREG_NVDEC1_HS_SECURITY_0_G2W_WOFFSET                        0x0
#define MISCREG_NVDEC1_HS_SECURITY_0_G2W_DEFAULT                        _MK_MASK_CONST(0x1)
#define MISCREG_NVDEC1_HS_SECURITY_0_G2W_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define MISCREG_NVDEC1_HS_SECURITY_0_G2W_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define MISCREG_NVDEC1_HS_SECURITY_0_G2W_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define MISCREG_NVDEC1_HS_SECURITY_0_G2W_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define MISCREG_NVDEC1_HS_SECURITY_0_G2W_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)

#define MISCREG_NVDEC1_HS_SECURITY_0_G1W_SHIFT                  _MK_SHIFT_CONST(9)
#define MISCREG_NVDEC1_HS_SECURITY_0_G1W_FIELD                  _MK_FIELD_CONST(0x1, MISCREG_NVDEC1_HS_SECURITY_0_G1W_SHIFT)
#define MISCREG_NVDEC1_HS_SECURITY_0_G1W_RANGE                  9:9
#define MISCREG_NVDEC1_HS_SECURITY_0_G1W_WOFFSET                        0x0
#define MISCREG_NVDEC1_HS_SECURITY_0_G1W_DEFAULT                        _MK_MASK_CONST(0x1)
#define MISCREG_NVDEC1_HS_SECURITY_0_G1W_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define MISCREG_NVDEC1_HS_SECURITY_0_G1W_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define MISCREG_NVDEC1_HS_SECURITY_0_G1W_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define MISCREG_NVDEC1_HS_SECURITY_0_G1W_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define MISCREG_NVDEC1_HS_SECURITY_0_G1W_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)

#define MISCREG_NVDEC1_HS_SECURITY_0_G0W_SHIFT                  _MK_SHIFT_CONST(8)
#define MISCREG_NVDEC1_HS_SECURITY_0_G0W_FIELD                  _MK_FIELD_CONST(0x1, MISCREG_NVDEC1_HS_SECURITY_0_G0W_SHIFT)
#define MISCREG_NVDEC1_HS_SECURITY_0_G0W_RANGE                  8:8
#define MISCREG_NVDEC1_HS_SECURITY_0_G0W_WOFFSET                        0x0
#define MISCREG_NVDEC1_HS_SECURITY_0_G0W_DEFAULT                        _MK_MASK_CONST(0x1)
#define MISCREG_NVDEC1_HS_SECURITY_0_G0W_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define MISCREG_NVDEC1_HS_SECURITY_0_G0W_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define MISCREG_NVDEC1_HS_SECURITY_0_G0W_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define MISCREG_NVDEC1_HS_SECURITY_0_G0W_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define MISCREG_NVDEC1_HS_SECURITY_0_G0W_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)

#define MISCREG_NVDEC1_HS_SECURITY_0_G7R_SHIFT                  _MK_SHIFT_CONST(7)
#define MISCREG_NVDEC1_HS_SECURITY_0_G7R_FIELD                  _MK_FIELD_CONST(0x1, MISCREG_NVDEC1_HS_SECURITY_0_G7R_SHIFT)
#define MISCREG_NVDEC1_HS_SECURITY_0_G7R_RANGE                  7:7
#define MISCREG_NVDEC1_HS_SECURITY_0_G7R_WOFFSET                        0x0
#define MISCREG_NVDEC1_HS_SECURITY_0_G7R_DEFAULT                        _MK_MASK_CONST(0x1)
#define MISCREG_NVDEC1_HS_SECURITY_0_G7R_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define MISCREG_NVDEC1_HS_SECURITY_0_G7R_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define MISCREG_NVDEC1_HS_SECURITY_0_G7R_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define MISCREG_NVDEC1_HS_SECURITY_0_G7R_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define MISCREG_NVDEC1_HS_SECURITY_0_G7R_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)

#define MISCREG_NVDEC1_HS_SECURITY_0_G6R_SHIFT                  _MK_SHIFT_CONST(6)
#define MISCREG_NVDEC1_HS_SECURITY_0_G6R_FIELD                  _MK_FIELD_CONST(0x1, MISCREG_NVDEC1_HS_SECURITY_0_G6R_SHIFT)
#define MISCREG_NVDEC1_HS_SECURITY_0_G6R_RANGE                  6:6
#define MISCREG_NVDEC1_HS_SECURITY_0_G6R_WOFFSET                        0x0
#define MISCREG_NVDEC1_HS_SECURITY_0_G6R_DEFAULT                        _MK_MASK_CONST(0x1)
#define MISCREG_NVDEC1_HS_SECURITY_0_G6R_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define MISCREG_NVDEC1_HS_SECURITY_0_G6R_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define MISCREG_NVDEC1_HS_SECURITY_0_G6R_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define MISCREG_NVDEC1_HS_SECURITY_0_G6R_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define MISCREG_NVDEC1_HS_SECURITY_0_G6R_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)

#define MISCREG_NVDEC1_HS_SECURITY_0_G5R_SHIFT                  _MK_SHIFT_CONST(5)
#define MISCREG_NVDEC1_HS_SECURITY_0_G5R_FIELD                  _MK_FIELD_CONST(0x1, MISCREG_NVDEC1_HS_SECURITY_0_G5R_SHIFT)
#define MISCREG_NVDEC1_HS_SECURITY_0_G5R_RANGE                  5:5
#define MISCREG_NVDEC1_HS_SECURITY_0_G5R_WOFFSET                        0x0
#define MISCREG_NVDEC1_HS_SECURITY_0_G5R_DEFAULT                        _MK_MASK_CONST(0x1)
#define MISCREG_NVDEC1_HS_SECURITY_0_G5R_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define MISCREG_NVDEC1_HS_SECURITY_0_G5R_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define MISCREG_NVDEC1_HS_SECURITY_0_G5R_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define MISCREG_NVDEC1_HS_SECURITY_0_G5R_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define MISCREG_NVDEC1_HS_SECURITY_0_G5R_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)

#define MISCREG_NVDEC1_HS_SECURITY_0_G4R_SHIFT                  _MK_SHIFT_CONST(4)
#define MISCREG_NVDEC1_HS_SECURITY_0_G4R_FIELD                  _MK_FIELD_CONST(0x1, MISCREG_NVDEC1_HS_SECURITY_0_G4R_SHIFT)
#define MISCREG_NVDEC1_HS_SECURITY_0_G4R_RANGE                  4:4
#define MISCREG_NVDEC1_HS_SECURITY_0_G4R_WOFFSET                        0x0
#define MISCREG_NVDEC1_HS_SECURITY_0_G4R_DEFAULT                        _MK_MASK_CONST(0x1)
#define MISCREG_NVDEC1_HS_SECURITY_0_G4R_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define MISCREG_NVDEC1_HS_SECURITY_0_G4R_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define MISCREG_NVDEC1_HS_SECURITY_0_G4R_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define MISCREG_NVDEC1_HS_SECURITY_0_G4R_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define MISCREG_NVDEC1_HS_SECURITY_0_G4R_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)

#define MISCREG_NVDEC1_HS_SECURITY_0_G3R_SHIFT                  _MK_SHIFT_CONST(3)
#define MISCREG_NVDEC1_HS_SECURITY_0_G3R_FIELD                  _MK_FIELD_CONST(0x1, MISCREG_NVDEC1_HS_SECURITY_0_G3R_SHIFT)
#define MISCREG_NVDEC1_HS_SECURITY_0_G3R_RANGE                  3:3
#define MISCREG_NVDEC1_HS_SECURITY_0_G3R_WOFFSET                        0x0
#define MISCREG_NVDEC1_HS_SECURITY_0_G3R_DEFAULT                        _MK_MASK_CONST(0x1)
#define MISCREG_NVDEC1_HS_SECURITY_0_G3R_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define MISCREG_NVDEC1_HS_SECURITY_0_G3R_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define MISCREG_NVDEC1_HS_SECURITY_0_G3R_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define MISCREG_NVDEC1_HS_SECURITY_0_G3R_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define MISCREG_NVDEC1_HS_SECURITY_0_G3R_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)

#define MISCREG_NVDEC1_HS_SECURITY_0_G2R_SHIFT                  _MK_SHIFT_CONST(2)
#define MISCREG_NVDEC1_HS_SECURITY_0_G2R_FIELD                  _MK_FIELD_CONST(0x1, MISCREG_NVDEC1_HS_SECURITY_0_G2R_SHIFT)
#define MISCREG_NVDEC1_HS_SECURITY_0_G2R_RANGE                  2:2
#define MISCREG_NVDEC1_HS_SECURITY_0_G2R_WOFFSET                        0x0
#define MISCREG_NVDEC1_HS_SECURITY_0_G2R_DEFAULT                        _MK_MASK_CONST(0x1)
#define MISCREG_NVDEC1_HS_SECURITY_0_G2R_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define MISCREG_NVDEC1_HS_SECURITY_0_G2R_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define MISCREG_NVDEC1_HS_SECURITY_0_G2R_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define MISCREG_NVDEC1_HS_SECURITY_0_G2R_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define MISCREG_NVDEC1_HS_SECURITY_0_G2R_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)

#define MISCREG_NVDEC1_HS_SECURITY_0_G1R_SHIFT                  _MK_SHIFT_CONST(1)
#define MISCREG_NVDEC1_HS_SECURITY_0_G1R_FIELD                  _MK_FIELD_CONST(0x1, MISCREG_NVDEC1_HS_SECURITY_0_G1R_SHIFT)
#define MISCREG_NVDEC1_HS_SECURITY_0_G1R_RANGE                  1:1
#define MISCREG_NVDEC1_HS_SECURITY_0_G1R_WOFFSET                        0x0
#define MISCREG_NVDEC1_HS_SECURITY_0_G1R_DEFAULT                        _MK_MASK_CONST(0x1)
#define MISCREG_NVDEC1_HS_SECURITY_0_G1R_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define MISCREG_NVDEC1_HS_SECURITY_0_G1R_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define MISCREG_NVDEC1_HS_SECURITY_0_G1R_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define MISCREG_NVDEC1_HS_SECURITY_0_G1R_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define MISCREG_NVDEC1_HS_SECURITY_0_G1R_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)

#define MISCREG_NVDEC1_HS_SECURITY_0_G0R_SHIFT                  _MK_SHIFT_CONST(0)
#define MISCREG_NVDEC1_HS_SECURITY_0_G0R_FIELD                  _MK_FIELD_CONST(0x1, MISCREG_NVDEC1_HS_SECURITY_0_G0R_SHIFT)
#define MISCREG_NVDEC1_HS_SECURITY_0_G0R_RANGE                  0:0
#define MISCREG_NVDEC1_HS_SECURITY_0_G0R_WOFFSET                        0x0
#define MISCREG_NVDEC1_HS_SECURITY_0_G0R_DEFAULT                        _MK_MASK_CONST(0x1)
#define MISCREG_NVDEC1_HS_SECURITY_0_G0R_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define MISCREG_NVDEC1_HS_SECURITY_0_G0R_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define MISCREG_NVDEC1_HS_SECURITY_0_G0R_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define MISCREG_NVDEC1_HS_SECURITY_0_G0R_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define MISCREG_NVDEC1_HS_SECURITY_0_G0R_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)


// Register MISCREG_NVDEC1_LS_SECURITY_0
#define MISCREG_NVDEC1_LS_SECURITY_0                    _MK_ADDR_CONST(0x1000)
#define MISCREG_NVDEC1_LS_SECURITY_0_SECURE                     0x0
#define MISCREG_NVDEC1_LS_SECURITY_0_DUAL                       0x0
#define MISCREG_NVDEC1_LS_SECURITY_0_SCR                        SCRNVDEC_0
#define MISCREG_NVDEC1_LS_SECURITY_0_WORD_COUNT                         0x1
#define MISCREG_NVDEC1_LS_SECURITY_0_RESET_VAL                  _MK_MASK_CONST(0xfffff)
#define MISCREG_NVDEC1_LS_SECURITY_0_RESET_MASK                         _MK_MASK_CONST(0xfffff)
#define MISCREG_NVDEC1_LS_SECURITY_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define MISCREG_NVDEC1_LS_SECURITY_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define MISCREG_NVDEC1_LS_SECURITY_0_READ_MASK                  _MK_MASK_CONST(0xfffff)
#define MISCREG_NVDEC1_LS_SECURITY_0_WRITE_MASK                         _MK_MASK_CONST(0xffff)
#define MISCREG_NVDEC1_LS_SECURITY_0_MSTR_ID_SHIFT                      _MK_SHIFT_CONST(16)
#define MISCREG_NVDEC1_LS_SECURITY_0_MSTR_ID_FIELD                      _MK_FIELD_CONST(0xf, MISCREG_NVDEC1_LS_SECURITY_0_MSTR_ID_SHIFT)
#define MISCREG_NVDEC1_LS_SECURITY_0_MSTR_ID_RANGE                      19:16
#define MISCREG_NVDEC1_LS_SECURITY_0_MSTR_ID_WOFFSET                    0x0
#define MISCREG_NVDEC1_LS_SECURITY_0_MSTR_ID_DEFAULT                    _MK_MASK_CONST(0xf)
#define MISCREG_NVDEC1_LS_SECURITY_0_MSTR_ID_DEFAULT_MASK                       _MK_MASK_CONST(0xf)
#define MISCREG_NVDEC1_LS_SECURITY_0_MSTR_ID_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define MISCREG_NVDEC1_LS_SECURITY_0_MSTR_ID_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define MISCREG_NVDEC1_LS_SECURITY_0_MSTR_ID_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define MISCREG_NVDEC1_LS_SECURITY_0_MSTR_ID_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define MISCREG_NVDEC1_LS_SECURITY_0_MSTR_ID_CCPLEX                     _MK_ENUM_CONST(1)
#define MISCREG_NVDEC1_LS_SECURITY_0_MSTR_ID_CCPLEX_DPMU                        _MK_ENUM_CONST(2)
#define MISCREG_NVDEC1_LS_SECURITY_0_MSTR_ID_BPMP                       _MK_ENUM_CONST(3)
#define MISCREG_NVDEC1_LS_SECURITY_0_MSTR_ID_SPE                        _MK_ENUM_CONST(4)
#define MISCREG_NVDEC1_LS_SECURITY_0_MSTR_ID_SCE                        _MK_ENUM_CONST(5)
#define MISCREG_NVDEC1_LS_SECURITY_0_MSTR_ID_DMA_PER                    _MK_ENUM_CONST(6)
#define MISCREG_NVDEC1_LS_SECURITY_0_MSTR_ID_TSECA                      _MK_ENUM_CONST(7)
#define MISCREG_NVDEC1_LS_SECURITY_0_MSTR_ID_TSECB                      _MK_ENUM_CONST(8)
#define MISCREG_NVDEC1_LS_SECURITY_0_MSTR_ID_JTAGM                      _MK_ENUM_CONST(9)
#define MISCREG_NVDEC1_LS_SECURITY_0_MSTR_ID_CSITE                      _MK_ENUM_CONST(10)
#define MISCREG_NVDEC1_LS_SECURITY_0_MSTR_ID_APE                        _MK_ENUM_CONST(11)
#define MISCREG_NVDEC1_LS_SECURITY_0_MSTR_ID_Peatrans                   _MK_ENUM_CONST(12)
#define MISCREG_NVDEC1_LS_SECURITY_0_MSTR_ID_NVDEC                      _MK_ENUM_CONST(13)
#define MISCREG_NVDEC1_LS_SECURITY_0_MSTR_ID_RCE                        _MK_ENUM_CONST(14)
#define MISCREG_NVDEC1_LS_SECURITY_0_MSTR_ID_NVDEC1                     _MK_ENUM_CONST(15)

#define MISCREG_NVDEC1_LS_SECURITY_0_G7W_SHIFT                  _MK_SHIFT_CONST(15)
#define MISCREG_NVDEC1_LS_SECURITY_0_G7W_FIELD                  _MK_FIELD_CONST(0x1, MISCREG_NVDEC1_LS_SECURITY_0_G7W_SHIFT)
#define MISCREG_NVDEC1_LS_SECURITY_0_G7W_RANGE                  15:15
#define MISCREG_NVDEC1_LS_SECURITY_0_G7W_WOFFSET                        0x0
#define MISCREG_NVDEC1_LS_SECURITY_0_G7W_DEFAULT                        _MK_MASK_CONST(0x1)
#define MISCREG_NVDEC1_LS_SECURITY_0_G7W_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define MISCREG_NVDEC1_LS_SECURITY_0_G7W_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define MISCREG_NVDEC1_LS_SECURITY_0_G7W_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define MISCREG_NVDEC1_LS_SECURITY_0_G7W_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define MISCREG_NVDEC1_LS_SECURITY_0_G7W_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)

#define MISCREG_NVDEC1_LS_SECURITY_0_G6W_SHIFT                  _MK_SHIFT_CONST(14)
#define MISCREG_NVDEC1_LS_SECURITY_0_G6W_FIELD                  _MK_FIELD_CONST(0x1, MISCREG_NVDEC1_LS_SECURITY_0_G6W_SHIFT)
#define MISCREG_NVDEC1_LS_SECURITY_0_G6W_RANGE                  14:14
#define MISCREG_NVDEC1_LS_SECURITY_0_G6W_WOFFSET                        0x0
#define MISCREG_NVDEC1_LS_SECURITY_0_G6W_DEFAULT                        _MK_MASK_CONST(0x1)
#define MISCREG_NVDEC1_LS_SECURITY_0_G6W_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define MISCREG_NVDEC1_LS_SECURITY_0_G6W_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define MISCREG_NVDEC1_LS_SECURITY_0_G6W_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define MISCREG_NVDEC1_LS_SECURITY_0_G6W_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define MISCREG_NVDEC1_LS_SECURITY_0_G6W_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)

#define MISCREG_NVDEC1_LS_SECURITY_0_G5W_SHIFT                  _MK_SHIFT_CONST(13)
#define MISCREG_NVDEC1_LS_SECURITY_0_G5W_FIELD                  _MK_FIELD_CONST(0x1, MISCREG_NVDEC1_LS_SECURITY_0_G5W_SHIFT)
#define MISCREG_NVDEC1_LS_SECURITY_0_G5W_RANGE                  13:13
#define MISCREG_NVDEC1_LS_SECURITY_0_G5W_WOFFSET                        0x0
#define MISCREG_NVDEC1_LS_SECURITY_0_G5W_DEFAULT                        _MK_MASK_CONST(0x1)
#define MISCREG_NVDEC1_LS_SECURITY_0_G5W_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define MISCREG_NVDEC1_LS_SECURITY_0_G5W_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define MISCREG_NVDEC1_LS_SECURITY_0_G5W_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define MISCREG_NVDEC1_LS_SECURITY_0_G5W_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define MISCREG_NVDEC1_LS_SECURITY_0_G5W_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)

#define MISCREG_NVDEC1_LS_SECURITY_0_G4W_SHIFT                  _MK_SHIFT_CONST(12)
#define MISCREG_NVDEC1_LS_SECURITY_0_G4W_FIELD                  _MK_FIELD_CONST(0x1, MISCREG_NVDEC1_LS_SECURITY_0_G4W_SHIFT)
#define MISCREG_NVDEC1_LS_SECURITY_0_G4W_RANGE                  12:12
#define MISCREG_NVDEC1_LS_SECURITY_0_G4W_WOFFSET                        0x0
#define MISCREG_NVDEC1_LS_SECURITY_0_G4W_DEFAULT                        _MK_MASK_CONST(0x1)
#define MISCREG_NVDEC1_LS_SECURITY_0_G4W_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define MISCREG_NVDEC1_LS_SECURITY_0_G4W_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define MISCREG_NVDEC1_LS_SECURITY_0_G4W_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define MISCREG_NVDEC1_LS_SECURITY_0_G4W_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define MISCREG_NVDEC1_LS_SECURITY_0_G4W_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)

#define MISCREG_NVDEC1_LS_SECURITY_0_G3W_SHIFT                  _MK_SHIFT_CONST(11)
#define MISCREG_NVDEC1_LS_SECURITY_0_G3W_FIELD                  _MK_FIELD_CONST(0x1, MISCREG_NVDEC1_LS_SECURITY_0_G3W_SHIFT)
#define MISCREG_NVDEC1_LS_SECURITY_0_G3W_RANGE                  11:11
#define MISCREG_NVDEC1_LS_SECURITY_0_G3W_WOFFSET                        0x0
#define MISCREG_NVDEC1_LS_SECURITY_0_G3W_DEFAULT                        _MK_MASK_CONST(0x1)
#define MISCREG_NVDEC1_LS_SECURITY_0_G3W_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define MISCREG_NVDEC1_LS_SECURITY_0_G3W_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define MISCREG_NVDEC1_LS_SECURITY_0_G3W_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define MISCREG_NVDEC1_LS_SECURITY_0_G3W_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define MISCREG_NVDEC1_LS_SECURITY_0_G3W_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)

#define MISCREG_NVDEC1_LS_SECURITY_0_G2W_SHIFT                  _MK_SHIFT_CONST(10)
#define MISCREG_NVDEC1_LS_SECURITY_0_G2W_FIELD                  _MK_FIELD_CONST(0x1, MISCREG_NVDEC1_LS_SECURITY_0_G2W_SHIFT)
#define MISCREG_NVDEC1_LS_SECURITY_0_G2W_RANGE                  10:10
#define MISCREG_NVDEC1_LS_SECURITY_0_G2W_WOFFSET                        0x0
#define MISCREG_NVDEC1_LS_SECURITY_0_G2W_DEFAULT                        _MK_MASK_CONST(0x1)
#define MISCREG_NVDEC1_LS_SECURITY_0_G2W_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define MISCREG_NVDEC1_LS_SECURITY_0_G2W_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define MISCREG_NVDEC1_LS_SECURITY_0_G2W_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define MISCREG_NVDEC1_LS_SECURITY_0_G2W_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define MISCREG_NVDEC1_LS_SECURITY_0_G2W_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)

#define MISCREG_NVDEC1_LS_SECURITY_0_G1W_SHIFT                  _MK_SHIFT_CONST(9)
#define MISCREG_NVDEC1_LS_SECURITY_0_G1W_FIELD                  _MK_FIELD_CONST(0x1, MISCREG_NVDEC1_LS_SECURITY_0_G1W_SHIFT)
#define MISCREG_NVDEC1_LS_SECURITY_0_G1W_RANGE                  9:9
#define MISCREG_NVDEC1_LS_SECURITY_0_G1W_WOFFSET                        0x0
#define MISCREG_NVDEC1_LS_SECURITY_0_G1W_DEFAULT                        _MK_MASK_CONST(0x1)
#define MISCREG_NVDEC1_LS_SECURITY_0_G1W_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define MISCREG_NVDEC1_LS_SECURITY_0_G1W_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define MISCREG_NVDEC1_LS_SECURITY_0_G1W_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define MISCREG_NVDEC1_LS_SECURITY_0_G1W_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define MISCREG_NVDEC1_LS_SECURITY_0_G1W_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)

#define MISCREG_NVDEC1_LS_SECURITY_0_G0W_SHIFT                  _MK_SHIFT_CONST(8)
#define MISCREG_NVDEC1_LS_SECURITY_0_G0W_FIELD                  _MK_FIELD_CONST(0x1, MISCREG_NVDEC1_LS_SECURITY_0_G0W_SHIFT)
#define MISCREG_NVDEC1_LS_SECURITY_0_G0W_RANGE                  8:8
#define MISCREG_NVDEC1_LS_SECURITY_0_G0W_WOFFSET                        0x0
#define MISCREG_NVDEC1_LS_SECURITY_0_G0W_DEFAULT                        _MK_MASK_CONST(0x1)
#define MISCREG_NVDEC1_LS_SECURITY_0_G0W_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define MISCREG_NVDEC1_LS_SECURITY_0_G0W_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define MISCREG_NVDEC1_LS_SECURITY_0_G0W_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define MISCREG_NVDEC1_LS_SECURITY_0_G0W_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define MISCREG_NVDEC1_LS_SECURITY_0_G0W_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)

#define MISCREG_NVDEC1_LS_SECURITY_0_G7R_SHIFT                  _MK_SHIFT_CONST(7)
#define MISCREG_NVDEC1_LS_SECURITY_0_G7R_FIELD                  _MK_FIELD_CONST(0x1, MISCREG_NVDEC1_LS_SECURITY_0_G7R_SHIFT)
#define MISCREG_NVDEC1_LS_SECURITY_0_G7R_RANGE                  7:7
#define MISCREG_NVDEC1_LS_SECURITY_0_G7R_WOFFSET                        0x0
#define MISCREG_NVDEC1_LS_SECURITY_0_G7R_DEFAULT                        _MK_MASK_CONST(0x1)
#define MISCREG_NVDEC1_LS_SECURITY_0_G7R_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define MISCREG_NVDEC1_LS_SECURITY_0_G7R_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define MISCREG_NVDEC1_LS_SECURITY_0_G7R_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define MISCREG_NVDEC1_LS_SECURITY_0_G7R_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define MISCREG_NVDEC1_LS_SECURITY_0_G7R_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)

#define MISCREG_NVDEC1_LS_SECURITY_0_G6R_SHIFT                  _MK_SHIFT_CONST(6)
#define MISCREG_NVDEC1_LS_SECURITY_0_G6R_FIELD                  _MK_FIELD_CONST(0x1, MISCREG_NVDEC1_LS_SECURITY_0_G6R_SHIFT)
#define MISCREG_NVDEC1_LS_SECURITY_0_G6R_RANGE                  6:6
#define MISCREG_NVDEC1_LS_SECURITY_0_G6R_WOFFSET                        0x0
#define MISCREG_NVDEC1_LS_SECURITY_0_G6R_DEFAULT                        _MK_MASK_CONST(0x1)
#define MISCREG_NVDEC1_LS_SECURITY_0_G6R_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define MISCREG_NVDEC1_LS_SECURITY_0_G6R_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define MISCREG_NVDEC1_LS_SECURITY_0_G6R_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define MISCREG_NVDEC1_LS_SECURITY_0_G6R_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define MISCREG_NVDEC1_LS_SECURITY_0_G6R_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)

#define MISCREG_NVDEC1_LS_SECURITY_0_G5R_SHIFT                  _MK_SHIFT_CONST(5)
#define MISCREG_NVDEC1_LS_SECURITY_0_G5R_FIELD                  _MK_FIELD_CONST(0x1, MISCREG_NVDEC1_LS_SECURITY_0_G5R_SHIFT)
#define MISCREG_NVDEC1_LS_SECURITY_0_G5R_RANGE                  5:5
#define MISCREG_NVDEC1_LS_SECURITY_0_G5R_WOFFSET                        0x0
#define MISCREG_NVDEC1_LS_SECURITY_0_G5R_DEFAULT                        _MK_MASK_CONST(0x1)
#define MISCREG_NVDEC1_LS_SECURITY_0_G5R_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define MISCREG_NVDEC1_LS_SECURITY_0_G5R_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define MISCREG_NVDEC1_LS_SECURITY_0_G5R_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define MISCREG_NVDEC1_LS_SECURITY_0_G5R_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define MISCREG_NVDEC1_LS_SECURITY_0_G5R_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)

#define MISCREG_NVDEC1_LS_SECURITY_0_G4R_SHIFT                  _MK_SHIFT_CONST(4)
#define MISCREG_NVDEC1_LS_SECURITY_0_G4R_FIELD                  _MK_FIELD_CONST(0x1, MISCREG_NVDEC1_LS_SECURITY_0_G4R_SHIFT)
#define MISCREG_NVDEC1_LS_SECURITY_0_G4R_RANGE                  4:4
#define MISCREG_NVDEC1_LS_SECURITY_0_G4R_WOFFSET                        0x0
#define MISCREG_NVDEC1_LS_SECURITY_0_G4R_DEFAULT                        _MK_MASK_CONST(0x1)
#define MISCREG_NVDEC1_LS_SECURITY_0_G4R_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define MISCREG_NVDEC1_LS_SECURITY_0_G4R_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define MISCREG_NVDEC1_LS_SECURITY_0_G4R_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define MISCREG_NVDEC1_LS_SECURITY_0_G4R_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define MISCREG_NVDEC1_LS_SECURITY_0_G4R_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)

#define MISCREG_NVDEC1_LS_SECURITY_0_G3R_SHIFT                  _MK_SHIFT_CONST(3)
#define MISCREG_NVDEC1_LS_SECURITY_0_G3R_FIELD                  _MK_FIELD_CONST(0x1, MISCREG_NVDEC1_LS_SECURITY_0_G3R_SHIFT)
#define MISCREG_NVDEC1_LS_SECURITY_0_G3R_RANGE                  3:3
#define MISCREG_NVDEC1_LS_SECURITY_0_G3R_WOFFSET                        0x0
#define MISCREG_NVDEC1_LS_SECURITY_0_G3R_DEFAULT                        _MK_MASK_CONST(0x1)
#define MISCREG_NVDEC1_LS_SECURITY_0_G3R_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define MISCREG_NVDEC1_LS_SECURITY_0_G3R_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define MISCREG_NVDEC1_LS_SECURITY_0_G3R_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define MISCREG_NVDEC1_LS_SECURITY_0_G3R_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define MISCREG_NVDEC1_LS_SECURITY_0_G3R_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)

#define MISCREG_NVDEC1_LS_SECURITY_0_G2R_SHIFT                  _MK_SHIFT_CONST(2)
#define MISCREG_NVDEC1_LS_SECURITY_0_G2R_FIELD                  _MK_FIELD_CONST(0x1, MISCREG_NVDEC1_LS_SECURITY_0_G2R_SHIFT)
#define MISCREG_NVDEC1_LS_SECURITY_0_G2R_RANGE                  2:2
#define MISCREG_NVDEC1_LS_SECURITY_0_G2R_WOFFSET                        0x0
#define MISCREG_NVDEC1_LS_SECURITY_0_G2R_DEFAULT                        _MK_MASK_CONST(0x1)
#define MISCREG_NVDEC1_LS_SECURITY_0_G2R_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define MISCREG_NVDEC1_LS_SECURITY_0_G2R_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define MISCREG_NVDEC1_LS_SECURITY_0_G2R_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define MISCREG_NVDEC1_LS_SECURITY_0_G2R_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define MISCREG_NVDEC1_LS_SECURITY_0_G2R_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)

#define MISCREG_NVDEC1_LS_SECURITY_0_G1R_SHIFT                  _MK_SHIFT_CONST(1)
#define MISCREG_NVDEC1_LS_SECURITY_0_G1R_FIELD                  _MK_FIELD_CONST(0x1, MISCREG_NVDEC1_LS_SECURITY_0_G1R_SHIFT)
#define MISCREG_NVDEC1_LS_SECURITY_0_G1R_RANGE                  1:1
#define MISCREG_NVDEC1_LS_SECURITY_0_G1R_WOFFSET                        0x0
#define MISCREG_NVDEC1_LS_SECURITY_0_G1R_DEFAULT                        _MK_MASK_CONST(0x1)
#define MISCREG_NVDEC1_LS_SECURITY_0_G1R_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define MISCREG_NVDEC1_LS_SECURITY_0_G1R_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define MISCREG_NVDEC1_LS_SECURITY_0_G1R_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define MISCREG_NVDEC1_LS_SECURITY_0_G1R_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define MISCREG_NVDEC1_LS_SECURITY_0_G1R_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)

#define MISCREG_NVDEC1_LS_SECURITY_0_G0R_SHIFT                  _MK_SHIFT_CONST(0)
#define MISCREG_NVDEC1_LS_SECURITY_0_G0R_FIELD                  _MK_FIELD_CONST(0x1, MISCREG_NVDEC1_LS_SECURITY_0_G0R_SHIFT)
#define MISCREG_NVDEC1_LS_SECURITY_0_G0R_RANGE                  0:0
#define MISCREG_NVDEC1_LS_SECURITY_0_G0R_WOFFSET                        0x0
#define MISCREG_NVDEC1_LS_SECURITY_0_G0R_DEFAULT                        _MK_MASK_CONST(0x1)
#define MISCREG_NVDEC1_LS_SECURITY_0_G0R_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define MISCREG_NVDEC1_LS_SECURITY_0_G0R_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define MISCREG_NVDEC1_LS_SECURITY_0_G0R_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define MISCREG_NVDEC1_LS_SECURITY_0_G0R_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define MISCREG_NVDEC1_LS_SECURITY_0_G0R_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)


// Register MISCREG_BPMP_SECURITY_0
#define MISCREG_BPMP_SECURITY_0                 _MK_ADDR_CONST(0x1004)
#define MISCREG_BPMP_SECURITY_0_SECURE                  0x0
#define MISCREG_BPMP_SECURITY_0_DUAL                    0x0
#define MISCREG_BPMP_SECURITY_0_SCR                     SCRBPMP_0
#define MISCREG_BPMP_SECURITY_0_WORD_COUNT                      0x1
#define MISCREG_BPMP_SECURITY_0_RESET_VAL                       _MK_MASK_CONST(0x30000)
#define MISCREG_BPMP_SECURITY_0_RESET_MASK                      _MK_MASK_CONST(0xfffff)
#define MISCREG_BPMP_SECURITY_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define MISCREG_BPMP_SECURITY_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define MISCREG_BPMP_SECURITY_0_READ_MASK                       _MK_MASK_CONST(0xfffff)
#define MISCREG_BPMP_SECURITY_0_WRITE_MASK                      _MK_MASK_CONST(0xffff)
#define MISCREG_BPMP_SECURITY_0_MSTR_ID_SHIFT                   _MK_SHIFT_CONST(16)
#define MISCREG_BPMP_SECURITY_0_MSTR_ID_FIELD                   _MK_FIELD_CONST(0xf, MISCREG_BPMP_SECURITY_0_MSTR_ID_SHIFT)
#define MISCREG_BPMP_SECURITY_0_MSTR_ID_RANGE                   19:16
#define MISCREG_BPMP_SECURITY_0_MSTR_ID_WOFFSET                 0x0
#define MISCREG_BPMP_SECURITY_0_MSTR_ID_DEFAULT                 _MK_MASK_CONST(0x3)
#define MISCREG_BPMP_SECURITY_0_MSTR_ID_DEFAULT_MASK                    _MK_MASK_CONST(0xf)
#define MISCREG_BPMP_SECURITY_0_MSTR_ID_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define MISCREG_BPMP_SECURITY_0_MSTR_ID_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define MISCREG_BPMP_SECURITY_0_MSTR_ID_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define MISCREG_BPMP_SECURITY_0_MSTR_ID_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define MISCREG_BPMP_SECURITY_0_MSTR_ID_CCPLEX                  _MK_ENUM_CONST(1)
#define MISCREG_BPMP_SECURITY_0_MSTR_ID_CCPLEX_DPMU                     _MK_ENUM_CONST(2)
#define MISCREG_BPMP_SECURITY_0_MSTR_ID_BPMP                    _MK_ENUM_CONST(3)
#define MISCREG_BPMP_SECURITY_0_MSTR_ID_SPE                     _MK_ENUM_CONST(4)
#define MISCREG_BPMP_SECURITY_0_MSTR_ID_SCE                     _MK_ENUM_CONST(5)
#define MISCREG_BPMP_SECURITY_0_MSTR_ID_DMA_PER                 _MK_ENUM_CONST(6)
#define MISCREG_BPMP_SECURITY_0_MSTR_ID_TSECA                   _MK_ENUM_CONST(7)
#define MISCREG_BPMP_SECURITY_0_MSTR_ID_TSECB                   _MK_ENUM_CONST(8)
#define MISCREG_BPMP_SECURITY_0_MSTR_ID_JTAGM                   _MK_ENUM_CONST(9)
#define MISCREG_BPMP_SECURITY_0_MSTR_ID_CSITE                   _MK_ENUM_CONST(10)
#define MISCREG_BPMP_SECURITY_0_MSTR_ID_APE                     _MK_ENUM_CONST(11)
#define MISCREG_BPMP_SECURITY_0_MSTR_ID_Peatrans                        _MK_ENUM_CONST(12)
#define MISCREG_BPMP_SECURITY_0_MSTR_ID_NVDEC                   _MK_ENUM_CONST(13)
#define MISCREG_BPMP_SECURITY_0_MSTR_ID_RCE                     _MK_ENUM_CONST(14)
#define MISCREG_BPMP_SECURITY_0_MSTR_ID_NVDEC1                  _MK_ENUM_CONST(15)

#define MISCREG_BPMP_SECURITY_0_G7W_SHIFT                       _MK_SHIFT_CONST(15)
#define MISCREG_BPMP_SECURITY_0_G7W_FIELD                       _MK_FIELD_CONST(0x1, MISCREG_BPMP_SECURITY_0_G7W_SHIFT)
#define MISCREG_BPMP_SECURITY_0_G7W_RANGE                       15:15
#define MISCREG_BPMP_SECURITY_0_G7W_WOFFSET                     0x0
#define MISCREG_BPMP_SECURITY_0_G7W_DEFAULT                     _MK_MASK_CONST(0x0)
#define MISCREG_BPMP_SECURITY_0_G7W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define MISCREG_BPMP_SECURITY_0_G7W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define MISCREG_BPMP_SECURITY_0_G7W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define MISCREG_BPMP_SECURITY_0_G7W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define MISCREG_BPMP_SECURITY_0_G7W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define MISCREG_BPMP_SECURITY_0_G6W_SHIFT                       _MK_SHIFT_CONST(14)
#define MISCREG_BPMP_SECURITY_0_G6W_FIELD                       _MK_FIELD_CONST(0x1, MISCREG_BPMP_SECURITY_0_G6W_SHIFT)
#define MISCREG_BPMP_SECURITY_0_G6W_RANGE                       14:14
#define MISCREG_BPMP_SECURITY_0_G6W_WOFFSET                     0x0
#define MISCREG_BPMP_SECURITY_0_G6W_DEFAULT                     _MK_MASK_CONST(0x0)
#define MISCREG_BPMP_SECURITY_0_G6W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define MISCREG_BPMP_SECURITY_0_G6W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define MISCREG_BPMP_SECURITY_0_G6W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define MISCREG_BPMP_SECURITY_0_G6W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define MISCREG_BPMP_SECURITY_0_G6W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define MISCREG_BPMP_SECURITY_0_G5W_SHIFT                       _MK_SHIFT_CONST(13)
#define MISCREG_BPMP_SECURITY_0_G5W_FIELD                       _MK_FIELD_CONST(0x1, MISCREG_BPMP_SECURITY_0_G5W_SHIFT)
#define MISCREG_BPMP_SECURITY_0_G5W_RANGE                       13:13
#define MISCREG_BPMP_SECURITY_0_G5W_WOFFSET                     0x0
#define MISCREG_BPMP_SECURITY_0_G5W_DEFAULT                     _MK_MASK_CONST(0x0)
#define MISCREG_BPMP_SECURITY_0_G5W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define MISCREG_BPMP_SECURITY_0_G5W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define MISCREG_BPMP_SECURITY_0_G5W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define MISCREG_BPMP_SECURITY_0_G5W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define MISCREG_BPMP_SECURITY_0_G5W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define MISCREG_BPMP_SECURITY_0_G4W_SHIFT                       _MK_SHIFT_CONST(12)
#define MISCREG_BPMP_SECURITY_0_G4W_FIELD                       _MK_FIELD_CONST(0x1, MISCREG_BPMP_SECURITY_0_G4W_SHIFT)
#define MISCREG_BPMP_SECURITY_0_G4W_RANGE                       12:12
#define MISCREG_BPMP_SECURITY_0_G4W_WOFFSET                     0x0
#define MISCREG_BPMP_SECURITY_0_G4W_DEFAULT                     _MK_MASK_CONST(0x0)
#define MISCREG_BPMP_SECURITY_0_G4W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define MISCREG_BPMP_SECURITY_0_G4W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define MISCREG_BPMP_SECURITY_0_G4W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define MISCREG_BPMP_SECURITY_0_G4W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define MISCREG_BPMP_SECURITY_0_G4W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define MISCREG_BPMP_SECURITY_0_G3W_SHIFT                       _MK_SHIFT_CONST(11)
#define MISCREG_BPMP_SECURITY_0_G3W_FIELD                       _MK_FIELD_CONST(0x1, MISCREG_BPMP_SECURITY_0_G3W_SHIFT)
#define MISCREG_BPMP_SECURITY_0_G3W_RANGE                       11:11
#define MISCREG_BPMP_SECURITY_0_G3W_WOFFSET                     0x0
#define MISCREG_BPMP_SECURITY_0_G3W_DEFAULT                     _MK_MASK_CONST(0x0)
#define MISCREG_BPMP_SECURITY_0_G3W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define MISCREG_BPMP_SECURITY_0_G3W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define MISCREG_BPMP_SECURITY_0_G3W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define MISCREG_BPMP_SECURITY_0_G3W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define MISCREG_BPMP_SECURITY_0_G3W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define MISCREG_BPMP_SECURITY_0_G2W_SHIFT                       _MK_SHIFT_CONST(10)
#define MISCREG_BPMP_SECURITY_0_G2W_FIELD                       _MK_FIELD_CONST(0x1, MISCREG_BPMP_SECURITY_0_G2W_SHIFT)
#define MISCREG_BPMP_SECURITY_0_G2W_RANGE                       10:10
#define MISCREG_BPMP_SECURITY_0_G2W_WOFFSET                     0x0
#define MISCREG_BPMP_SECURITY_0_G2W_DEFAULT                     _MK_MASK_CONST(0x0)
#define MISCREG_BPMP_SECURITY_0_G2W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define MISCREG_BPMP_SECURITY_0_G2W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define MISCREG_BPMP_SECURITY_0_G2W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define MISCREG_BPMP_SECURITY_0_G2W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define MISCREG_BPMP_SECURITY_0_G2W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define MISCREG_BPMP_SECURITY_0_G1W_SHIFT                       _MK_SHIFT_CONST(9)
#define MISCREG_BPMP_SECURITY_0_G1W_FIELD                       _MK_FIELD_CONST(0x1, MISCREG_BPMP_SECURITY_0_G1W_SHIFT)
#define MISCREG_BPMP_SECURITY_0_G1W_RANGE                       9:9
#define MISCREG_BPMP_SECURITY_0_G1W_WOFFSET                     0x0
#define MISCREG_BPMP_SECURITY_0_G1W_DEFAULT                     _MK_MASK_CONST(0x0)
#define MISCREG_BPMP_SECURITY_0_G1W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define MISCREG_BPMP_SECURITY_0_G1W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define MISCREG_BPMP_SECURITY_0_G1W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define MISCREG_BPMP_SECURITY_0_G1W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define MISCREG_BPMP_SECURITY_0_G1W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define MISCREG_BPMP_SECURITY_0_G0W_SHIFT                       _MK_SHIFT_CONST(8)
#define MISCREG_BPMP_SECURITY_0_G0W_FIELD                       _MK_FIELD_CONST(0x1, MISCREG_BPMP_SECURITY_0_G0W_SHIFT)
#define MISCREG_BPMP_SECURITY_0_G0W_RANGE                       8:8
#define MISCREG_BPMP_SECURITY_0_G0W_WOFFSET                     0x0
#define MISCREG_BPMP_SECURITY_0_G0W_DEFAULT                     _MK_MASK_CONST(0x0)
#define MISCREG_BPMP_SECURITY_0_G0W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define MISCREG_BPMP_SECURITY_0_G0W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define MISCREG_BPMP_SECURITY_0_G0W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define MISCREG_BPMP_SECURITY_0_G0W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define MISCREG_BPMP_SECURITY_0_G0W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define MISCREG_BPMP_SECURITY_0_G7R_SHIFT                       _MK_SHIFT_CONST(7)
#define MISCREG_BPMP_SECURITY_0_G7R_FIELD                       _MK_FIELD_CONST(0x1, MISCREG_BPMP_SECURITY_0_G7R_SHIFT)
#define MISCREG_BPMP_SECURITY_0_G7R_RANGE                       7:7
#define MISCREG_BPMP_SECURITY_0_G7R_WOFFSET                     0x0
#define MISCREG_BPMP_SECURITY_0_G7R_DEFAULT                     _MK_MASK_CONST(0x0)
#define MISCREG_BPMP_SECURITY_0_G7R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define MISCREG_BPMP_SECURITY_0_G7R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define MISCREG_BPMP_SECURITY_0_G7R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define MISCREG_BPMP_SECURITY_0_G7R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define MISCREG_BPMP_SECURITY_0_G7R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define MISCREG_BPMP_SECURITY_0_G6R_SHIFT                       _MK_SHIFT_CONST(6)
#define MISCREG_BPMP_SECURITY_0_G6R_FIELD                       _MK_FIELD_CONST(0x1, MISCREG_BPMP_SECURITY_0_G6R_SHIFT)
#define MISCREG_BPMP_SECURITY_0_G6R_RANGE                       6:6
#define MISCREG_BPMP_SECURITY_0_G6R_WOFFSET                     0x0
#define MISCREG_BPMP_SECURITY_0_G6R_DEFAULT                     _MK_MASK_CONST(0x0)
#define MISCREG_BPMP_SECURITY_0_G6R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define MISCREG_BPMP_SECURITY_0_G6R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define MISCREG_BPMP_SECURITY_0_G6R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define MISCREG_BPMP_SECURITY_0_G6R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define MISCREG_BPMP_SECURITY_0_G6R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define MISCREG_BPMP_SECURITY_0_G5R_SHIFT                       _MK_SHIFT_CONST(5)
#define MISCREG_BPMP_SECURITY_0_G5R_FIELD                       _MK_FIELD_CONST(0x1, MISCREG_BPMP_SECURITY_0_G5R_SHIFT)
#define MISCREG_BPMP_SECURITY_0_G5R_RANGE                       5:5
#define MISCREG_BPMP_SECURITY_0_G5R_WOFFSET                     0x0
#define MISCREG_BPMP_SECURITY_0_G5R_DEFAULT                     _MK_MASK_CONST(0x0)
#define MISCREG_BPMP_SECURITY_0_G5R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define MISCREG_BPMP_SECURITY_0_G5R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define MISCREG_BPMP_SECURITY_0_G5R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define MISCREG_BPMP_SECURITY_0_G5R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define MISCREG_BPMP_SECURITY_0_G5R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define MISCREG_BPMP_SECURITY_0_G4R_SHIFT                       _MK_SHIFT_CONST(4)
#define MISCREG_BPMP_SECURITY_0_G4R_FIELD                       _MK_FIELD_CONST(0x1, MISCREG_BPMP_SECURITY_0_G4R_SHIFT)
#define MISCREG_BPMP_SECURITY_0_G4R_RANGE                       4:4
#define MISCREG_BPMP_SECURITY_0_G4R_WOFFSET                     0x0
#define MISCREG_BPMP_SECURITY_0_G4R_DEFAULT                     _MK_MASK_CONST(0x0)
#define MISCREG_BPMP_SECURITY_0_G4R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define MISCREG_BPMP_SECURITY_0_G4R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define MISCREG_BPMP_SECURITY_0_G4R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define MISCREG_BPMP_SECURITY_0_G4R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define MISCREG_BPMP_SECURITY_0_G4R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define MISCREG_BPMP_SECURITY_0_G3R_SHIFT                       _MK_SHIFT_CONST(3)
#define MISCREG_BPMP_SECURITY_0_G3R_FIELD                       _MK_FIELD_CONST(0x1, MISCREG_BPMP_SECURITY_0_G3R_SHIFT)
#define MISCREG_BPMP_SECURITY_0_G3R_RANGE                       3:3
#define MISCREG_BPMP_SECURITY_0_G3R_WOFFSET                     0x0
#define MISCREG_BPMP_SECURITY_0_G3R_DEFAULT                     _MK_MASK_CONST(0x0)
#define MISCREG_BPMP_SECURITY_0_G3R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define MISCREG_BPMP_SECURITY_0_G3R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define MISCREG_BPMP_SECURITY_0_G3R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define MISCREG_BPMP_SECURITY_0_G3R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define MISCREG_BPMP_SECURITY_0_G3R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define MISCREG_BPMP_SECURITY_0_G2R_SHIFT                       _MK_SHIFT_CONST(2)
#define MISCREG_BPMP_SECURITY_0_G2R_FIELD                       _MK_FIELD_CONST(0x1, MISCREG_BPMP_SECURITY_0_G2R_SHIFT)
#define MISCREG_BPMP_SECURITY_0_G2R_RANGE                       2:2
#define MISCREG_BPMP_SECURITY_0_G2R_WOFFSET                     0x0
#define MISCREG_BPMP_SECURITY_0_G2R_DEFAULT                     _MK_MASK_CONST(0x0)
#define MISCREG_BPMP_SECURITY_0_G2R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define MISCREG_BPMP_SECURITY_0_G2R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define MISCREG_BPMP_SECURITY_0_G2R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define MISCREG_BPMP_SECURITY_0_G2R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define MISCREG_BPMP_SECURITY_0_G2R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define MISCREG_BPMP_SECURITY_0_G1R_SHIFT                       _MK_SHIFT_CONST(1)
#define MISCREG_BPMP_SECURITY_0_G1R_FIELD                       _MK_FIELD_CONST(0x1, MISCREG_BPMP_SECURITY_0_G1R_SHIFT)
#define MISCREG_BPMP_SECURITY_0_G1R_RANGE                       1:1
#define MISCREG_BPMP_SECURITY_0_G1R_WOFFSET                     0x0
#define MISCREG_BPMP_SECURITY_0_G1R_DEFAULT                     _MK_MASK_CONST(0x0)
#define MISCREG_BPMP_SECURITY_0_G1R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define MISCREG_BPMP_SECURITY_0_G1R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define MISCREG_BPMP_SECURITY_0_G1R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define MISCREG_BPMP_SECURITY_0_G1R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define MISCREG_BPMP_SECURITY_0_G1R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define MISCREG_BPMP_SECURITY_0_G0R_SHIFT                       _MK_SHIFT_CONST(0)
#define MISCREG_BPMP_SECURITY_0_G0R_FIELD                       _MK_FIELD_CONST(0x1, MISCREG_BPMP_SECURITY_0_G0R_SHIFT)
#define MISCREG_BPMP_SECURITY_0_G0R_RANGE                       0:0
#define MISCREG_BPMP_SECURITY_0_G0R_WOFFSET                     0x0
#define MISCREG_BPMP_SECURITY_0_G0R_DEFAULT                     _MK_MASK_CONST(0x0)
#define MISCREG_BPMP_SECURITY_0_G0R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define MISCREG_BPMP_SECURITY_0_G0R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define MISCREG_BPMP_SECURITY_0_G0R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define MISCREG_BPMP_SECURITY_0_G0R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define MISCREG_BPMP_SECURITY_0_G0R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)


// Register MISCREG_CPU_SECURITY_0
#define MISCREG_CPU_SECURITY_0                  _MK_ADDR_CONST(0x1008)
#define MISCREG_CPU_SECURITY_0_SECURE                   0x0
#define MISCREG_CPU_SECURITY_0_DUAL                     0x0
#define MISCREG_CPU_SECURITY_0_SCR                      SCRCPU_0
#define MISCREG_CPU_SECURITY_0_WORD_COUNT                       0x1
#define MISCREG_CPU_SECURITY_0_RESET_VAL                        _MK_MASK_CONST(0x1ffff)
#define MISCREG_CPU_SECURITY_0_RESET_MASK                       _MK_MASK_CONST(0xfffff)
#define MISCREG_CPU_SECURITY_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define MISCREG_CPU_SECURITY_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define MISCREG_CPU_SECURITY_0_READ_MASK                        _MK_MASK_CONST(0xfffff)
#define MISCREG_CPU_SECURITY_0_WRITE_MASK                       _MK_MASK_CONST(0xffff)
#define MISCREG_CPU_SECURITY_0_MSTR_ID_SHIFT                    _MK_SHIFT_CONST(16)
#define MISCREG_CPU_SECURITY_0_MSTR_ID_FIELD                    _MK_FIELD_CONST(0xf, MISCREG_CPU_SECURITY_0_MSTR_ID_SHIFT)
#define MISCREG_CPU_SECURITY_0_MSTR_ID_RANGE                    19:16
#define MISCREG_CPU_SECURITY_0_MSTR_ID_WOFFSET                  0x0
#define MISCREG_CPU_SECURITY_0_MSTR_ID_DEFAULT                  _MK_MASK_CONST(0x1)
#define MISCREG_CPU_SECURITY_0_MSTR_ID_DEFAULT_MASK                     _MK_MASK_CONST(0xf)
#define MISCREG_CPU_SECURITY_0_MSTR_ID_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define MISCREG_CPU_SECURITY_0_MSTR_ID_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define MISCREG_CPU_SECURITY_0_MSTR_ID_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define MISCREG_CPU_SECURITY_0_MSTR_ID_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)
#define MISCREG_CPU_SECURITY_0_MSTR_ID_CCPLEX                   _MK_ENUM_CONST(1)
#define MISCREG_CPU_SECURITY_0_MSTR_ID_CCPLEX_DPMU                      _MK_ENUM_CONST(2)
#define MISCREG_CPU_SECURITY_0_MSTR_ID_BPMP                     _MK_ENUM_CONST(3)
#define MISCREG_CPU_SECURITY_0_MSTR_ID_SPE                      _MK_ENUM_CONST(4)
#define MISCREG_CPU_SECURITY_0_MSTR_ID_SCE                      _MK_ENUM_CONST(5)
#define MISCREG_CPU_SECURITY_0_MSTR_ID_DMA_PER                  _MK_ENUM_CONST(6)
#define MISCREG_CPU_SECURITY_0_MSTR_ID_TSECA                    _MK_ENUM_CONST(7)
#define MISCREG_CPU_SECURITY_0_MSTR_ID_TSECB                    _MK_ENUM_CONST(8)
#define MISCREG_CPU_SECURITY_0_MSTR_ID_JTAGM                    _MK_ENUM_CONST(9)
#define MISCREG_CPU_SECURITY_0_MSTR_ID_CSITE                    _MK_ENUM_CONST(10)
#define MISCREG_CPU_SECURITY_0_MSTR_ID_APE                      _MK_ENUM_CONST(11)
#define MISCREG_CPU_SECURITY_0_MSTR_ID_Peatrans                 _MK_ENUM_CONST(12)
#define MISCREG_CPU_SECURITY_0_MSTR_ID_NVDEC                    _MK_ENUM_CONST(13)
#define MISCREG_CPU_SECURITY_0_MSTR_ID_RCE                      _MK_ENUM_CONST(14)
#define MISCREG_CPU_SECURITY_0_MSTR_ID_NVDEC1                   _MK_ENUM_CONST(15)

#define MISCREG_CPU_SECURITY_0_G7W_SHIFT                        _MK_SHIFT_CONST(15)
#define MISCREG_CPU_SECURITY_0_G7W_FIELD                        _MK_FIELD_CONST(0x1, MISCREG_CPU_SECURITY_0_G7W_SHIFT)
#define MISCREG_CPU_SECURITY_0_G7W_RANGE                        15:15
#define MISCREG_CPU_SECURITY_0_G7W_WOFFSET                      0x0
#define MISCREG_CPU_SECURITY_0_G7W_DEFAULT                      _MK_MASK_CONST(0x1)
#define MISCREG_CPU_SECURITY_0_G7W_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define MISCREG_CPU_SECURITY_0_G7W_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define MISCREG_CPU_SECURITY_0_G7W_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define MISCREG_CPU_SECURITY_0_G7W_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define MISCREG_CPU_SECURITY_0_G7W_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define MISCREG_CPU_SECURITY_0_G6W_SHIFT                        _MK_SHIFT_CONST(14)
#define MISCREG_CPU_SECURITY_0_G6W_FIELD                        _MK_FIELD_CONST(0x1, MISCREG_CPU_SECURITY_0_G6W_SHIFT)
#define MISCREG_CPU_SECURITY_0_G6W_RANGE                        14:14
#define MISCREG_CPU_SECURITY_0_G6W_WOFFSET                      0x0
#define MISCREG_CPU_SECURITY_0_G6W_DEFAULT                      _MK_MASK_CONST(0x1)
#define MISCREG_CPU_SECURITY_0_G6W_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define MISCREG_CPU_SECURITY_0_G6W_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define MISCREG_CPU_SECURITY_0_G6W_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define MISCREG_CPU_SECURITY_0_G6W_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define MISCREG_CPU_SECURITY_0_G6W_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define MISCREG_CPU_SECURITY_0_G5W_SHIFT                        _MK_SHIFT_CONST(13)
#define MISCREG_CPU_SECURITY_0_G5W_FIELD                        _MK_FIELD_CONST(0x1, MISCREG_CPU_SECURITY_0_G5W_SHIFT)
#define MISCREG_CPU_SECURITY_0_G5W_RANGE                        13:13
#define MISCREG_CPU_SECURITY_0_G5W_WOFFSET                      0x0
#define MISCREG_CPU_SECURITY_0_G5W_DEFAULT                      _MK_MASK_CONST(0x1)
#define MISCREG_CPU_SECURITY_0_G5W_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define MISCREG_CPU_SECURITY_0_G5W_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define MISCREG_CPU_SECURITY_0_G5W_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define MISCREG_CPU_SECURITY_0_G5W_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define MISCREG_CPU_SECURITY_0_G5W_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define MISCREG_CPU_SECURITY_0_G4W_SHIFT                        _MK_SHIFT_CONST(12)
#define MISCREG_CPU_SECURITY_0_G4W_FIELD                        _MK_FIELD_CONST(0x1, MISCREG_CPU_SECURITY_0_G4W_SHIFT)
#define MISCREG_CPU_SECURITY_0_G4W_RANGE                        12:12
#define MISCREG_CPU_SECURITY_0_G4W_WOFFSET                      0x0
#define MISCREG_CPU_SECURITY_0_G4W_DEFAULT                      _MK_MASK_CONST(0x1)
#define MISCREG_CPU_SECURITY_0_G4W_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define MISCREG_CPU_SECURITY_0_G4W_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define MISCREG_CPU_SECURITY_0_G4W_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define MISCREG_CPU_SECURITY_0_G4W_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define MISCREG_CPU_SECURITY_0_G4W_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define MISCREG_CPU_SECURITY_0_G3W_SHIFT                        _MK_SHIFT_CONST(11)
#define MISCREG_CPU_SECURITY_0_G3W_FIELD                        _MK_FIELD_CONST(0x1, MISCREG_CPU_SECURITY_0_G3W_SHIFT)
#define MISCREG_CPU_SECURITY_0_G3W_RANGE                        11:11
#define MISCREG_CPU_SECURITY_0_G3W_WOFFSET                      0x0
#define MISCREG_CPU_SECURITY_0_G3W_DEFAULT                      _MK_MASK_CONST(0x1)
#define MISCREG_CPU_SECURITY_0_G3W_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define MISCREG_CPU_SECURITY_0_G3W_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define MISCREG_CPU_SECURITY_0_G3W_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define MISCREG_CPU_SECURITY_0_G3W_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define MISCREG_CPU_SECURITY_0_G3W_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define MISCREG_CPU_SECURITY_0_G2W_SHIFT                        _MK_SHIFT_CONST(10)
#define MISCREG_CPU_SECURITY_0_G2W_FIELD                        _MK_FIELD_CONST(0x1, MISCREG_CPU_SECURITY_0_G2W_SHIFT)
#define MISCREG_CPU_SECURITY_0_G2W_RANGE                        10:10
#define MISCREG_CPU_SECURITY_0_G2W_WOFFSET                      0x0
#define MISCREG_CPU_SECURITY_0_G2W_DEFAULT                      _MK_MASK_CONST(0x1)
#define MISCREG_CPU_SECURITY_0_G2W_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define MISCREG_CPU_SECURITY_0_G2W_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define MISCREG_CPU_SECURITY_0_G2W_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define MISCREG_CPU_SECURITY_0_G2W_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define MISCREG_CPU_SECURITY_0_G2W_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define MISCREG_CPU_SECURITY_0_G1W_SHIFT                        _MK_SHIFT_CONST(9)
#define MISCREG_CPU_SECURITY_0_G1W_FIELD                        _MK_FIELD_CONST(0x1, MISCREG_CPU_SECURITY_0_G1W_SHIFT)
#define MISCREG_CPU_SECURITY_0_G1W_RANGE                        9:9
#define MISCREG_CPU_SECURITY_0_G1W_WOFFSET                      0x0
#define MISCREG_CPU_SECURITY_0_G1W_DEFAULT                      _MK_MASK_CONST(0x1)
#define MISCREG_CPU_SECURITY_0_G1W_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define MISCREG_CPU_SECURITY_0_G1W_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define MISCREG_CPU_SECURITY_0_G1W_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define MISCREG_CPU_SECURITY_0_G1W_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define MISCREG_CPU_SECURITY_0_G1W_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define MISCREG_CPU_SECURITY_0_G0W_SHIFT                        _MK_SHIFT_CONST(8)
#define MISCREG_CPU_SECURITY_0_G0W_FIELD                        _MK_FIELD_CONST(0x1, MISCREG_CPU_SECURITY_0_G0W_SHIFT)
#define MISCREG_CPU_SECURITY_0_G0W_RANGE                        8:8
#define MISCREG_CPU_SECURITY_0_G0W_WOFFSET                      0x0
#define MISCREG_CPU_SECURITY_0_G0W_DEFAULT                      _MK_MASK_CONST(0x1)
#define MISCREG_CPU_SECURITY_0_G0W_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define MISCREG_CPU_SECURITY_0_G0W_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define MISCREG_CPU_SECURITY_0_G0W_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define MISCREG_CPU_SECURITY_0_G0W_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define MISCREG_CPU_SECURITY_0_G0W_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define MISCREG_CPU_SECURITY_0_G7R_SHIFT                        _MK_SHIFT_CONST(7)
#define MISCREG_CPU_SECURITY_0_G7R_FIELD                        _MK_FIELD_CONST(0x1, MISCREG_CPU_SECURITY_0_G7R_SHIFT)
#define MISCREG_CPU_SECURITY_0_G7R_RANGE                        7:7
#define MISCREG_CPU_SECURITY_0_G7R_WOFFSET                      0x0
#define MISCREG_CPU_SECURITY_0_G7R_DEFAULT                      _MK_MASK_CONST(0x1)
#define MISCREG_CPU_SECURITY_0_G7R_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define MISCREG_CPU_SECURITY_0_G7R_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define MISCREG_CPU_SECURITY_0_G7R_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define MISCREG_CPU_SECURITY_0_G7R_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define MISCREG_CPU_SECURITY_0_G7R_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define MISCREG_CPU_SECURITY_0_G6R_SHIFT                        _MK_SHIFT_CONST(6)
#define MISCREG_CPU_SECURITY_0_G6R_FIELD                        _MK_FIELD_CONST(0x1, MISCREG_CPU_SECURITY_0_G6R_SHIFT)
#define MISCREG_CPU_SECURITY_0_G6R_RANGE                        6:6
#define MISCREG_CPU_SECURITY_0_G6R_WOFFSET                      0x0
#define MISCREG_CPU_SECURITY_0_G6R_DEFAULT                      _MK_MASK_CONST(0x1)
#define MISCREG_CPU_SECURITY_0_G6R_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define MISCREG_CPU_SECURITY_0_G6R_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define MISCREG_CPU_SECURITY_0_G6R_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define MISCREG_CPU_SECURITY_0_G6R_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define MISCREG_CPU_SECURITY_0_G6R_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define MISCREG_CPU_SECURITY_0_G5R_SHIFT                        _MK_SHIFT_CONST(5)
#define MISCREG_CPU_SECURITY_0_G5R_FIELD                        _MK_FIELD_CONST(0x1, MISCREG_CPU_SECURITY_0_G5R_SHIFT)
#define MISCREG_CPU_SECURITY_0_G5R_RANGE                        5:5
#define MISCREG_CPU_SECURITY_0_G5R_WOFFSET                      0x0
#define MISCREG_CPU_SECURITY_0_G5R_DEFAULT                      _MK_MASK_CONST(0x1)
#define MISCREG_CPU_SECURITY_0_G5R_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define MISCREG_CPU_SECURITY_0_G5R_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define MISCREG_CPU_SECURITY_0_G5R_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define MISCREG_CPU_SECURITY_0_G5R_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define MISCREG_CPU_SECURITY_0_G5R_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define MISCREG_CPU_SECURITY_0_G4R_SHIFT                        _MK_SHIFT_CONST(4)
#define MISCREG_CPU_SECURITY_0_G4R_FIELD                        _MK_FIELD_CONST(0x1, MISCREG_CPU_SECURITY_0_G4R_SHIFT)
#define MISCREG_CPU_SECURITY_0_G4R_RANGE                        4:4
#define MISCREG_CPU_SECURITY_0_G4R_WOFFSET                      0x0
#define MISCREG_CPU_SECURITY_0_G4R_DEFAULT                      _MK_MASK_CONST(0x1)
#define MISCREG_CPU_SECURITY_0_G4R_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define MISCREG_CPU_SECURITY_0_G4R_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define MISCREG_CPU_SECURITY_0_G4R_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define MISCREG_CPU_SECURITY_0_G4R_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define MISCREG_CPU_SECURITY_0_G4R_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define MISCREG_CPU_SECURITY_0_G3R_SHIFT                        _MK_SHIFT_CONST(3)
#define MISCREG_CPU_SECURITY_0_G3R_FIELD                        _MK_FIELD_CONST(0x1, MISCREG_CPU_SECURITY_0_G3R_SHIFT)
#define MISCREG_CPU_SECURITY_0_G3R_RANGE                        3:3
#define MISCREG_CPU_SECURITY_0_G3R_WOFFSET                      0x0
#define MISCREG_CPU_SECURITY_0_G3R_DEFAULT                      _MK_MASK_CONST(0x1)
#define MISCREG_CPU_SECURITY_0_G3R_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define MISCREG_CPU_SECURITY_0_G3R_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define MISCREG_CPU_SECURITY_0_G3R_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define MISCREG_CPU_SECURITY_0_G3R_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define MISCREG_CPU_SECURITY_0_G3R_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define MISCREG_CPU_SECURITY_0_G2R_SHIFT                        _MK_SHIFT_CONST(2)
#define MISCREG_CPU_SECURITY_0_G2R_FIELD                        _MK_FIELD_CONST(0x1, MISCREG_CPU_SECURITY_0_G2R_SHIFT)
#define MISCREG_CPU_SECURITY_0_G2R_RANGE                        2:2
#define MISCREG_CPU_SECURITY_0_G2R_WOFFSET                      0x0
#define MISCREG_CPU_SECURITY_0_G2R_DEFAULT                      _MK_MASK_CONST(0x1)
#define MISCREG_CPU_SECURITY_0_G2R_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define MISCREG_CPU_SECURITY_0_G2R_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define MISCREG_CPU_SECURITY_0_G2R_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define MISCREG_CPU_SECURITY_0_G2R_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define MISCREG_CPU_SECURITY_0_G2R_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define MISCREG_CPU_SECURITY_0_G1R_SHIFT                        _MK_SHIFT_CONST(1)
#define MISCREG_CPU_SECURITY_0_G1R_FIELD                        _MK_FIELD_CONST(0x1, MISCREG_CPU_SECURITY_0_G1R_SHIFT)
#define MISCREG_CPU_SECURITY_0_G1R_RANGE                        1:1
#define MISCREG_CPU_SECURITY_0_G1R_WOFFSET                      0x0
#define MISCREG_CPU_SECURITY_0_G1R_DEFAULT                      _MK_MASK_CONST(0x1)
#define MISCREG_CPU_SECURITY_0_G1R_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define MISCREG_CPU_SECURITY_0_G1R_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define MISCREG_CPU_SECURITY_0_G1R_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define MISCREG_CPU_SECURITY_0_G1R_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define MISCREG_CPU_SECURITY_0_G1R_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define MISCREG_CPU_SECURITY_0_G0R_SHIFT                        _MK_SHIFT_CONST(0)
#define MISCREG_CPU_SECURITY_0_G0R_FIELD                        _MK_FIELD_CONST(0x1, MISCREG_CPU_SECURITY_0_G0R_SHIFT)
#define MISCREG_CPU_SECURITY_0_G0R_RANGE                        0:0
#define MISCREG_CPU_SECURITY_0_G0R_WOFFSET                      0x0
#define MISCREG_CPU_SECURITY_0_G0R_DEFAULT                      _MK_MASK_CONST(0x1)
#define MISCREG_CPU_SECURITY_0_G0R_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define MISCREG_CPU_SECURITY_0_G0R_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define MISCREG_CPU_SECURITY_0_G0R_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define MISCREG_CPU_SECURITY_0_G0R_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define MISCREG_CPU_SECURITY_0_G0R_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)


// Register MISCREG_APE_SECURITY_0
#define MISCREG_APE_SECURITY_0                  _MK_ADDR_CONST(0x100c)
#define MISCREG_APE_SECURITY_0_SECURE                   0x0
#define MISCREG_APE_SECURITY_0_DUAL                     0x0
#define MISCREG_APE_SECURITY_0_SCR                      SCRAPE_0
#define MISCREG_APE_SECURITY_0_WORD_COUNT                       0x1
#define MISCREG_APE_SECURITY_0_RESET_VAL                        _MK_MASK_CONST(0xbffff)
#define MISCREG_APE_SECURITY_0_RESET_MASK                       _MK_MASK_CONST(0xfffff)
#define MISCREG_APE_SECURITY_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define MISCREG_APE_SECURITY_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define MISCREG_APE_SECURITY_0_READ_MASK                        _MK_MASK_CONST(0xfffff)
#define MISCREG_APE_SECURITY_0_WRITE_MASK                       _MK_MASK_CONST(0xffff)
#define MISCREG_APE_SECURITY_0_MSTR_ID_SHIFT                    _MK_SHIFT_CONST(16)
#define MISCREG_APE_SECURITY_0_MSTR_ID_FIELD                    _MK_FIELD_CONST(0xf, MISCREG_APE_SECURITY_0_MSTR_ID_SHIFT)
#define MISCREG_APE_SECURITY_0_MSTR_ID_RANGE                    19:16
#define MISCREG_APE_SECURITY_0_MSTR_ID_WOFFSET                  0x0
#define MISCREG_APE_SECURITY_0_MSTR_ID_DEFAULT                  _MK_MASK_CONST(0xb)
#define MISCREG_APE_SECURITY_0_MSTR_ID_DEFAULT_MASK                     _MK_MASK_CONST(0xf)
#define MISCREG_APE_SECURITY_0_MSTR_ID_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define MISCREG_APE_SECURITY_0_MSTR_ID_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define MISCREG_APE_SECURITY_0_MSTR_ID_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define MISCREG_APE_SECURITY_0_MSTR_ID_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)
#define MISCREG_APE_SECURITY_0_MSTR_ID_CCPLEX                   _MK_ENUM_CONST(1)
#define MISCREG_APE_SECURITY_0_MSTR_ID_CCPLEX_DPMU                      _MK_ENUM_CONST(2)
#define MISCREG_APE_SECURITY_0_MSTR_ID_BPMP                     _MK_ENUM_CONST(3)
#define MISCREG_APE_SECURITY_0_MSTR_ID_SPE                      _MK_ENUM_CONST(4)
#define MISCREG_APE_SECURITY_0_MSTR_ID_SCE                      _MK_ENUM_CONST(5)
#define MISCREG_APE_SECURITY_0_MSTR_ID_DMA_PER                  _MK_ENUM_CONST(6)
#define MISCREG_APE_SECURITY_0_MSTR_ID_TSECA                    _MK_ENUM_CONST(7)
#define MISCREG_APE_SECURITY_0_MSTR_ID_TSECB                    _MK_ENUM_CONST(8)
#define MISCREG_APE_SECURITY_0_MSTR_ID_JTAGM                    _MK_ENUM_CONST(9)
#define MISCREG_APE_SECURITY_0_MSTR_ID_CSITE                    _MK_ENUM_CONST(10)
#define MISCREG_APE_SECURITY_0_MSTR_ID_APE                      _MK_ENUM_CONST(11)
#define MISCREG_APE_SECURITY_0_MSTR_ID_Peatrans                 _MK_ENUM_CONST(12)
#define MISCREG_APE_SECURITY_0_MSTR_ID_NVDEC                    _MK_ENUM_CONST(13)
#define MISCREG_APE_SECURITY_0_MSTR_ID_RCE                      _MK_ENUM_CONST(14)
#define MISCREG_APE_SECURITY_0_MSTR_ID_NVDEC1                   _MK_ENUM_CONST(15)

#define MISCREG_APE_SECURITY_0_G7W_SHIFT                        _MK_SHIFT_CONST(15)
#define MISCREG_APE_SECURITY_0_G7W_FIELD                        _MK_FIELD_CONST(0x1, MISCREG_APE_SECURITY_0_G7W_SHIFT)
#define MISCREG_APE_SECURITY_0_G7W_RANGE                        15:15
#define MISCREG_APE_SECURITY_0_G7W_WOFFSET                      0x0
#define MISCREG_APE_SECURITY_0_G7W_DEFAULT                      _MK_MASK_CONST(0x1)
#define MISCREG_APE_SECURITY_0_G7W_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define MISCREG_APE_SECURITY_0_G7W_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define MISCREG_APE_SECURITY_0_G7W_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define MISCREG_APE_SECURITY_0_G7W_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define MISCREG_APE_SECURITY_0_G7W_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define MISCREG_APE_SECURITY_0_G6W_SHIFT                        _MK_SHIFT_CONST(14)
#define MISCREG_APE_SECURITY_0_G6W_FIELD                        _MK_FIELD_CONST(0x1, MISCREG_APE_SECURITY_0_G6W_SHIFT)
#define MISCREG_APE_SECURITY_0_G6W_RANGE                        14:14
#define MISCREG_APE_SECURITY_0_G6W_WOFFSET                      0x0
#define MISCREG_APE_SECURITY_0_G6W_DEFAULT                      _MK_MASK_CONST(0x1)
#define MISCREG_APE_SECURITY_0_G6W_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define MISCREG_APE_SECURITY_0_G6W_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define MISCREG_APE_SECURITY_0_G6W_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define MISCREG_APE_SECURITY_0_G6W_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define MISCREG_APE_SECURITY_0_G6W_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define MISCREG_APE_SECURITY_0_G5W_SHIFT                        _MK_SHIFT_CONST(13)
#define MISCREG_APE_SECURITY_0_G5W_FIELD                        _MK_FIELD_CONST(0x1, MISCREG_APE_SECURITY_0_G5W_SHIFT)
#define MISCREG_APE_SECURITY_0_G5W_RANGE                        13:13
#define MISCREG_APE_SECURITY_0_G5W_WOFFSET                      0x0
#define MISCREG_APE_SECURITY_0_G5W_DEFAULT                      _MK_MASK_CONST(0x1)
#define MISCREG_APE_SECURITY_0_G5W_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define MISCREG_APE_SECURITY_0_G5W_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define MISCREG_APE_SECURITY_0_G5W_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define MISCREG_APE_SECURITY_0_G5W_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define MISCREG_APE_SECURITY_0_G5W_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define MISCREG_APE_SECURITY_0_G4W_SHIFT                        _MK_SHIFT_CONST(12)
#define MISCREG_APE_SECURITY_0_G4W_FIELD                        _MK_FIELD_CONST(0x1, MISCREG_APE_SECURITY_0_G4W_SHIFT)
#define MISCREG_APE_SECURITY_0_G4W_RANGE                        12:12
#define MISCREG_APE_SECURITY_0_G4W_WOFFSET                      0x0
#define MISCREG_APE_SECURITY_0_G4W_DEFAULT                      _MK_MASK_CONST(0x1)
#define MISCREG_APE_SECURITY_0_G4W_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define MISCREG_APE_SECURITY_0_G4W_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define MISCREG_APE_SECURITY_0_G4W_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define MISCREG_APE_SECURITY_0_G4W_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define MISCREG_APE_SECURITY_0_G4W_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define MISCREG_APE_SECURITY_0_G3W_SHIFT                        _MK_SHIFT_CONST(11)
#define MISCREG_APE_SECURITY_0_G3W_FIELD                        _MK_FIELD_CONST(0x1, MISCREG_APE_SECURITY_0_G3W_SHIFT)
#define MISCREG_APE_SECURITY_0_G3W_RANGE                        11:11
#define MISCREG_APE_SECURITY_0_G3W_WOFFSET                      0x0
#define MISCREG_APE_SECURITY_0_G3W_DEFAULT                      _MK_MASK_CONST(0x1)
#define MISCREG_APE_SECURITY_0_G3W_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define MISCREG_APE_SECURITY_0_G3W_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define MISCREG_APE_SECURITY_0_G3W_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define MISCREG_APE_SECURITY_0_G3W_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define MISCREG_APE_SECURITY_0_G3W_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define MISCREG_APE_SECURITY_0_G2W_SHIFT                        _MK_SHIFT_CONST(10)
#define MISCREG_APE_SECURITY_0_G2W_FIELD                        _MK_FIELD_CONST(0x1, MISCREG_APE_SECURITY_0_G2W_SHIFT)
#define MISCREG_APE_SECURITY_0_G2W_RANGE                        10:10
#define MISCREG_APE_SECURITY_0_G2W_WOFFSET                      0x0
#define MISCREG_APE_SECURITY_0_G2W_DEFAULT                      _MK_MASK_CONST(0x1)
#define MISCREG_APE_SECURITY_0_G2W_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define MISCREG_APE_SECURITY_0_G2W_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define MISCREG_APE_SECURITY_0_G2W_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define MISCREG_APE_SECURITY_0_G2W_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define MISCREG_APE_SECURITY_0_G2W_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define MISCREG_APE_SECURITY_0_G1W_SHIFT                        _MK_SHIFT_CONST(9)
#define MISCREG_APE_SECURITY_0_G1W_FIELD                        _MK_FIELD_CONST(0x1, MISCREG_APE_SECURITY_0_G1W_SHIFT)
#define MISCREG_APE_SECURITY_0_G1W_RANGE                        9:9
#define MISCREG_APE_SECURITY_0_G1W_WOFFSET                      0x0
#define MISCREG_APE_SECURITY_0_G1W_DEFAULT                      _MK_MASK_CONST(0x1)
#define MISCREG_APE_SECURITY_0_G1W_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define MISCREG_APE_SECURITY_0_G1W_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define MISCREG_APE_SECURITY_0_G1W_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define MISCREG_APE_SECURITY_0_G1W_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define MISCREG_APE_SECURITY_0_G1W_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define MISCREG_APE_SECURITY_0_G0W_SHIFT                        _MK_SHIFT_CONST(8)
#define MISCREG_APE_SECURITY_0_G0W_FIELD                        _MK_FIELD_CONST(0x1, MISCREG_APE_SECURITY_0_G0W_SHIFT)
#define MISCREG_APE_SECURITY_0_G0W_RANGE                        8:8
#define MISCREG_APE_SECURITY_0_G0W_WOFFSET                      0x0
#define MISCREG_APE_SECURITY_0_G0W_DEFAULT                      _MK_MASK_CONST(0x1)
#define MISCREG_APE_SECURITY_0_G0W_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define MISCREG_APE_SECURITY_0_G0W_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define MISCREG_APE_SECURITY_0_G0W_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define MISCREG_APE_SECURITY_0_G0W_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define MISCREG_APE_SECURITY_0_G0W_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define MISCREG_APE_SECURITY_0_G7R_SHIFT                        _MK_SHIFT_CONST(7)
#define MISCREG_APE_SECURITY_0_G7R_FIELD                        _MK_FIELD_CONST(0x1, MISCREG_APE_SECURITY_0_G7R_SHIFT)
#define MISCREG_APE_SECURITY_0_G7R_RANGE                        7:7
#define MISCREG_APE_SECURITY_0_G7R_WOFFSET                      0x0
#define MISCREG_APE_SECURITY_0_G7R_DEFAULT                      _MK_MASK_CONST(0x1)
#define MISCREG_APE_SECURITY_0_G7R_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define MISCREG_APE_SECURITY_0_G7R_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define MISCREG_APE_SECURITY_0_G7R_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define MISCREG_APE_SECURITY_0_G7R_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define MISCREG_APE_SECURITY_0_G7R_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define MISCREG_APE_SECURITY_0_G6R_SHIFT                        _MK_SHIFT_CONST(6)
#define MISCREG_APE_SECURITY_0_G6R_FIELD                        _MK_FIELD_CONST(0x1, MISCREG_APE_SECURITY_0_G6R_SHIFT)
#define MISCREG_APE_SECURITY_0_G6R_RANGE                        6:6
#define MISCREG_APE_SECURITY_0_G6R_WOFFSET                      0x0
#define MISCREG_APE_SECURITY_0_G6R_DEFAULT                      _MK_MASK_CONST(0x1)
#define MISCREG_APE_SECURITY_0_G6R_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define MISCREG_APE_SECURITY_0_G6R_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define MISCREG_APE_SECURITY_0_G6R_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define MISCREG_APE_SECURITY_0_G6R_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define MISCREG_APE_SECURITY_0_G6R_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define MISCREG_APE_SECURITY_0_G5R_SHIFT                        _MK_SHIFT_CONST(5)
#define MISCREG_APE_SECURITY_0_G5R_FIELD                        _MK_FIELD_CONST(0x1, MISCREG_APE_SECURITY_0_G5R_SHIFT)
#define MISCREG_APE_SECURITY_0_G5R_RANGE                        5:5
#define MISCREG_APE_SECURITY_0_G5R_WOFFSET                      0x0
#define MISCREG_APE_SECURITY_0_G5R_DEFAULT                      _MK_MASK_CONST(0x1)
#define MISCREG_APE_SECURITY_0_G5R_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define MISCREG_APE_SECURITY_0_G5R_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define MISCREG_APE_SECURITY_0_G5R_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define MISCREG_APE_SECURITY_0_G5R_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define MISCREG_APE_SECURITY_0_G5R_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define MISCREG_APE_SECURITY_0_G4R_SHIFT                        _MK_SHIFT_CONST(4)
#define MISCREG_APE_SECURITY_0_G4R_FIELD                        _MK_FIELD_CONST(0x1, MISCREG_APE_SECURITY_0_G4R_SHIFT)
#define MISCREG_APE_SECURITY_0_G4R_RANGE                        4:4
#define MISCREG_APE_SECURITY_0_G4R_WOFFSET                      0x0
#define MISCREG_APE_SECURITY_0_G4R_DEFAULT                      _MK_MASK_CONST(0x1)
#define MISCREG_APE_SECURITY_0_G4R_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define MISCREG_APE_SECURITY_0_G4R_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define MISCREG_APE_SECURITY_0_G4R_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define MISCREG_APE_SECURITY_0_G4R_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define MISCREG_APE_SECURITY_0_G4R_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define MISCREG_APE_SECURITY_0_G3R_SHIFT                        _MK_SHIFT_CONST(3)
#define MISCREG_APE_SECURITY_0_G3R_FIELD                        _MK_FIELD_CONST(0x1, MISCREG_APE_SECURITY_0_G3R_SHIFT)
#define MISCREG_APE_SECURITY_0_G3R_RANGE                        3:3
#define MISCREG_APE_SECURITY_0_G3R_WOFFSET                      0x0
#define MISCREG_APE_SECURITY_0_G3R_DEFAULT                      _MK_MASK_CONST(0x1)
#define MISCREG_APE_SECURITY_0_G3R_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define MISCREG_APE_SECURITY_0_G3R_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define MISCREG_APE_SECURITY_0_G3R_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define MISCREG_APE_SECURITY_0_G3R_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define MISCREG_APE_SECURITY_0_G3R_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define MISCREG_APE_SECURITY_0_G2R_SHIFT                        _MK_SHIFT_CONST(2)
#define MISCREG_APE_SECURITY_0_G2R_FIELD                        _MK_FIELD_CONST(0x1, MISCREG_APE_SECURITY_0_G2R_SHIFT)
#define MISCREG_APE_SECURITY_0_G2R_RANGE                        2:2
#define MISCREG_APE_SECURITY_0_G2R_WOFFSET                      0x0
#define MISCREG_APE_SECURITY_0_G2R_DEFAULT                      _MK_MASK_CONST(0x1)
#define MISCREG_APE_SECURITY_0_G2R_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define MISCREG_APE_SECURITY_0_G2R_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define MISCREG_APE_SECURITY_0_G2R_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define MISCREG_APE_SECURITY_0_G2R_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define MISCREG_APE_SECURITY_0_G2R_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define MISCREG_APE_SECURITY_0_G1R_SHIFT                        _MK_SHIFT_CONST(1)
#define MISCREG_APE_SECURITY_0_G1R_FIELD                        _MK_FIELD_CONST(0x1, MISCREG_APE_SECURITY_0_G1R_SHIFT)
#define MISCREG_APE_SECURITY_0_G1R_RANGE                        1:1
#define MISCREG_APE_SECURITY_0_G1R_WOFFSET                      0x0
#define MISCREG_APE_SECURITY_0_G1R_DEFAULT                      _MK_MASK_CONST(0x1)
#define MISCREG_APE_SECURITY_0_G1R_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define MISCREG_APE_SECURITY_0_G1R_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define MISCREG_APE_SECURITY_0_G1R_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define MISCREG_APE_SECURITY_0_G1R_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define MISCREG_APE_SECURITY_0_G1R_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define MISCREG_APE_SECURITY_0_G0R_SHIFT                        _MK_SHIFT_CONST(0)
#define MISCREG_APE_SECURITY_0_G0R_FIELD                        _MK_FIELD_CONST(0x1, MISCREG_APE_SECURITY_0_G0R_SHIFT)
#define MISCREG_APE_SECURITY_0_G0R_RANGE                        0:0
#define MISCREG_APE_SECURITY_0_G0R_WOFFSET                      0x0
#define MISCREG_APE_SECURITY_0_G0R_DEFAULT                      _MK_MASK_CONST(0x1)
#define MISCREG_APE_SECURITY_0_G0R_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define MISCREG_APE_SECURITY_0_G0R_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define MISCREG_APE_SECURITY_0_G0R_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define MISCREG_APE_SECURITY_0_G0R_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define MISCREG_APE_SECURITY_0_G0R_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)


// Register MISCREG_GPCDMA_SECURITY_0
#define MISCREG_GPCDMA_SECURITY_0                       _MK_ADDR_CONST(0x1010)
#define MISCREG_GPCDMA_SECURITY_0_SECURE                        0x0
#define MISCREG_GPCDMA_SECURITY_0_DUAL                  0x0
#define MISCREG_GPCDMA_SECURITY_0_SCR                   SCRDMA_0
#define MISCREG_GPCDMA_SECURITY_0_WORD_COUNT                    0x1
#define MISCREG_GPCDMA_SECURITY_0_RESET_VAL                     _MK_MASK_CONST(0x6ffff)
#define MISCREG_GPCDMA_SECURITY_0_RESET_MASK                    _MK_MASK_CONST(0xfffff)
#define MISCREG_GPCDMA_SECURITY_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define MISCREG_GPCDMA_SECURITY_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define MISCREG_GPCDMA_SECURITY_0_READ_MASK                     _MK_MASK_CONST(0xfffff)
#define MISCREG_GPCDMA_SECURITY_0_WRITE_MASK                    _MK_MASK_CONST(0xffff)
#define MISCREG_GPCDMA_SECURITY_0_MSTR_ID_SHIFT                 _MK_SHIFT_CONST(16)
#define MISCREG_GPCDMA_SECURITY_0_MSTR_ID_FIELD                 _MK_FIELD_CONST(0xf, MISCREG_GPCDMA_SECURITY_0_MSTR_ID_SHIFT)
#define MISCREG_GPCDMA_SECURITY_0_MSTR_ID_RANGE                 19:16
#define MISCREG_GPCDMA_SECURITY_0_MSTR_ID_WOFFSET                       0x0
#define MISCREG_GPCDMA_SECURITY_0_MSTR_ID_DEFAULT                       _MK_MASK_CONST(0x6)
#define MISCREG_GPCDMA_SECURITY_0_MSTR_ID_DEFAULT_MASK                  _MK_MASK_CONST(0xf)
#define MISCREG_GPCDMA_SECURITY_0_MSTR_ID_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define MISCREG_GPCDMA_SECURITY_0_MSTR_ID_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define MISCREG_GPCDMA_SECURITY_0_MSTR_ID_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define MISCREG_GPCDMA_SECURITY_0_MSTR_ID_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)
#define MISCREG_GPCDMA_SECURITY_0_MSTR_ID_CCPLEX                        _MK_ENUM_CONST(1)
#define MISCREG_GPCDMA_SECURITY_0_MSTR_ID_CCPLEX_DPMU                   _MK_ENUM_CONST(2)
#define MISCREG_GPCDMA_SECURITY_0_MSTR_ID_BPMP                  _MK_ENUM_CONST(3)
#define MISCREG_GPCDMA_SECURITY_0_MSTR_ID_SPE                   _MK_ENUM_CONST(4)
#define MISCREG_GPCDMA_SECURITY_0_MSTR_ID_SCE                   _MK_ENUM_CONST(5)
#define MISCREG_GPCDMA_SECURITY_0_MSTR_ID_DMA_PER                       _MK_ENUM_CONST(6)
#define MISCREG_GPCDMA_SECURITY_0_MSTR_ID_TSECA                 _MK_ENUM_CONST(7)
#define MISCREG_GPCDMA_SECURITY_0_MSTR_ID_TSECB                 _MK_ENUM_CONST(8)
#define MISCREG_GPCDMA_SECURITY_0_MSTR_ID_JTAGM                 _MK_ENUM_CONST(9)
#define MISCREG_GPCDMA_SECURITY_0_MSTR_ID_CSITE                 _MK_ENUM_CONST(10)
#define MISCREG_GPCDMA_SECURITY_0_MSTR_ID_APE                   _MK_ENUM_CONST(11)
#define MISCREG_GPCDMA_SECURITY_0_MSTR_ID_Peatrans                      _MK_ENUM_CONST(12)
#define MISCREG_GPCDMA_SECURITY_0_MSTR_ID_NVDEC                 _MK_ENUM_CONST(13)
#define MISCREG_GPCDMA_SECURITY_0_MSTR_ID_RCE                   _MK_ENUM_CONST(14)
#define MISCREG_GPCDMA_SECURITY_0_MSTR_ID_NVDEC1                        _MK_ENUM_CONST(15)

#define MISCREG_GPCDMA_SECURITY_0_G7W_SHIFT                     _MK_SHIFT_CONST(15)
#define MISCREG_GPCDMA_SECURITY_0_G7W_FIELD                     _MK_FIELD_CONST(0x1, MISCREG_GPCDMA_SECURITY_0_G7W_SHIFT)
#define MISCREG_GPCDMA_SECURITY_0_G7W_RANGE                     15:15
#define MISCREG_GPCDMA_SECURITY_0_G7W_WOFFSET                   0x0
#define MISCREG_GPCDMA_SECURITY_0_G7W_DEFAULT                   _MK_MASK_CONST(0x1)
#define MISCREG_GPCDMA_SECURITY_0_G7W_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define MISCREG_GPCDMA_SECURITY_0_G7W_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define MISCREG_GPCDMA_SECURITY_0_G7W_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define MISCREG_GPCDMA_SECURITY_0_G7W_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define MISCREG_GPCDMA_SECURITY_0_G7W_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)

#define MISCREG_GPCDMA_SECURITY_0_G6W_SHIFT                     _MK_SHIFT_CONST(14)
#define MISCREG_GPCDMA_SECURITY_0_G6W_FIELD                     _MK_FIELD_CONST(0x1, MISCREG_GPCDMA_SECURITY_0_G6W_SHIFT)
#define MISCREG_GPCDMA_SECURITY_0_G6W_RANGE                     14:14
#define MISCREG_GPCDMA_SECURITY_0_G6W_WOFFSET                   0x0
#define MISCREG_GPCDMA_SECURITY_0_G6W_DEFAULT                   _MK_MASK_CONST(0x1)
#define MISCREG_GPCDMA_SECURITY_0_G6W_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define MISCREG_GPCDMA_SECURITY_0_G6W_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define MISCREG_GPCDMA_SECURITY_0_G6W_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define MISCREG_GPCDMA_SECURITY_0_G6W_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define MISCREG_GPCDMA_SECURITY_0_G6W_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)

#define MISCREG_GPCDMA_SECURITY_0_G5W_SHIFT                     _MK_SHIFT_CONST(13)
#define MISCREG_GPCDMA_SECURITY_0_G5W_FIELD                     _MK_FIELD_CONST(0x1, MISCREG_GPCDMA_SECURITY_0_G5W_SHIFT)
#define MISCREG_GPCDMA_SECURITY_0_G5W_RANGE                     13:13
#define MISCREG_GPCDMA_SECURITY_0_G5W_WOFFSET                   0x0
#define MISCREG_GPCDMA_SECURITY_0_G5W_DEFAULT                   _MK_MASK_CONST(0x1)
#define MISCREG_GPCDMA_SECURITY_0_G5W_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define MISCREG_GPCDMA_SECURITY_0_G5W_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define MISCREG_GPCDMA_SECURITY_0_G5W_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define MISCREG_GPCDMA_SECURITY_0_G5W_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define MISCREG_GPCDMA_SECURITY_0_G5W_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)

#define MISCREG_GPCDMA_SECURITY_0_G4W_SHIFT                     _MK_SHIFT_CONST(12)
#define MISCREG_GPCDMA_SECURITY_0_G4W_FIELD                     _MK_FIELD_CONST(0x1, MISCREG_GPCDMA_SECURITY_0_G4W_SHIFT)
#define MISCREG_GPCDMA_SECURITY_0_G4W_RANGE                     12:12
#define MISCREG_GPCDMA_SECURITY_0_G4W_WOFFSET                   0x0
#define MISCREG_GPCDMA_SECURITY_0_G4W_DEFAULT                   _MK_MASK_CONST(0x1)
#define MISCREG_GPCDMA_SECURITY_0_G4W_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define MISCREG_GPCDMA_SECURITY_0_G4W_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define MISCREG_GPCDMA_SECURITY_0_G4W_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define MISCREG_GPCDMA_SECURITY_0_G4W_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define MISCREG_GPCDMA_SECURITY_0_G4W_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)

#define MISCREG_GPCDMA_SECURITY_0_G3W_SHIFT                     _MK_SHIFT_CONST(11)
#define MISCREG_GPCDMA_SECURITY_0_G3W_FIELD                     _MK_FIELD_CONST(0x1, MISCREG_GPCDMA_SECURITY_0_G3W_SHIFT)
#define MISCREG_GPCDMA_SECURITY_0_G3W_RANGE                     11:11
#define MISCREG_GPCDMA_SECURITY_0_G3W_WOFFSET                   0x0
#define MISCREG_GPCDMA_SECURITY_0_G3W_DEFAULT                   _MK_MASK_CONST(0x1)
#define MISCREG_GPCDMA_SECURITY_0_G3W_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define MISCREG_GPCDMA_SECURITY_0_G3W_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define MISCREG_GPCDMA_SECURITY_0_G3W_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define MISCREG_GPCDMA_SECURITY_0_G3W_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define MISCREG_GPCDMA_SECURITY_0_G3W_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)

#define MISCREG_GPCDMA_SECURITY_0_G2W_SHIFT                     _MK_SHIFT_CONST(10)
#define MISCREG_GPCDMA_SECURITY_0_G2W_FIELD                     _MK_FIELD_CONST(0x1, MISCREG_GPCDMA_SECURITY_0_G2W_SHIFT)
#define MISCREG_GPCDMA_SECURITY_0_G2W_RANGE                     10:10
#define MISCREG_GPCDMA_SECURITY_0_G2W_WOFFSET                   0x0
#define MISCREG_GPCDMA_SECURITY_0_G2W_DEFAULT                   _MK_MASK_CONST(0x1)
#define MISCREG_GPCDMA_SECURITY_0_G2W_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define MISCREG_GPCDMA_SECURITY_0_G2W_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define MISCREG_GPCDMA_SECURITY_0_G2W_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define MISCREG_GPCDMA_SECURITY_0_G2W_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define MISCREG_GPCDMA_SECURITY_0_G2W_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)

#define MISCREG_GPCDMA_SECURITY_0_G1W_SHIFT                     _MK_SHIFT_CONST(9)
#define MISCREG_GPCDMA_SECURITY_0_G1W_FIELD                     _MK_FIELD_CONST(0x1, MISCREG_GPCDMA_SECURITY_0_G1W_SHIFT)
#define MISCREG_GPCDMA_SECURITY_0_G1W_RANGE                     9:9
#define MISCREG_GPCDMA_SECURITY_0_G1W_WOFFSET                   0x0
#define MISCREG_GPCDMA_SECURITY_0_G1W_DEFAULT                   _MK_MASK_CONST(0x1)
#define MISCREG_GPCDMA_SECURITY_0_G1W_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define MISCREG_GPCDMA_SECURITY_0_G1W_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define MISCREG_GPCDMA_SECURITY_0_G1W_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define MISCREG_GPCDMA_SECURITY_0_G1W_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define MISCREG_GPCDMA_SECURITY_0_G1W_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)

#define MISCREG_GPCDMA_SECURITY_0_G0W_SHIFT                     _MK_SHIFT_CONST(8)
#define MISCREG_GPCDMA_SECURITY_0_G0W_FIELD                     _MK_FIELD_CONST(0x1, MISCREG_GPCDMA_SECURITY_0_G0W_SHIFT)
#define MISCREG_GPCDMA_SECURITY_0_G0W_RANGE                     8:8
#define MISCREG_GPCDMA_SECURITY_0_G0W_WOFFSET                   0x0
#define MISCREG_GPCDMA_SECURITY_0_G0W_DEFAULT                   _MK_MASK_CONST(0x1)
#define MISCREG_GPCDMA_SECURITY_0_G0W_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define MISCREG_GPCDMA_SECURITY_0_G0W_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define MISCREG_GPCDMA_SECURITY_0_G0W_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define MISCREG_GPCDMA_SECURITY_0_G0W_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define MISCREG_GPCDMA_SECURITY_0_G0W_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)

#define MISCREG_GPCDMA_SECURITY_0_G7R_SHIFT                     _MK_SHIFT_CONST(7)
#define MISCREG_GPCDMA_SECURITY_0_G7R_FIELD                     _MK_FIELD_CONST(0x1, MISCREG_GPCDMA_SECURITY_0_G7R_SHIFT)
#define MISCREG_GPCDMA_SECURITY_0_G7R_RANGE                     7:7
#define MISCREG_GPCDMA_SECURITY_0_G7R_WOFFSET                   0x0
#define MISCREG_GPCDMA_SECURITY_0_G7R_DEFAULT                   _MK_MASK_CONST(0x1)
#define MISCREG_GPCDMA_SECURITY_0_G7R_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define MISCREG_GPCDMA_SECURITY_0_G7R_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define MISCREG_GPCDMA_SECURITY_0_G7R_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define MISCREG_GPCDMA_SECURITY_0_G7R_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define MISCREG_GPCDMA_SECURITY_0_G7R_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)

#define MISCREG_GPCDMA_SECURITY_0_G6R_SHIFT                     _MK_SHIFT_CONST(6)
#define MISCREG_GPCDMA_SECURITY_0_G6R_FIELD                     _MK_FIELD_CONST(0x1, MISCREG_GPCDMA_SECURITY_0_G6R_SHIFT)
#define MISCREG_GPCDMA_SECURITY_0_G6R_RANGE                     6:6
#define MISCREG_GPCDMA_SECURITY_0_G6R_WOFFSET                   0x0
#define MISCREG_GPCDMA_SECURITY_0_G6R_DEFAULT                   _MK_MASK_CONST(0x1)
#define MISCREG_GPCDMA_SECURITY_0_G6R_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define MISCREG_GPCDMA_SECURITY_0_G6R_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define MISCREG_GPCDMA_SECURITY_0_G6R_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define MISCREG_GPCDMA_SECURITY_0_G6R_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define MISCREG_GPCDMA_SECURITY_0_G6R_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)

#define MISCREG_GPCDMA_SECURITY_0_G5R_SHIFT                     _MK_SHIFT_CONST(5)
#define MISCREG_GPCDMA_SECURITY_0_G5R_FIELD                     _MK_FIELD_CONST(0x1, MISCREG_GPCDMA_SECURITY_0_G5R_SHIFT)
#define MISCREG_GPCDMA_SECURITY_0_G5R_RANGE                     5:5
#define MISCREG_GPCDMA_SECURITY_0_G5R_WOFFSET                   0x0
#define MISCREG_GPCDMA_SECURITY_0_G5R_DEFAULT                   _MK_MASK_CONST(0x1)
#define MISCREG_GPCDMA_SECURITY_0_G5R_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define MISCREG_GPCDMA_SECURITY_0_G5R_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define MISCREG_GPCDMA_SECURITY_0_G5R_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define MISCREG_GPCDMA_SECURITY_0_G5R_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define MISCREG_GPCDMA_SECURITY_0_G5R_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)

#define MISCREG_GPCDMA_SECURITY_0_G4R_SHIFT                     _MK_SHIFT_CONST(4)
#define MISCREG_GPCDMA_SECURITY_0_G4R_FIELD                     _MK_FIELD_CONST(0x1, MISCREG_GPCDMA_SECURITY_0_G4R_SHIFT)
#define MISCREG_GPCDMA_SECURITY_0_G4R_RANGE                     4:4
#define MISCREG_GPCDMA_SECURITY_0_G4R_WOFFSET                   0x0
#define MISCREG_GPCDMA_SECURITY_0_G4R_DEFAULT                   _MK_MASK_CONST(0x1)
#define MISCREG_GPCDMA_SECURITY_0_G4R_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define MISCREG_GPCDMA_SECURITY_0_G4R_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define MISCREG_GPCDMA_SECURITY_0_G4R_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define MISCREG_GPCDMA_SECURITY_0_G4R_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define MISCREG_GPCDMA_SECURITY_0_G4R_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)

#define MISCREG_GPCDMA_SECURITY_0_G3R_SHIFT                     _MK_SHIFT_CONST(3)
#define MISCREG_GPCDMA_SECURITY_0_G3R_FIELD                     _MK_FIELD_CONST(0x1, MISCREG_GPCDMA_SECURITY_0_G3R_SHIFT)
#define MISCREG_GPCDMA_SECURITY_0_G3R_RANGE                     3:3
#define MISCREG_GPCDMA_SECURITY_0_G3R_WOFFSET                   0x0
#define MISCREG_GPCDMA_SECURITY_0_G3R_DEFAULT                   _MK_MASK_CONST(0x1)
#define MISCREG_GPCDMA_SECURITY_0_G3R_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define MISCREG_GPCDMA_SECURITY_0_G3R_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define MISCREG_GPCDMA_SECURITY_0_G3R_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define MISCREG_GPCDMA_SECURITY_0_G3R_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define MISCREG_GPCDMA_SECURITY_0_G3R_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)

#define MISCREG_GPCDMA_SECURITY_0_G2R_SHIFT                     _MK_SHIFT_CONST(2)
#define MISCREG_GPCDMA_SECURITY_0_G2R_FIELD                     _MK_FIELD_CONST(0x1, MISCREG_GPCDMA_SECURITY_0_G2R_SHIFT)
#define MISCREG_GPCDMA_SECURITY_0_G2R_RANGE                     2:2
#define MISCREG_GPCDMA_SECURITY_0_G2R_WOFFSET                   0x0
#define MISCREG_GPCDMA_SECURITY_0_G2R_DEFAULT                   _MK_MASK_CONST(0x1)
#define MISCREG_GPCDMA_SECURITY_0_G2R_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define MISCREG_GPCDMA_SECURITY_0_G2R_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define MISCREG_GPCDMA_SECURITY_0_G2R_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define MISCREG_GPCDMA_SECURITY_0_G2R_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define MISCREG_GPCDMA_SECURITY_0_G2R_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)

#define MISCREG_GPCDMA_SECURITY_0_G1R_SHIFT                     _MK_SHIFT_CONST(1)
#define MISCREG_GPCDMA_SECURITY_0_G1R_FIELD                     _MK_FIELD_CONST(0x1, MISCREG_GPCDMA_SECURITY_0_G1R_SHIFT)
#define MISCREG_GPCDMA_SECURITY_0_G1R_RANGE                     1:1
#define MISCREG_GPCDMA_SECURITY_0_G1R_WOFFSET                   0x0
#define MISCREG_GPCDMA_SECURITY_0_G1R_DEFAULT                   _MK_MASK_CONST(0x1)
#define MISCREG_GPCDMA_SECURITY_0_G1R_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define MISCREG_GPCDMA_SECURITY_0_G1R_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define MISCREG_GPCDMA_SECURITY_0_G1R_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define MISCREG_GPCDMA_SECURITY_0_G1R_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define MISCREG_GPCDMA_SECURITY_0_G1R_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)

#define MISCREG_GPCDMA_SECURITY_0_G0R_SHIFT                     _MK_SHIFT_CONST(0)
#define MISCREG_GPCDMA_SECURITY_0_G0R_FIELD                     _MK_FIELD_CONST(0x1, MISCREG_GPCDMA_SECURITY_0_G0R_SHIFT)
#define MISCREG_GPCDMA_SECURITY_0_G0R_RANGE                     0:0
#define MISCREG_GPCDMA_SECURITY_0_G0R_WOFFSET                   0x0
#define MISCREG_GPCDMA_SECURITY_0_G0R_DEFAULT                   _MK_MASK_CONST(0x1)
#define MISCREG_GPCDMA_SECURITY_0_G0R_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define MISCREG_GPCDMA_SECURITY_0_G0R_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define MISCREG_GPCDMA_SECURITY_0_G0R_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define MISCREG_GPCDMA_SECURITY_0_G0R_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define MISCREG_GPCDMA_SECURITY_0_G0R_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)


// Register MISCREG_SCE_SECURITY_0
#define MISCREG_SCE_SECURITY_0                  _MK_ADDR_CONST(0x1014)
#define MISCREG_SCE_SECURITY_0_SECURE                   0x0
#define MISCREG_SCE_SECURITY_0_DUAL                     0x0
#define MISCREG_SCE_SECURITY_0_SCR                      SCRSCE_0
#define MISCREG_SCE_SECURITY_0_WORD_COUNT                       0x1
#define MISCREG_SCE_SECURITY_0_RESET_VAL                        _MK_MASK_CONST(0x5ffff)
#define MISCREG_SCE_SECURITY_0_RESET_MASK                       _MK_MASK_CONST(0xfffff)
#define MISCREG_SCE_SECURITY_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define MISCREG_SCE_SECURITY_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define MISCREG_SCE_SECURITY_0_READ_MASK                        _MK_MASK_CONST(0xfffff)
#define MISCREG_SCE_SECURITY_0_WRITE_MASK                       _MK_MASK_CONST(0xffff)
#define MISCREG_SCE_SECURITY_0_MSTR_ID_SHIFT                    _MK_SHIFT_CONST(16)
#define MISCREG_SCE_SECURITY_0_MSTR_ID_FIELD                    _MK_FIELD_CONST(0xf, MISCREG_SCE_SECURITY_0_MSTR_ID_SHIFT)
#define MISCREG_SCE_SECURITY_0_MSTR_ID_RANGE                    19:16
#define MISCREG_SCE_SECURITY_0_MSTR_ID_WOFFSET                  0x0
#define MISCREG_SCE_SECURITY_0_MSTR_ID_DEFAULT                  _MK_MASK_CONST(0x5)
#define MISCREG_SCE_SECURITY_0_MSTR_ID_DEFAULT_MASK                     _MK_MASK_CONST(0xf)
#define MISCREG_SCE_SECURITY_0_MSTR_ID_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define MISCREG_SCE_SECURITY_0_MSTR_ID_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define MISCREG_SCE_SECURITY_0_MSTR_ID_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define MISCREG_SCE_SECURITY_0_MSTR_ID_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)
#define MISCREG_SCE_SECURITY_0_MSTR_ID_CCPLEX                   _MK_ENUM_CONST(1)
#define MISCREG_SCE_SECURITY_0_MSTR_ID_CCPLEX_DPMU                      _MK_ENUM_CONST(2)
#define MISCREG_SCE_SECURITY_0_MSTR_ID_BPMP                     _MK_ENUM_CONST(3)
#define MISCREG_SCE_SECURITY_0_MSTR_ID_SPE                      _MK_ENUM_CONST(4)
#define MISCREG_SCE_SECURITY_0_MSTR_ID_SCE                      _MK_ENUM_CONST(5)
#define MISCREG_SCE_SECURITY_0_MSTR_ID_DMA_PER                  _MK_ENUM_CONST(6)
#define MISCREG_SCE_SECURITY_0_MSTR_ID_TSECA                    _MK_ENUM_CONST(7)
#define MISCREG_SCE_SECURITY_0_MSTR_ID_TSECB                    _MK_ENUM_CONST(8)
#define MISCREG_SCE_SECURITY_0_MSTR_ID_JTAGM                    _MK_ENUM_CONST(9)
#define MISCREG_SCE_SECURITY_0_MSTR_ID_CSITE                    _MK_ENUM_CONST(10)
#define MISCREG_SCE_SECURITY_0_MSTR_ID_APE                      _MK_ENUM_CONST(11)
#define MISCREG_SCE_SECURITY_0_MSTR_ID_Peatrans                 _MK_ENUM_CONST(12)
#define MISCREG_SCE_SECURITY_0_MSTR_ID_NVDEC                    _MK_ENUM_CONST(13)
#define MISCREG_SCE_SECURITY_0_MSTR_ID_RCE                      _MK_ENUM_CONST(14)
#define MISCREG_SCE_SECURITY_0_MSTR_ID_NVDEC1                   _MK_ENUM_CONST(15)

#define MISCREG_SCE_SECURITY_0_G7W_SHIFT                        _MK_SHIFT_CONST(15)
#define MISCREG_SCE_SECURITY_0_G7W_FIELD                        _MK_FIELD_CONST(0x1, MISCREG_SCE_SECURITY_0_G7W_SHIFT)
#define MISCREG_SCE_SECURITY_0_G7W_RANGE                        15:15
#define MISCREG_SCE_SECURITY_0_G7W_WOFFSET                      0x0
#define MISCREG_SCE_SECURITY_0_G7W_DEFAULT                      _MK_MASK_CONST(0x1)
#define MISCREG_SCE_SECURITY_0_G7W_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define MISCREG_SCE_SECURITY_0_G7W_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define MISCREG_SCE_SECURITY_0_G7W_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define MISCREG_SCE_SECURITY_0_G7W_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define MISCREG_SCE_SECURITY_0_G7W_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define MISCREG_SCE_SECURITY_0_G6W_SHIFT                        _MK_SHIFT_CONST(14)
#define MISCREG_SCE_SECURITY_0_G6W_FIELD                        _MK_FIELD_CONST(0x1, MISCREG_SCE_SECURITY_0_G6W_SHIFT)
#define MISCREG_SCE_SECURITY_0_G6W_RANGE                        14:14
#define MISCREG_SCE_SECURITY_0_G6W_WOFFSET                      0x0
#define MISCREG_SCE_SECURITY_0_G6W_DEFAULT                      _MK_MASK_CONST(0x1)
#define MISCREG_SCE_SECURITY_0_G6W_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define MISCREG_SCE_SECURITY_0_G6W_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define MISCREG_SCE_SECURITY_0_G6W_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define MISCREG_SCE_SECURITY_0_G6W_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define MISCREG_SCE_SECURITY_0_G6W_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define MISCREG_SCE_SECURITY_0_G5W_SHIFT                        _MK_SHIFT_CONST(13)
#define MISCREG_SCE_SECURITY_0_G5W_FIELD                        _MK_FIELD_CONST(0x1, MISCREG_SCE_SECURITY_0_G5W_SHIFT)
#define MISCREG_SCE_SECURITY_0_G5W_RANGE                        13:13
#define MISCREG_SCE_SECURITY_0_G5W_WOFFSET                      0x0
#define MISCREG_SCE_SECURITY_0_G5W_DEFAULT                      _MK_MASK_CONST(0x1)
#define MISCREG_SCE_SECURITY_0_G5W_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define MISCREG_SCE_SECURITY_0_G5W_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define MISCREG_SCE_SECURITY_0_G5W_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define MISCREG_SCE_SECURITY_0_G5W_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define MISCREG_SCE_SECURITY_0_G5W_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define MISCREG_SCE_SECURITY_0_G4W_SHIFT                        _MK_SHIFT_CONST(12)
#define MISCREG_SCE_SECURITY_0_G4W_FIELD                        _MK_FIELD_CONST(0x1, MISCREG_SCE_SECURITY_0_G4W_SHIFT)
#define MISCREG_SCE_SECURITY_0_G4W_RANGE                        12:12
#define MISCREG_SCE_SECURITY_0_G4W_WOFFSET                      0x0
#define MISCREG_SCE_SECURITY_0_G4W_DEFAULT                      _MK_MASK_CONST(0x1)
#define MISCREG_SCE_SECURITY_0_G4W_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define MISCREG_SCE_SECURITY_0_G4W_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define MISCREG_SCE_SECURITY_0_G4W_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define MISCREG_SCE_SECURITY_0_G4W_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define MISCREG_SCE_SECURITY_0_G4W_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define MISCREG_SCE_SECURITY_0_G3W_SHIFT                        _MK_SHIFT_CONST(11)
#define MISCREG_SCE_SECURITY_0_G3W_FIELD                        _MK_FIELD_CONST(0x1, MISCREG_SCE_SECURITY_0_G3W_SHIFT)
#define MISCREG_SCE_SECURITY_0_G3W_RANGE                        11:11
#define MISCREG_SCE_SECURITY_0_G3W_WOFFSET                      0x0
#define MISCREG_SCE_SECURITY_0_G3W_DEFAULT                      _MK_MASK_CONST(0x1)
#define MISCREG_SCE_SECURITY_0_G3W_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define MISCREG_SCE_SECURITY_0_G3W_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define MISCREG_SCE_SECURITY_0_G3W_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define MISCREG_SCE_SECURITY_0_G3W_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define MISCREG_SCE_SECURITY_0_G3W_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define MISCREG_SCE_SECURITY_0_G2W_SHIFT                        _MK_SHIFT_CONST(10)
#define MISCREG_SCE_SECURITY_0_G2W_FIELD                        _MK_FIELD_CONST(0x1, MISCREG_SCE_SECURITY_0_G2W_SHIFT)
#define MISCREG_SCE_SECURITY_0_G2W_RANGE                        10:10
#define MISCREG_SCE_SECURITY_0_G2W_WOFFSET                      0x0
#define MISCREG_SCE_SECURITY_0_G2W_DEFAULT                      _MK_MASK_CONST(0x1)
#define MISCREG_SCE_SECURITY_0_G2W_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define MISCREG_SCE_SECURITY_0_G2W_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define MISCREG_SCE_SECURITY_0_G2W_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define MISCREG_SCE_SECURITY_0_G2W_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define MISCREG_SCE_SECURITY_0_G2W_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define MISCREG_SCE_SECURITY_0_G1W_SHIFT                        _MK_SHIFT_CONST(9)
#define MISCREG_SCE_SECURITY_0_G1W_FIELD                        _MK_FIELD_CONST(0x1, MISCREG_SCE_SECURITY_0_G1W_SHIFT)
#define MISCREG_SCE_SECURITY_0_G1W_RANGE                        9:9
#define MISCREG_SCE_SECURITY_0_G1W_WOFFSET                      0x0
#define MISCREG_SCE_SECURITY_0_G1W_DEFAULT                      _MK_MASK_CONST(0x1)
#define MISCREG_SCE_SECURITY_0_G1W_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define MISCREG_SCE_SECURITY_0_G1W_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define MISCREG_SCE_SECURITY_0_G1W_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define MISCREG_SCE_SECURITY_0_G1W_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define MISCREG_SCE_SECURITY_0_G1W_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define MISCREG_SCE_SECURITY_0_G0W_SHIFT                        _MK_SHIFT_CONST(8)
#define MISCREG_SCE_SECURITY_0_G0W_FIELD                        _MK_FIELD_CONST(0x1, MISCREG_SCE_SECURITY_0_G0W_SHIFT)
#define MISCREG_SCE_SECURITY_0_G0W_RANGE                        8:8
#define MISCREG_SCE_SECURITY_0_G0W_WOFFSET                      0x0
#define MISCREG_SCE_SECURITY_0_G0W_DEFAULT                      _MK_MASK_CONST(0x1)
#define MISCREG_SCE_SECURITY_0_G0W_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define MISCREG_SCE_SECURITY_0_G0W_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define MISCREG_SCE_SECURITY_0_G0W_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define MISCREG_SCE_SECURITY_0_G0W_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define MISCREG_SCE_SECURITY_0_G0W_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define MISCREG_SCE_SECURITY_0_G7R_SHIFT                        _MK_SHIFT_CONST(7)
#define MISCREG_SCE_SECURITY_0_G7R_FIELD                        _MK_FIELD_CONST(0x1, MISCREG_SCE_SECURITY_0_G7R_SHIFT)
#define MISCREG_SCE_SECURITY_0_G7R_RANGE                        7:7
#define MISCREG_SCE_SECURITY_0_G7R_WOFFSET                      0x0
#define MISCREG_SCE_SECURITY_0_G7R_DEFAULT                      _MK_MASK_CONST(0x1)
#define MISCREG_SCE_SECURITY_0_G7R_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define MISCREG_SCE_SECURITY_0_G7R_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define MISCREG_SCE_SECURITY_0_G7R_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define MISCREG_SCE_SECURITY_0_G7R_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define MISCREG_SCE_SECURITY_0_G7R_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define MISCREG_SCE_SECURITY_0_G6R_SHIFT                        _MK_SHIFT_CONST(6)
#define MISCREG_SCE_SECURITY_0_G6R_FIELD                        _MK_FIELD_CONST(0x1, MISCREG_SCE_SECURITY_0_G6R_SHIFT)
#define MISCREG_SCE_SECURITY_0_G6R_RANGE                        6:6
#define MISCREG_SCE_SECURITY_0_G6R_WOFFSET                      0x0
#define MISCREG_SCE_SECURITY_0_G6R_DEFAULT                      _MK_MASK_CONST(0x1)
#define MISCREG_SCE_SECURITY_0_G6R_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define MISCREG_SCE_SECURITY_0_G6R_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define MISCREG_SCE_SECURITY_0_G6R_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define MISCREG_SCE_SECURITY_0_G6R_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define MISCREG_SCE_SECURITY_0_G6R_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define MISCREG_SCE_SECURITY_0_G5R_SHIFT                        _MK_SHIFT_CONST(5)
#define MISCREG_SCE_SECURITY_0_G5R_FIELD                        _MK_FIELD_CONST(0x1, MISCREG_SCE_SECURITY_0_G5R_SHIFT)
#define MISCREG_SCE_SECURITY_0_G5R_RANGE                        5:5
#define MISCREG_SCE_SECURITY_0_G5R_WOFFSET                      0x0
#define MISCREG_SCE_SECURITY_0_G5R_DEFAULT                      _MK_MASK_CONST(0x1)
#define MISCREG_SCE_SECURITY_0_G5R_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define MISCREG_SCE_SECURITY_0_G5R_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define MISCREG_SCE_SECURITY_0_G5R_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define MISCREG_SCE_SECURITY_0_G5R_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define MISCREG_SCE_SECURITY_0_G5R_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define MISCREG_SCE_SECURITY_0_G4R_SHIFT                        _MK_SHIFT_CONST(4)
#define MISCREG_SCE_SECURITY_0_G4R_FIELD                        _MK_FIELD_CONST(0x1, MISCREG_SCE_SECURITY_0_G4R_SHIFT)
#define MISCREG_SCE_SECURITY_0_G4R_RANGE                        4:4
#define MISCREG_SCE_SECURITY_0_G4R_WOFFSET                      0x0
#define MISCREG_SCE_SECURITY_0_G4R_DEFAULT                      _MK_MASK_CONST(0x1)
#define MISCREG_SCE_SECURITY_0_G4R_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define MISCREG_SCE_SECURITY_0_G4R_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define MISCREG_SCE_SECURITY_0_G4R_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define MISCREG_SCE_SECURITY_0_G4R_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define MISCREG_SCE_SECURITY_0_G4R_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define MISCREG_SCE_SECURITY_0_G3R_SHIFT                        _MK_SHIFT_CONST(3)
#define MISCREG_SCE_SECURITY_0_G3R_FIELD                        _MK_FIELD_CONST(0x1, MISCREG_SCE_SECURITY_0_G3R_SHIFT)
#define MISCREG_SCE_SECURITY_0_G3R_RANGE                        3:3
#define MISCREG_SCE_SECURITY_0_G3R_WOFFSET                      0x0
#define MISCREG_SCE_SECURITY_0_G3R_DEFAULT                      _MK_MASK_CONST(0x1)
#define MISCREG_SCE_SECURITY_0_G3R_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define MISCREG_SCE_SECURITY_0_G3R_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define MISCREG_SCE_SECURITY_0_G3R_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define MISCREG_SCE_SECURITY_0_G3R_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define MISCREG_SCE_SECURITY_0_G3R_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define MISCREG_SCE_SECURITY_0_G2R_SHIFT                        _MK_SHIFT_CONST(2)
#define MISCREG_SCE_SECURITY_0_G2R_FIELD                        _MK_FIELD_CONST(0x1, MISCREG_SCE_SECURITY_0_G2R_SHIFT)
#define MISCREG_SCE_SECURITY_0_G2R_RANGE                        2:2
#define MISCREG_SCE_SECURITY_0_G2R_WOFFSET                      0x0
#define MISCREG_SCE_SECURITY_0_G2R_DEFAULT                      _MK_MASK_CONST(0x1)
#define MISCREG_SCE_SECURITY_0_G2R_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define MISCREG_SCE_SECURITY_0_G2R_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define MISCREG_SCE_SECURITY_0_G2R_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define MISCREG_SCE_SECURITY_0_G2R_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define MISCREG_SCE_SECURITY_0_G2R_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define MISCREG_SCE_SECURITY_0_G1R_SHIFT                        _MK_SHIFT_CONST(1)
#define MISCREG_SCE_SECURITY_0_G1R_FIELD                        _MK_FIELD_CONST(0x1, MISCREG_SCE_SECURITY_0_G1R_SHIFT)
#define MISCREG_SCE_SECURITY_0_G1R_RANGE                        1:1
#define MISCREG_SCE_SECURITY_0_G1R_WOFFSET                      0x0
#define MISCREG_SCE_SECURITY_0_G1R_DEFAULT                      _MK_MASK_CONST(0x1)
#define MISCREG_SCE_SECURITY_0_G1R_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define MISCREG_SCE_SECURITY_0_G1R_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define MISCREG_SCE_SECURITY_0_G1R_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define MISCREG_SCE_SECURITY_0_G1R_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define MISCREG_SCE_SECURITY_0_G1R_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define MISCREG_SCE_SECURITY_0_G0R_SHIFT                        _MK_SHIFT_CONST(0)
#define MISCREG_SCE_SECURITY_0_G0R_FIELD                        _MK_FIELD_CONST(0x1, MISCREG_SCE_SECURITY_0_G0R_SHIFT)
#define MISCREG_SCE_SECURITY_0_G0R_RANGE                        0:0
#define MISCREG_SCE_SECURITY_0_G0R_WOFFSET                      0x0
#define MISCREG_SCE_SECURITY_0_G0R_DEFAULT                      _MK_MASK_CONST(0x1)
#define MISCREG_SCE_SECURITY_0_G0R_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define MISCREG_SCE_SECURITY_0_G0R_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define MISCREG_SCE_SECURITY_0_G0R_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define MISCREG_SCE_SECURITY_0_G0R_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define MISCREG_SCE_SECURITY_0_G0R_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)


// Register MISCREG_SPE_SECURITY_0
#define MISCREG_SPE_SECURITY_0                  _MK_ADDR_CONST(0x1018)
#define MISCREG_SPE_SECURITY_0_SECURE                   0x0
#define MISCREG_SPE_SECURITY_0_DUAL                     0x0
#define MISCREG_SPE_SECURITY_0_SCR                      SCRSPE_0
#define MISCREG_SPE_SECURITY_0_WORD_COUNT                       0x1
#define MISCREG_SPE_SECURITY_0_RESET_VAL                        _MK_MASK_CONST(0x4ffff)
#define MISCREG_SPE_SECURITY_0_RESET_MASK                       _MK_MASK_CONST(0xfffff)
#define MISCREG_SPE_SECURITY_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define MISCREG_SPE_SECURITY_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define MISCREG_SPE_SECURITY_0_READ_MASK                        _MK_MASK_CONST(0xfffff)
#define MISCREG_SPE_SECURITY_0_WRITE_MASK                       _MK_MASK_CONST(0xffff)
#define MISCREG_SPE_SECURITY_0_MSTR_ID_SHIFT                    _MK_SHIFT_CONST(16)
#define MISCREG_SPE_SECURITY_0_MSTR_ID_FIELD                    _MK_FIELD_CONST(0xf, MISCREG_SPE_SECURITY_0_MSTR_ID_SHIFT)
#define MISCREG_SPE_SECURITY_0_MSTR_ID_RANGE                    19:16
#define MISCREG_SPE_SECURITY_0_MSTR_ID_WOFFSET                  0x0
#define MISCREG_SPE_SECURITY_0_MSTR_ID_DEFAULT                  _MK_MASK_CONST(0x4)
#define MISCREG_SPE_SECURITY_0_MSTR_ID_DEFAULT_MASK                     _MK_MASK_CONST(0xf)
#define MISCREG_SPE_SECURITY_0_MSTR_ID_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define MISCREG_SPE_SECURITY_0_MSTR_ID_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define MISCREG_SPE_SECURITY_0_MSTR_ID_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define MISCREG_SPE_SECURITY_0_MSTR_ID_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)
#define MISCREG_SPE_SECURITY_0_MSTR_ID_CCPLEX                   _MK_ENUM_CONST(1)
#define MISCREG_SPE_SECURITY_0_MSTR_ID_CCPLEX_DPMU                      _MK_ENUM_CONST(2)
#define MISCREG_SPE_SECURITY_0_MSTR_ID_BPMP                     _MK_ENUM_CONST(3)
#define MISCREG_SPE_SECURITY_0_MSTR_ID_SPE                      _MK_ENUM_CONST(4)
#define MISCREG_SPE_SECURITY_0_MSTR_ID_SCE                      _MK_ENUM_CONST(5)
#define MISCREG_SPE_SECURITY_0_MSTR_ID_DMA_PER                  _MK_ENUM_CONST(6)
#define MISCREG_SPE_SECURITY_0_MSTR_ID_TSECA                    _MK_ENUM_CONST(7)
#define MISCREG_SPE_SECURITY_0_MSTR_ID_TSECB                    _MK_ENUM_CONST(8)
#define MISCREG_SPE_SECURITY_0_MSTR_ID_JTAGM                    _MK_ENUM_CONST(9)
#define MISCREG_SPE_SECURITY_0_MSTR_ID_CSITE                    _MK_ENUM_CONST(10)
#define MISCREG_SPE_SECURITY_0_MSTR_ID_APE                      _MK_ENUM_CONST(11)
#define MISCREG_SPE_SECURITY_0_MSTR_ID_Peatrans                 _MK_ENUM_CONST(12)
#define MISCREG_SPE_SECURITY_0_MSTR_ID_NVDEC                    _MK_ENUM_CONST(13)
#define MISCREG_SPE_SECURITY_0_MSTR_ID_RCE                      _MK_ENUM_CONST(14)
#define MISCREG_SPE_SECURITY_0_MSTR_ID_NVDEC1                   _MK_ENUM_CONST(15)

#define MISCREG_SPE_SECURITY_0_G7W_SHIFT                        _MK_SHIFT_CONST(15)
#define MISCREG_SPE_SECURITY_0_G7W_FIELD                        _MK_FIELD_CONST(0x1, MISCREG_SPE_SECURITY_0_G7W_SHIFT)
#define MISCREG_SPE_SECURITY_0_G7W_RANGE                        15:15
#define MISCREG_SPE_SECURITY_0_G7W_WOFFSET                      0x0
#define MISCREG_SPE_SECURITY_0_G7W_DEFAULT                      _MK_MASK_CONST(0x1)
#define MISCREG_SPE_SECURITY_0_G7W_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define MISCREG_SPE_SECURITY_0_G7W_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define MISCREG_SPE_SECURITY_0_G7W_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define MISCREG_SPE_SECURITY_0_G7W_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define MISCREG_SPE_SECURITY_0_G7W_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define MISCREG_SPE_SECURITY_0_G6W_SHIFT                        _MK_SHIFT_CONST(14)
#define MISCREG_SPE_SECURITY_0_G6W_FIELD                        _MK_FIELD_CONST(0x1, MISCREG_SPE_SECURITY_0_G6W_SHIFT)
#define MISCREG_SPE_SECURITY_0_G6W_RANGE                        14:14
#define MISCREG_SPE_SECURITY_0_G6W_WOFFSET                      0x0
#define MISCREG_SPE_SECURITY_0_G6W_DEFAULT                      _MK_MASK_CONST(0x1)
#define MISCREG_SPE_SECURITY_0_G6W_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define MISCREG_SPE_SECURITY_0_G6W_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define MISCREG_SPE_SECURITY_0_G6W_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define MISCREG_SPE_SECURITY_0_G6W_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define MISCREG_SPE_SECURITY_0_G6W_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define MISCREG_SPE_SECURITY_0_G5W_SHIFT                        _MK_SHIFT_CONST(13)
#define MISCREG_SPE_SECURITY_0_G5W_FIELD                        _MK_FIELD_CONST(0x1, MISCREG_SPE_SECURITY_0_G5W_SHIFT)
#define MISCREG_SPE_SECURITY_0_G5W_RANGE                        13:13
#define MISCREG_SPE_SECURITY_0_G5W_WOFFSET                      0x0
#define MISCREG_SPE_SECURITY_0_G5W_DEFAULT                      _MK_MASK_CONST(0x1)
#define MISCREG_SPE_SECURITY_0_G5W_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define MISCREG_SPE_SECURITY_0_G5W_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define MISCREG_SPE_SECURITY_0_G5W_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define MISCREG_SPE_SECURITY_0_G5W_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define MISCREG_SPE_SECURITY_0_G5W_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define MISCREG_SPE_SECURITY_0_G4W_SHIFT                        _MK_SHIFT_CONST(12)
#define MISCREG_SPE_SECURITY_0_G4W_FIELD                        _MK_FIELD_CONST(0x1, MISCREG_SPE_SECURITY_0_G4W_SHIFT)
#define MISCREG_SPE_SECURITY_0_G4W_RANGE                        12:12
#define MISCREG_SPE_SECURITY_0_G4W_WOFFSET                      0x0
#define MISCREG_SPE_SECURITY_0_G4W_DEFAULT                      _MK_MASK_CONST(0x1)
#define MISCREG_SPE_SECURITY_0_G4W_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define MISCREG_SPE_SECURITY_0_G4W_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define MISCREG_SPE_SECURITY_0_G4W_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define MISCREG_SPE_SECURITY_0_G4W_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define MISCREG_SPE_SECURITY_0_G4W_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define MISCREG_SPE_SECURITY_0_G3W_SHIFT                        _MK_SHIFT_CONST(11)
#define MISCREG_SPE_SECURITY_0_G3W_FIELD                        _MK_FIELD_CONST(0x1, MISCREG_SPE_SECURITY_0_G3W_SHIFT)
#define MISCREG_SPE_SECURITY_0_G3W_RANGE                        11:11
#define MISCREG_SPE_SECURITY_0_G3W_WOFFSET                      0x0
#define MISCREG_SPE_SECURITY_0_G3W_DEFAULT                      _MK_MASK_CONST(0x1)
#define MISCREG_SPE_SECURITY_0_G3W_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define MISCREG_SPE_SECURITY_0_G3W_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define MISCREG_SPE_SECURITY_0_G3W_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define MISCREG_SPE_SECURITY_0_G3W_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define MISCREG_SPE_SECURITY_0_G3W_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define MISCREG_SPE_SECURITY_0_G2W_SHIFT                        _MK_SHIFT_CONST(10)
#define MISCREG_SPE_SECURITY_0_G2W_FIELD                        _MK_FIELD_CONST(0x1, MISCREG_SPE_SECURITY_0_G2W_SHIFT)
#define MISCREG_SPE_SECURITY_0_G2W_RANGE                        10:10
#define MISCREG_SPE_SECURITY_0_G2W_WOFFSET                      0x0
#define MISCREG_SPE_SECURITY_0_G2W_DEFAULT                      _MK_MASK_CONST(0x1)
#define MISCREG_SPE_SECURITY_0_G2W_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define MISCREG_SPE_SECURITY_0_G2W_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define MISCREG_SPE_SECURITY_0_G2W_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define MISCREG_SPE_SECURITY_0_G2W_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define MISCREG_SPE_SECURITY_0_G2W_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define MISCREG_SPE_SECURITY_0_G1W_SHIFT                        _MK_SHIFT_CONST(9)
#define MISCREG_SPE_SECURITY_0_G1W_FIELD                        _MK_FIELD_CONST(0x1, MISCREG_SPE_SECURITY_0_G1W_SHIFT)
#define MISCREG_SPE_SECURITY_0_G1W_RANGE                        9:9
#define MISCREG_SPE_SECURITY_0_G1W_WOFFSET                      0x0
#define MISCREG_SPE_SECURITY_0_G1W_DEFAULT                      _MK_MASK_CONST(0x1)
#define MISCREG_SPE_SECURITY_0_G1W_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define MISCREG_SPE_SECURITY_0_G1W_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define MISCREG_SPE_SECURITY_0_G1W_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define MISCREG_SPE_SECURITY_0_G1W_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define MISCREG_SPE_SECURITY_0_G1W_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define MISCREG_SPE_SECURITY_0_G0W_SHIFT                        _MK_SHIFT_CONST(8)
#define MISCREG_SPE_SECURITY_0_G0W_FIELD                        _MK_FIELD_CONST(0x1, MISCREG_SPE_SECURITY_0_G0W_SHIFT)
#define MISCREG_SPE_SECURITY_0_G0W_RANGE                        8:8
#define MISCREG_SPE_SECURITY_0_G0W_WOFFSET                      0x0
#define MISCREG_SPE_SECURITY_0_G0W_DEFAULT                      _MK_MASK_CONST(0x1)
#define MISCREG_SPE_SECURITY_0_G0W_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define MISCREG_SPE_SECURITY_0_G0W_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define MISCREG_SPE_SECURITY_0_G0W_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define MISCREG_SPE_SECURITY_0_G0W_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define MISCREG_SPE_SECURITY_0_G0W_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define MISCREG_SPE_SECURITY_0_G7R_SHIFT                        _MK_SHIFT_CONST(7)
#define MISCREG_SPE_SECURITY_0_G7R_FIELD                        _MK_FIELD_CONST(0x1, MISCREG_SPE_SECURITY_0_G7R_SHIFT)
#define MISCREG_SPE_SECURITY_0_G7R_RANGE                        7:7
#define MISCREG_SPE_SECURITY_0_G7R_WOFFSET                      0x0
#define MISCREG_SPE_SECURITY_0_G7R_DEFAULT                      _MK_MASK_CONST(0x1)
#define MISCREG_SPE_SECURITY_0_G7R_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define MISCREG_SPE_SECURITY_0_G7R_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define MISCREG_SPE_SECURITY_0_G7R_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define MISCREG_SPE_SECURITY_0_G7R_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define MISCREG_SPE_SECURITY_0_G7R_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define MISCREG_SPE_SECURITY_0_G6R_SHIFT                        _MK_SHIFT_CONST(6)
#define MISCREG_SPE_SECURITY_0_G6R_FIELD                        _MK_FIELD_CONST(0x1, MISCREG_SPE_SECURITY_0_G6R_SHIFT)
#define MISCREG_SPE_SECURITY_0_G6R_RANGE                        6:6
#define MISCREG_SPE_SECURITY_0_G6R_WOFFSET                      0x0
#define MISCREG_SPE_SECURITY_0_G6R_DEFAULT                      _MK_MASK_CONST(0x1)
#define MISCREG_SPE_SECURITY_0_G6R_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define MISCREG_SPE_SECURITY_0_G6R_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define MISCREG_SPE_SECURITY_0_G6R_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define MISCREG_SPE_SECURITY_0_G6R_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define MISCREG_SPE_SECURITY_0_G6R_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define MISCREG_SPE_SECURITY_0_G5R_SHIFT                        _MK_SHIFT_CONST(5)
#define MISCREG_SPE_SECURITY_0_G5R_FIELD                        _MK_FIELD_CONST(0x1, MISCREG_SPE_SECURITY_0_G5R_SHIFT)
#define MISCREG_SPE_SECURITY_0_G5R_RANGE                        5:5
#define MISCREG_SPE_SECURITY_0_G5R_WOFFSET                      0x0
#define MISCREG_SPE_SECURITY_0_G5R_DEFAULT                      _MK_MASK_CONST(0x1)
#define MISCREG_SPE_SECURITY_0_G5R_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define MISCREG_SPE_SECURITY_0_G5R_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define MISCREG_SPE_SECURITY_0_G5R_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define MISCREG_SPE_SECURITY_0_G5R_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define MISCREG_SPE_SECURITY_0_G5R_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define MISCREG_SPE_SECURITY_0_G4R_SHIFT                        _MK_SHIFT_CONST(4)
#define MISCREG_SPE_SECURITY_0_G4R_FIELD                        _MK_FIELD_CONST(0x1, MISCREG_SPE_SECURITY_0_G4R_SHIFT)
#define MISCREG_SPE_SECURITY_0_G4R_RANGE                        4:4
#define MISCREG_SPE_SECURITY_0_G4R_WOFFSET                      0x0
#define MISCREG_SPE_SECURITY_0_G4R_DEFAULT                      _MK_MASK_CONST(0x1)
#define MISCREG_SPE_SECURITY_0_G4R_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define MISCREG_SPE_SECURITY_0_G4R_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define MISCREG_SPE_SECURITY_0_G4R_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define MISCREG_SPE_SECURITY_0_G4R_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define MISCREG_SPE_SECURITY_0_G4R_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define MISCREG_SPE_SECURITY_0_G3R_SHIFT                        _MK_SHIFT_CONST(3)
#define MISCREG_SPE_SECURITY_0_G3R_FIELD                        _MK_FIELD_CONST(0x1, MISCREG_SPE_SECURITY_0_G3R_SHIFT)
#define MISCREG_SPE_SECURITY_0_G3R_RANGE                        3:3
#define MISCREG_SPE_SECURITY_0_G3R_WOFFSET                      0x0
#define MISCREG_SPE_SECURITY_0_G3R_DEFAULT                      _MK_MASK_CONST(0x1)
#define MISCREG_SPE_SECURITY_0_G3R_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define MISCREG_SPE_SECURITY_0_G3R_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define MISCREG_SPE_SECURITY_0_G3R_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define MISCREG_SPE_SECURITY_0_G3R_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define MISCREG_SPE_SECURITY_0_G3R_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define MISCREG_SPE_SECURITY_0_G2R_SHIFT                        _MK_SHIFT_CONST(2)
#define MISCREG_SPE_SECURITY_0_G2R_FIELD                        _MK_FIELD_CONST(0x1, MISCREG_SPE_SECURITY_0_G2R_SHIFT)
#define MISCREG_SPE_SECURITY_0_G2R_RANGE                        2:2
#define MISCREG_SPE_SECURITY_0_G2R_WOFFSET                      0x0
#define MISCREG_SPE_SECURITY_0_G2R_DEFAULT                      _MK_MASK_CONST(0x1)
#define MISCREG_SPE_SECURITY_0_G2R_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define MISCREG_SPE_SECURITY_0_G2R_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define MISCREG_SPE_SECURITY_0_G2R_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define MISCREG_SPE_SECURITY_0_G2R_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define MISCREG_SPE_SECURITY_0_G2R_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define MISCREG_SPE_SECURITY_0_G1R_SHIFT                        _MK_SHIFT_CONST(1)
#define MISCREG_SPE_SECURITY_0_G1R_FIELD                        _MK_FIELD_CONST(0x1, MISCREG_SPE_SECURITY_0_G1R_SHIFT)
#define MISCREG_SPE_SECURITY_0_G1R_RANGE                        1:1
#define MISCREG_SPE_SECURITY_0_G1R_WOFFSET                      0x0
#define MISCREG_SPE_SECURITY_0_G1R_DEFAULT                      _MK_MASK_CONST(0x1)
#define MISCREG_SPE_SECURITY_0_G1R_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define MISCREG_SPE_SECURITY_0_G1R_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define MISCREG_SPE_SECURITY_0_G1R_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define MISCREG_SPE_SECURITY_0_G1R_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define MISCREG_SPE_SECURITY_0_G1R_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define MISCREG_SPE_SECURITY_0_G0R_SHIFT                        _MK_SHIFT_CONST(0)
#define MISCREG_SPE_SECURITY_0_G0R_FIELD                        _MK_FIELD_CONST(0x1, MISCREG_SPE_SECURITY_0_G0R_SHIFT)
#define MISCREG_SPE_SECURITY_0_G0R_RANGE                        0:0
#define MISCREG_SPE_SECURITY_0_G0R_WOFFSET                      0x0
#define MISCREG_SPE_SECURITY_0_G0R_DEFAULT                      _MK_MASK_CONST(0x1)
#define MISCREG_SPE_SECURITY_0_G0R_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define MISCREG_SPE_SECURITY_0_G0R_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define MISCREG_SPE_SECURITY_0_G0R_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define MISCREG_SPE_SECURITY_0_G0R_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define MISCREG_SPE_SECURITY_0_G0R_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)


// Register MISCREG_TSECA_HS_SECURITY_0
#define MISCREG_TSECA_HS_SECURITY_0                     _MK_ADDR_CONST(0x101c)
#define MISCREG_TSECA_HS_SECURITY_0_SECURE                      0x0
#define MISCREG_TSECA_HS_SECURITY_0_DUAL                        0x0
#define MISCREG_TSECA_HS_SECURITY_0_SCR                         SCRTSEC_0
#define MISCREG_TSECA_HS_SECURITY_0_WORD_COUNT                  0x1
#define MISCREG_TSECA_HS_SECURITY_0_RESET_VAL                   _MK_MASK_CONST(0x7ffff)
#define MISCREG_TSECA_HS_SECURITY_0_RESET_MASK                  _MK_MASK_CONST(0xfffff)
#define MISCREG_TSECA_HS_SECURITY_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define MISCREG_TSECA_HS_SECURITY_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define MISCREG_TSECA_HS_SECURITY_0_READ_MASK                   _MK_MASK_CONST(0xfffff)
#define MISCREG_TSECA_HS_SECURITY_0_WRITE_MASK                  _MK_MASK_CONST(0xffff)
#define MISCREG_TSECA_HS_SECURITY_0_MSTR_ID_SHIFT                       _MK_SHIFT_CONST(16)
#define MISCREG_TSECA_HS_SECURITY_0_MSTR_ID_FIELD                       _MK_FIELD_CONST(0xf, MISCREG_TSECA_HS_SECURITY_0_MSTR_ID_SHIFT)
#define MISCREG_TSECA_HS_SECURITY_0_MSTR_ID_RANGE                       19:16
#define MISCREG_TSECA_HS_SECURITY_0_MSTR_ID_WOFFSET                     0x0
#define MISCREG_TSECA_HS_SECURITY_0_MSTR_ID_DEFAULT                     _MK_MASK_CONST(0x7)
#define MISCREG_TSECA_HS_SECURITY_0_MSTR_ID_DEFAULT_MASK                        _MK_MASK_CONST(0xf)
#define MISCREG_TSECA_HS_SECURITY_0_MSTR_ID_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define MISCREG_TSECA_HS_SECURITY_0_MSTR_ID_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define MISCREG_TSECA_HS_SECURITY_0_MSTR_ID_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define MISCREG_TSECA_HS_SECURITY_0_MSTR_ID_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define MISCREG_TSECA_HS_SECURITY_0_MSTR_ID_CCPLEX                      _MK_ENUM_CONST(1)
#define MISCREG_TSECA_HS_SECURITY_0_MSTR_ID_CCPLEX_DPMU                 _MK_ENUM_CONST(2)
#define MISCREG_TSECA_HS_SECURITY_0_MSTR_ID_BPMP                        _MK_ENUM_CONST(3)
#define MISCREG_TSECA_HS_SECURITY_0_MSTR_ID_SPE                 _MK_ENUM_CONST(4)
#define MISCREG_TSECA_HS_SECURITY_0_MSTR_ID_SCE                 _MK_ENUM_CONST(5)
#define MISCREG_TSECA_HS_SECURITY_0_MSTR_ID_DMA_PER                     _MK_ENUM_CONST(6)
#define MISCREG_TSECA_HS_SECURITY_0_MSTR_ID_TSECA                       _MK_ENUM_CONST(7)
#define MISCREG_TSECA_HS_SECURITY_0_MSTR_ID_TSECB                       _MK_ENUM_CONST(8)
#define MISCREG_TSECA_HS_SECURITY_0_MSTR_ID_JTAGM                       _MK_ENUM_CONST(9)
#define MISCREG_TSECA_HS_SECURITY_0_MSTR_ID_CSITE                       _MK_ENUM_CONST(10)
#define MISCREG_TSECA_HS_SECURITY_0_MSTR_ID_APE                 _MK_ENUM_CONST(11)
#define MISCREG_TSECA_HS_SECURITY_0_MSTR_ID_Peatrans                    _MK_ENUM_CONST(12)
#define MISCREG_TSECA_HS_SECURITY_0_MSTR_ID_NVDEC                       _MK_ENUM_CONST(13)
#define MISCREG_TSECA_HS_SECURITY_0_MSTR_ID_RCE                 _MK_ENUM_CONST(14)
#define MISCREG_TSECA_HS_SECURITY_0_MSTR_ID_NVDEC1                      _MK_ENUM_CONST(15)

#define MISCREG_TSECA_HS_SECURITY_0_G7W_SHIFT                   _MK_SHIFT_CONST(15)
#define MISCREG_TSECA_HS_SECURITY_0_G7W_FIELD                   _MK_FIELD_CONST(0x1, MISCREG_TSECA_HS_SECURITY_0_G7W_SHIFT)
#define MISCREG_TSECA_HS_SECURITY_0_G7W_RANGE                   15:15
#define MISCREG_TSECA_HS_SECURITY_0_G7W_WOFFSET                 0x0
#define MISCREG_TSECA_HS_SECURITY_0_G7W_DEFAULT                 _MK_MASK_CONST(0x1)
#define MISCREG_TSECA_HS_SECURITY_0_G7W_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define MISCREG_TSECA_HS_SECURITY_0_G7W_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define MISCREG_TSECA_HS_SECURITY_0_G7W_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define MISCREG_TSECA_HS_SECURITY_0_G7W_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define MISCREG_TSECA_HS_SECURITY_0_G7W_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define MISCREG_TSECA_HS_SECURITY_0_G6W_SHIFT                   _MK_SHIFT_CONST(14)
#define MISCREG_TSECA_HS_SECURITY_0_G6W_FIELD                   _MK_FIELD_CONST(0x1, MISCREG_TSECA_HS_SECURITY_0_G6W_SHIFT)
#define MISCREG_TSECA_HS_SECURITY_0_G6W_RANGE                   14:14
#define MISCREG_TSECA_HS_SECURITY_0_G6W_WOFFSET                 0x0
#define MISCREG_TSECA_HS_SECURITY_0_G6W_DEFAULT                 _MK_MASK_CONST(0x1)
#define MISCREG_TSECA_HS_SECURITY_0_G6W_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define MISCREG_TSECA_HS_SECURITY_0_G6W_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define MISCREG_TSECA_HS_SECURITY_0_G6W_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define MISCREG_TSECA_HS_SECURITY_0_G6W_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define MISCREG_TSECA_HS_SECURITY_0_G6W_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define MISCREG_TSECA_HS_SECURITY_0_G5W_SHIFT                   _MK_SHIFT_CONST(13)
#define MISCREG_TSECA_HS_SECURITY_0_G5W_FIELD                   _MK_FIELD_CONST(0x1, MISCREG_TSECA_HS_SECURITY_0_G5W_SHIFT)
#define MISCREG_TSECA_HS_SECURITY_0_G5W_RANGE                   13:13
#define MISCREG_TSECA_HS_SECURITY_0_G5W_WOFFSET                 0x0
#define MISCREG_TSECA_HS_SECURITY_0_G5W_DEFAULT                 _MK_MASK_CONST(0x1)
#define MISCREG_TSECA_HS_SECURITY_0_G5W_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define MISCREG_TSECA_HS_SECURITY_0_G5W_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define MISCREG_TSECA_HS_SECURITY_0_G5W_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define MISCREG_TSECA_HS_SECURITY_0_G5W_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define MISCREG_TSECA_HS_SECURITY_0_G5W_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define MISCREG_TSECA_HS_SECURITY_0_G4W_SHIFT                   _MK_SHIFT_CONST(12)
#define MISCREG_TSECA_HS_SECURITY_0_G4W_FIELD                   _MK_FIELD_CONST(0x1, MISCREG_TSECA_HS_SECURITY_0_G4W_SHIFT)
#define MISCREG_TSECA_HS_SECURITY_0_G4W_RANGE                   12:12
#define MISCREG_TSECA_HS_SECURITY_0_G4W_WOFFSET                 0x0
#define MISCREG_TSECA_HS_SECURITY_0_G4W_DEFAULT                 _MK_MASK_CONST(0x1)
#define MISCREG_TSECA_HS_SECURITY_0_G4W_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define MISCREG_TSECA_HS_SECURITY_0_G4W_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define MISCREG_TSECA_HS_SECURITY_0_G4W_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define MISCREG_TSECA_HS_SECURITY_0_G4W_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define MISCREG_TSECA_HS_SECURITY_0_G4W_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define MISCREG_TSECA_HS_SECURITY_0_G3W_SHIFT                   _MK_SHIFT_CONST(11)
#define MISCREG_TSECA_HS_SECURITY_0_G3W_FIELD                   _MK_FIELD_CONST(0x1, MISCREG_TSECA_HS_SECURITY_0_G3W_SHIFT)
#define MISCREG_TSECA_HS_SECURITY_0_G3W_RANGE                   11:11
#define MISCREG_TSECA_HS_SECURITY_0_G3W_WOFFSET                 0x0
#define MISCREG_TSECA_HS_SECURITY_0_G3W_DEFAULT                 _MK_MASK_CONST(0x1)
#define MISCREG_TSECA_HS_SECURITY_0_G3W_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define MISCREG_TSECA_HS_SECURITY_0_G3W_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define MISCREG_TSECA_HS_SECURITY_0_G3W_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define MISCREG_TSECA_HS_SECURITY_0_G3W_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define MISCREG_TSECA_HS_SECURITY_0_G3W_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define MISCREG_TSECA_HS_SECURITY_0_G2W_SHIFT                   _MK_SHIFT_CONST(10)
#define MISCREG_TSECA_HS_SECURITY_0_G2W_FIELD                   _MK_FIELD_CONST(0x1, MISCREG_TSECA_HS_SECURITY_0_G2W_SHIFT)
#define MISCREG_TSECA_HS_SECURITY_0_G2W_RANGE                   10:10
#define MISCREG_TSECA_HS_SECURITY_0_G2W_WOFFSET                 0x0
#define MISCREG_TSECA_HS_SECURITY_0_G2W_DEFAULT                 _MK_MASK_CONST(0x1)
#define MISCREG_TSECA_HS_SECURITY_0_G2W_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define MISCREG_TSECA_HS_SECURITY_0_G2W_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define MISCREG_TSECA_HS_SECURITY_0_G2W_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define MISCREG_TSECA_HS_SECURITY_0_G2W_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define MISCREG_TSECA_HS_SECURITY_0_G2W_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define MISCREG_TSECA_HS_SECURITY_0_G1W_SHIFT                   _MK_SHIFT_CONST(9)
#define MISCREG_TSECA_HS_SECURITY_0_G1W_FIELD                   _MK_FIELD_CONST(0x1, MISCREG_TSECA_HS_SECURITY_0_G1W_SHIFT)
#define MISCREG_TSECA_HS_SECURITY_0_G1W_RANGE                   9:9
#define MISCREG_TSECA_HS_SECURITY_0_G1W_WOFFSET                 0x0
#define MISCREG_TSECA_HS_SECURITY_0_G1W_DEFAULT                 _MK_MASK_CONST(0x1)
#define MISCREG_TSECA_HS_SECURITY_0_G1W_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define MISCREG_TSECA_HS_SECURITY_0_G1W_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define MISCREG_TSECA_HS_SECURITY_0_G1W_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define MISCREG_TSECA_HS_SECURITY_0_G1W_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define MISCREG_TSECA_HS_SECURITY_0_G1W_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define MISCREG_TSECA_HS_SECURITY_0_G0W_SHIFT                   _MK_SHIFT_CONST(8)
#define MISCREG_TSECA_HS_SECURITY_0_G0W_FIELD                   _MK_FIELD_CONST(0x1, MISCREG_TSECA_HS_SECURITY_0_G0W_SHIFT)
#define MISCREG_TSECA_HS_SECURITY_0_G0W_RANGE                   8:8
#define MISCREG_TSECA_HS_SECURITY_0_G0W_WOFFSET                 0x0
#define MISCREG_TSECA_HS_SECURITY_0_G0W_DEFAULT                 _MK_MASK_CONST(0x1)
#define MISCREG_TSECA_HS_SECURITY_0_G0W_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define MISCREG_TSECA_HS_SECURITY_0_G0W_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define MISCREG_TSECA_HS_SECURITY_0_G0W_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define MISCREG_TSECA_HS_SECURITY_0_G0W_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define MISCREG_TSECA_HS_SECURITY_0_G0W_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define MISCREG_TSECA_HS_SECURITY_0_G7R_SHIFT                   _MK_SHIFT_CONST(7)
#define MISCREG_TSECA_HS_SECURITY_0_G7R_FIELD                   _MK_FIELD_CONST(0x1, MISCREG_TSECA_HS_SECURITY_0_G7R_SHIFT)
#define MISCREG_TSECA_HS_SECURITY_0_G7R_RANGE                   7:7
#define MISCREG_TSECA_HS_SECURITY_0_G7R_WOFFSET                 0x0
#define MISCREG_TSECA_HS_SECURITY_0_G7R_DEFAULT                 _MK_MASK_CONST(0x1)
#define MISCREG_TSECA_HS_SECURITY_0_G7R_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define MISCREG_TSECA_HS_SECURITY_0_G7R_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define MISCREG_TSECA_HS_SECURITY_0_G7R_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define MISCREG_TSECA_HS_SECURITY_0_G7R_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define MISCREG_TSECA_HS_SECURITY_0_G7R_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define MISCREG_TSECA_HS_SECURITY_0_G6R_SHIFT                   _MK_SHIFT_CONST(6)
#define MISCREG_TSECA_HS_SECURITY_0_G6R_FIELD                   _MK_FIELD_CONST(0x1, MISCREG_TSECA_HS_SECURITY_0_G6R_SHIFT)
#define MISCREG_TSECA_HS_SECURITY_0_G6R_RANGE                   6:6
#define MISCREG_TSECA_HS_SECURITY_0_G6R_WOFFSET                 0x0
#define MISCREG_TSECA_HS_SECURITY_0_G6R_DEFAULT                 _MK_MASK_CONST(0x1)
#define MISCREG_TSECA_HS_SECURITY_0_G6R_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define MISCREG_TSECA_HS_SECURITY_0_G6R_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define MISCREG_TSECA_HS_SECURITY_0_G6R_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define MISCREG_TSECA_HS_SECURITY_0_G6R_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define MISCREG_TSECA_HS_SECURITY_0_G6R_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define MISCREG_TSECA_HS_SECURITY_0_G5R_SHIFT                   _MK_SHIFT_CONST(5)
#define MISCREG_TSECA_HS_SECURITY_0_G5R_FIELD                   _MK_FIELD_CONST(0x1, MISCREG_TSECA_HS_SECURITY_0_G5R_SHIFT)
#define MISCREG_TSECA_HS_SECURITY_0_G5R_RANGE                   5:5
#define MISCREG_TSECA_HS_SECURITY_0_G5R_WOFFSET                 0x0
#define MISCREG_TSECA_HS_SECURITY_0_G5R_DEFAULT                 _MK_MASK_CONST(0x1)
#define MISCREG_TSECA_HS_SECURITY_0_G5R_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define MISCREG_TSECA_HS_SECURITY_0_G5R_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define MISCREG_TSECA_HS_SECURITY_0_G5R_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define MISCREG_TSECA_HS_SECURITY_0_G5R_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define MISCREG_TSECA_HS_SECURITY_0_G5R_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define MISCREG_TSECA_HS_SECURITY_0_G4R_SHIFT                   _MK_SHIFT_CONST(4)
#define MISCREG_TSECA_HS_SECURITY_0_G4R_FIELD                   _MK_FIELD_CONST(0x1, MISCREG_TSECA_HS_SECURITY_0_G4R_SHIFT)
#define MISCREG_TSECA_HS_SECURITY_0_G4R_RANGE                   4:4
#define MISCREG_TSECA_HS_SECURITY_0_G4R_WOFFSET                 0x0
#define MISCREG_TSECA_HS_SECURITY_0_G4R_DEFAULT                 _MK_MASK_CONST(0x1)
#define MISCREG_TSECA_HS_SECURITY_0_G4R_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define MISCREG_TSECA_HS_SECURITY_0_G4R_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define MISCREG_TSECA_HS_SECURITY_0_G4R_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define MISCREG_TSECA_HS_SECURITY_0_G4R_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define MISCREG_TSECA_HS_SECURITY_0_G4R_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define MISCREG_TSECA_HS_SECURITY_0_G3R_SHIFT                   _MK_SHIFT_CONST(3)
#define MISCREG_TSECA_HS_SECURITY_0_G3R_FIELD                   _MK_FIELD_CONST(0x1, MISCREG_TSECA_HS_SECURITY_0_G3R_SHIFT)
#define MISCREG_TSECA_HS_SECURITY_0_G3R_RANGE                   3:3
#define MISCREG_TSECA_HS_SECURITY_0_G3R_WOFFSET                 0x0
#define MISCREG_TSECA_HS_SECURITY_0_G3R_DEFAULT                 _MK_MASK_CONST(0x1)
#define MISCREG_TSECA_HS_SECURITY_0_G3R_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define MISCREG_TSECA_HS_SECURITY_0_G3R_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define MISCREG_TSECA_HS_SECURITY_0_G3R_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define MISCREG_TSECA_HS_SECURITY_0_G3R_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define MISCREG_TSECA_HS_SECURITY_0_G3R_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define MISCREG_TSECA_HS_SECURITY_0_G2R_SHIFT                   _MK_SHIFT_CONST(2)
#define MISCREG_TSECA_HS_SECURITY_0_G2R_FIELD                   _MK_FIELD_CONST(0x1, MISCREG_TSECA_HS_SECURITY_0_G2R_SHIFT)
#define MISCREG_TSECA_HS_SECURITY_0_G2R_RANGE                   2:2
#define MISCREG_TSECA_HS_SECURITY_0_G2R_WOFFSET                 0x0
#define MISCREG_TSECA_HS_SECURITY_0_G2R_DEFAULT                 _MK_MASK_CONST(0x1)
#define MISCREG_TSECA_HS_SECURITY_0_G2R_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define MISCREG_TSECA_HS_SECURITY_0_G2R_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define MISCREG_TSECA_HS_SECURITY_0_G2R_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define MISCREG_TSECA_HS_SECURITY_0_G2R_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define MISCREG_TSECA_HS_SECURITY_0_G2R_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define MISCREG_TSECA_HS_SECURITY_0_G1R_SHIFT                   _MK_SHIFT_CONST(1)
#define MISCREG_TSECA_HS_SECURITY_0_G1R_FIELD                   _MK_FIELD_CONST(0x1, MISCREG_TSECA_HS_SECURITY_0_G1R_SHIFT)
#define MISCREG_TSECA_HS_SECURITY_0_G1R_RANGE                   1:1
#define MISCREG_TSECA_HS_SECURITY_0_G1R_WOFFSET                 0x0
#define MISCREG_TSECA_HS_SECURITY_0_G1R_DEFAULT                 _MK_MASK_CONST(0x1)
#define MISCREG_TSECA_HS_SECURITY_0_G1R_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define MISCREG_TSECA_HS_SECURITY_0_G1R_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define MISCREG_TSECA_HS_SECURITY_0_G1R_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define MISCREG_TSECA_HS_SECURITY_0_G1R_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define MISCREG_TSECA_HS_SECURITY_0_G1R_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define MISCREG_TSECA_HS_SECURITY_0_G0R_SHIFT                   _MK_SHIFT_CONST(0)
#define MISCREG_TSECA_HS_SECURITY_0_G0R_FIELD                   _MK_FIELD_CONST(0x1, MISCREG_TSECA_HS_SECURITY_0_G0R_SHIFT)
#define MISCREG_TSECA_HS_SECURITY_0_G0R_RANGE                   0:0
#define MISCREG_TSECA_HS_SECURITY_0_G0R_WOFFSET                 0x0
#define MISCREG_TSECA_HS_SECURITY_0_G0R_DEFAULT                 _MK_MASK_CONST(0x1)
#define MISCREG_TSECA_HS_SECURITY_0_G0R_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define MISCREG_TSECA_HS_SECURITY_0_G0R_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define MISCREG_TSECA_HS_SECURITY_0_G0R_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define MISCREG_TSECA_HS_SECURITY_0_G0R_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define MISCREG_TSECA_HS_SECURITY_0_G0R_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)


// Register MISCREG_TSECA_LS_SECURITY_0
#define MISCREG_TSECA_LS_SECURITY_0                     _MK_ADDR_CONST(0x1020)
#define MISCREG_TSECA_LS_SECURITY_0_SECURE                      0x0
#define MISCREG_TSECA_LS_SECURITY_0_DUAL                        0x0
#define MISCREG_TSECA_LS_SECURITY_0_SCR                         SCRTSEC_0
#define MISCREG_TSECA_LS_SECURITY_0_WORD_COUNT                  0x1
#define MISCREG_TSECA_LS_SECURITY_0_RESET_VAL                   _MK_MASK_CONST(0x7ffff)
#define MISCREG_TSECA_LS_SECURITY_0_RESET_MASK                  _MK_MASK_CONST(0xfffff)
#define MISCREG_TSECA_LS_SECURITY_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define MISCREG_TSECA_LS_SECURITY_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define MISCREG_TSECA_LS_SECURITY_0_READ_MASK                   _MK_MASK_CONST(0xfffff)
#define MISCREG_TSECA_LS_SECURITY_0_WRITE_MASK                  _MK_MASK_CONST(0xffff)
#define MISCREG_TSECA_LS_SECURITY_0_MSTR_ID_SHIFT                       _MK_SHIFT_CONST(16)
#define MISCREG_TSECA_LS_SECURITY_0_MSTR_ID_FIELD                       _MK_FIELD_CONST(0xf, MISCREG_TSECA_LS_SECURITY_0_MSTR_ID_SHIFT)
#define MISCREG_TSECA_LS_SECURITY_0_MSTR_ID_RANGE                       19:16
#define MISCREG_TSECA_LS_SECURITY_0_MSTR_ID_WOFFSET                     0x0
#define MISCREG_TSECA_LS_SECURITY_0_MSTR_ID_DEFAULT                     _MK_MASK_CONST(0x7)
#define MISCREG_TSECA_LS_SECURITY_0_MSTR_ID_DEFAULT_MASK                        _MK_MASK_CONST(0xf)
#define MISCREG_TSECA_LS_SECURITY_0_MSTR_ID_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define MISCREG_TSECA_LS_SECURITY_0_MSTR_ID_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define MISCREG_TSECA_LS_SECURITY_0_MSTR_ID_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define MISCREG_TSECA_LS_SECURITY_0_MSTR_ID_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define MISCREG_TSECA_LS_SECURITY_0_MSTR_ID_CCPLEX                      _MK_ENUM_CONST(1)
#define MISCREG_TSECA_LS_SECURITY_0_MSTR_ID_CCPLEX_DPMU                 _MK_ENUM_CONST(2)
#define MISCREG_TSECA_LS_SECURITY_0_MSTR_ID_BPMP                        _MK_ENUM_CONST(3)
#define MISCREG_TSECA_LS_SECURITY_0_MSTR_ID_SPE                 _MK_ENUM_CONST(4)
#define MISCREG_TSECA_LS_SECURITY_0_MSTR_ID_SCE                 _MK_ENUM_CONST(5)
#define MISCREG_TSECA_LS_SECURITY_0_MSTR_ID_DMA_PER                     _MK_ENUM_CONST(6)
#define MISCREG_TSECA_LS_SECURITY_0_MSTR_ID_TSECA                       _MK_ENUM_CONST(7)
#define MISCREG_TSECA_LS_SECURITY_0_MSTR_ID_TSECB                       _MK_ENUM_CONST(8)
#define MISCREG_TSECA_LS_SECURITY_0_MSTR_ID_JTAGM                       _MK_ENUM_CONST(9)
#define MISCREG_TSECA_LS_SECURITY_0_MSTR_ID_CSITE                       _MK_ENUM_CONST(10)
#define MISCREG_TSECA_LS_SECURITY_0_MSTR_ID_APE                 _MK_ENUM_CONST(11)
#define MISCREG_TSECA_LS_SECURITY_0_MSTR_ID_Peatrans                    _MK_ENUM_CONST(12)
#define MISCREG_TSECA_LS_SECURITY_0_MSTR_ID_NVDEC                       _MK_ENUM_CONST(13)
#define MISCREG_TSECA_LS_SECURITY_0_MSTR_ID_RCE                 _MK_ENUM_CONST(14)
#define MISCREG_TSECA_LS_SECURITY_0_MSTR_ID_NVDEC1                      _MK_ENUM_CONST(15)

#define MISCREG_TSECA_LS_SECURITY_0_G7W_SHIFT                   _MK_SHIFT_CONST(15)
#define MISCREG_TSECA_LS_SECURITY_0_G7W_FIELD                   _MK_FIELD_CONST(0x1, MISCREG_TSECA_LS_SECURITY_0_G7W_SHIFT)
#define MISCREG_TSECA_LS_SECURITY_0_G7W_RANGE                   15:15
#define MISCREG_TSECA_LS_SECURITY_0_G7W_WOFFSET                 0x0
#define MISCREG_TSECA_LS_SECURITY_0_G7W_DEFAULT                 _MK_MASK_CONST(0x1)
#define MISCREG_TSECA_LS_SECURITY_0_G7W_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define MISCREG_TSECA_LS_SECURITY_0_G7W_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define MISCREG_TSECA_LS_SECURITY_0_G7W_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define MISCREG_TSECA_LS_SECURITY_0_G7W_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define MISCREG_TSECA_LS_SECURITY_0_G7W_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define MISCREG_TSECA_LS_SECURITY_0_G6W_SHIFT                   _MK_SHIFT_CONST(14)
#define MISCREG_TSECA_LS_SECURITY_0_G6W_FIELD                   _MK_FIELD_CONST(0x1, MISCREG_TSECA_LS_SECURITY_0_G6W_SHIFT)
#define MISCREG_TSECA_LS_SECURITY_0_G6W_RANGE                   14:14
#define MISCREG_TSECA_LS_SECURITY_0_G6W_WOFFSET                 0x0
#define MISCREG_TSECA_LS_SECURITY_0_G6W_DEFAULT                 _MK_MASK_CONST(0x1)
#define MISCREG_TSECA_LS_SECURITY_0_G6W_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define MISCREG_TSECA_LS_SECURITY_0_G6W_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define MISCREG_TSECA_LS_SECURITY_0_G6W_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define MISCREG_TSECA_LS_SECURITY_0_G6W_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define MISCREG_TSECA_LS_SECURITY_0_G6W_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define MISCREG_TSECA_LS_SECURITY_0_G5W_SHIFT                   _MK_SHIFT_CONST(13)
#define MISCREG_TSECA_LS_SECURITY_0_G5W_FIELD                   _MK_FIELD_CONST(0x1, MISCREG_TSECA_LS_SECURITY_0_G5W_SHIFT)
#define MISCREG_TSECA_LS_SECURITY_0_G5W_RANGE                   13:13
#define MISCREG_TSECA_LS_SECURITY_0_G5W_WOFFSET                 0x0
#define MISCREG_TSECA_LS_SECURITY_0_G5W_DEFAULT                 _MK_MASK_CONST(0x1)
#define MISCREG_TSECA_LS_SECURITY_0_G5W_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define MISCREG_TSECA_LS_SECURITY_0_G5W_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define MISCREG_TSECA_LS_SECURITY_0_G5W_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define MISCREG_TSECA_LS_SECURITY_0_G5W_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define MISCREG_TSECA_LS_SECURITY_0_G5W_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define MISCREG_TSECA_LS_SECURITY_0_G4W_SHIFT                   _MK_SHIFT_CONST(12)
#define MISCREG_TSECA_LS_SECURITY_0_G4W_FIELD                   _MK_FIELD_CONST(0x1, MISCREG_TSECA_LS_SECURITY_0_G4W_SHIFT)
#define MISCREG_TSECA_LS_SECURITY_0_G4W_RANGE                   12:12
#define MISCREG_TSECA_LS_SECURITY_0_G4W_WOFFSET                 0x0
#define MISCREG_TSECA_LS_SECURITY_0_G4W_DEFAULT                 _MK_MASK_CONST(0x1)
#define MISCREG_TSECA_LS_SECURITY_0_G4W_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define MISCREG_TSECA_LS_SECURITY_0_G4W_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define MISCREG_TSECA_LS_SECURITY_0_G4W_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define MISCREG_TSECA_LS_SECURITY_0_G4W_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define MISCREG_TSECA_LS_SECURITY_0_G4W_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define MISCREG_TSECA_LS_SECURITY_0_G3W_SHIFT                   _MK_SHIFT_CONST(11)
#define MISCREG_TSECA_LS_SECURITY_0_G3W_FIELD                   _MK_FIELD_CONST(0x1, MISCREG_TSECA_LS_SECURITY_0_G3W_SHIFT)
#define MISCREG_TSECA_LS_SECURITY_0_G3W_RANGE                   11:11
#define MISCREG_TSECA_LS_SECURITY_0_G3W_WOFFSET                 0x0
#define MISCREG_TSECA_LS_SECURITY_0_G3W_DEFAULT                 _MK_MASK_CONST(0x1)
#define MISCREG_TSECA_LS_SECURITY_0_G3W_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define MISCREG_TSECA_LS_SECURITY_0_G3W_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define MISCREG_TSECA_LS_SECURITY_0_G3W_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define MISCREG_TSECA_LS_SECURITY_0_G3W_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define MISCREG_TSECA_LS_SECURITY_0_G3W_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define MISCREG_TSECA_LS_SECURITY_0_G2W_SHIFT                   _MK_SHIFT_CONST(10)
#define MISCREG_TSECA_LS_SECURITY_0_G2W_FIELD                   _MK_FIELD_CONST(0x1, MISCREG_TSECA_LS_SECURITY_0_G2W_SHIFT)
#define MISCREG_TSECA_LS_SECURITY_0_G2W_RANGE                   10:10
#define MISCREG_TSECA_LS_SECURITY_0_G2W_WOFFSET                 0x0
#define MISCREG_TSECA_LS_SECURITY_0_G2W_DEFAULT                 _MK_MASK_CONST(0x1)
#define MISCREG_TSECA_LS_SECURITY_0_G2W_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define MISCREG_TSECA_LS_SECURITY_0_G2W_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define MISCREG_TSECA_LS_SECURITY_0_G2W_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define MISCREG_TSECA_LS_SECURITY_0_G2W_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define MISCREG_TSECA_LS_SECURITY_0_G2W_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define MISCREG_TSECA_LS_SECURITY_0_G1W_SHIFT                   _MK_SHIFT_CONST(9)
#define MISCREG_TSECA_LS_SECURITY_0_G1W_FIELD                   _MK_FIELD_CONST(0x1, MISCREG_TSECA_LS_SECURITY_0_G1W_SHIFT)
#define MISCREG_TSECA_LS_SECURITY_0_G1W_RANGE                   9:9
#define MISCREG_TSECA_LS_SECURITY_0_G1W_WOFFSET                 0x0
#define MISCREG_TSECA_LS_SECURITY_0_G1W_DEFAULT                 _MK_MASK_CONST(0x1)
#define MISCREG_TSECA_LS_SECURITY_0_G1W_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define MISCREG_TSECA_LS_SECURITY_0_G1W_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define MISCREG_TSECA_LS_SECURITY_0_G1W_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define MISCREG_TSECA_LS_SECURITY_0_G1W_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define MISCREG_TSECA_LS_SECURITY_0_G1W_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define MISCREG_TSECA_LS_SECURITY_0_G0W_SHIFT                   _MK_SHIFT_CONST(8)
#define MISCREG_TSECA_LS_SECURITY_0_G0W_FIELD                   _MK_FIELD_CONST(0x1, MISCREG_TSECA_LS_SECURITY_0_G0W_SHIFT)
#define MISCREG_TSECA_LS_SECURITY_0_G0W_RANGE                   8:8
#define MISCREG_TSECA_LS_SECURITY_0_G0W_WOFFSET                 0x0
#define MISCREG_TSECA_LS_SECURITY_0_G0W_DEFAULT                 _MK_MASK_CONST(0x1)
#define MISCREG_TSECA_LS_SECURITY_0_G0W_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define MISCREG_TSECA_LS_SECURITY_0_G0W_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define MISCREG_TSECA_LS_SECURITY_0_G0W_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define MISCREG_TSECA_LS_SECURITY_0_G0W_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define MISCREG_TSECA_LS_SECURITY_0_G0W_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define MISCREG_TSECA_LS_SECURITY_0_G7R_SHIFT                   _MK_SHIFT_CONST(7)
#define MISCREG_TSECA_LS_SECURITY_0_G7R_FIELD                   _MK_FIELD_CONST(0x1, MISCREG_TSECA_LS_SECURITY_0_G7R_SHIFT)
#define MISCREG_TSECA_LS_SECURITY_0_G7R_RANGE                   7:7
#define MISCREG_TSECA_LS_SECURITY_0_G7R_WOFFSET                 0x0
#define MISCREG_TSECA_LS_SECURITY_0_G7R_DEFAULT                 _MK_MASK_CONST(0x1)
#define MISCREG_TSECA_LS_SECURITY_0_G7R_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define MISCREG_TSECA_LS_SECURITY_0_G7R_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define MISCREG_TSECA_LS_SECURITY_0_G7R_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define MISCREG_TSECA_LS_SECURITY_0_G7R_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define MISCREG_TSECA_LS_SECURITY_0_G7R_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define MISCREG_TSECA_LS_SECURITY_0_G6R_SHIFT                   _MK_SHIFT_CONST(6)
#define MISCREG_TSECA_LS_SECURITY_0_G6R_FIELD                   _MK_FIELD_CONST(0x1, MISCREG_TSECA_LS_SECURITY_0_G6R_SHIFT)
#define MISCREG_TSECA_LS_SECURITY_0_G6R_RANGE                   6:6
#define MISCREG_TSECA_LS_SECURITY_0_G6R_WOFFSET                 0x0
#define MISCREG_TSECA_LS_SECURITY_0_G6R_DEFAULT                 _MK_MASK_CONST(0x1)
#define MISCREG_TSECA_LS_SECURITY_0_G6R_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define MISCREG_TSECA_LS_SECURITY_0_G6R_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define MISCREG_TSECA_LS_SECURITY_0_G6R_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define MISCREG_TSECA_LS_SECURITY_0_G6R_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define MISCREG_TSECA_LS_SECURITY_0_G6R_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define MISCREG_TSECA_LS_SECURITY_0_G5R_SHIFT                   _MK_SHIFT_CONST(5)
#define MISCREG_TSECA_LS_SECURITY_0_G5R_FIELD                   _MK_FIELD_CONST(0x1, MISCREG_TSECA_LS_SECURITY_0_G5R_SHIFT)
#define MISCREG_TSECA_LS_SECURITY_0_G5R_RANGE                   5:5
#define MISCREG_TSECA_LS_SECURITY_0_G5R_WOFFSET                 0x0
#define MISCREG_TSECA_LS_SECURITY_0_G5R_DEFAULT                 _MK_MASK_CONST(0x1)
#define MISCREG_TSECA_LS_SECURITY_0_G5R_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define MISCREG_TSECA_LS_SECURITY_0_G5R_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define MISCREG_TSECA_LS_SECURITY_0_G5R_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define MISCREG_TSECA_LS_SECURITY_0_G5R_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define MISCREG_TSECA_LS_SECURITY_0_G5R_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define MISCREG_TSECA_LS_SECURITY_0_G4R_SHIFT                   _MK_SHIFT_CONST(4)
#define MISCREG_TSECA_LS_SECURITY_0_G4R_FIELD                   _MK_FIELD_CONST(0x1, MISCREG_TSECA_LS_SECURITY_0_G4R_SHIFT)
#define MISCREG_TSECA_LS_SECURITY_0_G4R_RANGE                   4:4
#define MISCREG_TSECA_LS_SECURITY_0_G4R_WOFFSET                 0x0
#define MISCREG_TSECA_LS_SECURITY_0_G4R_DEFAULT                 _MK_MASK_CONST(0x1)
#define MISCREG_TSECA_LS_SECURITY_0_G4R_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define MISCREG_TSECA_LS_SECURITY_0_G4R_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define MISCREG_TSECA_LS_SECURITY_0_G4R_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define MISCREG_TSECA_LS_SECURITY_0_G4R_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define MISCREG_TSECA_LS_SECURITY_0_G4R_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define MISCREG_TSECA_LS_SECURITY_0_G3R_SHIFT                   _MK_SHIFT_CONST(3)
#define MISCREG_TSECA_LS_SECURITY_0_G3R_FIELD                   _MK_FIELD_CONST(0x1, MISCREG_TSECA_LS_SECURITY_0_G3R_SHIFT)
#define MISCREG_TSECA_LS_SECURITY_0_G3R_RANGE                   3:3
#define MISCREG_TSECA_LS_SECURITY_0_G3R_WOFFSET                 0x0
#define MISCREG_TSECA_LS_SECURITY_0_G3R_DEFAULT                 _MK_MASK_CONST(0x1)
#define MISCREG_TSECA_LS_SECURITY_0_G3R_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define MISCREG_TSECA_LS_SECURITY_0_G3R_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define MISCREG_TSECA_LS_SECURITY_0_G3R_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define MISCREG_TSECA_LS_SECURITY_0_G3R_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define MISCREG_TSECA_LS_SECURITY_0_G3R_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define MISCREG_TSECA_LS_SECURITY_0_G2R_SHIFT                   _MK_SHIFT_CONST(2)
#define MISCREG_TSECA_LS_SECURITY_0_G2R_FIELD                   _MK_FIELD_CONST(0x1, MISCREG_TSECA_LS_SECURITY_0_G2R_SHIFT)
#define MISCREG_TSECA_LS_SECURITY_0_G2R_RANGE                   2:2
#define MISCREG_TSECA_LS_SECURITY_0_G2R_WOFFSET                 0x0
#define MISCREG_TSECA_LS_SECURITY_0_G2R_DEFAULT                 _MK_MASK_CONST(0x1)
#define MISCREG_TSECA_LS_SECURITY_0_G2R_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define MISCREG_TSECA_LS_SECURITY_0_G2R_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define MISCREG_TSECA_LS_SECURITY_0_G2R_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define MISCREG_TSECA_LS_SECURITY_0_G2R_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define MISCREG_TSECA_LS_SECURITY_0_G2R_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define MISCREG_TSECA_LS_SECURITY_0_G1R_SHIFT                   _MK_SHIFT_CONST(1)
#define MISCREG_TSECA_LS_SECURITY_0_G1R_FIELD                   _MK_FIELD_CONST(0x1, MISCREG_TSECA_LS_SECURITY_0_G1R_SHIFT)
#define MISCREG_TSECA_LS_SECURITY_0_G1R_RANGE                   1:1
#define MISCREG_TSECA_LS_SECURITY_0_G1R_WOFFSET                 0x0
#define MISCREG_TSECA_LS_SECURITY_0_G1R_DEFAULT                 _MK_MASK_CONST(0x1)
#define MISCREG_TSECA_LS_SECURITY_0_G1R_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define MISCREG_TSECA_LS_SECURITY_0_G1R_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define MISCREG_TSECA_LS_SECURITY_0_G1R_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define MISCREG_TSECA_LS_SECURITY_0_G1R_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define MISCREG_TSECA_LS_SECURITY_0_G1R_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define MISCREG_TSECA_LS_SECURITY_0_G0R_SHIFT                   _MK_SHIFT_CONST(0)
#define MISCREG_TSECA_LS_SECURITY_0_G0R_FIELD                   _MK_FIELD_CONST(0x1, MISCREG_TSECA_LS_SECURITY_0_G0R_SHIFT)
#define MISCREG_TSECA_LS_SECURITY_0_G0R_RANGE                   0:0
#define MISCREG_TSECA_LS_SECURITY_0_G0R_WOFFSET                 0x0
#define MISCREG_TSECA_LS_SECURITY_0_G0R_DEFAULT                 _MK_MASK_CONST(0x1)
#define MISCREG_TSECA_LS_SECURITY_0_G0R_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define MISCREG_TSECA_LS_SECURITY_0_G0R_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define MISCREG_TSECA_LS_SECURITY_0_G0R_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define MISCREG_TSECA_LS_SECURITY_0_G0R_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define MISCREG_TSECA_LS_SECURITY_0_G0R_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)


// Register MISCREG_TSECB_HS_SECURITY_0
#define MISCREG_TSECB_HS_SECURITY_0                     _MK_ADDR_CONST(0x1024)
#define MISCREG_TSECB_HS_SECURITY_0_SECURE                      0x0
#define MISCREG_TSECB_HS_SECURITY_0_DUAL                        0x0
#define MISCREG_TSECB_HS_SECURITY_0_SCR                         SCRTSEC_0
#define MISCREG_TSECB_HS_SECURITY_0_WORD_COUNT                  0x1
#define MISCREG_TSECB_HS_SECURITY_0_RESET_VAL                   _MK_MASK_CONST(0x8ffff)
#define MISCREG_TSECB_HS_SECURITY_0_RESET_MASK                  _MK_MASK_CONST(0xfffff)
#define MISCREG_TSECB_HS_SECURITY_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define MISCREG_TSECB_HS_SECURITY_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define MISCREG_TSECB_HS_SECURITY_0_READ_MASK                   _MK_MASK_CONST(0xfffff)
#define MISCREG_TSECB_HS_SECURITY_0_WRITE_MASK                  _MK_MASK_CONST(0xffff)
#define MISCREG_TSECB_HS_SECURITY_0_MSTR_ID_SHIFT                       _MK_SHIFT_CONST(16)
#define MISCREG_TSECB_HS_SECURITY_0_MSTR_ID_FIELD                       _MK_FIELD_CONST(0xf, MISCREG_TSECB_HS_SECURITY_0_MSTR_ID_SHIFT)
#define MISCREG_TSECB_HS_SECURITY_0_MSTR_ID_RANGE                       19:16
#define MISCREG_TSECB_HS_SECURITY_0_MSTR_ID_WOFFSET                     0x0
#define MISCREG_TSECB_HS_SECURITY_0_MSTR_ID_DEFAULT                     _MK_MASK_CONST(0x8)
#define MISCREG_TSECB_HS_SECURITY_0_MSTR_ID_DEFAULT_MASK                        _MK_MASK_CONST(0xf)
#define MISCREG_TSECB_HS_SECURITY_0_MSTR_ID_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define MISCREG_TSECB_HS_SECURITY_0_MSTR_ID_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define MISCREG_TSECB_HS_SECURITY_0_MSTR_ID_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define MISCREG_TSECB_HS_SECURITY_0_MSTR_ID_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define MISCREG_TSECB_HS_SECURITY_0_MSTR_ID_CCPLEX                      _MK_ENUM_CONST(1)
#define MISCREG_TSECB_HS_SECURITY_0_MSTR_ID_CCPLEX_DPMU                 _MK_ENUM_CONST(2)
#define MISCREG_TSECB_HS_SECURITY_0_MSTR_ID_BPMP                        _MK_ENUM_CONST(3)
#define MISCREG_TSECB_HS_SECURITY_0_MSTR_ID_SPE                 _MK_ENUM_CONST(4)
#define MISCREG_TSECB_HS_SECURITY_0_MSTR_ID_SCE                 _MK_ENUM_CONST(5)
#define MISCREG_TSECB_HS_SECURITY_0_MSTR_ID_DMA_PER                     _MK_ENUM_CONST(6)
#define MISCREG_TSECB_HS_SECURITY_0_MSTR_ID_TSECA                       _MK_ENUM_CONST(7)
#define MISCREG_TSECB_HS_SECURITY_0_MSTR_ID_TSECB                       _MK_ENUM_CONST(8)
#define MISCREG_TSECB_HS_SECURITY_0_MSTR_ID_JTAGM                       _MK_ENUM_CONST(9)
#define MISCREG_TSECB_HS_SECURITY_0_MSTR_ID_CSITE                       _MK_ENUM_CONST(10)
#define MISCREG_TSECB_HS_SECURITY_0_MSTR_ID_APE                 _MK_ENUM_CONST(11)
#define MISCREG_TSECB_HS_SECURITY_0_MSTR_ID_Peatrans                    _MK_ENUM_CONST(12)
#define MISCREG_TSECB_HS_SECURITY_0_MSTR_ID_NVDEC                       _MK_ENUM_CONST(13)
#define MISCREG_TSECB_HS_SECURITY_0_MSTR_ID_RCE                 _MK_ENUM_CONST(14)
#define MISCREG_TSECB_HS_SECURITY_0_MSTR_ID_NVDEC1                      _MK_ENUM_CONST(15)

#define MISCREG_TSECB_HS_SECURITY_0_G7W_SHIFT                   _MK_SHIFT_CONST(15)
#define MISCREG_TSECB_HS_SECURITY_0_G7W_FIELD                   _MK_FIELD_CONST(0x1, MISCREG_TSECB_HS_SECURITY_0_G7W_SHIFT)
#define MISCREG_TSECB_HS_SECURITY_0_G7W_RANGE                   15:15
#define MISCREG_TSECB_HS_SECURITY_0_G7W_WOFFSET                 0x0
#define MISCREG_TSECB_HS_SECURITY_0_G7W_DEFAULT                 _MK_MASK_CONST(0x1)
#define MISCREG_TSECB_HS_SECURITY_0_G7W_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define MISCREG_TSECB_HS_SECURITY_0_G7W_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define MISCREG_TSECB_HS_SECURITY_0_G7W_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define MISCREG_TSECB_HS_SECURITY_0_G7W_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define MISCREG_TSECB_HS_SECURITY_0_G7W_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define MISCREG_TSECB_HS_SECURITY_0_G6W_SHIFT                   _MK_SHIFT_CONST(14)
#define MISCREG_TSECB_HS_SECURITY_0_G6W_FIELD                   _MK_FIELD_CONST(0x1, MISCREG_TSECB_HS_SECURITY_0_G6W_SHIFT)
#define MISCREG_TSECB_HS_SECURITY_0_G6W_RANGE                   14:14
#define MISCREG_TSECB_HS_SECURITY_0_G6W_WOFFSET                 0x0
#define MISCREG_TSECB_HS_SECURITY_0_G6W_DEFAULT                 _MK_MASK_CONST(0x1)
#define MISCREG_TSECB_HS_SECURITY_0_G6W_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define MISCREG_TSECB_HS_SECURITY_0_G6W_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define MISCREG_TSECB_HS_SECURITY_0_G6W_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define MISCREG_TSECB_HS_SECURITY_0_G6W_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define MISCREG_TSECB_HS_SECURITY_0_G6W_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define MISCREG_TSECB_HS_SECURITY_0_G5W_SHIFT                   _MK_SHIFT_CONST(13)
#define MISCREG_TSECB_HS_SECURITY_0_G5W_FIELD                   _MK_FIELD_CONST(0x1, MISCREG_TSECB_HS_SECURITY_0_G5W_SHIFT)
#define MISCREG_TSECB_HS_SECURITY_0_G5W_RANGE                   13:13
#define MISCREG_TSECB_HS_SECURITY_0_G5W_WOFFSET                 0x0
#define MISCREG_TSECB_HS_SECURITY_0_G5W_DEFAULT                 _MK_MASK_CONST(0x1)
#define MISCREG_TSECB_HS_SECURITY_0_G5W_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define MISCREG_TSECB_HS_SECURITY_0_G5W_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define MISCREG_TSECB_HS_SECURITY_0_G5W_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define MISCREG_TSECB_HS_SECURITY_0_G5W_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define MISCREG_TSECB_HS_SECURITY_0_G5W_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define MISCREG_TSECB_HS_SECURITY_0_G4W_SHIFT                   _MK_SHIFT_CONST(12)
#define MISCREG_TSECB_HS_SECURITY_0_G4W_FIELD                   _MK_FIELD_CONST(0x1, MISCREG_TSECB_HS_SECURITY_0_G4W_SHIFT)
#define MISCREG_TSECB_HS_SECURITY_0_G4W_RANGE                   12:12
#define MISCREG_TSECB_HS_SECURITY_0_G4W_WOFFSET                 0x0
#define MISCREG_TSECB_HS_SECURITY_0_G4W_DEFAULT                 _MK_MASK_CONST(0x1)
#define MISCREG_TSECB_HS_SECURITY_0_G4W_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define MISCREG_TSECB_HS_SECURITY_0_G4W_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define MISCREG_TSECB_HS_SECURITY_0_G4W_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define MISCREG_TSECB_HS_SECURITY_0_G4W_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define MISCREG_TSECB_HS_SECURITY_0_G4W_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define MISCREG_TSECB_HS_SECURITY_0_G3W_SHIFT                   _MK_SHIFT_CONST(11)
#define MISCREG_TSECB_HS_SECURITY_0_G3W_FIELD                   _MK_FIELD_CONST(0x1, MISCREG_TSECB_HS_SECURITY_0_G3W_SHIFT)
#define MISCREG_TSECB_HS_SECURITY_0_G3W_RANGE                   11:11
#define MISCREG_TSECB_HS_SECURITY_0_G3W_WOFFSET                 0x0
#define MISCREG_TSECB_HS_SECURITY_0_G3W_DEFAULT                 _MK_MASK_CONST(0x1)
#define MISCREG_TSECB_HS_SECURITY_0_G3W_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define MISCREG_TSECB_HS_SECURITY_0_G3W_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define MISCREG_TSECB_HS_SECURITY_0_G3W_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define MISCREG_TSECB_HS_SECURITY_0_G3W_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define MISCREG_TSECB_HS_SECURITY_0_G3W_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define MISCREG_TSECB_HS_SECURITY_0_G2W_SHIFT                   _MK_SHIFT_CONST(10)
#define MISCREG_TSECB_HS_SECURITY_0_G2W_FIELD                   _MK_FIELD_CONST(0x1, MISCREG_TSECB_HS_SECURITY_0_G2W_SHIFT)
#define MISCREG_TSECB_HS_SECURITY_0_G2W_RANGE                   10:10
#define MISCREG_TSECB_HS_SECURITY_0_G2W_WOFFSET                 0x0
#define MISCREG_TSECB_HS_SECURITY_0_G2W_DEFAULT                 _MK_MASK_CONST(0x1)
#define MISCREG_TSECB_HS_SECURITY_0_G2W_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define MISCREG_TSECB_HS_SECURITY_0_G2W_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define MISCREG_TSECB_HS_SECURITY_0_G2W_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define MISCREG_TSECB_HS_SECURITY_0_G2W_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define MISCREG_TSECB_HS_SECURITY_0_G2W_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define MISCREG_TSECB_HS_SECURITY_0_G1W_SHIFT                   _MK_SHIFT_CONST(9)
#define MISCREG_TSECB_HS_SECURITY_0_G1W_FIELD                   _MK_FIELD_CONST(0x1, MISCREG_TSECB_HS_SECURITY_0_G1W_SHIFT)
#define MISCREG_TSECB_HS_SECURITY_0_G1W_RANGE                   9:9
#define MISCREG_TSECB_HS_SECURITY_0_G1W_WOFFSET                 0x0
#define MISCREG_TSECB_HS_SECURITY_0_G1W_DEFAULT                 _MK_MASK_CONST(0x1)
#define MISCREG_TSECB_HS_SECURITY_0_G1W_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define MISCREG_TSECB_HS_SECURITY_0_G1W_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define MISCREG_TSECB_HS_SECURITY_0_G1W_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define MISCREG_TSECB_HS_SECURITY_0_G1W_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define MISCREG_TSECB_HS_SECURITY_0_G1W_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define MISCREG_TSECB_HS_SECURITY_0_G0W_SHIFT                   _MK_SHIFT_CONST(8)
#define MISCREG_TSECB_HS_SECURITY_0_G0W_FIELD                   _MK_FIELD_CONST(0x1, MISCREG_TSECB_HS_SECURITY_0_G0W_SHIFT)
#define MISCREG_TSECB_HS_SECURITY_0_G0W_RANGE                   8:8
#define MISCREG_TSECB_HS_SECURITY_0_G0W_WOFFSET                 0x0
#define MISCREG_TSECB_HS_SECURITY_0_G0W_DEFAULT                 _MK_MASK_CONST(0x1)
#define MISCREG_TSECB_HS_SECURITY_0_G0W_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define MISCREG_TSECB_HS_SECURITY_0_G0W_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define MISCREG_TSECB_HS_SECURITY_0_G0W_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define MISCREG_TSECB_HS_SECURITY_0_G0W_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define MISCREG_TSECB_HS_SECURITY_0_G0W_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define MISCREG_TSECB_HS_SECURITY_0_G7R_SHIFT                   _MK_SHIFT_CONST(7)
#define MISCREG_TSECB_HS_SECURITY_0_G7R_FIELD                   _MK_FIELD_CONST(0x1, MISCREG_TSECB_HS_SECURITY_0_G7R_SHIFT)
#define MISCREG_TSECB_HS_SECURITY_0_G7R_RANGE                   7:7
#define MISCREG_TSECB_HS_SECURITY_0_G7R_WOFFSET                 0x0
#define MISCREG_TSECB_HS_SECURITY_0_G7R_DEFAULT                 _MK_MASK_CONST(0x1)
#define MISCREG_TSECB_HS_SECURITY_0_G7R_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define MISCREG_TSECB_HS_SECURITY_0_G7R_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define MISCREG_TSECB_HS_SECURITY_0_G7R_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define MISCREG_TSECB_HS_SECURITY_0_G7R_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define MISCREG_TSECB_HS_SECURITY_0_G7R_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define MISCREG_TSECB_HS_SECURITY_0_G6R_SHIFT                   _MK_SHIFT_CONST(6)
#define MISCREG_TSECB_HS_SECURITY_0_G6R_FIELD                   _MK_FIELD_CONST(0x1, MISCREG_TSECB_HS_SECURITY_0_G6R_SHIFT)
#define MISCREG_TSECB_HS_SECURITY_0_G6R_RANGE                   6:6
#define MISCREG_TSECB_HS_SECURITY_0_G6R_WOFFSET                 0x0
#define MISCREG_TSECB_HS_SECURITY_0_G6R_DEFAULT                 _MK_MASK_CONST(0x1)
#define MISCREG_TSECB_HS_SECURITY_0_G6R_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define MISCREG_TSECB_HS_SECURITY_0_G6R_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define MISCREG_TSECB_HS_SECURITY_0_G6R_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define MISCREG_TSECB_HS_SECURITY_0_G6R_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define MISCREG_TSECB_HS_SECURITY_0_G6R_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define MISCREG_TSECB_HS_SECURITY_0_G5R_SHIFT                   _MK_SHIFT_CONST(5)
#define MISCREG_TSECB_HS_SECURITY_0_G5R_FIELD                   _MK_FIELD_CONST(0x1, MISCREG_TSECB_HS_SECURITY_0_G5R_SHIFT)
#define MISCREG_TSECB_HS_SECURITY_0_G5R_RANGE                   5:5
#define MISCREG_TSECB_HS_SECURITY_0_G5R_WOFFSET                 0x0
#define MISCREG_TSECB_HS_SECURITY_0_G5R_DEFAULT                 _MK_MASK_CONST(0x1)
#define MISCREG_TSECB_HS_SECURITY_0_G5R_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define MISCREG_TSECB_HS_SECURITY_0_G5R_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define MISCREG_TSECB_HS_SECURITY_0_G5R_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define MISCREG_TSECB_HS_SECURITY_0_G5R_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define MISCREG_TSECB_HS_SECURITY_0_G5R_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define MISCREG_TSECB_HS_SECURITY_0_G4R_SHIFT                   _MK_SHIFT_CONST(4)
#define MISCREG_TSECB_HS_SECURITY_0_G4R_FIELD                   _MK_FIELD_CONST(0x1, MISCREG_TSECB_HS_SECURITY_0_G4R_SHIFT)
#define MISCREG_TSECB_HS_SECURITY_0_G4R_RANGE                   4:4
#define MISCREG_TSECB_HS_SECURITY_0_G4R_WOFFSET                 0x0
#define MISCREG_TSECB_HS_SECURITY_0_G4R_DEFAULT                 _MK_MASK_CONST(0x1)
#define MISCREG_TSECB_HS_SECURITY_0_G4R_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define MISCREG_TSECB_HS_SECURITY_0_G4R_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define MISCREG_TSECB_HS_SECURITY_0_G4R_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define MISCREG_TSECB_HS_SECURITY_0_G4R_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define MISCREG_TSECB_HS_SECURITY_0_G4R_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define MISCREG_TSECB_HS_SECURITY_0_G3R_SHIFT                   _MK_SHIFT_CONST(3)
#define MISCREG_TSECB_HS_SECURITY_0_G3R_FIELD                   _MK_FIELD_CONST(0x1, MISCREG_TSECB_HS_SECURITY_0_G3R_SHIFT)
#define MISCREG_TSECB_HS_SECURITY_0_G3R_RANGE                   3:3
#define MISCREG_TSECB_HS_SECURITY_0_G3R_WOFFSET                 0x0
#define MISCREG_TSECB_HS_SECURITY_0_G3R_DEFAULT                 _MK_MASK_CONST(0x1)
#define MISCREG_TSECB_HS_SECURITY_0_G3R_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define MISCREG_TSECB_HS_SECURITY_0_G3R_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define MISCREG_TSECB_HS_SECURITY_0_G3R_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define MISCREG_TSECB_HS_SECURITY_0_G3R_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define MISCREG_TSECB_HS_SECURITY_0_G3R_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define MISCREG_TSECB_HS_SECURITY_0_G2R_SHIFT                   _MK_SHIFT_CONST(2)
#define MISCREG_TSECB_HS_SECURITY_0_G2R_FIELD                   _MK_FIELD_CONST(0x1, MISCREG_TSECB_HS_SECURITY_0_G2R_SHIFT)
#define MISCREG_TSECB_HS_SECURITY_0_G2R_RANGE                   2:2
#define MISCREG_TSECB_HS_SECURITY_0_G2R_WOFFSET                 0x0
#define MISCREG_TSECB_HS_SECURITY_0_G2R_DEFAULT                 _MK_MASK_CONST(0x1)
#define MISCREG_TSECB_HS_SECURITY_0_G2R_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define MISCREG_TSECB_HS_SECURITY_0_G2R_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define MISCREG_TSECB_HS_SECURITY_0_G2R_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define MISCREG_TSECB_HS_SECURITY_0_G2R_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define MISCREG_TSECB_HS_SECURITY_0_G2R_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define MISCREG_TSECB_HS_SECURITY_0_G1R_SHIFT                   _MK_SHIFT_CONST(1)
#define MISCREG_TSECB_HS_SECURITY_0_G1R_FIELD                   _MK_FIELD_CONST(0x1, MISCREG_TSECB_HS_SECURITY_0_G1R_SHIFT)
#define MISCREG_TSECB_HS_SECURITY_0_G1R_RANGE                   1:1
#define MISCREG_TSECB_HS_SECURITY_0_G1R_WOFFSET                 0x0
#define MISCREG_TSECB_HS_SECURITY_0_G1R_DEFAULT                 _MK_MASK_CONST(0x1)
#define MISCREG_TSECB_HS_SECURITY_0_G1R_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define MISCREG_TSECB_HS_SECURITY_0_G1R_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define MISCREG_TSECB_HS_SECURITY_0_G1R_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define MISCREG_TSECB_HS_SECURITY_0_G1R_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define MISCREG_TSECB_HS_SECURITY_0_G1R_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define MISCREG_TSECB_HS_SECURITY_0_G0R_SHIFT                   _MK_SHIFT_CONST(0)
#define MISCREG_TSECB_HS_SECURITY_0_G0R_FIELD                   _MK_FIELD_CONST(0x1, MISCREG_TSECB_HS_SECURITY_0_G0R_SHIFT)
#define MISCREG_TSECB_HS_SECURITY_0_G0R_RANGE                   0:0
#define MISCREG_TSECB_HS_SECURITY_0_G0R_WOFFSET                 0x0
#define MISCREG_TSECB_HS_SECURITY_0_G0R_DEFAULT                 _MK_MASK_CONST(0x1)
#define MISCREG_TSECB_HS_SECURITY_0_G0R_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define MISCREG_TSECB_HS_SECURITY_0_G0R_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define MISCREG_TSECB_HS_SECURITY_0_G0R_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define MISCREG_TSECB_HS_SECURITY_0_G0R_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define MISCREG_TSECB_HS_SECURITY_0_G0R_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)


// Register MISCREG_TSECB_LS_SECURITY_0
#define MISCREG_TSECB_LS_SECURITY_0                     _MK_ADDR_CONST(0x1028)
#define MISCREG_TSECB_LS_SECURITY_0_SECURE                      0x0
#define MISCREG_TSECB_LS_SECURITY_0_DUAL                        0x0
#define MISCREG_TSECB_LS_SECURITY_0_SCR                         SCRTSEC_0
#define MISCREG_TSECB_LS_SECURITY_0_WORD_COUNT                  0x1
#define MISCREG_TSECB_LS_SECURITY_0_RESET_VAL                   _MK_MASK_CONST(0x8ffff)
#define MISCREG_TSECB_LS_SECURITY_0_RESET_MASK                  _MK_MASK_CONST(0xfffff)
#define MISCREG_TSECB_LS_SECURITY_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define MISCREG_TSECB_LS_SECURITY_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define MISCREG_TSECB_LS_SECURITY_0_READ_MASK                   _MK_MASK_CONST(0xfffff)
#define MISCREG_TSECB_LS_SECURITY_0_WRITE_MASK                  _MK_MASK_CONST(0xffff)
#define MISCREG_TSECB_LS_SECURITY_0_MSTR_ID_SHIFT                       _MK_SHIFT_CONST(16)
#define MISCREG_TSECB_LS_SECURITY_0_MSTR_ID_FIELD                       _MK_FIELD_CONST(0xf, MISCREG_TSECB_LS_SECURITY_0_MSTR_ID_SHIFT)
#define MISCREG_TSECB_LS_SECURITY_0_MSTR_ID_RANGE                       19:16
#define MISCREG_TSECB_LS_SECURITY_0_MSTR_ID_WOFFSET                     0x0
#define MISCREG_TSECB_LS_SECURITY_0_MSTR_ID_DEFAULT                     _MK_MASK_CONST(0x8)
#define MISCREG_TSECB_LS_SECURITY_0_MSTR_ID_DEFAULT_MASK                        _MK_MASK_CONST(0xf)
#define MISCREG_TSECB_LS_SECURITY_0_MSTR_ID_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define MISCREG_TSECB_LS_SECURITY_0_MSTR_ID_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define MISCREG_TSECB_LS_SECURITY_0_MSTR_ID_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define MISCREG_TSECB_LS_SECURITY_0_MSTR_ID_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define MISCREG_TSECB_LS_SECURITY_0_MSTR_ID_CCPLEX                      _MK_ENUM_CONST(1)
#define MISCREG_TSECB_LS_SECURITY_0_MSTR_ID_CCPLEX_DPMU                 _MK_ENUM_CONST(2)
#define MISCREG_TSECB_LS_SECURITY_0_MSTR_ID_BPMP                        _MK_ENUM_CONST(3)
#define MISCREG_TSECB_LS_SECURITY_0_MSTR_ID_SPE                 _MK_ENUM_CONST(4)
#define MISCREG_TSECB_LS_SECURITY_0_MSTR_ID_SCE                 _MK_ENUM_CONST(5)
#define MISCREG_TSECB_LS_SECURITY_0_MSTR_ID_DMA_PER                     _MK_ENUM_CONST(6)
#define MISCREG_TSECB_LS_SECURITY_0_MSTR_ID_TSECA                       _MK_ENUM_CONST(7)
#define MISCREG_TSECB_LS_SECURITY_0_MSTR_ID_TSECB                       _MK_ENUM_CONST(8)
#define MISCREG_TSECB_LS_SECURITY_0_MSTR_ID_JTAGM                       _MK_ENUM_CONST(9)
#define MISCREG_TSECB_LS_SECURITY_0_MSTR_ID_CSITE                       _MK_ENUM_CONST(10)
#define MISCREG_TSECB_LS_SECURITY_0_MSTR_ID_APE                 _MK_ENUM_CONST(11)
#define MISCREG_TSECB_LS_SECURITY_0_MSTR_ID_Peatrans                    _MK_ENUM_CONST(12)
#define MISCREG_TSECB_LS_SECURITY_0_MSTR_ID_NVDEC                       _MK_ENUM_CONST(13)
#define MISCREG_TSECB_LS_SECURITY_0_MSTR_ID_RCE                 _MK_ENUM_CONST(14)
#define MISCREG_TSECB_LS_SECURITY_0_MSTR_ID_NVDEC1                      _MK_ENUM_CONST(15)

#define MISCREG_TSECB_LS_SECURITY_0_G7W_SHIFT                   _MK_SHIFT_CONST(15)
#define MISCREG_TSECB_LS_SECURITY_0_G7W_FIELD                   _MK_FIELD_CONST(0x1, MISCREG_TSECB_LS_SECURITY_0_G7W_SHIFT)
#define MISCREG_TSECB_LS_SECURITY_0_G7W_RANGE                   15:15
#define MISCREG_TSECB_LS_SECURITY_0_G7W_WOFFSET                 0x0
#define MISCREG_TSECB_LS_SECURITY_0_G7W_DEFAULT                 _MK_MASK_CONST(0x1)
#define MISCREG_TSECB_LS_SECURITY_0_G7W_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define MISCREG_TSECB_LS_SECURITY_0_G7W_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define MISCREG_TSECB_LS_SECURITY_0_G7W_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define MISCREG_TSECB_LS_SECURITY_0_G7W_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define MISCREG_TSECB_LS_SECURITY_0_G7W_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define MISCREG_TSECB_LS_SECURITY_0_G6W_SHIFT                   _MK_SHIFT_CONST(14)
#define MISCREG_TSECB_LS_SECURITY_0_G6W_FIELD                   _MK_FIELD_CONST(0x1, MISCREG_TSECB_LS_SECURITY_0_G6W_SHIFT)
#define MISCREG_TSECB_LS_SECURITY_0_G6W_RANGE                   14:14
#define MISCREG_TSECB_LS_SECURITY_0_G6W_WOFFSET                 0x0
#define MISCREG_TSECB_LS_SECURITY_0_G6W_DEFAULT                 _MK_MASK_CONST(0x1)
#define MISCREG_TSECB_LS_SECURITY_0_G6W_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define MISCREG_TSECB_LS_SECURITY_0_G6W_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define MISCREG_TSECB_LS_SECURITY_0_G6W_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define MISCREG_TSECB_LS_SECURITY_0_G6W_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define MISCREG_TSECB_LS_SECURITY_0_G6W_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define MISCREG_TSECB_LS_SECURITY_0_G5W_SHIFT                   _MK_SHIFT_CONST(13)
#define MISCREG_TSECB_LS_SECURITY_0_G5W_FIELD                   _MK_FIELD_CONST(0x1, MISCREG_TSECB_LS_SECURITY_0_G5W_SHIFT)
#define MISCREG_TSECB_LS_SECURITY_0_G5W_RANGE                   13:13
#define MISCREG_TSECB_LS_SECURITY_0_G5W_WOFFSET                 0x0
#define MISCREG_TSECB_LS_SECURITY_0_G5W_DEFAULT                 _MK_MASK_CONST(0x1)
#define MISCREG_TSECB_LS_SECURITY_0_G5W_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define MISCREG_TSECB_LS_SECURITY_0_G5W_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define MISCREG_TSECB_LS_SECURITY_0_G5W_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define MISCREG_TSECB_LS_SECURITY_0_G5W_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define MISCREG_TSECB_LS_SECURITY_0_G5W_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define MISCREG_TSECB_LS_SECURITY_0_G4W_SHIFT                   _MK_SHIFT_CONST(12)
#define MISCREG_TSECB_LS_SECURITY_0_G4W_FIELD                   _MK_FIELD_CONST(0x1, MISCREG_TSECB_LS_SECURITY_0_G4W_SHIFT)
#define MISCREG_TSECB_LS_SECURITY_0_G4W_RANGE                   12:12
#define MISCREG_TSECB_LS_SECURITY_0_G4W_WOFFSET                 0x0
#define MISCREG_TSECB_LS_SECURITY_0_G4W_DEFAULT                 _MK_MASK_CONST(0x1)
#define MISCREG_TSECB_LS_SECURITY_0_G4W_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define MISCREG_TSECB_LS_SECURITY_0_G4W_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define MISCREG_TSECB_LS_SECURITY_0_G4W_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define MISCREG_TSECB_LS_SECURITY_0_G4W_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define MISCREG_TSECB_LS_SECURITY_0_G4W_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define MISCREG_TSECB_LS_SECURITY_0_G3W_SHIFT                   _MK_SHIFT_CONST(11)
#define MISCREG_TSECB_LS_SECURITY_0_G3W_FIELD                   _MK_FIELD_CONST(0x1, MISCREG_TSECB_LS_SECURITY_0_G3W_SHIFT)
#define MISCREG_TSECB_LS_SECURITY_0_G3W_RANGE                   11:11
#define MISCREG_TSECB_LS_SECURITY_0_G3W_WOFFSET                 0x0
#define MISCREG_TSECB_LS_SECURITY_0_G3W_DEFAULT                 _MK_MASK_CONST(0x1)
#define MISCREG_TSECB_LS_SECURITY_0_G3W_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define MISCREG_TSECB_LS_SECURITY_0_G3W_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define MISCREG_TSECB_LS_SECURITY_0_G3W_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define MISCREG_TSECB_LS_SECURITY_0_G3W_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define MISCREG_TSECB_LS_SECURITY_0_G3W_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define MISCREG_TSECB_LS_SECURITY_0_G2W_SHIFT                   _MK_SHIFT_CONST(10)
#define MISCREG_TSECB_LS_SECURITY_0_G2W_FIELD                   _MK_FIELD_CONST(0x1, MISCREG_TSECB_LS_SECURITY_0_G2W_SHIFT)
#define MISCREG_TSECB_LS_SECURITY_0_G2W_RANGE                   10:10
#define MISCREG_TSECB_LS_SECURITY_0_G2W_WOFFSET                 0x0
#define MISCREG_TSECB_LS_SECURITY_0_G2W_DEFAULT                 _MK_MASK_CONST(0x1)
#define MISCREG_TSECB_LS_SECURITY_0_G2W_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define MISCREG_TSECB_LS_SECURITY_0_G2W_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define MISCREG_TSECB_LS_SECURITY_0_G2W_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define MISCREG_TSECB_LS_SECURITY_0_G2W_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define MISCREG_TSECB_LS_SECURITY_0_G2W_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define MISCREG_TSECB_LS_SECURITY_0_G1W_SHIFT                   _MK_SHIFT_CONST(9)
#define MISCREG_TSECB_LS_SECURITY_0_G1W_FIELD                   _MK_FIELD_CONST(0x1, MISCREG_TSECB_LS_SECURITY_0_G1W_SHIFT)
#define MISCREG_TSECB_LS_SECURITY_0_G1W_RANGE                   9:9
#define MISCREG_TSECB_LS_SECURITY_0_G1W_WOFFSET                 0x0
#define MISCREG_TSECB_LS_SECURITY_0_G1W_DEFAULT                 _MK_MASK_CONST(0x1)
#define MISCREG_TSECB_LS_SECURITY_0_G1W_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define MISCREG_TSECB_LS_SECURITY_0_G1W_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define MISCREG_TSECB_LS_SECURITY_0_G1W_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define MISCREG_TSECB_LS_SECURITY_0_G1W_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define MISCREG_TSECB_LS_SECURITY_0_G1W_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define MISCREG_TSECB_LS_SECURITY_0_G0W_SHIFT                   _MK_SHIFT_CONST(8)
#define MISCREG_TSECB_LS_SECURITY_0_G0W_FIELD                   _MK_FIELD_CONST(0x1, MISCREG_TSECB_LS_SECURITY_0_G0W_SHIFT)
#define MISCREG_TSECB_LS_SECURITY_0_G0W_RANGE                   8:8
#define MISCREG_TSECB_LS_SECURITY_0_G0W_WOFFSET                 0x0
#define MISCREG_TSECB_LS_SECURITY_0_G0W_DEFAULT                 _MK_MASK_CONST(0x1)
#define MISCREG_TSECB_LS_SECURITY_0_G0W_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define MISCREG_TSECB_LS_SECURITY_0_G0W_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define MISCREG_TSECB_LS_SECURITY_0_G0W_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define MISCREG_TSECB_LS_SECURITY_0_G0W_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define MISCREG_TSECB_LS_SECURITY_0_G0W_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define MISCREG_TSECB_LS_SECURITY_0_G7R_SHIFT                   _MK_SHIFT_CONST(7)
#define MISCREG_TSECB_LS_SECURITY_0_G7R_FIELD                   _MK_FIELD_CONST(0x1, MISCREG_TSECB_LS_SECURITY_0_G7R_SHIFT)
#define MISCREG_TSECB_LS_SECURITY_0_G7R_RANGE                   7:7
#define MISCREG_TSECB_LS_SECURITY_0_G7R_WOFFSET                 0x0
#define MISCREG_TSECB_LS_SECURITY_0_G7R_DEFAULT                 _MK_MASK_CONST(0x1)
#define MISCREG_TSECB_LS_SECURITY_0_G7R_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define MISCREG_TSECB_LS_SECURITY_0_G7R_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define MISCREG_TSECB_LS_SECURITY_0_G7R_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define MISCREG_TSECB_LS_SECURITY_0_G7R_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define MISCREG_TSECB_LS_SECURITY_0_G7R_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define MISCREG_TSECB_LS_SECURITY_0_G6R_SHIFT                   _MK_SHIFT_CONST(6)
#define MISCREG_TSECB_LS_SECURITY_0_G6R_FIELD                   _MK_FIELD_CONST(0x1, MISCREG_TSECB_LS_SECURITY_0_G6R_SHIFT)
#define MISCREG_TSECB_LS_SECURITY_0_G6R_RANGE                   6:6
#define MISCREG_TSECB_LS_SECURITY_0_G6R_WOFFSET                 0x0
#define MISCREG_TSECB_LS_SECURITY_0_G6R_DEFAULT                 _MK_MASK_CONST(0x1)
#define MISCREG_TSECB_LS_SECURITY_0_G6R_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define MISCREG_TSECB_LS_SECURITY_0_G6R_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define MISCREG_TSECB_LS_SECURITY_0_G6R_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define MISCREG_TSECB_LS_SECURITY_0_G6R_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define MISCREG_TSECB_LS_SECURITY_0_G6R_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define MISCREG_TSECB_LS_SECURITY_0_G5R_SHIFT                   _MK_SHIFT_CONST(5)
#define MISCREG_TSECB_LS_SECURITY_0_G5R_FIELD                   _MK_FIELD_CONST(0x1, MISCREG_TSECB_LS_SECURITY_0_G5R_SHIFT)
#define MISCREG_TSECB_LS_SECURITY_0_G5R_RANGE                   5:5
#define MISCREG_TSECB_LS_SECURITY_0_G5R_WOFFSET                 0x0
#define MISCREG_TSECB_LS_SECURITY_0_G5R_DEFAULT                 _MK_MASK_CONST(0x1)
#define MISCREG_TSECB_LS_SECURITY_0_G5R_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define MISCREG_TSECB_LS_SECURITY_0_G5R_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define MISCREG_TSECB_LS_SECURITY_0_G5R_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define MISCREG_TSECB_LS_SECURITY_0_G5R_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define MISCREG_TSECB_LS_SECURITY_0_G5R_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define MISCREG_TSECB_LS_SECURITY_0_G4R_SHIFT                   _MK_SHIFT_CONST(4)
#define MISCREG_TSECB_LS_SECURITY_0_G4R_FIELD                   _MK_FIELD_CONST(0x1, MISCREG_TSECB_LS_SECURITY_0_G4R_SHIFT)
#define MISCREG_TSECB_LS_SECURITY_0_G4R_RANGE                   4:4
#define MISCREG_TSECB_LS_SECURITY_0_G4R_WOFFSET                 0x0
#define MISCREG_TSECB_LS_SECURITY_0_G4R_DEFAULT                 _MK_MASK_CONST(0x1)
#define MISCREG_TSECB_LS_SECURITY_0_G4R_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define MISCREG_TSECB_LS_SECURITY_0_G4R_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define MISCREG_TSECB_LS_SECURITY_0_G4R_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define MISCREG_TSECB_LS_SECURITY_0_G4R_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define MISCREG_TSECB_LS_SECURITY_0_G4R_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define MISCREG_TSECB_LS_SECURITY_0_G3R_SHIFT                   _MK_SHIFT_CONST(3)
#define MISCREG_TSECB_LS_SECURITY_0_G3R_FIELD                   _MK_FIELD_CONST(0x1, MISCREG_TSECB_LS_SECURITY_0_G3R_SHIFT)
#define MISCREG_TSECB_LS_SECURITY_0_G3R_RANGE                   3:3
#define MISCREG_TSECB_LS_SECURITY_0_G3R_WOFFSET                 0x0
#define MISCREG_TSECB_LS_SECURITY_0_G3R_DEFAULT                 _MK_MASK_CONST(0x1)
#define MISCREG_TSECB_LS_SECURITY_0_G3R_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define MISCREG_TSECB_LS_SECURITY_0_G3R_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define MISCREG_TSECB_LS_SECURITY_0_G3R_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define MISCREG_TSECB_LS_SECURITY_0_G3R_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define MISCREG_TSECB_LS_SECURITY_0_G3R_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define MISCREG_TSECB_LS_SECURITY_0_G2R_SHIFT                   _MK_SHIFT_CONST(2)
#define MISCREG_TSECB_LS_SECURITY_0_G2R_FIELD                   _MK_FIELD_CONST(0x1, MISCREG_TSECB_LS_SECURITY_0_G2R_SHIFT)
#define MISCREG_TSECB_LS_SECURITY_0_G2R_RANGE                   2:2
#define MISCREG_TSECB_LS_SECURITY_0_G2R_WOFFSET                 0x0
#define MISCREG_TSECB_LS_SECURITY_0_G2R_DEFAULT                 _MK_MASK_CONST(0x1)
#define MISCREG_TSECB_LS_SECURITY_0_G2R_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define MISCREG_TSECB_LS_SECURITY_0_G2R_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define MISCREG_TSECB_LS_SECURITY_0_G2R_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define MISCREG_TSECB_LS_SECURITY_0_G2R_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define MISCREG_TSECB_LS_SECURITY_0_G2R_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define MISCREG_TSECB_LS_SECURITY_0_G1R_SHIFT                   _MK_SHIFT_CONST(1)
#define MISCREG_TSECB_LS_SECURITY_0_G1R_FIELD                   _MK_FIELD_CONST(0x1, MISCREG_TSECB_LS_SECURITY_0_G1R_SHIFT)
#define MISCREG_TSECB_LS_SECURITY_0_G1R_RANGE                   1:1
#define MISCREG_TSECB_LS_SECURITY_0_G1R_WOFFSET                 0x0
#define MISCREG_TSECB_LS_SECURITY_0_G1R_DEFAULT                 _MK_MASK_CONST(0x1)
#define MISCREG_TSECB_LS_SECURITY_0_G1R_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define MISCREG_TSECB_LS_SECURITY_0_G1R_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define MISCREG_TSECB_LS_SECURITY_0_G1R_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define MISCREG_TSECB_LS_SECURITY_0_G1R_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define MISCREG_TSECB_LS_SECURITY_0_G1R_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define MISCREG_TSECB_LS_SECURITY_0_G0R_SHIFT                   _MK_SHIFT_CONST(0)
#define MISCREG_TSECB_LS_SECURITY_0_G0R_FIELD                   _MK_FIELD_CONST(0x1, MISCREG_TSECB_LS_SECURITY_0_G0R_SHIFT)
#define MISCREG_TSECB_LS_SECURITY_0_G0R_RANGE                   0:0
#define MISCREG_TSECB_LS_SECURITY_0_G0R_WOFFSET                 0x0
#define MISCREG_TSECB_LS_SECURITY_0_G0R_DEFAULT                 _MK_MASK_CONST(0x1)
#define MISCREG_TSECB_LS_SECURITY_0_G0R_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define MISCREG_TSECB_LS_SECURITY_0_G0R_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define MISCREG_TSECB_LS_SECURITY_0_G0R_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define MISCREG_TSECB_LS_SECURITY_0_G0R_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define MISCREG_TSECB_LS_SECURITY_0_G0R_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)


// Register MISCREG_JTAGM_SECURITY_0
#define MISCREG_JTAGM_SECURITY_0                        _MK_ADDR_CONST(0x102c)
#define MISCREG_JTAGM_SECURITY_0_SECURE                         0x0
#define MISCREG_JTAGM_SECURITY_0_DUAL                   0x0
#define MISCREG_JTAGM_SECURITY_0_SCR                    SCRJTAG_0
#define MISCREG_JTAGM_SECURITY_0_WORD_COUNT                     0x1
#define MISCREG_JTAGM_SECURITY_0_RESET_VAL                      _MK_MASK_CONST(0x9ffff)
#define MISCREG_JTAGM_SECURITY_0_RESET_MASK                     _MK_MASK_CONST(0xfffff)
#define MISCREG_JTAGM_SECURITY_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define MISCREG_JTAGM_SECURITY_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define MISCREG_JTAGM_SECURITY_0_READ_MASK                      _MK_MASK_CONST(0xfffff)
#define MISCREG_JTAGM_SECURITY_0_WRITE_MASK                     _MK_MASK_CONST(0xffff)
#define MISCREG_JTAGM_SECURITY_0_MSTR_ID_SHIFT                  _MK_SHIFT_CONST(16)
#define MISCREG_JTAGM_SECURITY_0_MSTR_ID_FIELD                  _MK_FIELD_CONST(0xf, MISCREG_JTAGM_SECURITY_0_MSTR_ID_SHIFT)
#define MISCREG_JTAGM_SECURITY_0_MSTR_ID_RANGE                  19:16
#define MISCREG_JTAGM_SECURITY_0_MSTR_ID_WOFFSET                        0x0
#define MISCREG_JTAGM_SECURITY_0_MSTR_ID_DEFAULT                        _MK_MASK_CONST(0x9)
#define MISCREG_JTAGM_SECURITY_0_MSTR_ID_DEFAULT_MASK                   _MK_MASK_CONST(0xf)
#define MISCREG_JTAGM_SECURITY_0_MSTR_ID_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define MISCREG_JTAGM_SECURITY_0_MSTR_ID_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define MISCREG_JTAGM_SECURITY_0_MSTR_ID_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define MISCREG_JTAGM_SECURITY_0_MSTR_ID_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define MISCREG_JTAGM_SECURITY_0_MSTR_ID_CCPLEX                 _MK_ENUM_CONST(1)
#define MISCREG_JTAGM_SECURITY_0_MSTR_ID_CCPLEX_DPMU                    _MK_ENUM_CONST(2)
#define MISCREG_JTAGM_SECURITY_0_MSTR_ID_BPMP                   _MK_ENUM_CONST(3)
#define MISCREG_JTAGM_SECURITY_0_MSTR_ID_SPE                    _MK_ENUM_CONST(4)
#define MISCREG_JTAGM_SECURITY_0_MSTR_ID_SCE                    _MK_ENUM_CONST(5)
#define MISCREG_JTAGM_SECURITY_0_MSTR_ID_DMA_PER                        _MK_ENUM_CONST(6)
#define MISCREG_JTAGM_SECURITY_0_MSTR_ID_TSECA                  _MK_ENUM_CONST(7)
#define MISCREG_JTAGM_SECURITY_0_MSTR_ID_TSECB                  _MK_ENUM_CONST(8)
#define MISCREG_JTAGM_SECURITY_0_MSTR_ID_JTAGM                  _MK_ENUM_CONST(9)
#define MISCREG_JTAGM_SECURITY_0_MSTR_ID_CSITE                  _MK_ENUM_CONST(10)
#define MISCREG_JTAGM_SECURITY_0_MSTR_ID_APE                    _MK_ENUM_CONST(11)
#define MISCREG_JTAGM_SECURITY_0_MSTR_ID_Peatrans                       _MK_ENUM_CONST(12)
#define MISCREG_JTAGM_SECURITY_0_MSTR_ID_NVDEC                  _MK_ENUM_CONST(13)
#define MISCREG_JTAGM_SECURITY_0_MSTR_ID_RCE                    _MK_ENUM_CONST(14)
#define MISCREG_JTAGM_SECURITY_0_MSTR_ID_NVDEC1                 _MK_ENUM_CONST(15)

#define MISCREG_JTAGM_SECURITY_0_G7W_SHIFT                      _MK_SHIFT_CONST(15)
#define MISCREG_JTAGM_SECURITY_0_G7W_FIELD                      _MK_FIELD_CONST(0x1, MISCREG_JTAGM_SECURITY_0_G7W_SHIFT)
#define MISCREG_JTAGM_SECURITY_0_G7W_RANGE                      15:15
#define MISCREG_JTAGM_SECURITY_0_G7W_WOFFSET                    0x0
#define MISCREG_JTAGM_SECURITY_0_G7W_DEFAULT                    _MK_MASK_CONST(0x1)
#define MISCREG_JTAGM_SECURITY_0_G7W_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define MISCREG_JTAGM_SECURITY_0_G7W_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define MISCREG_JTAGM_SECURITY_0_G7W_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define MISCREG_JTAGM_SECURITY_0_G7W_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define MISCREG_JTAGM_SECURITY_0_G7W_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)

#define MISCREG_JTAGM_SECURITY_0_G6W_SHIFT                      _MK_SHIFT_CONST(14)
#define MISCREG_JTAGM_SECURITY_0_G6W_FIELD                      _MK_FIELD_CONST(0x1, MISCREG_JTAGM_SECURITY_0_G6W_SHIFT)
#define MISCREG_JTAGM_SECURITY_0_G6W_RANGE                      14:14
#define MISCREG_JTAGM_SECURITY_0_G6W_WOFFSET                    0x0
#define MISCREG_JTAGM_SECURITY_0_G6W_DEFAULT                    _MK_MASK_CONST(0x1)
#define MISCREG_JTAGM_SECURITY_0_G6W_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define MISCREG_JTAGM_SECURITY_0_G6W_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define MISCREG_JTAGM_SECURITY_0_G6W_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define MISCREG_JTAGM_SECURITY_0_G6W_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define MISCREG_JTAGM_SECURITY_0_G6W_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)

#define MISCREG_JTAGM_SECURITY_0_G5W_SHIFT                      _MK_SHIFT_CONST(13)
#define MISCREG_JTAGM_SECURITY_0_G5W_FIELD                      _MK_FIELD_CONST(0x1, MISCREG_JTAGM_SECURITY_0_G5W_SHIFT)
#define MISCREG_JTAGM_SECURITY_0_G5W_RANGE                      13:13
#define MISCREG_JTAGM_SECURITY_0_G5W_WOFFSET                    0x0
#define MISCREG_JTAGM_SECURITY_0_G5W_DEFAULT                    _MK_MASK_CONST(0x1)
#define MISCREG_JTAGM_SECURITY_0_G5W_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define MISCREG_JTAGM_SECURITY_0_G5W_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define MISCREG_JTAGM_SECURITY_0_G5W_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define MISCREG_JTAGM_SECURITY_0_G5W_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define MISCREG_JTAGM_SECURITY_0_G5W_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)

#define MISCREG_JTAGM_SECURITY_0_G4W_SHIFT                      _MK_SHIFT_CONST(12)
#define MISCREG_JTAGM_SECURITY_0_G4W_FIELD                      _MK_FIELD_CONST(0x1, MISCREG_JTAGM_SECURITY_0_G4W_SHIFT)
#define MISCREG_JTAGM_SECURITY_0_G4W_RANGE                      12:12
#define MISCREG_JTAGM_SECURITY_0_G4W_WOFFSET                    0x0
#define MISCREG_JTAGM_SECURITY_0_G4W_DEFAULT                    _MK_MASK_CONST(0x1)
#define MISCREG_JTAGM_SECURITY_0_G4W_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define MISCREG_JTAGM_SECURITY_0_G4W_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define MISCREG_JTAGM_SECURITY_0_G4W_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define MISCREG_JTAGM_SECURITY_0_G4W_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define MISCREG_JTAGM_SECURITY_0_G4W_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)

#define MISCREG_JTAGM_SECURITY_0_G3W_SHIFT                      _MK_SHIFT_CONST(11)
#define MISCREG_JTAGM_SECURITY_0_G3W_FIELD                      _MK_FIELD_CONST(0x1, MISCREG_JTAGM_SECURITY_0_G3W_SHIFT)
#define MISCREG_JTAGM_SECURITY_0_G3W_RANGE                      11:11
#define MISCREG_JTAGM_SECURITY_0_G3W_WOFFSET                    0x0
#define MISCREG_JTAGM_SECURITY_0_G3W_DEFAULT                    _MK_MASK_CONST(0x1)
#define MISCREG_JTAGM_SECURITY_0_G3W_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define MISCREG_JTAGM_SECURITY_0_G3W_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define MISCREG_JTAGM_SECURITY_0_G3W_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define MISCREG_JTAGM_SECURITY_0_G3W_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define MISCREG_JTAGM_SECURITY_0_G3W_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)

#define MISCREG_JTAGM_SECURITY_0_G2W_SHIFT                      _MK_SHIFT_CONST(10)
#define MISCREG_JTAGM_SECURITY_0_G2W_FIELD                      _MK_FIELD_CONST(0x1, MISCREG_JTAGM_SECURITY_0_G2W_SHIFT)
#define MISCREG_JTAGM_SECURITY_0_G2W_RANGE                      10:10
#define MISCREG_JTAGM_SECURITY_0_G2W_WOFFSET                    0x0
#define MISCREG_JTAGM_SECURITY_0_G2W_DEFAULT                    _MK_MASK_CONST(0x1)
#define MISCREG_JTAGM_SECURITY_0_G2W_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define MISCREG_JTAGM_SECURITY_0_G2W_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define MISCREG_JTAGM_SECURITY_0_G2W_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define MISCREG_JTAGM_SECURITY_0_G2W_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define MISCREG_JTAGM_SECURITY_0_G2W_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)

#define MISCREG_JTAGM_SECURITY_0_G1W_SHIFT                      _MK_SHIFT_CONST(9)
#define MISCREG_JTAGM_SECURITY_0_G1W_FIELD                      _MK_FIELD_CONST(0x1, MISCREG_JTAGM_SECURITY_0_G1W_SHIFT)
#define MISCREG_JTAGM_SECURITY_0_G1W_RANGE                      9:9
#define MISCREG_JTAGM_SECURITY_0_G1W_WOFFSET                    0x0
#define MISCREG_JTAGM_SECURITY_0_G1W_DEFAULT                    _MK_MASK_CONST(0x1)
#define MISCREG_JTAGM_SECURITY_0_G1W_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define MISCREG_JTAGM_SECURITY_0_G1W_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define MISCREG_JTAGM_SECURITY_0_G1W_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define MISCREG_JTAGM_SECURITY_0_G1W_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define MISCREG_JTAGM_SECURITY_0_G1W_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)

#define MISCREG_JTAGM_SECURITY_0_G0W_SHIFT                      _MK_SHIFT_CONST(8)
#define MISCREG_JTAGM_SECURITY_0_G0W_FIELD                      _MK_FIELD_CONST(0x1, MISCREG_JTAGM_SECURITY_0_G0W_SHIFT)
#define MISCREG_JTAGM_SECURITY_0_G0W_RANGE                      8:8
#define MISCREG_JTAGM_SECURITY_0_G0W_WOFFSET                    0x0
#define MISCREG_JTAGM_SECURITY_0_G0W_DEFAULT                    _MK_MASK_CONST(0x1)
#define MISCREG_JTAGM_SECURITY_0_G0W_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define MISCREG_JTAGM_SECURITY_0_G0W_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define MISCREG_JTAGM_SECURITY_0_G0W_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define MISCREG_JTAGM_SECURITY_0_G0W_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define MISCREG_JTAGM_SECURITY_0_G0W_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)

#define MISCREG_JTAGM_SECURITY_0_G7R_SHIFT                      _MK_SHIFT_CONST(7)
#define MISCREG_JTAGM_SECURITY_0_G7R_FIELD                      _MK_FIELD_CONST(0x1, MISCREG_JTAGM_SECURITY_0_G7R_SHIFT)
#define MISCREG_JTAGM_SECURITY_0_G7R_RANGE                      7:7
#define MISCREG_JTAGM_SECURITY_0_G7R_WOFFSET                    0x0
#define MISCREG_JTAGM_SECURITY_0_G7R_DEFAULT                    _MK_MASK_CONST(0x1)
#define MISCREG_JTAGM_SECURITY_0_G7R_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define MISCREG_JTAGM_SECURITY_0_G7R_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define MISCREG_JTAGM_SECURITY_0_G7R_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define MISCREG_JTAGM_SECURITY_0_G7R_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define MISCREG_JTAGM_SECURITY_0_G7R_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)

#define MISCREG_JTAGM_SECURITY_0_G6R_SHIFT                      _MK_SHIFT_CONST(6)
#define MISCREG_JTAGM_SECURITY_0_G6R_FIELD                      _MK_FIELD_CONST(0x1, MISCREG_JTAGM_SECURITY_0_G6R_SHIFT)
#define MISCREG_JTAGM_SECURITY_0_G6R_RANGE                      6:6
#define MISCREG_JTAGM_SECURITY_0_G6R_WOFFSET                    0x0
#define MISCREG_JTAGM_SECURITY_0_G6R_DEFAULT                    _MK_MASK_CONST(0x1)
#define MISCREG_JTAGM_SECURITY_0_G6R_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define MISCREG_JTAGM_SECURITY_0_G6R_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define MISCREG_JTAGM_SECURITY_0_G6R_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define MISCREG_JTAGM_SECURITY_0_G6R_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define MISCREG_JTAGM_SECURITY_0_G6R_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)

#define MISCREG_JTAGM_SECURITY_0_G5R_SHIFT                      _MK_SHIFT_CONST(5)
#define MISCREG_JTAGM_SECURITY_0_G5R_FIELD                      _MK_FIELD_CONST(0x1, MISCREG_JTAGM_SECURITY_0_G5R_SHIFT)
#define MISCREG_JTAGM_SECURITY_0_G5R_RANGE                      5:5
#define MISCREG_JTAGM_SECURITY_0_G5R_WOFFSET                    0x0
#define MISCREG_JTAGM_SECURITY_0_G5R_DEFAULT                    _MK_MASK_CONST(0x1)
#define MISCREG_JTAGM_SECURITY_0_G5R_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define MISCREG_JTAGM_SECURITY_0_G5R_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define MISCREG_JTAGM_SECURITY_0_G5R_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define MISCREG_JTAGM_SECURITY_0_G5R_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define MISCREG_JTAGM_SECURITY_0_G5R_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)

#define MISCREG_JTAGM_SECURITY_0_G4R_SHIFT                      _MK_SHIFT_CONST(4)
#define MISCREG_JTAGM_SECURITY_0_G4R_FIELD                      _MK_FIELD_CONST(0x1, MISCREG_JTAGM_SECURITY_0_G4R_SHIFT)
#define MISCREG_JTAGM_SECURITY_0_G4R_RANGE                      4:4
#define MISCREG_JTAGM_SECURITY_0_G4R_WOFFSET                    0x0
#define MISCREG_JTAGM_SECURITY_0_G4R_DEFAULT                    _MK_MASK_CONST(0x1)
#define MISCREG_JTAGM_SECURITY_0_G4R_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define MISCREG_JTAGM_SECURITY_0_G4R_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define MISCREG_JTAGM_SECURITY_0_G4R_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define MISCREG_JTAGM_SECURITY_0_G4R_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define MISCREG_JTAGM_SECURITY_0_G4R_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)

#define MISCREG_JTAGM_SECURITY_0_G3R_SHIFT                      _MK_SHIFT_CONST(3)
#define MISCREG_JTAGM_SECURITY_0_G3R_FIELD                      _MK_FIELD_CONST(0x1, MISCREG_JTAGM_SECURITY_0_G3R_SHIFT)
#define MISCREG_JTAGM_SECURITY_0_G3R_RANGE                      3:3
#define MISCREG_JTAGM_SECURITY_0_G3R_WOFFSET                    0x0
#define MISCREG_JTAGM_SECURITY_0_G3R_DEFAULT                    _MK_MASK_CONST(0x1)
#define MISCREG_JTAGM_SECURITY_0_G3R_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define MISCREG_JTAGM_SECURITY_0_G3R_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define MISCREG_JTAGM_SECURITY_0_G3R_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define MISCREG_JTAGM_SECURITY_0_G3R_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define MISCREG_JTAGM_SECURITY_0_G3R_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)

#define MISCREG_JTAGM_SECURITY_0_G2R_SHIFT                      _MK_SHIFT_CONST(2)
#define MISCREG_JTAGM_SECURITY_0_G2R_FIELD                      _MK_FIELD_CONST(0x1, MISCREG_JTAGM_SECURITY_0_G2R_SHIFT)
#define MISCREG_JTAGM_SECURITY_0_G2R_RANGE                      2:2
#define MISCREG_JTAGM_SECURITY_0_G2R_WOFFSET                    0x0
#define MISCREG_JTAGM_SECURITY_0_G2R_DEFAULT                    _MK_MASK_CONST(0x1)
#define MISCREG_JTAGM_SECURITY_0_G2R_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define MISCREG_JTAGM_SECURITY_0_G2R_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define MISCREG_JTAGM_SECURITY_0_G2R_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define MISCREG_JTAGM_SECURITY_0_G2R_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define MISCREG_JTAGM_SECURITY_0_G2R_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)

#define MISCREG_JTAGM_SECURITY_0_G1R_SHIFT                      _MK_SHIFT_CONST(1)
#define MISCREG_JTAGM_SECURITY_0_G1R_FIELD                      _MK_FIELD_CONST(0x1, MISCREG_JTAGM_SECURITY_0_G1R_SHIFT)
#define MISCREG_JTAGM_SECURITY_0_G1R_RANGE                      1:1
#define MISCREG_JTAGM_SECURITY_0_G1R_WOFFSET                    0x0
#define MISCREG_JTAGM_SECURITY_0_G1R_DEFAULT                    _MK_MASK_CONST(0x1)
#define MISCREG_JTAGM_SECURITY_0_G1R_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define MISCREG_JTAGM_SECURITY_0_G1R_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define MISCREG_JTAGM_SECURITY_0_G1R_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define MISCREG_JTAGM_SECURITY_0_G1R_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define MISCREG_JTAGM_SECURITY_0_G1R_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)

#define MISCREG_JTAGM_SECURITY_0_G0R_SHIFT                      _MK_SHIFT_CONST(0)
#define MISCREG_JTAGM_SECURITY_0_G0R_FIELD                      _MK_FIELD_CONST(0x1, MISCREG_JTAGM_SECURITY_0_G0R_SHIFT)
#define MISCREG_JTAGM_SECURITY_0_G0R_RANGE                      0:0
#define MISCREG_JTAGM_SECURITY_0_G0R_WOFFSET                    0x0
#define MISCREG_JTAGM_SECURITY_0_G0R_DEFAULT                    _MK_MASK_CONST(0x1)
#define MISCREG_JTAGM_SECURITY_0_G0R_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define MISCREG_JTAGM_SECURITY_0_G0R_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define MISCREG_JTAGM_SECURITY_0_G0R_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define MISCREG_JTAGM_SECURITY_0_G0R_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define MISCREG_JTAGM_SECURITY_0_G0R_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)


// Register MISCREG_CSITE_SECURITY_0
#define MISCREG_CSITE_SECURITY_0                        _MK_ADDR_CONST(0x1030)
#define MISCREG_CSITE_SECURITY_0_SECURE                         0x0
#define MISCREG_CSITE_SECURITY_0_DUAL                   0x0
#define MISCREG_CSITE_SECURITY_0_SCR                    SCRCSITE_0
#define MISCREG_CSITE_SECURITY_0_WORD_COUNT                     0x1
#define MISCREG_CSITE_SECURITY_0_RESET_VAL                      _MK_MASK_CONST(0xaffff)
#define MISCREG_CSITE_SECURITY_0_RESET_MASK                     _MK_MASK_CONST(0xfffff)
#define MISCREG_CSITE_SECURITY_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define MISCREG_CSITE_SECURITY_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define MISCREG_CSITE_SECURITY_0_READ_MASK                      _MK_MASK_CONST(0xfffff)
#define MISCREG_CSITE_SECURITY_0_WRITE_MASK                     _MK_MASK_CONST(0xffff)
#define MISCREG_CSITE_SECURITY_0_MSTR_ID_SHIFT                  _MK_SHIFT_CONST(16)
#define MISCREG_CSITE_SECURITY_0_MSTR_ID_FIELD                  _MK_FIELD_CONST(0xf, MISCREG_CSITE_SECURITY_0_MSTR_ID_SHIFT)
#define MISCREG_CSITE_SECURITY_0_MSTR_ID_RANGE                  19:16
#define MISCREG_CSITE_SECURITY_0_MSTR_ID_WOFFSET                        0x0
#define MISCREG_CSITE_SECURITY_0_MSTR_ID_DEFAULT                        _MK_MASK_CONST(0xa)
#define MISCREG_CSITE_SECURITY_0_MSTR_ID_DEFAULT_MASK                   _MK_MASK_CONST(0xf)
#define MISCREG_CSITE_SECURITY_0_MSTR_ID_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define MISCREG_CSITE_SECURITY_0_MSTR_ID_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define MISCREG_CSITE_SECURITY_0_MSTR_ID_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define MISCREG_CSITE_SECURITY_0_MSTR_ID_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define MISCREG_CSITE_SECURITY_0_MSTR_ID_CCPLEX                 _MK_ENUM_CONST(1)
#define MISCREG_CSITE_SECURITY_0_MSTR_ID_CCPLEX_DPMU                    _MK_ENUM_CONST(2)
#define MISCREG_CSITE_SECURITY_0_MSTR_ID_BPMP                   _MK_ENUM_CONST(3)
#define MISCREG_CSITE_SECURITY_0_MSTR_ID_SPE                    _MK_ENUM_CONST(4)
#define MISCREG_CSITE_SECURITY_0_MSTR_ID_SCE                    _MK_ENUM_CONST(5)
#define MISCREG_CSITE_SECURITY_0_MSTR_ID_DMA_PER                        _MK_ENUM_CONST(6)
#define MISCREG_CSITE_SECURITY_0_MSTR_ID_TSECA                  _MK_ENUM_CONST(7)
#define MISCREG_CSITE_SECURITY_0_MSTR_ID_TSECB                  _MK_ENUM_CONST(8)
#define MISCREG_CSITE_SECURITY_0_MSTR_ID_JTAGM                  _MK_ENUM_CONST(9)
#define MISCREG_CSITE_SECURITY_0_MSTR_ID_CSITE                  _MK_ENUM_CONST(10)
#define MISCREG_CSITE_SECURITY_0_MSTR_ID_APE                    _MK_ENUM_CONST(11)
#define MISCREG_CSITE_SECURITY_0_MSTR_ID_Peatrans                       _MK_ENUM_CONST(12)
#define MISCREG_CSITE_SECURITY_0_MSTR_ID_NVDEC                  _MK_ENUM_CONST(13)
#define MISCREG_CSITE_SECURITY_0_MSTR_ID_RCE                    _MK_ENUM_CONST(14)
#define MISCREG_CSITE_SECURITY_0_MSTR_ID_NVDEC1                 _MK_ENUM_CONST(15)

#define MISCREG_CSITE_SECURITY_0_G7W_SHIFT                      _MK_SHIFT_CONST(15)
#define MISCREG_CSITE_SECURITY_0_G7W_FIELD                      _MK_FIELD_CONST(0x1, MISCREG_CSITE_SECURITY_0_G7W_SHIFT)
#define MISCREG_CSITE_SECURITY_0_G7W_RANGE                      15:15
#define MISCREG_CSITE_SECURITY_0_G7W_WOFFSET                    0x0
#define MISCREG_CSITE_SECURITY_0_G7W_DEFAULT                    _MK_MASK_CONST(0x1)
#define MISCREG_CSITE_SECURITY_0_G7W_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define MISCREG_CSITE_SECURITY_0_G7W_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define MISCREG_CSITE_SECURITY_0_G7W_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define MISCREG_CSITE_SECURITY_0_G7W_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define MISCREG_CSITE_SECURITY_0_G7W_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)

#define MISCREG_CSITE_SECURITY_0_G6W_SHIFT                      _MK_SHIFT_CONST(14)
#define MISCREG_CSITE_SECURITY_0_G6W_FIELD                      _MK_FIELD_CONST(0x1, MISCREG_CSITE_SECURITY_0_G6W_SHIFT)
#define MISCREG_CSITE_SECURITY_0_G6W_RANGE                      14:14
#define MISCREG_CSITE_SECURITY_0_G6W_WOFFSET                    0x0
#define MISCREG_CSITE_SECURITY_0_G6W_DEFAULT                    _MK_MASK_CONST(0x1)
#define MISCREG_CSITE_SECURITY_0_G6W_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define MISCREG_CSITE_SECURITY_0_G6W_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define MISCREG_CSITE_SECURITY_0_G6W_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define MISCREG_CSITE_SECURITY_0_G6W_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define MISCREG_CSITE_SECURITY_0_G6W_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)

#define MISCREG_CSITE_SECURITY_0_G5W_SHIFT                      _MK_SHIFT_CONST(13)
#define MISCREG_CSITE_SECURITY_0_G5W_FIELD                      _MK_FIELD_CONST(0x1, MISCREG_CSITE_SECURITY_0_G5W_SHIFT)
#define MISCREG_CSITE_SECURITY_0_G5W_RANGE                      13:13
#define MISCREG_CSITE_SECURITY_0_G5W_WOFFSET                    0x0
#define MISCREG_CSITE_SECURITY_0_G5W_DEFAULT                    _MK_MASK_CONST(0x1)
#define MISCREG_CSITE_SECURITY_0_G5W_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define MISCREG_CSITE_SECURITY_0_G5W_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define MISCREG_CSITE_SECURITY_0_G5W_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define MISCREG_CSITE_SECURITY_0_G5W_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define MISCREG_CSITE_SECURITY_0_G5W_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)

#define MISCREG_CSITE_SECURITY_0_G4W_SHIFT                      _MK_SHIFT_CONST(12)
#define MISCREG_CSITE_SECURITY_0_G4W_FIELD                      _MK_FIELD_CONST(0x1, MISCREG_CSITE_SECURITY_0_G4W_SHIFT)
#define MISCREG_CSITE_SECURITY_0_G4W_RANGE                      12:12
#define MISCREG_CSITE_SECURITY_0_G4W_WOFFSET                    0x0
#define MISCREG_CSITE_SECURITY_0_G4W_DEFAULT                    _MK_MASK_CONST(0x1)
#define MISCREG_CSITE_SECURITY_0_G4W_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define MISCREG_CSITE_SECURITY_0_G4W_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define MISCREG_CSITE_SECURITY_0_G4W_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define MISCREG_CSITE_SECURITY_0_G4W_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define MISCREG_CSITE_SECURITY_0_G4W_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)

#define MISCREG_CSITE_SECURITY_0_G3W_SHIFT                      _MK_SHIFT_CONST(11)
#define MISCREG_CSITE_SECURITY_0_G3W_FIELD                      _MK_FIELD_CONST(0x1, MISCREG_CSITE_SECURITY_0_G3W_SHIFT)
#define MISCREG_CSITE_SECURITY_0_G3W_RANGE                      11:11
#define MISCREG_CSITE_SECURITY_0_G3W_WOFFSET                    0x0
#define MISCREG_CSITE_SECURITY_0_G3W_DEFAULT                    _MK_MASK_CONST(0x1)
#define MISCREG_CSITE_SECURITY_0_G3W_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define MISCREG_CSITE_SECURITY_0_G3W_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define MISCREG_CSITE_SECURITY_0_G3W_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define MISCREG_CSITE_SECURITY_0_G3W_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define MISCREG_CSITE_SECURITY_0_G3W_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)

#define MISCREG_CSITE_SECURITY_0_G2W_SHIFT                      _MK_SHIFT_CONST(10)
#define MISCREG_CSITE_SECURITY_0_G2W_FIELD                      _MK_FIELD_CONST(0x1, MISCREG_CSITE_SECURITY_0_G2W_SHIFT)
#define MISCREG_CSITE_SECURITY_0_G2W_RANGE                      10:10
#define MISCREG_CSITE_SECURITY_0_G2W_WOFFSET                    0x0
#define MISCREG_CSITE_SECURITY_0_G2W_DEFAULT                    _MK_MASK_CONST(0x1)
#define MISCREG_CSITE_SECURITY_0_G2W_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define MISCREG_CSITE_SECURITY_0_G2W_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define MISCREG_CSITE_SECURITY_0_G2W_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define MISCREG_CSITE_SECURITY_0_G2W_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define MISCREG_CSITE_SECURITY_0_G2W_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)

#define MISCREG_CSITE_SECURITY_0_G1W_SHIFT                      _MK_SHIFT_CONST(9)
#define MISCREG_CSITE_SECURITY_0_G1W_FIELD                      _MK_FIELD_CONST(0x1, MISCREG_CSITE_SECURITY_0_G1W_SHIFT)
#define MISCREG_CSITE_SECURITY_0_G1W_RANGE                      9:9
#define MISCREG_CSITE_SECURITY_0_G1W_WOFFSET                    0x0
#define MISCREG_CSITE_SECURITY_0_G1W_DEFAULT                    _MK_MASK_CONST(0x1)
#define MISCREG_CSITE_SECURITY_0_G1W_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define MISCREG_CSITE_SECURITY_0_G1W_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define MISCREG_CSITE_SECURITY_0_G1W_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define MISCREG_CSITE_SECURITY_0_G1W_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define MISCREG_CSITE_SECURITY_0_G1W_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)

#define MISCREG_CSITE_SECURITY_0_G0W_SHIFT                      _MK_SHIFT_CONST(8)
#define MISCREG_CSITE_SECURITY_0_G0W_FIELD                      _MK_FIELD_CONST(0x1, MISCREG_CSITE_SECURITY_0_G0W_SHIFT)
#define MISCREG_CSITE_SECURITY_0_G0W_RANGE                      8:8
#define MISCREG_CSITE_SECURITY_0_G0W_WOFFSET                    0x0
#define MISCREG_CSITE_SECURITY_0_G0W_DEFAULT                    _MK_MASK_CONST(0x1)
#define MISCREG_CSITE_SECURITY_0_G0W_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define MISCREG_CSITE_SECURITY_0_G0W_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define MISCREG_CSITE_SECURITY_0_G0W_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define MISCREG_CSITE_SECURITY_0_G0W_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define MISCREG_CSITE_SECURITY_0_G0W_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)

#define MISCREG_CSITE_SECURITY_0_G7R_SHIFT                      _MK_SHIFT_CONST(7)
#define MISCREG_CSITE_SECURITY_0_G7R_FIELD                      _MK_FIELD_CONST(0x1, MISCREG_CSITE_SECURITY_0_G7R_SHIFT)
#define MISCREG_CSITE_SECURITY_0_G7R_RANGE                      7:7
#define MISCREG_CSITE_SECURITY_0_G7R_WOFFSET                    0x0
#define MISCREG_CSITE_SECURITY_0_G7R_DEFAULT                    _MK_MASK_CONST(0x1)
#define MISCREG_CSITE_SECURITY_0_G7R_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define MISCREG_CSITE_SECURITY_0_G7R_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define MISCREG_CSITE_SECURITY_0_G7R_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define MISCREG_CSITE_SECURITY_0_G7R_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define MISCREG_CSITE_SECURITY_0_G7R_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)

#define MISCREG_CSITE_SECURITY_0_G6R_SHIFT                      _MK_SHIFT_CONST(6)
#define MISCREG_CSITE_SECURITY_0_G6R_FIELD                      _MK_FIELD_CONST(0x1, MISCREG_CSITE_SECURITY_0_G6R_SHIFT)
#define MISCREG_CSITE_SECURITY_0_G6R_RANGE                      6:6
#define MISCREG_CSITE_SECURITY_0_G6R_WOFFSET                    0x0
#define MISCREG_CSITE_SECURITY_0_G6R_DEFAULT                    _MK_MASK_CONST(0x1)
#define MISCREG_CSITE_SECURITY_0_G6R_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define MISCREG_CSITE_SECURITY_0_G6R_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define MISCREG_CSITE_SECURITY_0_G6R_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define MISCREG_CSITE_SECURITY_0_G6R_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define MISCREG_CSITE_SECURITY_0_G6R_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)

#define MISCREG_CSITE_SECURITY_0_G5R_SHIFT                      _MK_SHIFT_CONST(5)
#define MISCREG_CSITE_SECURITY_0_G5R_FIELD                      _MK_FIELD_CONST(0x1, MISCREG_CSITE_SECURITY_0_G5R_SHIFT)
#define MISCREG_CSITE_SECURITY_0_G5R_RANGE                      5:5
#define MISCREG_CSITE_SECURITY_0_G5R_WOFFSET                    0x0
#define MISCREG_CSITE_SECURITY_0_G5R_DEFAULT                    _MK_MASK_CONST(0x1)
#define MISCREG_CSITE_SECURITY_0_G5R_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define MISCREG_CSITE_SECURITY_0_G5R_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define MISCREG_CSITE_SECURITY_0_G5R_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define MISCREG_CSITE_SECURITY_0_G5R_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define MISCREG_CSITE_SECURITY_0_G5R_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)

#define MISCREG_CSITE_SECURITY_0_G4R_SHIFT                      _MK_SHIFT_CONST(4)
#define MISCREG_CSITE_SECURITY_0_G4R_FIELD                      _MK_FIELD_CONST(0x1, MISCREG_CSITE_SECURITY_0_G4R_SHIFT)
#define MISCREG_CSITE_SECURITY_0_G4R_RANGE                      4:4
#define MISCREG_CSITE_SECURITY_0_G4R_WOFFSET                    0x0
#define MISCREG_CSITE_SECURITY_0_G4R_DEFAULT                    _MK_MASK_CONST(0x1)
#define MISCREG_CSITE_SECURITY_0_G4R_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define MISCREG_CSITE_SECURITY_0_G4R_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define MISCREG_CSITE_SECURITY_0_G4R_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define MISCREG_CSITE_SECURITY_0_G4R_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define MISCREG_CSITE_SECURITY_0_G4R_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)

#define MISCREG_CSITE_SECURITY_0_G3R_SHIFT                      _MK_SHIFT_CONST(3)
#define MISCREG_CSITE_SECURITY_0_G3R_FIELD                      _MK_FIELD_CONST(0x1, MISCREG_CSITE_SECURITY_0_G3R_SHIFT)
#define MISCREG_CSITE_SECURITY_0_G3R_RANGE                      3:3
#define MISCREG_CSITE_SECURITY_0_G3R_WOFFSET                    0x0
#define MISCREG_CSITE_SECURITY_0_G3R_DEFAULT                    _MK_MASK_CONST(0x1)
#define MISCREG_CSITE_SECURITY_0_G3R_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define MISCREG_CSITE_SECURITY_0_G3R_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define MISCREG_CSITE_SECURITY_0_G3R_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define MISCREG_CSITE_SECURITY_0_G3R_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define MISCREG_CSITE_SECURITY_0_G3R_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)

#define MISCREG_CSITE_SECURITY_0_G2R_SHIFT                      _MK_SHIFT_CONST(2)
#define MISCREG_CSITE_SECURITY_0_G2R_FIELD                      _MK_FIELD_CONST(0x1, MISCREG_CSITE_SECURITY_0_G2R_SHIFT)
#define MISCREG_CSITE_SECURITY_0_G2R_RANGE                      2:2
#define MISCREG_CSITE_SECURITY_0_G2R_WOFFSET                    0x0
#define MISCREG_CSITE_SECURITY_0_G2R_DEFAULT                    _MK_MASK_CONST(0x1)
#define MISCREG_CSITE_SECURITY_0_G2R_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define MISCREG_CSITE_SECURITY_0_G2R_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define MISCREG_CSITE_SECURITY_0_G2R_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define MISCREG_CSITE_SECURITY_0_G2R_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define MISCREG_CSITE_SECURITY_0_G2R_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)

#define MISCREG_CSITE_SECURITY_0_G1R_SHIFT                      _MK_SHIFT_CONST(1)
#define MISCREG_CSITE_SECURITY_0_G1R_FIELD                      _MK_FIELD_CONST(0x1, MISCREG_CSITE_SECURITY_0_G1R_SHIFT)
#define MISCREG_CSITE_SECURITY_0_G1R_RANGE                      1:1
#define MISCREG_CSITE_SECURITY_0_G1R_WOFFSET                    0x0
#define MISCREG_CSITE_SECURITY_0_G1R_DEFAULT                    _MK_MASK_CONST(0x1)
#define MISCREG_CSITE_SECURITY_0_G1R_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define MISCREG_CSITE_SECURITY_0_G1R_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define MISCREG_CSITE_SECURITY_0_G1R_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define MISCREG_CSITE_SECURITY_0_G1R_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define MISCREG_CSITE_SECURITY_0_G1R_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)

#define MISCREG_CSITE_SECURITY_0_G0R_SHIFT                      _MK_SHIFT_CONST(0)
#define MISCREG_CSITE_SECURITY_0_G0R_FIELD                      _MK_FIELD_CONST(0x1, MISCREG_CSITE_SECURITY_0_G0R_SHIFT)
#define MISCREG_CSITE_SECURITY_0_G0R_RANGE                      0:0
#define MISCREG_CSITE_SECURITY_0_G0R_WOFFSET                    0x0
#define MISCREG_CSITE_SECURITY_0_G0R_DEFAULT                    _MK_MASK_CONST(0x1)
#define MISCREG_CSITE_SECURITY_0_G0R_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define MISCREG_CSITE_SECURITY_0_G0R_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define MISCREG_CSITE_SECURITY_0_G0R_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define MISCREG_CSITE_SECURITY_0_G0R_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define MISCREG_CSITE_SECURITY_0_G0R_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)


// Register MISCREG_DPMU_SECURITY_0
#define MISCREG_DPMU_SECURITY_0                 _MK_ADDR_CONST(0x1034)
#define MISCREG_DPMU_SECURITY_0_SECURE                  0x0
#define MISCREG_DPMU_SECURITY_0_DUAL                    0x0
#define MISCREG_DPMU_SECURITY_0_SCR                     SCRDPMU_0
#define MISCREG_DPMU_SECURITY_0_WORD_COUNT                      0x1
#define MISCREG_DPMU_SECURITY_0_RESET_VAL                       _MK_MASK_CONST(0x2ffff)
#define MISCREG_DPMU_SECURITY_0_RESET_MASK                      _MK_MASK_CONST(0xfffff)
#define MISCREG_DPMU_SECURITY_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define MISCREG_DPMU_SECURITY_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define MISCREG_DPMU_SECURITY_0_READ_MASK                       _MK_MASK_CONST(0xfffff)
#define MISCREG_DPMU_SECURITY_0_WRITE_MASK                      _MK_MASK_CONST(0xffff)
#define MISCREG_DPMU_SECURITY_0_MSTR_ID_SHIFT                   _MK_SHIFT_CONST(16)
#define MISCREG_DPMU_SECURITY_0_MSTR_ID_FIELD                   _MK_FIELD_CONST(0xf, MISCREG_DPMU_SECURITY_0_MSTR_ID_SHIFT)
#define MISCREG_DPMU_SECURITY_0_MSTR_ID_RANGE                   19:16
#define MISCREG_DPMU_SECURITY_0_MSTR_ID_WOFFSET                 0x0
#define MISCREG_DPMU_SECURITY_0_MSTR_ID_DEFAULT                 _MK_MASK_CONST(0x2)
#define MISCREG_DPMU_SECURITY_0_MSTR_ID_DEFAULT_MASK                    _MK_MASK_CONST(0xf)
#define MISCREG_DPMU_SECURITY_0_MSTR_ID_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define MISCREG_DPMU_SECURITY_0_MSTR_ID_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define MISCREG_DPMU_SECURITY_0_MSTR_ID_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define MISCREG_DPMU_SECURITY_0_MSTR_ID_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define MISCREG_DPMU_SECURITY_0_MSTR_ID_CCPLEX                  _MK_ENUM_CONST(1)
#define MISCREG_DPMU_SECURITY_0_MSTR_ID_CCPLEX_DPMU                     _MK_ENUM_CONST(2)
#define MISCREG_DPMU_SECURITY_0_MSTR_ID_BPMP                    _MK_ENUM_CONST(3)
#define MISCREG_DPMU_SECURITY_0_MSTR_ID_SPE                     _MK_ENUM_CONST(4)
#define MISCREG_DPMU_SECURITY_0_MSTR_ID_SCE                     _MK_ENUM_CONST(5)
#define MISCREG_DPMU_SECURITY_0_MSTR_ID_DMA_PER                 _MK_ENUM_CONST(6)
#define MISCREG_DPMU_SECURITY_0_MSTR_ID_TSECA                   _MK_ENUM_CONST(7)
#define MISCREG_DPMU_SECURITY_0_MSTR_ID_TSECB                   _MK_ENUM_CONST(8)
#define MISCREG_DPMU_SECURITY_0_MSTR_ID_JTAGM                   _MK_ENUM_CONST(9)
#define MISCREG_DPMU_SECURITY_0_MSTR_ID_CSITE                   _MK_ENUM_CONST(10)
#define MISCREG_DPMU_SECURITY_0_MSTR_ID_APE                     _MK_ENUM_CONST(11)
#define MISCREG_DPMU_SECURITY_0_MSTR_ID_Peatrans                        _MK_ENUM_CONST(12)
#define MISCREG_DPMU_SECURITY_0_MSTR_ID_NVDEC                   _MK_ENUM_CONST(13)
#define MISCREG_DPMU_SECURITY_0_MSTR_ID_RCE                     _MK_ENUM_CONST(14)
#define MISCREG_DPMU_SECURITY_0_MSTR_ID_NVDEC1                  _MK_ENUM_CONST(15)

#define MISCREG_DPMU_SECURITY_0_G7W_SHIFT                       _MK_SHIFT_CONST(15)
#define MISCREG_DPMU_SECURITY_0_G7W_FIELD                       _MK_FIELD_CONST(0x1, MISCREG_DPMU_SECURITY_0_G7W_SHIFT)
#define MISCREG_DPMU_SECURITY_0_G7W_RANGE                       15:15
#define MISCREG_DPMU_SECURITY_0_G7W_WOFFSET                     0x0
#define MISCREG_DPMU_SECURITY_0_G7W_DEFAULT                     _MK_MASK_CONST(0x1)
#define MISCREG_DPMU_SECURITY_0_G7W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define MISCREG_DPMU_SECURITY_0_G7W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define MISCREG_DPMU_SECURITY_0_G7W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define MISCREG_DPMU_SECURITY_0_G7W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define MISCREG_DPMU_SECURITY_0_G7W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define MISCREG_DPMU_SECURITY_0_G6W_SHIFT                       _MK_SHIFT_CONST(14)
#define MISCREG_DPMU_SECURITY_0_G6W_FIELD                       _MK_FIELD_CONST(0x1, MISCREG_DPMU_SECURITY_0_G6W_SHIFT)
#define MISCREG_DPMU_SECURITY_0_G6W_RANGE                       14:14
#define MISCREG_DPMU_SECURITY_0_G6W_WOFFSET                     0x0
#define MISCREG_DPMU_SECURITY_0_G6W_DEFAULT                     _MK_MASK_CONST(0x1)
#define MISCREG_DPMU_SECURITY_0_G6W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define MISCREG_DPMU_SECURITY_0_G6W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define MISCREG_DPMU_SECURITY_0_G6W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define MISCREG_DPMU_SECURITY_0_G6W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define MISCREG_DPMU_SECURITY_0_G6W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define MISCREG_DPMU_SECURITY_0_G5W_SHIFT                       _MK_SHIFT_CONST(13)
#define MISCREG_DPMU_SECURITY_0_G5W_FIELD                       _MK_FIELD_CONST(0x1, MISCREG_DPMU_SECURITY_0_G5W_SHIFT)
#define MISCREG_DPMU_SECURITY_0_G5W_RANGE                       13:13
#define MISCREG_DPMU_SECURITY_0_G5W_WOFFSET                     0x0
#define MISCREG_DPMU_SECURITY_0_G5W_DEFAULT                     _MK_MASK_CONST(0x1)
#define MISCREG_DPMU_SECURITY_0_G5W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define MISCREG_DPMU_SECURITY_0_G5W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define MISCREG_DPMU_SECURITY_0_G5W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define MISCREG_DPMU_SECURITY_0_G5W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define MISCREG_DPMU_SECURITY_0_G5W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define MISCREG_DPMU_SECURITY_0_G4W_SHIFT                       _MK_SHIFT_CONST(12)
#define MISCREG_DPMU_SECURITY_0_G4W_FIELD                       _MK_FIELD_CONST(0x1, MISCREG_DPMU_SECURITY_0_G4W_SHIFT)
#define MISCREG_DPMU_SECURITY_0_G4W_RANGE                       12:12
#define MISCREG_DPMU_SECURITY_0_G4W_WOFFSET                     0x0
#define MISCREG_DPMU_SECURITY_0_G4W_DEFAULT                     _MK_MASK_CONST(0x1)
#define MISCREG_DPMU_SECURITY_0_G4W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define MISCREG_DPMU_SECURITY_0_G4W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define MISCREG_DPMU_SECURITY_0_G4W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define MISCREG_DPMU_SECURITY_0_G4W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define MISCREG_DPMU_SECURITY_0_G4W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define MISCREG_DPMU_SECURITY_0_G3W_SHIFT                       _MK_SHIFT_CONST(11)
#define MISCREG_DPMU_SECURITY_0_G3W_FIELD                       _MK_FIELD_CONST(0x1, MISCREG_DPMU_SECURITY_0_G3W_SHIFT)
#define MISCREG_DPMU_SECURITY_0_G3W_RANGE                       11:11
#define MISCREG_DPMU_SECURITY_0_G3W_WOFFSET                     0x0
#define MISCREG_DPMU_SECURITY_0_G3W_DEFAULT                     _MK_MASK_CONST(0x1)
#define MISCREG_DPMU_SECURITY_0_G3W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define MISCREG_DPMU_SECURITY_0_G3W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define MISCREG_DPMU_SECURITY_0_G3W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define MISCREG_DPMU_SECURITY_0_G3W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define MISCREG_DPMU_SECURITY_0_G3W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define MISCREG_DPMU_SECURITY_0_G2W_SHIFT                       _MK_SHIFT_CONST(10)
#define MISCREG_DPMU_SECURITY_0_G2W_FIELD                       _MK_FIELD_CONST(0x1, MISCREG_DPMU_SECURITY_0_G2W_SHIFT)
#define MISCREG_DPMU_SECURITY_0_G2W_RANGE                       10:10
#define MISCREG_DPMU_SECURITY_0_G2W_WOFFSET                     0x0
#define MISCREG_DPMU_SECURITY_0_G2W_DEFAULT                     _MK_MASK_CONST(0x1)
#define MISCREG_DPMU_SECURITY_0_G2W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define MISCREG_DPMU_SECURITY_0_G2W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define MISCREG_DPMU_SECURITY_0_G2W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define MISCREG_DPMU_SECURITY_0_G2W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define MISCREG_DPMU_SECURITY_0_G2W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define MISCREG_DPMU_SECURITY_0_G1W_SHIFT                       _MK_SHIFT_CONST(9)
#define MISCREG_DPMU_SECURITY_0_G1W_FIELD                       _MK_FIELD_CONST(0x1, MISCREG_DPMU_SECURITY_0_G1W_SHIFT)
#define MISCREG_DPMU_SECURITY_0_G1W_RANGE                       9:9
#define MISCREG_DPMU_SECURITY_0_G1W_WOFFSET                     0x0
#define MISCREG_DPMU_SECURITY_0_G1W_DEFAULT                     _MK_MASK_CONST(0x1)
#define MISCREG_DPMU_SECURITY_0_G1W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define MISCREG_DPMU_SECURITY_0_G1W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define MISCREG_DPMU_SECURITY_0_G1W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define MISCREG_DPMU_SECURITY_0_G1W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define MISCREG_DPMU_SECURITY_0_G1W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define MISCREG_DPMU_SECURITY_0_G0W_SHIFT                       _MK_SHIFT_CONST(8)
#define MISCREG_DPMU_SECURITY_0_G0W_FIELD                       _MK_FIELD_CONST(0x1, MISCREG_DPMU_SECURITY_0_G0W_SHIFT)
#define MISCREG_DPMU_SECURITY_0_G0W_RANGE                       8:8
#define MISCREG_DPMU_SECURITY_0_G0W_WOFFSET                     0x0
#define MISCREG_DPMU_SECURITY_0_G0W_DEFAULT                     _MK_MASK_CONST(0x1)
#define MISCREG_DPMU_SECURITY_0_G0W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define MISCREG_DPMU_SECURITY_0_G0W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define MISCREG_DPMU_SECURITY_0_G0W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define MISCREG_DPMU_SECURITY_0_G0W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define MISCREG_DPMU_SECURITY_0_G0W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define MISCREG_DPMU_SECURITY_0_G7R_SHIFT                       _MK_SHIFT_CONST(7)
#define MISCREG_DPMU_SECURITY_0_G7R_FIELD                       _MK_FIELD_CONST(0x1, MISCREG_DPMU_SECURITY_0_G7R_SHIFT)
#define MISCREG_DPMU_SECURITY_0_G7R_RANGE                       7:7
#define MISCREG_DPMU_SECURITY_0_G7R_WOFFSET                     0x0
#define MISCREG_DPMU_SECURITY_0_G7R_DEFAULT                     _MK_MASK_CONST(0x1)
#define MISCREG_DPMU_SECURITY_0_G7R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define MISCREG_DPMU_SECURITY_0_G7R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define MISCREG_DPMU_SECURITY_0_G7R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define MISCREG_DPMU_SECURITY_0_G7R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define MISCREG_DPMU_SECURITY_0_G7R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define MISCREG_DPMU_SECURITY_0_G6R_SHIFT                       _MK_SHIFT_CONST(6)
#define MISCREG_DPMU_SECURITY_0_G6R_FIELD                       _MK_FIELD_CONST(0x1, MISCREG_DPMU_SECURITY_0_G6R_SHIFT)
#define MISCREG_DPMU_SECURITY_0_G6R_RANGE                       6:6
#define MISCREG_DPMU_SECURITY_0_G6R_WOFFSET                     0x0
#define MISCREG_DPMU_SECURITY_0_G6R_DEFAULT                     _MK_MASK_CONST(0x1)
#define MISCREG_DPMU_SECURITY_0_G6R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define MISCREG_DPMU_SECURITY_0_G6R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define MISCREG_DPMU_SECURITY_0_G6R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define MISCREG_DPMU_SECURITY_0_G6R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define MISCREG_DPMU_SECURITY_0_G6R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define MISCREG_DPMU_SECURITY_0_G5R_SHIFT                       _MK_SHIFT_CONST(5)
#define MISCREG_DPMU_SECURITY_0_G5R_FIELD                       _MK_FIELD_CONST(0x1, MISCREG_DPMU_SECURITY_0_G5R_SHIFT)
#define MISCREG_DPMU_SECURITY_0_G5R_RANGE                       5:5
#define MISCREG_DPMU_SECURITY_0_G5R_WOFFSET                     0x0
#define MISCREG_DPMU_SECURITY_0_G5R_DEFAULT                     _MK_MASK_CONST(0x1)
#define MISCREG_DPMU_SECURITY_0_G5R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define MISCREG_DPMU_SECURITY_0_G5R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define MISCREG_DPMU_SECURITY_0_G5R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define MISCREG_DPMU_SECURITY_0_G5R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define MISCREG_DPMU_SECURITY_0_G5R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define MISCREG_DPMU_SECURITY_0_G4R_SHIFT                       _MK_SHIFT_CONST(4)
#define MISCREG_DPMU_SECURITY_0_G4R_FIELD                       _MK_FIELD_CONST(0x1, MISCREG_DPMU_SECURITY_0_G4R_SHIFT)
#define MISCREG_DPMU_SECURITY_0_G4R_RANGE                       4:4
#define MISCREG_DPMU_SECURITY_0_G4R_WOFFSET                     0x0
#define MISCREG_DPMU_SECURITY_0_G4R_DEFAULT                     _MK_MASK_CONST(0x1)
#define MISCREG_DPMU_SECURITY_0_G4R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define MISCREG_DPMU_SECURITY_0_G4R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define MISCREG_DPMU_SECURITY_0_G4R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define MISCREG_DPMU_SECURITY_0_G4R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define MISCREG_DPMU_SECURITY_0_G4R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define MISCREG_DPMU_SECURITY_0_G3R_SHIFT                       _MK_SHIFT_CONST(3)
#define MISCREG_DPMU_SECURITY_0_G3R_FIELD                       _MK_FIELD_CONST(0x1, MISCREG_DPMU_SECURITY_0_G3R_SHIFT)
#define MISCREG_DPMU_SECURITY_0_G3R_RANGE                       3:3
#define MISCREG_DPMU_SECURITY_0_G3R_WOFFSET                     0x0
#define MISCREG_DPMU_SECURITY_0_G3R_DEFAULT                     _MK_MASK_CONST(0x1)
#define MISCREG_DPMU_SECURITY_0_G3R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define MISCREG_DPMU_SECURITY_0_G3R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define MISCREG_DPMU_SECURITY_0_G3R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define MISCREG_DPMU_SECURITY_0_G3R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define MISCREG_DPMU_SECURITY_0_G3R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define MISCREG_DPMU_SECURITY_0_G2R_SHIFT                       _MK_SHIFT_CONST(2)
#define MISCREG_DPMU_SECURITY_0_G2R_FIELD                       _MK_FIELD_CONST(0x1, MISCREG_DPMU_SECURITY_0_G2R_SHIFT)
#define MISCREG_DPMU_SECURITY_0_G2R_RANGE                       2:2
#define MISCREG_DPMU_SECURITY_0_G2R_WOFFSET                     0x0
#define MISCREG_DPMU_SECURITY_0_G2R_DEFAULT                     _MK_MASK_CONST(0x1)
#define MISCREG_DPMU_SECURITY_0_G2R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define MISCREG_DPMU_SECURITY_0_G2R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define MISCREG_DPMU_SECURITY_0_G2R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define MISCREG_DPMU_SECURITY_0_G2R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define MISCREG_DPMU_SECURITY_0_G2R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define MISCREG_DPMU_SECURITY_0_G1R_SHIFT                       _MK_SHIFT_CONST(1)
#define MISCREG_DPMU_SECURITY_0_G1R_FIELD                       _MK_FIELD_CONST(0x1, MISCREG_DPMU_SECURITY_0_G1R_SHIFT)
#define MISCREG_DPMU_SECURITY_0_G1R_RANGE                       1:1
#define MISCREG_DPMU_SECURITY_0_G1R_WOFFSET                     0x0
#define MISCREG_DPMU_SECURITY_0_G1R_DEFAULT                     _MK_MASK_CONST(0x1)
#define MISCREG_DPMU_SECURITY_0_G1R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define MISCREG_DPMU_SECURITY_0_G1R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define MISCREG_DPMU_SECURITY_0_G1R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define MISCREG_DPMU_SECURITY_0_G1R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define MISCREG_DPMU_SECURITY_0_G1R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define MISCREG_DPMU_SECURITY_0_G0R_SHIFT                       _MK_SHIFT_CONST(0)
#define MISCREG_DPMU_SECURITY_0_G0R_FIELD                       _MK_FIELD_CONST(0x1, MISCREG_DPMU_SECURITY_0_G0R_SHIFT)
#define MISCREG_DPMU_SECURITY_0_G0R_RANGE                       0:0
#define MISCREG_DPMU_SECURITY_0_G0R_WOFFSET                     0x0
#define MISCREG_DPMU_SECURITY_0_G0R_DEFAULT                     _MK_MASK_CONST(0x1)
#define MISCREG_DPMU_SECURITY_0_G0R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define MISCREG_DPMU_SECURITY_0_G0R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define MISCREG_DPMU_SECURITY_0_G0R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define MISCREG_DPMU_SECURITY_0_G0R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define MISCREG_DPMU_SECURITY_0_G0R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)


// Register MISCREG_NVDEC_HS_SECURITY_0
#define MISCREG_NVDEC_HS_SECURITY_0                     _MK_ADDR_CONST(0x1038)
#define MISCREG_NVDEC_HS_SECURITY_0_SECURE                      0x0
#define MISCREG_NVDEC_HS_SECURITY_0_DUAL                        0x0
#define MISCREG_NVDEC_HS_SECURITY_0_SCR                         SCRNVDEC_0
#define MISCREG_NVDEC_HS_SECURITY_0_WORD_COUNT                  0x1
#define MISCREG_NVDEC_HS_SECURITY_0_RESET_VAL                   _MK_MASK_CONST(0xdffff)
#define MISCREG_NVDEC_HS_SECURITY_0_RESET_MASK                  _MK_MASK_CONST(0xfffff)
#define MISCREG_NVDEC_HS_SECURITY_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define MISCREG_NVDEC_HS_SECURITY_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define MISCREG_NVDEC_HS_SECURITY_0_READ_MASK                   _MK_MASK_CONST(0xfffff)
#define MISCREG_NVDEC_HS_SECURITY_0_WRITE_MASK                  _MK_MASK_CONST(0xffff)
#define MISCREG_NVDEC_HS_SECURITY_0_MSTR_ID_SHIFT                       _MK_SHIFT_CONST(16)
#define MISCREG_NVDEC_HS_SECURITY_0_MSTR_ID_FIELD                       _MK_FIELD_CONST(0xf, MISCREG_NVDEC_HS_SECURITY_0_MSTR_ID_SHIFT)
#define MISCREG_NVDEC_HS_SECURITY_0_MSTR_ID_RANGE                       19:16
#define MISCREG_NVDEC_HS_SECURITY_0_MSTR_ID_WOFFSET                     0x0
#define MISCREG_NVDEC_HS_SECURITY_0_MSTR_ID_DEFAULT                     _MK_MASK_CONST(0xd)
#define MISCREG_NVDEC_HS_SECURITY_0_MSTR_ID_DEFAULT_MASK                        _MK_MASK_CONST(0xf)
#define MISCREG_NVDEC_HS_SECURITY_0_MSTR_ID_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define MISCREG_NVDEC_HS_SECURITY_0_MSTR_ID_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define MISCREG_NVDEC_HS_SECURITY_0_MSTR_ID_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define MISCREG_NVDEC_HS_SECURITY_0_MSTR_ID_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define MISCREG_NVDEC_HS_SECURITY_0_MSTR_ID_CCPLEX                      _MK_ENUM_CONST(1)
#define MISCREG_NVDEC_HS_SECURITY_0_MSTR_ID_CCPLEX_DPMU                 _MK_ENUM_CONST(2)
#define MISCREG_NVDEC_HS_SECURITY_0_MSTR_ID_BPMP                        _MK_ENUM_CONST(3)
#define MISCREG_NVDEC_HS_SECURITY_0_MSTR_ID_SPE                 _MK_ENUM_CONST(4)
#define MISCREG_NVDEC_HS_SECURITY_0_MSTR_ID_SCE                 _MK_ENUM_CONST(5)
#define MISCREG_NVDEC_HS_SECURITY_0_MSTR_ID_DMA_PER                     _MK_ENUM_CONST(6)
#define MISCREG_NVDEC_HS_SECURITY_0_MSTR_ID_TSECA                       _MK_ENUM_CONST(7)
#define MISCREG_NVDEC_HS_SECURITY_0_MSTR_ID_TSECB                       _MK_ENUM_CONST(8)
#define MISCREG_NVDEC_HS_SECURITY_0_MSTR_ID_JTAGM                       _MK_ENUM_CONST(9)
#define MISCREG_NVDEC_HS_SECURITY_0_MSTR_ID_CSITE                       _MK_ENUM_CONST(10)
#define MISCREG_NVDEC_HS_SECURITY_0_MSTR_ID_APE                 _MK_ENUM_CONST(11)
#define MISCREG_NVDEC_HS_SECURITY_0_MSTR_ID_Peatrans                    _MK_ENUM_CONST(12)
#define MISCREG_NVDEC_HS_SECURITY_0_MSTR_ID_NVDEC                       _MK_ENUM_CONST(13)
#define MISCREG_NVDEC_HS_SECURITY_0_MSTR_ID_RCE                 _MK_ENUM_CONST(14)
#define MISCREG_NVDEC_HS_SECURITY_0_MSTR_ID_NVDEC1                      _MK_ENUM_CONST(15)

#define MISCREG_NVDEC_HS_SECURITY_0_G7W_SHIFT                   _MK_SHIFT_CONST(15)
#define MISCREG_NVDEC_HS_SECURITY_0_G7W_FIELD                   _MK_FIELD_CONST(0x1, MISCREG_NVDEC_HS_SECURITY_0_G7W_SHIFT)
#define MISCREG_NVDEC_HS_SECURITY_0_G7W_RANGE                   15:15
#define MISCREG_NVDEC_HS_SECURITY_0_G7W_WOFFSET                 0x0
#define MISCREG_NVDEC_HS_SECURITY_0_G7W_DEFAULT                 _MK_MASK_CONST(0x1)
#define MISCREG_NVDEC_HS_SECURITY_0_G7W_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define MISCREG_NVDEC_HS_SECURITY_0_G7W_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define MISCREG_NVDEC_HS_SECURITY_0_G7W_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define MISCREG_NVDEC_HS_SECURITY_0_G7W_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define MISCREG_NVDEC_HS_SECURITY_0_G7W_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define MISCREG_NVDEC_HS_SECURITY_0_G6W_SHIFT                   _MK_SHIFT_CONST(14)
#define MISCREG_NVDEC_HS_SECURITY_0_G6W_FIELD                   _MK_FIELD_CONST(0x1, MISCREG_NVDEC_HS_SECURITY_0_G6W_SHIFT)
#define MISCREG_NVDEC_HS_SECURITY_0_G6W_RANGE                   14:14
#define MISCREG_NVDEC_HS_SECURITY_0_G6W_WOFFSET                 0x0
#define MISCREG_NVDEC_HS_SECURITY_0_G6W_DEFAULT                 _MK_MASK_CONST(0x1)
#define MISCREG_NVDEC_HS_SECURITY_0_G6W_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define MISCREG_NVDEC_HS_SECURITY_0_G6W_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define MISCREG_NVDEC_HS_SECURITY_0_G6W_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define MISCREG_NVDEC_HS_SECURITY_0_G6W_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define MISCREG_NVDEC_HS_SECURITY_0_G6W_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define MISCREG_NVDEC_HS_SECURITY_0_G5W_SHIFT                   _MK_SHIFT_CONST(13)
#define MISCREG_NVDEC_HS_SECURITY_0_G5W_FIELD                   _MK_FIELD_CONST(0x1, MISCREG_NVDEC_HS_SECURITY_0_G5W_SHIFT)
#define MISCREG_NVDEC_HS_SECURITY_0_G5W_RANGE                   13:13
#define MISCREG_NVDEC_HS_SECURITY_0_G5W_WOFFSET                 0x0
#define MISCREG_NVDEC_HS_SECURITY_0_G5W_DEFAULT                 _MK_MASK_CONST(0x1)
#define MISCREG_NVDEC_HS_SECURITY_0_G5W_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define MISCREG_NVDEC_HS_SECURITY_0_G5W_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define MISCREG_NVDEC_HS_SECURITY_0_G5W_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define MISCREG_NVDEC_HS_SECURITY_0_G5W_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define MISCREG_NVDEC_HS_SECURITY_0_G5W_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define MISCREG_NVDEC_HS_SECURITY_0_G4W_SHIFT                   _MK_SHIFT_CONST(12)
#define MISCREG_NVDEC_HS_SECURITY_0_G4W_FIELD                   _MK_FIELD_CONST(0x1, MISCREG_NVDEC_HS_SECURITY_0_G4W_SHIFT)
#define MISCREG_NVDEC_HS_SECURITY_0_G4W_RANGE                   12:12
#define MISCREG_NVDEC_HS_SECURITY_0_G4W_WOFFSET                 0x0
#define MISCREG_NVDEC_HS_SECURITY_0_G4W_DEFAULT                 _MK_MASK_CONST(0x1)
#define MISCREG_NVDEC_HS_SECURITY_0_G4W_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define MISCREG_NVDEC_HS_SECURITY_0_G4W_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define MISCREG_NVDEC_HS_SECURITY_0_G4W_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define MISCREG_NVDEC_HS_SECURITY_0_G4W_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define MISCREG_NVDEC_HS_SECURITY_0_G4W_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define MISCREG_NVDEC_HS_SECURITY_0_G3W_SHIFT                   _MK_SHIFT_CONST(11)
#define MISCREG_NVDEC_HS_SECURITY_0_G3W_FIELD                   _MK_FIELD_CONST(0x1, MISCREG_NVDEC_HS_SECURITY_0_G3W_SHIFT)
#define MISCREG_NVDEC_HS_SECURITY_0_G3W_RANGE                   11:11
#define MISCREG_NVDEC_HS_SECURITY_0_G3W_WOFFSET                 0x0
#define MISCREG_NVDEC_HS_SECURITY_0_G3W_DEFAULT                 _MK_MASK_CONST(0x1)
#define MISCREG_NVDEC_HS_SECURITY_0_G3W_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define MISCREG_NVDEC_HS_SECURITY_0_G3W_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define MISCREG_NVDEC_HS_SECURITY_0_G3W_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define MISCREG_NVDEC_HS_SECURITY_0_G3W_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define MISCREG_NVDEC_HS_SECURITY_0_G3W_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define MISCREG_NVDEC_HS_SECURITY_0_G2W_SHIFT                   _MK_SHIFT_CONST(10)
#define MISCREG_NVDEC_HS_SECURITY_0_G2W_FIELD                   _MK_FIELD_CONST(0x1, MISCREG_NVDEC_HS_SECURITY_0_G2W_SHIFT)
#define MISCREG_NVDEC_HS_SECURITY_0_G2W_RANGE                   10:10
#define MISCREG_NVDEC_HS_SECURITY_0_G2W_WOFFSET                 0x0
#define MISCREG_NVDEC_HS_SECURITY_0_G2W_DEFAULT                 _MK_MASK_CONST(0x1)
#define MISCREG_NVDEC_HS_SECURITY_0_G2W_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define MISCREG_NVDEC_HS_SECURITY_0_G2W_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define MISCREG_NVDEC_HS_SECURITY_0_G2W_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define MISCREG_NVDEC_HS_SECURITY_0_G2W_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define MISCREG_NVDEC_HS_SECURITY_0_G2W_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define MISCREG_NVDEC_HS_SECURITY_0_G1W_SHIFT                   _MK_SHIFT_CONST(9)
#define MISCREG_NVDEC_HS_SECURITY_0_G1W_FIELD                   _MK_FIELD_CONST(0x1, MISCREG_NVDEC_HS_SECURITY_0_G1W_SHIFT)
#define MISCREG_NVDEC_HS_SECURITY_0_G1W_RANGE                   9:9
#define MISCREG_NVDEC_HS_SECURITY_0_G1W_WOFFSET                 0x0
#define MISCREG_NVDEC_HS_SECURITY_0_G1W_DEFAULT                 _MK_MASK_CONST(0x1)
#define MISCREG_NVDEC_HS_SECURITY_0_G1W_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define MISCREG_NVDEC_HS_SECURITY_0_G1W_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define MISCREG_NVDEC_HS_SECURITY_0_G1W_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define MISCREG_NVDEC_HS_SECURITY_0_G1W_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define MISCREG_NVDEC_HS_SECURITY_0_G1W_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define MISCREG_NVDEC_HS_SECURITY_0_G0W_SHIFT                   _MK_SHIFT_CONST(8)
#define MISCREG_NVDEC_HS_SECURITY_0_G0W_FIELD                   _MK_FIELD_CONST(0x1, MISCREG_NVDEC_HS_SECURITY_0_G0W_SHIFT)
#define MISCREG_NVDEC_HS_SECURITY_0_G0W_RANGE                   8:8
#define MISCREG_NVDEC_HS_SECURITY_0_G0W_WOFFSET                 0x0
#define MISCREG_NVDEC_HS_SECURITY_0_G0W_DEFAULT                 _MK_MASK_CONST(0x1)
#define MISCREG_NVDEC_HS_SECURITY_0_G0W_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define MISCREG_NVDEC_HS_SECURITY_0_G0W_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define MISCREG_NVDEC_HS_SECURITY_0_G0W_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define MISCREG_NVDEC_HS_SECURITY_0_G0W_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define MISCREG_NVDEC_HS_SECURITY_0_G0W_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define MISCREG_NVDEC_HS_SECURITY_0_G7R_SHIFT                   _MK_SHIFT_CONST(7)
#define MISCREG_NVDEC_HS_SECURITY_0_G7R_FIELD                   _MK_FIELD_CONST(0x1, MISCREG_NVDEC_HS_SECURITY_0_G7R_SHIFT)
#define MISCREG_NVDEC_HS_SECURITY_0_G7R_RANGE                   7:7
#define MISCREG_NVDEC_HS_SECURITY_0_G7R_WOFFSET                 0x0
#define MISCREG_NVDEC_HS_SECURITY_0_G7R_DEFAULT                 _MK_MASK_CONST(0x1)
#define MISCREG_NVDEC_HS_SECURITY_0_G7R_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define MISCREG_NVDEC_HS_SECURITY_0_G7R_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define MISCREG_NVDEC_HS_SECURITY_0_G7R_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define MISCREG_NVDEC_HS_SECURITY_0_G7R_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define MISCREG_NVDEC_HS_SECURITY_0_G7R_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define MISCREG_NVDEC_HS_SECURITY_0_G6R_SHIFT                   _MK_SHIFT_CONST(6)
#define MISCREG_NVDEC_HS_SECURITY_0_G6R_FIELD                   _MK_FIELD_CONST(0x1, MISCREG_NVDEC_HS_SECURITY_0_G6R_SHIFT)
#define MISCREG_NVDEC_HS_SECURITY_0_G6R_RANGE                   6:6
#define MISCREG_NVDEC_HS_SECURITY_0_G6R_WOFFSET                 0x0
#define MISCREG_NVDEC_HS_SECURITY_0_G6R_DEFAULT                 _MK_MASK_CONST(0x1)
#define MISCREG_NVDEC_HS_SECURITY_0_G6R_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define MISCREG_NVDEC_HS_SECURITY_0_G6R_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define MISCREG_NVDEC_HS_SECURITY_0_G6R_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define MISCREG_NVDEC_HS_SECURITY_0_G6R_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define MISCREG_NVDEC_HS_SECURITY_0_G6R_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define MISCREG_NVDEC_HS_SECURITY_0_G5R_SHIFT                   _MK_SHIFT_CONST(5)
#define MISCREG_NVDEC_HS_SECURITY_0_G5R_FIELD                   _MK_FIELD_CONST(0x1, MISCREG_NVDEC_HS_SECURITY_0_G5R_SHIFT)
#define MISCREG_NVDEC_HS_SECURITY_0_G5R_RANGE                   5:5
#define MISCREG_NVDEC_HS_SECURITY_0_G5R_WOFFSET                 0x0
#define MISCREG_NVDEC_HS_SECURITY_0_G5R_DEFAULT                 _MK_MASK_CONST(0x1)
#define MISCREG_NVDEC_HS_SECURITY_0_G5R_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define MISCREG_NVDEC_HS_SECURITY_0_G5R_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define MISCREG_NVDEC_HS_SECURITY_0_G5R_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define MISCREG_NVDEC_HS_SECURITY_0_G5R_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define MISCREG_NVDEC_HS_SECURITY_0_G5R_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define MISCREG_NVDEC_HS_SECURITY_0_G4R_SHIFT                   _MK_SHIFT_CONST(4)
#define MISCREG_NVDEC_HS_SECURITY_0_G4R_FIELD                   _MK_FIELD_CONST(0x1, MISCREG_NVDEC_HS_SECURITY_0_G4R_SHIFT)
#define MISCREG_NVDEC_HS_SECURITY_0_G4R_RANGE                   4:4
#define MISCREG_NVDEC_HS_SECURITY_0_G4R_WOFFSET                 0x0
#define MISCREG_NVDEC_HS_SECURITY_0_G4R_DEFAULT                 _MK_MASK_CONST(0x1)
#define MISCREG_NVDEC_HS_SECURITY_0_G4R_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define MISCREG_NVDEC_HS_SECURITY_0_G4R_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define MISCREG_NVDEC_HS_SECURITY_0_G4R_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define MISCREG_NVDEC_HS_SECURITY_0_G4R_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define MISCREG_NVDEC_HS_SECURITY_0_G4R_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define MISCREG_NVDEC_HS_SECURITY_0_G3R_SHIFT                   _MK_SHIFT_CONST(3)
#define MISCREG_NVDEC_HS_SECURITY_0_G3R_FIELD                   _MK_FIELD_CONST(0x1, MISCREG_NVDEC_HS_SECURITY_0_G3R_SHIFT)
#define MISCREG_NVDEC_HS_SECURITY_0_G3R_RANGE                   3:3
#define MISCREG_NVDEC_HS_SECURITY_0_G3R_WOFFSET                 0x0
#define MISCREG_NVDEC_HS_SECURITY_0_G3R_DEFAULT                 _MK_MASK_CONST(0x1)
#define MISCREG_NVDEC_HS_SECURITY_0_G3R_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define MISCREG_NVDEC_HS_SECURITY_0_G3R_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define MISCREG_NVDEC_HS_SECURITY_0_G3R_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define MISCREG_NVDEC_HS_SECURITY_0_G3R_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define MISCREG_NVDEC_HS_SECURITY_0_G3R_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define MISCREG_NVDEC_HS_SECURITY_0_G2R_SHIFT                   _MK_SHIFT_CONST(2)
#define MISCREG_NVDEC_HS_SECURITY_0_G2R_FIELD                   _MK_FIELD_CONST(0x1, MISCREG_NVDEC_HS_SECURITY_0_G2R_SHIFT)
#define MISCREG_NVDEC_HS_SECURITY_0_G2R_RANGE                   2:2
#define MISCREG_NVDEC_HS_SECURITY_0_G2R_WOFFSET                 0x0
#define MISCREG_NVDEC_HS_SECURITY_0_G2R_DEFAULT                 _MK_MASK_CONST(0x1)
#define MISCREG_NVDEC_HS_SECURITY_0_G2R_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define MISCREG_NVDEC_HS_SECURITY_0_G2R_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define MISCREG_NVDEC_HS_SECURITY_0_G2R_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define MISCREG_NVDEC_HS_SECURITY_0_G2R_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define MISCREG_NVDEC_HS_SECURITY_0_G2R_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define MISCREG_NVDEC_HS_SECURITY_0_G1R_SHIFT                   _MK_SHIFT_CONST(1)
#define MISCREG_NVDEC_HS_SECURITY_0_G1R_FIELD                   _MK_FIELD_CONST(0x1, MISCREG_NVDEC_HS_SECURITY_0_G1R_SHIFT)
#define MISCREG_NVDEC_HS_SECURITY_0_G1R_RANGE                   1:1
#define MISCREG_NVDEC_HS_SECURITY_0_G1R_WOFFSET                 0x0
#define MISCREG_NVDEC_HS_SECURITY_0_G1R_DEFAULT                 _MK_MASK_CONST(0x1)
#define MISCREG_NVDEC_HS_SECURITY_0_G1R_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define MISCREG_NVDEC_HS_SECURITY_0_G1R_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define MISCREG_NVDEC_HS_SECURITY_0_G1R_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define MISCREG_NVDEC_HS_SECURITY_0_G1R_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define MISCREG_NVDEC_HS_SECURITY_0_G1R_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define MISCREG_NVDEC_HS_SECURITY_0_G0R_SHIFT                   _MK_SHIFT_CONST(0)
#define MISCREG_NVDEC_HS_SECURITY_0_G0R_FIELD                   _MK_FIELD_CONST(0x1, MISCREG_NVDEC_HS_SECURITY_0_G0R_SHIFT)
#define MISCREG_NVDEC_HS_SECURITY_0_G0R_RANGE                   0:0
#define MISCREG_NVDEC_HS_SECURITY_0_G0R_WOFFSET                 0x0
#define MISCREG_NVDEC_HS_SECURITY_0_G0R_DEFAULT                 _MK_MASK_CONST(0x1)
#define MISCREG_NVDEC_HS_SECURITY_0_G0R_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define MISCREG_NVDEC_HS_SECURITY_0_G0R_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define MISCREG_NVDEC_HS_SECURITY_0_G0R_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define MISCREG_NVDEC_HS_SECURITY_0_G0R_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define MISCREG_NVDEC_HS_SECURITY_0_G0R_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)


// Register MISCREG_NVDEC_LS_SECURITY_0
#define MISCREG_NVDEC_LS_SECURITY_0                     _MK_ADDR_CONST(0x103c)
#define MISCREG_NVDEC_LS_SECURITY_0_SECURE                      0x0
#define MISCREG_NVDEC_LS_SECURITY_0_DUAL                        0x0
#define MISCREG_NVDEC_LS_SECURITY_0_SCR                         SCRNVDEC_0
#define MISCREG_NVDEC_LS_SECURITY_0_WORD_COUNT                  0x1
#define MISCREG_NVDEC_LS_SECURITY_0_RESET_VAL                   _MK_MASK_CONST(0xdffff)
#define MISCREG_NVDEC_LS_SECURITY_0_RESET_MASK                  _MK_MASK_CONST(0xfffff)
#define MISCREG_NVDEC_LS_SECURITY_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define MISCREG_NVDEC_LS_SECURITY_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define MISCREG_NVDEC_LS_SECURITY_0_READ_MASK                   _MK_MASK_CONST(0xfffff)
#define MISCREG_NVDEC_LS_SECURITY_0_WRITE_MASK                  _MK_MASK_CONST(0xffff)
#define MISCREG_NVDEC_LS_SECURITY_0_MSTR_ID_SHIFT                       _MK_SHIFT_CONST(16)
#define MISCREG_NVDEC_LS_SECURITY_0_MSTR_ID_FIELD                       _MK_FIELD_CONST(0xf, MISCREG_NVDEC_LS_SECURITY_0_MSTR_ID_SHIFT)
#define MISCREG_NVDEC_LS_SECURITY_0_MSTR_ID_RANGE                       19:16
#define MISCREG_NVDEC_LS_SECURITY_0_MSTR_ID_WOFFSET                     0x0
#define MISCREG_NVDEC_LS_SECURITY_0_MSTR_ID_DEFAULT                     _MK_MASK_CONST(0xd)
#define MISCREG_NVDEC_LS_SECURITY_0_MSTR_ID_DEFAULT_MASK                        _MK_MASK_CONST(0xf)
#define MISCREG_NVDEC_LS_SECURITY_0_MSTR_ID_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define MISCREG_NVDEC_LS_SECURITY_0_MSTR_ID_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define MISCREG_NVDEC_LS_SECURITY_0_MSTR_ID_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define MISCREG_NVDEC_LS_SECURITY_0_MSTR_ID_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define MISCREG_NVDEC_LS_SECURITY_0_MSTR_ID_CCPLEX                      _MK_ENUM_CONST(1)
#define MISCREG_NVDEC_LS_SECURITY_0_MSTR_ID_CCPLEX_DPMU                 _MK_ENUM_CONST(2)
#define MISCREG_NVDEC_LS_SECURITY_0_MSTR_ID_BPMP                        _MK_ENUM_CONST(3)
#define MISCREG_NVDEC_LS_SECURITY_0_MSTR_ID_SPE                 _MK_ENUM_CONST(4)
#define MISCREG_NVDEC_LS_SECURITY_0_MSTR_ID_SCE                 _MK_ENUM_CONST(5)
#define MISCREG_NVDEC_LS_SECURITY_0_MSTR_ID_DMA_PER                     _MK_ENUM_CONST(6)
#define MISCREG_NVDEC_LS_SECURITY_0_MSTR_ID_TSECA                       _MK_ENUM_CONST(7)
#define MISCREG_NVDEC_LS_SECURITY_0_MSTR_ID_TSECB                       _MK_ENUM_CONST(8)
#define MISCREG_NVDEC_LS_SECURITY_0_MSTR_ID_JTAGM                       _MK_ENUM_CONST(9)
#define MISCREG_NVDEC_LS_SECURITY_0_MSTR_ID_CSITE                       _MK_ENUM_CONST(10)
#define MISCREG_NVDEC_LS_SECURITY_0_MSTR_ID_APE                 _MK_ENUM_CONST(11)
#define MISCREG_NVDEC_LS_SECURITY_0_MSTR_ID_Peatrans                    _MK_ENUM_CONST(12)
#define MISCREG_NVDEC_LS_SECURITY_0_MSTR_ID_NVDEC                       _MK_ENUM_CONST(13)
#define MISCREG_NVDEC_LS_SECURITY_0_MSTR_ID_RCE                 _MK_ENUM_CONST(14)
#define MISCREG_NVDEC_LS_SECURITY_0_MSTR_ID_NVDEC1                      _MK_ENUM_CONST(15)

#define MISCREG_NVDEC_LS_SECURITY_0_G7W_SHIFT                   _MK_SHIFT_CONST(15)
#define MISCREG_NVDEC_LS_SECURITY_0_G7W_FIELD                   _MK_FIELD_CONST(0x1, MISCREG_NVDEC_LS_SECURITY_0_G7W_SHIFT)
#define MISCREG_NVDEC_LS_SECURITY_0_G7W_RANGE                   15:15
#define MISCREG_NVDEC_LS_SECURITY_0_G7W_WOFFSET                 0x0
#define MISCREG_NVDEC_LS_SECURITY_0_G7W_DEFAULT                 _MK_MASK_CONST(0x1)
#define MISCREG_NVDEC_LS_SECURITY_0_G7W_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define MISCREG_NVDEC_LS_SECURITY_0_G7W_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define MISCREG_NVDEC_LS_SECURITY_0_G7W_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define MISCREG_NVDEC_LS_SECURITY_0_G7W_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define MISCREG_NVDEC_LS_SECURITY_0_G7W_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define MISCREG_NVDEC_LS_SECURITY_0_G6W_SHIFT                   _MK_SHIFT_CONST(14)
#define MISCREG_NVDEC_LS_SECURITY_0_G6W_FIELD                   _MK_FIELD_CONST(0x1, MISCREG_NVDEC_LS_SECURITY_0_G6W_SHIFT)
#define MISCREG_NVDEC_LS_SECURITY_0_G6W_RANGE                   14:14
#define MISCREG_NVDEC_LS_SECURITY_0_G6W_WOFFSET                 0x0
#define MISCREG_NVDEC_LS_SECURITY_0_G6W_DEFAULT                 _MK_MASK_CONST(0x1)
#define MISCREG_NVDEC_LS_SECURITY_0_G6W_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define MISCREG_NVDEC_LS_SECURITY_0_G6W_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define MISCREG_NVDEC_LS_SECURITY_0_G6W_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define MISCREG_NVDEC_LS_SECURITY_0_G6W_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define MISCREG_NVDEC_LS_SECURITY_0_G6W_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define MISCREG_NVDEC_LS_SECURITY_0_G5W_SHIFT                   _MK_SHIFT_CONST(13)
#define MISCREG_NVDEC_LS_SECURITY_0_G5W_FIELD                   _MK_FIELD_CONST(0x1, MISCREG_NVDEC_LS_SECURITY_0_G5W_SHIFT)
#define MISCREG_NVDEC_LS_SECURITY_0_G5W_RANGE                   13:13
#define MISCREG_NVDEC_LS_SECURITY_0_G5W_WOFFSET                 0x0
#define MISCREG_NVDEC_LS_SECURITY_0_G5W_DEFAULT                 _MK_MASK_CONST(0x1)
#define MISCREG_NVDEC_LS_SECURITY_0_G5W_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define MISCREG_NVDEC_LS_SECURITY_0_G5W_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define MISCREG_NVDEC_LS_SECURITY_0_G5W_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define MISCREG_NVDEC_LS_SECURITY_0_G5W_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define MISCREG_NVDEC_LS_SECURITY_0_G5W_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define MISCREG_NVDEC_LS_SECURITY_0_G4W_SHIFT                   _MK_SHIFT_CONST(12)
#define MISCREG_NVDEC_LS_SECURITY_0_G4W_FIELD                   _MK_FIELD_CONST(0x1, MISCREG_NVDEC_LS_SECURITY_0_G4W_SHIFT)
#define MISCREG_NVDEC_LS_SECURITY_0_G4W_RANGE                   12:12
#define MISCREG_NVDEC_LS_SECURITY_0_G4W_WOFFSET                 0x0
#define MISCREG_NVDEC_LS_SECURITY_0_G4W_DEFAULT                 _MK_MASK_CONST(0x1)
#define MISCREG_NVDEC_LS_SECURITY_0_G4W_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define MISCREG_NVDEC_LS_SECURITY_0_G4W_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define MISCREG_NVDEC_LS_SECURITY_0_G4W_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define MISCREG_NVDEC_LS_SECURITY_0_G4W_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define MISCREG_NVDEC_LS_SECURITY_0_G4W_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define MISCREG_NVDEC_LS_SECURITY_0_G3W_SHIFT                   _MK_SHIFT_CONST(11)
#define MISCREG_NVDEC_LS_SECURITY_0_G3W_FIELD                   _MK_FIELD_CONST(0x1, MISCREG_NVDEC_LS_SECURITY_0_G3W_SHIFT)
#define MISCREG_NVDEC_LS_SECURITY_0_G3W_RANGE                   11:11
#define MISCREG_NVDEC_LS_SECURITY_0_G3W_WOFFSET                 0x0
#define MISCREG_NVDEC_LS_SECURITY_0_G3W_DEFAULT                 _MK_MASK_CONST(0x1)
#define MISCREG_NVDEC_LS_SECURITY_0_G3W_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define MISCREG_NVDEC_LS_SECURITY_0_G3W_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define MISCREG_NVDEC_LS_SECURITY_0_G3W_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define MISCREG_NVDEC_LS_SECURITY_0_G3W_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define MISCREG_NVDEC_LS_SECURITY_0_G3W_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define MISCREG_NVDEC_LS_SECURITY_0_G2W_SHIFT                   _MK_SHIFT_CONST(10)
#define MISCREG_NVDEC_LS_SECURITY_0_G2W_FIELD                   _MK_FIELD_CONST(0x1, MISCREG_NVDEC_LS_SECURITY_0_G2W_SHIFT)
#define MISCREG_NVDEC_LS_SECURITY_0_G2W_RANGE                   10:10
#define MISCREG_NVDEC_LS_SECURITY_0_G2W_WOFFSET                 0x0
#define MISCREG_NVDEC_LS_SECURITY_0_G2W_DEFAULT                 _MK_MASK_CONST(0x1)
#define MISCREG_NVDEC_LS_SECURITY_0_G2W_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define MISCREG_NVDEC_LS_SECURITY_0_G2W_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define MISCREG_NVDEC_LS_SECURITY_0_G2W_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define MISCREG_NVDEC_LS_SECURITY_0_G2W_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define MISCREG_NVDEC_LS_SECURITY_0_G2W_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define MISCREG_NVDEC_LS_SECURITY_0_G1W_SHIFT                   _MK_SHIFT_CONST(9)
#define MISCREG_NVDEC_LS_SECURITY_0_G1W_FIELD                   _MK_FIELD_CONST(0x1, MISCREG_NVDEC_LS_SECURITY_0_G1W_SHIFT)
#define MISCREG_NVDEC_LS_SECURITY_0_G1W_RANGE                   9:9
#define MISCREG_NVDEC_LS_SECURITY_0_G1W_WOFFSET                 0x0
#define MISCREG_NVDEC_LS_SECURITY_0_G1W_DEFAULT                 _MK_MASK_CONST(0x1)
#define MISCREG_NVDEC_LS_SECURITY_0_G1W_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define MISCREG_NVDEC_LS_SECURITY_0_G1W_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define MISCREG_NVDEC_LS_SECURITY_0_G1W_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define MISCREG_NVDEC_LS_SECURITY_0_G1W_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define MISCREG_NVDEC_LS_SECURITY_0_G1W_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define MISCREG_NVDEC_LS_SECURITY_0_G0W_SHIFT                   _MK_SHIFT_CONST(8)
#define MISCREG_NVDEC_LS_SECURITY_0_G0W_FIELD                   _MK_FIELD_CONST(0x1, MISCREG_NVDEC_LS_SECURITY_0_G0W_SHIFT)
#define MISCREG_NVDEC_LS_SECURITY_0_G0W_RANGE                   8:8
#define MISCREG_NVDEC_LS_SECURITY_0_G0W_WOFFSET                 0x0
#define MISCREG_NVDEC_LS_SECURITY_0_G0W_DEFAULT                 _MK_MASK_CONST(0x1)
#define MISCREG_NVDEC_LS_SECURITY_0_G0W_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define MISCREG_NVDEC_LS_SECURITY_0_G0W_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define MISCREG_NVDEC_LS_SECURITY_0_G0W_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define MISCREG_NVDEC_LS_SECURITY_0_G0W_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define MISCREG_NVDEC_LS_SECURITY_0_G0W_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define MISCREG_NVDEC_LS_SECURITY_0_G7R_SHIFT                   _MK_SHIFT_CONST(7)
#define MISCREG_NVDEC_LS_SECURITY_0_G7R_FIELD                   _MK_FIELD_CONST(0x1, MISCREG_NVDEC_LS_SECURITY_0_G7R_SHIFT)
#define MISCREG_NVDEC_LS_SECURITY_0_G7R_RANGE                   7:7
#define MISCREG_NVDEC_LS_SECURITY_0_G7R_WOFFSET                 0x0
#define MISCREG_NVDEC_LS_SECURITY_0_G7R_DEFAULT                 _MK_MASK_CONST(0x1)
#define MISCREG_NVDEC_LS_SECURITY_0_G7R_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define MISCREG_NVDEC_LS_SECURITY_0_G7R_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define MISCREG_NVDEC_LS_SECURITY_0_G7R_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define MISCREG_NVDEC_LS_SECURITY_0_G7R_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define MISCREG_NVDEC_LS_SECURITY_0_G7R_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define MISCREG_NVDEC_LS_SECURITY_0_G6R_SHIFT                   _MK_SHIFT_CONST(6)
#define MISCREG_NVDEC_LS_SECURITY_0_G6R_FIELD                   _MK_FIELD_CONST(0x1, MISCREG_NVDEC_LS_SECURITY_0_G6R_SHIFT)
#define MISCREG_NVDEC_LS_SECURITY_0_G6R_RANGE                   6:6
#define MISCREG_NVDEC_LS_SECURITY_0_G6R_WOFFSET                 0x0
#define MISCREG_NVDEC_LS_SECURITY_0_G6R_DEFAULT                 _MK_MASK_CONST(0x1)
#define MISCREG_NVDEC_LS_SECURITY_0_G6R_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define MISCREG_NVDEC_LS_SECURITY_0_G6R_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define MISCREG_NVDEC_LS_SECURITY_0_G6R_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define MISCREG_NVDEC_LS_SECURITY_0_G6R_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define MISCREG_NVDEC_LS_SECURITY_0_G6R_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define MISCREG_NVDEC_LS_SECURITY_0_G5R_SHIFT                   _MK_SHIFT_CONST(5)
#define MISCREG_NVDEC_LS_SECURITY_0_G5R_FIELD                   _MK_FIELD_CONST(0x1, MISCREG_NVDEC_LS_SECURITY_0_G5R_SHIFT)
#define MISCREG_NVDEC_LS_SECURITY_0_G5R_RANGE                   5:5
#define MISCREG_NVDEC_LS_SECURITY_0_G5R_WOFFSET                 0x0
#define MISCREG_NVDEC_LS_SECURITY_0_G5R_DEFAULT                 _MK_MASK_CONST(0x1)
#define MISCREG_NVDEC_LS_SECURITY_0_G5R_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define MISCREG_NVDEC_LS_SECURITY_0_G5R_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define MISCREG_NVDEC_LS_SECURITY_0_G5R_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define MISCREG_NVDEC_LS_SECURITY_0_G5R_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define MISCREG_NVDEC_LS_SECURITY_0_G5R_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define MISCREG_NVDEC_LS_SECURITY_0_G4R_SHIFT                   _MK_SHIFT_CONST(4)
#define MISCREG_NVDEC_LS_SECURITY_0_G4R_FIELD                   _MK_FIELD_CONST(0x1, MISCREG_NVDEC_LS_SECURITY_0_G4R_SHIFT)
#define MISCREG_NVDEC_LS_SECURITY_0_G4R_RANGE                   4:4
#define MISCREG_NVDEC_LS_SECURITY_0_G4R_WOFFSET                 0x0
#define MISCREG_NVDEC_LS_SECURITY_0_G4R_DEFAULT                 _MK_MASK_CONST(0x1)
#define MISCREG_NVDEC_LS_SECURITY_0_G4R_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define MISCREG_NVDEC_LS_SECURITY_0_G4R_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define MISCREG_NVDEC_LS_SECURITY_0_G4R_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define MISCREG_NVDEC_LS_SECURITY_0_G4R_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define MISCREG_NVDEC_LS_SECURITY_0_G4R_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define MISCREG_NVDEC_LS_SECURITY_0_G3R_SHIFT                   _MK_SHIFT_CONST(3)
#define MISCREG_NVDEC_LS_SECURITY_0_G3R_FIELD                   _MK_FIELD_CONST(0x1, MISCREG_NVDEC_LS_SECURITY_0_G3R_SHIFT)
#define MISCREG_NVDEC_LS_SECURITY_0_G3R_RANGE                   3:3
#define MISCREG_NVDEC_LS_SECURITY_0_G3R_WOFFSET                 0x0
#define MISCREG_NVDEC_LS_SECURITY_0_G3R_DEFAULT                 _MK_MASK_CONST(0x1)
#define MISCREG_NVDEC_LS_SECURITY_0_G3R_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define MISCREG_NVDEC_LS_SECURITY_0_G3R_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define MISCREG_NVDEC_LS_SECURITY_0_G3R_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define MISCREG_NVDEC_LS_SECURITY_0_G3R_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define MISCREG_NVDEC_LS_SECURITY_0_G3R_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define MISCREG_NVDEC_LS_SECURITY_0_G2R_SHIFT                   _MK_SHIFT_CONST(2)
#define MISCREG_NVDEC_LS_SECURITY_0_G2R_FIELD                   _MK_FIELD_CONST(0x1, MISCREG_NVDEC_LS_SECURITY_0_G2R_SHIFT)
#define MISCREG_NVDEC_LS_SECURITY_0_G2R_RANGE                   2:2
#define MISCREG_NVDEC_LS_SECURITY_0_G2R_WOFFSET                 0x0
#define MISCREG_NVDEC_LS_SECURITY_0_G2R_DEFAULT                 _MK_MASK_CONST(0x1)
#define MISCREG_NVDEC_LS_SECURITY_0_G2R_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define MISCREG_NVDEC_LS_SECURITY_0_G2R_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define MISCREG_NVDEC_LS_SECURITY_0_G2R_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define MISCREG_NVDEC_LS_SECURITY_0_G2R_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define MISCREG_NVDEC_LS_SECURITY_0_G2R_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define MISCREG_NVDEC_LS_SECURITY_0_G1R_SHIFT                   _MK_SHIFT_CONST(1)
#define MISCREG_NVDEC_LS_SECURITY_0_G1R_FIELD                   _MK_FIELD_CONST(0x1, MISCREG_NVDEC_LS_SECURITY_0_G1R_SHIFT)
#define MISCREG_NVDEC_LS_SECURITY_0_G1R_RANGE                   1:1
#define MISCREG_NVDEC_LS_SECURITY_0_G1R_WOFFSET                 0x0
#define MISCREG_NVDEC_LS_SECURITY_0_G1R_DEFAULT                 _MK_MASK_CONST(0x1)
#define MISCREG_NVDEC_LS_SECURITY_0_G1R_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define MISCREG_NVDEC_LS_SECURITY_0_G1R_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define MISCREG_NVDEC_LS_SECURITY_0_G1R_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define MISCREG_NVDEC_LS_SECURITY_0_G1R_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define MISCREG_NVDEC_LS_SECURITY_0_G1R_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define MISCREG_NVDEC_LS_SECURITY_0_G0R_SHIFT                   _MK_SHIFT_CONST(0)
#define MISCREG_NVDEC_LS_SECURITY_0_G0R_FIELD                   _MK_FIELD_CONST(0x1, MISCREG_NVDEC_LS_SECURITY_0_G0R_SHIFT)
#define MISCREG_NVDEC_LS_SECURITY_0_G0R_RANGE                   0:0
#define MISCREG_NVDEC_LS_SECURITY_0_G0R_WOFFSET                 0x0
#define MISCREG_NVDEC_LS_SECURITY_0_G0R_DEFAULT                 _MK_MASK_CONST(0x1)
#define MISCREG_NVDEC_LS_SECURITY_0_G0R_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define MISCREG_NVDEC_LS_SECURITY_0_G0R_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define MISCREG_NVDEC_LS_SECURITY_0_G0R_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define MISCREG_NVDEC_LS_SECURITY_0_G0R_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define MISCREG_NVDEC_LS_SECURITY_0_G0R_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)


// Register MISCREG_RCE_SECURITY_0
#define MISCREG_RCE_SECURITY_0                  _MK_ADDR_CONST(0x1040)
#define MISCREG_RCE_SECURITY_0_SECURE                   0x0
#define MISCREG_RCE_SECURITY_0_DUAL                     0x0
#define MISCREG_RCE_SECURITY_0_SCR                      SCRRCE_0
#define MISCREG_RCE_SECURITY_0_WORD_COUNT                       0x1
#define MISCREG_RCE_SECURITY_0_RESET_VAL                        _MK_MASK_CONST(0xeffff)
#define MISCREG_RCE_SECURITY_0_RESET_MASK                       _MK_MASK_CONST(0xfffff)
#define MISCREG_RCE_SECURITY_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define MISCREG_RCE_SECURITY_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define MISCREG_RCE_SECURITY_0_READ_MASK                        _MK_MASK_CONST(0xfffff)
#define MISCREG_RCE_SECURITY_0_WRITE_MASK                       _MK_MASK_CONST(0xffff)
#define MISCREG_RCE_SECURITY_0_MSTR_ID_SHIFT                    _MK_SHIFT_CONST(16)
#define MISCREG_RCE_SECURITY_0_MSTR_ID_FIELD                    _MK_FIELD_CONST(0xf, MISCREG_RCE_SECURITY_0_MSTR_ID_SHIFT)
#define MISCREG_RCE_SECURITY_0_MSTR_ID_RANGE                    19:16
#define MISCREG_RCE_SECURITY_0_MSTR_ID_WOFFSET                  0x0
#define MISCREG_RCE_SECURITY_0_MSTR_ID_DEFAULT                  _MK_MASK_CONST(0xe)
#define MISCREG_RCE_SECURITY_0_MSTR_ID_DEFAULT_MASK                     _MK_MASK_CONST(0xf)
#define MISCREG_RCE_SECURITY_0_MSTR_ID_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define MISCREG_RCE_SECURITY_0_MSTR_ID_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define MISCREG_RCE_SECURITY_0_MSTR_ID_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define MISCREG_RCE_SECURITY_0_MSTR_ID_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)
#define MISCREG_RCE_SECURITY_0_MSTR_ID_CCPLEX                   _MK_ENUM_CONST(1)
#define MISCREG_RCE_SECURITY_0_MSTR_ID_CCPLEX_DPMU                      _MK_ENUM_CONST(2)
#define MISCREG_RCE_SECURITY_0_MSTR_ID_BPMP                     _MK_ENUM_CONST(3)
#define MISCREG_RCE_SECURITY_0_MSTR_ID_SPE                      _MK_ENUM_CONST(4)
#define MISCREG_RCE_SECURITY_0_MSTR_ID_SCE                      _MK_ENUM_CONST(5)
#define MISCREG_RCE_SECURITY_0_MSTR_ID_DMA_PER                  _MK_ENUM_CONST(6)
#define MISCREG_RCE_SECURITY_0_MSTR_ID_TSECA                    _MK_ENUM_CONST(7)
#define MISCREG_RCE_SECURITY_0_MSTR_ID_TSECB                    _MK_ENUM_CONST(8)
#define MISCREG_RCE_SECURITY_0_MSTR_ID_JTAGM                    _MK_ENUM_CONST(9)
#define MISCREG_RCE_SECURITY_0_MSTR_ID_CSITE                    _MK_ENUM_CONST(10)
#define MISCREG_RCE_SECURITY_0_MSTR_ID_APE                      _MK_ENUM_CONST(11)
#define MISCREG_RCE_SECURITY_0_MSTR_ID_Peatrans                 _MK_ENUM_CONST(12)
#define MISCREG_RCE_SECURITY_0_MSTR_ID_NVDEC                    _MK_ENUM_CONST(13)
#define MISCREG_RCE_SECURITY_0_MSTR_ID_RCE                      _MK_ENUM_CONST(14)
#define MISCREG_RCE_SECURITY_0_MSTR_ID_NVDEC1                   _MK_ENUM_CONST(15)

#define MISCREG_RCE_SECURITY_0_G7W_SHIFT                        _MK_SHIFT_CONST(15)
#define MISCREG_RCE_SECURITY_0_G7W_FIELD                        _MK_FIELD_CONST(0x1, MISCREG_RCE_SECURITY_0_G7W_SHIFT)
#define MISCREG_RCE_SECURITY_0_G7W_RANGE                        15:15
#define MISCREG_RCE_SECURITY_0_G7W_WOFFSET                      0x0
#define MISCREG_RCE_SECURITY_0_G7W_DEFAULT                      _MK_MASK_CONST(0x1)
#define MISCREG_RCE_SECURITY_0_G7W_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define MISCREG_RCE_SECURITY_0_G7W_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define MISCREG_RCE_SECURITY_0_G7W_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define MISCREG_RCE_SECURITY_0_G7W_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define MISCREG_RCE_SECURITY_0_G7W_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define MISCREG_RCE_SECURITY_0_G6W_SHIFT                        _MK_SHIFT_CONST(14)
#define MISCREG_RCE_SECURITY_0_G6W_FIELD                        _MK_FIELD_CONST(0x1, MISCREG_RCE_SECURITY_0_G6W_SHIFT)
#define MISCREG_RCE_SECURITY_0_G6W_RANGE                        14:14
#define MISCREG_RCE_SECURITY_0_G6W_WOFFSET                      0x0
#define MISCREG_RCE_SECURITY_0_G6W_DEFAULT                      _MK_MASK_CONST(0x1)
#define MISCREG_RCE_SECURITY_0_G6W_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define MISCREG_RCE_SECURITY_0_G6W_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define MISCREG_RCE_SECURITY_0_G6W_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define MISCREG_RCE_SECURITY_0_G6W_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define MISCREG_RCE_SECURITY_0_G6W_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define MISCREG_RCE_SECURITY_0_G5W_SHIFT                        _MK_SHIFT_CONST(13)
#define MISCREG_RCE_SECURITY_0_G5W_FIELD                        _MK_FIELD_CONST(0x1, MISCREG_RCE_SECURITY_0_G5W_SHIFT)
#define MISCREG_RCE_SECURITY_0_G5W_RANGE                        13:13
#define MISCREG_RCE_SECURITY_0_G5W_WOFFSET                      0x0
#define MISCREG_RCE_SECURITY_0_G5W_DEFAULT                      _MK_MASK_CONST(0x1)
#define MISCREG_RCE_SECURITY_0_G5W_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define MISCREG_RCE_SECURITY_0_G5W_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define MISCREG_RCE_SECURITY_0_G5W_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define MISCREG_RCE_SECURITY_0_G5W_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define MISCREG_RCE_SECURITY_0_G5W_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define MISCREG_RCE_SECURITY_0_G4W_SHIFT                        _MK_SHIFT_CONST(12)
#define MISCREG_RCE_SECURITY_0_G4W_FIELD                        _MK_FIELD_CONST(0x1, MISCREG_RCE_SECURITY_0_G4W_SHIFT)
#define MISCREG_RCE_SECURITY_0_G4W_RANGE                        12:12
#define MISCREG_RCE_SECURITY_0_G4W_WOFFSET                      0x0
#define MISCREG_RCE_SECURITY_0_G4W_DEFAULT                      _MK_MASK_CONST(0x1)
#define MISCREG_RCE_SECURITY_0_G4W_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define MISCREG_RCE_SECURITY_0_G4W_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define MISCREG_RCE_SECURITY_0_G4W_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define MISCREG_RCE_SECURITY_0_G4W_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define MISCREG_RCE_SECURITY_0_G4W_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define MISCREG_RCE_SECURITY_0_G3W_SHIFT                        _MK_SHIFT_CONST(11)
#define MISCREG_RCE_SECURITY_0_G3W_FIELD                        _MK_FIELD_CONST(0x1, MISCREG_RCE_SECURITY_0_G3W_SHIFT)
#define MISCREG_RCE_SECURITY_0_G3W_RANGE                        11:11
#define MISCREG_RCE_SECURITY_0_G3W_WOFFSET                      0x0
#define MISCREG_RCE_SECURITY_0_G3W_DEFAULT                      _MK_MASK_CONST(0x1)
#define MISCREG_RCE_SECURITY_0_G3W_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define MISCREG_RCE_SECURITY_0_G3W_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define MISCREG_RCE_SECURITY_0_G3W_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define MISCREG_RCE_SECURITY_0_G3W_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define MISCREG_RCE_SECURITY_0_G3W_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define MISCREG_RCE_SECURITY_0_G2W_SHIFT                        _MK_SHIFT_CONST(10)
#define MISCREG_RCE_SECURITY_0_G2W_FIELD                        _MK_FIELD_CONST(0x1, MISCREG_RCE_SECURITY_0_G2W_SHIFT)
#define MISCREG_RCE_SECURITY_0_G2W_RANGE                        10:10
#define MISCREG_RCE_SECURITY_0_G2W_WOFFSET                      0x0
#define MISCREG_RCE_SECURITY_0_G2W_DEFAULT                      _MK_MASK_CONST(0x1)
#define MISCREG_RCE_SECURITY_0_G2W_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define MISCREG_RCE_SECURITY_0_G2W_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define MISCREG_RCE_SECURITY_0_G2W_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define MISCREG_RCE_SECURITY_0_G2W_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define MISCREG_RCE_SECURITY_0_G2W_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define MISCREG_RCE_SECURITY_0_G1W_SHIFT                        _MK_SHIFT_CONST(9)
#define MISCREG_RCE_SECURITY_0_G1W_FIELD                        _MK_FIELD_CONST(0x1, MISCREG_RCE_SECURITY_0_G1W_SHIFT)
#define MISCREG_RCE_SECURITY_0_G1W_RANGE                        9:9
#define MISCREG_RCE_SECURITY_0_G1W_WOFFSET                      0x0
#define MISCREG_RCE_SECURITY_0_G1W_DEFAULT                      _MK_MASK_CONST(0x1)
#define MISCREG_RCE_SECURITY_0_G1W_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define MISCREG_RCE_SECURITY_0_G1W_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define MISCREG_RCE_SECURITY_0_G1W_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define MISCREG_RCE_SECURITY_0_G1W_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define MISCREG_RCE_SECURITY_0_G1W_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define MISCREG_RCE_SECURITY_0_G0W_SHIFT                        _MK_SHIFT_CONST(8)
#define MISCREG_RCE_SECURITY_0_G0W_FIELD                        _MK_FIELD_CONST(0x1, MISCREG_RCE_SECURITY_0_G0W_SHIFT)
#define MISCREG_RCE_SECURITY_0_G0W_RANGE                        8:8
#define MISCREG_RCE_SECURITY_0_G0W_WOFFSET                      0x0
#define MISCREG_RCE_SECURITY_0_G0W_DEFAULT                      _MK_MASK_CONST(0x1)
#define MISCREG_RCE_SECURITY_0_G0W_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define MISCREG_RCE_SECURITY_0_G0W_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define MISCREG_RCE_SECURITY_0_G0W_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define MISCREG_RCE_SECURITY_0_G0W_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define MISCREG_RCE_SECURITY_0_G0W_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define MISCREG_RCE_SECURITY_0_G7R_SHIFT                        _MK_SHIFT_CONST(7)
#define MISCREG_RCE_SECURITY_0_G7R_FIELD                        _MK_FIELD_CONST(0x1, MISCREG_RCE_SECURITY_0_G7R_SHIFT)
#define MISCREG_RCE_SECURITY_0_G7R_RANGE                        7:7
#define MISCREG_RCE_SECURITY_0_G7R_WOFFSET                      0x0
#define MISCREG_RCE_SECURITY_0_G7R_DEFAULT                      _MK_MASK_CONST(0x1)
#define MISCREG_RCE_SECURITY_0_G7R_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define MISCREG_RCE_SECURITY_0_G7R_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define MISCREG_RCE_SECURITY_0_G7R_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define MISCREG_RCE_SECURITY_0_G7R_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define MISCREG_RCE_SECURITY_0_G7R_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define MISCREG_RCE_SECURITY_0_G6R_SHIFT                        _MK_SHIFT_CONST(6)
#define MISCREG_RCE_SECURITY_0_G6R_FIELD                        _MK_FIELD_CONST(0x1, MISCREG_RCE_SECURITY_0_G6R_SHIFT)
#define MISCREG_RCE_SECURITY_0_G6R_RANGE                        6:6
#define MISCREG_RCE_SECURITY_0_G6R_WOFFSET                      0x0
#define MISCREG_RCE_SECURITY_0_G6R_DEFAULT                      _MK_MASK_CONST(0x1)
#define MISCREG_RCE_SECURITY_0_G6R_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define MISCREG_RCE_SECURITY_0_G6R_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define MISCREG_RCE_SECURITY_0_G6R_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define MISCREG_RCE_SECURITY_0_G6R_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define MISCREG_RCE_SECURITY_0_G6R_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define MISCREG_RCE_SECURITY_0_G5R_SHIFT                        _MK_SHIFT_CONST(5)
#define MISCREG_RCE_SECURITY_0_G5R_FIELD                        _MK_FIELD_CONST(0x1, MISCREG_RCE_SECURITY_0_G5R_SHIFT)
#define MISCREG_RCE_SECURITY_0_G5R_RANGE                        5:5
#define MISCREG_RCE_SECURITY_0_G5R_WOFFSET                      0x0
#define MISCREG_RCE_SECURITY_0_G5R_DEFAULT                      _MK_MASK_CONST(0x1)
#define MISCREG_RCE_SECURITY_0_G5R_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define MISCREG_RCE_SECURITY_0_G5R_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define MISCREG_RCE_SECURITY_0_G5R_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define MISCREG_RCE_SECURITY_0_G5R_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define MISCREG_RCE_SECURITY_0_G5R_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define MISCREG_RCE_SECURITY_0_G4R_SHIFT                        _MK_SHIFT_CONST(4)
#define MISCREG_RCE_SECURITY_0_G4R_FIELD                        _MK_FIELD_CONST(0x1, MISCREG_RCE_SECURITY_0_G4R_SHIFT)
#define MISCREG_RCE_SECURITY_0_G4R_RANGE                        4:4
#define MISCREG_RCE_SECURITY_0_G4R_WOFFSET                      0x0
#define MISCREG_RCE_SECURITY_0_G4R_DEFAULT                      _MK_MASK_CONST(0x1)
#define MISCREG_RCE_SECURITY_0_G4R_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define MISCREG_RCE_SECURITY_0_G4R_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define MISCREG_RCE_SECURITY_0_G4R_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define MISCREG_RCE_SECURITY_0_G4R_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define MISCREG_RCE_SECURITY_0_G4R_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define MISCREG_RCE_SECURITY_0_G3R_SHIFT                        _MK_SHIFT_CONST(3)
#define MISCREG_RCE_SECURITY_0_G3R_FIELD                        _MK_FIELD_CONST(0x1, MISCREG_RCE_SECURITY_0_G3R_SHIFT)
#define MISCREG_RCE_SECURITY_0_G3R_RANGE                        3:3
#define MISCREG_RCE_SECURITY_0_G3R_WOFFSET                      0x0
#define MISCREG_RCE_SECURITY_0_G3R_DEFAULT                      _MK_MASK_CONST(0x1)
#define MISCREG_RCE_SECURITY_0_G3R_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define MISCREG_RCE_SECURITY_0_G3R_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define MISCREG_RCE_SECURITY_0_G3R_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define MISCREG_RCE_SECURITY_0_G3R_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define MISCREG_RCE_SECURITY_0_G3R_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define MISCREG_RCE_SECURITY_0_G2R_SHIFT                        _MK_SHIFT_CONST(2)
#define MISCREG_RCE_SECURITY_0_G2R_FIELD                        _MK_FIELD_CONST(0x1, MISCREG_RCE_SECURITY_0_G2R_SHIFT)
#define MISCREG_RCE_SECURITY_0_G2R_RANGE                        2:2
#define MISCREG_RCE_SECURITY_0_G2R_WOFFSET                      0x0
#define MISCREG_RCE_SECURITY_0_G2R_DEFAULT                      _MK_MASK_CONST(0x1)
#define MISCREG_RCE_SECURITY_0_G2R_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define MISCREG_RCE_SECURITY_0_G2R_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define MISCREG_RCE_SECURITY_0_G2R_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define MISCREG_RCE_SECURITY_0_G2R_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define MISCREG_RCE_SECURITY_0_G2R_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define MISCREG_RCE_SECURITY_0_G1R_SHIFT                        _MK_SHIFT_CONST(1)
#define MISCREG_RCE_SECURITY_0_G1R_FIELD                        _MK_FIELD_CONST(0x1, MISCREG_RCE_SECURITY_0_G1R_SHIFT)
#define MISCREG_RCE_SECURITY_0_G1R_RANGE                        1:1
#define MISCREG_RCE_SECURITY_0_G1R_WOFFSET                      0x0
#define MISCREG_RCE_SECURITY_0_G1R_DEFAULT                      _MK_MASK_CONST(0x1)
#define MISCREG_RCE_SECURITY_0_G1R_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define MISCREG_RCE_SECURITY_0_G1R_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define MISCREG_RCE_SECURITY_0_G1R_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define MISCREG_RCE_SECURITY_0_G1R_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define MISCREG_RCE_SECURITY_0_G1R_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define MISCREG_RCE_SECURITY_0_G0R_SHIFT                        _MK_SHIFT_CONST(0)
#define MISCREG_RCE_SECURITY_0_G0R_FIELD                        _MK_FIELD_CONST(0x1, MISCREG_RCE_SECURITY_0_G0R_SHIFT)
#define MISCREG_RCE_SECURITY_0_G0R_RANGE                        0:0
#define MISCREG_RCE_SECURITY_0_G0R_WOFFSET                      0x0
#define MISCREG_RCE_SECURITY_0_G0R_DEFAULT                      _MK_MASK_CONST(0x1)
#define MISCREG_RCE_SECURITY_0_G0R_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define MISCREG_RCE_SECURITY_0_G0R_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define MISCREG_RCE_SECURITY_0_G0R_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define MISCREG_RCE_SECURITY_0_G0R_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define MISCREG_RCE_SECURITY_0_G0R_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)


// Reserved address 0x1044

// Reserved address 0x1048

// Reserved address 0x104c

// Register MISCREG_LPI_CONFIG_0
#define MISCREG_LPI_CONFIG_0                    _MK_ADDR_CONST(0x1050)
#define MISCREG_LPI_CONFIG_0_SECURE                     0x0
#define MISCREG_LPI_CONFIG_0_DUAL                       0x0
#define MISCREG_LPI_CONFIG_0_SCR                        SCRLPI_0
#define MISCREG_LPI_CONFIG_0_WORD_COUNT                         0x1
#define MISCREG_LPI_CONFIG_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define MISCREG_LPI_CONFIG_0_RESET_MASK                         _MK_MASK_CONST(0xfc0ffc3e)
#define MISCREG_LPI_CONFIG_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define MISCREG_LPI_CONFIG_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define MISCREG_LPI_CONFIG_0_READ_MASK                  _MK_MASK_CONST(0xfc0ffc3e)
#define MISCREG_LPI_CONFIG_0_WRITE_MASK                         _MK_MASK_CONST(0xfc0ffc3e)
#define MISCREG_LPI_CONFIG_0_EN_LP_SHIFT                        _MK_SHIFT_CONST(31)
#define MISCREG_LPI_CONFIG_0_EN_LP_FIELD                        _MK_FIELD_CONST(0x1, MISCREG_LPI_CONFIG_0_EN_LP_SHIFT)
#define MISCREG_LPI_CONFIG_0_EN_LP_RANGE                        31:31
#define MISCREG_LPI_CONFIG_0_EN_LP_WOFFSET                      0x0
#define MISCREG_LPI_CONFIG_0_EN_LP_DEFAULT                      _MK_MASK_CONST(0x0)
#define MISCREG_LPI_CONFIG_0_EN_LP_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define MISCREG_LPI_CONFIG_0_EN_LP_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define MISCREG_LPI_CONFIG_0_EN_LP_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define MISCREG_LPI_CONFIG_0_EN_LP_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define MISCREG_LPI_CONFIG_0_EN_LP_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)
#define MISCREG_LPI_CONFIG_0_EN_LP_DISABLED                     _MK_ENUM_CONST(0)
#define MISCREG_LPI_CONFIG_0_EN_LP_ENABLED                      _MK_ENUM_CONST(1)

#define MISCREG_LPI_CONFIG_0_SNIC_CLK_GATING_MODE_SHIFT                 _MK_SHIFT_CONST(30)
#define MISCREG_LPI_CONFIG_0_SNIC_CLK_GATING_MODE_FIELD                 _MK_FIELD_CONST(0x1, MISCREG_LPI_CONFIG_0_SNIC_CLK_GATING_MODE_SHIFT)
#define MISCREG_LPI_CONFIG_0_SNIC_CLK_GATING_MODE_RANGE                 30:30
#define MISCREG_LPI_CONFIG_0_SNIC_CLK_GATING_MODE_WOFFSET                       0x0
#define MISCREG_LPI_CONFIG_0_SNIC_CLK_GATING_MODE_DEFAULT                       _MK_MASK_CONST(0x0)
#define MISCREG_LPI_CONFIG_0_SNIC_CLK_GATING_MODE_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define MISCREG_LPI_CONFIG_0_SNIC_CLK_GATING_MODE_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define MISCREG_LPI_CONFIG_0_SNIC_CLK_GATING_MODE_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define MISCREG_LPI_CONFIG_0_SNIC_CLK_GATING_MODE_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define MISCREG_LPI_CONFIG_0_SNIC_CLK_GATING_MODE_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)
#define MISCREG_LPI_CONFIG_0_SNIC_CLK_GATING_MODE_DISABLED                      _MK_ENUM_CONST(0)
#define MISCREG_LPI_CONFIG_0_SNIC_CLK_GATING_MODE_ENABLED                       _MK_ENUM_CONST(1)

#define MISCREG_LPI_CONFIG_0_DMA_ACT_MASK_SHIFT                 _MK_SHIFT_CONST(29)
#define MISCREG_LPI_CONFIG_0_DMA_ACT_MASK_FIELD                 _MK_FIELD_CONST(0x1, MISCREG_LPI_CONFIG_0_DMA_ACT_MASK_SHIFT)
#define MISCREG_LPI_CONFIG_0_DMA_ACT_MASK_RANGE                 29:29
#define MISCREG_LPI_CONFIG_0_DMA_ACT_MASK_WOFFSET                       0x0
#define MISCREG_LPI_CONFIG_0_DMA_ACT_MASK_DEFAULT                       _MK_MASK_CONST(0x0)
#define MISCREG_LPI_CONFIG_0_DMA_ACT_MASK_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define MISCREG_LPI_CONFIG_0_DMA_ACT_MASK_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define MISCREG_LPI_CONFIG_0_DMA_ACT_MASK_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define MISCREG_LPI_CONFIG_0_DMA_ACT_MASK_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define MISCREG_LPI_CONFIG_0_DMA_ACT_MASK_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)
#define MISCREG_LPI_CONFIG_0_DMA_ACT_MASK_ENABLED                       _MK_ENUM_CONST(0)
#define MISCREG_LPI_CONFIG_0_DMA_ACT_MASK_MASKED                        _MK_ENUM_CONST(1)

#define MISCREG_LPI_CONFIG_0_CORESIGHT_ACT_MASK_SHIFT                   _MK_SHIFT_CONST(28)
#define MISCREG_LPI_CONFIG_0_CORESIGHT_ACT_MASK_FIELD                   _MK_FIELD_CONST(0x1, MISCREG_LPI_CONFIG_0_CORESIGHT_ACT_MASK_SHIFT)
#define MISCREG_LPI_CONFIG_0_CORESIGHT_ACT_MASK_RANGE                   28:28
#define MISCREG_LPI_CONFIG_0_CORESIGHT_ACT_MASK_WOFFSET                 0x0
#define MISCREG_LPI_CONFIG_0_CORESIGHT_ACT_MASK_DEFAULT                 _MK_MASK_CONST(0x0)
#define MISCREG_LPI_CONFIG_0_CORESIGHT_ACT_MASK_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define MISCREG_LPI_CONFIG_0_CORESIGHT_ACT_MASK_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define MISCREG_LPI_CONFIG_0_CORESIGHT_ACT_MASK_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define MISCREG_LPI_CONFIG_0_CORESIGHT_ACT_MASK_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define MISCREG_LPI_CONFIG_0_CORESIGHT_ACT_MASK_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define MISCREG_LPI_CONFIG_0_CORESIGHT_ACT_MASK_ENABLED                 _MK_ENUM_CONST(0)
#define MISCREG_LPI_CONFIG_0_CORESIGHT_ACT_MASK_MASKED                  _MK_ENUM_CONST(1)

#define MISCREG_LPI_CONFIG_0_JTAGM_ACT_MASK_SHIFT                       _MK_SHIFT_CONST(27)
#define MISCREG_LPI_CONFIG_0_JTAGM_ACT_MASK_FIELD                       _MK_FIELD_CONST(0x1, MISCREG_LPI_CONFIG_0_JTAGM_ACT_MASK_SHIFT)
#define MISCREG_LPI_CONFIG_0_JTAGM_ACT_MASK_RANGE                       27:27
#define MISCREG_LPI_CONFIG_0_JTAGM_ACT_MASK_WOFFSET                     0x0
#define MISCREG_LPI_CONFIG_0_JTAGM_ACT_MASK_DEFAULT                     _MK_MASK_CONST(0x0)
#define MISCREG_LPI_CONFIG_0_JTAGM_ACT_MASK_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define MISCREG_LPI_CONFIG_0_JTAGM_ACT_MASK_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define MISCREG_LPI_CONFIG_0_JTAGM_ACT_MASK_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define MISCREG_LPI_CONFIG_0_JTAGM_ACT_MASK_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define MISCREG_LPI_CONFIG_0_JTAGM_ACT_MASK_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define MISCREG_LPI_CONFIG_0_JTAGM_ACT_MASK_ENABLED                     _MK_ENUM_CONST(0)
#define MISCREG_LPI_CONFIG_0_JTAGM_ACT_MASK_MASKED                      _MK_ENUM_CONST(1)

#define MISCREG_LPI_CONFIG_0_SNIC_ACT_MASK_SHIFT                        _MK_SHIFT_CONST(26)
#define MISCREG_LPI_CONFIG_0_SNIC_ACT_MASK_FIELD                        _MK_FIELD_CONST(0x1, MISCREG_LPI_CONFIG_0_SNIC_ACT_MASK_SHIFT)
#define MISCREG_LPI_CONFIG_0_SNIC_ACT_MASK_RANGE                        26:26
#define MISCREG_LPI_CONFIG_0_SNIC_ACT_MASK_WOFFSET                      0x0
#define MISCREG_LPI_CONFIG_0_SNIC_ACT_MASK_DEFAULT                      _MK_MASK_CONST(0x0)
#define MISCREG_LPI_CONFIG_0_SNIC_ACT_MASK_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define MISCREG_LPI_CONFIG_0_SNIC_ACT_MASK_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define MISCREG_LPI_CONFIG_0_SNIC_ACT_MASK_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define MISCREG_LPI_CONFIG_0_SNIC_ACT_MASK_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define MISCREG_LPI_CONFIG_0_SNIC_ACT_MASK_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)
#define MISCREG_LPI_CONFIG_0_SNIC_ACT_MASK_ENABLED                      _MK_ENUM_CONST(0)
#define MISCREG_LPI_CONFIG_0_SNIC_ACT_MASK_MASKED                       _MK_ENUM_CONST(1)

#define MISCREG_LPI_CONFIG_0_SMMU_ACT_MASK_SHIFT                        _MK_SHIFT_CONST(19)
#define MISCREG_LPI_CONFIG_0_SMMU_ACT_MASK_FIELD                        _MK_FIELD_CONST(0x1, MISCREG_LPI_CONFIG_0_SMMU_ACT_MASK_SHIFT)
#define MISCREG_LPI_CONFIG_0_SMMU_ACT_MASK_RANGE                        19:19
#define MISCREG_LPI_CONFIG_0_SMMU_ACT_MASK_WOFFSET                      0x0
#define MISCREG_LPI_CONFIG_0_SMMU_ACT_MASK_DEFAULT                      _MK_MASK_CONST(0x0)
#define MISCREG_LPI_CONFIG_0_SMMU_ACT_MASK_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define MISCREG_LPI_CONFIG_0_SMMU_ACT_MASK_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define MISCREG_LPI_CONFIG_0_SMMU_ACT_MASK_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define MISCREG_LPI_CONFIG_0_SMMU_ACT_MASK_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define MISCREG_LPI_CONFIG_0_SMMU_ACT_MASK_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)
#define MISCREG_LPI_CONFIG_0_SMMU_ACT_MASK_ENABLED                      _MK_ENUM_CONST(0)
#define MISCREG_LPI_CONFIG_0_SMMU_ACT_MASK_MASKED                       _MK_ENUM_CONST(1)

#define MISCREG_LPI_CONFIG_0_CPU_ACT_MASK_SHIFT                 _MK_SHIFT_CONST(18)
#define MISCREG_LPI_CONFIG_0_CPU_ACT_MASK_FIELD                 _MK_FIELD_CONST(0x1, MISCREG_LPI_CONFIG_0_CPU_ACT_MASK_SHIFT)
#define MISCREG_LPI_CONFIG_0_CPU_ACT_MASK_RANGE                 18:18
#define MISCREG_LPI_CONFIG_0_CPU_ACT_MASK_WOFFSET                       0x0
#define MISCREG_LPI_CONFIG_0_CPU_ACT_MASK_DEFAULT                       _MK_MASK_CONST(0x0)
#define MISCREG_LPI_CONFIG_0_CPU_ACT_MASK_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define MISCREG_LPI_CONFIG_0_CPU_ACT_MASK_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define MISCREG_LPI_CONFIG_0_CPU_ACT_MASK_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define MISCREG_LPI_CONFIG_0_CPU_ACT_MASK_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define MISCREG_LPI_CONFIG_0_CPU_ACT_MASK_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)
#define MISCREG_LPI_CONFIG_0_CPU_ACT_MASK_ENABLED                       _MK_ENUM_CONST(0)
#define MISCREG_LPI_CONFIG_0_CPU_ACT_MASK_MASKED                        _MK_ENUM_CONST(1)

#define MISCREG_LPI_CONFIG_0_HOST1X_ACT_MASK_SHIFT                      _MK_SHIFT_CONST(17)
#define MISCREG_LPI_CONFIG_0_HOST1X_ACT_MASK_FIELD                      _MK_FIELD_CONST(0x1, MISCREG_LPI_CONFIG_0_HOST1X_ACT_MASK_SHIFT)
#define MISCREG_LPI_CONFIG_0_HOST1X_ACT_MASK_RANGE                      17:17
#define MISCREG_LPI_CONFIG_0_HOST1X_ACT_MASK_WOFFSET                    0x0
#define MISCREG_LPI_CONFIG_0_HOST1X_ACT_MASK_DEFAULT                    _MK_MASK_CONST(0x0)
#define MISCREG_LPI_CONFIG_0_HOST1X_ACT_MASK_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define MISCREG_LPI_CONFIG_0_HOST1X_ACT_MASK_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define MISCREG_LPI_CONFIG_0_HOST1X_ACT_MASK_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define MISCREG_LPI_CONFIG_0_HOST1X_ACT_MASK_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define MISCREG_LPI_CONFIG_0_HOST1X_ACT_MASK_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define MISCREG_LPI_CONFIG_0_HOST1X_ACT_MASK_ENABLED                    _MK_ENUM_CONST(0)
#define MISCREG_LPI_CONFIG_0_HOST1X_ACT_MASK_MASKED                     _MK_ENUM_CONST(1)

#define MISCREG_LPI_CONFIG_0_PCIE_ACT_MASK_SHIFT                        _MK_SHIFT_CONST(16)
#define MISCREG_LPI_CONFIG_0_PCIE_ACT_MASK_FIELD                        _MK_FIELD_CONST(0x1, MISCREG_LPI_CONFIG_0_PCIE_ACT_MASK_SHIFT)
#define MISCREG_LPI_CONFIG_0_PCIE_ACT_MASK_RANGE                        16:16
#define MISCREG_LPI_CONFIG_0_PCIE_ACT_MASK_WOFFSET                      0x0
#define MISCREG_LPI_CONFIG_0_PCIE_ACT_MASK_DEFAULT                      _MK_MASK_CONST(0x0)
#define MISCREG_LPI_CONFIG_0_PCIE_ACT_MASK_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define MISCREG_LPI_CONFIG_0_PCIE_ACT_MASK_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define MISCREG_LPI_CONFIG_0_PCIE_ACT_MASK_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define MISCREG_LPI_CONFIG_0_PCIE_ACT_MASK_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define MISCREG_LPI_CONFIG_0_PCIE_ACT_MASK_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)
#define MISCREG_LPI_CONFIG_0_PCIE_ACT_MASK_ENABLED                      _MK_ENUM_CONST(0)
#define MISCREG_LPI_CONFIG_0_PCIE_ACT_MASK_MASKED                       _MK_ENUM_CONST(1)

#define MISCREG_LPI_CONFIG_0_GPU_ACT_MASK_SHIFT                 _MK_SHIFT_CONST(15)
#define MISCREG_LPI_CONFIG_0_GPU_ACT_MASK_FIELD                 _MK_FIELD_CONST(0x1, MISCREG_LPI_CONFIG_0_GPU_ACT_MASK_SHIFT)
#define MISCREG_LPI_CONFIG_0_GPU_ACT_MASK_RANGE                 15:15
#define MISCREG_LPI_CONFIG_0_GPU_ACT_MASK_WOFFSET                       0x0
#define MISCREG_LPI_CONFIG_0_GPU_ACT_MASK_DEFAULT                       _MK_MASK_CONST(0x0)
#define MISCREG_LPI_CONFIG_0_GPU_ACT_MASK_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define MISCREG_LPI_CONFIG_0_GPU_ACT_MASK_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define MISCREG_LPI_CONFIG_0_GPU_ACT_MASK_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define MISCREG_LPI_CONFIG_0_GPU_ACT_MASK_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define MISCREG_LPI_CONFIG_0_GPU_ACT_MASK_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)
#define MISCREG_LPI_CONFIG_0_GPU_ACT_MASK_ENABLED                       _MK_ENUM_CONST(0)
#define MISCREG_LPI_CONFIG_0_GPU_ACT_MASK_MASKED                        _MK_ENUM_CONST(1)

#define MISCREG_LPI_CONFIG_0_APE_ACT_MASK_SHIFT                 _MK_SHIFT_CONST(14)
#define MISCREG_LPI_CONFIG_0_APE_ACT_MASK_FIELD                 _MK_FIELD_CONST(0x1, MISCREG_LPI_CONFIG_0_APE_ACT_MASK_SHIFT)
#define MISCREG_LPI_CONFIG_0_APE_ACT_MASK_RANGE                 14:14
#define MISCREG_LPI_CONFIG_0_APE_ACT_MASK_WOFFSET                       0x0
#define MISCREG_LPI_CONFIG_0_APE_ACT_MASK_DEFAULT                       _MK_MASK_CONST(0x0)
#define MISCREG_LPI_CONFIG_0_APE_ACT_MASK_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define MISCREG_LPI_CONFIG_0_APE_ACT_MASK_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define MISCREG_LPI_CONFIG_0_APE_ACT_MASK_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define MISCREG_LPI_CONFIG_0_APE_ACT_MASK_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define MISCREG_LPI_CONFIG_0_APE_ACT_MASK_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)
#define MISCREG_LPI_CONFIG_0_APE_ACT_MASK_ENABLED                       _MK_ENUM_CONST(0)
#define MISCREG_LPI_CONFIG_0_APE_ACT_MASK_MASKED                        _MK_ENUM_CONST(1)

#define MISCREG_LPI_CONFIG_0_SSPE_ACT_MASK_SHIFT                        _MK_SHIFT_CONST(13)
#define MISCREG_LPI_CONFIG_0_SSPE_ACT_MASK_FIELD                        _MK_FIELD_CONST(0x1, MISCREG_LPI_CONFIG_0_SSPE_ACT_MASK_SHIFT)
#define MISCREG_LPI_CONFIG_0_SSPE_ACT_MASK_RANGE                        13:13
#define MISCREG_LPI_CONFIG_0_SSPE_ACT_MASK_WOFFSET                      0x0
#define MISCREG_LPI_CONFIG_0_SSPE_ACT_MASK_DEFAULT                      _MK_MASK_CONST(0x0)
#define MISCREG_LPI_CONFIG_0_SSPE_ACT_MASK_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define MISCREG_LPI_CONFIG_0_SSPE_ACT_MASK_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define MISCREG_LPI_CONFIG_0_SSPE_ACT_MASK_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define MISCREG_LPI_CONFIG_0_SSPE_ACT_MASK_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define MISCREG_LPI_CONFIG_0_SSPE_ACT_MASK_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)
#define MISCREG_LPI_CONFIG_0_SSPE_ACT_MASK_ENABLED                      _MK_ENUM_CONST(0)
#define MISCREG_LPI_CONFIG_0_SSPE_ACT_MASK_MASKED                       _MK_ENUM_CONST(1)

#define MISCREG_LPI_CONFIG_0_MSPE_ACT_MASK_SHIFT                        _MK_SHIFT_CONST(12)
#define MISCREG_LPI_CONFIG_0_MSPE_ACT_MASK_FIELD                        _MK_FIELD_CONST(0x1, MISCREG_LPI_CONFIG_0_MSPE_ACT_MASK_SHIFT)
#define MISCREG_LPI_CONFIG_0_MSPE_ACT_MASK_RANGE                        12:12
#define MISCREG_LPI_CONFIG_0_MSPE_ACT_MASK_WOFFSET                      0x0
#define MISCREG_LPI_CONFIG_0_MSPE_ACT_MASK_DEFAULT                      _MK_MASK_CONST(0x0)
#define MISCREG_LPI_CONFIG_0_MSPE_ACT_MASK_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define MISCREG_LPI_CONFIG_0_MSPE_ACT_MASK_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define MISCREG_LPI_CONFIG_0_MSPE_ACT_MASK_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define MISCREG_LPI_CONFIG_0_MSPE_ACT_MASK_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define MISCREG_LPI_CONFIG_0_MSPE_ACT_MASK_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)
#define MISCREG_LPI_CONFIG_0_MSPE_ACT_MASK_ENABLED                      _MK_ENUM_CONST(0)
#define MISCREG_LPI_CONFIG_0_MSPE_ACT_MASK_MASKED                       _MK_ENUM_CONST(1)

#define MISCREG_LPI_CONFIG_0_BPMP_ACT_MASK_SHIFT                        _MK_SHIFT_CONST(11)
#define MISCREG_LPI_CONFIG_0_BPMP_ACT_MASK_FIELD                        _MK_FIELD_CONST(0x1, MISCREG_LPI_CONFIG_0_BPMP_ACT_MASK_SHIFT)
#define MISCREG_LPI_CONFIG_0_BPMP_ACT_MASK_RANGE                        11:11
#define MISCREG_LPI_CONFIG_0_BPMP_ACT_MASK_WOFFSET                      0x0
#define MISCREG_LPI_CONFIG_0_BPMP_ACT_MASK_DEFAULT                      _MK_MASK_CONST(0x0)
#define MISCREG_LPI_CONFIG_0_BPMP_ACT_MASK_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define MISCREG_LPI_CONFIG_0_BPMP_ACT_MASK_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define MISCREG_LPI_CONFIG_0_BPMP_ACT_MASK_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define MISCREG_LPI_CONFIG_0_BPMP_ACT_MASK_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define MISCREG_LPI_CONFIG_0_BPMP_ACT_MASK_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)
#define MISCREG_LPI_CONFIG_0_BPMP_ACT_MASK_ENABLED                      _MK_ENUM_CONST(0)
#define MISCREG_LPI_CONFIG_0_BPMP_ACT_MASK_MASKED                       _MK_ENUM_CONST(1)

#define MISCREG_LPI_CONFIG_0_SCE_ACT_MASK_SHIFT                 _MK_SHIFT_CONST(10)
#define MISCREG_LPI_CONFIG_0_SCE_ACT_MASK_FIELD                 _MK_FIELD_CONST(0x1, MISCREG_LPI_CONFIG_0_SCE_ACT_MASK_SHIFT)
#define MISCREG_LPI_CONFIG_0_SCE_ACT_MASK_RANGE                 10:10
#define MISCREG_LPI_CONFIG_0_SCE_ACT_MASK_WOFFSET                       0x0
#define MISCREG_LPI_CONFIG_0_SCE_ACT_MASK_DEFAULT                       _MK_MASK_CONST(0x0)
#define MISCREG_LPI_CONFIG_0_SCE_ACT_MASK_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define MISCREG_LPI_CONFIG_0_SCE_ACT_MASK_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define MISCREG_LPI_CONFIG_0_SCE_ACT_MASK_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define MISCREG_LPI_CONFIG_0_SCE_ACT_MASK_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define MISCREG_LPI_CONFIG_0_SCE_ACT_MASK_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)
#define MISCREG_LPI_CONFIG_0_SCE_ACT_MASK_ENABLED                       _MK_ENUM_CONST(0)
#define MISCREG_LPI_CONFIG_0_SCE_ACT_MASK_MASKED                        _MK_ENUM_CONST(1)

#define MISCREG_LPI_CONFIG_0_AXIAPB_BR_ACT_MASK_SHIFT                   _MK_SHIFT_CONST(1)
#define MISCREG_LPI_CONFIG_0_AXIAPB_BR_ACT_MASK_FIELD                   _MK_FIELD_CONST(0x1f, MISCREG_LPI_CONFIG_0_AXIAPB_BR_ACT_MASK_SHIFT)
#define MISCREG_LPI_CONFIG_0_AXIAPB_BR_ACT_MASK_RANGE                   5:1
#define MISCREG_LPI_CONFIG_0_AXIAPB_BR_ACT_MASK_WOFFSET                 0x0
#define MISCREG_LPI_CONFIG_0_AXIAPB_BR_ACT_MASK_DEFAULT                 _MK_MASK_CONST(0x0)
#define MISCREG_LPI_CONFIG_0_AXIAPB_BR_ACT_MASK_DEFAULT_MASK                    _MK_MASK_CONST(0x1f)
#define MISCREG_LPI_CONFIG_0_AXIAPB_BR_ACT_MASK_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define MISCREG_LPI_CONFIG_0_AXIAPB_BR_ACT_MASK_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define MISCREG_LPI_CONFIG_0_AXIAPB_BR_ACT_MASK_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define MISCREG_LPI_CONFIG_0_AXIAPB_BR_ACT_MASK_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define MISCREG_LPI_CONFIG_0_AXIAPB_BR_ACT_MASK_ENABLED                 _MK_ENUM_CONST(0)
#define MISCREG_LPI_CONFIG_0_AXIAPB_BR_ACT_MASK_MASKED                  _MK_ENUM_CONST(1)


// Register MISCREG_LPI_STATUS_0
#define MISCREG_LPI_STATUS_0                    _MK_ADDR_CONST(0x1054)
#define MISCREG_LPI_STATUS_0_SECURE                     0x0
#define MISCREG_LPI_STATUS_0_DUAL                       0x0
#define MISCREG_LPI_STATUS_0_SCR                        SCRLPI_0
#define MISCREG_LPI_STATUS_0_WORD_COUNT                         0x1
#define MISCREG_LPI_STATUS_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define MISCREG_LPI_STATUS_0_RESET_MASK                         _MK_MASK_CONST(0x3c0ffc3e)
#define MISCREG_LPI_STATUS_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define MISCREG_LPI_STATUS_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define MISCREG_LPI_STATUS_0_READ_MASK                  _MK_MASK_CONST(0x3c0ffc3e)
#define MISCREG_LPI_STATUS_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
#define MISCREG_LPI_STATUS_0_DMA_ACTIVITY_SHIFT                 _MK_SHIFT_CONST(29)
#define MISCREG_LPI_STATUS_0_DMA_ACTIVITY_FIELD                 _MK_FIELD_CONST(0x1, MISCREG_LPI_STATUS_0_DMA_ACTIVITY_SHIFT)
#define MISCREG_LPI_STATUS_0_DMA_ACTIVITY_RANGE                 29:29
#define MISCREG_LPI_STATUS_0_DMA_ACTIVITY_WOFFSET                       0x0
#define MISCREG_LPI_STATUS_0_DMA_ACTIVITY_DEFAULT                       _MK_MASK_CONST(0x0)
#define MISCREG_LPI_STATUS_0_DMA_ACTIVITY_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define MISCREG_LPI_STATUS_0_DMA_ACTIVITY_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define MISCREG_LPI_STATUS_0_DMA_ACTIVITY_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define MISCREG_LPI_STATUS_0_DMA_ACTIVITY_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define MISCREG_LPI_STATUS_0_DMA_ACTIVITY_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)

#define MISCREG_LPI_STATUS_0_CORESIGHT_ACTIVITY_SHIFT                   _MK_SHIFT_CONST(28)
#define MISCREG_LPI_STATUS_0_CORESIGHT_ACTIVITY_FIELD                   _MK_FIELD_CONST(0x1, MISCREG_LPI_STATUS_0_CORESIGHT_ACTIVITY_SHIFT)
#define MISCREG_LPI_STATUS_0_CORESIGHT_ACTIVITY_RANGE                   28:28
#define MISCREG_LPI_STATUS_0_CORESIGHT_ACTIVITY_WOFFSET                 0x0
#define MISCREG_LPI_STATUS_0_CORESIGHT_ACTIVITY_DEFAULT                 _MK_MASK_CONST(0x0)
#define MISCREG_LPI_STATUS_0_CORESIGHT_ACTIVITY_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define MISCREG_LPI_STATUS_0_CORESIGHT_ACTIVITY_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define MISCREG_LPI_STATUS_0_CORESIGHT_ACTIVITY_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define MISCREG_LPI_STATUS_0_CORESIGHT_ACTIVITY_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define MISCREG_LPI_STATUS_0_CORESIGHT_ACTIVITY_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define MISCREG_LPI_STATUS_0_JTAGM_ACTIVITY_SHIFT                       _MK_SHIFT_CONST(27)
#define MISCREG_LPI_STATUS_0_JTAGM_ACTIVITY_FIELD                       _MK_FIELD_CONST(0x1, MISCREG_LPI_STATUS_0_JTAGM_ACTIVITY_SHIFT)
#define MISCREG_LPI_STATUS_0_JTAGM_ACTIVITY_RANGE                       27:27
#define MISCREG_LPI_STATUS_0_JTAGM_ACTIVITY_WOFFSET                     0x0
#define MISCREG_LPI_STATUS_0_JTAGM_ACTIVITY_DEFAULT                     _MK_MASK_CONST(0x0)
#define MISCREG_LPI_STATUS_0_JTAGM_ACTIVITY_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define MISCREG_LPI_STATUS_0_JTAGM_ACTIVITY_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define MISCREG_LPI_STATUS_0_JTAGM_ACTIVITY_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define MISCREG_LPI_STATUS_0_JTAGM_ACTIVITY_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define MISCREG_LPI_STATUS_0_JTAGM_ACTIVITY_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define MISCREG_LPI_STATUS_0_SNIC_ACTIVITY_SHIFT                        _MK_SHIFT_CONST(26)
#define MISCREG_LPI_STATUS_0_SNIC_ACTIVITY_FIELD                        _MK_FIELD_CONST(0x1, MISCREG_LPI_STATUS_0_SNIC_ACTIVITY_SHIFT)
#define MISCREG_LPI_STATUS_0_SNIC_ACTIVITY_RANGE                        26:26
#define MISCREG_LPI_STATUS_0_SNIC_ACTIVITY_WOFFSET                      0x0
#define MISCREG_LPI_STATUS_0_SNIC_ACTIVITY_DEFAULT                      _MK_MASK_CONST(0x0)
#define MISCREG_LPI_STATUS_0_SNIC_ACTIVITY_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define MISCREG_LPI_STATUS_0_SNIC_ACTIVITY_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define MISCREG_LPI_STATUS_0_SNIC_ACTIVITY_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define MISCREG_LPI_STATUS_0_SNIC_ACTIVITY_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define MISCREG_LPI_STATUS_0_SNIC_ACTIVITY_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define MISCREG_LPI_STATUS_0_AXIP2P_SMMU_ACTIVITY_SHIFT                 _MK_SHIFT_CONST(19)
#define MISCREG_LPI_STATUS_0_AXIP2P_SMMU_ACTIVITY_FIELD                 _MK_FIELD_CONST(0x1, MISCREG_LPI_STATUS_0_AXIP2P_SMMU_ACTIVITY_SHIFT)
#define MISCREG_LPI_STATUS_0_AXIP2P_SMMU_ACTIVITY_RANGE                 19:19
#define MISCREG_LPI_STATUS_0_AXIP2P_SMMU_ACTIVITY_WOFFSET                       0x0
#define MISCREG_LPI_STATUS_0_AXIP2P_SMMU_ACTIVITY_DEFAULT                       _MK_MASK_CONST(0x0)
#define MISCREG_LPI_STATUS_0_AXIP2P_SMMU_ACTIVITY_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define MISCREG_LPI_STATUS_0_AXIP2P_SMMU_ACTIVITY_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define MISCREG_LPI_STATUS_0_AXIP2P_SMMU_ACTIVITY_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define MISCREG_LPI_STATUS_0_AXIP2P_SMMU_ACTIVITY_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define MISCREG_LPI_STATUS_0_AXIP2P_SMMU_ACTIVITY_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)

#define MISCREG_LPI_STATUS_0_AXIP2P_CPU_ACTIVITY_SHIFT                  _MK_SHIFT_CONST(18)
#define MISCREG_LPI_STATUS_0_AXIP2P_CPU_ACTIVITY_FIELD                  _MK_FIELD_CONST(0x1, MISCREG_LPI_STATUS_0_AXIP2P_CPU_ACTIVITY_SHIFT)
#define MISCREG_LPI_STATUS_0_AXIP2P_CPU_ACTIVITY_RANGE                  18:18
#define MISCREG_LPI_STATUS_0_AXIP2P_CPU_ACTIVITY_WOFFSET                        0x0
#define MISCREG_LPI_STATUS_0_AXIP2P_CPU_ACTIVITY_DEFAULT                        _MK_MASK_CONST(0x0)
#define MISCREG_LPI_STATUS_0_AXIP2P_CPU_ACTIVITY_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define MISCREG_LPI_STATUS_0_AXIP2P_CPU_ACTIVITY_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define MISCREG_LPI_STATUS_0_AXIP2P_CPU_ACTIVITY_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define MISCREG_LPI_STATUS_0_AXIP2P_CPU_ACTIVITY_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define MISCREG_LPI_STATUS_0_AXIP2P_CPU_ACTIVITY_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)

#define MISCREG_LPI_STATUS_0_AXIP2P_HOST1X_ACTIVITY_SHIFT                       _MK_SHIFT_CONST(17)
#define MISCREG_LPI_STATUS_0_AXIP2P_HOST1X_ACTIVITY_FIELD                       _MK_FIELD_CONST(0x1, MISCREG_LPI_STATUS_0_AXIP2P_HOST1X_ACTIVITY_SHIFT)
#define MISCREG_LPI_STATUS_0_AXIP2P_HOST1X_ACTIVITY_RANGE                       17:17
#define MISCREG_LPI_STATUS_0_AXIP2P_HOST1X_ACTIVITY_WOFFSET                     0x0
#define MISCREG_LPI_STATUS_0_AXIP2P_HOST1X_ACTIVITY_DEFAULT                     _MK_MASK_CONST(0x0)
#define MISCREG_LPI_STATUS_0_AXIP2P_HOST1X_ACTIVITY_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define MISCREG_LPI_STATUS_0_AXIP2P_HOST1X_ACTIVITY_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define MISCREG_LPI_STATUS_0_AXIP2P_HOST1X_ACTIVITY_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define MISCREG_LPI_STATUS_0_AXIP2P_HOST1X_ACTIVITY_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define MISCREG_LPI_STATUS_0_AXIP2P_HOST1X_ACTIVITY_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define MISCREG_LPI_STATUS_0_AXIP2P_PCIE_ACTIVITY_SHIFT                 _MK_SHIFT_CONST(16)
#define MISCREG_LPI_STATUS_0_AXIP2P_PCIE_ACTIVITY_FIELD                 _MK_FIELD_CONST(0x1, MISCREG_LPI_STATUS_0_AXIP2P_PCIE_ACTIVITY_SHIFT)
#define MISCREG_LPI_STATUS_0_AXIP2P_PCIE_ACTIVITY_RANGE                 16:16
#define MISCREG_LPI_STATUS_0_AXIP2P_PCIE_ACTIVITY_WOFFSET                       0x0
#define MISCREG_LPI_STATUS_0_AXIP2P_PCIE_ACTIVITY_DEFAULT                       _MK_MASK_CONST(0x0)
#define MISCREG_LPI_STATUS_0_AXIP2P_PCIE_ACTIVITY_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define MISCREG_LPI_STATUS_0_AXIP2P_PCIE_ACTIVITY_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define MISCREG_LPI_STATUS_0_AXIP2P_PCIE_ACTIVITY_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define MISCREG_LPI_STATUS_0_AXIP2P_PCIE_ACTIVITY_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define MISCREG_LPI_STATUS_0_AXIP2P_PCIE_ACTIVITY_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)

#define MISCREG_LPI_STATUS_0_AXIP2P_GPU_ACTIVITY_SHIFT                  _MK_SHIFT_CONST(15)
#define MISCREG_LPI_STATUS_0_AXIP2P_GPU_ACTIVITY_FIELD                  _MK_FIELD_CONST(0x1, MISCREG_LPI_STATUS_0_AXIP2P_GPU_ACTIVITY_SHIFT)
#define MISCREG_LPI_STATUS_0_AXIP2P_GPU_ACTIVITY_RANGE                  15:15
#define MISCREG_LPI_STATUS_0_AXIP2P_GPU_ACTIVITY_WOFFSET                        0x0
#define MISCREG_LPI_STATUS_0_AXIP2P_GPU_ACTIVITY_DEFAULT                        _MK_MASK_CONST(0x0)
#define MISCREG_LPI_STATUS_0_AXIP2P_GPU_ACTIVITY_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define MISCREG_LPI_STATUS_0_AXIP2P_GPU_ACTIVITY_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define MISCREG_LPI_STATUS_0_AXIP2P_GPU_ACTIVITY_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define MISCREG_LPI_STATUS_0_AXIP2P_GPU_ACTIVITY_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define MISCREG_LPI_STATUS_0_AXIP2P_GPU_ACTIVITY_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)

#define MISCREG_LPI_STATUS_0_AXIP2P_APE_ACTIVITY_SHIFT                  _MK_SHIFT_CONST(14)
#define MISCREG_LPI_STATUS_0_AXIP2P_APE_ACTIVITY_FIELD                  _MK_FIELD_CONST(0x1, MISCREG_LPI_STATUS_0_AXIP2P_APE_ACTIVITY_SHIFT)
#define MISCREG_LPI_STATUS_0_AXIP2P_APE_ACTIVITY_RANGE                  14:14
#define MISCREG_LPI_STATUS_0_AXIP2P_APE_ACTIVITY_WOFFSET                        0x0
#define MISCREG_LPI_STATUS_0_AXIP2P_APE_ACTIVITY_DEFAULT                        _MK_MASK_CONST(0x0)
#define MISCREG_LPI_STATUS_0_AXIP2P_APE_ACTIVITY_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define MISCREG_LPI_STATUS_0_AXIP2P_APE_ACTIVITY_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define MISCREG_LPI_STATUS_0_AXIP2P_APE_ACTIVITY_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define MISCREG_LPI_STATUS_0_AXIP2P_APE_ACTIVITY_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define MISCREG_LPI_STATUS_0_AXIP2P_APE_ACTIVITY_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)

#define MISCREG_LPI_STATUS_0_AXIP2P_SSPE_ACTIVITY_SHIFT                 _MK_SHIFT_CONST(13)
#define MISCREG_LPI_STATUS_0_AXIP2P_SSPE_ACTIVITY_FIELD                 _MK_FIELD_CONST(0x1, MISCREG_LPI_STATUS_0_AXIP2P_SSPE_ACTIVITY_SHIFT)
#define MISCREG_LPI_STATUS_0_AXIP2P_SSPE_ACTIVITY_RANGE                 13:13
#define MISCREG_LPI_STATUS_0_AXIP2P_SSPE_ACTIVITY_WOFFSET                       0x0
#define MISCREG_LPI_STATUS_0_AXIP2P_SSPE_ACTIVITY_DEFAULT                       _MK_MASK_CONST(0x0)
#define MISCREG_LPI_STATUS_0_AXIP2P_SSPE_ACTIVITY_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define MISCREG_LPI_STATUS_0_AXIP2P_SSPE_ACTIVITY_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define MISCREG_LPI_STATUS_0_AXIP2P_SSPE_ACTIVITY_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define MISCREG_LPI_STATUS_0_AXIP2P_SSPE_ACTIVITY_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define MISCREG_LPI_STATUS_0_AXIP2P_SSPE_ACTIVITY_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)

#define MISCREG_LPI_STATUS_0_AXIP2P_MSPE_ACTIVITY_SHIFT                 _MK_SHIFT_CONST(12)
#define MISCREG_LPI_STATUS_0_AXIP2P_MSPE_ACTIVITY_FIELD                 _MK_FIELD_CONST(0x1, MISCREG_LPI_STATUS_0_AXIP2P_MSPE_ACTIVITY_SHIFT)
#define MISCREG_LPI_STATUS_0_AXIP2P_MSPE_ACTIVITY_RANGE                 12:12
#define MISCREG_LPI_STATUS_0_AXIP2P_MSPE_ACTIVITY_WOFFSET                       0x0
#define MISCREG_LPI_STATUS_0_AXIP2P_MSPE_ACTIVITY_DEFAULT                       _MK_MASK_CONST(0x0)
#define MISCREG_LPI_STATUS_0_AXIP2P_MSPE_ACTIVITY_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define MISCREG_LPI_STATUS_0_AXIP2P_MSPE_ACTIVITY_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define MISCREG_LPI_STATUS_0_AXIP2P_MSPE_ACTIVITY_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define MISCREG_LPI_STATUS_0_AXIP2P_MSPE_ACTIVITY_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define MISCREG_LPI_STATUS_0_AXIP2P_MSPE_ACTIVITY_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)

#define MISCREG_LPI_STATUS_0_AXIP2P_BPMP_ACTIVITY_SHIFT                 _MK_SHIFT_CONST(11)
#define MISCREG_LPI_STATUS_0_AXIP2P_BPMP_ACTIVITY_FIELD                 _MK_FIELD_CONST(0x1, MISCREG_LPI_STATUS_0_AXIP2P_BPMP_ACTIVITY_SHIFT)
#define MISCREG_LPI_STATUS_0_AXIP2P_BPMP_ACTIVITY_RANGE                 11:11
#define MISCREG_LPI_STATUS_0_AXIP2P_BPMP_ACTIVITY_WOFFSET                       0x0
#define MISCREG_LPI_STATUS_0_AXIP2P_BPMP_ACTIVITY_DEFAULT                       _MK_MASK_CONST(0x0)
#define MISCREG_LPI_STATUS_0_AXIP2P_BPMP_ACTIVITY_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define MISCREG_LPI_STATUS_0_AXIP2P_BPMP_ACTIVITY_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define MISCREG_LPI_STATUS_0_AXIP2P_BPMP_ACTIVITY_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define MISCREG_LPI_STATUS_0_AXIP2P_BPMP_ACTIVITY_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define MISCREG_LPI_STATUS_0_AXIP2P_BPMP_ACTIVITY_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)

#define MISCREG_LPI_STATUS_0_AXIP2P_SCE_ACTIVITY_SHIFT                  _MK_SHIFT_CONST(10)
#define MISCREG_LPI_STATUS_0_AXIP2P_SCE_ACTIVITY_FIELD                  _MK_FIELD_CONST(0x1, MISCREG_LPI_STATUS_0_AXIP2P_SCE_ACTIVITY_SHIFT)
#define MISCREG_LPI_STATUS_0_AXIP2P_SCE_ACTIVITY_RANGE                  10:10
#define MISCREG_LPI_STATUS_0_AXIP2P_SCE_ACTIVITY_WOFFSET                        0x0
#define MISCREG_LPI_STATUS_0_AXIP2P_SCE_ACTIVITY_DEFAULT                        _MK_MASK_CONST(0x0)
#define MISCREG_LPI_STATUS_0_AXIP2P_SCE_ACTIVITY_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define MISCREG_LPI_STATUS_0_AXIP2P_SCE_ACTIVITY_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define MISCREG_LPI_STATUS_0_AXIP2P_SCE_ACTIVITY_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define MISCREG_LPI_STATUS_0_AXIP2P_SCE_ACTIVITY_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define MISCREG_LPI_STATUS_0_AXIP2P_SCE_ACTIVITY_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)

#define MISCREG_LPI_STATUS_0_AXIAPB_BRIDGE1_5_ACTIVITY_SHIFT                    _MK_SHIFT_CONST(1)
#define MISCREG_LPI_STATUS_0_AXIAPB_BRIDGE1_5_ACTIVITY_FIELD                    _MK_FIELD_CONST(0x1f, MISCREG_LPI_STATUS_0_AXIAPB_BRIDGE1_5_ACTIVITY_SHIFT)
#define MISCREG_LPI_STATUS_0_AXIAPB_BRIDGE1_5_ACTIVITY_RANGE                    5:1
#define MISCREG_LPI_STATUS_0_AXIAPB_BRIDGE1_5_ACTIVITY_WOFFSET                  0x0
#define MISCREG_LPI_STATUS_0_AXIAPB_BRIDGE1_5_ACTIVITY_DEFAULT                  _MK_MASK_CONST(0x0)
#define MISCREG_LPI_STATUS_0_AXIAPB_BRIDGE1_5_ACTIVITY_DEFAULT_MASK                     _MK_MASK_CONST(0x1f)
#define MISCREG_LPI_STATUS_0_AXIAPB_BRIDGE1_5_ACTIVITY_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define MISCREG_LPI_STATUS_0_AXIAPB_BRIDGE1_5_ACTIVITY_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define MISCREG_LPI_STATUS_0_AXIAPB_BRIDGE1_5_ACTIVITY_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define MISCREG_LPI_STATUS_0_AXIAPB_BRIDGE1_5_ACTIVITY_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)


// Register MISCREG_LPI_HYSTERESIS_0
#define MISCREG_LPI_HYSTERESIS_0                        _MK_ADDR_CONST(0x1058)
#define MISCREG_LPI_HYSTERESIS_0_SECURE                         0x0
#define MISCREG_LPI_HYSTERESIS_0_DUAL                   0x0
#define MISCREG_LPI_HYSTERESIS_0_SCR                    SCRLPI_0
#define MISCREG_LPI_HYSTERESIS_0_WORD_COUNT                     0x1
#define MISCREG_LPI_HYSTERESIS_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define MISCREG_LPI_HYSTERESIS_0_RESET_MASK                     _MK_MASK_CONST(0xffffffff)
#define MISCREG_LPI_HYSTERESIS_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define MISCREG_LPI_HYSTERESIS_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define MISCREG_LPI_HYSTERESIS_0_READ_MASK                      _MK_MASK_CONST(0xffffffff)
#define MISCREG_LPI_HYSTERESIS_0_WRITE_MASK                     _MK_MASK_CONST(0xffffffff)
#define MISCREG_LPI_HYSTERESIS_0_SCALE_UP_VALUE_SHIFT                   _MK_SHIFT_CONST(16)
#define MISCREG_LPI_HYSTERESIS_0_SCALE_UP_VALUE_FIELD                   _MK_FIELD_CONST(0xffff, MISCREG_LPI_HYSTERESIS_0_SCALE_UP_VALUE_SHIFT)
#define MISCREG_LPI_HYSTERESIS_0_SCALE_UP_VALUE_RANGE                   31:16
#define MISCREG_LPI_HYSTERESIS_0_SCALE_UP_VALUE_WOFFSET                 0x0
#define MISCREG_LPI_HYSTERESIS_0_SCALE_UP_VALUE_DEFAULT                 _MK_MASK_CONST(0x0)
#define MISCREG_LPI_HYSTERESIS_0_SCALE_UP_VALUE_DEFAULT_MASK                    _MK_MASK_CONST(0xffff)
#define MISCREG_LPI_HYSTERESIS_0_SCALE_UP_VALUE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define MISCREG_LPI_HYSTERESIS_0_SCALE_UP_VALUE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define MISCREG_LPI_HYSTERESIS_0_SCALE_UP_VALUE_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define MISCREG_LPI_HYSTERESIS_0_SCALE_UP_VALUE_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define MISCREG_LPI_HYSTERESIS_0_SCALE_DOWN_VALUE_SHIFT                 _MK_SHIFT_CONST(0)
#define MISCREG_LPI_HYSTERESIS_0_SCALE_DOWN_VALUE_FIELD                 _MK_FIELD_CONST(0xffff, MISCREG_LPI_HYSTERESIS_0_SCALE_DOWN_VALUE_SHIFT)
#define MISCREG_LPI_HYSTERESIS_0_SCALE_DOWN_VALUE_RANGE                 15:0
#define MISCREG_LPI_HYSTERESIS_0_SCALE_DOWN_VALUE_WOFFSET                       0x0
#define MISCREG_LPI_HYSTERESIS_0_SCALE_DOWN_VALUE_DEFAULT                       _MK_MASK_CONST(0x0)
#define MISCREG_LPI_HYSTERESIS_0_SCALE_DOWN_VALUE_DEFAULT_MASK                  _MK_MASK_CONST(0xffff)
#define MISCREG_LPI_HYSTERESIS_0_SCALE_DOWN_VALUE_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define MISCREG_LPI_HYSTERESIS_0_SCALE_DOWN_VALUE_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define MISCREG_LPI_HYSTERESIS_0_SCALE_DOWN_VALUE_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define MISCREG_LPI_HYSTERESIS_0_SCALE_DOWN_VALUE_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)


// Register MISCREG_GP0_GPU_SEC_0
#define MISCREG_GP0_GPU_SEC_0                   _MK_ADDR_CONST(0x105c)
#define MISCREG_GP0_GPU_SEC_0_SECURE                    0x0
#define MISCREG_GP0_GPU_SEC_0_DUAL                      0x0
#define MISCREG_GP0_GPU_SEC_0_SCR                       SCRGP0_0
#define MISCREG_GP0_GPU_SEC_0_WORD_COUNT                        0x1
#define MISCREG_GP0_GPU_SEC_0_RESET_VAL                         _MK_MASK_CONST(0x0)
#define MISCREG_GP0_GPU_SEC_0_RESET_MASK                        _MK_MASK_CONST(0xffff)
#define MISCREG_GP0_GPU_SEC_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define MISCREG_GP0_GPU_SEC_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define MISCREG_GP0_GPU_SEC_0_READ_MASK                         _MK_MASK_CONST(0xffff)
#define MISCREG_GP0_GPU_SEC_0_WRITE_MASK                        _MK_MASK_CONST(0xffff)
#define MISCREG_GP0_GPU_SEC_0_G7W_SHIFT                 _MK_SHIFT_CONST(15)
#define MISCREG_GP0_GPU_SEC_0_G7W_FIELD                 _MK_FIELD_CONST(0x1, MISCREG_GP0_GPU_SEC_0_G7W_SHIFT)
#define MISCREG_GP0_GPU_SEC_0_G7W_RANGE                 15:15
#define MISCREG_GP0_GPU_SEC_0_G7W_WOFFSET                       0x0
#define MISCREG_GP0_GPU_SEC_0_G7W_DEFAULT                       _MK_MASK_CONST(0x0)
#define MISCREG_GP0_GPU_SEC_0_G7W_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define MISCREG_GP0_GPU_SEC_0_G7W_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define MISCREG_GP0_GPU_SEC_0_G7W_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define MISCREG_GP0_GPU_SEC_0_G7W_PARITY_PROTECTION                     _MK_MASK_CONST(0x1)
#define MISCREG_GP0_GPU_SEC_0_G7W_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)

#define MISCREG_GP0_GPU_SEC_0_G6W_SHIFT                 _MK_SHIFT_CONST(14)
#define MISCREG_GP0_GPU_SEC_0_G6W_FIELD                 _MK_FIELD_CONST(0x1, MISCREG_GP0_GPU_SEC_0_G6W_SHIFT)
#define MISCREG_GP0_GPU_SEC_0_G6W_RANGE                 14:14
#define MISCREG_GP0_GPU_SEC_0_G6W_WOFFSET                       0x0
#define MISCREG_GP0_GPU_SEC_0_G6W_DEFAULT                       _MK_MASK_CONST(0x0)
#define MISCREG_GP0_GPU_SEC_0_G6W_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define MISCREG_GP0_GPU_SEC_0_G6W_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define MISCREG_GP0_GPU_SEC_0_G6W_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define MISCREG_GP0_GPU_SEC_0_G6W_PARITY_PROTECTION                     _MK_MASK_CONST(0x1)
#define MISCREG_GP0_GPU_SEC_0_G6W_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)

#define MISCREG_GP0_GPU_SEC_0_G5W_SHIFT                 _MK_SHIFT_CONST(13)
#define MISCREG_GP0_GPU_SEC_0_G5W_FIELD                 _MK_FIELD_CONST(0x1, MISCREG_GP0_GPU_SEC_0_G5W_SHIFT)
#define MISCREG_GP0_GPU_SEC_0_G5W_RANGE                 13:13
#define MISCREG_GP0_GPU_SEC_0_G5W_WOFFSET                       0x0
#define MISCREG_GP0_GPU_SEC_0_G5W_DEFAULT                       _MK_MASK_CONST(0x0)
#define MISCREG_GP0_GPU_SEC_0_G5W_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define MISCREG_GP0_GPU_SEC_0_G5W_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define MISCREG_GP0_GPU_SEC_0_G5W_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define MISCREG_GP0_GPU_SEC_0_G5W_PARITY_PROTECTION                     _MK_MASK_CONST(0x1)
#define MISCREG_GP0_GPU_SEC_0_G5W_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)

#define MISCREG_GP0_GPU_SEC_0_G4W_SHIFT                 _MK_SHIFT_CONST(12)
#define MISCREG_GP0_GPU_SEC_0_G4W_FIELD                 _MK_FIELD_CONST(0x1, MISCREG_GP0_GPU_SEC_0_G4W_SHIFT)
#define MISCREG_GP0_GPU_SEC_0_G4W_RANGE                 12:12
#define MISCREG_GP0_GPU_SEC_0_G4W_WOFFSET                       0x0
#define MISCREG_GP0_GPU_SEC_0_G4W_DEFAULT                       _MK_MASK_CONST(0x0)
#define MISCREG_GP0_GPU_SEC_0_G4W_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define MISCREG_GP0_GPU_SEC_0_G4W_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define MISCREG_GP0_GPU_SEC_0_G4W_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define MISCREG_GP0_GPU_SEC_0_G4W_PARITY_PROTECTION                     _MK_MASK_CONST(0x1)
#define MISCREG_GP0_GPU_SEC_0_G4W_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)

#define MISCREG_GP0_GPU_SEC_0_G3W_SHIFT                 _MK_SHIFT_CONST(11)
#define MISCREG_GP0_GPU_SEC_0_G3W_FIELD                 _MK_FIELD_CONST(0x1, MISCREG_GP0_GPU_SEC_0_G3W_SHIFT)
#define MISCREG_GP0_GPU_SEC_0_G3W_RANGE                 11:11
#define MISCREG_GP0_GPU_SEC_0_G3W_WOFFSET                       0x0
#define MISCREG_GP0_GPU_SEC_0_G3W_DEFAULT                       _MK_MASK_CONST(0x0)
#define MISCREG_GP0_GPU_SEC_0_G3W_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define MISCREG_GP0_GPU_SEC_0_G3W_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define MISCREG_GP0_GPU_SEC_0_G3W_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define MISCREG_GP0_GPU_SEC_0_G3W_PARITY_PROTECTION                     _MK_MASK_CONST(0x1)
#define MISCREG_GP0_GPU_SEC_0_G3W_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)

#define MISCREG_GP0_GPU_SEC_0_G2W_SHIFT                 _MK_SHIFT_CONST(10)
#define MISCREG_GP0_GPU_SEC_0_G2W_FIELD                 _MK_FIELD_CONST(0x1, MISCREG_GP0_GPU_SEC_0_G2W_SHIFT)
#define MISCREG_GP0_GPU_SEC_0_G2W_RANGE                 10:10
#define MISCREG_GP0_GPU_SEC_0_G2W_WOFFSET                       0x0
#define MISCREG_GP0_GPU_SEC_0_G2W_DEFAULT                       _MK_MASK_CONST(0x0)
#define MISCREG_GP0_GPU_SEC_0_G2W_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define MISCREG_GP0_GPU_SEC_0_G2W_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define MISCREG_GP0_GPU_SEC_0_G2W_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define MISCREG_GP0_GPU_SEC_0_G2W_PARITY_PROTECTION                     _MK_MASK_CONST(0x1)
#define MISCREG_GP0_GPU_SEC_0_G2W_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)

#define MISCREG_GP0_GPU_SEC_0_G1W_SHIFT                 _MK_SHIFT_CONST(9)
#define MISCREG_GP0_GPU_SEC_0_G1W_FIELD                 _MK_FIELD_CONST(0x1, MISCREG_GP0_GPU_SEC_0_G1W_SHIFT)
#define MISCREG_GP0_GPU_SEC_0_G1W_RANGE                 9:9
#define MISCREG_GP0_GPU_SEC_0_G1W_WOFFSET                       0x0
#define MISCREG_GP0_GPU_SEC_0_G1W_DEFAULT                       _MK_MASK_CONST(0x0)
#define MISCREG_GP0_GPU_SEC_0_G1W_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define MISCREG_GP0_GPU_SEC_0_G1W_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define MISCREG_GP0_GPU_SEC_0_G1W_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define MISCREG_GP0_GPU_SEC_0_G1W_PARITY_PROTECTION                     _MK_MASK_CONST(0x1)
#define MISCREG_GP0_GPU_SEC_0_G1W_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)

#define MISCREG_GP0_GPU_SEC_0_G0W_SHIFT                 _MK_SHIFT_CONST(8)
#define MISCREG_GP0_GPU_SEC_0_G0W_FIELD                 _MK_FIELD_CONST(0x1, MISCREG_GP0_GPU_SEC_0_G0W_SHIFT)
#define MISCREG_GP0_GPU_SEC_0_G0W_RANGE                 8:8
#define MISCREG_GP0_GPU_SEC_0_G0W_WOFFSET                       0x0
#define MISCREG_GP0_GPU_SEC_0_G0W_DEFAULT                       _MK_MASK_CONST(0x0)
#define MISCREG_GP0_GPU_SEC_0_G0W_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define MISCREG_GP0_GPU_SEC_0_G0W_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define MISCREG_GP0_GPU_SEC_0_G0W_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define MISCREG_GP0_GPU_SEC_0_G0W_PARITY_PROTECTION                     _MK_MASK_CONST(0x1)
#define MISCREG_GP0_GPU_SEC_0_G0W_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)

#define MISCREG_GP0_GPU_SEC_0_G7R_SHIFT                 _MK_SHIFT_CONST(7)
#define MISCREG_GP0_GPU_SEC_0_G7R_FIELD                 _MK_FIELD_CONST(0x1, MISCREG_GP0_GPU_SEC_0_G7R_SHIFT)
#define MISCREG_GP0_GPU_SEC_0_G7R_RANGE                 7:7
#define MISCREG_GP0_GPU_SEC_0_G7R_WOFFSET                       0x0
#define MISCREG_GP0_GPU_SEC_0_G7R_DEFAULT                       _MK_MASK_CONST(0x0)
#define MISCREG_GP0_GPU_SEC_0_G7R_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define MISCREG_GP0_GPU_SEC_0_G7R_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define MISCREG_GP0_GPU_SEC_0_G7R_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define MISCREG_GP0_GPU_SEC_0_G7R_PARITY_PROTECTION                     _MK_MASK_CONST(0x1)
#define MISCREG_GP0_GPU_SEC_0_G7R_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)

#define MISCREG_GP0_GPU_SEC_0_G6R_SHIFT                 _MK_SHIFT_CONST(6)
#define MISCREG_GP0_GPU_SEC_0_G6R_FIELD                 _MK_FIELD_CONST(0x1, MISCREG_GP0_GPU_SEC_0_G6R_SHIFT)
#define MISCREG_GP0_GPU_SEC_0_G6R_RANGE                 6:6
#define MISCREG_GP0_GPU_SEC_0_G6R_WOFFSET                       0x0
#define MISCREG_GP0_GPU_SEC_0_G6R_DEFAULT                       _MK_MASK_CONST(0x0)
#define MISCREG_GP0_GPU_SEC_0_G6R_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define MISCREG_GP0_GPU_SEC_0_G6R_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define MISCREG_GP0_GPU_SEC_0_G6R_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define MISCREG_GP0_GPU_SEC_0_G6R_PARITY_PROTECTION                     _MK_MASK_CONST(0x1)
#define MISCREG_GP0_GPU_SEC_0_G6R_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)

#define MISCREG_GP0_GPU_SEC_0_G5R_SHIFT                 _MK_SHIFT_CONST(5)
#define MISCREG_GP0_GPU_SEC_0_G5R_FIELD                 _MK_FIELD_CONST(0x1, MISCREG_GP0_GPU_SEC_0_G5R_SHIFT)
#define MISCREG_GP0_GPU_SEC_0_G5R_RANGE                 5:5
#define MISCREG_GP0_GPU_SEC_0_G5R_WOFFSET                       0x0
#define MISCREG_GP0_GPU_SEC_0_G5R_DEFAULT                       _MK_MASK_CONST(0x0)
#define MISCREG_GP0_GPU_SEC_0_G5R_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define MISCREG_GP0_GPU_SEC_0_G5R_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define MISCREG_GP0_GPU_SEC_0_G5R_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define MISCREG_GP0_GPU_SEC_0_G5R_PARITY_PROTECTION                     _MK_MASK_CONST(0x1)
#define MISCREG_GP0_GPU_SEC_0_G5R_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)

#define MISCREG_GP0_GPU_SEC_0_G4R_SHIFT                 _MK_SHIFT_CONST(4)
#define MISCREG_GP0_GPU_SEC_0_G4R_FIELD                 _MK_FIELD_CONST(0x1, MISCREG_GP0_GPU_SEC_0_G4R_SHIFT)
#define MISCREG_GP0_GPU_SEC_0_G4R_RANGE                 4:4
#define MISCREG_GP0_GPU_SEC_0_G4R_WOFFSET                       0x0
#define MISCREG_GP0_GPU_SEC_0_G4R_DEFAULT                       _MK_MASK_CONST(0x0)
#define MISCREG_GP0_GPU_SEC_0_G4R_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define MISCREG_GP0_GPU_SEC_0_G4R_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define MISCREG_GP0_GPU_SEC_0_G4R_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define MISCREG_GP0_GPU_SEC_0_G4R_PARITY_PROTECTION                     _MK_MASK_CONST(0x1)
#define MISCREG_GP0_GPU_SEC_0_G4R_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)

#define MISCREG_GP0_GPU_SEC_0_G3R_SHIFT                 _MK_SHIFT_CONST(3)
#define MISCREG_GP0_GPU_SEC_0_G3R_FIELD                 _MK_FIELD_CONST(0x1, MISCREG_GP0_GPU_SEC_0_G3R_SHIFT)
#define MISCREG_GP0_GPU_SEC_0_G3R_RANGE                 3:3
#define MISCREG_GP0_GPU_SEC_0_G3R_WOFFSET                       0x0
#define MISCREG_GP0_GPU_SEC_0_G3R_DEFAULT                       _MK_MASK_CONST(0x0)
#define MISCREG_GP0_GPU_SEC_0_G3R_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define MISCREG_GP0_GPU_SEC_0_G3R_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define MISCREG_GP0_GPU_SEC_0_G3R_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define MISCREG_GP0_GPU_SEC_0_G3R_PARITY_PROTECTION                     _MK_MASK_CONST(0x1)
#define MISCREG_GP0_GPU_SEC_0_G3R_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)

#define MISCREG_GP0_GPU_SEC_0_G2R_SHIFT                 _MK_SHIFT_CONST(2)
#define MISCREG_GP0_GPU_SEC_0_G2R_FIELD                 _MK_FIELD_CONST(0x1, MISCREG_GP0_GPU_SEC_0_G2R_SHIFT)
#define MISCREG_GP0_GPU_SEC_0_G2R_RANGE                 2:2
#define MISCREG_GP0_GPU_SEC_0_G2R_WOFFSET                       0x0
#define MISCREG_GP0_GPU_SEC_0_G2R_DEFAULT                       _MK_MASK_CONST(0x0)
#define MISCREG_GP0_GPU_SEC_0_G2R_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define MISCREG_GP0_GPU_SEC_0_G2R_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define MISCREG_GP0_GPU_SEC_0_G2R_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define MISCREG_GP0_GPU_SEC_0_G2R_PARITY_PROTECTION                     _MK_MASK_CONST(0x1)
#define MISCREG_GP0_GPU_SEC_0_G2R_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)

#define MISCREG_GP0_GPU_SEC_0_G1R_SHIFT                 _MK_SHIFT_CONST(1)
#define MISCREG_GP0_GPU_SEC_0_G1R_FIELD                 _MK_FIELD_CONST(0x1, MISCREG_GP0_GPU_SEC_0_G1R_SHIFT)
#define MISCREG_GP0_GPU_SEC_0_G1R_RANGE                 1:1
#define MISCREG_GP0_GPU_SEC_0_G1R_WOFFSET                       0x0
#define MISCREG_GP0_GPU_SEC_0_G1R_DEFAULT                       _MK_MASK_CONST(0x0)
#define MISCREG_GP0_GPU_SEC_0_G1R_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define MISCREG_GP0_GPU_SEC_0_G1R_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define MISCREG_GP0_GPU_SEC_0_G1R_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define MISCREG_GP0_GPU_SEC_0_G1R_PARITY_PROTECTION                     _MK_MASK_CONST(0x1)
#define MISCREG_GP0_GPU_SEC_0_G1R_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)

#define MISCREG_GP0_GPU_SEC_0_G0R_SHIFT                 _MK_SHIFT_CONST(0)
#define MISCREG_GP0_GPU_SEC_0_G0R_FIELD                 _MK_FIELD_CONST(0x1, MISCREG_GP0_GPU_SEC_0_G0R_SHIFT)
#define MISCREG_GP0_GPU_SEC_0_G0R_RANGE                 0:0
#define MISCREG_GP0_GPU_SEC_0_G0R_WOFFSET                       0x0
#define MISCREG_GP0_GPU_SEC_0_G0R_DEFAULT                       _MK_MASK_CONST(0x0)
#define MISCREG_GP0_GPU_SEC_0_G0R_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define MISCREG_GP0_GPU_SEC_0_G0R_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define MISCREG_GP0_GPU_SEC_0_G0R_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define MISCREG_GP0_GPU_SEC_0_G0R_PARITY_PROTECTION                     _MK_MASK_CONST(0x1)
#define MISCREG_GP0_GPU_SEC_0_G0R_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)


// Reserved address 0x1060

// Reserved address 0x1064

// Reserved address 0x1068

// Reserved address 0x106c

// Reserved address 0x1070

// Reserved address 0x1074

// Reserved address 0x1078

// Reserved address 0x107c

// Register MISCREG_FUSEROMENCRYPTIONTESTKEY0_0
#define MISCREG_FUSEROMENCRYPTIONTESTKEY0_0                     _MK_ADDR_CONST(0x1080)
#define MISCREG_FUSEROMENCRYPTIONTESTKEY0_0_SECURE                      0x0
#define MISCREG_FUSEROMENCRYPTIONTESTKEY0_0_DUAL                        0x0
#define MISCREG_FUSEROMENCRYPTIONTESTKEY0_0_SCR                         SCRKEY_0
#define MISCREG_FUSEROMENCRYPTIONTESTKEY0_0_WORD_COUNT                  0x1
#define MISCREG_FUSEROMENCRYPTIONTESTKEY0_0_RESET_VAL                   _MK_MASK_CONST(0xe6e8bda2)
#define MISCREG_FUSEROMENCRYPTIONTESTKEY0_0_RESET_MASK                  _MK_MASK_CONST(0xffffffff)
#define MISCREG_FUSEROMENCRYPTIONTESTKEY0_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define MISCREG_FUSEROMENCRYPTIONTESTKEY0_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define MISCREG_FUSEROMENCRYPTIONTESTKEY0_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
#define MISCREG_FUSEROMENCRYPTIONTESTKEY0_0_WRITE_MASK                  _MK_MASK_CONST(0x0)
#define MISCREG_FUSEROMENCRYPTIONTESTKEY0_0_VAL_SHIFT                   _MK_SHIFT_CONST(0)
#define MISCREG_FUSEROMENCRYPTIONTESTKEY0_0_VAL_FIELD                   _MK_FIELD_CONST(0xffffffff, MISCREG_FUSEROMENCRYPTIONTESTKEY0_0_VAL_SHIFT)
#define MISCREG_FUSEROMENCRYPTIONTESTKEY0_0_VAL_RANGE                   31:0
#define MISCREG_FUSEROMENCRYPTIONTESTKEY0_0_VAL_WOFFSET                 0x0
#define MISCREG_FUSEROMENCRYPTIONTESTKEY0_0_VAL_DEFAULT                 _MK_MASK_CONST(0xe6e8bda2)
#define MISCREG_FUSEROMENCRYPTIONTESTKEY0_0_VAL_DEFAULT_MASK                    _MK_MASK_CONST(0xffffffff)
#define MISCREG_FUSEROMENCRYPTIONTESTKEY0_0_VAL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define MISCREG_FUSEROMENCRYPTIONTESTKEY0_0_VAL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define MISCREG_FUSEROMENCRYPTIONTESTKEY0_0_VAL_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define MISCREG_FUSEROMENCRYPTIONTESTKEY0_0_VAL_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define MISCREG_FUSEROMENCRYPTIONTESTKEY0_0_VAL_INIT_ENUM                       -420954718


// Register MISCREG_FUSEROMENCRYPTIONTESTKEY1_0
#define MISCREG_FUSEROMENCRYPTIONTESTKEY1_0                     _MK_ADDR_CONST(0x1084)
#define MISCREG_FUSEROMENCRYPTIONTESTKEY1_0_SECURE                      0x0
#define MISCREG_FUSEROMENCRYPTIONTESTKEY1_0_DUAL                        0x0
#define MISCREG_FUSEROMENCRYPTIONTESTKEY1_0_SCR                         SCRKEY_0
#define MISCREG_FUSEROMENCRYPTIONTESTKEY1_0_WORD_COUNT                  0x1
#define MISCREG_FUSEROMENCRYPTIONTESTKEY1_0_RESET_VAL                   _MK_MASK_CONST(0xea39674a)
#define MISCREG_FUSEROMENCRYPTIONTESTKEY1_0_RESET_MASK                  _MK_MASK_CONST(0xffffffff)
#define MISCREG_FUSEROMENCRYPTIONTESTKEY1_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define MISCREG_FUSEROMENCRYPTIONTESTKEY1_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define MISCREG_FUSEROMENCRYPTIONTESTKEY1_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
#define MISCREG_FUSEROMENCRYPTIONTESTKEY1_0_WRITE_MASK                  _MK_MASK_CONST(0x0)
#define MISCREG_FUSEROMENCRYPTIONTESTKEY1_0_VAL_SHIFT                   _MK_SHIFT_CONST(0)
#define MISCREG_FUSEROMENCRYPTIONTESTKEY1_0_VAL_FIELD                   _MK_FIELD_CONST(0xffffffff, MISCREG_FUSEROMENCRYPTIONTESTKEY1_0_VAL_SHIFT)
#define MISCREG_FUSEROMENCRYPTIONTESTKEY1_0_VAL_RANGE                   31:0
#define MISCREG_FUSEROMENCRYPTIONTESTKEY1_0_VAL_WOFFSET                 0x0
#define MISCREG_FUSEROMENCRYPTIONTESTKEY1_0_VAL_DEFAULT                 _MK_MASK_CONST(0xea39674a)
#define MISCREG_FUSEROMENCRYPTIONTESTKEY1_0_VAL_DEFAULT_MASK                    _MK_MASK_CONST(0xffffffff)
#define MISCREG_FUSEROMENCRYPTIONTESTKEY1_0_VAL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define MISCREG_FUSEROMENCRYPTIONTESTKEY1_0_VAL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define MISCREG_FUSEROMENCRYPTIONTESTKEY1_0_VAL_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define MISCREG_FUSEROMENCRYPTIONTESTKEY1_0_VAL_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define MISCREG_FUSEROMENCRYPTIONTESTKEY1_0_VAL_INIT_ENUM                       -365336758


// Register MISCREG_FUSEROMENCRYPTIONTESTKEY2_0
#define MISCREG_FUSEROMENCRYPTIONTESTKEY2_0                     _MK_ADDR_CONST(0x1088)
#define MISCREG_FUSEROMENCRYPTIONTESTKEY2_0_SECURE                      0x0
#define MISCREG_FUSEROMENCRYPTIONTESTKEY2_0_DUAL                        0x0
#define MISCREG_FUSEROMENCRYPTIONTESTKEY2_0_SCR                         SCRKEY_0
#define MISCREG_FUSEROMENCRYPTIONTESTKEY2_0_WORD_COUNT                  0x1
#define MISCREG_FUSEROMENCRYPTIONTESTKEY2_0_RESET_VAL                   _MK_MASK_CONST(0xe6411e71)
#define MISCREG_FUSEROMENCRYPTIONTESTKEY2_0_RESET_MASK                  _MK_MASK_CONST(0xffffffff)
#define MISCREG_FUSEROMENCRYPTIONTESTKEY2_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define MISCREG_FUSEROMENCRYPTIONTESTKEY2_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define MISCREG_FUSEROMENCRYPTIONTESTKEY2_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
#define MISCREG_FUSEROMENCRYPTIONTESTKEY2_0_WRITE_MASK                  _MK_MASK_CONST(0x0)
#define MISCREG_FUSEROMENCRYPTIONTESTKEY2_0_VAL_SHIFT                   _MK_SHIFT_CONST(0)
#define MISCREG_FUSEROMENCRYPTIONTESTKEY2_0_VAL_FIELD                   _MK_FIELD_CONST(0xffffffff, MISCREG_FUSEROMENCRYPTIONTESTKEY2_0_VAL_SHIFT)
#define MISCREG_FUSEROMENCRYPTIONTESTKEY2_0_VAL_RANGE                   31:0
#define MISCREG_FUSEROMENCRYPTIONTESTKEY2_0_VAL_WOFFSET                 0x0
#define MISCREG_FUSEROMENCRYPTIONTESTKEY2_0_VAL_DEFAULT                 _MK_MASK_CONST(0xe6411e71)
#define MISCREG_FUSEROMENCRYPTIONTESTKEY2_0_VAL_DEFAULT_MASK                    _MK_MASK_CONST(0xffffffff)
#define MISCREG_FUSEROMENCRYPTIONTESTKEY2_0_VAL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define MISCREG_FUSEROMENCRYPTIONTESTKEY2_0_VAL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define MISCREG_FUSEROMENCRYPTIONTESTKEY2_0_VAL_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define MISCREG_FUSEROMENCRYPTIONTESTKEY2_0_VAL_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define MISCREG_FUSEROMENCRYPTIONTESTKEY2_0_VAL_INIT_ENUM                       -431939983


// Register MISCREG_FUSEROMENCRYPTIONTESTKEY3_0
#define MISCREG_FUSEROMENCRYPTIONTESTKEY3_0                     _MK_ADDR_CONST(0x108c)
#define MISCREG_FUSEROMENCRYPTIONTESTKEY3_0_SECURE                      0x0
#define MISCREG_FUSEROMENCRYPTIONTESTKEY3_0_DUAL                        0x0
#define MISCREG_FUSEROMENCRYPTIONTESTKEY3_0_SCR                         SCRKEY_0
#define MISCREG_FUSEROMENCRYPTIONTESTKEY3_0_WORD_COUNT                  0x1
#define MISCREG_FUSEROMENCRYPTIONTESTKEY3_0_RESET_VAL                   _MK_MASK_CONST(0x87f83807)
#define MISCREG_FUSEROMENCRYPTIONTESTKEY3_0_RESET_MASK                  _MK_MASK_CONST(0xffffffff)
#define MISCREG_FUSEROMENCRYPTIONTESTKEY3_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define MISCREG_FUSEROMENCRYPTIONTESTKEY3_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define MISCREG_FUSEROMENCRYPTIONTESTKEY3_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
#define MISCREG_FUSEROMENCRYPTIONTESTKEY3_0_WRITE_MASK                  _MK_MASK_CONST(0x0)
#define MISCREG_FUSEROMENCRYPTIONTESTKEY3_0_VAL_SHIFT                   _MK_SHIFT_CONST(0)
#define MISCREG_FUSEROMENCRYPTIONTESTKEY3_0_VAL_FIELD                   _MK_FIELD_CONST(0xffffffff, MISCREG_FUSEROMENCRYPTIONTESTKEY3_0_VAL_SHIFT)
#define MISCREG_FUSEROMENCRYPTIONTESTKEY3_0_VAL_RANGE                   31:0
#define MISCREG_FUSEROMENCRYPTIONTESTKEY3_0_VAL_WOFFSET                 0x0
#define MISCREG_FUSEROMENCRYPTIONTESTKEY3_0_VAL_DEFAULT                 _MK_MASK_CONST(0x87f83807)
#define MISCREG_FUSEROMENCRYPTIONTESTKEY3_0_VAL_DEFAULT_MASK                    _MK_MASK_CONST(0xffffffff)
#define MISCREG_FUSEROMENCRYPTIONTESTKEY3_0_VAL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define MISCREG_FUSEROMENCRYPTIONTESTKEY3_0_VAL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define MISCREG_FUSEROMENCRYPTIONTESTKEY3_0_VAL_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define MISCREG_FUSEROMENCRYPTIONTESTKEY3_0_VAL_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define MISCREG_FUSEROMENCRYPTIONTESTKEY3_0_VAL_INIT_ENUM                       -2013775865


// Register MISCREG_FUSEROMENCRYPTIONNVKEY0_0
#define MISCREG_FUSEROMENCRYPTIONNVKEY0_0                       _MK_ADDR_CONST(0x1090)
#define MISCREG_FUSEROMENCRYPTIONNVKEY0_0_SECURE                        0x0
#define MISCREG_FUSEROMENCRYPTIONNVKEY0_0_DUAL                  0x0
#define MISCREG_FUSEROMENCRYPTIONNVKEY0_0_SCR                   SCRKEY_0
#define MISCREG_FUSEROMENCRYPTIONNVKEY0_0_WORD_COUNT                    0x1
#define MISCREG_FUSEROMENCRYPTIONNVKEY0_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define MISCREG_FUSEROMENCRYPTIONNVKEY0_0_RESET_MASK                    _MK_MASK_CONST(0xffffffff)
#define MISCREG_FUSEROMENCRYPTIONNVKEY0_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define MISCREG_FUSEROMENCRYPTIONNVKEY0_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define MISCREG_FUSEROMENCRYPTIONNVKEY0_0_READ_MASK                     _MK_MASK_CONST(0xffffffff)
#define MISCREG_FUSEROMENCRYPTIONNVKEY0_0_WRITE_MASK                    _MK_MASK_CONST(0x0)
#define MISCREG_FUSEROMENCRYPTIONNVKEY0_0_VAL_SHIFT                     _MK_SHIFT_CONST(0)
#define MISCREG_FUSEROMENCRYPTIONNVKEY0_0_VAL_FIELD                     _MK_FIELD_CONST(0xffffffff, MISCREG_FUSEROMENCRYPTIONNVKEY0_0_VAL_SHIFT)
#define MISCREG_FUSEROMENCRYPTIONNVKEY0_0_VAL_RANGE                     31:0
#define MISCREG_FUSEROMENCRYPTIONNVKEY0_0_VAL_WOFFSET                   0x0
#define MISCREG_FUSEROMENCRYPTIONNVKEY0_0_VAL_DEFAULT                   _MK_MASK_CONST(0x0)
#define MISCREG_FUSEROMENCRYPTIONNVKEY0_0_VAL_DEFAULT_MASK                      _MK_MASK_CONST(0xffffffff)
#define MISCREG_FUSEROMENCRYPTIONNVKEY0_0_VAL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define MISCREG_FUSEROMENCRYPTIONNVKEY0_0_VAL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define MISCREG_FUSEROMENCRYPTIONNVKEY0_0_VAL_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define MISCREG_FUSEROMENCRYPTIONNVKEY0_0_VAL_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)


// Register MISCREG_FUSEROMENCRYPTIONNVKEY1_0
#define MISCREG_FUSEROMENCRYPTIONNVKEY1_0                       _MK_ADDR_CONST(0x1094)
#define MISCREG_FUSEROMENCRYPTIONNVKEY1_0_SECURE                        0x0
#define MISCREG_FUSEROMENCRYPTIONNVKEY1_0_DUAL                  0x0
#define MISCREG_FUSEROMENCRYPTIONNVKEY1_0_SCR                   SCRKEY_0
#define MISCREG_FUSEROMENCRYPTIONNVKEY1_0_WORD_COUNT                    0x1
#define MISCREG_FUSEROMENCRYPTIONNVKEY1_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define MISCREG_FUSEROMENCRYPTIONNVKEY1_0_RESET_MASK                    _MK_MASK_CONST(0xffffffff)
#define MISCREG_FUSEROMENCRYPTIONNVKEY1_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define MISCREG_FUSEROMENCRYPTIONNVKEY1_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define MISCREG_FUSEROMENCRYPTIONNVKEY1_0_READ_MASK                     _MK_MASK_CONST(0xffffffff)
#define MISCREG_FUSEROMENCRYPTIONNVKEY1_0_WRITE_MASK                    _MK_MASK_CONST(0x0)
#define MISCREG_FUSEROMENCRYPTIONNVKEY1_0_VAL_SHIFT                     _MK_SHIFT_CONST(0)
#define MISCREG_FUSEROMENCRYPTIONNVKEY1_0_VAL_FIELD                     _MK_FIELD_CONST(0xffffffff, MISCREG_FUSEROMENCRYPTIONNVKEY1_0_VAL_SHIFT)
#define MISCREG_FUSEROMENCRYPTIONNVKEY1_0_VAL_RANGE                     31:0
#define MISCREG_FUSEROMENCRYPTIONNVKEY1_0_VAL_WOFFSET                   0x0
#define MISCREG_FUSEROMENCRYPTIONNVKEY1_0_VAL_DEFAULT                   _MK_MASK_CONST(0x0)
#define MISCREG_FUSEROMENCRYPTIONNVKEY1_0_VAL_DEFAULT_MASK                      _MK_MASK_CONST(0xffffffff)
#define MISCREG_FUSEROMENCRYPTIONNVKEY1_0_VAL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define MISCREG_FUSEROMENCRYPTIONNVKEY1_0_VAL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define MISCREG_FUSEROMENCRYPTIONNVKEY1_0_VAL_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define MISCREG_FUSEROMENCRYPTIONNVKEY1_0_VAL_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)


// Register MISCREG_FUSEROMENCRYPTIONNVKEY2_0
#define MISCREG_FUSEROMENCRYPTIONNVKEY2_0                       _MK_ADDR_CONST(0x1098)
#define MISCREG_FUSEROMENCRYPTIONNVKEY2_0_SECURE                        0x0
#define MISCREG_FUSEROMENCRYPTIONNVKEY2_0_DUAL                  0x0
#define MISCREG_FUSEROMENCRYPTIONNVKEY2_0_SCR                   SCRKEY_0
#define MISCREG_FUSEROMENCRYPTIONNVKEY2_0_WORD_COUNT                    0x1
#define MISCREG_FUSEROMENCRYPTIONNVKEY2_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define MISCREG_FUSEROMENCRYPTIONNVKEY2_0_RESET_MASK                    _MK_MASK_CONST(0xffffffff)
#define MISCREG_FUSEROMENCRYPTIONNVKEY2_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define MISCREG_FUSEROMENCRYPTIONNVKEY2_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define MISCREG_FUSEROMENCRYPTIONNVKEY2_0_READ_MASK                     _MK_MASK_CONST(0xffffffff)
#define MISCREG_FUSEROMENCRYPTIONNVKEY2_0_WRITE_MASK                    _MK_MASK_CONST(0x0)
#define MISCREG_FUSEROMENCRYPTIONNVKEY2_0_VAL_SHIFT                     _MK_SHIFT_CONST(0)
#define MISCREG_FUSEROMENCRYPTIONNVKEY2_0_VAL_FIELD                     _MK_FIELD_CONST(0xffffffff, MISCREG_FUSEROMENCRYPTIONNVKEY2_0_VAL_SHIFT)
#define MISCREG_FUSEROMENCRYPTIONNVKEY2_0_VAL_RANGE                     31:0
#define MISCREG_FUSEROMENCRYPTIONNVKEY2_0_VAL_WOFFSET                   0x0
#define MISCREG_FUSEROMENCRYPTIONNVKEY2_0_VAL_DEFAULT                   _MK_MASK_CONST(0x0)
#define MISCREG_FUSEROMENCRYPTIONNVKEY2_0_VAL_DEFAULT_MASK                      _MK_MASK_CONST(0xffffffff)
#define MISCREG_FUSEROMENCRYPTIONNVKEY2_0_VAL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define MISCREG_FUSEROMENCRYPTIONNVKEY2_0_VAL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define MISCREG_FUSEROMENCRYPTIONNVKEY2_0_VAL_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define MISCREG_FUSEROMENCRYPTIONNVKEY2_0_VAL_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)


// Register MISCREG_FUSEROMENCRYPTIONNVKEY3_0
#define MISCREG_FUSEROMENCRYPTIONNVKEY3_0                       _MK_ADDR_CONST(0x109c)
#define MISCREG_FUSEROMENCRYPTIONNVKEY3_0_SECURE                        0x0
#define MISCREG_FUSEROMENCRYPTIONNVKEY3_0_DUAL                  0x0
#define MISCREG_FUSEROMENCRYPTIONNVKEY3_0_SCR                   SCRKEY_0
#define MISCREG_FUSEROMENCRYPTIONNVKEY3_0_WORD_COUNT                    0x1
#define MISCREG_FUSEROMENCRYPTIONNVKEY3_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define MISCREG_FUSEROMENCRYPTIONNVKEY3_0_RESET_MASK                    _MK_MASK_CONST(0xffffffff)
#define MISCREG_FUSEROMENCRYPTIONNVKEY3_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define MISCREG_FUSEROMENCRYPTIONNVKEY3_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define MISCREG_FUSEROMENCRYPTIONNVKEY3_0_READ_MASK                     _MK_MASK_CONST(0xffffffff)
#define MISCREG_FUSEROMENCRYPTIONNVKEY3_0_WRITE_MASK                    _MK_MASK_CONST(0x0)
#define MISCREG_FUSEROMENCRYPTIONNVKEY3_0_VAL_SHIFT                     _MK_SHIFT_CONST(0)
#define MISCREG_FUSEROMENCRYPTIONNVKEY3_0_VAL_FIELD                     _MK_FIELD_CONST(0xffffffff, MISCREG_FUSEROMENCRYPTIONNVKEY3_0_VAL_SHIFT)
#define MISCREG_FUSEROMENCRYPTIONNVKEY3_0_VAL_RANGE                     31:0
#define MISCREG_FUSEROMENCRYPTIONNVKEY3_0_VAL_WOFFSET                   0x0
#define MISCREG_FUSEROMENCRYPTIONNVKEY3_0_VAL_DEFAULT                   _MK_MASK_CONST(0x0)
#define MISCREG_FUSEROMENCRYPTIONNVKEY3_0_VAL_DEFAULT_MASK                      _MK_MASK_CONST(0xffffffff)
#define MISCREG_FUSEROMENCRYPTIONNVKEY3_0_VAL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define MISCREG_FUSEROMENCRYPTIONNVKEY3_0_VAL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define MISCREG_FUSEROMENCRYPTIONNVKEY3_0_VAL_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define MISCREG_FUSEROMENCRYPTIONNVKEY3_0_VAL_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)


// Register MISCREG_FUSEROMENCRYPTIONOEM1KEY0_0
#define MISCREG_FUSEROMENCRYPTIONOEM1KEY0_0                     _MK_ADDR_CONST(0x10a0)
#define MISCREG_FUSEROMENCRYPTIONOEM1KEY0_0_SECURE                      0x0
#define MISCREG_FUSEROMENCRYPTIONOEM1KEY0_0_DUAL                        0x0
#define MISCREG_FUSEROMENCRYPTIONOEM1KEY0_0_SCR                         SCRKEY_0
#define MISCREG_FUSEROMENCRYPTIONOEM1KEY0_0_WORD_COUNT                  0x1
#define MISCREG_FUSEROMENCRYPTIONOEM1KEY0_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define MISCREG_FUSEROMENCRYPTIONOEM1KEY0_0_RESET_MASK                  _MK_MASK_CONST(0xffffffff)
#define MISCREG_FUSEROMENCRYPTIONOEM1KEY0_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define MISCREG_FUSEROMENCRYPTIONOEM1KEY0_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define MISCREG_FUSEROMENCRYPTIONOEM1KEY0_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
#define MISCREG_FUSEROMENCRYPTIONOEM1KEY0_0_WRITE_MASK                  _MK_MASK_CONST(0x0)
#define MISCREG_FUSEROMENCRYPTIONOEM1KEY0_0_VAL_SHIFT                   _MK_SHIFT_CONST(0)
#define MISCREG_FUSEROMENCRYPTIONOEM1KEY0_0_VAL_FIELD                   _MK_FIELD_CONST(0xffffffff, MISCREG_FUSEROMENCRYPTIONOEM1KEY0_0_VAL_SHIFT)
#define MISCREG_FUSEROMENCRYPTIONOEM1KEY0_0_VAL_RANGE                   31:0
#define MISCREG_FUSEROMENCRYPTIONOEM1KEY0_0_VAL_WOFFSET                 0x0
#define MISCREG_FUSEROMENCRYPTIONOEM1KEY0_0_VAL_DEFAULT                 _MK_MASK_CONST(0x0)
#define MISCREG_FUSEROMENCRYPTIONOEM1KEY0_0_VAL_DEFAULT_MASK                    _MK_MASK_CONST(0xffffffff)
#define MISCREG_FUSEROMENCRYPTIONOEM1KEY0_0_VAL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define MISCREG_FUSEROMENCRYPTIONOEM1KEY0_0_VAL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define MISCREG_FUSEROMENCRYPTIONOEM1KEY0_0_VAL_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define MISCREG_FUSEROMENCRYPTIONOEM1KEY0_0_VAL_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)


// Register MISCREG_FUSEROMENCRYPTIONOEM1KEY1_0
#define MISCREG_FUSEROMENCRYPTIONOEM1KEY1_0                     _MK_ADDR_CONST(0x10a4)
#define MISCREG_FUSEROMENCRYPTIONOEM1KEY1_0_SECURE                      0x0
#define MISCREG_FUSEROMENCRYPTIONOEM1KEY1_0_DUAL                        0x0
#define MISCREG_FUSEROMENCRYPTIONOEM1KEY1_0_SCR                         SCRKEY_0
#define MISCREG_FUSEROMENCRYPTIONOEM1KEY1_0_WORD_COUNT                  0x1
#define MISCREG_FUSEROMENCRYPTIONOEM1KEY1_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define MISCREG_FUSEROMENCRYPTIONOEM1KEY1_0_RESET_MASK                  _MK_MASK_CONST(0xffffffff)
#define MISCREG_FUSEROMENCRYPTIONOEM1KEY1_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define MISCREG_FUSEROMENCRYPTIONOEM1KEY1_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define MISCREG_FUSEROMENCRYPTIONOEM1KEY1_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
#define MISCREG_FUSEROMENCRYPTIONOEM1KEY1_0_WRITE_MASK                  _MK_MASK_CONST(0x0)
#define MISCREG_FUSEROMENCRYPTIONOEM1KEY1_0_VAL_SHIFT                   _MK_SHIFT_CONST(0)
#define MISCREG_FUSEROMENCRYPTIONOEM1KEY1_0_VAL_FIELD                   _MK_FIELD_CONST(0xffffffff, MISCREG_FUSEROMENCRYPTIONOEM1KEY1_0_VAL_SHIFT)
#define MISCREG_FUSEROMENCRYPTIONOEM1KEY1_0_VAL_RANGE                   31:0
#define MISCREG_FUSEROMENCRYPTIONOEM1KEY1_0_VAL_WOFFSET                 0x0
#define MISCREG_FUSEROMENCRYPTIONOEM1KEY1_0_VAL_DEFAULT                 _MK_MASK_CONST(0x0)
#define MISCREG_FUSEROMENCRYPTIONOEM1KEY1_0_VAL_DEFAULT_MASK                    _MK_MASK_CONST(0xffffffff)
#define MISCREG_FUSEROMENCRYPTIONOEM1KEY1_0_VAL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define MISCREG_FUSEROMENCRYPTIONOEM1KEY1_0_VAL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define MISCREG_FUSEROMENCRYPTIONOEM1KEY1_0_VAL_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define MISCREG_FUSEROMENCRYPTIONOEM1KEY1_0_VAL_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)


// Register MISCREG_FUSEROMENCRYPTIONOEM1KEY2_0
#define MISCREG_FUSEROMENCRYPTIONOEM1KEY2_0                     _MK_ADDR_CONST(0x10a8)
#define MISCREG_FUSEROMENCRYPTIONOEM1KEY2_0_SECURE                      0x0
#define MISCREG_FUSEROMENCRYPTIONOEM1KEY2_0_DUAL                        0x0
#define MISCREG_FUSEROMENCRYPTIONOEM1KEY2_0_SCR                         SCRKEY_0
#define MISCREG_FUSEROMENCRYPTIONOEM1KEY2_0_WORD_COUNT                  0x1
#define MISCREG_FUSEROMENCRYPTIONOEM1KEY2_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define MISCREG_FUSEROMENCRYPTIONOEM1KEY2_0_RESET_MASK                  _MK_MASK_CONST(0xffffffff)
#define MISCREG_FUSEROMENCRYPTIONOEM1KEY2_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define MISCREG_FUSEROMENCRYPTIONOEM1KEY2_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define MISCREG_FUSEROMENCRYPTIONOEM1KEY2_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
#define MISCREG_FUSEROMENCRYPTIONOEM1KEY2_0_WRITE_MASK                  _MK_MASK_CONST(0x0)
#define MISCREG_FUSEROMENCRYPTIONOEM1KEY2_0_VAL_SHIFT                   _MK_SHIFT_CONST(0)
#define MISCREG_FUSEROMENCRYPTIONOEM1KEY2_0_VAL_FIELD                   _MK_FIELD_CONST(0xffffffff, MISCREG_FUSEROMENCRYPTIONOEM1KEY2_0_VAL_SHIFT)
#define MISCREG_FUSEROMENCRYPTIONOEM1KEY2_0_VAL_RANGE                   31:0
#define MISCREG_FUSEROMENCRYPTIONOEM1KEY2_0_VAL_WOFFSET                 0x0
#define MISCREG_FUSEROMENCRYPTIONOEM1KEY2_0_VAL_DEFAULT                 _MK_MASK_CONST(0x0)
#define MISCREG_FUSEROMENCRYPTIONOEM1KEY2_0_VAL_DEFAULT_MASK                    _MK_MASK_CONST(0xffffffff)
#define MISCREG_FUSEROMENCRYPTIONOEM1KEY2_0_VAL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define MISCREG_FUSEROMENCRYPTIONOEM1KEY2_0_VAL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define MISCREG_FUSEROMENCRYPTIONOEM1KEY2_0_VAL_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define MISCREG_FUSEROMENCRYPTIONOEM1KEY2_0_VAL_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)


// Register MISCREG_FUSEROMENCRYPTIONOEM1KEY3_0
#define MISCREG_FUSEROMENCRYPTIONOEM1KEY3_0                     _MK_ADDR_CONST(0x10ac)
#define MISCREG_FUSEROMENCRYPTIONOEM1KEY3_0_SECURE                      0x0
#define MISCREG_FUSEROMENCRYPTIONOEM1KEY3_0_DUAL                        0x0
#define MISCREG_FUSEROMENCRYPTIONOEM1KEY3_0_SCR                         SCRKEY_0
#define MISCREG_FUSEROMENCRYPTIONOEM1KEY3_0_WORD_COUNT                  0x1
#define MISCREG_FUSEROMENCRYPTIONOEM1KEY3_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define MISCREG_FUSEROMENCRYPTIONOEM1KEY3_0_RESET_MASK                  _MK_MASK_CONST(0xffffffff)
#define MISCREG_FUSEROMENCRYPTIONOEM1KEY3_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define MISCREG_FUSEROMENCRYPTIONOEM1KEY3_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define MISCREG_FUSEROMENCRYPTIONOEM1KEY3_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
#define MISCREG_FUSEROMENCRYPTIONOEM1KEY3_0_WRITE_MASK                  _MK_MASK_CONST(0x0)
#define MISCREG_FUSEROMENCRYPTIONOEM1KEY3_0_VAL_SHIFT                   _MK_SHIFT_CONST(0)
#define MISCREG_FUSEROMENCRYPTIONOEM1KEY3_0_VAL_FIELD                   _MK_FIELD_CONST(0xffffffff, MISCREG_FUSEROMENCRYPTIONOEM1KEY3_0_VAL_SHIFT)
#define MISCREG_FUSEROMENCRYPTIONOEM1KEY3_0_VAL_RANGE                   31:0
#define MISCREG_FUSEROMENCRYPTIONOEM1KEY3_0_VAL_WOFFSET                 0x0
#define MISCREG_FUSEROMENCRYPTIONOEM1KEY3_0_VAL_DEFAULT                 _MK_MASK_CONST(0x0)
#define MISCREG_FUSEROMENCRYPTIONOEM1KEY3_0_VAL_DEFAULT_MASK                    _MK_MASK_CONST(0xffffffff)
#define MISCREG_FUSEROMENCRYPTIONOEM1KEY3_0_VAL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define MISCREG_FUSEROMENCRYPTIONOEM1KEY3_0_VAL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define MISCREG_FUSEROMENCRYPTIONOEM1KEY3_0_VAL_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define MISCREG_FUSEROMENCRYPTIONOEM1KEY3_0_VAL_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)


// Register MISCREG_FUSEROMENCRYPTIONOEM2KEY0_0
#define MISCREG_FUSEROMENCRYPTIONOEM2KEY0_0                     _MK_ADDR_CONST(0x10b0)
#define MISCREG_FUSEROMENCRYPTIONOEM2KEY0_0_SECURE                      0x0
#define MISCREG_FUSEROMENCRYPTIONOEM2KEY0_0_DUAL                        0x0
#define MISCREG_FUSEROMENCRYPTIONOEM2KEY0_0_SCR                         SCRKEY_0
#define MISCREG_FUSEROMENCRYPTIONOEM2KEY0_0_WORD_COUNT                  0x1
#define MISCREG_FUSEROMENCRYPTIONOEM2KEY0_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define MISCREG_FUSEROMENCRYPTIONOEM2KEY0_0_RESET_MASK                  _MK_MASK_CONST(0xffffffff)
#define MISCREG_FUSEROMENCRYPTIONOEM2KEY0_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define MISCREG_FUSEROMENCRYPTIONOEM2KEY0_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define MISCREG_FUSEROMENCRYPTIONOEM2KEY0_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
#define MISCREG_FUSEROMENCRYPTIONOEM2KEY0_0_WRITE_MASK                  _MK_MASK_CONST(0x0)
#define MISCREG_FUSEROMENCRYPTIONOEM2KEY0_0_VAL_SHIFT                   _MK_SHIFT_CONST(0)
#define MISCREG_FUSEROMENCRYPTIONOEM2KEY0_0_VAL_FIELD                   _MK_FIELD_CONST(0xffffffff, MISCREG_FUSEROMENCRYPTIONOEM2KEY0_0_VAL_SHIFT)
#define MISCREG_FUSEROMENCRYPTIONOEM2KEY0_0_VAL_RANGE                   31:0
#define MISCREG_FUSEROMENCRYPTIONOEM2KEY0_0_VAL_WOFFSET                 0x0
#define MISCREG_FUSEROMENCRYPTIONOEM2KEY0_0_VAL_DEFAULT                 _MK_MASK_CONST(0x0)
#define MISCREG_FUSEROMENCRYPTIONOEM2KEY0_0_VAL_DEFAULT_MASK                    _MK_MASK_CONST(0xffffffff)
#define MISCREG_FUSEROMENCRYPTIONOEM2KEY0_0_VAL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define MISCREG_FUSEROMENCRYPTIONOEM2KEY0_0_VAL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define MISCREG_FUSEROMENCRYPTIONOEM2KEY0_0_VAL_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define MISCREG_FUSEROMENCRYPTIONOEM2KEY0_0_VAL_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)


// Register MISCREG_FUSEROMENCRYPTIONOEM2KEY1_0
#define MISCREG_FUSEROMENCRYPTIONOEM2KEY1_0                     _MK_ADDR_CONST(0x10b4)
#define MISCREG_FUSEROMENCRYPTIONOEM2KEY1_0_SECURE                      0x0
#define MISCREG_FUSEROMENCRYPTIONOEM2KEY1_0_DUAL                        0x0
#define MISCREG_FUSEROMENCRYPTIONOEM2KEY1_0_SCR                         SCRKEY_0
#define MISCREG_FUSEROMENCRYPTIONOEM2KEY1_0_WORD_COUNT                  0x1
#define MISCREG_FUSEROMENCRYPTIONOEM2KEY1_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define MISCREG_FUSEROMENCRYPTIONOEM2KEY1_0_RESET_MASK                  _MK_MASK_CONST(0xffffffff)
#define MISCREG_FUSEROMENCRYPTIONOEM2KEY1_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define MISCREG_FUSEROMENCRYPTIONOEM2KEY1_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define MISCREG_FUSEROMENCRYPTIONOEM2KEY1_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
#define MISCREG_FUSEROMENCRYPTIONOEM2KEY1_0_WRITE_MASK                  _MK_MASK_CONST(0x0)
#define MISCREG_FUSEROMENCRYPTIONOEM2KEY1_0_VAL_SHIFT                   _MK_SHIFT_CONST(0)
#define MISCREG_FUSEROMENCRYPTIONOEM2KEY1_0_VAL_FIELD                   _MK_FIELD_CONST(0xffffffff, MISCREG_FUSEROMENCRYPTIONOEM2KEY1_0_VAL_SHIFT)
#define MISCREG_FUSEROMENCRYPTIONOEM2KEY1_0_VAL_RANGE                   31:0
#define MISCREG_FUSEROMENCRYPTIONOEM2KEY1_0_VAL_WOFFSET                 0x0
#define MISCREG_FUSEROMENCRYPTIONOEM2KEY1_0_VAL_DEFAULT                 _MK_MASK_CONST(0x0)
#define MISCREG_FUSEROMENCRYPTIONOEM2KEY1_0_VAL_DEFAULT_MASK                    _MK_MASK_CONST(0xffffffff)
#define MISCREG_FUSEROMENCRYPTIONOEM2KEY1_0_VAL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define MISCREG_FUSEROMENCRYPTIONOEM2KEY1_0_VAL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define MISCREG_FUSEROMENCRYPTIONOEM2KEY1_0_VAL_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define MISCREG_FUSEROMENCRYPTIONOEM2KEY1_0_VAL_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)


// Register MISCREG_FUSEROMENCRYPTIONOEM2KEY2_0
#define MISCREG_FUSEROMENCRYPTIONOEM2KEY2_0                     _MK_ADDR_CONST(0x10b8)
#define MISCREG_FUSEROMENCRYPTIONOEM2KEY2_0_SECURE                      0x0
#define MISCREG_FUSEROMENCRYPTIONOEM2KEY2_0_DUAL                        0x0
#define MISCREG_FUSEROMENCRYPTIONOEM2KEY2_0_SCR                         SCRKEY_0
#define MISCREG_FUSEROMENCRYPTIONOEM2KEY2_0_WORD_COUNT                  0x1
#define MISCREG_FUSEROMENCRYPTIONOEM2KEY2_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define MISCREG_FUSEROMENCRYPTIONOEM2KEY2_0_RESET_MASK                  _MK_MASK_CONST(0xffffffff)
#define MISCREG_FUSEROMENCRYPTIONOEM2KEY2_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define MISCREG_FUSEROMENCRYPTIONOEM2KEY2_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define MISCREG_FUSEROMENCRYPTIONOEM2KEY2_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
#define MISCREG_FUSEROMENCRYPTIONOEM2KEY2_0_WRITE_MASK                  _MK_MASK_CONST(0x0)
#define MISCREG_FUSEROMENCRYPTIONOEM2KEY2_0_VAL_SHIFT                   _MK_SHIFT_CONST(0)
#define MISCREG_FUSEROMENCRYPTIONOEM2KEY2_0_VAL_FIELD                   _MK_FIELD_CONST(0xffffffff, MISCREG_FUSEROMENCRYPTIONOEM2KEY2_0_VAL_SHIFT)
#define MISCREG_FUSEROMENCRYPTIONOEM2KEY2_0_VAL_RANGE                   31:0
#define MISCREG_FUSEROMENCRYPTIONOEM2KEY2_0_VAL_WOFFSET                 0x0
#define MISCREG_FUSEROMENCRYPTIONOEM2KEY2_0_VAL_DEFAULT                 _MK_MASK_CONST(0x0)
#define MISCREG_FUSEROMENCRYPTIONOEM2KEY2_0_VAL_DEFAULT_MASK                    _MK_MASK_CONST(0xffffffff)
#define MISCREG_FUSEROMENCRYPTIONOEM2KEY2_0_VAL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define MISCREG_FUSEROMENCRYPTIONOEM2KEY2_0_VAL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define MISCREG_FUSEROMENCRYPTIONOEM2KEY2_0_VAL_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define MISCREG_FUSEROMENCRYPTIONOEM2KEY2_0_VAL_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)


// Register MISCREG_FUSEROMENCRYPTIONOEM2KEY3_0
#define MISCREG_FUSEROMENCRYPTIONOEM2KEY3_0                     _MK_ADDR_CONST(0x10bc)
#define MISCREG_FUSEROMENCRYPTIONOEM2KEY3_0_SECURE                      0x0
#define MISCREG_FUSEROMENCRYPTIONOEM2KEY3_0_DUAL                        0x0
#define MISCREG_FUSEROMENCRYPTIONOEM2KEY3_0_SCR                         SCRKEY_0
#define MISCREG_FUSEROMENCRYPTIONOEM2KEY3_0_WORD_COUNT                  0x1
#define MISCREG_FUSEROMENCRYPTIONOEM2KEY3_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define MISCREG_FUSEROMENCRYPTIONOEM2KEY3_0_RESET_MASK                  _MK_MASK_CONST(0xffffffff)
#define MISCREG_FUSEROMENCRYPTIONOEM2KEY3_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define MISCREG_FUSEROMENCRYPTIONOEM2KEY3_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define MISCREG_FUSEROMENCRYPTIONOEM2KEY3_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
#define MISCREG_FUSEROMENCRYPTIONOEM2KEY3_0_WRITE_MASK                  _MK_MASK_CONST(0x0)
#define MISCREG_FUSEROMENCRYPTIONOEM2KEY3_0_VAL_SHIFT                   _MK_SHIFT_CONST(0)
#define MISCREG_FUSEROMENCRYPTIONOEM2KEY3_0_VAL_FIELD                   _MK_FIELD_CONST(0xffffffff, MISCREG_FUSEROMENCRYPTIONOEM2KEY3_0_VAL_SHIFT)
#define MISCREG_FUSEROMENCRYPTIONOEM2KEY3_0_VAL_RANGE                   31:0
#define MISCREG_FUSEROMENCRYPTIONOEM2KEY3_0_VAL_WOFFSET                 0x0
#define MISCREG_FUSEROMENCRYPTIONOEM2KEY3_0_VAL_DEFAULT                 _MK_MASK_CONST(0x0)
#define MISCREG_FUSEROMENCRYPTIONOEM2KEY3_0_VAL_DEFAULT_MASK                    _MK_MASK_CONST(0xffffffff)
#define MISCREG_FUSEROMENCRYPTIONOEM2KEY3_0_VAL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define MISCREG_FUSEROMENCRYPTIONOEM2KEY3_0_VAL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define MISCREG_FUSEROMENCRYPTIONOEM2KEY3_0_VAL_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define MISCREG_FUSEROMENCRYPTIONOEM2KEY3_0_VAL_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)


// Register MISCREG_FUSEROMENCRYPTIONOEM3KEY0_0
#define MISCREG_FUSEROMENCRYPTIONOEM3KEY0_0                     _MK_ADDR_CONST(0x10c0)
#define MISCREG_FUSEROMENCRYPTIONOEM3KEY0_0_SECURE                      0x0
#define MISCREG_FUSEROMENCRYPTIONOEM3KEY0_0_DUAL                        0x0
#define MISCREG_FUSEROMENCRYPTIONOEM3KEY0_0_SCR                         SCRKEY_0
#define MISCREG_FUSEROMENCRYPTIONOEM3KEY0_0_WORD_COUNT                  0x1
#define MISCREG_FUSEROMENCRYPTIONOEM3KEY0_0_RESET_VAL                   _MK_MASK_CONST(0x9f6500f)
#define MISCREG_FUSEROMENCRYPTIONOEM3KEY0_0_RESET_MASK                  _MK_MASK_CONST(0xffffffff)
#define MISCREG_FUSEROMENCRYPTIONOEM3KEY0_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define MISCREG_FUSEROMENCRYPTIONOEM3KEY0_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define MISCREG_FUSEROMENCRYPTIONOEM3KEY0_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
#define MISCREG_FUSEROMENCRYPTIONOEM3KEY0_0_WRITE_MASK                  _MK_MASK_CONST(0x0)
#define MISCREG_FUSEROMENCRYPTIONOEM3KEY0_0_VAL_SHIFT                   _MK_SHIFT_CONST(0)
#define MISCREG_FUSEROMENCRYPTIONOEM3KEY0_0_VAL_FIELD                   _MK_FIELD_CONST(0xffffffff, MISCREG_FUSEROMENCRYPTIONOEM3KEY0_0_VAL_SHIFT)
#define MISCREG_FUSEROMENCRYPTIONOEM3KEY0_0_VAL_RANGE                   31:0
#define MISCREG_FUSEROMENCRYPTIONOEM3KEY0_0_VAL_WOFFSET                 0x0
#define MISCREG_FUSEROMENCRYPTIONOEM3KEY0_0_VAL_DEFAULT                 _MK_MASK_CONST(0x9f6500f)
#define MISCREG_FUSEROMENCRYPTIONOEM3KEY0_0_VAL_DEFAULT_MASK                    _MK_MASK_CONST(0xffffffff)
#define MISCREG_FUSEROMENCRYPTIONOEM3KEY0_0_VAL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define MISCREG_FUSEROMENCRYPTIONOEM3KEY0_0_VAL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define MISCREG_FUSEROMENCRYPTIONOEM3KEY0_0_VAL_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define MISCREG_FUSEROMENCRYPTIONOEM3KEY0_0_VAL_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)


// Register MISCREG_FUSEROMENCRYPTIONOEM3KEY1_0
#define MISCREG_FUSEROMENCRYPTIONOEM3KEY1_0                     _MK_ADDR_CONST(0x10c4)
#define MISCREG_FUSEROMENCRYPTIONOEM3KEY1_0_SECURE                      0x0
#define MISCREG_FUSEROMENCRYPTIONOEM3KEY1_0_DUAL                        0x0
#define MISCREG_FUSEROMENCRYPTIONOEM3KEY1_0_SCR                         SCRKEY_0
#define MISCREG_FUSEROMENCRYPTIONOEM3KEY1_0_WORD_COUNT                  0x1
#define MISCREG_FUSEROMENCRYPTIONOEM3KEY1_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define MISCREG_FUSEROMENCRYPTIONOEM3KEY1_0_RESET_MASK                  _MK_MASK_CONST(0xffffffff)
#define MISCREG_FUSEROMENCRYPTIONOEM3KEY1_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define MISCREG_FUSEROMENCRYPTIONOEM3KEY1_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define MISCREG_FUSEROMENCRYPTIONOEM3KEY1_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
#define MISCREG_FUSEROMENCRYPTIONOEM3KEY1_0_WRITE_MASK                  _MK_MASK_CONST(0x0)
#define MISCREG_FUSEROMENCRYPTIONOEM3KEY1_0_VAL_SHIFT                   _MK_SHIFT_CONST(0)
#define MISCREG_FUSEROMENCRYPTIONOEM3KEY1_0_VAL_FIELD                   _MK_FIELD_CONST(0xffffffff, MISCREG_FUSEROMENCRYPTIONOEM3KEY1_0_VAL_SHIFT)
#define MISCREG_FUSEROMENCRYPTIONOEM3KEY1_0_VAL_RANGE                   31:0
#define MISCREG_FUSEROMENCRYPTIONOEM3KEY1_0_VAL_WOFFSET                 0x0
#define MISCREG_FUSEROMENCRYPTIONOEM3KEY1_0_VAL_DEFAULT                 _MK_MASK_CONST(0x0)
#define MISCREG_FUSEROMENCRYPTIONOEM3KEY1_0_VAL_DEFAULT_MASK                    _MK_MASK_CONST(0xffffffff)
#define MISCREG_FUSEROMENCRYPTIONOEM3KEY1_0_VAL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define MISCREG_FUSEROMENCRYPTIONOEM3KEY1_0_VAL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define MISCREG_FUSEROMENCRYPTIONOEM3KEY1_0_VAL_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define MISCREG_FUSEROMENCRYPTIONOEM3KEY1_0_VAL_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)


// Register MISCREG_FUSEROMENCRYPTIONOEM3KEY2_0
#define MISCREG_FUSEROMENCRYPTIONOEM3KEY2_0                     _MK_ADDR_CONST(0x10c8)
#define MISCREG_FUSEROMENCRYPTIONOEM3KEY2_0_SECURE                      0x0
#define MISCREG_FUSEROMENCRYPTIONOEM3KEY2_0_DUAL                        0x0
#define MISCREG_FUSEROMENCRYPTIONOEM3KEY2_0_SCR                         SCRKEY_0
#define MISCREG_FUSEROMENCRYPTIONOEM3KEY2_0_WORD_COUNT                  0x1
#define MISCREG_FUSEROMENCRYPTIONOEM3KEY2_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define MISCREG_FUSEROMENCRYPTIONOEM3KEY2_0_RESET_MASK                  _MK_MASK_CONST(0xffffffff)
#define MISCREG_FUSEROMENCRYPTIONOEM3KEY2_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define MISCREG_FUSEROMENCRYPTIONOEM3KEY2_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define MISCREG_FUSEROMENCRYPTIONOEM3KEY2_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
#define MISCREG_FUSEROMENCRYPTIONOEM3KEY2_0_WRITE_MASK                  _MK_MASK_CONST(0x0)
#define MISCREG_FUSEROMENCRYPTIONOEM3KEY2_0_VAL_SHIFT                   _MK_SHIFT_CONST(0)
#define MISCREG_FUSEROMENCRYPTIONOEM3KEY2_0_VAL_FIELD                   _MK_FIELD_CONST(0xffffffff, MISCREG_FUSEROMENCRYPTIONOEM3KEY2_0_VAL_SHIFT)
#define MISCREG_FUSEROMENCRYPTIONOEM3KEY2_0_VAL_RANGE                   31:0
#define MISCREG_FUSEROMENCRYPTIONOEM3KEY2_0_VAL_WOFFSET                 0x0
#define MISCREG_FUSEROMENCRYPTIONOEM3KEY2_0_VAL_DEFAULT                 _MK_MASK_CONST(0x0)
#define MISCREG_FUSEROMENCRYPTIONOEM3KEY2_0_VAL_DEFAULT_MASK                    _MK_MASK_CONST(0xffffffff)
#define MISCREG_FUSEROMENCRYPTIONOEM3KEY2_0_VAL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define MISCREG_FUSEROMENCRYPTIONOEM3KEY2_0_VAL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define MISCREG_FUSEROMENCRYPTIONOEM3KEY2_0_VAL_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define MISCREG_FUSEROMENCRYPTIONOEM3KEY2_0_VAL_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)


// Register MISCREG_FUSEROMENCRYPTIONOEM3KEY3_0
#define MISCREG_FUSEROMENCRYPTIONOEM3KEY3_0                     _MK_ADDR_CONST(0x10cc)
#define MISCREG_FUSEROMENCRYPTIONOEM3KEY3_0_SECURE                      0x0
#define MISCREG_FUSEROMENCRYPTIONOEM3KEY3_0_DUAL                        0x0
#define MISCREG_FUSEROMENCRYPTIONOEM3KEY3_0_SCR                         SCRKEY_0
#define MISCREG_FUSEROMENCRYPTIONOEM3KEY3_0_WORD_COUNT                  0x1
#define MISCREG_FUSEROMENCRYPTIONOEM3KEY3_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define MISCREG_FUSEROMENCRYPTIONOEM3KEY3_0_RESET_MASK                  _MK_MASK_CONST(0xffffffff)
#define MISCREG_FUSEROMENCRYPTIONOEM3KEY3_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define MISCREG_FUSEROMENCRYPTIONOEM3KEY3_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define MISCREG_FUSEROMENCRYPTIONOEM3KEY3_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
#define MISCREG_FUSEROMENCRYPTIONOEM3KEY3_0_WRITE_MASK                  _MK_MASK_CONST(0x0)
#define MISCREG_FUSEROMENCRYPTIONOEM3KEY3_0_VAL_SHIFT                   _MK_SHIFT_CONST(0)
#define MISCREG_FUSEROMENCRYPTIONOEM3KEY3_0_VAL_FIELD                   _MK_FIELD_CONST(0xffffffff, MISCREG_FUSEROMENCRYPTIONOEM3KEY3_0_VAL_SHIFT)
#define MISCREG_FUSEROMENCRYPTIONOEM3KEY3_0_VAL_RANGE                   31:0
#define MISCREG_FUSEROMENCRYPTIONOEM3KEY3_0_VAL_WOFFSET                 0x0
#define MISCREG_FUSEROMENCRYPTIONOEM3KEY3_0_VAL_DEFAULT                 _MK_MASK_CONST(0x0)
#define MISCREG_FUSEROMENCRYPTIONOEM3KEY3_0_VAL_DEFAULT_MASK                    _MK_MASK_CONST(0xffffffff)
#define MISCREG_FUSEROMENCRYPTIONOEM3KEY3_0_VAL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define MISCREG_FUSEROMENCRYPTIONOEM3KEY3_0_VAL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define MISCREG_FUSEROMENCRYPTIONOEM3KEY3_0_VAL_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define MISCREG_FUSEROMENCRYPTIONOEM3KEY3_0_VAL_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)


// Register MISCREG_FUSEROMENCRYPTIONOEM4KEY0_0
#define MISCREG_FUSEROMENCRYPTIONOEM4KEY0_0                     _MK_ADDR_CONST(0x10d0)
#define MISCREG_FUSEROMENCRYPTIONOEM4KEY0_0_SECURE                      0x0
#define MISCREG_FUSEROMENCRYPTIONOEM4KEY0_0_DUAL                        0x0
#define MISCREG_FUSEROMENCRYPTIONOEM4KEY0_0_SCR                         SCRKEY_0
#define MISCREG_FUSEROMENCRYPTIONOEM4KEY0_0_WORD_COUNT                  0x1
#define MISCREG_FUSEROMENCRYPTIONOEM4KEY0_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define MISCREG_FUSEROMENCRYPTIONOEM4KEY0_0_RESET_MASK                  _MK_MASK_CONST(0xffffffff)
#define MISCREG_FUSEROMENCRYPTIONOEM4KEY0_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define MISCREG_FUSEROMENCRYPTIONOEM4KEY0_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define MISCREG_FUSEROMENCRYPTIONOEM4KEY0_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
#define MISCREG_FUSEROMENCRYPTIONOEM4KEY0_0_WRITE_MASK                  _MK_MASK_CONST(0x0)
#define MISCREG_FUSEROMENCRYPTIONOEM4KEY0_0_VAL_SHIFT                   _MK_SHIFT_CONST(0)
#define MISCREG_FUSEROMENCRYPTIONOEM4KEY0_0_VAL_FIELD                   _MK_FIELD_CONST(0xffffffff, MISCREG_FUSEROMENCRYPTIONOEM4KEY0_0_VAL_SHIFT)
#define MISCREG_FUSEROMENCRYPTIONOEM4KEY0_0_VAL_RANGE                   31:0
#define MISCREG_FUSEROMENCRYPTIONOEM4KEY0_0_VAL_WOFFSET                 0x0
#define MISCREG_FUSEROMENCRYPTIONOEM4KEY0_0_VAL_DEFAULT                 _MK_MASK_CONST(0x0)
#define MISCREG_FUSEROMENCRYPTIONOEM4KEY0_0_VAL_DEFAULT_MASK                    _MK_MASK_CONST(0xffffffff)
#define MISCREG_FUSEROMENCRYPTIONOEM4KEY0_0_VAL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define MISCREG_FUSEROMENCRYPTIONOEM4KEY0_0_VAL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define MISCREG_FUSEROMENCRYPTIONOEM4KEY0_0_VAL_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define MISCREG_FUSEROMENCRYPTIONOEM4KEY0_0_VAL_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)


// Register MISCREG_FUSEROMENCRYPTIONOEM4KEY1_0
#define MISCREG_FUSEROMENCRYPTIONOEM4KEY1_0                     _MK_ADDR_CONST(0x10d4)
#define MISCREG_FUSEROMENCRYPTIONOEM4KEY1_0_SECURE                      0x0
#define MISCREG_FUSEROMENCRYPTIONOEM4KEY1_0_DUAL                        0x0
#define MISCREG_FUSEROMENCRYPTIONOEM4KEY1_0_SCR                         SCRKEY_0
#define MISCREG_FUSEROMENCRYPTIONOEM4KEY1_0_WORD_COUNT                  0x1
#define MISCREG_FUSEROMENCRYPTIONOEM4KEY1_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define MISCREG_FUSEROMENCRYPTIONOEM4KEY1_0_RESET_MASK                  _MK_MASK_CONST(0xffffffff)
#define MISCREG_FUSEROMENCRYPTIONOEM4KEY1_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define MISCREG_FUSEROMENCRYPTIONOEM4KEY1_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define MISCREG_FUSEROMENCRYPTIONOEM4KEY1_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
#define MISCREG_FUSEROMENCRYPTIONOEM4KEY1_0_WRITE_MASK                  _MK_MASK_CONST(0x0)
#define MISCREG_FUSEROMENCRYPTIONOEM4KEY1_0_VAL_SHIFT                   _MK_SHIFT_CONST(0)
#define MISCREG_FUSEROMENCRYPTIONOEM4KEY1_0_VAL_FIELD                   _MK_FIELD_CONST(0xffffffff, MISCREG_FUSEROMENCRYPTIONOEM4KEY1_0_VAL_SHIFT)
#define MISCREG_FUSEROMENCRYPTIONOEM4KEY1_0_VAL_RANGE                   31:0
#define MISCREG_FUSEROMENCRYPTIONOEM4KEY1_0_VAL_WOFFSET                 0x0
#define MISCREG_FUSEROMENCRYPTIONOEM4KEY1_0_VAL_DEFAULT                 _MK_MASK_CONST(0x0)
#define MISCREG_FUSEROMENCRYPTIONOEM4KEY1_0_VAL_DEFAULT_MASK                    _MK_MASK_CONST(0xffffffff)
#define MISCREG_FUSEROMENCRYPTIONOEM4KEY1_0_VAL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define MISCREG_FUSEROMENCRYPTIONOEM4KEY1_0_VAL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define MISCREG_FUSEROMENCRYPTIONOEM4KEY1_0_VAL_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define MISCREG_FUSEROMENCRYPTIONOEM4KEY1_0_VAL_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)


// Register MISCREG_FUSEROMENCRYPTIONOEM4KEY2_0
#define MISCREG_FUSEROMENCRYPTIONOEM4KEY2_0                     _MK_ADDR_CONST(0x10d8)
#define MISCREG_FUSEROMENCRYPTIONOEM4KEY2_0_SECURE                      0x0
#define MISCREG_FUSEROMENCRYPTIONOEM4KEY2_0_DUAL                        0x0
#define MISCREG_FUSEROMENCRYPTIONOEM4KEY2_0_SCR                         SCRKEY_0
#define MISCREG_FUSEROMENCRYPTIONOEM4KEY2_0_WORD_COUNT                  0x1
#define MISCREG_FUSEROMENCRYPTIONOEM4KEY2_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define MISCREG_FUSEROMENCRYPTIONOEM4KEY2_0_RESET_MASK                  _MK_MASK_CONST(0xffffffff)
#define MISCREG_FUSEROMENCRYPTIONOEM4KEY2_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define MISCREG_FUSEROMENCRYPTIONOEM4KEY2_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define MISCREG_FUSEROMENCRYPTIONOEM4KEY2_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
#define MISCREG_FUSEROMENCRYPTIONOEM4KEY2_0_WRITE_MASK                  _MK_MASK_CONST(0x0)
#define MISCREG_FUSEROMENCRYPTIONOEM4KEY2_0_VAL_SHIFT                   _MK_SHIFT_CONST(0)
#define MISCREG_FUSEROMENCRYPTIONOEM4KEY2_0_VAL_FIELD                   _MK_FIELD_CONST(0xffffffff, MISCREG_FUSEROMENCRYPTIONOEM4KEY2_0_VAL_SHIFT)
#define MISCREG_FUSEROMENCRYPTIONOEM4KEY2_0_VAL_RANGE                   31:0
#define MISCREG_FUSEROMENCRYPTIONOEM4KEY2_0_VAL_WOFFSET                 0x0
#define MISCREG_FUSEROMENCRYPTIONOEM4KEY2_0_VAL_DEFAULT                 _MK_MASK_CONST(0x0)
#define MISCREG_FUSEROMENCRYPTIONOEM4KEY2_0_VAL_DEFAULT_MASK                    _MK_MASK_CONST(0xffffffff)
#define MISCREG_FUSEROMENCRYPTIONOEM4KEY2_0_VAL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define MISCREG_FUSEROMENCRYPTIONOEM4KEY2_0_VAL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define MISCREG_FUSEROMENCRYPTIONOEM4KEY2_0_VAL_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define MISCREG_FUSEROMENCRYPTIONOEM4KEY2_0_VAL_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)


// Register MISCREG_FUSEROMENCRYPTIONOEM4KEY3_0
#define MISCREG_FUSEROMENCRYPTIONOEM4KEY3_0                     _MK_ADDR_CONST(0x10dc)
#define MISCREG_FUSEROMENCRYPTIONOEM4KEY3_0_SECURE                      0x0
#define MISCREG_FUSEROMENCRYPTIONOEM4KEY3_0_DUAL                        0x0
#define MISCREG_FUSEROMENCRYPTIONOEM4KEY3_0_SCR                         SCRKEY_0
#define MISCREG_FUSEROMENCRYPTIONOEM4KEY3_0_WORD_COUNT                  0x1
#define MISCREG_FUSEROMENCRYPTIONOEM4KEY3_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define MISCREG_FUSEROMENCRYPTIONOEM4KEY3_0_RESET_MASK                  _MK_MASK_CONST(0xffffffff)
#define MISCREG_FUSEROMENCRYPTIONOEM4KEY3_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define MISCREG_FUSEROMENCRYPTIONOEM4KEY3_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define MISCREG_FUSEROMENCRYPTIONOEM4KEY3_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
#define MISCREG_FUSEROMENCRYPTIONOEM4KEY3_0_WRITE_MASK                  _MK_MASK_CONST(0x0)
#define MISCREG_FUSEROMENCRYPTIONOEM4KEY3_0_VAL_SHIFT                   _MK_SHIFT_CONST(0)
#define MISCREG_FUSEROMENCRYPTIONOEM4KEY3_0_VAL_FIELD                   _MK_FIELD_CONST(0xffffffff, MISCREG_FUSEROMENCRYPTIONOEM4KEY3_0_VAL_SHIFT)
#define MISCREG_FUSEROMENCRYPTIONOEM4KEY3_0_VAL_RANGE                   31:0
#define MISCREG_FUSEROMENCRYPTIONOEM4KEY3_0_VAL_WOFFSET                 0x0
#define MISCREG_FUSEROMENCRYPTIONOEM4KEY3_0_VAL_DEFAULT                 _MK_MASK_CONST(0x0)
#define MISCREG_FUSEROMENCRYPTIONOEM4KEY3_0_VAL_DEFAULT_MASK                    _MK_MASK_CONST(0xffffffff)
#define MISCREG_FUSEROMENCRYPTIONOEM4KEY3_0_VAL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define MISCREG_FUSEROMENCRYPTIONOEM4KEY3_0_VAL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define MISCREG_FUSEROMENCRYPTIONOEM4KEY3_0_VAL_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define MISCREG_FUSEROMENCRYPTIONOEM4KEY3_0_VAL_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)


// Register MISCREG_FUSEROMENCRYPTIONOEM5KEY0_0
#define MISCREG_FUSEROMENCRYPTIONOEM5KEY0_0                     _MK_ADDR_CONST(0x10e0)
#define MISCREG_FUSEROMENCRYPTIONOEM5KEY0_0_SECURE                      0x0
#define MISCREG_FUSEROMENCRYPTIONOEM5KEY0_0_DUAL                        0x0
#define MISCREG_FUSEROMENCRYPTIONOEM5KEY0_0_SCR                         SCRKEY_0
#define MISCREG_FUSEROMENCRYPTIONOEM5KEY0_0_WORD_COUNT                  0x1
#define MISCREG_FUSEROMENCRYPTIONOEM5KEY0_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define MISCREG_FUSEROMENCRYPTIONOEM5KEY0_0_RESET_MASK                  _MK_MASK_CONST(0xffffffff)
#define MISCREG_FUSEROMENCRYPTIONOEM5KEY0_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define MISCREG_FUSEROMENCRYPTIONOEM5KEY0_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define MISCREG_FUSEROMENCRYPTIONOEM5KEY0_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
#define MISCREG_FUSEROMENCRYPTIONOEM5KEY0_0_WRITE_MASK                  _MK_MASK_CONST(0x0)
#define MISCREG_FUSEROMENCRYPTIONOEM5KEY0_0_VAL_SHIFT                   _MK_SHIFT_CONST(0)
#define MISCREG_FUSEROMENCRYPTIONOEM5KEY0_0_VAL_FIELD                   _MK_FIELD_CONST(0xffffffff, MISCREG_FUSEROMENCRYPTIONOEM5KEY0_0_VAL_SHIFT)
#define MISCREG_FUSEROMENCRYPTIONOEM5KEY0_0_VAL_RANGE                   31:0
#define MISCREG_FUSEROMENCRYPTIONOEM5KEY0_0_VAL_WOFFSET                 0x0
#define MISCREG_FUSEROMENCRYPTIONOEM5KEY0_0_VAL_DEFAULT                 _MK_MASK_CONST(0x0)
#define MISCREG_FUSEROMENCRYPTIONOEM5KEY0_0_VAL_DEFAULT_MASK                    _MK_MASK_CONST(0xffffffff)
#define MISCREG_FUSEROMENCRYPTIONOEM5KEY0_0_VAL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define MISCREG_FUSEROMENCRYPTIONOEM5KEY0_0_VAL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define MISCREG_FUSEROMENCRYPTIONOEM5KEY0_0_VAL_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define MISCREG_FUSEROMENCRYPTIONOEM5KEY0_0_VAL_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)


// Register MISCREG_FUSEROMENCRYPTIONOEM5KEY1_0
#define MISCREG_FUSEROMENCRYPTIONOEM5KEY1_0                     _MK_ADDR_CONST(0x10e4)
#define MISCREG_FUSEROMENCRYPTIONOEM5KEY1_0_SECURE                      0x0
#define MISCREG_FUSEROMENCRYPTIONOEM5KEY1_0_DUAL                        0x0
#define MISCREG_FUSEROMENCRYPTIONOEM5KEY1_0_SCR                         SCRKEY_0
#define MISCREG_FUSEROMENCRYPTIONOEM5KEY1_0_WORD_COUNT                  0x1
#define MISCREG_FUSEROMENCRYPTIONOEM5KEY1_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define MISCREG_FUSEROMENCRYPTIONOEM5KEY1_0_RESET_MASK                  _MK_MASK_CONST(0xffffffff)
#define MISCREG_FUSEROMENCRYPTIONOEM5KEY1_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define MISCREG_FUSEROMENCRYPTIONOEM5KEY1_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define MISCREG_FUSEROMENCRYPTIONOEM5KEY1_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
#define MISCREG_FUSEROMENCRYPTIONOEM5KEY1_0_WRITE_MASK                  _MK_MASK_CONST(0x0)
#define MISCREG_FUSEROMENCRYPTIONOEM5KEY1_0_VAL_SHIFT                   _MK_SHIFT_CONST(0)
#define MISCREG_FUSEROMENCRYPTIONOEM5KEY1_0_VAL_FIELD                   _MK_FIELD_CONST(0xffffffff, MISCREG_FUSEROMENCRYPTIONOEM5KEY1_0_VAL_SHIFT)
#define MISCREG_FUSEROMENCRYPTIONOEM5KEY1_0_VAL_RANGE                   31:0
#define MISCREG_FUSEROMENCRYPTIONOEM5KEY1_0_VAL_WOFFSET                 0x0
#define MISCREG_FUSEROMENCRYPTIONOEM5KEY1_0_VAL_DEFAULT                 _MK_MASK_CONST(0x0)
#define MISCREG_FUSEROMENCRYPTIONOEM5KEY1_0_VAL_DEFAULT_MASK                    _MK_MASK_CONST(0xffffffff)
#define MISCREG_FUSEROMENCRYPTIONOEM5KEY1_0_VAL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define MISCREG_FUSEROMENCRYPTIONOEM5KEY1_0_VAL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define MISCREG_FUSEROMENCRYPTIONOEM5KEY1_0_VAL_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define MISCREG_FUSEROMENCRYPTIONOEM5KEY1_0_VAL_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)


// Register MISCREG_FUSEROMENCRYPTIONOEM5KEY2_0
#define MISCREG_FUSEROMENCRYPTIONOEM5KEY2_0                     _MK_ADDR_CONST(0x10e8)
#define MISCREG_FUSEROMENCRYPTIONOEM5KEY2_0_SECURE                      0x0
#define MISCREG_FUSEROMENCRYPTIONOEM5KEY2_0_DUAL                        0x0
#define MISCREG_FUSEROMENCRYPTIONOEM5KEY2_0_SCR                         SCRKEY_0
#define MISCREG_FUSEROMENCRYPTIONOEM5KEY2_0_WORD_COUNT                  0x1
#define MISCREG_FUSEROMENCRYPTIONOEM5KEY2_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define MISCREG_FUSEROMENCRYPTIONOEM5KEY2_0_RESET_MASK                  _MK_MASK_CONST(0xffffffff)
#define MISCREG_FUSEROMENCRYPTIONOEM5KEY2_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define MISCREG_FUSEROMENCRYPTIONOEM5KEY2_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define MISCREG_FUSEROMENCRYPTIONOEM5KEY2_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
#define MISCREG_FUSEROMENCRYPTIONOEM5KEY2_0_WRITE_MASK                  _MK_MASK_CONST(0x0)
#define MISCREG_FUSEROMENCRYPTIONOEM5KEY2_0_VAL_SHIFT                   _MK_SHIFT_CONST(0)
#define MISCREG_FUSEROMENCRYPTIONOEM5KEY2_0_VAL_FIELD                   _MK_FIELD_CONST(0xffffffff, MISCREG_FUSEROMENCRYPTIONOEM5KEY2_0_VAL_SHIFT)
#define MISCREG_FUSEROMENCRYPTIONOEM5KEY2_0_VAL_RANGE                   31:0
#define MISCREG_FUSEROMENCRYPTIONOEM5KEY2_0_VAL_WOFFSET                 0x0
#define MISCREG_FUSEROMENCRYPTIONOEM5KEY2_0_VAL_DEFAULT                 _MK_MASK_CONST(0x0)
#define MISCREG_FUSEROMENCRYPTIONOEM5KEY2_0_VAL_DEFAULT_MASK                    _MK_MASK_CONST(0xffffffff)
#define MISCREG_FUSEROMENCRYPTIONOEM5KEY2_0_VAL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define MISCREG_FUSEROMENCRYPTIONOEM5KEY2_0_VAL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define MISCREG_FUSEROMENCRYPTIONOEM5KEY2_0_VAL_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define MISCREG_FUSEROMENCRYPTIONOEM5KEY2_0_VAL_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)


// Register MISCREG_FUSEROMENCRYPTIONOEM5KEY3_0
#define MISCREG_FUSEROMENCRYPTIONOEM5KEY3_0                     _MK_ADDR_CONST(0x10ec)
#define MISCREG_FUSEROMENCRYPTIONOEM5KEY3_0_SECURE                      0x0
#define MISCREG_FUSEROMENCRYPTIONOEM5KEY3_0_DUAL                        0x0
#define MISCREG_FUSEROMENCRYPTIONOEM5KEY3_0_SCR                         SCRKEY_0
#define MISCREG_FUSEROMENCRYPTIONOEM5KEY3_0_WORD_COUNT                  0x1
#define MISCREG_FUSEROMENCRYPTIONOEM5KEY3_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define MISCREG_FUSEROMENCRYPTIONOEM5KEY3_0_RESET_MASK                  _MK_MASK_CONST(0xffffffff)
#define MISCREG_FUSEROMENCRYPTIONOEM5KEY3_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define MISCREG_FUSEROMENCRYPTIONOEM5KEY3_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define MISCREG_FUSEROMENCRYPTIONOEM5KEY3_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
#define MISCREG_FUSEROMENCRYPTIONOEM5KEY3_0_WRITE_MASK                  _MK_MASK_CONST(0x0)
#define MISCREG_FUSEROMENCRYPTIONOEM5KEY3_0_VAL_SHIFT                   _MK_SHIFT_CONST(0)
#define MISCREG_FUSEROMENCRYPTIONOEM5KEY3_0_VAL_FIELD                   _MK_FIELD_CONST(0xffffffff, MISCREG_FUSEROMENCRYPTIONOEM5KEY3_0_VAL_SHIFT)
#define MISCREG_FUSEROMENCRYPTIONOEM5KEY3_0_VAL_RANGE                   31:0
#define MISCREG_FUSEROMENCRYPTIONOEM5KEY3_0_VAL_WOFFSET                 0x0
#define MISCREG_FUSEROMENCRYPTIONOEM5KEY3_0_VAL_DEFAULT                 _MK_MASK_CONST(0x0)
#define MISCREG_FUSEROMENCRYPTIONOEM5KEY3_0_VAL_DEFAULT_MASK                    _MK_MASK_CONST(0xffffffff)
#define MISCREG_FUSEROMENCRYPTIONOEM5KEY3_0_VAL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define MISCREG_FUSEROMENCRYPTIONOEM5KEY3_0_VAL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define MISCREG_FUSEROMENCRYPTIONOEM5KEY3_0_VAL_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define MISCREG_FUSEROMENCRYPTIONOEM5KEY3_0_VAL_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)


// Register MISCREG_FUSEROMENCRYPTIONOEM6KEY0_0
#define MISCREG_FUSEROMENCRYPTIONOEM6KEY0_0                     _MK_ADDR_CONST(0x10f0)
#define MISCREG_FUSEROMENCRYPTIONOEM6KEY0_0_SECURE                      0x0
#define MISCREG_FUSEROMENCRYPTIONOEM6KEY0_0_DUAL                        0x0
#define MISCREG_FUSEROMENCRYPTIONOEM6KEY0_0_SCR                         SCRKEY_0
#define MISCREG_FUSEROMENCRYPTIONOEM6KEY0_0_WORD_COUNT                  0x1
#define MISCREG_FUSEROMENCRYPTIONOEM6KEY0_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define MISCREG_FUSEROMENCRYPTIONOEM6KEY0_0_RESET_MASK                  _MK_MASK_CONST(0xffffffff)
#define MISCREG_FUSEROMENCRYPTIONOEM6KEY0_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define MISCREG_FUSEROMENCRYPTIONOEM6KEY0_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define MISCREG_FUSEROMENCRYPTIONOEM6KEY0_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
#define MISCREG_FUSEROMENCRYPTIONOEM6KEY0_0_WRITE_MASK                  _MK_MASK_CONST(0x0)
#define MISCREG_FUSEROMENCRYPTIONOEM6KEY0_0_VAL_SHIFT                   _MK_SHIFT_CONST(0)
#define MISCREG_FUSEROMENCRYPTIONOEM6KEY0_0_VAL_FIELD                   _MK_FIELD_CONST(0xffffffff, MISCREG_FUSEROMENCRYPTIONOEM6KEY0_0_VAL_SHIFT)
#define MISCREG_FUSEROMENCRYPTIONOEM6KEY0_0_VAL_RANGE                   31:0
#define MISCREG_FUSEROMENCRYPTIONOEM6KEY0_0_VAL_WOFFSET                 0x0
#define MISCREG_FUSEROMENCRYPTIONOEM6KEY0_0_VAL_DEFAULT                 _MK_MASK_CONST(0x0)
#define MISCREG_FUSEROMENCRYPTIONOEM6KEY0_0_VAL_DEFAULT_MASK                    _MK_MASK_CONST(0xffffffff)
#define MISCREG_FUSEROMENCRYPTIONOEM6KEY0_0_VAL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define MISCREG_FUSEROMENCRYPTIONOEM6KEY0_0_VAL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define MISCREG_FUSEROMENCRYPTIONOEM6KEY0_0_VAL_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define MISCREG_FUSEROMENCRYPTIONOEM6KEY0_0_VAL_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)


// Register MISCREG_FUSEROMENCRYPTIONOEM6KEY1_0
#define MISCREG_FUSEROMENCRYPTIONOEM6KEY1_0                     _MK_ADDR_CONST(0x10f4)
#define MISCREG_FUSEROMENCRYPTIONOEM6KEY1_0_SECURE                      0x0
#define MISCREG_FUSEROMENCRYPTIONOEM6KEY1_0_DUAL                        0x0
#define MISCREG_FUSEROMENCRYPTIONOEM6KEY1_0_SCR                         SCRKEY_0
#define MISCREG_FUSEROMENCRYPTIONOEM6KEY1_0_WORD_COUNT                  0x1
#define MISCREG_FUSEROMENCRYPTIONOEM6KEY1_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define MISCREG_FUSEROMENCRYPTIONOEM6KEY1_0_RESET_MASK                  _MK_MASK_CONST(0xffffffff)
#define MISCREG_FUSEROMENCRYPTIONOEM6KEY1_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define MISCREG_FUSEROMENCRYPTIONOEM6KEY1_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define MISCREG_FUSEROMENCRYPTIONOEM6KEY1_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
#define MISCREG_FUSEROMENCRYPTIONOEM6KEY1_0_WRITE_MASK                  _MK_MASK_CONST(0x0)
#define MISCREG_FUSEROMENCRYPTIONOEM6KEY1_0_VAL_SHIFT                   _MK_SHIFT_CONST(0)
#define MISCREG_FUSEROMENCRYPTIONOEM6KEY1_0_VAL_FIELD                   _MK_FIELD_CONST(0xffffffff, MISCREG_FUSEROMENCRYPTIONOEM6KEY1_0_VAL_SHIFT)
#define MISCREG_FUSEROMENCRYPTIONOEM6KEY1_0_VAL_RANGE                   31:0
#define MISCREG_FUSEROMENCRYPTIONOEM6KEY1_0_VAL_WOFFSET                 0x0
#define MISCREG_FUSEROMENCRYPTIONOEM6KEY1_0_VAL_DEFAULT                 _MK_MASK_CONST(0x0)
#define MISCREG_FUSEROMENCRYPTIONOEM6KEY1_0_VAL_DEFAULT_MASK                    _MK_MASK_CONST(0xffffffff)
#define MISCREG_FUSEROMENCRYPTIONOEM6KEY1_0_VAL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define MISCREG_FUSEROMENCRYPTIONOEM6KEY1_0_VAL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define MISCREG_FUSEROMENCRYPTIONOEM6KEY1_0_VAL_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define MISCREG_FUSEROMENCRYPTIONOEM6KEY1_0_VAL_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)


// Register MISCREG_FUSEROMENCRYPTIONOEM6KEY2_0
#define MISCREG_FUSEROMENCRYPTIONOEM6KEY2_0                     _MK_ADDR_CONST(0x10f8)
#define MISCREG_FUSEROMENCRYPTIONOEM6KEY2_0_SECURE                      0x0
#define MISCREG_FUSEROMENCRYPTIONOEM6KEY2_0_DUAL                        0x0
#define MISCREG_FUSEROMENCRYPTIONOEM6KEY2_0_SCR                         SCRKEY_0
#define MISCREG_FUSEROMENCRYPTIONOEM6KEY2_0_WORD_COUNT                  0x1
#define MISCREG_FUSEROMENCRYPTIONOEM6KEY2_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define MISCREG_FUSEROMENCRYPTIONOEM6KEY2_0_RESET_MASK                  _MK_MASK_CONST(0xffffffff)
#define MISCREG_FUSEROMENCRYPTIONOEM6KEY2_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define MISCREG_FUSEROMENCRYPTIONOEM6KEY2_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define MISCREG_FUSEROMENCRYPTIONOEM6KEY2_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
#define MISCREG_FUSEROMENCRYPTIONOEM6KEY2_0_WRITE_MASK                  _MK_MASK_CONST(0x0)
#define MISCREG_FUSEROMENCRYPTIONOEM6KEY2_0_VAL_SHIFT                   _MK_SHIFT_CONST(0)
#define MISCREG_FUSEROMENCRYPTIONOEM6KEY2_0_VAL_FIELD                   _MK_FIELD_CONST(0xffffffff, MISCREG_FUSEROMENCRYPTIONOEM6KEY2_0_VAL_SHIFT)
#define MISCREG_FUSEROMENCRYPTIONOEM6KEY2_0_VAL_RANGE                   31:0
#define MISCREG_FUSEROMENCRYPTIONOEM6KEY2_0_VAL_WOFFSET                 0x0
#define MISCREG_FUSEROMENCRYPTIONOEM6KEY2_0_VAL_DEFAULT                 _MK_MASK_CONST(0x0)
#define MISCREG_FUSEROMENCRYPTIONOEM6KEY2_0_VAL_DEFAULT_MASK                    _MK_MASK_CONST(0xffffffff)
#define MISCREG_FUSEROMENCRYPTIONOEM6KEY2_0_VAL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define MISCREG_FUSEROMENCRYPTIONOEM6KEY2_0_VAL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define MISCREG_FUSEROMENCRYPTIONOEM6KEY2_0_VAL_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define MISCREG_FUSEROMENCRYPTIONOEM6KEY2_0_VAL_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)


// Register MISCREG_FUSEROMENCRYPTIONOEM6KEY3_0
#define MISCREG_FUSEROMENCRYPTIONOEM6KEY3_0                     _MK_ADDR_CONST(0x10fc)
#define MISCREG_FUSEROMENCRYPTIONOEM6KEY3_0_SECURE                      0x0
#define MISCREG_FUSEROMENCRYPTIONOEM6KEY3_0_DUAL                        0x0
#define MISCREG_FUSEROMENCRYPTIONOEM6KEY3_0_SCR                         SCRKEY_0
#define MISCREG_FUSEROMENCRYPTIONOEM6KEY3_0_WORD_COUNT                  0x1
#define MISCREG_FUSEROMENCRYPTIONOEM6KEY3_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define MISCREG_FUSEROMENCRYPTIONOEM6KEY3_0_RESET_MASK                  _MK_MASK_CONST(0xffffffff)
#define MISCREG_FUSEROMENCRYPTIONOEM6KEY3_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define MISCREG_FUSEROMENCRYPTIONOEM6KEY3_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define MISCREG_FUSEROMENCRYPTIONOEM6KEY3_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
#define MISCREG_FUSEROMENCRYPTIONOEM6KEY3_0_WRITE_MASK                  _MK_MASK_CONST(0x0)
#define MISCREG_FUSEROMENCRYPTIONOEM6KEY3_0_VAL_SHIFT                   _MK_SHIFT_CONST(0)
#define MISCREG_FUSEROMENCRYPTIONOEM6KEY3_0_VAL_FIELD                   _MK_FIELD_CONST(0xffffffff, MISCREG_FUSEROMENCRYPTIONOEM6KEY3_0_VAL_SHIFT)
#define MISCREG_FUSEROMENCRYPTIONOEM6KEY3_0_VAL_RANGE                   31:0
#define MISCREG_FUSEROMENCRYPTIONOEM6KEY3_0_VAL_WOFFSET                 0x0
#define MISCREG_FUSEROMENCRYPTIONOEM6KEY3_0_VAL_DEFAULT                 _MK_MASK_CONST(0x0)
#define MISCREG_FUSEROMENCRYPTIONOEM6KEY3_0_VAL_DEFAULT_MASK                    _MK_MASK_CONST(0xffffffff)
#define MISCREG_FUSEROMENCRYPTIONOEM6KEY3_0_VAL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define MISCREG_FUSEROMENCRYPTIONOEM6KEY3_0_VAL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define MISCREG_FUSEROMENCRYPTIONOEM6KEY3_0_VAL_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define MISCREG_FUSEROMENCRYPTIONOEM6KEY3_0_VAL_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)


// Register MISCREG_AON_ERR_CONFIG_0
#define MISCREG_AON_ERR_CONFIG_0                        _MK_ADDR_CONST(0x1200)
#define MISCREG_AON_ERR_CONFIG_0_SECURE                         0x0
#define MISCREG_AON_ERR_CONFIG_0_DUAL                   0x0
#define MISCREG_AON_ERR_CONFIG_0_SCR                    SCRERD_AON_0
#define MISCREG_AON_ERR_CONFIG_0_WORD_COUNT                     0x1
#define MISCREG_AON_ERR_CONFIG_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define MISCREG_AON_ERR_CONFIG_0_RESET_MASK                     _MK_MASK_CONST(0x1)
#define MISCREG_AON_ERR_CONFIG_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define MISCREG_AON_ERR_CONFIG_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define MISCREG_AON_ERR_CONFIG_0_READ_MASK                      _MK_MASK_CONST(0x1)
#define MISCREG_AON_ERR_CONFIG_0_WRITE_MASK                     _MK_MASK_CONST(0x1)
#define MISCREG_AON_ERR_CONFIG_0_ERD_SHIFT                      _MK_SHIFT_CONST(0)
#define MISCREG_AON_ERR_CONFIG_0_ERD_FIELD                      _MK_FIELD_CONST(0x1, MISCREG_AON_ERR_CONFIG_0_ERD_SHIFT)
#define MISCREG_AON_ERR_CONFIG_0_ERD_RANGE                      0:0
#define MISCREG_AON_ERR_CONFIG_0_ERD_WOFFSET                    0x0
#define MISCREG_AON_ERR_CONFIG_0_ERD_DEFAULT                    _MK_MASK_CONST(0x0)
#define MISCREG_AON_ERR_CONFIG_0_ERD_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define MISCREG_AON_ERR_CONFIG_0_ERD_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define MISCREG_AON_ERR_CONFIG_0_ERD_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define MISCREG_AON_ERR_CONFIG_0_ERD_PARITY_PROTECTION                  _MK_MASK_CONST(0x1)
#define MISCREG_AON_ERR_CONFIG_0_ERD_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)


// Register MISCREG_APE_ERR_CONFIG_0
#define MISCREG_APE_ERR_CONFIG_0                        _MK_ADDR_CONST(0x1204)
#define MISCREG_APE_ERR_CONFIG_0_SECURE                         0x0
#define MISCREG_APE_ERR_CONFIG_0_DUAL                   0x0
#define MISCREG_APE_ERR_CONFIG_0_SCR                    SCRERD_APE_0
#define MISCREG_APE_ERR_CONFIG_0_WORD_COUNT                     0x1
#define MISCREG_APE_ERR_CONFIG_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define MISCREG_APE_ERR_CONFIG_0_RESET_MASK                     _MK_MASK_CONST(0x1)
#define MISCREG_APE_ERR_CONFIG_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define MISCREG_APE_ERR_CONFIG_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define MISCREG_APE_ERR_CONFIG_0_READ_MASK                      _MK_MASK_CONST(0x1)
#define MISCREG_APE_ERR_CONFIG_0_WRITE_MASK                     _MK_MASK_CONST(0x1)
#define MISCREG_APE_ERR_CONFIG_0_ERD_SHIFT                      _MK_SHIFT_CONST(0)
#define MISCREG_APE_ERR_CONFIG_0_ERD_FIELD                      _MK_FIELD_CONST(0x1, MISCREG_APE_ERR_CONFIG_0_ERD_SHIFT)
#define MISCREG_APE_ERR_CONFIG_0_ERD_RANGE                      0:0
#define MISCREG_APE_ERR_CONFIG_0_ERD_WOFFSET                    0x0
#define MISCREG_APE_ERR_CONFIG_0_ERD_DEFAULT                    _MK_MASK_CONST(0x0)
#define MISCREG_APE_ERR_CONFIG_0_ERD_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define MISCREG_APE_ERR_CONFIG_0_ERD_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define MISCREG_APE_ERR_CONFIG_0_ERD_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define MISCREG_APE_ERR_CONFIG_0_ERD_PARITY_PROTECTION                  _MK_MASK_CONST(0x1)
#define MISCREG_APE_ERR_CONFIG_0_ERD_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)


// Register MISCREG_BPMP_ERR_CONFIG_0
#define MISCREG_BPMP_ERR_CONFIG_0                       _MK_ADDR_CONST(0x1208)
#define MISCREG_BPMP_ERR_CONFIG_0_SECURE                        0x0
#define MISCREG_BPMP_ERR_CONFIG_0_DUAL                  0x0
#define MISCREG_BPMP_ERR_CONFIG_0_SCR                   SCRERD_BPMP_0
#define MISCREG_BPMP_ERR_CONFIG_0_WORD_COUNT                    0x1
#define MISCREG_BPMP_ERR_CONFIG_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define MISCREG_BPMP_ERR_CONFIG_0_RESET_MASK                    _MK_MASK_CONST(0x1)
#define MISCREG_BPMP_ERR_CONFIG_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define MISCREG_BPMP_ERR_CONFIG_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define MISCREG_BPMP_ERR_CONFIG_0_READ_MASK                     _MK_MASK_CONST(0x1)
#define MISCREG_BPMP_ERR_CONFIG_0_WRITE_MASK                    _MK_MASK_CONST(0x1)
#define MISCREG_BPMP_ERR_CONFIG_0_ERD_SHIFT                     _MK_SHIFT_CONST(0)
#define MISCREG_BPMP_ERR_CONFIG_0_ERD_FIELD                     _MK_FIELD_CONST(0x1, MISCREG_BPMP_ERR_CONFIG_0_ERD_SHIFT)
#define MISCREG_BPMP_ERR_CONFIG_0_ERD_RANGE                     0:0
#define MISCREG_BPMP_ERR_CONFIG_0_ERD_WOFFSET                   0x0
#define MISCREG_BPMP_ERR_CONFIG_0_ERD_DEFAULT                   _MK_MASK_CONST(0x0)
#define MISCREG_BPMP_ERR_CONFIG_0_ERD_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define MISCREG_BPMP_ERR_CONFIG_0_ERD_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define MISCREG_BPMP_ERR_CONFIG_0_ERD_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define MISCREG_BPMP_ERR_CONFIG_0_ERD_PARITY_PROTECTION                 _MK_MASK_CONST(0x1)
#define MISCREG_BPMP_ERR_CONFIG_0_ERD_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)


// Register MISCREG_CCROC_ERR_CONFIG_0
#define MISCREG_CCROC_ERR_CONFIG_0                      _MK_ADDR_CONST(0x120c)
#define MISCREG_CCROC_ERR_CONFIG_0_SECURE                       0x0
#define MISCREG_CCROC_ERR_CONFIG_0_DUAL                         0x0
#define MISCREG_CCROC_ERR_CONFIG_0_SCR                  SCRERD_CCROC_0
#define MISCREG_CCROC_ERR_CONFIG_0_WORD_COUNT                   0x1
#define MISCREG_CCROC_ERR_CONFIG_0_RESET_VAL                    _MK_MASK_CONST(0x0)
#define MISCREG_CCROC_ERR_CONFIG_0_RESET_MASK                   _MK_MASK_CONST(0x1)
#define MISCREG_CCROC_ERR_CONFIG_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define MISCREG_CCROC_ERR_CONFIG_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define MISCREG_CCROC_ERR_CONFIG_0_READ_MASK                    _MK_MASK_CONST(0x1)
#define MISCREG_CCROC_ERR_CONFIG_0_WRITE_MASK                   _MK_MASK_CONST(0x1)
#define MISCREG_CCROC_ERR_CONFIG_0_ERD_SHIFT                    _MK_SHIFT_CONST(0)
#define MISCREG_CCROC_ERR_CONFIG_0_ERD_FIELD                    _MK_FIELD_CONST(0x1, MISCREG_CCROC_ERR_CONFIG_0_ERD_SHIFT)
#define MISCREG_CCROC_ERR_CONFIG_0_ERD_RANGE                    0:0
#define MISCREG_CCROC_ERR_CONFIG_0_ERD_WOFFSET                  0x0
#define MISCREG_CCROC_ERR_CONFIG_0_ERD_DEFAULT                  _MK_MASK_CONST(0x0)
#define MISCREG_CCROC_ERR_CONFIG_0_ERD_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define MISCREG_CCROC_ERR_CONFIG_0_ERD_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define MISCREG_CCROC_ERR_CONFIG_0_ERD_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define MISCREG_CCROC_ERR_CONFIG_0_ERD_PARITY_PROTECTION                        _MK_MASK_CONST(0x1)
#define MISCREG_CCROC_ERR_CONFIG_0_ERD_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)


// Register MISCREG_CSITE_ERR_CONFIG_0
#define MISCREG_CSITE_ERR_CONFIG_0                      _MK_ADDR_CONST(0x1210)
#define MISCREG_CSITE_ERR_CONFIG_0_SECURE                       0x0
#define MISCREG_CSITE_ERR_CONFIG_0_DUAL                         0x0
#define MISCREG_CSITE_ERR_CONFIG_0_SCR                  SCRERD_CSITE_0
#define MISCREG_CSITE_ERR_CONFIG_0_WORD_COUNT                   0x1
#define MISCREG_CSITE_ERR_CONFIG_0_RESET_VAL                    _MK_MASK_CONST(0x0)
#define MISCREG_CSITE_ERR_CONFIG_0_RESET_MASK                   _MK_MASK_CONST(0x1)
#define MISCREG_CSITE_ERR_CONFIG_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define MISCREG_CSITE_ERR_CONFIG_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define MISCREG_CSITE_ERR_CONFIG_0_READ_MASK                    _MK_MASK_CONST(0x1)
#define MISCREG_CSITE_ERR_CONFIG_0_WRITE_MASK                   _MK_MASK_CONST(0x1)
#define MISCREG_CSITE_ERR_CONFIG_0_ERD_SHIFT                    _MK_SHIFT_CONST(0)
#define MISCREG_CSITE_ERR_CONFIG_0_ERD_FIELD                    _MK_FIELD_CONST(0x1, MISCREG_CSITE_ERR_CONFIG_0_ERD_SHIFT)
#define MISCREG_CSITE_ERR_CONFIG_0_ERD_RANGE                    0:0
#define MISCREG_CSITE_ERR_CONFIG_0_ERD_WOFFSET                  0x0
#define MISCREG_CSITE_ERR_CONFIG_0_ERD_DEFAULT                  _MK_MASK_CONST(0x0)
#define MISCREG_CSITE_ERR_CONFIG_0_ERD_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define MISCREG_CSITE_ERR_CONFIG_0_ERD_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define MISCREG_CSITE_ERR_CONFIG_0_ERD_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define MISCREG_CSITE_ERR_CONFIG_0_ERD_PARITY_PROTECTION                        _MK_MASK_CONST(0x1)
#define MISCREG_CSITE_ERR_CONFIG_0_ERD_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)


// Register MISCREG_GPCDMA_MMIO_ERR_CONFIG_0
#define MISCREG_GPCDMA_MMIO_ERR_CONFIG_0                        _MK_ADDR_CONST(0x1214)
#define MISCREG_GPCDMA_MMIO_ERR_CONFIG_0_SECURE                         0x0
#define MISCREG_GPCDMA_MMIO_ERR_CONFIG_0_DUAL                   0x0
#define MISCREG_GPCDMA_MMIO_ERR_CONFIG_0_SCR                    SCRERD_GPCDMA_MMIO_0
#define MISCREG_GPCDMA_MMIO_ERR_CONFIG_0_WORD_COUNT                     0x1
#define MISCREG_GPCDMA_MMIO_ERR_CONFIG_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define MISCREG_GPCDMA_MMIO_ERR_CONFIG_0_RESET_MASK                     _MK_MASK_CONST(0x1)
#define MISCREG_GPCDMA_MMIO_ERR_CONFIG_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define MISCREG_GPCDMA_MMIO_ERR_CONFIG_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define MISCREG_GPCDMA_MMIO_ERR_CONFIG_0_READ_MASK                      _MK_MASK_CONST(0x1)
#define MISCREG_GPCDMA_MMIO_ERR_CONFIG_0_WRITE_MASK                     _MK_MASK_CONST(0x1)
#define MISCREG_GPCDMA_MMIO_ERR_CONFIG_0_ERD_SHIFT                      _MK_SHIFT_CONST(0)
#define MISCREG_GPCDMA_MMIO_ERR_CONFIG_0_ERD_FIELD                      _MK_FIELD_CONST(0x1, MISCREG_GPCDMA_MMIO_ERR_CONFIG_0_ERD_SHIFT)
#define MISCREG_GPCDMA_MMIO_ERR_CONFIG_0_ERD_RANGE                      0:0
#define MISCREG_GPCDMA_MMIO_ERR_CONFIG_0_ERD_WOFFSET                    0x0
#define MISCREG_GPCDMA_MMIO_ERR_CONFIG_0_ERD_DEFAULT                    _MK_MASK_CONST(0x0)
#define MISCREG_GPCDMA_MMIO_ERR_CONFIG_0_ERD_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define MISCREG_GPCDMA_MMIO_ERR_CONFIG_0_ERD_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define MISCREG_GPCDMA_MMIO_ERR_CONFIG_0_ERD_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define MISCREG_GPCDMA_MMIO_ERR_CONFIG_0_ERD_PARITY_PROTECTION                  _MK_MASK_CONST(0x1)
#define MISCREG_GPCDMA_MMIO_ERR_CONFIG_0_ERD_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)


// Register MISCREG_JTAG_ERR_CONFIG_0
#define MISCREG_JTAG_ERR_CONFIG_0                       _MK_ADDR_CONST(0x1218)
#define MISCREG_JTAG_ERR_CONFIG_0_SECURE                        0x0
#define MISCREG_JTAG_ERR_CONFIG_0_DUAL                  0x0
#define MISCREG_JTAG_ERR_CONFIG_0_SCR                   SCRERD_JTAG_0
#define MISCREG_JTAG_ERR_CONFIG_0_WORD_COUNT                    0x1
#define MISCREG_JTAG_ERR_CONFIG_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define MISCREG_JTAG_ERR_CONFIG_0_RESET_MASK                    _MK_MASK_CONST(0x1)
#define MISCREG_JTAG_ERR_CONFIG_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define MISCREG_JTAG_ERR_CONFIG_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define MISCREG_JTAG_ERR_CONFIG_0_READ_MASK                     _MK_MASK_CONST(0x1)
#define MISCREG_JTAG_ERR_CONFIG_0_WRITE_MASK                    _MK_MASK_CONST(0x1)
#define MISCREG_JTAG_ERR_CONFIG_0_ERD_SHIFT                     _MK_SHIFT_CONST(0)
#define MISCREG_JTAG_ERR_CONFIG_0_ERD_FIELD                     _MK_FIELD_CONST(0x1, MISCREG_JTAG_ERR_CONFIG_0_ERD_SHIFT)
#define MISCREG_JTAG_ERR_CONFIG_0_ERD_RANGE                     0:0
#define MISCREG_JTAG_ERR_CONFIG_0_ERD_WOFFSET                   0x0
#define MISCREG_JTAG_ERR_CONFIG_0_ERD_DEFAULT                   _MK_MASK_CONST(0x0)
#define MISCREG_JTAG_ERR_CONFIG_0_ERD_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define MISCREG_JTAG_ERR_CONFIG_0_ERD_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define MISCREG_JTAG_ERR_CONFIG_0_ERD_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define MISCREG_JTAG_ERR_CONFIG_0_ERD_PARITY_PROTECTION                 _MK_MASK_CONST(0x1)
#define MISCREG_JTAG_ERR_CONFIG_0_ERD_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)


// Register MISCREG_NVDEC_ERR_CONFIG_0
#define MISCREG_NVDEC_ERR_CONFIG_0                      _MK_ADDR_CONST(0x121c)
#define MISCREG_NVDEC_ERR_CONFIG_0_SECURE                       0x0
#define MISCREG_NVDEC_ERR_CONFIG_0_DUAL                         0x0
#define MISCREG_NVDEC_ERR_CONFIG_0_SCR                  SCRERD_NVDEC_0
#define MISCREG_NVDEC_ERR_CONFIG_0_WORD_COUNT                   0x1
#define MISCREG_NVDEC_ERR_CONFIG_0_RESET_VAL                    _MK_MASK_CONST(0x0)
#define MISCREG_NVDEC_ERR_CONFIG_0_RESET_MASK                   _MK_MASK_CONST(0x1)
#define MISCREG_NVDEC_ERR_CONFIG_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define MISCREG_NVDEC_ERR_CONFIG_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define MISCREG_NVDEC_ERR_CONFIG_0_READ_MASK                    _MK_MASK_CONST(0x1)
#define MISCREG_NVDEC_ERR_CONFIG_0_WRITE_MASK                   _MK_MASK_CONST(0x1)
#define MISCREG_NVDEC_ERR_CONFIG_0_ERD_SHIFT                    _MK_SHIFT_CONST(0)
#define MISCREG_NVDEC_ERR_CONFIG_0_ERD_FIELD                    _MK_FIELD_CONST(0x1, MISCREG_NVDEC_ERR_CONFIG_0_ERD_SHIFT)
#define MISCREG_NVDEC_ERR_CONFIG_0_ERD_RANGE                    0:0
#define MISCREG_NVDEC_ERR_CONFIG_0_ERD_WOFFSET                  0x0
#define MISCREG_NVDEC_ERR_CONFIG_0_ERD_DEFAULT                  _MK_MASK_CONST(0x0)
#define MISCREG_NVDEC_ERR_CONFIG_0_ERD_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define MISCREG_NVDEC_ERR_CONFIG_0_ERD_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define MISCREG_NVDEC_ERR_CONFIG_0_ERD_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define MISCREG_NVDEC_ERR_CONFIG_0_ERD_PARITY_PROTECTION                        _MK_MASK_CONST(0x1)
#define MISCREG_NVDEC_ERR_CONFIG_0_ERD_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)


// Register MISCREG_NVDEC1_ERR_CONFIG_0
#define MISCREG_NVDEC1_ERR_CONFIG_0                     _MK_ADDR_CONST(0x1220)
#define MISCREG_NVDEC1_ERR_CONFIG_0_SECURE                      0x0
#define MISCREG_NVDEC1_ERR_CONFIG_0_DUAL                        0x0
#define MISCREG_NVDEC1_ERR_CONFIG_0_SCR                         SCRERD_NVDEC_0
#define MISCREG_NVDEC1_ERR_CONFIG_0_WORD_COUNT                  0x1
#define MISCREG_NVDEC1_ERR_CONFIG_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define MISCREG_NVDEC1_ERR_CONFIG_0_RESET_MASK                  _MK_MASK_CONST(0x1)
#define MISCREG_NVDEC1_ERR_CONFIG_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define MISCREG_NVDEC1_ERR_CONFIG_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define MISCREG_NVDEC1_ERR_CONFIG_0_READ_MASK                   _MK_MASK_CONST(0x1)
#define MISCREG_NVDEC1_ERR_CONFIG_0_WRITE_MASK                  _MK_MASK_CONST(0x1)
#define MISCREG_NVDEC1_ERR_CONFIG_0_ERD_SHIFT                   _MK_SHIFT_CONST(0)
#define MISCREG_NVDEC1_ERR_CONFIG_0_ERD_FIELD                   _MK_FIELD_CONST(0x1, MISCREG_NVDEC1_ERR_CONFIG_0_ERD_SHIFT)
#define MISCREG_NVDEC1_ERR_CONFIG_0_ERD_RANGE                   0:0
#define MISCREG_NVDEC1_ERR_CONFIG_0_ERD_WOFFSET                 0x0
#define MISCREG_NVDEC1_ERR_CONFIG_0_ERD_DEFAULT                 _MK_MASK_CONST(0x0)
#define MISCREG_NVDEC1_ERR_CONFIG_0_ERD_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define MISCREG_NVDEC1_ERR_CONFIG_0_ERD_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define MISCREG_NVDEC1_ERR_CONFIG_0_ERD_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define MISCREG_NVDEC1_ERR_CONFIG_0_ERD_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define MISCREG_NVDEC1_ERR_CONFIG_0_ERD_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)


// Register MISCREG_RCE_ERR_CONFIG_0
#define MISCREG_RCE_ERR_CONFIG_0                        _MK_ADDR_CONST(0x1224)
#define MISCREG_RCE_ERR_CONFIG_0_SECURE                         0x0
#define MISCREG_RCE_ERR_CONFIG_0_DUAL                   0x0
#define MISCREG_RCE_ERR_CONFIG_0_SCR                    SCRERD_RCE_0
#define MISCREG_RCE_ERR_CONFIG_0_WORD_COUNT                     0x1
#define MISCREG_RCE_ERR_CONFIG_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define MISCREG_RCE_ERR_CONFIG_0_RESET_MASK                     _MK_MASK_CONST(0x1)
#define MISCREG_RCE_ERR_CONFIG_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define MISCREG_RCE_ERR_CONFIG_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define MISCREG_RCE_ERR_CONFIG_0_READ_MASK                      _MK_MASK_CONST(0x1)
#define MISCREG_RCE_ERR_CONFIG_0_WRITE_MASK                     _MK_MASK_CONST(0x1)
#define MISCREG_RCE_ERR_CONFIG_0_ERD_SHIFT                      _MK_SHIFT_CONST(0)
#define MISCREG_RCE_ERR_CONFIG_0_ERD_FIELD                      _MK_FIELD_CONST(0x1, MISCREG_RCE_ERR_CONFIG_0_ERD_SHIFT)
#define MISCREG_RCE_ERR_CONFIG_0_ERD_RANGE                      0:0
#define MISCREG_RCE_ERR_CONFIG_0_ERD_WOFFSET                    0x0
#define MISCREG_RCE_ERR_CONFIG_0_ERD_DEFAULT                    _MK_MASK_CONST(0x0)
#define MISCREG_RCE_ERR_CONFIG_0_ERD_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define MISCREG_RCE_ERR_CONFIG_0_ERD_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define MISCREG_RCE_ERR_CONFIG_0_ERD_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define MISCREG_RCE_ERR_CONFIG_0_ERD_PARITY_PROTECTION                  _MK_MASK_CONST(0x1)
#define MISCREG_RCE_ERR_CONFIG_0_ERD_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)


// Register MISCREG_SCE_ERR_CONFIG_0
#define MISCREG_SCE_ERR_CONFIG_0                        _MK_ADDR_CONST(0x1228)
#define MISCREG_SCE_ERR_CONFIG_0_SECURE                         0x0
#define MISCREG_SCE_ERR_CONFIG_0_DUAL                   0x0
#define MISCREG_SCE_ERR_CONFIG_0_SCR                    SCRERD_SCE_0
#define MISCREG_SCE_ERR_CONFIG_0_WORD_COUNT                     0x1
#define MISCREG_SCE_ERR_CONFIG_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define MISCREG_SCE_ERR_CONFIG_0_RESET_MASK                     _MK_MASK_CONST(0x1)
#define MISCREG_SCE_ERR_CONFIG_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define MISCREG_SCE_ERR_CONFIG_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define MISCREG_SCE_ERR_CONFIG_0_READ_MASK                      _MK_MASK_CONST(0x1)
#define MISCREG_SCE_ERR_CONFIG_0_WRITE_MASK                     _MK_MASK_CONST(0x1)
#define MISCREG_SCE_ERR_CONFIG_0_ERD_SHIFT                      _MK_SHIFT_CONST(0)
#define MISCREG_SCE_ERR_CONFIG_0_ERD_FIELD                      _MK_FIELD_CONST(0x1, MISCREG_SCE_ERR_CONFIG_0_ERD_SHIFT)
#define MISCREG_SCE_ERR_CONFIG_0_ERD_RANGE                      0:0
#define MISCREG_SCE_ERR_CONFIG_0_ERD_WOFFSET                    0x0
#define MISCREG_SCE_ERR_CONFIG_0_ERD_DEFAULT                    _MK_MASK_CONST(0x0)
#define MISCREG_SCE_ERR_CONFIG_0_ERD_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define MISCREG_SCE_ERR_CONFIG_0_ERD_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define MISCREG_SCE_ERR_CONFIG_0_ERD_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define MISCREG_SCE_ERR_CONFIG_0_ERD_PARITY_PROTECTION                  _MK_MASK_CONST(0x1)
#define MISCREG_SCE_ERR_CONFIG_0_ERD_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)


// Register MISCREG_TSECA_ERR_CONFIG_0
#define MISCREG_TSECA_ERR_CONFIG_0                      _MK_ADDR_CONST(0x122c)
#define MISCREG_TSECA_ERR_CONFIG_0_SECURE                       0x0
#define MISCREG_TSECA_ERR_CONFIG_0_DUAL                         0x0
#define MISCREG_TSECA_ERR_CONFIG_0_SCR                  SCRERD_TSECA_0
#define MISCREG_TSECA_ERR_CONFIG_0_WORD_COUNT                   0x1
#define MISCREG_TSECA_ERR_CONFIG_0_RESET_VAL                    _MK_MASK_CONST(0x0)
#define MISCREG_TSECA_ERR_CONFIG_0_RESET_MASK                   _MK_MASK_CONST(0x1)
#define MISCREG_TSECA_ERR_CONFIG_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define MISCREG_TSECA_ERR_CONFIG_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define MISCREG_TSECA_ERR_CONFIG_0_READ_MASK                    _MK_MASK_CONST(0x1)
#define MISCREG_TSECA_ERR_CONFIG_0_WRITE_MASK                   _MK_MASK_CONST(0x1)
#define MISCREG_TSECA_ERR_CONFIG_0_ERD_SHIFT                    _MK_SHIFT_CONST(0)
#define MISCREG_TSECA_ERR_CONFIG_0_ERD_FIELD                    _MK_FIELD_CONST(0x1, MISCREG_TSECA_ERR_CONFIG_0_ERD_SHIFT)
#define MISCREG_TSECA_ERR_CONFIG_0_ERD_RANGE                    0:0
#define MISCREG_TSECA_ERR_CONFIG_0_ERD_WOFFSET                  0x0
#define MISCREG_TSECA_ERR_CONFIG_0_ERD_DEFAULT                  _MK_MASK_CONST(0x0)
#define MISCREG_TSECA_ERR_CONFIG_0_ERD_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define MISCREG_TSECA_ERR_CONFIG_0_ERD_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define MISCREG_TSECA_ERR_CONFIG_0_ERD_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define MISCREG_TSECA_ERR_CONFIG_0_ERD_PARITY_PROTECTION                        _MK_MASK_CONST(0x1)
#define MISCREG_TSECA_ERR_CONFIG_0_ERD_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)


// Register MISCREG_TSECB_ERR_CONFIG_0
#define MISCREG_TSECB_ERR_CONFIG_0                      _MK_ADDR_CONST(0x1230)
#define MISCREG_TSECB_ERR_CONFIG_0_SECURE                       0x0
#define MISCREG_TSECB_ERR_CONFIG_0_DUAL                         0x0
#define MISCREG_TSECB_ERR_CONFIG_0_SCR                  SCRERD_TSECB_0
#define MISCREG_TSECB_ERR_CONFIG_0_WORD_COUNT                   0x1
#define MISCREG_TSECB_ERR_CONFIG_0_RESET_VAL                    _MK_MASK_CONST(0x0)
#define MISCREG_TSECB_ERR_CONFIG_0_RESET_MASK                   _MK_MASK_CONST(0x1)
#define MISCREG_TSECB_ERR_CONFIG_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define MISCREG_TSECB_ERR_CONFIG_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define MISCREG_TSECB_ERR_CONFIG_0_READ_MASK                    _MK_MASK_CONST(0x1)
#define MISCREG_TSECB_ERR_CONFIG_0_WRITE_MASK                   _MK_MASK_CONST(0x1)
#define MISCREG_TSECB_ERR_CONFIG_0_ERD_SHIFT                    _MK_SHIFT_CONST(0)
#define MISCREG_TSECB_ERR_CONFIG_0_ERD_FIELD                    _MK_FIELD_CONST(0x1, MISCREG_TSECB_ERR_CONFIG_0_ERD_SHIFT)
#define MISCREG_TSECB_ERR_CONFIG_0_ERD_RANGE                    0:0
#define MISCREG_TSECB_ERR_CONFIG_0_ERD_WOFFSET                  0x0
#define MISCREG_TSECB_ERR_CONFIG_0_ERD_DEFAULT                  _MK_MASK_CONST(0x0)
#define MISCREG_TSECB_ERR_CONFIG_0_ERD_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define MISCREG_TSECB_ERR_CONFIG_0_ERD_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define MISCREG_TSECB_ERR_CONFIG_0_ERD_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define MISCREG_TSECB_ERR_CONFIG_0_ERD_PARITY_PROTECTION                        _MK_MASK_CONST(0x1)
#define MISCREG_TSECB_ERR_CONFIG_0_ERD_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)


// Register MISCREG_IORAIL_FENCE_CONFIG_0
#define MISCREG_IORAIL_FENCE_CONFIG_0                   _MK_ADDR_CONST(0x1234)
#define MISCREG_IORAIL_FENCE_CONFIG_0_SECURE                    0x0
#define MISCREG_IORAIL_FENCE_CONFIG_0_DUAL                      0x0
#define MISCREG_IORAIL_FENCE_CONFIG_0_SCR                       SCRFENCE_0
#define MISCREG_IORAIL_FENCE_CONFIG_0_WORD_COUNT                        0x1
#define MISCREG_IORAIL_FENCE_CONFIG_0_RESET_VAL                         _MK_MASK_CONST(0x0)
#define MISCREG_IORAIL_FENCE_CONFIG_0_RESET_MASK                        _MK_MASK_CONST(0x1)
#define MISCREG_IORAIL_FENCE_CONFIG_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define MISCREG_IORAIL_FENCE_CONFIG_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define MISCREG_IORAIL_FENCE_CONFIG_0_READ_MASK                         _MK_MASK_CONST(0x1)
#define MISCREG_IORAIL_FENCE_CONFIG_0_WRITE_MASK                        _MK_MASK_CONST(0x1)
#define MISCREG_IORAIL_FENCE_CONFIG_0_FE_SHIFT                  _MK_SHIFT_CONST(0)
#define MISCREG_IORAIL_FENCE_CONFIG_0_FE_FIELD                  _MK_FIELD_CONST(0x1, MISCREG_IORAIL_FENCE_CONFIG_0_FE_SHIFT)
#define MISCREG_IORAIL_FENCE_CONFIG_0_FE_RANGE                  0:0
#define MISCREG_IORAIL_FENCE_CONFIG_0_FE_WOFFSET                        0x0
#define MISCREG_IORAIL_FENCE_CONFIG_0_FE_DEFAULT                        _MK_MASK_CONST(0x0)
#define MISCREG_IORAIL_FENCE_CONFIG_0_FE_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define MISCREG_IORAIL_FENCE_CONFIG_0_FE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define MISCREG_IORAIL_FENCE_CONFIG_0_FE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define MISCREG_IORAIL_FENCE_CONFIG_0_FE_PARITY_PROTECTION                      _MK_MASK_CONST(0x1)
#define MISCREG_IORAIL_FENCE_CONFIG_0_FE_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)


// Register MISCREG_CVRAIL_FENCE_CONFIG_0
#define MISCREG_CVRAIL_FENCE_CONFIG_0                   _MK_ADDR_CONST(0x1238)
#define MISCREG_CVRAIL_FENCE_CONFIG_0_SECURE                    0x0
#define MISCREG_CVRAIL_FENCE_CONFIG_0_DUAL                      0x0
#define MISCREG_CVRAIL_FENCE_CONFIG_0_SCR                       SCRFENCE_0
#define MISCREG_CVRAIL_FENCE_CONFIG_0_WORD_COUNT                        0x1
#define MISCREG_CVRAIL_FENCE_CONFIG_0_RESET_VAL                         _MK_MASK_CONST(0x0)
#define MISCREG_CVRAIL_FENCE_CONFIG_0_RESET_MASK                        _MK_MASK_CONST(0x1)
#define MISCREG_CVRAIL_FENCE_CONFIG_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define MISCREG_CVRAIL_FENCE_CONFIG_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define MISCREG_CVRAIL_FENCE_CONFIG_0_READ_MASK                         _MK_MASK_CONST(0x1)
#define MISCREG_CVRAIL_FENCE_CONFIG_0_WRITE_MASK                        _MK_MASK_CONST(0x1)
#define MISCREG_CVRAIL_FENCE_CONFIG_0_FE_SHIFT                  _MK_SHIFT_CONST(0)
#define MISCREG_CVRAIL_FENCE_CONFIG_0_FE_FIELD                  _MK_FIELD_CONST(0x1, MISCREG_CVRAIL_FENCE_CONFIG_0_FE_SHIFT)
#define MISCREG_CVRAIL_FENCE_CONFIG_0_FE_RANGE                  0:0
#define MISCREG_CVRAIL_FENCE_CONFIG_0_FE_WOFFSET                        0x0
#define MISCREG_CVRAIL_FENCE_CONFIG_0_FE_DEFAULT                        _MK_MASK_CONST(0x0)
#define MISCREG_CVRAIL_FENCE_CONFIG_0_FE_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define MISCREG_CVRAIL_FENCE_CONFIG_0_FE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define MISCREG_CVRAIL_FENCE_CONFIG_0_FE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define MISCREG_CVRAIL_FENCE_CONFIG_0_FE_PARITY_PROTECTION                      _MK_MASK_CONST(0x1)
#define MISCREG_CVRAIL_FENCE_CONFIG_0_FE_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)


// Register MISCREG_GPURAIL_FENCE_CONFIG_0
#define MISCREG_GPURAIL_FENCE_CONFIG_0                  _MK_ADDR_CONST(0x123c)
#define MISCREG_GPURAIL_FENCE_CONFIG_0_SECURE                   0x0
#define MISCREG_GPURAIL_FENCE_CONFIG_0_DUAL                     0x0
#define MISCREG_GPURAIL_FENCE_CONFIG_0_SCR                      SCRFENCE_0
#define MISCREG_GPURAIL_FENCE_CONFIG_0_WORD_COUNT                       0x1
#define MISCREG_GPURAIL_FENCE_CONFIG_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define MISCREG_GPURAIL_FENCE_CONFIG_0_RESET_MASK                       _MK_MASK_CONST(0x1)
#define MISCREG_GPURAIL_FENCE_CONFIG_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define MISCREG_GPURAIL_FENCE_CONFIG_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define MISCREG_GPURAIL_FENCE_CONFIG_0_READ_MASK                        _MK_MASK_CONST(0x1)
#define MISCREG_GPURAIL_FENCE_CONFIG_0_WRITE_MASK                       _MK_MASK_CONST(0x1)
#define MISCREG_GPURAIL_FENCE_CONFIG_0_FE_SHIFT                 _MK_SHIFT_CONST(0)
#define MISCREG_GPURAIL_FENCE_CONFIG_0_FE_FIELD                 _MK_FIELD_CONST(0x1, MISCREG_GPURAIL_FENCE_CONFIG_0_FE_SHIFT)
#define MISCREG_GPURAIL_FENCE_CONFIG_0_FE_RANGE                 0:0
#define MISCREG_GPURAIL_FENCE_CONFIG_0_FE_WOFFSET                       0x0
#define MISCREG_GPURAIL_FENCE_CONFIG_0_FE_DEFAULT                       _MK_MASK_CONST(0x0)
#define MISCREG_GPURAIL_FENCE_CONFIG_0_FE_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define MISCREG_GPURAIL_FENCE_CONFIG_0_FE_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define MISCREG_GPURAIL_FENCE_CONFIG_0_FE_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define MISCREG_GPURAIL_FENCE_CONFIG_0_FE_PARITY_PROTECTION                     _MK_MASK_CONST(0x1)
#define MISCREG_GPURAIL_FENCE_CONFIG_0_FE_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)


// Reserved address 0x1240

// Register MISCREG_AXIS_CENTRAL_CLK_OVR_ON_0
#define MISCREG_AXIS_CENTRAL_CLK_OVR_ON_0                       _MK_ADDR_CONST(0x1244)
#define MISCREG_AXIS_CENTRAL_CLK_OVR_ON_0_SECURE                        0x0
#define MISCREG_AXIS_CENTRAL_CLK_OVR_ON_0_DUAL                  0x0
#define MISCREG_AXIS_CENTRAL_CLK_OVR_ON_0_SCR                   SCRMISC_0
#define MISCREG_AXIS_CENTRAL_CLK_OVR_ON_0_WORD_COUNT                    0x1
#define MISCREG_AXIS_CENTRAL_CLK_OVR_ON_0_RESET_VAL                     _MK_MASK_CONST(0x1)
#define MISCREG_AXIS_CENTRAL_CLK_OVR_ON_0_RESET_MASK                    _MK_MASK_CONST(0x1)
#define MISCREG_AXIS_CENTRAL_CLK_OVR_ON_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define MISCREG_AXIS_CENTRAL_CLK_OVR_ON_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define MISCREG_AXIS_CENTRAL_CLK_OVR_ON_0_READ_MASK                     _MK_MASK_CONST(0x1)
#define MISCREG_AXIS_CENTRAL_CLK_OVR_ON_0_WRITE_MASK                    _MK_MASK_CONST(0x1)
#define MISCREG_AXIS_CENTRAL_CLK_OVR_ON_0_EN_SHIFT                      _MK_SHIFT_CONST(0)
#define MISCREG_AXIS_CENTRAL_CLK_OVR_ON_0_EN_FIELD                      _MK_FIELD_CONST(0x1, MISCREG_AXIS_CENTRAL_CLK_OVR_ON_0_EN_SHIFT)
#define MISCREG_AXIS_CENTRAL_CLK_OVR_ON_0_EN_RANGE                      0:0
#define MISCREG_AXIS_CENTRAL_CLK_OVR_ON_0_EN_WOFFSET                    0x0
#define MISCREG_AXIS_CENTRAL_CLK_OVR_ON_0_EN_DEFAULT                    _MK_MASK_CONST(0x1)
#define MISCREG_AXIS_CENTRAL_CLK_OVR_ON_0_EN_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define MISCREG_AXIS_CENTRAL_CLK_OVR_ON_0_EN_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define MISCREG_AXIS_CENTRAL_CLK_OVR_ON_0_EN_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define MISCREG_AXIS_CENTRAL_CLK_OVR_ON_0_EN_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define MISCREG_AXIS_CENTRAL_CLK_OVR_ON_0_EN_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define MISCREG_AXIS_CENTRAL_CLK_OVR_ON_0_EN_DISABLE                    _MK_ENUM_CONST(0)
#define MISCREG_AXIS_CENTRAL_CLK_OVR_ON_0_EN_ENABLE                     _MK_ENUM_CONST(1)


// Register MISCREG_AXIS_SATELLITE_AON_CLK_OVR_ON_0
#define MISCREG_AXIS_SATELLITE_AON_CLK_OVR_ON_0                 _MK_ADDR_CONST(0x1248)
#define MISCREG_AXIS_SATELLITE_AON_CLK_OVR_ON_0_SECURE                  0x0
#define MISCREG_AXIS_SATELLITE_AON_CLK_OVR_ON_0_DUAL                    0x0
#define MISCREG_AXIS_SATELLITE_AON_CLK_OVR_ON_0_SCR                     SCRMISC_0
#define MISCREG_AXIS_SATELLITE_AON_CLK_OVR_ON_0_WORD_COUNT                      0x1
#define MISCREG_AXIS_SATELLITE_AON_CLK_OVR_ON_0_RESET_VAL                       _MK_MASK_CONST(0x1)
#define MISCREG_AXIS_SATELLITE_AON_CLK_OVR_ON_0_RESET_MASK                      _MK_MASK_CONST(0x1)
#define MISCREG_AXIS_SATELLITE_AON_CLK_OVR_ON_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define MISCREG_AXIS_SATELLITE_AON_CLK_OVR_ON_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define MISCREG_AXIS_SATELLITE_AON_CLK_OVR_ON_0_READ_MASK                       _MK_MASK_CONST(0x1)
#define MISCREG_AXIS_SATELLITE_AON_CLK_OVR_ON_0_WRITE_MASK                      _MK_MASK_CONST(0x1)
#define MISCREG_AXIS_SATELLITE_AON_CLK_OVR_ON_0_EN_SHIFT                        _MK_SHIFT_CONST(0)
#define MISCREG_AXIS_SATELLITE_AON_CLK_OVR_ON_0_EN_FIELD                        _MK_FIELD_CONST(0x1, MISCREG_AXIS_SATELLITE_AON_CLK_OVR_ON_0_EN_SHIFT)
#define MISCREG_AXIS_SATELLITE_AON_CLK_OVR_ON_0_EN_RANGE                        0:0
#define MISCREG_AXIS_SATELLITE_AON_CLK_OVR_ON_0_EN_WOFFSET                      0x0
#define MISCREG_AXIS_SATELLITE_AON_CLK_OVR_ON_0_EN_DEFAULT                      _MK_MASK_CONST(0x1)
#define MISCREG_AXIS_SATELLITE_AON_CLK_OVR_ON_0_EN_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define MISCREG_AXIS_SATELLITE_AON_CLK_OVR_ON_0_EN_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define MISCREG_AXIS_SATELLITE_AON_CLK_OVR_ON_0_EN_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define MISCREG_AXIS_SATELLITE_AON_CLK_OVR_ON_0_EN_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define MISCREG_AXIS_SATELLITE_AON_CLK_OVR_ON_0_EN_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)
#define MISCREG_AXIS_SATELLITE_AON_CLK_OVR_ON_0_EN_DISABLE                      _MK_ENUM_CONST(0)
#define MISCREG_AXIS_SATELLITE_AON_CLK_OVR_ON_0_EN_ENABLE                       _MK_ENUM_CONST(1)


// Register MISCREG_AXIS_SATELLITE_AXI2APB_CLK_OVR_ON_0
#define MISCREG_AXIS_SATELLITE_AXI2APB_CLK_OVR_ON_0                     _MK_ADDR_CONST(0x124c)
#define MISCREG_AXIS_SATELLITE_AXI2APB_CLK_OVR_ON_0_SECURE                      0x0
#define MISCREG_AXIS_SATELLITE_AXI2APB_CLK_OVR_ON_0_DUAL                        0x0
#define MISCREG_AXIS_SATELLITE_AXI2APB_CLK_OVR_ON_0_SCR                         SCRMISC_0
#define MISCREG_AXIS_SATELLITE_AXI2APB_CLK_OVR_ON_0_WORD_COUNT                  0x1
#define MISCREG_AXIS_SATELLITE_AXI2APB_CLK_OVR_ON_0_RESET_VAL                   _MK_MASK_CONST(0x1)
#define MISCREG_AXIS_SATELLITE_AXI2APB_CLK_OVR_ON_0_RESET_MASK                  _MK_MASK_CONST(0x1)
#define MISCREG_AXIS_SATELLITE_AXI2APB_CLK_OVR_ON_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define MISCREG_AXIS_SATELLITE_AXI2APB_CLK_OVR_ON_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define MISCREG_AXIS_SATELLITE_AXI2APB_CLK_OVR_ON_0_READ_MASK                   _MK_MASK_CONST(0x1)
#define MISCREG_AXIS_SATELLITE_AXI2APB_CLK_OVR_ON_0_WRITE_MASK                  _MK_MASK_CONST(0x1)
#define MISCREG_AXIS_SATELLITE_AXI2APB_CLK_OVR_ON_0_EN_SHIFT                    _MK_SHIFT_CONST(0)
#define MISCREG_AXIS_SATELLITE_AXI2APB_CLK_OVR_ON_0_EN_FIELD                    _MK_FIELD_CONST(0x1, MISCREG_AXIS_SATELLITE_AXI2APB_CLK_OVR_ON_0_EN_SHIFT)
#define MISCREG_AXIS_SATELLITE_AXI2APB_CLK_OVR_ON_0_EN_RANGE                    0:0
#define MISCREG_AXIS_SATELLITE_AXI2APB_CLK_OVR_ON_0_EN_WOFFSET                  0x0
#define MISCREG_AXIS_SATELLITE_AXI2APB_CLK_OVR_ON_0_EN_DEFAULT                  _MK_MASK_CONST(0x1)
#define MISCREG_AXIS_SATELLITE_AXI2APB_CLK_OVR_ON_0_EN_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define MISCREG_AXIS_SATELLITE_AXI2APB_CLK_OVR_ON_0_EN_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define MISCREG_AXIS_SATELLITE_AXI2APB_CLK_OVR_ON_0_EN_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define MISCREG_AXIS_SATELLITE_AXI2APB_CLK_OVR_ON_0_EN_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define MISCREG_AXIS_SATELLITE_AXI2APB_CLK_OVR_ON_0_EN_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)
#define MISCREG_AXIS_SATELLITE_AXI2APB_CLK_OVR_ON_0_EN_DISABLE                  _MK_ENUM_CONST(0)
#define MISCREG_AXIS_SATELLITE_AXI2APB_CLK_OVR_ON_0_EN_ENABLE                   _MK_ENUM_CONST(1)


// Register MISCREG_AXIS_SATELLITE_PCIE_CLK_OVR_ON_0
#define MISCREG_AXIS_SATELLITE_PCIE_CLK_OVR_ON_0                        _MK_ADDR_CONST(0x1250)
#define MISCREG_AXIS_SATELLITE_PCIE_CLK_OVR_ON_0_SECURE                         0x0
#define MISCREG_AXIS_SATELLITE_PCIE_CLK_OVR_ON_0_DUAL                   0x0
#define MISCREG_AXIS_SATELLITE_PCIE_CLK_OVR_ON_0_SCR                    SCRMISC_0
#define MISCREG_AXIS_SATELLITE_PCIE_CLK_OVR_ON_0_WORD_COUNT                     0x1
#define MISCREG_AXIS_SATELLITE_PCIE_CLK_OVR_ON_0_RESET_VAL                      _MK_MASK_CONST(0x1)
#define MISCREG_AXIS_SATELLITE_PCIE_CLK_OVR_ON_0_RESET_MASK                     _MK_MASK_CONST(0x1)
#define MISCREG_AXIS_SATELLITE_PCIE_CLK_OVR_ON_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define MISCREG_AXIS_SATELLITE_PCIE_CLK_OVR_ON_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define MISCREG_AXIS_SATELLITE_PCIE_CLK_OVR_ON_0_READ_MASK                      _MK_MASK_CONST(0x1)
#define MISCREG_AXIS_SATELLITE_PCIE_CLK_OVR_ON_0_WRITE_MASK                     _MK_MASK_CONST(0x1)
#define MISCREG_AXIS_SATELLITE_PCIE_CLK_OVR_ON_0_EN_SHIFT                       _MK_SHIFT_CONST(0)
#define MISCREG_AXIS_SATELLITE_PCIE_CLK_OVR_ON_0_EN_FIELD                       _MK_FIELD_CONST(0x1, MISCREG_AXIS_SATELLITE_PCIE_CLK_OVR_ON_0_EN_SHIFT)
#define MISCREG_AXIS_SATELLITE_PCIE_CLK_OVR_ON_0_EN_RANGE                       0:0
#define MISCREG_AXIS_SATELLITE_PCIE_CLK_OVR_ON_0_EN_WOFFSET                     0x0
#define MISCREG_AXIS_SATELLITE_PCIE_CLK_OVR_ON_0_EN_DEFAULT                     _MK_MASK_CONST(0x1)
#define MISCREG_AXIS_SATELLITE_PCIE_CLK_OVR_ON_0_EN_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define MISCREG_AXIS_SATELLITE_PCIE_CLK_OVR_ON_0_EN_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define MISCREG_AXIS_SATELLITE_PCIE_CLK_OVR_ON_0_EN_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define MISCREG_AXIS_SATELLITE_PCIE_CLK_OVR_ON_0_EN_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define MISCREG_AXIS_SATELLITE_PCIE_CLK_OVR_ON_0_EN_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define MISCREG_AXIS_SATELLITE_PCIE_CLK_OVR_ON_0_EN_DISABLE                     _MK_ENUM_CONST(0)
#define MISCREG_AXIS_SATELLITE_PCIE_CLK_OVR_ON_0_EN_ENABLE                      _MK_ENUM_CONST(1)


// Register MISCREG_AXIS_SATELLITE_GROUT_CLK_OVR_ON_0
#define MISCREG_AXIS_SATELLITE_GROUT_CLK_OVR_ON_0                       _MK_ADDR_CONST(0x1254)
#define MISCREG_AXIS_SATELLITE_GROUT_CLK_OVR_ON_0_SECURE                        0x0
#define MISCREG_AXIS_SATELLITE_GROUT_CLK_OVR_ON_0_DUAL                  0x0
#define MISCREG_AXIS_SATELLITE_GROUT_CLK_OVR_ON_0_SCR                   SCRMISC_0
#define MISCREG_AXIS_SATELLITE_GROUT_CLK_OVR_ON_0_WORD_COUNT                    0x1
#define MISCREG_AXIS_SATELLITE_GROUT_CLK_OVR_ON_0_RESET_VAL                     _MK_MASK_CONST(0x1)
#define MISCREG_AXIS_SATELLITE_GROUT_CLK_OVR_ON_0_RESET_MASK                    _MK_MASK_CONST(0x1)
#define MISCREG_AXIS_SATELLITE_GROUT_CLK_OVR_ON_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define MISCREG_AXIS_SATELLITE_GROUT_CLK_OVR_ON_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define MISCREG_AXIS_SATELLITE_GROUT_CLK_OVR_ON_0_READ_MASK                     _MK_MASK_CONST(0x1)
#define MISCREG_AXIS_SATELLITE_GROUT_CLK_OVR_ON_0_WRITE_MASK                    _MK_MASK_CONST(0x1)
#define MISCREG_AXIS_SATELLITE_GROUT_CLK_OVR_ON_0_EN_SHIFT                      _MK_SHIFT_CONST(0)
#define MISCREG_AXIS_SATELLITE_GROUT_CLK_OVR_ON_0_EN_FIELD                      _MK_FIELD_CONST(0x1, MISCREG_AXIS_SATELLITE_GROUT_CLK_OVR_ON_0_EN_SHIFT)
#define MISCREG_AXIS_SATELLITE_GROUT_CLK_OVR_ON_0_EN_RANGE                      0:0
#define MISCREG_AXIS_SATELLITE_GROUT_CLK_OVR_ON_0_EN_WOFFSET                    0x0
#define MISCREG_AXIS_SATELLITE_GROUT_CLK_OVR_ON_0_EN_DEFAULT                    _MK_MASK_CONST(0x1)
#define MISCREG_AXIS_SATELLITE_GROUT_CLK_OVR_ON_0_EN_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define MISCREG_AXIS_SATELLITE_GROUT_CLK_OVR_ON_0_EN_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define MISCREG_AXIS_SATELLITE_GROUT_CLK_OVR_ON_0_EN_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define MISCREG_AXIS_SATELLITE_GROUT_CLK_OVR_ON_0_EN_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define MISCREG_AXIS_SATELLITE_GROUT_CLK_OVR_ON_0_EN_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define MISCREG_AXIS_SATELLITE_GROUT_CLK_OVR_ON_0_EN_DISABLE                    _MK_ENUM_CONST(0)
#define MISCREG_AXIS_SATELLITE_GROUT_CLK_OVR_ON_0_EN_ENABLE                     _MK_ENUM_CONST(1)


// Register MISCREG_AON_P2PS_MST_TIMEOUT_PRESCALER_CFG_0
#define MISCREG_AON_P2PS_MST_TIMEOUT_PRESCALER_CFG_0                    _MK_ADDR_CONST(0x1258)
#define MISCREG_AON_P2PS_MST_TIMEOUT_PRESCALER_CFG_0_SECURE                     0x0
#define MISCREG_AON_P2PS_MST_TIMEOUT_PRESCALER_CFG_0_DUAL                       0x0
#define MISCREG_AON_P2PS_MST_TIMEOUT_PRESCALER_CFG_0_SCR                        0
#define MISCREG_AON_P2PS_MST_TIMEOUT_PRESCALER_CFG_0_WORD_COUNT                         0x1
#define MISCREG_AON_P2PS_MST_TIMEOUT_PRESCALER_CFG_0_RESET_VAL                  _MK_MASK_CONST(0x8000000d)
#define MISCREG_AON_P2PS_MST_TIMEOUT_PRESCALER_CFG_0_RESET_MASK                         _MK_MASK_CONST(0x8000000f)
#define MISCREG_AON_P2PS_MST_TIMEOUT_PRESCALER_CFG_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define MISCREG_AON_P2PS_MST_TIMEOUT_PRESCALER_CFG_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define MISCREG_AON_P2PS_MST_TIMEOUT_PRESCALER_CFG_0_READ_MASK                  _MK_MASK_CONST(0x8000000f)
#define MISCREG_AON_P2PS_MST_TIMEOUT_PRESCALER_CFG_0_WRITE_MASK                         _MK_MASK_CONST(0x8000000f)
#define MISCREG_AON_P2PS_MST_TIMEOUT_PRESCALER_CFG_0_EXTREF_EN_SHIFT                    _MK_SHIFT_CONST(31)
#define MISCREG_AON_P2PS_MST_TIMEOUT_PRESCALER_CFG_0_EXTREF_EN_FIELD                    _MK_FIELD_CONST(0x1, MISCREG_AON_P2PS_MST_TIMEOUT_PRESCALER_CFG_0_EXTREF_EN_SHIFT)
#define MISCREG_AON_P2PS_MST_TIMEOUT_PRESCALER_CFG_0_EXTREF_EN_RANGE                    31:31
#define MISCREG_AON_P2PS_MST_TIMEOUT_PRESCALER_CFG_0_EXTREF_EN_WOFFSET                  0x0
#define MISCREG_AON_P2PS_MST_TIMEOUT_PRESCALER_CFG_0_EXTREF_EN_DEFAULT                  _MK_MASK_CONST(0x1)
#define MISCREG_AON_P2PS_MST_TIMEOUT_PRESCALER_CFG_0_EXTREF_EN_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define MISCREG_AON_P2PS_MST_TIMEOUT_PRESCALER_CFG_0_EXTREF_EN_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define MISCREG_AON_P2PS_MST_TIMEOUT_PRESCALER_CFG_0_EXTREF_EN_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define MISCREG_AON_P2PS_MST_TIMEOUT_PRESCALER_CFG_0_EXTREF_EN_PARITY_PROTECTION                        _MK_MASK_CONST(0x1)
#define MISCREG_AON_P2PS_MST_TIMEOUT_PRESCALER_CFG_0_EXTREF_EN_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)
#define MISCREG_AON_P2PS_MST_TIMEOUT_PRESCALER_CFG_0_EXTREF_EN_DISABLE                  _MK_ENUM_CONST(0)
#define MISCREG_AON_P2PS_MST_TIMEOUT_PRESCALER_CFG_0_EXTREF_EN_ENABLE                   _MK_ENUM_CONST(1)

#define MISCREG_AON_P2PS_MST_TIMEOUT_PRESCALER_CFG_0_EXTREF_SRC_SHIFT                   _MK_SHIFT_CONST(0)
#define MISCREG_AON_P2PS_MST_TIMEOUT_PRESCALER_CFG_0_EXTREF_SRC_FIELD                   _MK_FIELD_CONST(0xf, MISCREG_AON_P2PS_MST_TIMEOUT_PRESCALER_CFG_0_EXTREF_SRC_SHIFT)
#define MISCREG_AON_P2PS_MST_TIMEOUT_PRESCALER_CFG_0_EXTREF_SRC_RANGE                   3:0
#define MISCREG_AON_P2PS_MST_TIMEOUT_PRESCALER_CFG_0_EXTREF_SRC_WOFFSET                 0x0
#define MISCREG_AON_P2PS_MST_TIMEOUT_PRESCALER_CFG_0_EXTREF_SRC_DEFAULT                 _MK_MASK_CONST(0xd)
#define MISCREG_AON_P2PS_MST_TIMEOUT_PRESCALER_CFG_0_EXTREF_SRC_DEFAULT_MASK                    _MK_MASK_CONST(0xf)
#define MISCREG_AON_P2PS_MST_TIMEOUT_PRESCALER_CFG_0_EXTREF_SRC_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define MISCREG_AON_P2PS_MST_TIMEOUT_PRESCALER_CFG_0_EXTREF_SRC_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define MISCREG_AON_P2PS_MST_TIMEOUT_PRESCALER_CFG_0_EXTREF_SRC_PARITY_PROTECTION                       _MK_MASK_CONST(0x1)
#define MISCREG_AON_P2PS_MST_TIMEOUT_PRESCALER_CFG_0_EXTREF_SRC_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)


// Register MISCREG_APE_P2PS_MST_TIMEOUT_PRESCALER_CFG_0
#define MISCREG_APE_P2PS_MST_TIMEOUT_PRESCALER_CFG_0                    _MK_ADDR_CONST(0x125c)
#define MISCREG_APE_P2PS_MST_TIMEOUT_PRESCALER_CFG_0_SECURE                     0x0
#define MISCREG_APE_P2PS_MST_TIMEOUT_PRESCALER_CFG_0_DUAL                       0x0
#define MISCREG_APE_P2PS_MST_TIMEOUT_PRESCALER_CFG_0_SCR                        0
#define MISCREG_APE_P2PS_MST_TIMEOUT_PRESCALER_CFG_0_WORD_COUNT                         0x1
#define MISCREG_APE_P2PS_MST_TIMEOUT_PRESCALER_CFG_0_RESET_VAL                  _MK_MASK_CONST(0x8000000d)
#define MISCREG_APE_P2PS_MST_TIMEOUT_PRESCALER_CFG_0_RESET_MASK                         _MK_MASK_CONST(0x8000000f)
#define MISCREG_APE_P2PS_MST_TIMEOUT_PRESCALER_CFG_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define MISCREG_APE_P2PS_MST_TIMEOUT_PRESCALER_CFG_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define MISCREG_APE_P2PS_MST_TIMEOUT_PRESCALER_CFG_0_READ_MASK                  _MK_MASK_CONST(0x8000000f)
#define MISCREG_APE_P2PS_MST_TIMEOUT_PRESCALER_CFG_0_WRITE_MASK                         _MK_MASK_CONST(0x8000000f)
#define MISCREG_APE_P2PS_MST_TIMEOUT_PRESCALER_CFG_0_EXTREF_EN_SHIFT                    _MK_SHIFT_CONST(31)
#define MISCREG_APE_P2PS_MST_TIMEOUT_PRESCALER_CFG_0_EXTREF_EN_FIELD                    _MK_FIELD_CONST(0x1, MISCREG_APE_P2PS_MST_TIMEOUT_PRESCALER_CFG_0_EXTREF_EN_SHIFT)
#define MISCREG_APE_P2PS_MST_TIMEOUT_PRESCALER_CFG_0_EXTREF_EN_RANGE                    31:31
#define MISCREG_APE_P2PS_MST_TIMEOUT_PRESCALER_CFG_0_EXTREF_EN_WOFFSET                  0x0
#define MISCREG_APE_P2PS_MST_TIMEOUT_PRESCALER_CFG_0_EXTREF_EN_DEFAULT                  _MK_MASK_CONST(0x1)
#define MISCREG_APE_P2PS_MST_TIMEOUT_PRESCALER_CFG_0_EXTREF_EN_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define MISCREG_APE_P2PS_MST_TIMEOUT_PRESCALER_CFG_0_EXTREF_EN_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define MISCREG_APE_P2PS_MST_TIMEOUT_PRESCALER_CFG_0_EXTREF_EN_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define MISCREG_APE_P2PS_MST_TIMEOUT_PRESCALER_CFG_0_EXTREF_EN_PARITY_PROTECTION                        _MK_MASK_CONST(0x1)
#define MISCREG_APE_P2PS_MST_TIMEOUT_PRESCALER_CFG_0_EXTREF_EN_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)
#define MISCREG_APE_P2PS_MST_TIMEOUT_PRESCALER_CFG_0_EXTREF_EN_DISABLE                  _MK_ENUM_CONST(0)
#define MISCREG_APE_P2PS_MST_TIMEOUT_PRESCALER_CFG_0_EXTREF_EN_ENABLE                   _MK_ENUM_CONST(1)

#define MISCREG_APE_P2PS_MST_TIMEOUT_PRESCALER_CFG_0_EXTREF_SRC_SHIFT                   _MK_SHIFT_CONST(0)
#define MISCREG_APE_P2PS_MST_TIMEOUT_PRESCALER_CFG_0_EXTREF_SRC_FIELD                   _MK_FIELD_CONST(0xf, MISCREG_APE_P2PS_MST_TIMEOUT_PRESCALER_CFG_0_EXTREF_SRC_SHIFT)
#define MISCREG_APE_P2PS_MST_TIMEOUT_PRESCALER_CFG_0_EXTREF_SRC_RANGE                   3:0
#define MISCREG_APE_P2PS_MST_TIMEOUT_PRESCALER_CFG_0_EXTREF_SRC_WOFFSET                 0x0
#define MISCREG_APE_P2PS_MST_TIMEOUT_PRESCALER_CFG_0_EXTREF_SRC_DEFAULT                 _MK_MASK_CONST(0xd)
#define MISCREG_APE_P2PS_MST_TIMEOUT_PRESCALER_CFG_0_EXTREF_SRC_DEFAULT_MASK                    _MK_MASK_CONST(0xf)
#define MISCREG_APE_P2PS_MST_TIMEOUT_PRESCALER_CFG_0_EXTREF_SRC_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define MISCREG_APE_P2PS_MST_TIMEOUT_PRESCALER_CFG_0_EXTREF_SRC_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define MISCREG_APE_P2PS_MST_TIMEOUT_PRESCALER_CFG_0_EXTREF_SRC_PARITY_PROTECTION                       _MK_MASK_CONST(0x1)
#define MISCREG_APE_P2PS_MST_TIMEOUT_PRESCALER_CFG_0_EXTREF_SRC_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)


// Register MISCREG_BPMP_P2PS_MST_TIMEOUT_PRESCALER_CFG_0
#define MISCREG_BPMP_P2PS_MST_TIMEOUT_PRESCALER_CFG_0                   _MK_ADDR_CONST(0x1260)
#define MISCREG_BPMP_P2PS_MST_TIMEOUT_PRESCALER_CFG_0_SECURE                    0x0
#define MISCREG_BPMP_P2PS_MST_TIMEOUT_PRESCALER_CFG_0_DUAL                      0x0
#define MISCREG_BPMP_P2PS_MST_TIMEOUT_PRESCALER_CFG_0_SCR                       0
#define MISCREG_BPMP_P2PS_MST_TIMEOUT_PRESCALER_CFG_0_WORD_COUNT                        0x1
#define MISCREG_BPMP_P2PS_MST_TIMEOUT_PRESCALER_CFG_0_RESET_VAL                         _MK_MASK_CONST(0x8000000d)
#define MISCREG_BPMP_P2PS_MST_TIMEOUT_PRESCALER_CFG_0_RESET_MASK                        _MK_MASK_CONST(0x8000000f)
#define MISCREG_BPMP_P2PS_MST_TIMEOUT_PRESCALER_CFG_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define MISCREG_BPMP_P2PS_MST_TIMEOUT_PRESCALER_CFG_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define MISCREG_BPMP_P2PS_MST_TIMEOUT_PRESCALER_CFG_0_READ_MASK                         _MK_MASK_CONST(0x8000000f)
#define MISCREG_BPMP_P2PS_MST_TIMEOUT_PRESCALER_CFG_0_WRITE_MASK                        _MK_MASK_CONST(0x8000000f)
#define MISCREG_BPMP_P2PS_MST_TIMEOUT_PRESCALER_CFG_0_EXTREF_EN_SHIFT                   _MK_SHIFT_CONST(31)
#define MISCREG_BPMP_P2PS_MST_TIMEOUT_PRESCALER_CFG_0_EXTREF_EN_FIELD                   _MK_FIELD_CONST(0x1, MISCREG_BPMP_P2PS_MST_TIMEOUT_PRESCALER_CFG_0_EXTREF_EN_SHIFT)
#define MISCREG_BPMP_P2PS_MST_TIMEOUT_PRESCALER_CFG_0_EXTREF_EN_RANGE                   31:31
#define MISCREG_BPMP_P2PS_MST_TIMEOUT_PRESCALER_CFG_0_EXTREF_EN_WOFFSET                 0x0
#define MISCREG_BPMP_P2PS_MST_TIMEOUT_PRESCALER_CFG_0_EXTREF_EN_DEFAULT                 _MK_MASK_CONST(0x1)
#define MISCREG_BPMP_P2PS_MST_TIMEOUT_PRESCALER_CFG_0_EXTREF_EN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define MISCREG_BPMP_P2PS_MST_TIMEOUT_PRESCALER_CFG_0_EXTREF_EN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define MISCREG_BPMP_P2PS_MST_TIMEOUT_PRESCALER_CFG_0_EXTREF_EN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define MISCREG_BPMP_P2PS_MST_TIMEOUT_PRESCALER_CFG_0_EXTREF_EN_PARITY_PROTECTION                       _MK_MASK_CONST(0x1)
#define MISCREG_BPMP_P2PS_MST_TIMEOUT_PRESCALER_CFG_0_EXTREF_EN_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define MISCREG_BPMP_P2PS_MST_TIMEOUT_PRESCALER_CFG_0_EXTREF_EN_DISABLE                 _MK_ENUM_CONST(0)
#define MISCREG_BPMP_P2PS_MST_TIMEOUT_PRESCALER_CFG_0_EXTREF_EN_ENABLE                  _MK_ENUM_CONST(1)

#define MISCREG_BPMP_P2PS_MST_TIMEOUT_PRESCALER_CFG_0_EXTREF_SRC_SHIFT                  _MK_SHIFT_CONST(0)
#define MISCREG_BPMP_P2PS_MST_TIMEOUT_PRESCALER_CFG_0_EXTREF_SRC_FIELD                  _MK_FIELD_CONST(0xf, MISCREG_BPMP_P2PS_MST_TIMEOUT_PRESCALER_CFG_0_EXTREF_SRC_SHIFT)
#define MISCREG_BPMP_P2PS_MST_TIMEOUT_PRESCALER_CFG_0_EXTREF_SRC_RANGE                  3:0
#define MISCREG_BPMP_P2PS_MST_TIMEOUT_PRESCALER_CFG_0_EXTREF_SRC_WOFFSET                        0x0
#define MISCREG_BPMP_P2PS_MST_TIMEOUT_PRESCALER_CFG_0_EXTREF_SRC_DEFAULT                        _MK_MASK_CONST(0xd)
#define MISCREG_BPMP_P2PS_MST_TIMEOUT_PRESCALER_CFG_0_EXTREF_SRC_DEFAULT_MASK                   _MK_MASK_CONST(0xf)
#define MISCREG_BPMP_P2PS_MST_TIMEOUT_PRESCALER_CFG_0_EXTREF_SRC_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define MISCREG_BPMP_P2PS_MST_TIMEOUT_PRESCALER_CFG_0_EXTREF_SRC_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define MISCREG_BPMP_P2PS_MST_TIMEOUT_PRESCALER_CFG_0_EXTREF_SRC_PARITY_PROTECTION                      _MK_MASK_CONST(0x1)
#define MISCREG_BPMP_P2PS_MST_TIMEOUT_PRESCALER_CFG_0_EXTREF_SRC_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)


// Register MISCREG_CCROC_P2PS_MST_TIMEOUT_PRESCALER_CFG_0
#define MISCREG_CCROC_P2PS_MST_TIMEOUT_PRESCALER_CFG_0                  _MK_ADDR_CONST(0x1264)
#define MISCREG_CCROC_P2PS_MST_TIMEOUT_PRESCALER_CFG_0_SECURE                   0x0
#define MISCREG_CCROC_P2PS_MST_TIMEOUT_PRESCALER_CFG_0_DUAL                     0x0
#define MISCREG_CCROC_P2PS_MST_TIMEOUT_PRESCALER_CFG_0_SCR                      0
#define MISCREG_CCROC_P2PS_MST_TIMEOUT_PRESCALER_CFG_0_WORD_COUNT                       0x1
#define MISCREG_CCROC_P2PS_MST_TIMEOUT_PRESCALER_CFG_0_RESET_VAL                        _MK_MASK_CONST(0x8000000d)
#define MISCREG_CCROC_P2PS_MST_TIMEOUT_PRESCALER_CFG_0_RESET_MASK                       _MK_MASK_CONST(0x8000000f)
#define MISCREG_CCROC_P2PS_MST_TIMEOUT_PRESCALER_CFG_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define MISCREG_CCROC_P2PS_MST_TIMEOUT_PRESCALER_CFG_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define MISCREG_CCROC_P2PS_MST_TIMEOUT_PRESCALER_CFG_0_READ_MASK                        _MK_MASK_CONST(0x8000000f)
#define MISCREG_CCROC_P2PS_MST_TIMEOUT_PRESCALER_CFG_0_WRITE_MASK                       _MK_MASK_CONST(0x8000000f)
#define MISCREG_CCROC_P2PS_MST_TIMEOUT_PRESCALER_CFG_0_EXTREF_EN_SHIFT                  _MK_SHIFT_CONST(31)
#define MISCREG_CCROC_P2PS_MST_TIMEOUT_PRESCALER_CFG_0_EXTREF_EN_FIELD                  _MK_FIELD_CONST(0x1, MISCREG_CCROC_P2PS_MST_TIMEOUT_PRESCALER_CFG_0_EXTREF_EN_SHIFT)
#define MISCREG_CCROC_P2PS_MST_TIMEOUT_PRESCALER_CFG_0_EXTREF_EN_RANGE                  31:31
#define MISCREG_CCROC_P2PS_MST_TIMEOUT_PRESCALER_CFG_0_EXTREF_EN_WOFFSET                        0x0
#define MISCREG_CCROC_P2PS_MST_TIMEOUT_PRESCALER_CFG_0_EXTREF_EN_DEFAULT                        _MK_MASK_CONST(0x1)
#define MISCREG_CCROC_P2PS_MST_TIMEOUT_PRESCALER_CFG_0_EXTREF_EN_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define MISCREG_CCROC_P2PS_MST_TIMEOUT_PRESCALER_CFG_0_EXTREF_EN_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define MISCREG_CCROC_P2PS_MST_TIMEOUT_PRESCALER_CFG_0_EXTREF_EN_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define MISCREG_CCROC_P2PS_MST_TIMEOUT_PRESCALER_CFG_0_EXTREF_EN_PARITY_PROTECTION                      _MK_MASK_CONST(0x1)
#define MISCREG_CCROC_P2PS_MST_TIMEOUT_PRESCALER_CFG_0_EXTREF_EN_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define MISCREG_CCROC_P2PS_MST_TIMEOUT_PRESCALER_CFG_0_EXTREF_EN_DISABLE                        _MK_ENUM_CONST(0)
#define MISCREG_CCROC_P2PS_MST_TIMEOUT_PRESCALER_CFG_0_EXTREF_EN_ENABLE                 _MK_ENUM_CONST(1)

#define MISCREG_CCROC_P2PS_MST_TIMEOUT_PRESCALER_CFG_0_EXTREF_SRC_SHIFT                 _MK_SHIFT_CONST(0)
#define MISCREG_CCROC_P2PS_MST_TIMEOUT_PRESCALER_CFG_0_EXTREF_SRC_FIELD                 _MK_FIELD_CONST(0xf, MISCREG_CCROC_P2PS_MST_TIMEOUT_PRESCALER_CFG_0_EXTREF_SRC_SHIFT)
#define MISCREG_CCROC_P2PS_MST_TIMEOUT_PRESCALER_CFG_0_EXTREF_SRC_RANGE                 3:0
#define MISCREG_CCROC_P2PS_MST_TIMEOUT_PRESCALER_CFG_0_EXTREF_SRC_WOFFSET                       0x0
#define MISCREG_CCROC_P2PS_MST_TIMEOUT_PRESCALER_CFG_0_EXTREF_SRC_DEFAULT                       _MK_MASK_CONST(0xd)
#define MISCREG_CCROC_P2PS_MST_TIMEOUT_PRESCALER_CFG_0_EXTREF_SRC_DEFAULT_MASK                  _MK_MASK_CONST(0xf)
#define MISCREG_CCROC_P2PS_MST_TIMEOUT_PRESCALER_CFG_0_EXTREF_SRC_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define MISCREG_CCROC_P2PS_MST_TIMEOUT_PRESCALER_CFG_0_EXTREF_SRC_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define MISCREG_CCROC_P2PS_MST_TIMEOUT_PRESCALER_CFG_0_EXTREF_SRC_PARITY_PROTECTION                     _MK_MASK_CONST(0x1)
#define MISCREG_CCROC_P2PS_MST_TIMEOUT_PRESCALER_CFG_0_EXTREF_SRC_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)


// Register MISCREG_CSITE_P2PS_MST_TIMEOUT_PRESCALER_CFG_0
#define MISCREG_CSITE_P2PS_MST_TIMEOUT_PRESCALER_CFG_0                  _MK_ADDR_CONST(0x1268)
#define MISCREG_CSITE_P2PS_MST_TIMEOUT_PRESCALER_CFG_0_SECURE                   0x0
#define MISCREG_CSITE_P2PS_MST_TIMEOUT_PRESCALER_CFG_0_DUAL                     0x0
#define MISCREG_CSITE_P2PS_MST_TIMEOUT_PRESCALER_CFG_0_SCR                      0
#define MISCREG_CSITE_P2PS_MST_TIMEOUT_PRESCALER_CFG_0_WORD_COUNT                       0x1
#define MISCREG_CSITE_P2PS_MST_TIMEOUT_PRESCALER_CFG_0_RESET_VAL                        _MK_MASK_CONST(0x8000000d)
#define MISCREG_CSITE_P2PS_MST_TIMEOUT_PRESCALER_CFG_0_RESET_MASK                       _MK_MASK_CONST(0x8000000f)
#define MISCREG_CSITE_P2PS_MST_TIMEOUT_PRESCALER_CFG_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define MISCREG_CSITE_P2PS_MST_TIMEOUT_PRESCALER_CFG_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define MISCREG_CSITE_P2PS_MST_TIMEOUT_PRESCALER_CFG_0_READ_MASK                        _MK_MASK_CONST(0x8000000f)
#define MISCREG_CSITE_P2PS_MST_TIMEOUT_PRESCALER_CFG_0_WRITE_MASK                       _MK_MASK_CONST(0x8000000f)
#define MISCREG_CSITE_P2PS_MST_TIMEOUT_PRESCALER_CFG_0_EXTREF_EN_SHIFT                  _MK_SHIFT_CONST(31)
#define MISCREG_CSITE_P2PS_MST_TIMEOUT_PRESCALER_CFG_0_EXTREF_EN_FIELD                  _MK_FIELD_CONST(0x1, MISCREG_CSITE_P2PS_MST_TIMEOUT_PRESCALER_CFG_0_EXTREF_EN_SHIFT)
#define MISCREG_CSITE_P2PS_MST_TIMEOUT_PRESCALER_CFG_0_EXTREF_EN_RANGE                  31:31
#define MISCREG_CSITE_P2PS_MST_TIMEOUT_PRESCALER_CFG_0_EXTREF_EN_WOFFSET                        0x0
#define MISCREG_CSITE_P2PS_MST_TIMEOUT_PRESCALER_CFG_0_EXTREF_EN_DEFAULT                        _MK_MASK_CONST(0x1)
#define MISCREG_CSITE_P2PS_MST_TIMEOUT_PRESCALER_CFG_0_EXTREF_EN_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define MISCREG_CSITE_P2PS_MST_TIMEOUT_PRESCALER_CFG_0_EXTREF_EN_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define MISCREG_CSITE_P2PS_MST_TIMEOUT_PRESCALER_CFG_0_EXTREF_EN_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define MISCREG_CSITE_P2PS_MST_TIMEOUT_PRESCALER_CFG_0_EXTREF_EN_PARITY_PROTECTION                      _MK_MASK_CONST(0x1)
#define MISCREG_CSITE_P2PS_MST_TIMEOUT_PRESCALER_CFG_0_EXTREF_EN_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define MISCREG_CSITE_P2PS_MST_TIMEOUT_PRESCALER_CFG_0_EXTREF_EN_DISABLE                        _MK_ENUM_CONST(0)
#define MISCREG_CSITE_P2PS_MST_TIMEOUT_PRESCALER_CFG_0_EXTREF_EN_ENABLE                 _MK_ENUM_CONST(1)

#define MISCREG_CSITE_P2PS_MST_TIMEOUT_PRESCALER_CFG_0_EXTREF_SRC_SHIFT                 _MK_SHIFT_CONST(0)
#define MISCREG_CSITE_P2PS_MST_TIMEOUT_PRESCALER_CFG_0_EXTREF_SRC_FIELD                 _MK_FIELD_CONST(0xf, MISCREG_CSITE_P2PS_MST_TIMEOUT_PRESCALER_CFG_0_EXTREF_SRC_SHIFT)
#define MISCREG_CSITE_P2PS_MST_TIMEOUT_PRESCALER_CFG_0_EXTREF_SRC_RANGE                 3:0
#define MISCREG_CSITE_P2PS_MST_TIMEOUT_PRESCALER_CFG_0_EXTREF_SRC_WOFFSET                       0x0
#define MISCREG_CSITE_P2PS_MST_TIMEOUT_PRESCALER_CFG_0_EXTREF_SRC_DEFAULT                       _MK_MASK_CONST(0xd)
#define MISCREG_CSITE_P2PS_MST_TIMEOUT_PRESCALER_CFG_0_EXTREF_SRC_DEFAULT_MASK                  _MK_MASK_CONST(0xf)
#define MISCREG_CSITE_P2PS_MST_TIMEOUT_PRESCALER_CFG_0_EXTREF_SRC_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define MISCREG_CSITE_P2PS_MST_TIMEOUT_PRESCALER_CFG_0_EXTREF_SRC_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define MISCREG_CSITE_P2PS_MST_TIMEOUT_PRESCALER_CFG_0_EXTREF_SRC_PARITY_PROTECTION                     _MK_MASK_CONST(0x1)
#define MISCREG_CSITE_P2PS_MST_TIMEOUT_PRESCALER_CFG_0_EXTREF_SRC_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)


// Register MISCREG_GPCDMA_MMIO_P2PS_MST_TIMEOUT_PRESCALER_CFG_0
#define MISCREG_GPCDMA_MMIO_P2PS_MST_TIMEOUT_PRESCALER_CFG_0                    _MK_ADDR_CONST(0x126c)
#define MISCREG_GPCDMA_MMIO_P2PS_MST_TIMEOUT_PRESCALER_CFG_0_SECURE                     0x0
#define MISCREG_GPCDMA_MMIO_P2PS_MST_TIMEOUT_PRESCALER_CFG_0_DUAL                       0x0
#define MISCREG_GPCDMA_MMIO_P2PS_MST_TIMEOUT_PRESCALER_CFG_0_SCR                        0
#define MISCREG_GPCDMA_MMIO_P2PS_MST_TIMEOUT_PRESCALER_CFG_0_WORD_COUNT                         0x1
#define MISCREG_GPCDMA_MMIO_P2PS_MST_TIMEOUT_PRESCALER_CFG_0_RESET_VAL                  _MK_MASK_CONST(0x8000000d)
#define MISCREG_GPCDMA_MMIO_P2PS_MST_TIMEOUT_PRESCALER_CFG_0_RESET_MASK                         _MK_MASK_CONST(0x8000000f)
#define MISCREG_GPCDMA_MMIO_P2PS_MST_TIMEOUT_PRESCALER_CFG_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define MISCREG_GPCDMA_MMIO_P2PS_MST_TIMEOUT_PRESCALER_CFG_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define MISCREG_GPCDMA_MMIO_P2PS_MST_TIMEOUT_PRESCALER_CFG_0_READ_MASK                  _MK_MASK_CONST(0x8000000f)
#define MISCREG_GPCDMA_MMIO_P2PS_MST_TIMEOUT_PRESCALER_CFG_0_WRITE_MASK                         _MK_MASK_CONST(0x8000000f)
#define MISCREG_GPCDMA_MMIO_P2PS_MST_TIMEOUT_PRESCALER_CFG_0_EXTREF_EN_SHIFT                    _MK_SHIFT_CONST(31)
#define MISCREG_GPCDMA_MMIO_P2PS_MST_TIMEOUT_PRESCALER_CFG_0_EXTREF_EN_FIELD                    _MK_FIELD_CONST(0x1, MISCREG_GPCDMA_MMIO_P2PS_MST_TIMEOUT_PRESCALER_CFG_0_EXTREF_EN_SHIFT)
#define MISCREG_GPCDMA_MMIO_P2PS_MST_TIMEOUT_PRESCALER_CFG_0_EXTREF_EN_RANGE                    31:31
#define MISCREG_GPCDMA_MMIO_P2PS_MST_TIMEOUT_PRESCALER_CFG_0_EXTREF_EN_WOFFSET                  0x0
#define MISCREG_GPCDMA_MMIO_P2PS_MST_TIMEOUT_PRESCALER_CFG_0_EXTREF_EN_DEFAULT                  _MK_MASK_CONST(0x1)
#define MISCREG_GPCDMA_MMIO_P2PS_MST_TIMEOUT_PRESCALER_CFG_0_EXTREF_EN_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define MISCREG_GPCDMA_MMIO_P2PS_MST_TIMEOUT_PRESCALER_CFG_0_EXTREF_EN_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define MISCREG_GPCDMA_MMIO_P2PS_MST_TIMEOUT_PRESCALER_CFG_0_EXTREF_EN_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define MISCREG_GPCDMA_MMIO_P2PS_MST_TIMEOUT_PRESCALER_CFG_0_EXTREF_EN_PARITY_PROTECTION                        _MK_MASK_CONST(0x1)
#define MISCREG_GPCDMA_MMIO_P2PS_MST_TIMEOUT_PRESCALER_CFG_0_EXTREF_EN_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)
#define MISCREG_GPCDMA_MMIO_P2PS_MST_TIMEOUT_PRESCALER_CFG_0_EXTREF_EN_DISABLE                  _MK_ENUM_CONST(0)
#define MISCREG_GPCDMA_MMIO_P2PS_MST_TIMEOUT_PRESCALER_CFG_0_EXTREF_EN_ENABLE                   _MK_ENUM_CONST(1)

#define MISCREG_GPCDMA_MMIO_P2PS_MST_TIMEOUT_PRESCALER_CFG_0_EXTREF_SRC_SHIFT                   _MK_SHIFT_CONST(0)
#define MISCREG_GPCDMA_MMIO_P2PS_MST_TIMEOUT_PRESCALER_CFG_0_EXTREF_SRC_FIELD                   _MK_FIELD_CONST(0xf, MISCREG_GPCDMA_MMIO_P2PS_MST_TIMEOUT_PRESCALER_CFG_0_EXTREF_SRC_SHIFT)
#define MISCREG_GPCDMA_MMIO_P2PS_MST_TIMEOUT_PRESCALER_CFG_0_EXTREF_SRC_RANGE                   3:0
#define MISCREG_GPCDMA_MMIO_P2PS_MST_TIMEOUT_PRESCALER_CFG_0_EXTREF_SRC_WOFFSET                 0x0
#define MISCREG_GPCDMA_MMIO_P2PS_MST_TIMEOUT_PRESCALER_CFG_0_EXTREF_SRC_DEFAULT                 _MK_MASK_CONST(0xd)
#define MISCREG_GPCDMA_MMIO_P2PS_MST_TIMEOUT_PRESCALER_CFG_0_EXTREF_SRC_DEFAULT_MASK                    _MK_MASK_CONST(0xf)
#define MISCREG_GPCDMA_MMIO_P2PS_MST_TIMEOUT_PRESCALER_CFG_0_EXTREF_SRC_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define MISCREG_GPCDMA_MMIO_P2PS_MST_TIMEOUT_PRESCALER_CFG_0_EXTREF_SRC_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define MISCREG_GPCDMA_MMIO_P2PS_MST_TIMEOUT_PRESCALER_CFG_0_EXTREF_SRC_PARITY_PROTECTION                       _MK_MASK_CONST(0x1)
#define MISCREG_GPCDMA_MMIO_P2PS_MST_TIMEOUT_PRESCALER_CFG_0_EXTREF_SRC_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)


// Register MISCREG_JTAG_P2PS_MST_TIMEOUT_PRESCALER_CFG_0
#define MISCREG_JTAG_P2PS_MST_TIMEOUT_PRESCALER_CFG_0                   _MK_ADDR_CONST(0x1270)
#define MISCREG_JTAG_P2PS_MST_TIMEOUT_PRESCALER_CFG_0_SECURE                    0x0
#define MISCREG_JTAG_P2PS_MST_TIMEOUT_PRESCALER_CFG_0_DUAL                      0x0
#define MISCREG_JTAG_P2PS_MST_TIMEOUT_PRESCALER_CFG_0_SCR                       0
#define MISCREG_JTAG_P2PS_MST_TIMEOUT_PRESCALER_CFG_0_WORD_COUNT                        0x1
#define MISCREG_JTAG_P2PS_MST_TIMEOUT_PRESCALER_CFG_0_RESET_VAL                         _MK_MASK_CONST(0x8000000d)
#define MISCREG_JTAG_P2PS_MST_TIMEOUT_PRESCALER_CFG_0_RESET_MASK                        _MK_MASK_CONST(0x8000000f)
#define MISCREG_JTAG_P2PS_MST_TIMEOUT_PRESCALER_CFG_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define MISCREG_JTAG_P2PS_MST_TIMEOUT_PRESCALER_CFG_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define MISCREG_JTAG_P2PS_MST_TIMEOUT_PRESCALER_CFG_0_READ_MASK                         _MK_MASK_CONST(0x8000000f)
#define MISCREG_JTAG_P2PS_MST_TIMEOUT_PRESCALER_CFG_0_WRITE_MASK                        _MK_MASK_CONST(0x8000000f)
#define MISCREG_JTAG_P2PS_MST_TIMEOUT_PRESCALER_CFG_0_EXTREF_EN_SHIFT                   _MK_SHIFT_CONST(31)
#define MISCREG_JTAG_P2PS_MST_TIMEOUT_PRESCALER_CFG_0_EXTREF_EN_FIELD                   _MK_FIELD_CONST(0x1, MISCREG_JTAG_P2PS_MST_TIMEOUT_PRESCALER_CFG_0_EXTREF_EN_SHIFT)
#define MISCREG_JTAG_P2PS_MST_TIMEOUT_PRESCALER_CFG_0_EXTREF_EN_RANGE                   31:31
#define MISCREG_JTAG_P2PS_MST_TIMEOUT_PRESCALER_CFG_0_EXTREF_EN_WOFFSET                 0x0
#define MISCREG_JTAG_P2PS_MST_TIMEOUT_PRESCALER_CFG_0_EXTREF_EN_DEFAULT                 _MK_MASK_CONST(0x1)
#define MISCREG_JTAG_P2PS_MST_TIMEOUT_PRESCALER_CFG_0_EXTREF_EN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define MISCREG_JTAG_P2PS_MST_TIMEOUT_PRESCALER_CFG_0_EXTREF_EN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define MISCREG_JTAG_P2PS_MST_TIMEOUT_PRESCALER_CFG_0_EXTREF_EN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define MISCREG_JTAG_P2PS_MST_TIMEOUT_PRESCALER_CFG_0_EXTREF_EN_PARITY_PROTECTION                       _MK_MASK_CONST(0x1)
#define MISCREG_JTAG_P2PS_MST_TIMEOUT_PRESCALER_CFG_0_EXTREF_EN_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define MISCREG_JTAG_P2PS_MST_TIMEOUT_PRESCALER_CFG_0_EXTREF_EN_DISABLE                 _MK_ENUM_CONST(0)
#define MISCREG_JTAG_P2PS_MST_TIMEOUT_PRESCALER_CFG_0_EXTREF_EN_ENABLE                  _MK_ENUM_CONST(1)

#define MISCREG_JTAG_P2PS_MST_TIMEOUT_PRESCALER_CFG_0_EXTREF_SRC_SHIFT                  _MK_SHIFT_CONST(0)
#define MISCREG_JTAG_P2PS_MST_TIMEOUT_PRESCALER_CFG_0_EXTREF_SRC_FIELD                  _MK_FIELD_CONST(0xf, MISCREG_JTAG_P2PS_MST_TIMEOUT_PRESCALER_CFG_0_EXTREF_SRC_SHIFT)
#define MISCREG_JTAG_P2PS_MST_TIMEOUT_PRESCALER_CFG_0_EXTREF_SRC_RANGE                  3:0
#define MISCREG_JTAG_P2PS_MST_TIMEOUT_PRESCALER_CFG_0_EXTREF_SRC_WOFFSET                        0x0
#define MISCREG_JTAG_P2PS_MST_TIMEOUT_PRESCALER_CFG_0_EXTREF_SRC_DEFAULT                        _MK_MASK_CONST(0xd)
#define MISCREG_JTAG_P2PS_MST_TIMEOUT_PRESCALER_CFG_0_EXTREF_SRC_DEFAULT_MASK                   _MK_MASK_CONST(0xf)
#define MISCREG_JTAG_P2PS_MST_TIMEOUT_PRESCALER_CFG_0_EXTREF_SRC_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define MISCREG_JTAG_P2PS_MST_TIMEOUT_PRESCALER_CFG_0_EXTREF_SRC_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define MISCREG_JTAG_P2PS_MST_TIMEOUT_PRESCALER_CFG_0_EXTREF_SRC_PARITY_PROTECTION                      _MK_MASK_CONST(0x1)
#define MISCREG_JTAG_P2PS_MST_TIMEOUT_PRESCALER_CFG_0_EXTREF_SRC_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)


// Register MISCREG_NVDEC_P2PS_MST_TIMEOUT_PRESCALER_CFG_0
#define MISCREG_NVDEC_P2PS_MST_TIMEOUT_PRESCALER_CFG_0                  _MK_ADDR_CONST(0x1274)
#define MISCREG_NVDEC_P2PS_MST_TIMEOUT_PRESCALER_CFG_0_SECURE                   0x0
#define MISCREG_NVDEC_P2PS_MST_TIMEOUT_PRESCALER_CFG_0_DUAL                     0x0
#define MISCREG_NVDEC_P2PS_MST_TIMEOUT_PRESCALER_CFG_0_SCR                      0
#define MISCREG_NVDEC_P2PS_MST_TIMEOUT_PRESCALER_CFG_0_WORD_COUNT                       0x1
#define MISCREG_NVDEC_P2PS_MST_TIMEOUT_PRESCALER_CFG_0_RESET_VAL                        _MK_MASK_CONST(0x8000000d)
#define MISCREG_NVDEC_P2PS_MST_TIMEOUT_PRESCALER_CFG_0_RESET_MASK                       _MK_MASK_CONST(0x8000000f)
#define MISCREG_NVDEC_P2PS_MST_TIMEOUT_PRESCALER_CFG_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define MISCREG_NVDEC_P2PS_MST_TIMEOUT_PRESCALER_CFG_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define MISCREG_NVDEC_P2PS_MST_TIMEOUT_PRESCALER_CFG_0_READ_MASK                        _MK_MASK_CONST(0x8000000f)
#define MISCREG_NVDEC_P2PS_MST_TIMEOUT_PRESCALER_CFG_0_WRITE_MASK                       _MK_MASK_CONST(0x8000000f)
#define MISCREG_NVDEC_P2PS_MST_TIMEOUT_PRESCALER_CFG_0_EXTREF_EN_SHIFT                  _MK_SHIFT_CONST(31)
#define MISCREG_NVDEC_P2PS_MST_TIMEOUT_PRESCALER_CFG_0_EXTREF_EN_FIELD                  _MK_FIELD_CONST(0x1, MISCREG_NVDEC_P2PS_MST_TIMEOUT_PRESCALER_CFG_0_EXTREF_EN_SHIFT)
#define MISCREG_NVDEC_P2PS_MST_TIMEOUT_PRESCALER_CFG_0_EXTREF_EN_RANGE                  31:31
#define MISCREG_NVDEC_P2PS_MST_TIMEOUT_PRESCALER_CFG_0_EXTREF_EN_WOFFSET                        0x0
#define MISCREG_NVDEC_P2PS_MST_TIMEOUT_PRESCALER_CFG_0_EXTREF_EN_DEFAULT                        _MK_MASK_CONST(0x1)
#define MISCREG_NVDEC_P2PS_MST_TIMEOUT_PRESCALER_CFG_0_EXTREF_EN_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define MISCREG_NVDEC_P2PS_MST_TIMEOUT_PRESCALER_CFG_0_EXTREF_EN_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define MISCREG_NVDEC_P2PS_MST_TIMEOUT_PRESCALER_CFG_0_EXTREF_EN_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define MISCREG_NVDEC_P2PS_MST_TIMEOUT_PRESCALER_CFG_0_EXTREF_EN_PARITY_PROTECTION                      _MK_MASK_CONST(0x1)
#define MISCREG_NVDEC_P2PS_MST_TIMEOUT_PRESCALER_CFG_0_EXTREF_EN_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define MISCREG_NVDEC_P2PS_MST_TIMEOUT_PRESCALER_CFG_0_EXTREF_EN_DISABLE                        _MK_ENUM_CONST(0)
#define MISCREG_NVDEC_P2PS_MST_TIMEOUT_PRESCALER_CFG_0_EXTREF_EN_ENABLE                 _MK_ENUM_CONST(1)

#define MISCREG_NVDEC_P2PS_MST_TIMEOUT_PRESCALER_CFG_0_EXTREF_SRC_SHIFT                 _MK_SHIFT_CONST(0)
#define MISCREG_NVDEC_P2PS_MST_TIMEOUT_PRESCALER_CFG_0_EXTREF_SRC_FIELD                 _MK_FIELD_CONST(0xf, MISCREG_NVDEC_P2PS_MST_TIMEOUT_PRESCALER_CFG_0_EXTREF_SRC_SHIFT)
#define MISCREG_NVDEC_P2PS_MST_TIMEOUT_PRESCALER_CFG_0_EXTREF_SRC_RANGE                 3:0
#define MISCREG_NVDEC_P2PS_MST_TIMEOUT_PRESCALER_CFG_0_EXTREF_SRC_WOFFSET                       0x0
#define MISCREG_NVDEC_P2PS_MST_TIMEOUT_PRESCALER_CFG_0_EXTREF_SRC_DEFAULT                       _MK_MASK_CONST(0xd)
#define MISCREG_NVDEC_P2PS_MST_TIMEOUT_PRESCALER_CFG_0_EXTREF_SRC_DEFAULT_MASK                  _MK_MASK_CONST(0xf)
#define MISCREG_NVDEC_P2PS_MST_TIMEOUT_PRESCALER_CFG_0_EXTREF_SRC_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define MISCREG_NVDEC_P2PS_MST_TIMEOUT_PRESCALER_CFG_0_EXTREF_SRC_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define MISCREG_NVDEC_P2PS_MST_TIMEOUT_PRESCALER_CFG_0_EXTREF_SRC_PARITY_PROTECTION                     _MK_MASK_CONST(0x1)
#define MISCREG_NVDEC_P2PS_MST_TIMEOUT_PRESCALER_CFG_0_EXTREF_SRC_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)


// Register MISCREG_NVDEC1_P2PS_MST_TIMEOUT_PRESCALER_CFG_0
#define MISCREG_NVDEC1_P2PS_MST_TIMEOUT_PRESCALER_CFG_0                 _MK_ADDR_CONST(0x1278)
#define MISCREG_NVDEC1_P2PS_MST_TIMEOUT_PRESCALER_CFG_0_SECURE                  0x0
#define MISCREG_NVDEC1_P2PS_MST_TIMEOUT_PRESCALER_CFG_0_DUAL                    0x0
#define MISCREG_NVDEC1_P2PS_MST_TIMEOUT_PRESCALER_CFG_0_SCR                     0
#define MISCREG_NVDEC1_P2PS_MST_TIMEOUT_PRESCALER_CFG_0_WORD_COUNT                      0x1
#define MISCREG_NVDEC1_P2PS_MST_TIMEOUT_PRESCALER_CFG_0_RESET_VAL                       _MK_MASK_CONST(0x8000000d)
#define MISCREG_NVDEC1_P2PS_MST_TIMEOUT_PRESCALER_CFG_0_RESET_MASK                      _MK_MASK_CONST(0x8000000f)
#define MISCREG_NVDEC1_P2PS_MST_TIMEOUT_PRESCALER_CFG_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define MISCREG_NVDEC1_P2PS_MST_TIMEOUT_PRESCALER_CFG_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define MISCREG_NVDEC1_P2PS_MST_TIMEOUT_PRESCALER_CFG_0_READ_MASK                       _MK_MASK_CONST(0x8000000f)
#define MISCREG_NVDEC1_P2PS_MST_TIMEOUT_PRESCALER_CFG_0_WRITE_MASK                      _MK_MASK_CONST(0x8000000f)
#define MISCREG_NVDEC1_P2PS_MST_TIMEOUT_PRESCALER_CFG_0_EXTREF_EN_SHIFT                 _MK_SHIFT_CONST(31)
#define MISCREG_NVDEC1_P2PS_MST_TIMEOUT_PRESCALER_CFG_0_EXTREF_EN_FIELD                 _MK_FIELD_CONST(0x1, MISCREG_NVDEC1_P2PS_MST_TIMEOUT_PRESCALER_CFG_0_EXTREF_EN_SHIFT)
#define MISCREG_NVDEC1_P2PS_MST_TIMEOUT_PRESCALER_CFG_0_EXTREF_EN_RANGE                 31:31
#define MISCREG_NVDEC1_P2PS_MST_TIMEOUT_PRESCALER_CFG_0_EXTREF_EN_WOFFSET                       0x0
#define MISCREG_NVDEC1_P2PS_MST_TIMEOUT_PRESCALER_CFG_0_EXTREF_EN_DEFAULT                       _MK_MASK_CONST(0x1)
#define MISCREG_NVDEC1_P2PS_MST_TIMEOUT_PRESCALER_CFG_0_EXTREF_EN_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define MISCREG_NVDEC1_P2PS_MST_TIMEOUT_PRESCALER_CFG_0_EXTREF_EN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define MISCREG_NVDEC1_P2PS_MST_TIMEOUT_PRESCALER_CFG_0_EXTREF_EN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define MISCREG_NVDEC1_P2PS_MST_TIMEOUT_PRESCALER_CFG_0_EXTREF_EN_PARITY_PROTECTION                     _MK_MASK_CONST(0x1)
#define MISCREG_NVDEC1_P2PS_MST_TIMEOUT_PRESCALER_CFG_0_EXTREF_EN_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)
#define MISCREG_NVDEC1_P2PS_MST_TIMEOUT_PRESCALER_CFG_0_EXTREF_EN_DISABLE                       _MK_ENUM_CONST(0)
#define MISCREG_NVDEC1_P2PS_MST_TIMEOUT_PRESCALER_CFG_0_EXTREF_EN_ENABLE                        _MK_ENUM_CONST(1)

#define MISCREG_NVDEC1_P2PS_MST_TIMEOUT_PRESCALER_CFG_0_EXTREF_SRC_SHIFT                        _MK_SHIFT_CONST(0)
#define MISCREG_NVDEC1_P2PS_MST_TIMEOUT_PRESCALER_CFG_0_EXTREF_SRC_FIELD                        _MK_FIELD_CONST(0xf, MISCREG_NVDEC1_P2PS_MST_TIMEOUT_PRESCALER_CFG_0_EXTREF_SRC_SHIFT)
#define MISCREG_NVDEC1_P2PS_MST_TIMEOUT_PRESCALER_CFG_0_EXTREF_SRC_RANGE                        3:0
#define MISCREG_NVDEC1_P2PS_MST_TIMEOUT_PRESCALER_CFG_0_EXTREF_SRC_WOFFSET                      0x0
#define MISCREG_NVDEC1_P2PS_MST_TIMEOUT_PRESCALER_CFG_0_EXTREF_SRC_DEFAULT                      _MK_MASK_CONST(0xd)
#define MISCREG_NVDEC1_P2PS_MST_TIMEOUT_PRESCALER_CFG_0_EXTREF_SRC_DEFAULT_MASK                 _MK_MASK_CONST(0xf)
#define MISCREG_NVDEC1_P2PS_MST_TIMEOUT_PRESCALER_CFG_0_EXTREF_SRC_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define MISCREG_NVDEC1_P2PS_MST_TIMEOUT_PRESCALER_CFG_0_EXTREF_SRC_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define MISCREG_NVDEC1_P2PS_MST_TIMEOUT_PRESCALER_CFG_0_EXTREF_SRC_PARITY_PROTECTION                    _MK_MASK_CONST(0x1)
#define MISCREG_NVDEC1_P2PS_MST_TIMEOUT_PRESCALER_CFG_0_EXTREF_SRC_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)


// Register MISCREG_RCE_P2PS_MST_TIMEOUT_PRESCALER_CFG_0
#define MISCREG_RCE_P2PS_MST_TIMEOUT_PRESCALER_CFG_0                    _MK_ADDR_CONST(0x127c)
#define MISCREG_RCE_P2PS_MST_TIMEOUT_PRESCALER_CFG_0_SECURE                     0x0
#define MISCREG_RCE_P2PS_MST_TIMEOUT_PRESCALER_CFG_0_DUAL                       0x0
#define MISCREG_RCE_P2PS_MST_TIMEOUT_PRESCALER_CFG_0_SCR                        0
#define MISCREG_RCE_P2PS_MST_TIMEOUT_PRESCALER_CFG_0_WORD_COUNT                         0x1
#define MISCREG_RCE_P2PS_MST_TIMEOUT_PRESCALER_CFG_0_RESET_VAL                  _MK_MASK_CONST(0x8000000d)
#define MISCREG_RCE_P2PS_MST_TIMEOUT_PRESCALER_CFG_0_RESET_MASK                         _MK_MASK_CONST(0x8000000f)
#define MISCREG_RCE_P2PS_MST_TIMEOUT_PRESCALER_CFG_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define MISCREG_RCE_P2PS_MST_TIMEOUT_PRESCALER_CFG_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define MISCREG_RCE_P2PS_MST_TIMEOUT_PRESCALER_CFG_0_READ_MASK                  _MK_MASK_CONST(0x8000000f)
#define MISCREG_RCE_P2PS_MST_TIMEOUT_PRESCALER_CFG_0_WRITE_MASK                         _MK_MASK_CONST(0x8000000f)
#define MISCREG_RCE_P2PS_MST_TIMEOUT_PRESCALER_CFG_0_EXTREF_EN_SHIFT                    _MK_SHIFT_CONST(31)
#define MISCREG_RCE_P2PS_MST_TIMEOUT_PRESCALER_CFG_0_EXTREF_EN_FIELD                    _MK_FIELD_CONST(0x1, MISCREG_RCE_P2PS_MST_TIMEOUT_PRESCALER_CFG_0_EXTREF_EN_SHIFT)
#define MISCREG_RCE_P2PS_MST_TIMEOUT_PRESCALER_CFG_0_EXTREF_EN_RANGE                    31:31
#define MISCREG_RCE_P2PS_MST_TIMEOUT_PRESCALER_CFG_0_EXTREF_EN_WOFFSET                  0x0
#define MISCREG_RCE_P2PS_MST_TIMEOUT_PRESCALER_CFG_0_EXTREF_EN_DEFAULT                  _MK_MASK_CONST(0x1)
#define MISCREG_RCE_P2PS_MST_TIMEOUT_PRESCALER_CFG_0_EXTREF_EN_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define MISCREG_RCE_P2PS_MST_TIMEOUT_PRESCALER_CFG_0_EXTREF_EN_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define MISCREG_RCE_P2PS_MST_TIMEOUT_PRESCALER_CFG_0_EXTREF_EN_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define MISCREG_RCE_P2PS_MST_TIMEOUT_PRESCALER_CFG_0_EXTREF_EN_PARITY_PROTECTION                        _MK_MASK_CONST(0x1)
#define MISCREG_RCE_P2PS_MST_TIMEOUT_PRESCALER_CFG_0_EXTREF_EN_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)
#define MISCREG_RCE_P2PS_MST_TIMEOUT_PRESCALER_CFG_0_EXTREF_EN_DISABLE                  _MK_ENUM_CONST(0)
#define MISCREG_RCE_P2PS_MST_TIMEOUT_PRESCALER_CFG_0_EXTREF_EN_ENABLE                   _MK_ENUM_CONST(1)

#define MISCREG_RCE_P2PS_MST_TIMEOUT_PRESCALER_CFG_0_EXTREF_SRC_SHIFT                   _MK_SHIFT_CONST(0)
#define MISCREG_RCE_P2PS_MST_TIMEOUT_PRESCALER_CFG_0_EXTREF_SRC_FIELD                   _MK_FIELD_CONST(0xf, MISCREG_RCE_P2PS_MST_TIMEOUT_PRESCALER_CFG_0_EXTREF_SRC_SHIFT)
#define MISCREG_RCE_P2PS_MST_TIMEOUT_PRESCALER_CFG_0_EXTREF_SRC_RANGE                   3:0
#define MISCREG_RCE_P2PS_MST_TIMEOUT_PRESCALER_CFG_0_EXTREF_SRC_WOFFSET                 0x0
#define MISCREG_RCE_P2PS_MST_TIMEOUT_PRESCALER_CFG_0_EXTREF_SRC_DEFAULT                 _MK_MASK_CONST(0xd)
#define MISCREG_RCE_P2PS_MST_TIMEOUT_PRESCALER_CFG_0_EXTREF_SRC_DEFAULT_MASK                    _MK_MASK_CONST(0xf)
#define MISCREG_RCE_P2PS_MST_TIMEOUT_PRESCALER_CFG_0_EXTREF_SRC_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define MISCREG_RCE_P2PS_MST_TIMEOUT_PRESCALER_CFG_0_EXTREF_SRC_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define MISCREG_RCE_P2PS_MST_TIMEOUT_PRESCALER_CFG_0_EXTREF_SRC_PARITY_PROTECTION                       _MK_MASK_CONST(0x1)
#define MISCREG_RCE_P2PS_MST_TIMEOUT_PRESCALER_CFG_0_EXTREF_SRC_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)


// Register MISCREG_SCE_P2PS_MST_TIMEOUT_PRESCALER_CFG_0
#define MISCREG_SCE_P2PS_MST_TIMEOUT_PRESCALER_CFG_0                    _MK_ADDR_CONST(0x1280)
#define MISCREG_SCE_P2PS_MST_TIMEOUT_PRESCALER_CFG_0_SECURE                     0x0
#define MISCREG_SCE_P2PS_MST_TIMEOUT_PRESCALER_CFG_0_DUAL                       0x0
#define MISCREG_SCE_P2PS_MST_TIMEOUT_PRESCALER_CFG_0_SCR                        0
#define MISCREG_SCE_P2PS_MST_TIMEOUT_PRESCALER_CFG_0_WORD_COUNT                         0x1
#define MISCREG_SCE_P2PS_MST_TIMEOUT_PRESCALER_CFG_0_RESET_VAL                  _MK_MASK_CONST(0x8000000d)
#define MISCREG_SCE_P2PS_MST_TIMEOUT_PRESCALER_CFG_0_RESET_MASK                         _MK_MASK_CONST(0x8000000f)
#define MISCREG_SCE_P2PS_MST_TIMEOUT_PRESCALER_CFG_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define MISCREG_SCE_P2PS_MST_TIMEOUT_PRESCALER_CFG_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define MISCREG_SCE_P2PS_MST_TIMEOUT_PRESCALER_CFG_0_READ_MASK                  _MK_MASK_CONST(0x8000000f)
#define MISCREG_SCE_P2PS_MST_TIMEOUT_PRESCALER_CFG_0_WRITE_MASK                         _MK_MASK_CONST(0x8000000f)
#define MISCREG_SCE_P2PS_MST_TIMEOUT_PRESCALER_CFG_0_EXTREF_EN_SHIFT                    _MK_SHIFT_CONST(31)
#define MISCREG_SCE_P2PS_MST_TIMEOUT_PRESCALER_CFG_0_EXTREF_EN_FIELD                    _MK_FIELD_CONST(0x1, MISCREG_SCE_P2PS_MST_TIMEOUT_PRESCALER_CFG_0_EXTREF_EN_SHIFT)
#define MISCREG_SCE_P2PS_MST_TIMEOUT_PRESCALER_CFG_0_EXTREF_EN_RANGE                    31:31
#define MISCREG_SCE_P2PS_MST_TIMEOUT_PRESCALER_CFG_0_EXTREF_EN_WOFFSET                  0x0
#define MISCREG_SCE_P2PS_MST_TIMEOUT_PRESCALER_CFG_0_EXTREF_EN_DEFAULT                  _MK_MASK_CONST(0x1)
#define MISCREG_SCE_P2PS_MST_TIMEOUT_PRESCALER_CFG_0_EXTREF_EN_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define MISCREG_SCE_P2PS_MST_TIMEOUT_PRESCALER_CFG_0_EXTREF_EN_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define MISCREG_SCE_P2PS_MST_TIMEOUT_PRESCALER_CFG_0_EXTREF_EN_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define MISCREG_SCE_P2PS_MST_TIMEOUT_PRESCALER_CFG_0_EXTREF_EN_PARITY_PROTECTION                        _MK_MASK_CONST(0x1)
#define MISCREG_SCE_P2PS_MST_TIMEOUT_PRESCALER_CFG_0_EXTREF_EN_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)
#define MISCREG_SCE_P2PS_MST_TIMEOUT_PRESCALER_CFG_0_EXTREF_EN_DISABLE                  _MK_ENUM_CONST(0)
#define MISCREG_SCE_P2PS_MST_TIMEOUT_PRESCALER_CFG_0_EXTREF_EN_ENABLE                   _MK_ENUM_CONST(1)

#define MISCREG_SCE_P2PS_MST_TIMEOUT_PRESCALER_CFG_0_EXTREF_SRC_SHIFT                   _MK_SHIFT_CONST(0)
#define MISCREG_SCE_P2PS_MST_TIMEOUT_PRESCALER_CFG_0_EXTREF_SRC_FIELD                   _MK_FIELD_CONST(0xf, MISCREG_SCE_P2PS_MST_TIMEOUT_PRESCALER_CFG_0_EXTREF_SRC_SHIFT)
#define MISCREG_SCE_P2PS_MST_TIMEOUT_PRESCALER_CFG_0_EXTREF_SRC_RANGE                   3:0
#define MISCREG_SCE_P2PS_MST_TIMEOUT_PRESCALER_CFG_0_EXTREF_SRC_WOFFSET                 0x0
#define MISCREG_SCE_P2PS_MST_TIMEOUT_PRESCALER_CFG_0_EXTREF_SRC_DEFAULT                 _MK_MASK_CONST(0xd)
#define MISCREG_SCE_P2PS_MST_TIMEOUT_PRESCALER_CFG_0_EXTREF_SRC_DEFAULT_MASK                    _MK_MASK_CONST(0xf)
#define MISCREG_SCE_P2PS_MST_TIMEOUT_PRESCALER_CFG_0_EXTREF_SRC_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define MISCREG_SCE_P2PS_MST_TIMEOUT_PRESCALER_CFG_0_EXTREF_SRC_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define MISCREG_SCE_P2PS_MST_TIMEOUT_PRESCALER_CFG_0_EXTREF_SRC_PARITY_PROTECTION                       _MK_MASK_CONST(0x1)
#define MISCREG_SCE_P2PS_MST_TIMEOUT_PRESCALER_CFG_0_EXTREF_SRC_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)


// Register MISCREG_TSECA_P2PS_MST_TIMEOUT_PRESCALER_CFG_0
#define MISCREG_TSECA_P2PS_MST_TIMEOUT_PRESCALER_CFG_0                  _MK_ADDR_CONST(0x1284)
#define MISCREG_TSECA_P2PS_MST_TIMEOUT_PRESCALER_CFG_0_SECURE                   0x0
#define MISCREG_TSECA_P2PS_MST_TIMEOUT_PRESCALER_CFG_0_DUAL                     0x0
#define MISCREG_TSECA_P2PS_MST_TIMEOUT_PRESCALER_CFG_0_SCR                      0
#define MISCREG_TSECA_P2PS_MST_TIMEOUT_PRESCALER_CFG_0_WORD_COUNT                       0x1
#define MISCREG_TSECA_P2PS_MST_TIMEOUT_PRESCALER_CFG_0_RESET_VAL                        _MK_MASK_CONST(0x8000000d)
#define MISCREG_TSECA_P2PS_MST_TIMEOUT_PRESCALER_CFG_0_RESET_MASK                       _MK_MASK_CONST(0x8000000f)
#define MISCREG_TSECA_P2PS_MST_TIMEOUT_PRESCALER_CFG_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define MISCREG_TSECA_P2PS_MST_TIMEOUT_PRESCALER_CFG_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define MISCREG_TSECA_P2PS_MST_TIMEOUT_PRESCALER_CFG_0_READ_MASK                        _MK_MASK_CONST(0x8000000f)
#define MISCREG_TSECA_P2PS_MST_TIMEOUT_PRESCALER_CFG_0_WRITE_MASK                       _MK_MASK_CONST(0x8000000f)
#define MISCREG_TSECA_P2PS_MST_TIMEOUT_PRESCALER_CFG_0_EXTREF_EN_SHIFT                  _MK_SHIFT_CONST(31)
#define MISCREG_TSECA_P2PS_MST_TIMEOUT_PRESCALER_CFG_0_EXTREF_EN_FIELD                  _MK_FIELD_CONST(0x1, MISCREG_TSECA_P2PS_MST_TIMEOUT_PRESCALER_CFG_0_EXTREF_EN_SHIFT)
#define MISCREG_TSECA_P2PS_MST_TIMEOUT_PRESCALER_CFG_0_EXTREF_EN_RANGE                  31:31
#define MISCREG_TSECA_P2PS_MST_TIMEOUT_PRESCALER_CFG_0_EXTREF_EN_WOFFSET                        0x0
#define MISCREG_TSECA_P2PS_MST_TIMEOUT_PRESCALER_CFG_0_EXTREF_EN_DEFAULT                        _MK_MASK_CONST(0x1)
#define MISCREG_TSECA_P2PS_MST_TIMEOUT_PRESCALER_CFG_0_EXTREF_EN_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define MISCREG_TSECA_P2PS_MST_TIMEOUT_PRESCALER_CFG_0_EXTREF_EN_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define MISCREG_TSECA_P2PS_MST_TIMEOUT_PRESCALER_CFG_0_EXTREF_EN_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define MISCREG_TSECA_P2PS_MST_TIMEOUT_PRESCALER_CFG_0_EXTREF_EN_PARITY_PROTECTION                      _MK_MASK_CONST(0x1)
#define MISCREG_TSECA_P2PS_MST_TIMEOUT_PRESCALER_CFG_0_EXTREF_EN_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define MISCREG_TSECA_P2PS_MST_TIMEOUT_PRESCALER_CFG_0_EXTREF_EN_DISABLE                        _MK_ENUM_CONST(0)
#define MISCREG_TSECA_P2PS_MST_TIMEOUT_PRESCALER_CFG_0_EXTREF_EN_ENABLE                 _MK_ENUM_CONST(1)

#define MISCREG_TSECA_P2PS_MST_TIMEOUT_PRESCALER_CFG_0_EXTREF_SRC_SHIFT                 _MK_SHIFT_CONST(0)
#define MISCREG_TSECA_P2PS_MST_TIMEOUT_PRESCALER_CFG_0_EXTREF_SRC_FIELD                 _MK_FIELD_CONST(0xf, MISCREG_TSECA_P2PS_MST_TIMEOUT_PRESCALER_CFG_0_EXTREF_SRC_SHIFT)
#define MISCREG_TSECA_P2PS_MST_TIMEOUT_PRESCALER_CFG_0_EXTREF_SRC_RANGE                 3:0
#define MISCREG_TSECA_P2PS_MST_TIMEOUT_PRESCALER_CFG_0_EXTREF_SRC_WOFFSET                       0x0
#define MISCREG_TSECA_P2PS_MST_TIMEOUT_PRESCALER_CFG_0_EXTREF_SRC_DEFAULT                       _MK_MASK_CONST(0xd)
#define MISCREG_TSECA_P2PS_MST_TIMEOUT_PRESCALER_CFG_0_EXTREF_SRC_DEFAULT_MASK                  _MK_MASK_CONST(0xf)
#define MISCREG_TSECA_P2PS_MST_TIMEOUT_PRESCALER_CFG_0_EXTREF_SRC_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define MISCREG_TSECA_P2PS_MST_TIMEOUT_PRESCALER_CFG_0_EXTREF_SRC_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define MISCREG_TSECA_P2PS_MST_TIMEOUT_PRESCALER_CFG_0_EXTREF_SRC_PARITY_PROTECTION                     _MK_MASK_CONST(0x1)
#define MISCREG_TSECA_P2PS_MST_TIMEOUT_PRESCALER_CFG_0_EXTREF_SRC_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)


// Register MISCREG_TSECB_P2PS_MST_TIMEOUT_PRESCALER_CFG_0
#define MISCREG_TSECB_P2PS_MST_TIMEOUT_PRESCALER_CFG_0                  _MK_ADDR_CONST(0x1288)
#define MISCREG_TSECB_P2PS_MST_TIMEOUT_PRESCALER_CFG_0_SECURE                   0x0
#define MISCREG_TSECB_P2PS_MST_TIMEOUT_PRESCALER_CFG_0_DUAL                     0x0
#define MISCREG_TSECB_P2PS_MST_TIMEOUT_PRESCALER_CFG_0_SCR                      0
#define MISCREG_TSECB_P2PS_MST_TIMEOUT_PRESCALER_CFG_0_WORD_COUNT                       0x1
#define MISCREG_TSECB_P2PS_MST_TIMEOUT_PRESCALER_CFG_0_RESET_VAL                        _MK_MASK_CONST(0x8000000d)
#define MISCREG_TSECB_P2PS_MST_TIMEOUT_PRESCALER_CFG_0_RESET_MASK                       _MK_MASK_CONST(0x8000000f)
#define MISCREG_TSECB_P2PS_MST_TIMEOUT_PRESCALER_CFG_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define MISCREG_TSECB_P2PS_MST_TIMEOUT_PRESCALER_CFG_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define MISCREG_TSECB_P2PS_MST_TIMEOUT_PRESCALER_CFG_0_READ_MASK                        _MK_MASK_CONST(0x8000000f)
#define MISCREG_TSECB_P2PS_MST_TIMEOUT_PRESCALER_CFG_0_WRITE_MASK                       _MK_MASK_CONST(0x8000000f)
#define MISCREG_TSECB_P2PS_MST_TIMEOUT_PRESCALER_CFG_0_EXTREF_EN_SHIFT                  _MK_SHIFT_CONST(31)
#define MISCREG_TSECB_P2PS_MST_TIMEOUT_PRESCALER_CFG_0_EXTREF_EN_FIELD                  _MK_FIELD_CONST(0x1, MISCREG_TSECB_P2PS_MST_TIMEOUT_PRESCALER_CFG_0_EXTREF_EN_SHIFT)
#define MISCREG_TSECB_P2PS_MST_TIMEOUT_PRESCALER_CFG_0_EXTREF_EN_RANGE                  31:31
#define MISCREG_TSECB_P2PS_MST_TIMEOUT_PRESCALER_CFG_0_EXTREF_EN_WOFFSET                        0x0
#define MISCREG_TSECB_P2PS_MST_TIMEOUT_PRESCALER_CFG_0_EXTREF_EN_DEFAULT                        _MK_MASK_CONST(0x1)
#define MISCREG_TSECB_P2PS_MST_TIMEOUT_PRESCALER_CFG_0_EXTREF_EN_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define MISCREG_TSECB_P2PS_MST_TIMEOUT_PRESCALER_CFG_0_EXTREF_EN_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define MISCREG_TSECB_P2PS_MST_TIMEOUT_PRESCALER_CFG_0_EXTREF_EN_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define MISCREG_TSECB_P2PS_MST_TIMEOUT_PRESCALER_CFG_0_EXTREF_EN_PARITY_PROTECTION                      _MK_MASK_CONST(0x1)
#define MISCREG_TSECB_P2PS_MST_TIMEOUT_PRESCALER_CFG_0_EXTREF_EN_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define MISCREG_TSECB_P2PS_MST_TIMEOUT_PRESCALER_CFG_0_EXTREF_EN_DISABLE                        _MK_ENUM_CONST(0)
#define MISCREG_TSECB_P2PS_MST_TIMEOUT_PRESCALER_CFG_0_EXTREF_EN_ENABLE                 _MK_ENUM_CONST(1)

#define MISCREG_TSECB_P2PS_MST_TIMEOUT_PRESCALER_CFG_0_EXTREF_SRC_SHIFT                 _MK_SHIFT_CONST(0)
#define MISCREG_TSECB_P2PS_MST_TIMEOUT_PRESCALER_CFG_0_EXTREF_SRC_FIELD                 _MK_FIELD_CONST(0xf, MISCREG_TSECB_P2PS_MST_TIMEOUT_PRESCALER_CFG_0_EXTREF_SRC_SHIFT)
#define MISCREG_TSECB_P2PS_MST_TIMEOUT_PRESCALER_CFG_0_EXTREF_SRC_RANGE                 3:0
#define MISCREG_TSECB_P2PS_MST_TIMEOUT_PRESCALER_CFG_0_EXTREF_SRC_WOFFSET                       0x0
#define MISCREG_TSECB_P2PS_MST_TIMEOUT_PRESCALER_CFG_0_EXTREF_SRC_DEFAULT                       _MK_MASK_CONST(0xd)
#define MISCREG_TSECB_P2PS_MST_TIMEOUT_PRESCALER_CFG_0_EXTREF_SRC_DEFAULT_MASK                  _MK_MASK_CONST(0xf)
#define MISCREG_TSECB_P2PS_MST_TIMEOUT_PRESCALER_CFG_0_EXTREF_SRC_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define MISCREG_TSECB_P2PS_MST_TIMEOUT_PRESCALER_CFG_0_EXTREF_SRC_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define MISCREG_TSECB_P2PS_MST_TIMEOUT_PRESCALER_CFG_0_EXTREF_SRC_PARITY_PROTECTION                     _MK_MASK_CONST(0x1)
#define MISCREG_TSECB_P2PS_MST_TIMEOUT_PRESCALER_CFG_0_EXTREF_SRC_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)


// Reserved address 0x128c

// Reserved address 0x1290

// Reserved address 0x1294

// Reserved address 0x1298

// Reserved address 0x129c

// Reserved address 0x12a0

// Reserved address 0x12a4

// Reserved address 0x12a8

// Reserved address 0x12ac

// Reserved address 0x12b0

// Reserved address 0x12b4

// Reserved address 0x12b8

// Reserved address 0x12bc

// Reserved address 0x12c0

// Reserved address 0x12c4

// Reserved address 0x12c8

// Reserved address 0x12cc

// Reserved address 0x12d0

// Reserved address 0x12d4

// Reserved address 0x12d8

// Reserved address 0x12dc

// Reserved address 0x12e0

// Reserved address 0x12e4

// Reserved address 0x12e8

// Reserved address 0x12ec

// Reserved address 0x12f0

// Reserved address 0x12f4

// Reserved address 0x12f8

// Reserved address 0x12fc

// Reserved address 0x1300

// Reserved address 0x1304

// Reserved address 0x1308

// Register MISCREG_AXIS_SATELLITE_AXI2APB_P2PM_SLV_TIMEOUT_PRESCALER_CFG_0
#define MISCREG_AXIS_SATELLITE_AXI2APB_P2PM_SLV_TIMEOUT_PRESCALER_CFG_0                 _MK_ADDR_CONST(0x130c)
#define MISCREG_AXIS_SATELLITE_AXI2APB_P2PM_SLV_TIMEOUT_PRESCALER_CFG_0_SECURE                  0x0
#define MISCREG_AXIS_SATELLITE_AXI2APB_P2PM_SLV_TIMEOUT_PRESCALER_CFG_0_DUAL                    0x0
#define MISCREG_AXIS_SATELLITE_AXI2APB_P2PM_SLV_TIMEOUT_PRESCALER_CFG_0_SCR                     0
#define MISCREG_AXIS_SATELLITE_AXI2APB_P2PM_SLV_TIMEOUT_PRESCALER_CFG_0_WORD_COUNT                      0x1
#define MISCREG_AXIS_SATELLITE_AXI2APB_P2PM_SLV_TIMEOUT_PRESCALER_CFG_0_RESET_VAL                       _MK_MASK_CONST(0x8000000d)
#define MISCREG_AXIS_SATELLITE_AXI2APB_P2PM_SLV_TIMEOUT_PRESCALER_CFG_0_RESET_MASK                      _MK_MASK_CONST(0x8000000f)
#define MISCREG_AXIS_SATELLITE_AXI2APB_P2PM_SLV_TIMEOUT_PRESCALER_CFG_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define MISCREG_AXIS_SATELLITE_AXI2APB_P2PM_SLV_TIMEOUT_PRESCALER_CFG_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define MISCREG_AXIS_SATELLITE_AXI2APB_P2PM_SLV_TIMEOUT_PRESCALER_CFG_0_READ_MASK                       _MK_MASK_CONST(0x8000000f)
#define MISCREG_AXIS_SATELLITE_AXI2APB_P2PM_SLV_TIMEOUT_PRESCALER_CFG_0_WRITE_MASK                      _MK_MASK_CONST(0x8000000f)
#define MISCREG_AXIS_SATELLITE_AXI2APB_P2PM_SLV_TIMEOUT_PRESCALER_CFG_0_EXTREF_EN_SHIFT                 _MK_SHIFT_CONST(31)
#define MISCREG_AXIS_SATELLITE_AXI2APB_P2PM_SLV_TIMEOUT_PRESCALER_CFG_0_EXTREF_EN_FIELD                 _MK_FIELD_CONST(0x1, MISCREG_AXIS_SATELLITE_AXI2APB_P2PM_SLV_TIMEOUT_PRESCALER_CFG_0_EXTREF_EN_SHIFT)
#define MISCREG_AXIS_SATELLITE_AXI2APB_P2PM_SLV_TIMEOUT_PRESCALER_CFG_0_EXTREF_EN_RANGE                 31:31
#define MISCREG_AXIS_SATELLITE_AXI2APB_P2PM_SLV_TIMEOUT_PRESCALER_CFG_0_EXTREF_EN_WOFFSET                       0x0
#define MISCREG_AXIS_SATELLITE_AXI2APB_P2PM_SLV_TIMEOUT_PRESCALER_CFG_0_EXTREF_EN_DEFAULT                       _MK_MASK_CONST(0x1)
#define MISCREG_AXIS_SATELLITE_AXI2APB_P2PM_SLV_TIMEOUT_PRESCALER_CFG_0_EXTREF_EN_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define MISCREG_AXIS_SATELLITE_AXI2APB_P2PM_SLV_TIMEOUT_PRESCALER_CFG_0_EXTREF_EN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define MISCREG_AXIS_SATELLITE_AXI2APB_P2PM_SLV_TIMEOUT_PRESCALER_CFG_0_EXTREF_EN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define MISCREG_AXIS_SATELLITE_AXI2APB_P2PM_SLV_TIMEOUT_PRESCALER_CFG_0_EXTREF_EN_PARITY_PROTECTION                     _MK_MASK_CONST(0x1)
#define MISCREG_AXIS_SATELLITE_AXI2APB_P2PM_SLV_TIMEOUT_PRESCALER_CFG_0_EXTREF_EN_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)
#define MISCREG_AXIS_SATELLITE_AXI2APB_P2PM_SLV_TIMEOUT_PRESCALER_CFG_0_EXTREF_EN_DISABLE                       _MK_ENUM_CONST(0)
#define MISCREG_AXIS_SATELLITE_AXI2APB_P2PM_SLV_TIMEOUT_PRESCALER_CFG_0_EXTREF_EN_ENABLE                        _MK_ENUM_CONST(1)

#define MISCREG_AXIS_SATELLITE_AXI2APB_P2PM_SLV_TIMEOUT_PRESCALER_CFG_0_EXTREF_SRC_SHIFT                        _MK_SHIFT_CONST(0)
#define MISCREG_AXIS_SATELLITE_AXI2APB_P2PM_SLV_TIMEOUT_PRESCALER_CFG_0_EXTREF_SRC_FIELD                        _MK_FIELD_CONST(0xf, MISCREG_AXIS_SATELLITE_AXI2APB_P2PM_SLV_TIMEOUT_PRESCALER_CFG_0_EXTREF_SRC_SHIFT)
#define MISCREG_AXIS_SATELLITE_AXI2APB_P2PM_SLV_TIMEOUT_PRESCALER_CFG_0_EXTREF_SRC_RANGE                        3:0
#define MISCREG_AXIS_SATELLITE_AXI2APB_P2PM_SLV_TIMEOUT_PRESCALER_CFG_0_EXTREF_SRC_WOFFSET                      0x0
#define MISCREG_AXIS_SATELLITE_AXI2APB_P2PM_SLV_TIMEOUT_PRESCALER_CFG_0_EXTREF_SRC_DEFAULT                      _MK_MASK_CONST(0xd)
#define MISCREG_AXIS_SATELLITE_AXI2APB_P2PM_SLV_TIMEOUT_PRESCALER_CFG_0_EXTREF_SRC_DEFAULT_MASK                 _MK_MASK_CONST(0xf)
#define MISCREG_AXIS_SATELLITE_AXI2APB_P2PM_SLV_TIMEOUT_PRESCALER_CFG_0_EXTREF_SRC_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define MISCREG_AXIS_SATELLITE_AXI2APB_P2PM_SLV_TIMEOUT_PRESCALER_CFG_0_EXTREF_SRC_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define MISCREG_AXIS_SATELLITE_AXI2APB_P2PM_SLV_TIMEOUT_PRESCALER_CFG_0_EXTREF_SRC_PARITY_PROTECTION                    _MK_MASK_CONST(0x1)
#define MISCREG_AXIS_SATELLITE_AXI2APB_P2PM_SLV_TIMEOUT_PRESCALER_CFG_0_EXTREF_SRC_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)


// Register MISCREG_AXIS_SATELLITE_GROUT_SLV_TIMEOUT_PRESCALER_CFG_0
#define MISCREG_AXIS_SATELLITE_GROUT_SLV_TIMEOUT_PRESCALER_CFG_0                        _MK_ADDR_CONST(0x1310)
#define MISCREG_AXIS_SATELLITE_GROUT_SLV_TIMEOUT_PRESCALER_CFG_0_SECURE                         0x0
#define MISCREG_AXIS_SATELLITE_GROUT_SLV_TIMEOUT_PRESCALER_CFG_0_DUAL                   0x0
#define MISCREG_AXIS_SATELLITE_GROUT_SLV_TIMEOUT_PRESCALER_CFG_0_SCR                    0
#define MISCREG_AXIS_SATELLITE_GROUT_SLV_TIMEOUT_PRESCALER_CFG_0_WORD_COUNT                     0x1
#define MISCREG_AXIS_SATELLITE_GROUT_SLV_TIMEOUT_PRESCALER_CFG_0_RESET_VAL                      _MK_MASK_CONST(0x8000000d)
#define MISCREG_AXIS_SATELLITE_GROUT_SLV_TIMEOUT_PRESCALER_CFG_0_RESET_MASK                     _MK_MASK_CONST(0x8000000f)
#define MISCREG_AXIS_SATELLITE_GROUT_SLV_TIMEOUT_PRESCALER_CFG_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define MISCREG_AXIS_SATELLITE_GROUT_SLV_TIMEOUT_PRESCALER_CFG_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define MISCREG_AXIS_SATELLITE_GROUT_SLV_TIMEOUT_PRESCALER_CFG_0_READ_MASK                      _MK_MASK_CONST(0x8000000f)
#define MISCREG_AXIS_SATELLITE_GROUT_SLV_TIMEOUT_PRESCALER_CFG_0_WRITE_MASK                     _MK_MASK_CONST(0x8000000f)
#define MISCREG_AXIS_SATELLITE_GROUT_SLV_TIMEOUT_PRESCALER_CFG_0_EXTREF_EN_SHIFT                        _MK_SHIFT_CONST(31)
#define MISCREG_AXIS_SATELLITE_GROUT_SLV_TIMEOUT_PRESCALER_CFG_0_EXTREF_EN_FIELD                        _MK_FIELD_CONST(0x1, MISCREG_AXIS_SATELLITE_GROUT_SLV_TIMEOUT_PRESCALER_CFG_0_EXTREF_EN_SHIFT)
#define MISCREG_AXIS_SATELLITE_GROUT_SLV_TIMEOUT_PRESCALER_CFG_0_EXTREF_EN_RANGE                        31:31
#define MISCREG_AXIS_SATELLITE_GROUT_SLV_TIMEOUT_PRESCALER_CFG_0_EXTREF_EN_WOFFSET                      0x0
#define MISCREG_AXIS_SATELLITE_GROUT_SLV_TIMEOUT_PRESCALER_CFG_0_EXTREF_EN_DEFAULT                      _MK_MASK_CONST(0x1)
#define MISCREG_AXIS_SATELLITE_GROUT_SLV_TIMEOUT_PRESCALER_CFG_0_EXTREF_EN_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define MISCREG_AXIS_SATELLITE_GROUT_SLV_TIMEOUT_PRESCALER_CFG_0_EXTREF_EN_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define MISCREG_AXIS_SATELLITE_GROUT_SLV_TIMEOUT_PRESCALER_CFG_0_EXTREF_EN_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define MISCREG_AXIS_SATELLITE_GROUT_SLV_TIMEOUT_PRESCALER_CFG_0_EXTREF_EN_PARITY_PROTECTION                    _MK_MASK_CONST(0x1)
#define MISCREG_AXIS_SATELLITE_GROUT_SLV_TIMEOUT_PRESCALER_CFG_0_EXTREF_EN_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)
#define MISCREG_AXIS_SATELLITE_GROUT_SLV_TIMEOUT_PRESCALER_CFG_0_EXTREF_EN_DISABLE                      _MK_ENUM_CONST(0)
#define MISCREG_AXIS_SATELLITE_GROUT_SLV_TIMEOUT_PRESCALER_CFG_0_EXTREF_EN_ENABLE                       _MK_ENUM_CONST(1)

#define MISCREG_AXIS_SATELLITE_GROUT_SLV_TIMEOUT_PRESCALER_CFG_0_EXTREF_SRC_SHIFT                       _MK_SHIFT_CONST(0)
#define MISCREG_AXIS_SATELLITE_GROUT_SLV_TIMEOUT_PRESCALER_CFG_0_EXTREF_SRC_FIELD                       _MK_FIELD_CONST(0xf, MISCREG_AXIS_SATELLITE_GROUT_SLV_TIMEOUT_PRESCALER_CFG_0_EXTREF_SRC_SHIFT)
#define MISCREG_AXIS_SATELLITE_GROUT_SLV_TIMEOUT_PRESCALER_CFG_0_EXTREF_SRC_RANGE                       3:0
#define MISCREG_AXIS_SATELLITE_GROUT_SLV_TIMEOUT_PRESCALER_CFG_0_EXTREF_SRC_WOFFSET                     0x0
#define MISCREG_AXIS_SATELLITE_GROUT_SLV_TIMEOUT_PRESCALER_CFG_0_EXTREF_SRC_DEFAULT                     _MK_MASK_CONST(0xd)
#define MISCREG_AXIS_SATELLITE_GROUT_SLV_TIMEOUT_PRESCALER_CFG_0_EXTREF_SRC_DEFAULT_MASK                        _MK_MASK_CONST(0xf)
#define MISCREG_AXIS_SATELLITE_GROUT_SLV_TIMEOUT_PRESCALER_CFG_0_EXTREF_SRC_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define MISCREG_AXIS_SATELLITE_GROUT_SLV_TIMEOUT_PRESCALER_CFG_0_EXTREF_SRC_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define MISCREG_AXIS_SATELLITE_GROUT_SLV_TIMEOUT_PRESCALER_CFG_0_EXTREF_SRC_PARITY_PROTECTION                   _MK_MASK_CONST(0x1)
#define MISCREG_AXIS_SATELLITE_GROUT_SLV_TIMEOUT_PRESCALER_CFG_0_EXTREF_SRC_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)


// Register MISCREG_GPU_P2PM_SLV_TIMEOUT_PRESCALER_CFG_0
#define MISCREG_GPU_P2PM_SLV_TIMEOUT_PRESCALER_CFG_0                    _MK_ADDR_CONST(0x1314)
#define MISCREG_GPU_P2PM_SLV_TIMEOUT_PRESCALER_CFG_0_SECURE                     0x0
#define MISCREG_GPU_P2PM_SLV_TIMEOUT_PRESCALER_CFG_0_DUAL                       0x0
#define MISCREG_GPU_P2PM_SLV_TIMEOUT_PRESCALER_CFG_0_SCR                        0
#define MISCREG_GPU_P2PM_SLV_TIMEOUT_PRESCALER_CFG_0_WORD_COUNT                         0x1
#define MISCREG_GPU_P2PM_SLV_TIMEOUT_PRESCALER_CFG_0_RESET_VAL                  _MK_MASK_CONST(0x8000000d)
#define MISCREG_GPU_P2PM_SLV_TIMEOUT_PRESCALER_CFG_0_RESET_MASK                         _MK_MASK_CONST(0x8000000f)
#define MISCREG_GPU_P2PM_SLV_TIMEOUT_PRESCALER_CFG_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define MISCREG_GPU_P2PM_SLV_TIMEOUT_PRESCALER_CFG_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define MISCREG_GPU_P2PM_SLV_TIMEOUT_PRESCALER_CFG_0_READ_MASK                  _MK_MASK_CONST(0x8000000f)
#define MISCREG_GPU_P2PM_SLV_TIMEOUT_PRESCALER_CFG_0_WRITE_MASK                         _MK_MASK_CONST(0x8000000f)
#define MISCREG_GPU_P2PM_SLV_TIMEOUT_PRESCALER_CFG_0_EXTREF_EN_SHIFT                    _MK_SHIFT_CONST(31)
#define MISCREG_GPU_P2PM_SLV_TIMEOUT_PRESCALER_CFG_0_EXTREF_EN_FIELD                    _MK_FIELD_CONST(0x1, MISCREG_GPU_P2PM_SLV_TIMEOUT_PRESCALER_CFG_0_EXTREF_EN_SHIFT)
#define MISCREG_GPU_P2PM_SLV_TIMEOUT_PRESCALER_CFG_0_EXTREF_EN_RANGE                    31:31
#define MISCREG_GPU_P2PM_SLV_TIMEOUT_PRESCALER_CFG_0_EXTREF_EN_WOFFSET                  0x0
#define MISCREG_GPU_P2PM_SLV_TIMEOUT_PRESCALER_CFG_0_EXTREF_EN_DEFAULT                  _MK_MASK_CONST(0x1)
#define MISCREG_GPU_P2PM_SLV_TIMEOUT_PRESCALER_CFG_0_EXTREF_EN_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define MISCREG_GPU_P2PM_SLV_TIMEOUT_PRESCALER_CFG_0_EXTREF_EN_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define MISCREG_GPU_P2PM_SLV_TIMEOUT_PRESCALER_CFG_0_EXTREF_EN_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define MISCREG_GPU_P2PM_SLV_TIMEOUT_PRESCALER_CFG_0_EXTREF_EN_PARITY_PROTECTION                        _MK_MASK_CONST(0x1)
#define MISCREG_GPU_P2PM_SLV_TIMEOUT_PRESCALER_CFG_0_EXTREF_EN_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)
#define MISCREG_GPU_P2PM_SLV_TIMEOUT_PRESCALER_CFG_0_EXTREF_EN_DISABLE                  _MK_ENUM_CONST(0)
#define MISCREG_GPU_P2PM_SLV_TIMEOUT_PRESCALER_CFG_0_EXTREF_EN_ENABLE                   _MK_ENUM_CONST(1)

#define MISCREG_GPU_P2PM_SLV_TIMEOUT_PRESCALER_CFG_0_EXTREF_SRC_SHIFT                   _MK_SHIFT_CONST(0)
#define MISCREG_GPU_P2PM_SLV_TIMEOUT_PRESCALER_CFG_0_EXTREF_SRC_FIELD                   _MK_FIELD_CONST(0xf, MISCREG_GPU_P2PM_SLV_TIMEOUT_PRESCALER_CFG_0_EXTREF_SRC_SHIFT)
#define MISCREG_GPU_P2PM_SLV_TIMEOUT_PRESCALER_CFG_0_EXTREF_SRC_RANGE                   3:0
#define MISCREG_GPU_P2PM_SLV_TIMEOUT_PRESCALER_CFG_0_EXTREF_SRC_WOFFSET                 0x0
#define MISCREG_GPU_P2PM_SLV_TIMEOUT_PRESCALER_CFG_0_EXTREF_SRC_DEFAULT                 _MK_MASK_CONST(0xd)
#define MISCREG_GPU_P2PM_SLV_TIMEOUT_PRESCALER_CFG_0_EXTREF_SRC_DEFAULT_MASK                    _MK_MASK_CONST(0xf)
#define MISCREG_GPU_P2PM_SLV_TIMEOUT_PRESCALER_CFG_0_EXTREF_SRC_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define MISCREG_GPU_P2PM_SLV_TIMEOUT_PRESCALER_CFG_0_EXTREF_SRC_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define MISCREG_GPU_P2PM_SLV_TIMEOUT_PRESCALER_CFG_0_EXTREF_SRC_PARITY_PROTECTION                       _MK_MASK_CONST(0x1)
#define MISCREG_GPU_P2PM_SLV_TIMEOUT_PRESCALER_CFG_0_EXTREF_SRC_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)


// Register MISCREG_HOST1X_P2PM_SLV_TIMEOUT_PRESCALER_CFG_0
#define MISCREG_HOST1X_P2PM_SLV_TIMEOUT_PRESCALER_CFG_0                 _MK_ADDR_CONST(0x1318)
#define MISCREG_HOST1X_P2PM_SLV_TIMEOUT_PRESCALER_CFG_0_SECURE                  0x0
#define MISCREG_HOST1X_P2PM_SLV_TIMEOUT_PRESCALER_CFG_0_DUAL                    0x0
#define MISCREG_HOST1X_P2PM_SLV_TIMEOUT_PRESCALER_CFG_0_SCR                     0
#define MISCREG_HOST1X_P2PM_SLV_TIMEOUT_PRESCALER_CFG_0_WORD_COUNT                      0x1
#define MISCREG_HOST1X_P2PM_SLV_TIMEOUT_PRESCALER_CFG_0_RESET_VAL                       _MK_MASK_CONST(0x8000000d)
#define MISCREG_HOST1X_P2PM_SLV_TIMEOUT_PRESCALER_CFG_0_RESET_MASK                      _MK_MASK_CONST(0x8000000f)
#define MISCREG_HOST1X_P2PM_SLV_TIMEOUT_PRESCALER_CFG_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define MISCREG_HOST1X_P2PM_SLV_TIMEOUT_PRESCALER_CFG_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define MISCREG_HOST1X_P2PM_SLV_TIMEOUT_PRESCALER_CFG_0_READ_MASK                       _MK_MASK_CONST(0x8000000f)
#define MISCREG_HOST1X_P2PM_SLV_TIMEOUT_PRESCALER_CFG_0_WRITE_MASK                      _MK_MASK_CONST(0x8000000f)
#define MISCREG_HOST1X_P2PM_SLV_TIMEOUT_PRESCALER_CFG_0_EXTREF_EN_SHIFT                 _MK_SHIFT_CONST(31)
#define MISCREG_HOST1X_P2PM_SLV_TIMEOUT_PRESCALER_CFG_0_EXTREF_EN_FIELD                 _MK_FIELD_CONST(0x1, MISCREG_HOST1X_P2PM_SLV_TIMEOUT_PRESCALER_CFG_0_EXTREF_EN_SHIFT)
#define MISCREG_HOST1X_P2PM_SLV_TIMEOUT_PRESCALER_CFG_0_EXTREF_EN_RANGE                 31:31
#define MISCREG_HOST1X_P2PM_SLV_TIMEOUT_PRESCALER_CFG_0_EXTREF_EN_WOFFSET                       0x0
#define MISCREG_HOST1X_P2PM_SLV_TIMEOUT_PRESCALER_CFG_0_EXTREF_EN_DEFAULT                       _MK_MASK_CONST(0x1)
#define MISCREG_HOST1X_P2PM_SLV_TIMEOUT_PRESCALER_CFG_0_EXTREF_EN_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define MISCREG_HOST1X_P2PM_SLV_TIMEOUT_PRESCALER_CFG_0_EXTREF_EN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define MISCREG_HOST1X_P2PM_SLV_TIMEOUT_PRESCALER_CFG_0_EXTREF_EN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define MISCREG_HOST1X_P2PM_SLV_TIMEOUT_PRESCALER_CFG_0_EXTREF_EN_PARITY_PROTECTION                     _MK_MASK_CONST(0x1)
#define MISCREG_HOST1X_P2PM_SLV_TIMEOUT_PRESCALER_CFG_0_EXTREF_EN_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)
#define MISCREG_HOST1X_P2PM_SLV_TIMEOUT_PRESCALER_CFG_0_EXTREF_EN_DISABLE                       _MK_ENUM_CONST(0)
#define MISCREG_HOST1X_P2PM_SLV_TIMEOUT_PRESCALER_CFG_0_EXTREF_EN_ENABLE                        _MK_ENUM_CONST(1)

#define MISCREG_HOST1X_P2PM_SLV_TIMEOUT_PRESCALER_CFG_0_EXTREF_SRC_SHIFT                        _MK_SHIFT_CONST(0)
#define MISCREG_HOST1X_P2PM_SLV_TIMEOUT_PRESCALER_CFG_0_EXTREF_SRC_FIELD                        _MK_FIELD_CONST(0xf, MISCREG_HOST1X_P2PM_SLV_TIMEOUT_PRESCALER_CFG_0_EXTREF_SRC_SHIFT)
#define MISCREG_HOST1X_P2PM_SLV_TIMEOUT_PRESCALER_CFG_0_EXTREF_SRC_RANGE                        3:0
#define MISCREG_HOST1X_P2PM_SLV_TIMEOUT_PRESCALER_CFG_0_EXTREF_SRC_WOFFSET                      0x0
#define MISCREG_HOST1X_P2PM_SLV_TIMEOUT_PRESCALER_CFG_0_EXTREF_SRC_DEFAULT                      _MK_MASK_CONST(0xd)
#define MISCREG_HOST1X_P2PM_SLV_TIMEOUT_PRESCALER_CFG_0_EXTREF_SRC_DEFAULT_MASK                 _MK_MASK_CONST(0xf)
#define MISCREG_HOST1X_P2PM_SLV_TIMEOUT_PRESCALER_CFG_0_EXTREF_SRC_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define MISCREG_HOST1X_P2PM_SLV_TIMEOUT_PRESCALER_CFG_0_EXTREF_SRC_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define MISCREG_HOST1X_P2PM_SLV_TIMEOUT_PRESCALER_CFG_0_EXTREF_SRC_PARITY_PROTECTION                    _MK_MASK_CONST(0x1)
#define MISCREG_HOST1X_P2PM_SLV_TIMEOUT_PRESCALER_CFG_0_EXTREF_SRC_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)


// Register MISCREG_SAPB_3_P2PM_SLV_TIMEOUT_PRESCALER_CFG_0
#define MISCREG_SAPB_3_P2PM_SLV_TIMEOUT_PRESCALER_CFG_0                 _MK_ADDR_CONST(0x131c)
#define MISCREG_SAPB_3_P2PM_SLV_TIMEOUT_PRESCALER_CFG_0_SECURE                  0x0
#define MISCREG_SAPB_3_P2PM_SLV_TIMEOUT_PRESCALER_CFG_0_DUAL                    0x0
#define MISCREG_SAPB_3_P2PM_SLV_TIMEOUT_PRESCALER_CFG_0_SCR                     0
#define MISCREG_SAPB_3_P2PM_SLV_TIMEOUT_PRESCALER_CFG_0_WORD_COUNT                      0x1
#define MISCREG_SAPB_3_P2PM_SLV_TIMEOUT_PRESCALER_CFG_0_RESET_VAL                       _MK_MASK_CONST(0x8000000d)
#define MISCREG_SAPB_3_P2PM_SLV_TIMEOUT_PRESCALER_CFG_0_RESET_MASK                      _MK_MASK_CONST(0x8000000f)
#define MISCREG_SAPB_3_P2PM_SLV_TIMEOUT_PRESCALER_CFG_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define MISCREG_SAPB_3_P2PM_SLV_TIMEOUT_PRESCALER_CFG_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define MISCREG_SAPB_3_P2PM_SLV_TIMEOUT_PRESCALER_CFG_0_READ_MASK                       _MK_MASK_CONST(0x8000000f)
#define MISCREG_SAPB_3_P2PM_SLV_TIMEOUT_PRESCALER_CFG_0_WRITE_MASK                      _MK_MASK_CONST(0x8000000f)
#define MISCREG_SAPB_3_P2PM_SLV_TIMEOUT_PRESCALER_CFG_0_EXTREF_EN_SHIFT                 _MK_SHIFT_CONST(31)
#define MISCREG_SAPB_3_P2PM_SLV_TIMEOUT_PRESCALER_CFG_0_EXTREF_EN_FIELD                 _MK_FIELD_CONST(0x1, MISCREG_SAPB_3_P2PM_SLV_TIMEOUT_PRESCALER_CFG_0_EXTREF_EN_SHIFT)
#define MISCREG_SAPB_3_P2PM_SLV_TIMEOUT_PRESCALER_CFG_0_EXTREF_EN_RANGE                 31:31
#define MISCREG_SAPB_3_P2PM_SLV_TIMEOUT_PRESCALER_CFG_0_EXTREF_EN_WOFFSET                       0x0
#define MISCREG_SAPB_3_P2PM_SLV_TIMEOUT_PRESCALER_CFG_0_EXTREF_EN_DEFAULT                       _MK_MASK_CONST(0x1)
#define MISCREG_SAPB_3_P2PM_SLV_TIMEOUT_PRESCALER_CFG_0_EXTREF_EN_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define MISCREG_SAPB_3_P2PM_SLV_TIMEOUT_PRESCALER_CFG_0_EXTREF_EN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define MISCREG_SAPB_3_P2PM_SLV_TIMEOUT_PRESCALER_CFG_0_EXTREF_EN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define MISCREG_SAPB_3_P2PM_SLV_TIMEOUT_PRESCALER_CFG_0_EXTREF_EN_PARITY_PROTECTION                     _MK_MASK_CONST(0x1)
#define MISCREG_SAPB_3_P2PM_SLV_TIMEOUT_PRESCALER_CFG_0_EXTREF_EN_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)
#define MISCREG_SAPB_3_P2PM_SLV_TIMEOUT_PRESCALER_CFG_0_EXTREF_EN_DISABLE                       _MK_ENUM_CONST(0)
#define MISCREG_SAPB_3_P2PM_SLV_TIMEOUT_PRESCALER_CFG_0_EXTREF_EN_ENABLE                        _MK_ENUM_CONST(1)

#define MISCREG_SAPB_3_P2PM_SLV_TIMEOUT_PRESCALER_CFG_0_EXTREF_SRC_SHIFT                        _MK_SHIFT_CONST(0)
#define MISCREG_SAPB_3_P2PM_SLV_TIMEOUT_PRESCALER_CFG_0_EXTREF_SRC_FIELD                        _MK_FIELD_CONST(0xf, MISCREG_SAPB_3_P2PM_SLV_TIMEOUT_PRESCALER_CFG_0_EXTREF_SRC_SHIFT)
#define MISCREG_SAPB_3_P2PM_SLV_TIMEOUT_PRESCALER_CFG_0_EXTREF_SRC_RANGE                        3:0
#define MISCREG_SAPB_3_P2PM_SLV_TIMEOUT_PRESCALER_CFG_0_EXTREF_SRC_WOFFSET                      0x0
#define MISCREG_SAPB_3_P2PM_SLV_TIMEOUT_PRESCALER_CFG_0_EXTREF_SRC_DEFAULT                      _MK_MASK_CONST(0xd)
#define MISCREG_SAPB_3_P2PM_SLV_TIMEOUT_PRESCALER_CFG_0_EXTREF_SRC_DEFAULT_MASK                 _MK_MASK_CONST(0xf)
#define MISCREG_SAPB_3_P2PM_SLV_TIMEOUT_PRESCALER_CFG_0_EXTREF_SRC_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define MISCREG_SAPB_3_P2PM_SLV_TIMEOUT_PRESCALER_CFG_0_EXTREF_SRC_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define MISCREG_SAPB_3_P2PM_SLV_TIMEOUT_PRESCALER_CFG_0_EXTREF_SRC_PARITY_PROTECTION                    _MK_MASK_CONST(0x1)
#define MISCREG_SAPB_3_P2PM_SLV_TIMEOUT_PRESCALER_CFG_0_EXTREF_SRC_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)


// Register MISCREG_SMMU0_P2PM_SLV_TIMEOUT_PRESCALER_CFG_0
#define MISCREG_SMMU0_P2PM_SLV_TIMEOUT_PRESCALER_CFG_0                  _MK_ADDR_CONST(0x1320)
#define MISCREG_SMMU0_P2PM_SLV_TIMEOUT_PRESCALER_CFG_0_SECURE                   0x0
#define MISCREG_SMMU0_P2PM_SLV_TIMEOUT_PRESCALER_CFG_0_DUAL                     0x0
#define MISCREG_SMMU0_P2PM_SLV_TIMEOUT_PRESCALER_CFG_0_SCR                      0
#define MISCREG_SMMU0_P2PM_SLV_TIMEOUT_PRESCALER_CFG_0_WORD_COUNT                       0x1
#define MISCREG_SMMU0_P2PM_SLV_TIMEOUT_PRESCALER_CFG_0_RESET_VAL                        _MK_MASK_CONST(0x8000000d)
#define MISCREG_SMMU0_P2PM_SLV_TIMEOUT_PRESCALER_CFG_0_RESET_MASK                       _MK_MASK_CONST(0x8000000f)
#define MISCREG_SMMU0_P2PM_SLV_TIMEOUT_PRESCALER_CFG_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define MISCREG_SMMU0_P2PM_SLV_TIMEOUT_PRESCALER_CFG_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define MISCREG_SMMU0_P2PM_SLV_TIMEOUT_PRESCALER_CFG_0_READ_MASK                        _MK_MASK_CONST(0x8000000f)
#define MISCREG_SMMU0_P2PM_SLV_TIMEOUT_PRESCALER_CFG_0_WRITE_MASK                       _MK_MASK_CONST(0x8000000f)
#define MISCREG_SMMU0_P2PM_SLV_TIMEOUT_PRESCALER_CFG_0_EXTREF_EN_SHIFT                  _MK_SHIFT_CONST(31)
#define MISCREG_SMMU0_P2PM_SLV_TIMEOUT_PRESCALER_CFG_0_EXTREF_EN_FIELD                  _MK_FIELD_CONST(0x1, MISCREG_SMMU0_P2PM_SLV_TIMEOUT_PRESCALER_CFG_0_EXTREF_EN_SHIFT)
#define MISCREG_SMMU0_P2PM_SLV_TIMEOUT_PRESCALER_CFG_0_EXTREF_EN_RANGE                  31:31
#define MISCREG_SMMU0_P2PM_SLV_TIMEOUT_PRESCALER_CFG_0_EXTREF_EN_WOFFSET                        0x0
#define MISCREG_SMMU0_P2PM_SLV_TIMEOUT_PRESCALER_CFG_0_EXTREF_EN_DEFAULT                        _MK_MASK_CONST(0x1)
#define MISCREG_SMMU0_P2PM_SLV_TIMEOUT_PRESCALER_CFG_0_EXTREF_EN_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define MISCREG_SMMU0_P2PM_SLV_TIMEOUT_PRESCALER_CFG_0_EXTREF_EN_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define MISCREG_SMMU0_P2PM_SLV_TIMEOUT_PRESCALER_CFG_0_EXTREF_EN_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define MISCREG_SMMU0_P2PM_SLV_TIMEOUT_PRESCALER_CFG_0_EXTREF_EN_PARITY_PROTECTION                      _MK_MASK_CONST(0x1)
#define MISCREG_SMMU0_P2PM_SLV_TIMEOUT_PRESCALER_CFG_0_EXTREF_EN_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define MISCREG_SMMU0_P2PM_SLV_TIMEOUT_PRESCALER_CFG_0_EXTREF_EN_DISABLE                        _MK_ENUM_CONST(0)
#define MISCREG_SMMU0_P2PM_SLV_TIMEOUT_PRESCALER_CFG_0_EXTREF_EN_ENABLE                 _MK_ENUM_CONST(1)

#define MISCREG_SMMU0_P2PM_SLV_TIMEOUT_PRESCALER_CFG_0_EXTREF_SRC_SHIFT                 _MK_SHIFT_CONST(0)
#define MISCREG_SMMU0_P2PM_SLV_TIMEOUT_PRESCALER_CFG_0_EXTREF_SRC_FIELD                 _MK_FIELD_CONST(0xf, MISCREG_SMMU0_P2PM_SLV_TIMEOUT_PRESCALER_CFG_0_EXTREF_SRC_SHIFT)
#define MISCREG_SMMU0_P2PM_SLV_TIMEOUT_PRESCALER_CFG_0_EXTREF_SRC_RANGE                 3:0
#define MISCREG_SMMU0_P2PM_SLV_TIMEOUT_PRESCALER_CFG_0_EXTREF_SRC_WOFFSET                       0x0
#define MISCREG_SMMU0_P2PM_SLV_TIMEOUT_PRESCALER_CFG_0_EXTREF_SRC_DEFAULT                       _MK_MASK_CONST(0xd)
#define MISCREG_SMMU0_P2PM_SLV_TIMEOUT_PRESCALER_CFG_0_EXTREF_SRC_DEFAULT_MASK                  _MK_MASK_CONST(0xf)
#define MISCREG_SMMU0_P2PM_SLV_TIMEOUT_PRESCALER_CFG_0_EXTREF_SRC_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define MISCREG_SMMU0_P2PM_SLV_TIMEOUT_PRESCALER_CFG_0_EXTREF_SRC_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define MISCREG_SMMU0_P2PM_SLV_TIMEOUT_PRESCALER_CFG_0_EXTREF_SRC_PARITY_PROTECTION                     _MK_MASK_CONST(0x1)
#define MISCREG_SMMU0_P2PM_SLV_TIMEOUT_PRESCALER_CFG_0_EXTREF_SRC_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)


// Register MISCREG_SMMU1_P2PM_SLV_TIMEOUT_PRESCALER_CFG_0
#define MISCREG_SMMU1_P2PM_SLV_TIMEOUT_PRESCALER_CFG_0                  _MK_ADDR_CONST(0x1324)
#define MISCREG_SMMU1_P2PM_SLV_TIMEOUT_PRESCALER_CFG_0_SECURE                   0x0
#define MISCREG_SMMU1_P2PM_SLV_TIMEOUT_PRESCALER_CFG_0_DUAL                     0x0
#define MISCREG_SMMU1_P2PM_SLV_TIMEOUT_PRESCALER_CFG_0_SCR                      0
#define MISCREG_SMMU1_P2PM_SLV_TIMEOUT_PRESCALER_CFG_0_WORD_COUNT                       0x1
#define MISCREG_SMMU1_P2PM_SLV_TIMEOUT_PRESCALER_CFG_0_RESET_VAL                        _MK_MASK_CONST(0x8000000d)
#define MISCREG_SMMU1_P2PM_SLV_TIMEOUT_PRESCALER_CFG_0_RESET_MASK                       _MK_MASK_CONST(0x8000000f)
#define MISCREG_SMMU1_P2PM_SLV_TIMEOUT_PRESCALER_CFG_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define MISCREG_SMMU1_P2PM_SLV_TIMEOUT_PRESCALER_CFG_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define MISCREG_SMMU1_P2PM_SLV_TIMEOUT_PRESCALER_CFG_0_READ_MASK                        _MK_MASK_CONST(0x8000000f)
#define MISCREG_SMMU1_P2PM_SLV_TIMEOUT_PRESCALER_CFG_0_WRITE_MASK                       _MK_MASK_CONST(0x8000000f)
#define MISCREG_SMMU1_P2PM_SLV_TIMEOUT_PRESCALER_CFG_0_EXTREF_EN_SHIFT                  _MK_SHIFT_CONST(31)
#define MISCREG_SMMU1_P2PM_SLV_TIMEOUT_PRESCALER_CFG_0_EXTREF_EN_FIELD                  _MK_FIELD_CONST(0x1, MISCREG_SMMU1_P2PM_SLV_TIMEOUT_PRESCALER_CFG_0_EXTREF_EN_SHIFT)
#define MISCREG_SMMU1_P2PM_SLV_TIMEOUT_PRESCALER_CFG_0_EXTREF_EN_RANGE                  31:31
#define MISCREG_SMMU1_P2PM_SLV_TIMEOUT_PRESCALER_CFG_0_EXTREF_EN_WOFFSET                        0x0
#define MISCREG_SMMU1_P2PM_SLV_TIMEOUT_PRESCALER_CFG_0_EXTREF_EN_DEFAULT                        _MK_MASK_CONST(0x1)
#define MISCREG_SMMU1_P2PM_SLV_TIMEOUT_PRESCALER_CFG_0_EXTREF_EN_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define MISCREG_SMMU1_P2PM_SLV_TIMEOUT_PRESCALER_CFG_0_EXTREF_EN_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define MISCREG_SMMU1_P2PM_SLV_TIMEOUT_PRESCALER_CFG_0_EXTREF_EN_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define MISCREG_SMMU1_P2PM_SLV_TIMEOUT_PRESCALER_CFG_0_EXTREF_EN_PARITY_PROTECTION                      _MK_MASK_CONST(0x1)
#define MISCREG_SMMU1_P2PM_SLV_TIMEOUT_PRESCALER_CFG_0_EXTREF_EN_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define MISCREG_SMMU1_P2PM_SLV_TIMEOUT_PRESCALER_CFG_0_EXTREF_EN_DISABLE                        _MK_ENUM_CONST(0)
#define MISCREG_SMMU1_P2PM_SLV_TIMEOUT_PRESCALER_CFG_0_EXTREF_EN_ENABLE                 _MK_ENUM_CONST(1)

#define MISCREG_SMMU1_P2PM_SLV_TIMEOUT_PRESCALER_CFG_0_EXTREF_SRC_SHIFT                 _MK_SHIFT_CONST(0)
#define MISCREG_SMMU1_P2PM_SLV_TIMEOUT_PRESCALER_CFG_0_EXTREF_SRC_FIELD                 _MK_FIELD_CONST(0xf, MISCREG_SMMU1_P2PM_SLV_TIMEOUT_PRESCALER_CFG_0_EXTREF_SRC_SHIFT)
#define MISCREG_SMMU1_P2PM_SLV_TIMEOUT_PRESCALER_CFG_0_EXTREF_SRC_RANGE                 3:0
#define MISCREG_SMMU1_P2PM_SLV_TIMEOUT_PRESCALER_CFG_0_EXTREF_SRC_WOFFSET                       0x0
#define MISCREG_SMMU1_P2PM_SLV_TIMEOUT_PRESCALER_CFG_0_EXTREF_SRC_DEFAULT                       _MK_MASK_CONST(0xd)
#define MISCREG_SMMU1_P2PM_SLV_TIMEOUT_PRESCALER_CFG_0_EXTREF_SRC_DEFAULT_MASK                  _MK_MASK_CONST(0xf)
#define MISCREG_SMMU1_P2PM_SLV_TIMEOUT_PRESCALER_CFG_0_EXTREF_SRC_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define MISCREG_SMMU1_P2PM_SLV_TIMEOUT_PRESCALER_CFG_0_EXTREF_SRC_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define MISCREG_SMMU1_P2PM_SLV_TIMEOUT_PRESCALER_CFG_0_EXTREF_SRC_PARITY_PROTECTION                     _MK_MASK_CONST(0x1)
#define MISCREG_SMMU1_P2PM_SLV_TIMEOUT_PRESCALER_CFG_0_EXTREF_SRC_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)


// Register MISCREG_SMMU2_P2PM_SLV_TIMEOUT_PRESCALER_CFG_0
#define MISCREG_SMMU2_P2PM_SLV_TIMEOUT_PRESCALER_CFG_0                  _MK_ADDR_CONST(0x1328)
#define MISCREG_SMMU2_P2PM_SLV_TIMEOUT_PRESCALER_CFG_0_SECURE                   0x0
#define MISCREG_SMMU2_P2PM_SLV_TIMEOUT_PRESCALER_CFG_0_DUAL                     0x0
#define MISCREG_SMMU2_P2PM_SLV_TIMEOUT_PRESCALER_CFG_0_SCR                      0
#define MISCREG_SMMU2_P2PM_SLV_TIMEOUT_PRESCALER_CFG_0_WORD_COUNT                       0x1
#define MISCREG_SMMU2_P2PM_SLV_TIMEOUT_PRESCALER_CFG_0_RESET_VAL                        _MK_MASK_CONST(0x8000000d)
#define MISCREG_SMMU2_P2PM_SLV_TIMEOUT_PRESCALER_CFG_0_RESET_MASK                       _MK_MASK_CONST(0x8000000f)
#define MISCREG_SMMU2_P2PM_SLV_TIMEOUT_PRESCALER_CFG_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define MISCREG_SMMU2_P2PM_SLV_TIMEOUT_PRESCALER_CFG_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define MISCREG_SMMU2_P2PM_SLV_TIMEOUT_PRESCALER_CFG_0_READ_MASK                        _MK_MASK_CONST(0x8000000f)
#define MISCREG_SMMU2_P2PM_SLV_TIMEOUT_PRESCALER_CFG_0_WRITE_MASK                       _MK_MASK_CONST(0x8000000f)
#define MISCREG_SMMU2_P2PM_SLV_TIMEOUT_PRESCALER_CFG_0_EXTREF_EN_SHIFT                  _MK_SHIFT_CONST(31)
#define MISCREG_SMMU2_P2PM_SLV_TIMEOUT_PRESCALER_CFG_0_EXTREF_EN_FIELD                  _MK_FIELD_CONST(0x1, MISCREG_SMMU2_P2PM_SLV_TIMEOUT_PRESCALER_CFG_0_EXTREF_EN_SHIFT)
#define MISCREG_SMMU2_P2PM_SLV_TIMEOUT_PRESCALER_CFG_0_EXTREF_EN_RANGE                  31:31
#define MISCREG_SMMU2_P2PM_SLV_TIMEOUT_PRESCALER_CFG_0_EXTREF_EN_WOFFSET                        0x0
#define MISCREG_SMMU2_P2PM_SLV_TIMEOUT_PRESCALER_CFG_0_EXTREF_EN_DEFAULT                        _MK_MASK_CONST(0x1)
#define MISCREG_SMMU2_P2PM_SLV_TIMEOUT_PRESCALER_CFG_0_EXTREF_EN_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define MISCREG_SMMU2_P2PM_SLV_TIMEOUT_PRESCALER_CFG_0_EXTREF_EN_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define MISCREG_SMMU2_P2PM_SLV_TIMEOUT_PRESCALER_CFG_0_EXTREF_EN_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define MISCREG_SMMU2_P2PM_SLV_TIMEOUT_PRESCALER_CFG_0_EXTREF_EN_PARITY_PROTECTION                      _MK_MASK_CONST(0x1)
#define MISCREG_SMMU2_P2PM_SLV_TIMEOUT_PRESCALER_CFG_0_EXTREF_EN_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define MISCREG_SMMU2_P2PM_SLV_TIMEOUT_PRESCALER_CFG_0_EXTREF_EN_DISABLE                        _MK_ENUM_CONST(0)
#define MISCREG_SMMU2_P2PM_SLV_TIMEOUT_PRESCALER_CFG_0_EXTREF_EN_ENABLE                 _MK_ENUM_CONST(1)

#define MISCREG_SMMU2_P2PM_SLV_TIMEOUT_PRESCALER_CFG_0_EXTREF_SRC_SHIFT                 _MK_SHIFT_CONST(0)
#define MISCREG_SMMU2_P2PM_SLV_TIMEOUT_PRESCALER_CFG_0_EXTREF_SRC_FIELD                 _MK_FIELD_CONST(0xf, MISCREG_SMMU2_P2PM_SLV_TIMEOUT_PRESCALER_CFG_0_EXTREF_SRC_SHIFT)
#define MISCREG_SMMU2_P2PM_SLV_TIMEOUT_PRESCALER_CFG_0_EXTREF_SRC_RANGE                 3:0
#define MISCREG_SMMU2_P2PM_SLV_TIMEOUT_PRESCALER_CFG_0_EXTREF_SRC_WOFFSET                       0x0
#define MISCREG_SMMU2_P2PM_SLV_TIMEOUT_PRESCALER_CFG_0_EXTREF_SRC_DEFAULT                       _MK_MASK_CONST(0xd)
#define MISCREG_SMMU2_P2PM_SLV_TIMEOUT_PRESCALER_CFG_0_EXTREF_SRC_DEFAULT_MASK                  _MK_MASK_CONST(0xf)
#define MISCREG_SMMU2_P2PM_SLV_TIMEOUT_PRESCALER_CFG_0_EXTREF_SRC_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define MISCREG_SMMU2_P2PM_SLV_TIMEOUT_PRESCALER_CFG_0_EXTREF_SRC_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define MISCREG_SMMU2_P2PM_SLV_TIMEOUT_PRESCALER_CFG_0_EXTREF_SRC_PARITY_PROTECTION                     _MK_MASK_CONST(0x1)
#define MISCREG_SMMU2_P2PM_SLV_TIMEOUT_PRESCALER_CFG_0_EXTREF_SRC_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)


// Register MISCREG_STM_P2PM_SLV_TIMEOUT_PRESCALER_CFG_0
#define MISCREG_STM_P2PM_SLV_TIMEOUT_PRESCALER_CFG_0                    _MK_ADDR_CONST(0x132c)
#define MISCREG_STM_P2PM_SLV_TIMEOUT_PRESCALER_CFG_0_SECURE                     0x0
#define MISCREG_STM_P2PM_SLV_TIMEOUT_PRESCALER_CFG_0_DUAL                       0x0
#define MISCREG_STM_P2PM_SLV_TIMEOUT_PRESCALER_CFG_0_SCR                        0
#define MISCREG_STM_P2PM_SLV_TIMEOUT_PRESCALER_CFG_0_WORD_COUNT                         0x1
#define MISCREG_STM_P2PM_SLV_TIMEOUT_PRESCALER_CFG_0_RESET_VAL                  _MK_MASK_CONST(0x8000000d)
#define MISCREG_STM_P2PM_SLV_TIMEOUT_PRESCALER_CFG_0_RESET_MASK                         _MK_MASK_CONST(0x8000000f)
#define MISCREG_STM_P2PM_SLV_TIMEOUT_PRESCALER_CFG_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define MISCREG_STM_P2PM_SLV_TIMEOUT_PRESCALER_CFG_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define MISCREG_STM_P2PM_SLV_TIMEOUT_PRESCALER_CFG_0_READ_MASK                  _MK_MASK_CONST(0x8000000f)
#define MISCREG_STM_P2PM_SLV_TIMEOUT_PRESCALER_CFG_0_WRITE_MASK                         _MK_MASK_CONST(0x8000000f)
#define MISCREG_STM_P2PM_SLV_TIMEOUT_PRESCALER_CFG_0_EXTREF_EN_SHIFT                    _MK_SHIFT_CONST(31)
#define MISCREG_STM_P2PM_SLV_TIMEOUT_PRESCALER_CFG_0_EXTREF_EN_FIELD                    _MK_FIELD_CONST(0x1, MISCREG_STM_P2PM_SLV_TIMEOUT_PRESCALER_CFG_0_EXTREF_EN_SHIFT)
#define MISCREG_STM_P2PM_SLV_TIMEOUT_PRESCALER_CFG_0_EXTREF_EN_RANGE                    31:31
#define MISCREG_STM_P2PM_SLV_TIMEOUT_PRESCALER_CFG_0_EXTREF_EN_WOFFSET                  0x0
#define MISCREG_STM_P2PM_SLV_TIMEOUT_PRESCALER_CFG_0_EXTREF_EN_DEFAULT                  _MK_MASK_CONST(0x1)
#define MISCREG_STM_P2PM_SLV_TIMEOUT_PRESCALER_CFG_0_EXTREF_EN_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define MISCREG_STM_P2PM_SLV_TIMEOUT_PRESCALER_CFG_0_EXTREF_EN_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define MISCREG_STM_P2PM_SLV_TIMEOUT_PRESCALER_CFG_0_EXTREF_EN_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define MISCREG_STM_P2PM_SLV_TIMEOUT_PRESCALER_CFG_0_EXTREF_EN_PARITY_PROTECTION                        _MK_MASK_CONST(0x1)
#define MISCREG_STM_P2PM_SLV_TIMEOUT_PRESCALER_CFG_0_EXTREF_EN_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)
#define MISCREG_STM_P2PM_SLV_TIMEOUT_PRESCALER_CFG_0_EXTREF_EN_DISABLE                  _MK_ENUM_CONST(0)
#define MISCREG_STM_P2PM_SLV_TIMEOUT_PRESCALER_CFG_0_EXTREF_EN_ENABLE                   _MK_ENUM_CONST(1)

#define MISCREG_STM_P2PM_SLV_TIMEOUT_PRESCALER_CFG_0_EXTREF_SRC_SHIFT                   _MK_SHIFT_CONST(0)
#define MISCREG_STM_P2PM_SLV_TIMEOUT_PRESCALER_CFG_0_EXTREF_SRC_FIELD                   _MK_FIELD_CONST(0xf, MISCREG_STM_P2PM_SLV_TIMEOUT_PRESCALER_CFG_0_EXTREF_SRC_SHIFT)
#define MISCREG_STM_P2PM_SLV_TIMEOUT_PRESCALER_CFG_0_EXTREF_SRC_RANGE                   3:0
#define MISCREG_STM_P2PM_SLV_TIMEOUT_PRESCALER_CFG_0_EXTREF_SRC_WOFFSET                 0x0
#define MISCREG_STM_P2PM_SLV_TIMEOUT_PRESCALER_CFG_0_EXTREF_SRC_DEFAULT                 _MK_MASK_CONST(0xd)
#define MISCREG_STM_P2PM_SLV_TIMEOUT_PRESCALER_CFG_0_EXTREF_SRC_DEFAULT_MASK                    _MK_MASK_CONST(0xf)
#define MISCREG_STM_P2PM_SLV_TIMEOUT_PRESCALER_CFG_0_EXTREF_SRC_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define MISCREG_STM_P2PM_SLV_TIMEOUT_PRESCALER_CFG_0_EXTREF_SRC_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define MISCREG_STM_P2PM_SLV_TIMEOUT_PRESCALER_CFG_0_EXTREF_SRC_PARITY_PROTECTION                       _MK_MASK_CONST(0x1)
#define MISCREG_STM_P2PM_SLV_TIMEOUT_PRESCALER_CFG_0_EXTREF_SRC_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)


// Register MISCREG_SVC_SLV_TIMEOUT_PRESCALER_CFG_0
#define MISCREG_SVC_SLV_TIMEOUT_PRESCALER_CFG_0                 _MK_ADDR_CONST(0x1330)
#define MISCREG_SVC_SLV_TIMEOUT_PRESCALER_CFG_0_SECURE                  0x0
#define MISCREG_SVC_SLV_TIMEOUT_PRESCALER_CFG_0_DUAL                    0x0
#define MISCREG_SVC_SLV_TIMEOUT_PRESCALER_CFG_0_SCR                     0
#define MISCREG_SVC_SLV_TIMEOUT_PRESCALER_CFG_0_WORD_COUNT                      0x1
#define MISCREG_SVC_SLV_TIMEOUT_PRESCALER_CFG_0_RESET_VAL                       _MK_MASK_CONST(0x8000000d)
#define MISCREG_SVC_SLV_TIMEOUT_PRESCALER_CFG_0_RESET_MASK                      _MK_MASK_CONST(0x8000000f)
#define MISCREG_SVC_SLV_TIMEOUT_PRESCALER_CFG_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define MISCREG_SVC_SLV_TIMEOUT_PRESCALER_CFG_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define MISCREG_SVC_SLV_TIMEOUT_PRESCALER_CFG_0_READ_MASK                       _MK_MASK_CONST(0x8000000f)
#define MISCREG_SVC_SLV_TIMEOUT_PRESCALER_CFG_0_WRITE_MASK                      _MK_MASK_CONST(0x8000000f)
#define MISCREG_SVC_SLV_TIMEOUT_PRESCALER_CFG_0_EXTREF_EN_SHIFT                 _MK_SHIFT_CONST(31)
#define MISCREG_SVC_SLV_TIMEOUT_PRESCALER_CFG_0_EXTREF_EN_FIELD                 _MK_FIELD_CONST(0x1, MISCREG_SVC_SLV_TIMEOUT_PRESCALER_CFG_0_EXTREF_EN_SHIFT)
#define MISCREG_SVC_SLV_TIMEOUT_PRESCALER_CFG_0_EXTREF_EN_RANGE                 31:31
#define MISCREG_SVC_SLV_TIMEOUT_PRESCALER_CFG_0_EXTREF_EN_WOFFSET                       0x0
#define MISCREG_SVC_SLV_TIMEOUT_PRESCALER_CFG_0_EXTREF_EN_DEFAULT                       _MK_MASK_CONST(0x1)
#define MISCREG_SVC_SLV_TIMEOUT_PRESCALER_CFG_0_EXTREF_EN_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define MISCREG_SVC_SLV_TIMEOUT_PRESCALER_CFG_0_EXTREF_EN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define MISCREG_SVC_SLV_TIMEOUT_PRESCALER_CFG_0_EXTREF_EN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define MISCREG_SVC_SLV_TIMEOUT_PRESCALER_CFG_0_EXTREF_EN_PARITY_PROTECTION                     _MK_MASK_CONST(0x1)
#define MISCREG_SVC_SLV_TIMEOUT_PRESCALER_CFG_0_EXTREF_EN_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)
#define MISCREG_SVC_SLV_TIMEOUT_PRESCALER_CFG_0_EXTREF_EN_DISABLE                       _MK_ENUM_CONST(0)
#define MISCREG_SVC_SLV_TIMEOUT_PRESCALER_CFG_0_EXTREF_EN_ENABLE                        _MK_ENUM_CONST(1)

#define MISCREG_SVC_SLV_TIMEOUT_PRESCALER_CFG_0_EXTREF_SRC_SHIFT                        _MK_SHIFT_CONST(0)
#define MISCREG_SVC_SLV_TIMEOUT_PRESCALER_CFG_0_EXTREF_SRC_FIELD                        _MK_FIELD_CONST(0xf, MISCREG_SVC_SLV_TIMEOUT_PRESCALER_CFG_0_EXTREF_SRC_SHIFT)
#define MISCREG_SVC_SLV_TIMEOUT_PRESCALER_CFG_0_EXTREF_SRC_RANGE                        3:0
#define MISCREG_SVC_SLV_TIMEOUT_PRESCALER_CFG_0_EXTREF_SRC_WOFFSET                      0x0
#define MISCREG_SVC_SLV_TIMEOUT_PRESCALER_CFG_0_EXTREF_SRC_DEFAULT                      _MK_MASK_CONST(0xd)
#define MISCREG_SVC_SLV_TIMEOUT_PRESCALER_CFG_0_EXTREF_SRC_DEFAULT_MASK                 _MK_MASK_CONST(0xf)
#define MISCREG_SVC_SLV_TIMEOUT_PRESCALER_CFG_0_EXTREF_SRC_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define MISCREG_SVC_SLV_TIMEOUT_PRESCALER_CFG_0_EXTREF_SRC_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define MISCREG_SVC_SLV_TIMEOUT_PRESCALER_CFG_0_EXTREF_SRC_PARITY_PROTECTION                    _MK_MASK_CONST(0x1)
#define MISCREG_SVC_SLV_TIMEOUT_PRESCALER_CFG_0_EXTREF_SRC_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)


// Register MISCREG_CBB_FIREWALL_SLV_TIMEOUT_PRESCALER_CFG_0
#define MISCREG_CBB_FIREWALL_SLV_TIMEOUT_PRESCALER_CFG_0                        _MK_ADDR_CONST(0x1334)
#define MISCREG_CBB_FIREWALL_SLV_TIMEOUT_PRESCALER_CFG_0_SECURE                         0x0
#define MISCREG_CBB_FIREWALL_SLV_TIMEOUT_PRESCALER_CFG_0_DUAL                   0x0
#define MISCREG_CBB_FIREWALL_SLV_TIMEOUT_PRESCALER_CFG_0_SCR                    0
#define MISCREG_CBB_FIREWALL_SLV_TIMEOUT_PRESCALER_CFG_0_WORD_COUNT                     0x1
#define MISCREG_CBB_FIREWALL_SLV_TIMEOUT_PRESCALER_CFG_0_RESET_VAL                      _MK_MASK_CONST(0x8000000d)
#define MISCREG_CBB_FIREWALL_SLV_TIMEOUT_PRESCALER_CFG_0_RESET_MASK                     _MK_MASK_CONST(0x8000000f)
#define MISCREG_CBB_FIREWALL_SLV_TIMEOUT_PRESCALER_CFG_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define MISCREG_CBB_FIREWALL_SLV_TIMEOUT_PRESCALER_CFG_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define MISCREG_CBB_FIREWALL_SLV_TIMEOUT_PRESCALER_CFG_0_READ_MASK                      _MK_MASK_CONST(0x8000000f)
#define MISCREG_CBB_FIREWALL_SLV_TIMEOUT_PRESCALER_CFG_0_WRITE_MASK                     _MK_MASK_CONST(0x8000000f)
#define MISCREG_CBB_FIREWALL_SLV_TIMEOUT_PRESCALER_CFG_0_EXTREF_EN_SHIFT                        _MK_SHIFT_CONST(31)
#define MISCREG_CBB_FIREWALL_SLV_TIMEOUT_PRESCALER_CFG_0_EXTREF_EN_FIELD                        _MK_FIELD_CONST(0x1, MISCREG_CBB_FIREWALL_SLV_TIMEOUT_PRESCALER_CFG_0_EXTREF_EN_SHIFT)
#define MISCREG_CBB_FIREWALL_SLV_TIMEOUT_PRESCALER_CFG_0_EXTREF_EN_RANGE                        31:31
#define MISCREG_CBB_FIREWALL_SLV_TIMEOUT_PRESCALER_CFG_0_EXTREF_EN_WOFFSET                      0x0
#define MISCREG_CBB_FIREWALL_SLV_TIMEOUT_PRESCALER_CFG_0_EXTREF_EN_DEFAULT                      _MK_MASK_CONST(0x1)
#define MISCREG_CBB_FIREWALL_SLV_TIMEOUT_PRESCALER_CFG_0_EXTREF_EN_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define MISCREG_CBB_FIREWALL_SLV_TIMEOUT_PRESCALER_CFG_0_EXTREF_EN_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define MISCREG_CBB_FIREWALL_SLV_TIMEOUT_PRESCALER_CFG_0_EXTREF_EN_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define MISCREG_CBB_FIREWALL_SLV_TIMEOUT_PRESCALER_CFG_0_EXTREF_EN_PARITY_PROTECTION                    _MK_MASK_CONST(0x1)
#define MISCREG_CBB_FIREWALL_SLV_TIMEOUT_PRESCALER_CFG_0_EXTREF_EN_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)
#define MISCREG_CBB_FIREWALL_SLV_TIMEOUT_PRESCALER_CFG_0_EXTREF_EN_DISABLE                      _MK_ENUM_CONST(0)
#define MISCREG_CBB_FIREWALL_SLV_TIMEOUT_PRESCALER_CFG_0_EXTREF_EN_ENABLE                       _MK_ENUM_CONST(1)

#define MISCREG_CBB_FIREWALL_SLV_TIMEOUT_PRESCALER_CFG_0_EXTREF_SRC_SHIFT                       _MK_SHIFT_CONST(0)
#define MISCREG_CBB_FIREWALL_SLV_TIMEOUT_PRESCALER_CFG_0_EXTREF_SRC_FIELD                       _MK_FIELD_CONST(0xf, MISCREG_CBB_FIREWALL_SLV_TIMEOUT_PRESCALER_CFG_0_EXTREF_SRC_SHIFT)
#define MISCREG_CBB_FIREWALL_SLV_TIMEOUT_PRESCALER_CFG_0_EXTREF_SRC_RANGE                       3:0
#define MISCREG_CBB_FIREWALL_SLV_TIMEOUT_PRESCALER_CFG_0_EXTREF_SRC_WOFFSET                     0x0
#define MISCREG_CBB_FIREWALL_SLV_TIMEOUT_PRESCALER_CFG_0_EXTREF_SRC_DEFAULT                     _MK_MASK_CONST(0xd)
#define MISCREG_CBB_FIREWALL_SLV_TIMEOUT_PRESCALER_CFG_0_EXTREF_SRC_DEFAULT_MASK                        _MK_MASK_CONST(0xf)
#define MISCREG_CBB_FIREWALL_SLV_TIMEOUT_PRESCALER_CFG_0_EXTREF_SRC_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define MISCREG_CBB_FIREWALL_SLV_TIMEOUT_PRESCALER_CFG_0_EXTREF_SRC_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define MISCREG_CBB_FIREWALL_SLV_TIMEOUT_PRESCALER_CFG_0_EXTREF_SRC_PARITY_PROTECTION                   _MK_MASK_CONST(0x1)
#define MISCREG_CBB_FIREWALL_SLV_TIMEOUT_PRESCALER_CFG_0_EXTREF_SRC_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)


// Reserved address 0x1338

// Reserved address 0x133c

// Reserved address 0x1340

// Reserved address 0x1344

// Reserved address 0x1348

// Reserved address 0x134c

// Reserved address 0x1350

// Reserved address 0x1354

// Reserved address 0x1358

// Reserved address 0x135c

// Reserved address 0x1360

// Reserved address 0x1364

// Reserved address 0x1368

// Reserved address 0x136c

// Reserved address 0x1370

// Reserved address 0x1374

// Reserved address 0x1378

// Reserved address 0x137c

// Reserved address 0x1380

// Reserved address 0x1384

// Reserved address 0x1388

// Reserved address 0x138c

// Reserved address 0x1390

// Reserved address 0x1394

// Reserved address 0x1398

// Reserved address 0x139c

// Reserved address 0x13a0

// Reserved address 0x13a4

// Reserved address 0x13a8

// Reserved address 0x13ac

// Reserved address 0x13b0

// Reserved address 0x13b4

// Register MISCREG_TOP_HSP_LOCKSTEP_CLK_ENABLE_0
#define MISCREG_TOP_HSP_LOCKSTEP_CLK_ENABLE_0                   _MK_ADDR_CONST(0x13b8)
#define MISCREG_TOP_HSP_LOCKSTEP_CLK_ENABLE_0_SECURE                    0x0
#define MISCREG_TOP_HSP_LOCKSTEP_CLK_ENABLE_0_DUAL                      0x0
#define MISCREG_TOP_HSP_LOCKSTEP_CLK_ENABLE_0_SCR                       0
#define MISCREG_TOP_HSP_LOCKSTEP_CLK_ENABLE_0_WORD_COUNT                        0x1
#define MISCREG_TOP_HSP_LOCKSTEP_CLK_ENABLE_0_RESET_VAL                         _MK_MASK_CONST(0x1)
#define MISCREG_TOP_HSP_LOCKSTEP_CLK_ENABLE_0_RESET_MASK                        _MK_MASK_CONST(0x3)
#define MISCREG_TOP_HSP_LOCKSTEP_CLK_ENABLE_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define MISCREG_TOP_HSP_LOCKSTEP_CLK_ENABLE_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define MISCREG_TOP_HSP_LOCKSTEP_CLK_ENABLE_0_READ_MASK                         _MK_MASK_CONST(0x3)
#define MISCREG_TOP_HSP_LOCKSTEP_CLK_ENABLE_0_WRITE_MASK                        _MK_MASK_CONST(0x3)
#define MISCREG_TOP_HSP_LOCKSTEP_CLK_ENABLE_0_ENABLE_SHIFT                      _MK_SHIFT_CONST(0)
#define MISCREG_TOP_HSP_LOCKSTEP_CLK_ENABLE_0_ENABLE_FIELD                      _MK_FIELD_CONST(0x3, MISCREG_TOP_HSP_LOCKSTEP_CLK_ENABLE_0_ENABLE_SHIFT)
#define MISCREG_TOP_HSP_LOCKSTEP_CLK_ENABLE_0_ENABLE_RANGE                      1:0
#define MISCREG_TOP_HSP_LOCKSTEP_CLK_ENABLE_0_ENABLE_WOFFSET                    0x0
#define MISCREG_TOP_HSP_LOCKSTEP_CLK_ENABLE_0_ENABLE_DEFAULT                    _MK_MASK_CONST(0x1)
#define MISCREG_TOP_HSP_LOCKSTEP_CLK_ENABLE_0_ENABLE_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
#define MISCREG_TOP_HSP_LOCKSTEP_CLK_ENABLE_0_ENABLE_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define MISCREG_TOP_HSP_LOCKSTEP_CLK_ENABLE_0_ENABLE_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define MISCREG_TOP_HSP_LOCKSTEP_CLK_ENABLE_0_ENABLE_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define MISCREG_TOP_HSP_LOCKSTEP_CLK_ENABLE_0_ENABLE_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define MISCREG_TOP_HSP_LOCKSTEP_CLK_ENABLE_0_ENABLE_INIT_ENUM                  ENABLE
#define MISCREG_TOP_HSP_LOCKSTEP_CLK_ENABLE_0_ENABLE_RSVD0                      _MK_ENUM_CONST(0)
#define MISCREG_TOP_HSP_LOCKSTEP_CLK_ENABLE_0_ENABLE_ENABLE                     _MK_ENUM_CONST(1)
#define MISCREG_TOP_HSP_LOCKSTEP_CLK_ENABLE_0_ENABLE_DISABLE                    _MK_ENUM_CONST(2)
#define MISCREG_TOP_HSP_LOCKSTEP_CLK_ENABLE_0_ENABLE_RSVD1                      _MK_ENUM_CONST(3)


// Register MISCREG_AXIS_CENTRAL_PENDING_TRANS_0
#define MISCREG_AXIS_CENTRAL_PENDING_TRANS_0                    _MK_ADDR_CONST(0x13bc)
#define MISCREG_AXIS_CENTRAL_PENDING_TRANS_0_SECURE                     0x0
#define MISCREG_AXIS_CENTRAL_PENDING_TRANS_0_DUAL                       0x0
#define MISCREG_AXIS_CENTRAL_PENDING_TRANS_0_SCR                        0
#define MISCREG_AXIS_CENTRAL_PENDING_TRANS_0_WORD_COUNT                         0x1
#define MISCREG_AXIS_CENTRAL_PENDING_TRANS_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define MISCREG_AXIS_CENTRAL_PENDING_TRANS_0_RESET_MASK                         _MK_MASK_CONST(0x3fff)
#define MISCREG_AXIS_CENTRAL_PENDING_TRANS_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define MISCREG_AXIS_CENTRAL_PENDING_TRANS_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define MISCREG_AXIS_CENTRAL_PENDING_TRANS_0_READ_MASK                  _MK_MASK_CONST(0x3fff)
#define MISCREG_AXIS_CENTRAL_PENDING_TRANS_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
#define MISCREG_AXIS_CENTRAL_PENDING_TRANS_0_SVC_SHIFT                  _MK_SHIFT_CONST(0)
#define MISCREG_AXIS_CENTRAL_PENDING_TRANS_0_SVC_FIELD                  _MK_FIELD_CONST(0x1, MISCREG_AXIS_CENTRAL_PENDING_TRANS_0_SVC_SHIFT)
#define MISCREG_AXIS_CENTRAL_PENDING_TRANS_0_SVC_RANGE                  0:0
#define MISCREG_AXIS_CENTRAL_PENDING_TRANS_0_SVC_WOFFSET                        0x0
#define MISCREG_AXIS_CENTRAL_PENDING_TRANS_0_SVC_DEFAULT                        _MK_MASK_CONST(0x0)
#define MISCREG_AXIS_CENTRAL_PENDING_TRANS_0_SVC_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define MISCREG_AXIS_CENTRAL_PENDING_TRANS_0_SVC_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define MISCREG_AXIS_CENTRAL_PENDING_TRANS_0_SVC_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define MISCREG_AXIS_CENTRAL_PENDING_TRANS_0_SVC_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define MISCREG_AXIS_CENTRAL_PENDING_TRANS_0_SVC_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)

#define MISCREG_AXIS_CENTRAL_PENDING_TRANS_0_AON_P2PS_SHIFT                     _MK_SHIFT_CONST(1)
#define MISCREG_AXIS_CENTRAL_PENDING_TRANS_0_AON_P2PS_FIELD                     _MK_FIELD_CONST(0x1, MISCREG_AXIS_CENTRAL_PENDING_TRANS_0_AON_P2PS_SHIFT)
#define MISCREG_AXIS_CENTRAL_PENDING_TRANS_0_AON_P2PS_RANGE                     1:1
#define MISCREG_AXIS_CENTRAL_PENDING_TRANS_0_AON_P2PS_WOFFSET                   0x0
#define MISCREG_AXIS_CENTRAL_PENDING_TRANS_0_AON_P2PS_DEFAULT                   _MK_MASK_CONST(0x0)
#define MISCREG_AXIS_CENTRAL_PENDING_TRANS_0_AON_P2PS_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define MISCREG_AXIS_CENTRAL_PENDING_TRANS_0_AON_P2PS_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define MISCREG_AXIS_CENTRAL_PENDING_TRANS_0_AON_P2PS_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define MISCREG_AXIS_CENTRAL_PENDING_TRANS_0_AON_P2PS_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define MISCREG_AXIS_CENTRAL_PENDING_TRANS_0_AON_P2PS_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)

#define MISCREG_AXIS_CENTRAL_PENDING_TRANS_0_APE_P2PS_SHIFT                     _MK_SHIFT_CONST(2)
#define MISCREG_AXIS_CENTRAL_PENDING_TRANS_0_APE_P2PS_FIELD                     _MK_FIELD_CONST(0x1, MISCREG_AXIS_CENTRAL_PENDING_TRANS_0_APE_P2PS_SHIFT)
#define MISCREG_AXIS_CENTRAL_PENDING_TRANS_0_APE_P2PS_RANGE                     2:2
#define MISCREG_AXIS_CENTRAL_PENDING_TRANS_0_APE_P2PS_WOFFSET                   0x0
#define MISCREG_AXIS_CENTRAL_PENDING_TRANS_0_APE_P2PS_DEFAULT                   _MK_MASK_CONST(0x0)
#define MISCREG_AXIS_CENTRAL_PENDING_TRANS_0_APE_P2PS_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define MISCREG_AXIS_CENTRAL_PENDING_TRANS_0_APE_P2PS_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define MISCREG_AXIS_CENTRAL_PENDING_TRANS_0_APE_P2PS_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define MISCREG_AXIS_CENTRAL_PENDING_TRANS_0_APE_P2PS_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define MISCREG_AXIS_CENTRAL_PENDING_TRANS_0_APE_P2PS_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)

#define MISCREG_AXIS_CENTRAL_PENDING_TRANS_0_BPMP_P2PS_SHIFT                    _MK_SHIFT_CONST(3)
#define MISCREG_AXIS_CENTRAL_PENDING_TRANS_0_BPMP_P2PS_FIELD                    _MK_FIELD_CONST(0x1, MISCREG_AXIS_CENTRAL_PENDING_TRANS_0_BPMP_P2PS_SHIFT)
#define MISCREG_AXIS_CENTRAL_PENDING_TRANS_0_BPMP_P2PS_RANGE                    3:3
#define MISCREG_AXIS_CENTRAL_PENDING_TRANS_0_BPMP_P2PS_WOFFSET                  0x0
#define MISCREG_AXIS_CENTRAL_PENDING_TRANS_0_BPMP_P2PS_DEFAULT                  _MK_MASK_CONST(0x0)
#define MISCREG_AXIS_CENTRAL_PENDING_TRANS_0_BPMP_P2PS_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define MISCREG_AXIS_CENTRAL_PENDING_TRANS_0_BPMP_P2PS_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define MISCREG_AXIS_CENTRAL_PENDING_TRANS_0_BPMP_P2PS_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define MISCREG_AXIS_CENTRAL_PENDING_TRANS_0_BPMP_P2PS_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define MISCREG_AXIS_CENTRAL_PENDING_TRANS_0_BPMP_P2PS_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)

#define MISCREG_AXIS_CENTRAL_PENDING_TRANS_0_CCROC_P2PS_SHIFT                   _MK_SHIFT_CONST(4)
#define MISCREG_AXIS_CENTRAL_PENDING_TRANS_0_CCROC_P2PS_FIELD                   _MK_FIELD_CONST(0x1, MISCREG_AXIS_CENTRAL_PENDING_TRANS_0_CCROC_P2PS_SHIFT)
#define MISCREG_AXIS_CENTRAL_PENDING_TRANS_0_CCROC_P2PS_RANGE                   4:4
#define MISCREG_AXIS_CENTRAL_PENDING_TRANS_0_CCROC_P2PS_WOFFSET                 0x0
#define MISCREG_AXIS_CENTRAL_PENDING_TRANS_0_CCROC_P2PS_DEFAULT                 _MK_MASK_CONST(0x0)
#define MISCREG_AXIS_CENTRAL_PENDING_TRANS_0_CCROC_P2PS_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define MISCREG_AXIS_CENTRAL_PENDING_TRANS_0_CCROC_P2PS_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define MISCREG_AXIS_CENTRAL_PENDING_TRANS_0_CCROC_P2PS_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define MISCREG_AXIS_CENTRAL_PENDING_TRANS_0_CCROC_P2PS_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define MISCREG_AXIS_CENTRAL_PENDING_TRANS_0_CCROC_P2PS_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define MISCREG_AXIS_CENTRAL_PENDING_TRANS_0_CSITE_P2PS_SHIFT                   _MK_SHIFT_CONST(5)
#define MISCREG_AXIS_CENTRAL_PENDING_TRANS_0_CSITE_P2PS_FIELD                   _MK_FIELD_CONST(0x1, MISCREG_AXIS_CENTRAL_PENDING_TRANS_0_CSITE_P2PS_SHIFT)
#define MISCREG_AXIS_CENTRAL_PENDING_TRANS_0_CSITE_P2PS_RANGE                   5:5
#define MISCREG_AXIS_CENTRAL_PENDING_TRANS_0_CSITE_P2PS_WOFFSET                 0x0
#define MISCREG_AXIS_CENTRAL_PENDING_TRANS_0_CSITE_P2PS_DEFAULT                 _MK_MASK_CONST(0x0)
#define MISCREG_AXIS_CENTRAL_PENDING_TRANS_0_CSITE_P2PS_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define MISCREG_AXIS_CENTRAL_PENDING_TRANS_0_CSITE_P2PS_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define MISCREG_AXIS_CENTRAL_PENDING_TRANS_0_CSITE_P2PS_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define MISCREG_AXIS_CENTRAL_PENDING_TRANS_0_CSITE_P2PS_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define MISCREG_AXIS_CENTRAL_PENDING_TRANS_0_CSITE_P2PS_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define MISCREG_AXIS_CENTRAL_PENDING_TRANS_0_GPCDMA_MMIO_P2PS_SHIFT                     _MK_SHIFT_CONST(6)
#define MISCREG_AXIS_CENTRAL_PENDING_TRANS_0_GPCDMA_MMIO_P2PS_FIELD                     _MK_FIELD_CONST(0x1, MISCREG_AXIS_CENTRAL_PENDING_TRANS_0_GPCDMA_MMIO_P2PS_SHIFT)
#define MISCREG_AXIS_CENTRAL_PENDING_TRANS_0_GPCDMA_MMIO_P2PS_RANGE                     6:6
#define MISCREG_AXIS_CENTRAL_PENDING_TRANS_0_GPCDMA_MMIO_P2PS_WOFFSET                   0x0
#define MISCREG_AXIS_CENTRAL_PENDING_TRANS_0_GPCDMA_MMIO_P2PS_DEFAULT                   _MK_MASK_CONST(0x0)
#define MISCREG_AXIS_CENTRAL_PENDING_TRANS_0_GPCDMA_MMIO_P2PS_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define MISCREG_AXIS_CENTRAL_PENDING_TRANS_0_GPCDMA_MMIO_P2PS_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define MISCREG_AXIS_CENTRAL_PENDING_TRANS_0_GPCDMA_MMIO_P2PS_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define MISCREG_AXIS_CENTRAL_PENDING_TRANS_0_GPCDMA_MMIO_P2PS_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define MISCREG_AXIS_CENTRAL_PENDING_TRANS_0_GPCDMA_MMIO_P2PS_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)

#define MISCREG_AXIS_CENTRAL_PENDING_TRANS_0_JTAG_P2PS_SHIFT                    _MK_SHIFT_CONST(7)
#define MISCREG_AXIS_CENTRAL_PENDING_TRANS_0_JTAG_P2PS_FIELD                    _MK_FIELD_CONST(0x1, MISCREG_AXIS_CENTRAL_PENDING_TRANS_0_JTAG_P2PS_SHIFT)
#define MISCREG_AXIS_CENTRAL_PENDING_TRANS_0_JTAG_P2PS_RANGE                    7:7
#define MISCREG_AXIS_CENTRAL_PENDING_TRANS_0_JTAG_P2PS_WOFFSET                  0x0
#define MISCREG_AXIS_CENTRAL_PENDING_TRANS_0_JTAG_P2PS_DEFAULT                  _MK_MASK_CONST(0x0)
#define MISCREG_AXIS_CENTRAL_PENDING_TRANS_0_JTAG_P2PS_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define MISCREG_AXIS_CENTRAL_PENDING_TRANS_0_JTAG_P2PS_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define MISCREG_AXIS_CENTRAL_PENDING_TRANS_0_JTAG_P2PS_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define MISCREG_AXIS_CENTRAL_PENDING_TRANS_0_JTAG_P2PS_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define MISCREG_AXIS_CENTRAL_PENDING_TRANS_0_JTAG_P2PS_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)

#define MISCREG_AXIS_CENTRAL_PENDING_TRANS_0_NVDEC1_P2PS_SHIFT                  _MK_SHIFT_CONST(8)
#define MISCREG_AXIS_CENTRAL_PENDING_TRANS_0_NVDEC1_P2PS_FIELD                  _MK_FIELD_CONST(0x1, MISCREG_AXIS_CENTRAL_PENDING_TRANS_0_NVDEC1_P2PS_SHIFT)
#define MISCREG_AXIS_CENTRAL_PENDING_TRANS_0_NVDEC1_P2PS_RANGE                  8:8
#define MISCREG_AXIS_CENTRAL_PENDING_TRANS_0_NVDEC1_P2PS_WOFFSET                        0x0
#define MISCREG_AXIS_CENTRAL_PENDING_TRANS_0_NVDEC1_P2PS_DEFAULT                        _MK_MASK_CONST(0x0)
#define MISCREG_AXIS_CENTRAL_PENDING_TRANS_0_NVDEC1_P2PS_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define MISCREG_AXIS_CENTRAL_PENDING_TRANS_0_NVDEC1_P2PS_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define MISCREG_AXIS_CENTRAL_PENDING_TRANS_0_NVDEC1_P2PS_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define MISCREG_AXIS_CENTRAL_PENDING_TRANS_0_NVDEC1_P2PS_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define MISCREG_AXIS_CENTRAL_PENDING_TRANS_0_NVDEC1_P2PS_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)

#define MISCREG_AXIS_CENTRAL_PENDING_TRANS_0_NVDEC_P2PS_SHIFT                   _MK_SHIFT_CONST(9)
#define MISCREG_AXIS_CENTRAL_PENDING_TRANS_0_NVDEC_P2PS_FIELD                   _MK_FIELD_CONST(0x1, MISCREG_AXIS_CENTRAL_PENDING_TRANS_0_NVDEC_P2PS_SHIFT)
#define MISCREG_AXIS_CENTRAL_PENDING_TRANS_0_NVDEC_P2PS_RANGE                   9:9
#define MISCREG_AXIS_CENTRAL_PENDING_TRANS_0_NVDEC_P2PS_WOFFSET                 0x0
#define MISCREG_AXIS_CENTRAL_PENDING_TRANS_0_NVDEC_P2PS_DEFAULT                 _MK_MASK_CONST(0x0)
#define MISCREG_AXIS_CENTRAL_PENDING_TRANS_0_NVDEC_P2PS_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define MISCREG_AXIS_CENTRAL_PENDING_TRANS_0_NVDEC_P2PS_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define MISCREG_AXIS_CENTRAL_PENDING_TRANS_0_NVDEC_P2PS_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define MISCREG_AXIS_CENTRAL_PENDING_TRANS_0_NVDEC_P2PS_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define MISCREG_AXIS_CENTRAL_PENDING_TRANS_0_NVDEC_P2PS_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define MISCREG_AXIS_CENTRAL_PENDING_TRANS_0_RCE_P2PS_SHIFT                     _MK_SHIFT_CONST(10)
#define MISCREG_AXIS_CENTRAL_PENDING_TRANS_0_RCE_P2PS_FIELD                     _MK_FIELD_CONST(0x1, MISCREG_AXIS_CENTRAL_PENDING_TRANS_0_RCE_P2PS_SHIFT)
#define MISCREG_AXIS_CENTRAL_PENDING_TRANS_0_RCE_P2PS_RANGE                     10:10
#define MISCREG_AXIS_CENTRAL_PENDING_TRANS_0_RCE_P2PS_WOFFSET                   0x0
#define MISCREG_AXIS_CENTRAL_PENDING_TRANS_0_RCE_P2PS_DEFAULT                   _MK_MASK_CONST(0x0)
#define MISCREG_AXIS_CENTRAL_PENDING_TRANS_0_RCE_P2PS_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define MISCREG_AXIS_CENTRAL_PENDING_TRANS_0_RCE_P2PS_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define MISCREG_AXIS_CENTRAL_PENDING_TRANS_0_RCE_P2PS_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define MISCREG_AXIS_CENTRAL_PENDING_TRANS_0_RCE_P2PS_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define MISCREG_AXIS_CENTRAL_PENDING_TRANS_0_RCE_P2PS_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)

#define MISCREG_AXIS_CENTRAL_PENDING_TRANS_0_SCE_P2PS_SHIFT                     _MK_SHIFT_CONST(11)
#define MISCREG_AXIS_CENTRAL_PENDING_TRANS_0_SCE_P2PS_FIELD                     _MK_FIELD_CONST(0x1, MISCREG_AXIS_CENTRAL_PENDING_TRANS_0_SCE_P2PS_SHIFT)
#define MISCREG_AXIS_CENTRAL_PENDING_TRANS_0_SCE_P2PS_RANGE                     11:11
#define MISCREG_AXIS_CENTRAL_PENDING_TRANS_0_SCE_P2PS_WOFFSET                   0x0
#define MISCREG_AXIS_CENTRAL_PENDING_TRANS_0_SCE_P2PS_DEFAULT                   _MK_MASK_CONST(0x0)
#define MISCREG_AXIS_CENTRAL_PENDING_TRANS_0_SCE_P2PS_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define MISCREG_AXIS_CENTRAL_PENDING_TRANS_0_SCE_P2PS_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define MISCREG_AXIS_CENTRAL_PENDING_TRANS_0_SCE_P2PS_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define MISCREG_AXIS_CENTRAL_PENDING_TRANS_0_SCE_P2PS_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define MISCREG_AXIS_CENTRAL_PENDING_TRANS_0_SCE_P2PS_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)

#define MISCREG_AXIS_CENTRAL_PENDING_TRANS_0_TSECA_P2PS_SHIFT                   _MK_SHIFT_CONST(12)
#define MISCREG_AXIS_CENTRAL_PENDING_TRANS_0_TSECA_P2PS_FIELD                   _MK_FIELD_CONST(0x1, MISCREG_AXIS_CENTRAL_PENDING_TRANS_0_TSECA_P2PS_SHIFT)
#define MISCREG_AXIS_CENTRAL_PENDING_TRANS_0_TSECA_P2PS_RANGE                   12:12
#define MISCREG_AXIS_CENTRAL_PENDING_TRANS_0_TSECA_P2PS_WOFFSET                 0x0
#define MISCREG_AXIS_CENTRAL_PENDING_TRANS_0_TSECA_P2PS_DEFAULT                 _MK_MASK_CONST(0x0)
#define MISCREG_AXIS_CENTRAL_PENDING_TRANS_0_TSECA_P2PS_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define MISCREG_AXIS_CENTRAL_PENDING_TRANS_0_TSECA_P2PS_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define MISCREG_AXIS_CENTRAL_PENDING_TRANS_0_TSECA_P2PS_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define MISCREG_AXIS_CENTRAL_PENDING_TRANS_0_TSECA_P2PS_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define MISCREG_AXIS_CENTRAL_PENDING_TRANS_0_TSECA_P2PS_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define MISCREG_AXIS_CENTRAL_PENDING_TRANS_0_TSECB_P2PS_SHIFT                   _MK_SHIFT_CONST(13)
#define MISCREG_AXIS_CENTRAL_PENDING_TRANS_0_TSECB_P2PS_FIELD                   _MK_FIELD_CONST(0x1, MISCREG_AXIS_CENTRAL_PENDING_TRANS_0_TSECB_P2PS_SHIFT)
#define MISCREG_AXIS_CENTRAL_PENDING_TRANS_0_TSECB_P2PS_RANGE                   13:13
#define MISCREG_AXIS_CENTRAL_PENDING_TRANS_0_TSECB_P2PS_WOFFSET                 0x0
#define MISCREG_AXIS_CENTRAL_PENDING_TRANS_0_TSECB_P2PS_DEFAULT                 _MK_MASK_CONST(0x0)
#define MISCREG_AXIS_CENTRAL_PENDING_TRANS_0_TSECB_P2PS_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define MISCREG_AXIS_CENTRAL_PENDING_TRANS_0_TSECB_P2PS_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define MISCREG_AXIS_CENTRAL_PENDING_TRANS_0_TSECB_P2PS_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define MISCREG_AXIS_CENTRAL_PENDING_TRANS_0_TSECB_P2PS_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define MISCREG_AXIS_CENTRAL_PENDING_TRANS_0_TSECB_P2PS_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)


// Register MISCREG_CPU_RESET_VECTOR_0
#define MISCREG_CPU_RESET_VECTOR_0                      _MK_ADDR_CONST(0x2000)
#define MISCREG_CPU_RESET_VECTOR_0_SECURE                       0x0
#define MISCREG_CPU_RESET_VECTOR_0_DUAL                         0x0
#define MISCREG_CPU_RESET_VECTOR_0_SCR                  SCRTZWELCK_0
#define MISCREG_CPU_RESET_VECTOR_0_WORD_COUNT                   0x1
#define MISCREG_CPU_RESET_VECTOR_0_RESET_VAL                    _MK_MASK_CONST(0x0)
#define MISCREG_CPU_RESET_VECTOR_0_RESET_MASK                   _MK_MASK_CONST(0xffffffff)
#define MISCREG_CPU_RESET_VECTOR_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define MISCREG_CPU_RESET_VECTOR_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define MISCREG_CPU_RESET_VECTOR_0_READ_MASK                    _MK_MASK_CONST(0xffffffff)
#define MISCREG_CPU_RESET_VECTOR_0_WRITE_MASK                   _MK_MASK_CONST(0xffffffff)
#define MISCREG_CPU_RESET_VECTOR_0_CPU_RESET_VECTOR_SHIFT                       _MK_SHIFT_CONST(0)
#define MISCREG_CPU_RESET_VECTOR_0_CPU_RESET_VECTOR_FIELD                       _MK_FIELD_CONST(0xffffffff, MISCREG_CPU_RESET_VECTOR_0_CPU_RESET_VECTOR_SHIFT)
#define MISCREG_CPU_RESET_VECTOR_0_CPU_RESET_VECTOR_RANGE                       31:0
#define MISCREG_CPU_RESET_VECTOR_0_CPU_RESET_VECTOR_WOFFSET                     0x0
#define MISCREG_CPU_RESET_VECTOR_0_CPU_RESET_VECTOR_DEFAULT                     _MK_MASK_CONST(0x0)
#define MISCREG_CPU_RESET_VECTOR_0_CPU_RESET_VECTOR_DEFAULT_MASK                        _MK_MASK_CONST(0xffffffff)
#define MISCREG_CPU_RESET_VECTOR_0_CPU_RESET_VECTOR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define MISCREG_CPU_RESET_VECTOR_0_CPU_RESET_VECTOR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define MISCREG_CPU_RESET_VECTOR_0_CPU_RESET_VECTOR_PARITY_PROTECTION                   _MK_MASK_CONST(0x1)
#define MISCREG_CPU_RESET_VECTOR_0_CPU_RESET_VECTOR_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)


// Register MISCREG_AA64_RESET_LOW_0
#define MISCREG_AA64_RESET_LOW_0                        _MK_ADDR_CONST(0x2004)
#define MISCREG_AA64_RESET_LOW_0_SECURE                         0x0
#define MISCREG_AA64_RESET_LOW_0_DUAL                   0x0
#define MISCREG_AA64_RESET_LOW_0_SCR                    SCRTZWELCK_0
#define MISCREG_AA64_RESET_LOW_0_WORD_COUNT                     0x1
#define MISCREG_AA64_RESET_LOW_0_RESET_VAL                      _MK_MASK_CONST(0x1)
#define MISCREG_AA64_RESET_LOW_0_RESET_MASK                     _MK_MASK_CONST(0xffffffff)
#define MISCREG_AA64_RESET_LOW_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define MISCREG_AA64_RESET_LOW_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define MISCREG_AA64_RESET_LOW_0_READ_MASK                      _MK_MASK_CONST(0xffffffff)
#define MISCREG_AA64_RESET_LOW_0_WRITE_MASK                     _MK_MASK_CONST(0xffffffff)
#define MISCREG_AA64_RESET_LOW_0_AA64_RESET_LOW_SHIFT                   _MK_SHIFT_CONST(0)
#define MISCREG_AA64_RESET_LOW_0_AA64_RESET_LOW_FIELD                   _MK_FIELD_CONST(0xffffffff, MISCREG_AA64_RESET_LOW_0_AA64_RESET_LOW_SHIFT)
#define MISCREG_AA64_RESET_LOW_0_AA64_RESET_LOW_RANGE                   31:0
#define MISCREG_AA64_RESET_LOW_0_AA64_RESET_LOW_WOFFSET                 0x0
#define MISCREG_AA64_RESET_LOW_0_AA64_RESET_LOW_DEFAULT                 _MK_MASK_CONST(0x1)
#define MISCREG_AA64_RESET_LOW_0_AA64_RESET_LOW_DEFAULT_MASK                    _MK_MASK_CONST(0xffffffff)
#define MISCREG_AA64_RESET_LOW_0_AA64_RESET_LOW_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define MISCREG_AA64_RESET_LOW_0_AA64_RESET_LOW_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define MISCREG_AA64_RESET_LOW_0_AA64_RESET_LOW_PARITY_PROTECTION                       _MK_MASK_CONST(0x1)
#define MISCREG_AA64_RESET_LOW_0_AA64_RESET_LOW_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)


// Register MISCREG_AA64_RESET_HIGH_0
#define MISCREG_AA64_RESET_HIGH_0                       _MK_ADDR_CONST(0x2008)
#define MISCREG_AA64_RESET_HIGH_0_SECURE                        0x0
#define MISCREG_AA64_RESET_HIGH_0_DUAL                  0x0
#define MISCREG_AA64_RESET_HIGH_0_SCR                   SCRTZWELCK_0
#define MISCREG_AA64_RESET_HIGH_0_WORD_COUNT                    0x1
#define MISCREG_AA64_RESET_HIGH_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define MISCREG_AA64_RESET_HIGH_0_RESET_MASK                    _MK_MASK_CONST(0xfff)
#define MISCREG_AA64_RESET_HIGH_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define MISCREG_AA64_RESET_HIGH_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define MISCREG_AA64_RESET_HIGH_0_READ_MASK                     _MK_MASK_CONST(0xfff)
#define MISCREG_AA64_RESET_HIGH_0_WRITE_MASK                    _MK_MASK_CONST(0xfff)
#define MISCREG_AA64_RESET_HIGH_0_AA64_RESET_HIGH_SHIFT                 _MK_SHIFT_CONST(0)
#define MISCREG_AA64_RESET_HIGH_0_AA64_RESET_HIGH_FIELD                 _MK_FIELD_CONST(0xfff, MISCREG_AA64_RESET_HIGH_0_AA64_RESET_HIGH_SHIFT)
#define MISCREG_AA64_RESET_HIGH_0_AA64_RESET_HIGH_RANGE                 11:0
#define MISCREG_AA64_RESET_HIGH_0_AA64_RESET_HIGH_WOFFSET                       0x0
#define MISCREG_AA64_RESET_HIGH_0_AA64_RESET_HIGH_DEFAULT                       _MK_MASK_CONST(0x0)
#define MISCREG_AA64_RESET_HIGH_0_AA64_RESET_HIGH_DEFAULT_MASK                  _MK_MASK_CONST(0xfff)
#define MISCREG_AA64_RESET_HIGH_0_AA64_RESET_HIGH_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define MISCREG_AA64_RESET_HIGH_0_AA64_RESET_HIGH_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define MISCREG_AA64_RESET_HIGH_0_AA64_RESET_HIGH_PARITY_PROTECTION                     _MK_MASK_CONST(0x1)
#define MISCREG_AA64_RESET_HIGH_0_AA64_RESET_HIGH_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)


// Register MISCREG_PFCFG_0
#define MISCREG_PFCFG_0                 _MK_ADDR_CONST(0x200c)
#define MISCREG_PFCFG_0_SECURE                  0x0
#define MISCREG_PFCFG_0_DUAL                    0x0
#define MISCREG_PFCFG_0_SCR                     SCRTZWELCK_0
#define MISCREG_PFCFG_0_WORD_COUNT                      0x1
#define MISCREG_PFCFG_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define MISCREG_PFCFG_0_RESET_MASK                      _MK_MASK_CONST(0x1)
#define MISCREG_PFCFG_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define MISCREG_PFCFG_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define MISCREG_PFCFG_0_READ_MASK                       _MK_MASK_CONST(0x1)
#define MISCREG_PFCFG_0_WRITE_MASK                      _MK_MASK_CONST(0x1)
#define MISCREG_PFCFG_0_CFGSDISABLE_SHIFT                       _MK_SHIFT_CONST(0)
#define MISCREG_PFCFG_0_CFGSDISABLE_FIELD                       _MK_FIELD_CONST(0x1, MISCREG_PFCFG_0_CFGSDISABLE_SHIFT)
#define MISCREG_PFCFG_0_CFGSDISABLE_RANGE                       0:0
#define MISCREG_PFCFG_0_CFGSDISABLE_WOFFSET                     0x0
#define MISCREG_PFCFG_0_CFGSDISABLE_DEFAULT                     _MK_MASK_CONST(0x0)
#define MISCREG_PFCFG_0_CFGSDISABLE_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define MISCREG_PFCFG_0_CFGSDISABLE_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define MISCREG_PFCFG_0_CFGSDISABLE_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define MISCREG_PFCFG_0_CFGSDISABLE_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define MISCREG_PFCFG_0_CFGSDISABLE_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define MISCREG_PFCFG_0_CFGSDISABLE_DISABLE                     _MK_ENUM_CONST(1)
#define MISCREG_PFCFG_0_CFGSDISABLE_ENABLE                      _MK_ENUM_CONST(0)


// Register MISCREG_STICKY_REG0_0
#define MISCREG_STICKY_REG0_0                   _MK_ADDR_CONST(0x3000)
#define MISCREG_STICKY_REG0_0_SECURE                    0x0
#define MISCREG_STICKY_REG0_0_DUAL                      0x0
#define MISCREG_STICKY_REG0_0_SCR                       0
#define MISCREG_STICKY_REG0_0_WORD_COUNT                        0x1
#define MISCREG_STICKY_REG0_0_RESET_VAL                         _MK_MASK_CONST(0x0)
#define MISCREG_STICKY_REG0_0_RESET_MASK                        _MK_MASK_CONST(0xffffffff)
#define MISCREG_STICKY_REG0_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define MISCREG_STICKY_REG0_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define MISCREG_STICKY_REG0_0_READ_MASK                         _MK_MASK_CONST(0xffffffff)
#define MISCREG_STICKY_REG0_0_WRITE_MASK                        _MK_MASK_CONST(0xffffffff)
#define MISCREG_STICKY_REG0_0_STICKY_REG0_SHIFT                 _MK_SHIFT_CONST(0)
#define MISCREG_STICKY_REG0_0_STICKY_REG0_FIELD                 _MK_FIELD_CONST(0xffffffff, MISCREG_STICKY_REG0_0_STICKY_REG0_SHIFT)
#define MISCREG_STICKY_REG0_0_STICKY_REG0_RANGE                 31:0
#define MISCREG_STICKY_REG0_0_STICKY_REG0_WOFFSET                       0x0
#define MISCREG_STICKY_REG0_0_STICKY_REG0_DEFAULT                       _MK_MASK_CONST(0x0)
#define MISCREG_STICKY_REG0_0_STICKY_REG0_DEFAULT_MASK                  _MK_MASK_CONST(0xffffffff)
#define MISCREG_STICKY_REG0_0_STICKY_REG0_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define MISCREG_STICKY_REG0_0_STICKY_REG0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define MISCREG_STICKY_REG0_0_STICKY_REG0_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define MISCREG_STICKY_REG0_0_STICKY_REG0_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)


// Register MISCREG_STICKY_REG1_0
#define MISCREG_STICKY_REG1_0                   _MK_ADDR_CONST(0x3004)
#define MISCREG_STICKY_REG1_0_SECURE                    0x0
#define MISCREG_STICKY_REG1_0_DUAL                      0x0
#define MISCREG_STICKY_REG1_0_SCR                       0
#define MISCREG_STICKY_REG1_0_WORD_COUNT                        0x1
#define MISCREG_STICKY_REG1_0_RESET_VAL                         _MK_MASK_CONST(0x0)
#define MISCREG_STICKY_REG1_0_RESET_MASK                        _MK_MASK_CONST(0xffffffff)
#define MISCREG_STICKY_REG1_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define MISCREG_STICKY_REG1_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define MISCREG_STICKY_REG1_0_READ_MASK                         _MK_MASK_CONST(0xffffffff)
#define MISCREG_STICKY_REG1_0_WRITE_MASK                        _MK_MASK_CONST(0xffffffff)
#define MISCREG_STICKY_REG1_0_STICKY_REG1_SHIFT                 _MK_SHIFT_CONST(0)
#define MISCREG_STICKY_REG1_0_STICKY_REG1_FIELD                 _MK_FIELD_CONST(0xffffffff, MISCREG_STICKY_REG1_0_STICKY_REG1_SHIFT)
#define MISCREG_STICKY_REG1_0_STICKY_REG1_RANGE                 31:0
#define MISCREG_STICKY_REG1_0_STICKY_REG1_WOFFSET                       0x0
#define MISCREG_STICKY_REG1_0_STICKY_REG1_DEFAULT                       _MK_MASK_CONST(0x0)
#define MISCREG_STICKY_REG1_0_STICKY_REG1_DEFAULT_MASK                  _MK_MASK_CONST(0xffffffff)
#define MISCREG_STICKY_REG1_0_STICKY_REG1_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define MISCREG_STICKY_REG1_0_STICKY_REG1_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define MISCREG_STICKY_REG1_0_STICKY_REG1_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define MISCREG_STICKY_REG1_0_STICKY_REG1_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)


// Register MISCREG_STICKY_REG2_0
#define MISCREG_STICKY_REG2_0                   _MK_ADDR_CONST(0x3008)
#define MISCREG_STICKY_REG2_0_SECURE                    0x0
#define MISCREG_STICKY_REG2_0_DUAL                      0x0
#define MISCREG_STICKY_REG2_0_SCR                       0
#define MISCREG_STICKY_REG2_0_WORD_COUNT                        0x1
#define MISCREG_STICKY_REG2_0_RESET_VAL                         _MK_MASK_CONST(0x0)
#define MISCREG_STICKY_REG2_0_RESET_MASK                        _MK_MASK_CONST(0xffffffff)
#define MISCREG_STICKY_REG2_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define MISCREG_STICKY_REG2_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define MISCREG_STICKY_REG2_0_READ_MASK                         _MK_MASK_CONST(0xffffffff)
#define MISCREG_STICKY_REG2_0_WRITE_MASK                        _MK_MASK_CONST(0xffffffff)
#define MISCREG_STICKY_REG2_0_STICKY_REG2_SHIFT                 _MK_SHIFT_CONST(0)
#define MISCREG_STICKY_REG2_0_STICKY_REG2_FIELD                 _MK_FIELD_CONST(0xffffffff, MISCREG_STICKY_REG2_0_STICKY_REG2_SHIFT)
#define MISCREG_STICKY_REG2_0_STICKY_REG2_RANGE                 31:0
#define MISCREG_STICKY_REG2_0_STICKY_REG2_WOFFSET                       0x0
#define MISCREG_STICKY_REG2_0_STICKY_REG2_DEFAULT                       _MK_MASK_CONST(0x0)
#define MISCREG_STICKY_REG2_0_STICKY_REG2_DEFAULT_MASK                  _MK_MASK_CONST(0xffffffff)
#define MISCREG_STICKY_REG2_0_STICKY_REG2_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define MISCREG_STICKY_REG2_0_STICKY_REG2_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define MISCREG_STICKY_REG2_0_STICKY_REG2_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define MISCREG_STICKY_REG2_0_STICKY_REG2_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)


// Register MISCREG_STICKY_REG3_0
#define MISCREG_STICKY_REG3_0                   _MK_ADDR_CONST(0x300c)
#define MISCREG_STICKY_REG3_0_SECURE                    0x0
#define MISCREG_STICKY_REG3_0_DUAL                      0x0
#define MISCREG_STICKY_REG3_0_SCR                       0
#define MISCREG_STICKY_REG3_0_WORD_COUNT                        0x1
#define MISCREG_STICKY_REG3_0_RESET_VAL                         _MK_MASK_CONST(0x0)
#define MISCREG_STICKY_REG3_0_RESET_MASK                        _MK_MASK_CONST(0xffffffff)
#define MISCREG_STICKY_REG3_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define MISCREG_STICKY_REG3_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define MISCREG_STICKY_REG3_0_READ_MASK                         _MK_MASK_CONST(0xffffffff)
#define MISCREG_STICKY_REG3_0_WRITE_MASK                        _MK_MASK_CONST(0xffffffff)
#define MISCREG_STICKY_REG3_0_STICKY_REG3_SHIFT                 _MK_SHIFT_CONST(0)
#define MISCREG_STICKY_REG3_0_STICKY_REG3_FIELD                 _MK_FIELD_CONST(0xffffffff, MISCREG_STICKY_REG3_0_STICKY_REG3_SHIFT)
#define MISCREG_STICKY_REG3_0_STICKY_REG3_RANGE                 31:0
#define MISCREG_STICKY_REG3_0_STICKY_REG3_WOFFSET                       0x0
#define MISCREG_STICKY_REG3_0_STICKY_REG3_DEFAULT                       _MK_MASK_CONST(0x0)
#define MISCREG_STICKY_REG3_0_STICKY_REG3_DEFAULT_MASK                  _MK_MASK_CONST(0xffffffff)
#define MISCREG_STICKY_REG3_0_STICKY_REG3_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define MISCREG_STICKY_REG3_0_STICKY_REG3_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define MISCREG_STICKY_REG3_0_STICKY_REG3_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define MISCREG_STICKY_REG3_0_STICKY_REG3_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)


// Register MISCREG_SPARE_REG0_0
#define MISCREG_SPARE_REG0_0                    _MK_ADDR_CONST(0x3010)
#define MISCREG_SPARE_REG0_0_SECURE                     0x0
#define MISCREG_SPARE_REG0_0_DUAL                       0x0
#define MISCREG_SPARE_REG0_0_SCR                        0
#define MISCREG_SPARE_REG0_0_WORD_COUNT                         0x1
#define MISCREG_SPARE_REG0_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define MISCREG_SPARE_REG0_0_RESET_MASK                         _MK_MASK_CONST(0xffffffff)
#define MISCREG_SPARE_REG0_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define MISCREG_SPARE_REG0_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define MISCREG_SPARE_REG0_0_READ_MASK                  _MK_MASK_CONST(0xffffffff)
#define MISCREG_SPARE_REG0_0_WRITE_MASK                         _MK_MASK_CONST(0xffffffff)
#define MISCREG_SPARE_REG0_0_SPARE_REG0_SHIFT                   _MK_SHIFT_CONST(0)
#define MISCREG_SPARE_REG0_0_SPARE_REG0_FIELD                   _MK_FIELD_CONST(0xffffffff, MISCREG_SPARE_REG0_0_SPARE_REG0_SHIFT)
#define MISCREG_SPARE_REG0_0_SPARE_REG0_RANGE                   31:0
#define MISCREG_SPARE_REG0_0_SPARE_REG0_WOFFSET                 0x0
#define MISCREG_SPARE_REG0_0_SPARE_REG0_DEFAULT                 _MK_MASK_CONST(0x0)
#define MISCREG_SPARE_REG0_0_SPARE_REG0_DEFAULT_MASK                    _MK_MASK_CONST(0xffffffff)
#define MISCREG_SPARE_REG0_0_SPARE_REG0_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define MISCREG_SPARE_REG0_0_SPARE_REG0_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define MISCREG_SPARE_REG0_0_SPARE_REG0_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define MISCREG_SPARE_REG0_0_SPARE_REG0_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)


// Register MISCREG_SPARE_REG1_0
#define MISCREG_SPARE_REG1_0                    _MK_ADDR_CONST(0x3014)
#define MISCREG_SPARE_REG1_0_SECURE                     0x0
#define MISCREG_SPARE_REG1_0_DUAL                       0x0
#define MISCREG_SPARE_REG1_0_SCR                        0
#define MISCREG_SPARE_REG1_0_WORD_COUNT                         0x1
#define MISCREG_SPARE_REG1_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define MISCREG_SPARE_REG1_0_RESET_MASK                         _MK_MASK_CONST(0xffffffff)
#define MISCREG_SPARE_REG1_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define MISCREG_SPARE_REG1_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define MISCREG_SPARE_REG1_0_READ_MASK                  _MK_MASK_CONST(0xffffffff)
#define MISCREG_SPARE_REG1_0_WRITE_MASK                         _MK_MASK_CONST(0xffffffff)
#define MISCREG_SPARE_REG1_0_SPARE_REG1_SHIFT                   _MK_SHIFT_CONST(0)
#define MISCREG_SPARE_REG1_0_SPARE_REG1_FIELD                   _MK_FIELD_CONST(0xffffffff, MISCREG_SPARE_REG1_0_SPARE_REG1_SHIFT)
#define MISCREG_SPARE_REG1_0_SPARE_REG1_RANGE                   31:0
#define MISCREG_SPARE_REG1_0_SPARE_REG1_WOFFSET                 0x0
#define MISCREG_SPARE_REG1_0_SPARE_REG1_DEFAULT                 _MK_MASK_CONST(0x0)
#define MISCREG_SPARE_REG1_0_SPARE_REG1_DEFAULT_MASK                    _MK_MASK_CONST(0xffffffff)
#define MISCREG_SPARE_REG1_0_SPARE_REG1_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define MISCREG_SPARE_REG1_0_SPARE_REG1_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define MISCREG_SPARE_REG1_0_SPARE_REG1_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define MISCREG_SPARE_REG1_0_SPARE_REG1_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)


// Register MISCREG_SPARE_REG2_0
#define MISCREG_SPARE_REG2_0                    _MK_ADDR_CONST(0x3018)
#define MISCREG_SPARE_REG2_0_SECURE                     0x0
#define MISCREG_SPARE_REG2_0_DUAL                       0x0
#define MISCREG_SPARE_REG2_0_SCR                        0
#define MISCREG_SPARE_REG2_0_WORD_COUNT                         0x1
#define MISCREG_SPARE_REG2_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define MISCREG_SPARE_REG2_0_RESET_MASK                         _MK_MASK_CONST(0xffffffff)
#define MISCREG_SPARE_REG2_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define MISCREG_SPARE_REG2_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define MISCREG_SPARE_REG2_0_READ_MASK                  _MK_MASK_CONST(0xffffffff)
#define MISCREG_SPARE_REG2_0_WRITE_MASK                         _MK_MASK_CONST(0xffffffff)
#define MISCREG_SPARE_REG2_0_SPARE_REG2_SHIFT                   _MK_SHIFT_CONST(0)
#define MISCREG_SPARE_REG2_0_SPARE_REG2_FIELD                   _MK_FIELD_CONST(0xffffffff, MISCREG_SPARE_REG2_0_SPARE_REG2_SHIFT)
#define MISCREG_SPARE_REG2_0_SPARE_REG2_RANGE                   31:0
#define MISCREG_SPARE_REG2_0_SPARE_REG2_WOFFSET                 0x0
#define MISCREG_SPARE_REG2_0_SPARE_REG2_DEFAULT                 _MK_MASK_CONST(0x0)
#define MISCREG_SPARE_REG2_0_SPARE_REG2_DEFAULT_MASK                    _MK_MASK_CONST(0xffffffff)
#define MISCREG_SPARE_REG2_0_SPARE_REG2_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define MISCREG_SPARE_REG2_0_SPARE_REG2_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define MISCREG_SPARE_REG2_0_SPARE_REG2_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define MISCREG_SPARE_REG2_0_SPARE_REG2_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)


// Register MISCREG_SPARE_REG3_0
#define MISCREG_SPARE_REG3_0                    _MK_ADDR_CONST(0x301c)
#define MISCREG_SPARE_REG3_0_SECURE                     0x0
#define MISCREG_SPARE_REG3_0_DUAL                       0x0
#define MISCREG_SPARE_REG3_0_SCR                        0
#define MISCREG_SPARE_REG3_0_WORD_COUNT                         0x1
#define MISCREG_SPARE_REG3_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define MISCREG_SPARE_REG3_0_RESET_MASK                         _MK_MASK_CONST(0xffffffff)
#define MISCREG_SPARE_REG3_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define MISCREG_SPARE_REG3_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define MISCREG_SPARE_REG3_0_READ_MASK                  _MK_MASK_CONST(0xffffffff)
#define MISCREG_SPARE_REG3_0_WRITE_MASK                         _MK_MASK_CONST(0xffffffff)
#define MISCREG_SPARE_REG3_0_SPARE_REG3_SHIFT                   _MK_SHIFT_CONST(0)
#define MISCREG_SPARE_REG3_0_SPARE_REG3_FIELD                   _MK_FIELD_CONST(0xffffffff, MISCREG_SPARE_REG3_0_SPARE_REG3_SHIFT)
#define MISCREG_SPARE_REG3_0_SPARE_REG3_RANGE                   31:0
#define MISCREG_SPARE_REG3_0_SPARE_REG3_WOFFSET                 0x0
#define MISCREG_SPARE_REG3_0_SPARE_REG3_DEFAULT                 _MK_MASK_CONST(0x0)
#define MISCREG_SPARE_REG3_0_SPARE_REG3_DEFAULT_MASK                    _MK_MASK_CONST(0xffffffff)
#define MISCREG_SPARE_REG3_0_SPARE_REG3_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define MISCREG_SPARE_REG3_0_SPARE_REG3_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define MISCREG_SPARE_REG3_0_SPARE_REG3_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define MISCREG_SPARE_REG3_0_SPARE_REG3_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)


// Register MISCREG_PROTO_CVRPTS_DATA0_0
#define MISCREG_PROTO_CVRPTS_DATA0_0                    _MK_ADDR_CONST(0x3100)
#define MISCREG_PROTO_CVRPTS_DATA0_0_SECURE                     0x0
#define MISCREG_PROTO_CVRPTS_DATA0_0_DUAL                       0x0
#define MISCREG_PROTO_CVRPTS_DATA0_0_SCR                        0
#define MISCREG_PROTO_CVRPTS_DATA0_0_WORD_COUNT                         0x1
#define MISCREG_PROTO_CVRPTS_DATA0_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define MISCREG_PROTO_CVRPTS_DATA0_0_RESET_MASK                         _MK_MASK_CONST(0xffffffff)
#define MISCREG_PROTO_CVRPTS_DATA0_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define MISCREG_PROTO_CVRPTS_DATA0_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define MISCREG_PROTO_CVRPTS_DATA0_0_READ_MASK                  _MK_MASK_CONST(0xffffffff)
#define MISCREG_PROTO_CVRPTS_DATA0_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
#define MISCREG_PROTO_CVRPTS_DATA0_0_CVRPT_COUNT_SHIFT                  _MK_SHIFT_CONST(24)
#define MISCREG_PROTO_CVRPTS_DATA0_0_CVRPT_COUNT_FIELD                  _MK_FIELD_CONST(0xff, MISCREG_PROTO_CVRPTS_DATA0_0_CVRPT_COUNT_SHIFT)
#define MISCREG_PROTO_CVRPTS_DATA0_0_CVRPT_COUNT_RANGE                  31:24
#define MISCREG_PROTO_CVRPTS_DATA0_0_CVRPT_COUNT_WOFFSET                        0x0
#define MISCREG_PROTO_CVRPTS_DATA0_0_CVRPT_COUNT_DEFAULT                        _MK_MASK_CONST(0x0)
#define MISCREG_PROTO_CVRPTS_DATA0_0_CVRPT_COUNT_DEFAULT_MASK                   _MK_MASK_CONST(0xff)
#define MISCREG_PROTO_CVRPTS_DATA0_0_CVRPT_COUNT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define MISCREG_PROTO_CVRPTS_DATA0_0_CVRPT_COUNT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define MISCREG_PROTO_CVRPTS_DATA0_0_CVRPT_COUNT_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define MISCREG_PROTO_CVRPTS_DATA0_0_CVRPT_COUNT_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)

#define MISCREG_PROTO_CVRPTS_DATA0_0_CVRPT_TIMESTAMP_SHIFT                      _MK_SHIFT_CONST(0)
#define MISCREG_PROTO_CVRPTS_DATA0_0_CVRPT_TIMESTAMP_FIELD                      _MK_FIELD_CONST(0xffffff, MISCREG_PROTO_CVRPTS_DATA0_0_CVRPT_TIMESTAMP_SHIFT)
#define MISCREG_PROTO_CVRPTS_DATA0_0_CVRPT_TIMESTAMP_RANGE                      23:0
#define MISCREG_PROTO_CVRPTS_DATA0_0_CVRPT_TIMESTAMP_WOFFSET                    0x0
#define MISCREG_PROTO_CVRPTS_DATA0_0_CVRPT_TIMESTAMP_DEFAULT                    _MK_MASK_CONST(0x0)
#define MISCREG_PROTO_CVRPTS_DATA0_0_CVRPT_TIMESTAMP_DEFAULT_MASK                       _MK_MASK_CONST(0xffffff)
#define MISCREG_PROTO_CVRPTS_DATA0_0_CVRPT_TIMESTAMP_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define MISCREG_PROTO_CVRPTS_DATA0_0_CVRPT_TIMESTAMP_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define MISCREG_PROTO_CVRPTS_DATA0_0_CVRPT_TIMESTAMP_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define MISCREG_PROTO_CVRPTS_DATA0_0_CVRPT_TIMESTAMP_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)


// Register MISCREG_PROTO_CVRPTS_DATA1_0
#define MISCREG_PROTO_CVRPTS_DATA1_0                    _MK_ADDR_CONST(0x3104)
#define MISCREG_PROTO_CVRPTS_DATA1_0_SECURE                     0x0
#define MISCREG_PROTO_CVRPTS_DATA1_0_DUAL                       0x0
#define MISCREG_PROTO_CVRPTS_DATA1_0_SCR                        0
#define MISCREG_PROTO_CVRPTS_DATA1_0_WORD_COUNT                         0x1
#define MISCREG_PROTO_CVRPTS_DATA1_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define MISCREG_PROTO_CVRPTS_DATA1_0_RESET_MASK                         _MK_MASK_CONST(0xffffffff)
#define MISCREG_PROTO_CVRPTS_DATA1_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define MISCREG_PROTO_CVRPTS_DATA1_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define MISCREG_PROTO_CVRPTS_DATA1_0_READ_MASK                  _MK_MASK_CONST(0xffffffff)
#define MISCREG_PROTO_CVRPTS_DATA1_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
#define MISCREG_PROTO_CVRPTS_DATA1_0_CVRPT_COUNT_SHIFT                  _MK_SHIFT_CONST(24)
#define MISCREG_PROTO_CVRPTS_DATA1_0_CVRPT_COUNT_FIELD                  _MK_FIELD_CONST(0xff, MISCREG_PROTO_CVRPTS_DATA1_0_CVRPT_COUNT_SHIFT)
#define MISCREG_PROTO_CVRPTS_DATA1_0_CVRPT_COUNT_RANGE                  31:24
#define MISCREG_PROTO_CVRPTS_DATA1_0_CVRPT_COUNT_WOFFSET                        0x0
#define MISCREG_PROTO_CVRPTS_DATA1_0_CVRPT_COUNT_DEFAULT                        _MK_MASK_CONST(0x0)
#define MISCREG_PROTO_CVRPTS_DATA1_0_CVRPT_COUNT_DEFAULT_MASK                   _MK_MASK_CONST(0xff)
#define MISCREG_PROTO_CVRPTS_DATA1_0_CVRPT_COUNT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define MISCREG_PROTO_CVRPTS_DATA1_0_CVRPT_COUNT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define MISCREG_PROTO_CVRPTS_DATA1_0_CVRPT_COUNT_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define MISCREG_PROTO_CVRPTS_DATA1_0_CVRPT_COUNT_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)

#define MISCREG_PROTO_CVRPTS_DATA1_0_CVRPT_TIMESTAMP_SHIFT                      _MK_SHIFT_CONST(0)
#define MISCREG_PROTO_CVRPTS_DATA1_0_CVRPT_TIMESTAMP_FIELD                      _MK_FIELD_CONST(0xffffff, MISCREG_PROTO_CVRPTS_DATA1_0_CVRPT_TIMESTAMP_SHIFT)
#define MISCREG_PROTO_CVRPTS_DATA1_0_CVRPT_TIMESTAMP_RANGE                      23:0
#define MISCREG_PROTO_CVRPTS_DATA1_0_CVRPT_TIMESTAMP_WOFFSET                    0x0
#define MISCREG_PROTO_CVRPTS_DATA1_0_CVRPT_TIMESTAMP_DEFAULT                    _MK_MASK_CONST(0x0)
#define MISCREG_PROTO_CVRPTS_DATA1_0_CVRPT_TIMESTAMP_DEFAULT_MASK                       _MK_MASK_CONST(0xffffff)
#define MISCREG_PROTO_CVRPTS_DATA1_0_CVRPT_TIMESTAMP_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define MISCREG_PROTO_CVRPTS_DATA1_0_CVRPT_TIMESTAMP_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define MISCREG_PROTO_CVRPTS_DATA1_0_CVRPT_TIMESTAMP_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define MISCREG_PROTO_CVRPTS_DATA1_0_CVRPT_TIMESTAMP_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)


// Register MISCREG_PROTO_CVRPTS_DATA2_0
#define MISCREG_PROTO_CVRPTS_DATA2_0                    _MK_ADDR_CONST(0x3108)
#define MISCREG_PROTO_CVRPTS_DATA2_0_SECURE                     0x0
#define MISCREG_PROTO_CVRPTS_DATA2_0_DUAL                       0x0
#define MISCREG_PROTO_CVRPTS_DATA2_0_SCR                        0
#define MISCREG_PROTO_CVRPTS_DATA2_0_WORD_COUNT                         0x1
#define MISCREG_PROTO_CVRPTS_DATA2_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define MISCREG_PROTO_CVRPTS_DATA2_0_RESET_MASK                         _MK_MASK_CONST(0xffffffff)
#define MISCREG_PROTO_CVRPTS_DATA2_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define MISCREG_PROTO_CVRPTS_DATA2_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define MISCREG_PROTO_CVRPTS_DATA2_0_READ_MASK                  _MK_MASK_CONST(0xffffffff)
#define MISCREG_PROTO_CVRPTS_DATA2_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
#define MISCREG_PROTO_CVRPTS_DATA2_0_CVRPT_COUNT_SHIFT                  _MK_SHIFT_CONST(24)
#define MISCREG_PROTO_CVRPTS_DATA2_0_CVRPT_COUNT_FIELD                  _MK_FIELD_CONST(0xff, MISCREG_PROTO_CVRPTS_DATA2_0_CVRPT_COUNT_SHIFT)
#define MISCREG_PROTO_CVRPTS_DATA2_0_CVRPT_COUNT_RANGE                  31:24
#define MISCREG_PROTO_CVRPTS_DATA2_0_CVRPT_COUNT_WOFFSET                        0x0
#define MISCREG_PROTO_CVRPTS_DATA2_0_CVRPT_COUNT_DEFAULT                        _MK_MASK_CONST(0x0)
#define MISCREG_PROTO_CVRPTS_DATA2_0_CVRPT_COUNT_DEFAULT_MASK                   _MK_MASK_CONST(0xff)
#define MISCREG_PROTO_CVRPTS_DATA2_0_CVRPT_COUNT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define MISCREG_PROTO_CVRPTS_DATA2_0_CVRPT_COUNT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define MISCREG_PROTO_CVRPTS_DATA2_0_CVRPT_COUNT_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define MISCREG_PROTO_CVRPTS_DATA2_0_CVRPT_COUNT_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)

#define MISCREG_PROTO_CVRPTS_DATA2_0_CVRPT_TIMESTAMP_SHIFT                      _MK_SHIFT_CONST(0)
#define MISCREG_PROTO_CVRPTS_DATA2_0_CVRPT_TIMESTAMP_FIELD                      _MK_FIELD_CONST(0xffffff, MISCREG_PROTO_CVRPTS_DATA2_0_CVRPT_TIMESTAMP_SHIFT)
#define MISCREG_PROTO_CVRPTS_DATA2_0_CVRPT_TIMESTAMP_RANGE                      23:0
#define MISCREG_PROTO_CVRPTS_DATA2_0_CVRPT_TIMESTAMP_WOFFSET                    0x0
#define MISCREG_PROTO_CVRPTS_DATA2_0_CVRPT_TIMESTAMP_DEFAULT                    _MK_MASK_CONST(0x0)
#define MISCREG_PROTO_CVRPTS_DATA2_0_CVRPT_TIMESTAMP_DEFAULT_MASK                       _MK_MASK_CONST(0xffffff)
#define MISCREG_PROTO_CVRPTS_DATA2_0_CVRPT_TIMESTAMP_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define MISCREG_PROTO_CVRPTS_DATA2_0_CVRPT_TIMESTAMP_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define MISCREG_PROTO_CVRPTS_DATA2_0_CVRPT_TIMESTAMP_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define MISCREG_PROTO_CVRPTS_DATA2_0_CVRPT_TIMESTAMP_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)


// Register MISCREG_PROTO_CVRPTS_DATA3_0
#define MISCREG_PROTO_CVRPTS_DATA3_0                    _MK_ADDR_CONST(0x310c)
#define MISCREG_PROTO_CVRPTS_DATA3_0_SECURE                     0x0
#define MISCREG_PROTO_CVRPTS_DATA3_0_DUAL                       0x0
#define MISCREG_PROTO_CVRPTS_DATA3_0_SCR                        0
#define MISCREG_PROTO_CVRPTS_DATA3_0_WORD_COUNT                         0x1
#define MISCREG_PROTO_CVRPTS_DATA3_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define MISCREG_PROTO_CVRPTS_DATA3_0_RESET_MASK                         _MK_MASK_CONST(0xffffffff)
#define MISCREG_PROTO_CVRPTS_DATA3_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define MISCREG_PROTO_CVRPTS_DATA3_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define MISCREG_PROTO_CVRPTS_DATA3_0_READ_MASK                  _MK_MASK_CONST(0xffffffff)
#define MISCREG_PROTO_CVRPTS_DATA3_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
#define MISCREG_PROTO_CVRPTS_DATA3_0_CVRPT_COUNT_SHIFT                  _MK_SHIFT_CONST(24)
#define MISCREG_PROTO_CVRPTS_DATA3_0_CVRPT_COUNT_FIELD                  _MK_FIELD_CONST(0xff, MISCREG_PROTO_CVRPTS_DATA3_0_CVRPT_COUNT_SHIFT)
#define MISCREG_PROTO_CVRPTS_DATA3_0_CVRPT_COUNT_RANGE                  31:24
#define MISCREG_PROTO_CVRPTS_DATA3_0_CVRPT_COUNT_WOFFSET                        0x0
#define MISCREG_PROTO_CVRPTS_DATA3_0_CVRPT_COUNT_DEFAULT                        _MK_MASK_CONST(0x0)
#define MISCREG_PROTO_CVRPTS_DATA3_0_CVRPT_COUNT_DEFAULT_MASK                   _MK_MASK_CONST(0xff)
#define MISCREG_PROTO_CVRPTS_DATA3_0_CVRPT_COUNT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define MISCREG_PROTO_CVRPTS_DATA3_0_CVRPT_COUNT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define MISCREG_PROTO_CVRPTS_DATA3_0_CVRPT_COUNT_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define MISCREG_PROTO_CVRPTS_DATA3_0_CVRPT_COUNT_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)

#define MISCREG_PROTO_CVRPTS_DATA3_0_CVRPT_TIMESTAMP_SHIFT                      _MK_SHIFT_CONST(0)
#define MISCREG_PROTO_CVRPTS_DATA3_0_CVRPT_TIMESTAMP_FIELD                      _MK_FIELD_CONST(0xffffff, MISCREG_PROTO_CVRPTS_DATA3_0_CVRPT_TIMESTAMP_SHIFT)
#define MISCREG_PROTO_CVRPTS_DATA3_0_CVRPT_TIMESTAMP_RANGE                      23:0
#define MISCREG_PROTO_CVRPTS_DATA3_0_CVRPT_TIMESTAMP_WOFFSET                    0x0
#define MISCREG_PROTO_CVRPTS_DATA3_0_CVRPT_TIMESTAMP_DEFAULT                    _MK_MASK_CONST(0x0)
#define MISCREG_PROTO_CVRPTS_DATA3_0_CVRPT_TIMESTAMP_DEFAULT_MASK                       _MK_MASK_CONST(0xffffff)
#define MISCREG_PROTO_CVRPTS_DATA3_0_CVRPT_TIMESTAMP_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define MISCREG_PROTO_CVRPTS_DATA3_0_CVRPT_TIMESTAMP_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define MISCREG_PROTO_CVRPTS_DATA3_0_CVRPT_TIMESTAMP_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define MISCREG_PROTO_CVRPTS_DATA3_0_CVRPT_TIMESTAMP_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)


// Register MISCREG_PROTO_CVRPTS_DATA4_0
#define MISCREG_PROTO_CVRPTS_DATA4_0                    _MK_ADDR_CONST(0x3110)
#define MISCREG_PROTO_CVRPTS_DATA4_0_SECURE                     0x0
#define MISCREG_PROTO_CVRPTS_DATA4_0_DUAL                       0x0
#define MISCREG_PROTO_CVRPTS_DATA4_0_SCR                        0
#define MISCREG_PROTO_CVRPTS_DATA4_0_WORD_COUNT                         0x1
#define MISCREG_PROTO_CVRPTS_DATA4_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define MISCREG_PROTO_CVRPTS_DATA4_0_RESET_MASK                         _MK_MASK_CONST(0xffffffff)
#define MISCREG_PROTO_CVRPTS_DATA4_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define MISCREG_PROTO_CVRPTS_DATA4_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define MISCREG_PROTO_CVRPTS_DATA4_0_READ_MASK                  _MK_MASK_CONST(0xffffffff)
#define MISCREG_PROTO_CVRPTS_DATA4_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
#define MISCREG_PROTO_CVRPTS_DATA4_0_CVRPT_COUNT_SHIFT                  _MK_SHIFT_CONST(24)
#define MISCREG_PROTO_CVRPTS_DATA4_0_CVRPT_COUNT_FIELD                  _MK_FIELD_CONST(0xff, MISCREG_PROTO_CVRPTS_DATA4_0_CVRPT_COUNT_SHIFT)
#define MISCREG_PROTO_CVRPTS_DATA4_0_CVRPT_COUNT_RANGE                  31:24
#define MISCREG_PROTO_CVRPTS_DATA4_0_CVRPT_COUNT_WOFFSET                        0x0
#define MISCREG_PROTO_CVRPTS_DATA4_0_CVRPT_COUNT_DEFAULT                        _MK_MASK_CONST(0x0)
#define MISCREG_PROTO_CVRPTS_DATA4_0_CVRPT_COUNT_DEFAULT_MASK                   _MK_MASK_CONST(0xff)
#define MISCREG_PROTO_CVRPTS_DATA4_0_CVRPT_COUNT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define MISCREG_PROTO_CVRPTS_DATA4_0_CVRPT_COUNT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define MISCREG_PROTO_CVRPTS_DATA4_0_CVRPT_COUNT_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define MISCREG_PROTO_CVRPTS_DATA4_0_CVRPT_COUNT_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)

#define MISCREG_PROTO_CVRPTS_DATA4_0_CVRPT_TIMESTAMP_SHIFT                      _MK_SHIFT_CONST(0)
#define MISCREG_PROTO_CVRPTS_DATA4_0_CVRPT_TIMESTAMP_FIELD                      _MK_FIELD_CONST(0xffffff, MISCREG_PROTO_CVRPTS_DATA4_0_CVRPT_TIMESTAMP_SHIFT)
#define MISCREG_PROTO_CVRPTS_DATA4_0_CVRPT_TIMESTAMP_RANGE                      23:0
#define MISCREG_PROTO_CVRPTS_DATA4_0_CVRPT_TIMESTAMP_WOFFSET                    0x0
#define MISCREG_PROTO_CVRPTS_DATA4_0_CVRPT_TIMESTAMP_DEFAULT                    _MK_MASK_CONST(0x0)
#define MISCREG_PROTO_CVRPTS_DATA4_0_CVRPT_TIMESTAMP_DEFAULT_MASK                       _MK_MASK_CONST(0xffffff)
#define MISCREG_PROTO_CVRPTS_DATA4_0_CVRPT_TIMESTAMP_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define MISCREG_PROTO_CVRPTS_DATA4_0_CVRPT_TIMESTAMP_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define MISCREG_PROTO_CVRPTS_DATA4_0_CVRPT_TIMESTAMP_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define MISCREG_PROTO_CVRPTS_DATA4_0_CVRPT_TIMESTAMP_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)


// Register MISCREG_PROTO_CVRPTS_DATA5_0
#define MISCREG_PROTO_CVRPTS_DATA5_0                    _MK_ADDR_CONST(0x3114)
#define MISCREG_PROTO_CVRPTS_DATA5_0_SECURE                     0x0
#define MISCREG_PROTO_CVRPTS_DATA5_0_DUAL                       0x0
#define MISCREG_PROTO_CVRPTS_DATA5_0_SCR                        0
#define MISCREG_PROTO_CVRPTS_DATA5_0_WORD_COUNT                         0x1
#define MISCREG_PROTO_CVRPTS_DATA5_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define MISCREG_PROTO_CVRPTS_DATA5_0_RESET_MASK                         _MK_MASK_CONST(0xffffffff)
#define MISCREG_PROTO_CVRPTS_DATA5_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define MISCREG_PROTO_CVRPTS_DATA5_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define MISCREG_PROTO_CVRPTS_DATA5_0_READ_MASK                  _MK_MASK_CONST(0xffffffff)
#define MISCREG_PROTO_CVRPTS_DATA5_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
#define MISCREG_PROTO_CVRPTS_DATA5_0_CVRPT_COUNT_SHIFT                  _MK_SHIFT_CONST(24)
#define MISCREG_PROTO_CVRPTS_DATA5_0_CVRPT_COUNT_FIELD                  _MK_FIELD_CONST(0xff, MISCREG_PROTO_CVRPTS_DATA5_0_CVRPT_COUNT_SHIFT)
#define MISCREG_PROTO_CVRPTS_DATA5_0_CVRPT_COUNT_RANGE                  31:24
#define MISCREG_PROTO_CVRPTS_DATA5_0_CVRPT_COUNT_WOFFSET                        0x0
#define MISCREG_PROTO_CVRPTS_DATA5_0_CVRPT_COUNT_DEFAULT                        _MK_MASK_CONST(0x0)
#define MISCREG_PROTO_CVRPTS_DATA5_0_CVRPT_COUNT_DEFAULT_MASK                   _MK_MASK_CONST(0xff)
#define MISCREG_PROTO_CVRPTS_DATA5_0_CVRPT_COUNT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define MISCREG_PROTO_CVRPTS_DATA5_0_CVRPT_COUNT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define MISCREG_PROTO_CVRPTS_DATA5_0_CVRPT_COUNT_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define MISCREG_PROTO_CVRPTS_DATA5_0_CVRPT_COUNT_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)

#define MISCREG_PROTO_CVRPTS_DATA5_0_CVRPT_TIMESTAMP_SHIFT                      _MK_SHIFT_CONST(0)
#define MISCREG_PROTO_CVRPTS_DATA5_0_CVRPT_TIMESTAMP_FIELD                      _MK_FIELD_CONST(0xffffff, MISCREG_PROTO_CVRPTS_DATA5_0_CVRPT_TIMESTAMP_SHIFT)
#define MISCREG_PROTO_CVRPTS_DATA5_0_CVRPT_TIMESTAMP_RANGE                      23:0
#define MISCREG_PROTO_CVRPTS_DATA5_0_CVRPT_TIMESTAMP_WOFFSET                    0x0
#define MISCREG_PROTO_CVRPTS_DATA5_0_CVRPT_TIMESTAMP_DEFAULT                    _MK_MASK_CONST(0x0)
#define MISCREG_PROTO_CVRPTS_DATA5_0_CVRPT_TIMESTAMP_DEFAULT_MASK                       _MK_MASK_CONST(0xffffff)
#define MISCREG_PROTO_CVRPTS_DATA5_0_CVRPT_TIMESTAMP_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define MISCREG_PROTO_CVRPTS_DATA5_0_CVRPT_TIMESTAMP_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define MISCREG_PROTO_CVRPTS_DATA5_0_CVRPT_TIMESTAMP_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define MISCREG_PROTO_CVRPTS_DATA5_0_CVRPT_TIMESTAMP_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)


// Register MISCREG_PROTO_CVRPTS_DATA6_0
#define MISCREG_PROTO_CVRPTS_DATA6_0                    _MK_ADDR_CONST(0x3118)
#define MISCREG_PROTO_CVRPTS_DATA6_0_SECURE                     0x0
#define MISCREG_PROTO_CVRPTS_DATA6_0_DUAL                       0x0
#define MISCREG_PROTO_CVRPTS_DATA6_0_SCR                        0
#define MISCREG_PROTO_CVRPTS_DATA6_0_WORD_COUNT                         0x1
#define MISCREG_PROTO_CVRPTS_DATA6_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define MISCREG_PROTO_CVRPTS_DATA6_0_RESET_MASK                         _MK_MASK_CONST(0xffffffff)
#define MISCREG_PROTO_CVRPTS_DATA6_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define MISCREG_PROTO_CVRPTS_DATA6_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define MISCREG_PROTO_CVRPTS_DATA6_0_READ_MASK                  _MK_MASK_CONST(0xffffffff)
#define MISCREG_PROTO_CVRPTS_DATA6_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
#define MISCREG_PROTO_CVRPTS_DATA6_0_CVRPT_COUNT_SHIFT                  _MK_SHIFT_CONST(24)
#define MISCREG_PROTO_CVRPTS_DATA6_0_CVRPT_COUNT_FIELD                  _MK_FIELD_CONST(0xff, MISCREG_PROTO_CVRPTS_DATA6_0_CVRPT_COUNT_SHIFT)
#define MISCREG_PROTO_CVRPTS_DATA6_0_CVRPT_COUNT_RANGE                  31:24
#define MISCREG_PROTO_CVRPTS_DATA6_0_CVRPT_COUNT_WOFFSET                        0x0
#define MISCREG_PROTO_CVRPTS_DATA6_0_CVRPT_COUNT_DEFAULT                        _MK_MASK_CONST(0x0)
#define MISCREG_PROTO_CVRPTS_DATA6_0_CVRPT_COUNT_DEFAULT_MASK                   _MK_MASK_CONST(0xff)
#define MISCREG_PROTO_CVRPTS_DATA6_0_CVRPT_COUNT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define MISCREG_PROTO_CVRPTS_DATA6_0_CVRPT_COUNT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define MISCREG_PROTO_CVRPTS_DATA6_0_CVRPT_COUNT_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define MISCREG_PROTO_CVRPTS_DATA6_0_CVRPT_COUNT_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)

#define MISCREG_PROTO_CVRPTS_DATA6_0_CVRPT_TIMESTAMP_SHIFT                      _MK_SHIFT_CONST(0)
#define MISCREG_PROTO_CVRPTS_DATA6_0_CVRPT_TIMESTAMP_FIELD                      _MK_FIELD_CONST(0xffffff, MISCREG_PROTO_CVRPTS_DATA6_0_CVRPT_TIMESTAMP_SHIFT)
#define MISCREG_PROTO_CVRPTS_DATA6_0_CVRPT_TIMESTAMP_RANGE                      23:0
#define MISCREG_PROTO_CVRPTS_DATA6_0_CVRPT_TIMESTAMP_WOFFSET                    0x0
#define MISCREG_PROTO_CVRPTS_DATA6_0_CVRPT_TIMESTAMP_DEFAULT                    _MK_MASK_CONST(0x0)
#define MISCREG_PROTO_CVRPTS_DATA6_0_CVRPT_TIMESTAMP_DEFAULT_MASK                       _MK_MASK_CONST(0xffffff)
#define MISCREG_PROTO_CVRPTS_DATA6_0_CVRPT_TIMESTAMP_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define MISCREG_PROTO_CVRPTS_DATA6_0_CVRPT_TIMESTAMP_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define MISCREG_PROTO_CVRPTS_DATA6_0_CVRPT_TIMESTAMP_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define MISCREG_PROTO_CVRPTS_DATA6_0_CVRPT_TIMESTAMP_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)


// Register MISCREG_PROTO_CVRPTS_DATA7_0
#define MISCREG_PROTO_CVRPTS_DATA7_0                    _MK_ADDR_CONST(0x311c)
#define MISCREG_PROTO_CVRPTS_DATA7_0_SECURE                     0x0
#define MISCREG_PROTO_CVRPTS_DATA7_0_DUAL                       0x0
#define MISCREG_PROTO_CVRPTS_DATA7_0_SCR                        0
#define MISCREG_PROTO_CVRPTS_DATA7_0_WORD_COUNT                         0x1
#define MISCREG_PROTO_CVRPTS_DATA7_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define MISCREG_PROTO_CVRPTS_DATA7_0_RESET_MASK                         _MK_MASK_CONST(0xffffffff)
#define MISCREG_PROTO_CVRPTS_DATA7_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define MISCREG_PROTO_CVRPTS_DATA7_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define MISCREG_PROTO_CVRPTS_DATA7_0_READ_MASK                  _MK_MASK_CONST(0xffffffff)
#define MISCREG_PROTO_CVRPTS_DATA7_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
#define MISCREG_PROTO_CVRPTS_DATA7_0_CVRPT_COUNT_SHIFT                  _MK_SHIFT_CONST(24)
#define MISCREG_PROTO_CVRPTS_DATA7_0_CVRPT_COUNT_FIELD                  _MK_FIELD_CONST(0xff, MISCREG_PROTO_CVRPTS_DATA7_0_CVRPT_COUNT_SHIFT)
#define MISCREG_PROTO_CVRPTS_DATA7_0_CVRPT_COUNT_RANGE                  31:24
#define MISCREG_PROTO_CVRPTS_DATA7_0_CVRPT_COUNT_WOFFSET                        0x0
#define MISCREG_PROTO_CVRPTS_DATA7_0_CVRPT_COUNT_DEFAULT                        _MK_MASK_CONST(0x0)
#define MISCREG_PROTO_CVRPTS_DATA7_0_CVRPT_COUNT_DEFAULT_MASK                   _MK_MASK_CONST(0xff)
#define MISCREG_PROTO_CVRPTS_DATA7_0_CVRPT_COUNT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define MISCREG_PROTO_CVRPTS_DATA7_0_CVRPT_COUNT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define MISCREG_PROTO_CVRPTS_DATA7_0_CVRPT_COUNT_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define MISCREG_PROTO_CVRPTS_DATA7_0_CVRPT_COUNT_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)

#define MISCREG_PROTO_CVRPTS_DATA7_0_CVRPT_TIMESTAMP_SHIFT                      _MK_SHIFT_CONST(0)
#define MISCREG_PROTO_CVRPTS_DATA7_0_CVRPT_TIMESTAMP_FIELD                      _MK_FIELD_CONST(0xffffff, MISCREG_PROTO_CVRPTS_DATA7_0_CVRPT_TIMESTAMP_SHIFT)
#define MISCREG_PROTO_CVRPTS_DATA7_0_CVRPT_TIMESTAMP_RANGE                      23:0
#define MISCREG_PROTO_CVRPTS_DATA7_0_CVRPT_TIMESTAMP_WOFFSET                    0x0
#define MISCREG_PROTO_CVRPTS_DATA7_0_CVRPT_TIMESTAMP_DEFAULT                    _MK_MASK_CONST(0x0)
#define MISCREG_PROTO_CVRPTS_DATA7_0_CVRPT_TIMESTAMP_DEFAULT_MASK                       _MK_MASK_CONST(0xffffff)
#define MISCREG_PROTO_CVRPTS_DATA7_0_CVRPT_TIMESTAMP_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define MISCREG_PROTO_CVRPTS_DATA7_0_CVRPT_TIMESTAMP_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define MISCREG_PROTO_CVRPTS_DATA7_0_CVRPT_TIMESTAMP_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define MISCREG_PROTO_CVRPTS_DATA7_0_CVRPT_TIMESTAMP_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)


// Register MISCREG_PROTO_CVRPTS_RESET_0
#define MISCREG_PROTO_CVRPTS_RESET_0                    _MK_ADDR_CONST(0x3120)
#define MISCREG_PROTO_CVRPTS_RESET_0_SECURE                     0x0
#define MISCREG_PROTO_CVRPTS_RESET_0_DUAL                       0x0
#define MISCREG_PROTO_CVRPTS_RESET_0_SCR                        0
#define MISCREG_PROTO_CVRPTS_RESET_0_WORD_COUNT                         0x1
#define MISCREG_PROTO_CVRPTS_RESET_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define MISCREG_PROTO_CVRPTS_RESET_0_RESET_MASK                         _MK_MASK_CONST(0xffffffff)
#define MISCREG_PROTO_CVRPTS_RESET_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define MISCREG_PROTO_CVRPTS_RESET_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define MISCREG_PROTO_CVRPTS_RESET_0_READ_MASK                  _MK_MASK_CONST(0xffffffff)
#define MISCREG_PROTO_CVRPTS_RESET_0_WRITE_MASK                         _MK_MASK_CONST(0xffffffff)
#define MISCREG_PROTO_CVRPTS_RESET_0_CVRPT_RESET_SHIFT                  _MK_SHIFT_CONST(0)
#define MISCREG_PROTO_CVRPTS_RESET_0_CVRPT_RESET_FIELD                  _MK_FIELD_CONST(0xffffffff, MISCREG_PROTO_CVRPTS_RESET_0_CVRPT_RESET_SHIFT)
#define MISCREG_PROTO_CVRPTS_RESET_0_CVRPT_RESET_RANGE                  31:0
#define MISCREG_PROTO_CVRPTS_RESET_0_CVRPT_RESET_WOFFSET                        0x0
#define MISCREG_PROTO_CVRPTS_RESET_0_CVRPT_RESET_DEFAULT                        _MK_MASK_CONST(0x0)
#define MISCREG_PROTO_CVRPTS_RESET_0_CVRPT_RESET_DEFAULT_MASK                   _MK_MASK_CONST(0xffffffff)
#define MISCREG_PROTO_CVRPTS_RESET_0_CVRPT_RESET_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define MISCREG_PROTO_CVRPTS_RESET_0_CVRPT_RESET_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define MISCREG_PROTO_CVRPTS_RESET_0_CVRPT_RESET_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define MISCREG_PROTO_CVRPTS_RESET_0_CVRPT_RESET_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)


// Register MISCREG_PROTO_CVRPTS_STATUS_0
#define MISCREG_PROTO_CVRPTS_STATUS_0                   _MK_ADDR_CONST(0x3124)
#define MISCREG_PROTO_CVRPTS_STATUS_0_SECURE                    0x0
#define MISCREG_PROTO_CVRPTS_STATUS_0_DUAL                      0x0
#define MISCREG_PROTO_CVRPTS_STATUS_0_SCR                       0
#define MISCREG_PROTO_CVRPTS_STATUS_0_WORD_COUNT                        0x1
#define MISCREG_PROTO_CVRPTS_STATUS_0_RESET_VAL                         _MK_MASK_CONST(0x0)
#define MISCREG_PROTO_CVRPTS_STATUS_0_RESET_MASK                        _MK_MASK_CONST(0xffffffff)
#define MISCREG_PROTO_CVRPTS_STATUS_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define MISCREG_PROTO_CVRPTS_STATUS_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define MISCREG_PROTO_CVRPTS_STATUS_0_READ_MASK                         _MK_MASK_CONST(0xffffffff)
#define MISCREG_PROTO_CVRPTS_STATUS_0_WRITE_MASK                        _MK_MASK_CONST(0x0)
#define MISCREG_PROTO_CVRPTS_STATUS_0_CVRPT_STATUS_SHIFT                        _MK_SHIFT_CONST(0)
#define MISCREG_PROTO_CVRPTS_STATUS_0_CVRPT_STATUS_FIELD                        _MK_FIELD_CONST(0xffffffff, MISCREG_PROTO_CVRPTS_STATUS_0_CVRPT_STATUS_SHIFT)
#define MISCREG_PROTO_CVRPTS_STATUS_0_CVRPT_STATUS_RANGE                        31:0
#define MISCREG_PROTO_CVRPTS_STATUS_0_CVRPT_STATUS_WOFFSET                      0x0
#define MISCREG_PROTO_CVRPTS_STATUS_0_CVRPT_STATUS_DEFAULT                      _MK_MASK_CONST(0x0)
#define MISCREG_PROTO_CVRPTS_STATUS_0_CVRPT_STATUS_DEFAULT_MASK                 _MK_MASK_CONST(0xffffffff)
#define MISCREG_PROTO_CVRPTS_STATUS_0_CVRPT_STATUS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define MISCREG_PROTO_CVRPTS_STATUS_0_CVRPT_STATUS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define MISCREG_PROTO_CVRPTS_STATUS_0_CVRPT_STATUS_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define MISCREG_PROTO_CVRPTS_STATUS_0_CVRPT_STATUS_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)


// Register MISCREG_PROTO_PROT0_SCRATCH0_0
#define MISCREG_PROTO_PROT0_SCRATCH0_0                  _MK_ADDR_CONST(0x3128)
#define MISCREG_PROTO_PROT0_SCRATCH0_0_SECURE                   0x0
#define MISCREG_PROTO_PROT0_SCRATCH0_0_DUAL                     0x0
#define MISCREG_PROTO_PROT0_SCRATCH0_0_SCR                      0
#define MISCREG_PROTO_PROT0_SCRATCH0_0_WORD_COUNT                       0x1
#define MISCREG_PROTO_PROT0_SCRATCH0_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define MISCREG_PROTO_PROT0_SCRATCH0_0_RESET_MASK                       _MK_MASK_CONST(0xffffffff)
#define MISCREG_PROTO_PROT0_SCRATCH0_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define MISCREG_PROTO_PROT0_SCRATCH0_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define MISCREG_PROTO_PROT0_SCRATCH0_0_READ_MASK                        _MK_MASK_CONST(0xffffffff)
#define MISCREG_PROTO_PROT0_SCRATCH0_0_WRITE_MASK                       _MK_MASK_CONST(0xffffffff)
#define MISCREG_PROTO_PROT0_SCRATCH0_0_PROTO_SCRATCH_SHIFT                      _MK_SHIFT_CONST(0)
#define MISCREG_PROTO_PROT0_SCRATCH0_0_PROTO_SCRATCH_FIELD                      _MK_FIELD_CONST(0xffffffff, MISCREG_PROTO_PROT0_SCRATCH0_0_PROTO_SCRATCH_SHIFT)
#define MISCREG_PROTO_PROT0_SCRATCH0_0_PROTO_SCRATCH_RANGE                      31:0
#define MISCREG_PROTO_PROT0_SCRATCH0_0_PROTO_SCRATCH_WOFFSET                    0x0
#define MISCREG_PROTO_PROT0_SCRATCH0_0_PROTO_SCRATCH_DEFAULT                    _MK_MASK_CONST(0x0)
#define MISCREG_PROTO_PROT0_SCRATCH0_0_PROTO_SCRATCH_DEFAULT_MASK                       _MK_MASK_CONST(0xffffffff)
#define MISCREG_PROTO_PROT0_SCRATCH0_0_PROTO_SCRATCH_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define MISCREG_PROTO_PROT0_SCRATCH0_0_PROTO_SCRATCH_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define MISCREG_PROTO_PROT0_SCRATCH0_0_PROTO_SCRATCH_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define MISCREG_PROTO_PROT0_SCRATCH0_0_PROTO_SCRATCH_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)


// Register MISCREG_PROTO_PROT0_SCRATCH1_0
#define MISCREG_PROTO_PROT0_SCRATCH1_0                  _MK_ADDR_CONST(0x312c)
#define MISCREG_PROTO_PROT0_SCRATCH1_0_SECURE                   0x0
#define MISCREG_PROTO_PROT0_SCRATCH1_0_DUAL                     0x0
#define MISCREG_PROTO_PROT0_SCRATCH1_0_SCR                      0
#define MISCREG_PROTO_PROT0_SCRATCH1_0_WORD_COUNT                       0x1
#define MISCREG_PROTO_PROT0_SCRATCH1_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define MISCREG_PROTO_PROT0_SCRATCH1_0_RESET_MASK                       _MK_MASK_CONST(0xffffffff)
#define MISCREG_PROTO_PROT0_SCRATCH1_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define MISCREG_PROTO_PROT0_SCRATCH1_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define MISCREG_PROTO_PROT0_SCRATCH1_0_READ_MASK                        _MK_MASK_CONST(0xffffffff)
#define MISCREG_PROTO_PROT0_SCRATCH1_0_WRITE_MASK                       _MK_MASK_CONST(0xffffffff)
#define MISCREG_PROTO_PROT0_SCRATCH1_0_PROTO_SCRATCH_SHIFT                      _MK_SHIFT_CONST(0)
#define MISCREG_PROTO_PROT0_SCRATCH1_0_PROTO_SCRATCH_FIELD                      _MK_FIELD_CONST(0xffffffff, MISCREG_PROTO_PROT0_SCRATCH1_0_PROTO_SCRATCH_SHIFT)
#define MISCREG_PROTO_PROT0_SCRATCH1_0_PROTO_SCRATCH_RANGE                      31:0
#define MISCREG_PROTO_PROT0_SCRATCH1_0_PROTO_SCRATCH_WOFFSET                    0x0
#define MISCREG_PROTO_PROT0_SCRATCH1_0_PROTO_SCRATCH_DEFAULT                    _MK_MASK_CONST(0x0)
#define MISCREG_PROTO_PROT0_SCRATCH1_0_PROTO_SCRATCH_DEFAULT_MASK                       _MK_MASK_CONST(0xffffffff)
#define MISCREG_PROTO_PROT0_SCRATCH1_0_PROTO_SCRATCH_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define MISCREG_PROTO_PROT0_SCRATCH1_0_PROTO_SCRATCH_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define MISCREG_PROTO_PROT0_SCRATCH1_0_PROTO_SCRATCH_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define MISCREG_PROTO_PROT0_SCRATCH1_0_PROTO_SCRATCH_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)


// Register MISCREG_PROTO_PROT0_SCRATCH2_0
#define MISCREG_PROTO_PROT0_SCRATCH2_0                  _MK_ADDR_CONST(0x3130)
#define MISCREG_PROTO_PROT0_SCRATCH2_0_SECURE                   0x0
#define MISCREG_PROTO_PROT0_SCRATCH2_0_DUAL                     0x0
#define MISCREG_PROTO_PROT0_SCRATCH2_0_SCR                      0
#define MISCREG_PROTO_PROT0_SCRATCH2_0_WORD_COUNT                       0x1
#define MISCREG_PROTO_PROT0_SCRATCH2_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define MISCREG_PROTO_PROT0_SCRATCH2_0_RESET_MASK                       _MK_MASK_CONST(0xffffffff)
#define MISCREG_PROTO_PROT0_SCRATCH2_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define MISCREG_PROTO_PROT0_SCRATCH2_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define MISCREG_PROTO_PROT0_SCRATCH2_0_READ_MASK                        _MK_MASK_CONST(0xffffffff)
#define MISCREG_PROTO_PROT0_SCRATCH2_0_WRITE_MASK                       _MK_MASK_CONST(0xffffffff)
#define MISCREG_PROTO_PROT0_SCRATCH2_0_PROTO_SCRATCH_SHIFT                      _MK_SHIFT_CONST(0)
#define MISCREG_PROTO_PROT0_SCRATCH2_0_PROTO_SCRATCH_FIELD                      _MK_FIELD_CONST(0xffffffff, MISCREG_PROTO_PROT0_SCRATCH2_0_PROTO_SCRATCH_SHIFT)
#define MISCREG_PROTO_PROT0_SCRATCH2_0_PROTO_SCRATCH_RANGE                      31:0
#define MISCREG_PROTO_PROT0_SCRATCH2_0_PROTO_SCRATCH_WOFFSET                    0x0
#define MISCREG_PROTO_PROT0_SCRATCH2_0_PROTO_SCRATCH_DEFAULT                    _MK_MASK_CONST(0x0)
#define MISCREG_PROTO_PROT0_SCRATCH2_0_PROTO_SCRATCH_DEFAULT_MASK                       _MK_MASK_CONST(0xffffffff)
#define MISCREG_PROTO_PROT0_SCRATCH2_0_PROTO_SCRATCH_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define MISCREG_PROTO_PROT0_SCRATCH2_0_PROTO_SCRATCH_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define MISCREG_PROTO_PROT0_SCRATCH2_0_PROTO_SCRATCH_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define MISCREG_PROTO_PROT0_SCRATCH2_0_PROTO_SCRATCH_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)


// Register MISCREG_PROTO_PROT0_SCRATCH3_0
#define MISCREG_PROTO_PROT0_SCRATCH3_0                  _MK_ADDR_CONST(0x3134)
#define MISCREG_PROTO_PROT0_SCRATCH3_0_SECURE                   0x0
#define MISCREG_PROTO_PROT0_SCRATCH3_0_DUAL                     0x0
#define MISCREG_PROTO_PROT0_SCRATCH3_0_SCR                      0
#define MISCREG_PROTO_PROT0_SCRATCH3_0_WORD_COUNT                       0x1
#define MISCREG_PROTO_PROT0_SCRATCH3_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define MISCREG_PROTO_PROT0_SCRATCH3_0_RESET_MASK                       _MK_MASK_CONST(0xffffffff)
#define MISCREG_PROTO_PROT0_SCRATCH3_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define MISCREG_PROTO_PROT0_SCRATCH3_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define MISCREG_PROTO_PROT0_SCRATCH3_0_READ_MASK                        _MK_MASK_CONST(0xffffffff)
#define MISCREG_PROTO_PROT0_SCRATCH3_0_WRITE_MASK                       _MK_MASK_CONST(0xffffffff)
#define MISCREG_PROTO_PROT0_SCRATCH3_0_PROTO_SCRATCH_SHIFT                      _MK_SHIFT_CONST(0)
#define MISCREG_PROTO_PROT0_SCRATCH3_0_PROTO_SCRATCH_FIELD                      _MK_FIELD_CONST(0xffffffff, MISCREG_PROTO_PROT0_SCRATCH3_0_PROTO_SCRATCH_SHIFT)
#define MISCREG_PROTO_PROT0_SCRATCH3_0_PROTO_SCRATCH_RANGE                      31:0
#define MISCREG_PROTO_PROT0_SCRATCH3_0_PROTO_SCRATCH_WOFFSET                    0x0
#define MISCREG_PROTO_PROT0_SCRATCH3_0_PROTO_SCRATCH_DEFAULT                    _MK_MASK_CONST(0x0)
#define MISCREG_PROTO_PROT0_SCRATCH3_0_PROTO_SCRATCH_DEFAULT_MASK                       _MK_MASK_CONST(0xffffffff)
#define MISCREG_PROTO_PROT0_SCRATCH3_0_PROTO_SCRATCH_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define MISCREG_PROTO_PROT0_SCRATCH3_0_PROTO_SCRATCH_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define MISCREG_PROTO_PROT0_SCRATCH3_0_PROTO_SCRATCH_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define MISCREG_PROTO_PROT0_SCRATCH3_0_PROTO_SCRATCH_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)


// Register MISCREG_PROTO_PROT0_SCRATCH4_0
#define MISCREG_PROTO_PROT0_SCRATCH4_0                  _MK_ADDR_CONST(0x3138)
#define MISCREG_PROTO_PROT0_SCRATCH4_0_SECURE                   0x0
#define MISCREG_PROTO_PROT0_SCRATCH4_0_DUAL                     0x0
#define MISCREG_PROTO_PROT0_SCRATCH4_0_SCR                      0
#define MISCREG_PROTO_PROT0_SCRATCH4_0_WORD_COUNT                       0x1
#define MISCREG_PROTO_PROT0_SCRATCH4_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define MISCREG_PROTO_PROT0_SCRATCH4_0_RESET_MASK                       _MK_MASK_CONST(0xffffffff)
#define MISCREG_PROTO_PROT0_SCRATCH4_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define MISCREG_PROTO_PROT0_SCRATCH4_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define MISCREG_PROTO_PROT0_SCRATCH4_0_READ_MASK                        _MK_MASK_CONST(0xffffffff)
#define MISCREG_PROTO_PROT0_SCRATCH4_0_WRITE_MASK                       _MK_MASK_CONST(0xffffffff)
#define MISCREG_PROTO_PROT0_SCRATCH4_0_PROTO_SCRATCH_SHIFT                      _MK_SHIFT_CONST(0)
#define MISCREG_PROTO_PROT0_SCRATCH4_0_PROTO_SCRATCH_FIELD                      _MK_FIELD_CONST(0xffffffff, MISCREG_PROTO_PROT0_SCRATCH4_0_PROTO_SCRATCH_SHIFT)
#define MISCREG_PROTO_PROT0_SCRATCH4_0_PROTO_SCRATCH_RANGE                      31:0
#define MISCREG_PROTO_PROT0_SCRATCH4_0_PROTO_SCRATCH_WOFFSET                    0x0
#define MISCREG_PROTO_PROT0_SCRATCH4_0_PROTO_SCRATCH_DEFAULT                    _MK_MASK_CONST(0x0)
#define MISCREG_PROTO_PROT0_SCRATCH4_0_PROTO_SCRATCH_DEFAULT_MASK                       _MK_MASK_CONST(0xffffffff)
#define MISCREG_PROTO_PROT0_SCRATCH4_0_PROTO_SCRATCH_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define MISCREG_PROTO_PROT0_SCRATCH4_0_PROTO_SCRATCH_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define MISCREG_PROTO_PROT0_SCRATCH4_0_PROTO_SCRATCH_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define MISCREG_PROTO_PROT0_SCRATCH4_0_PROTO_SCRATCH_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)


// Register MISCREG_PROTO_PROT0_SCRATCH5_0
#define MISCREG_PROTO_PROT0_SCRATCH5_0                  _MK_ADDR_CONST(0x313c)
#define MISCREG_PROTO_PROT0_SCRATCH5_0_SECURE                   0x0
#define MISCREG_PROTO_PROT0_SCRATCH5_0_DUAL                     0x0
#define MISCREG_PROTO_PROT0_SCRATCH5_0_SCR                      0
#define MISCREG_PROTO_PROT0_SCRATCH5_0_WORD_COUNT                       0x1
#define MISCREG_PROTO_PROT0_SCRATCH5_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define MISCREG_PROTO_PROT0_SCRATCH5_0_RESET_MASK                       _MK_MASK_CONST(0xffffffff)
#define MISCREG_PROTO_PROT0_SCRATCH5_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define MISCREG_PROTO_PROT0_SCRATCH5_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define MISCREG_PROTO_PROT0_SCRATCH5_0_READ_MASK                        _MK_MASK_CONST(0xffffffff)
#define MISCREG_PROTO_PROT0_SCRATCH5_0_WRITE_MASK                       _MK_MASK_CONST(0xffffffff)
#define MISCREG_PROTO_PROT0_SCRATCH5_0_PROTO_SCRATCH_SHIFT                      _MK_SHIFT_CONST(0)
#define MISCREG_PROTO_PROT0_SCRATCH5_0_PROTO_SCRATCH_FIELD                      _MK_FIELD_CONST(0xffffffff, MISCREG_PROTO_PROT0_SCRATCH5_0_PROTO_SCRATCH_SHIFT)
#define MISCREG_PROTO_PROT0_SCRATCH5_0_PROTO_SCRATCH_RANGE                      31:0
#define MISCREG_PROTO_PROT0_SCRATCH5_0_PROTO_SCRATCH_WOFFSET                    0x0
#define MISCREG_PROTO_PROT0_SCRATCH5_0_PROTO_SCRATCH_DEFAULT                    _MK_MASK_CONST(0x0)
#define MISCREG_PROTO_PROT0_SCRATCH5_0_PROTO_SCRATCH_DEFAULT_MASK                       _MK_MASK_CONST(0xffffffff)
#define MISCREG_PROTO_PROT0_SCRATCH5_0_PROTO_SCRATCH_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define MISCREG_PROTO_PROT0_SCRATCH5_0_PROTO_SCRATCH_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define MISCREG_PROTO_PROT0_SCRATCH5_0_PROTO_SCRATCH_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define MISCREG_PROTO_PROT0_SCRATCH5_0_PROTO_SCRATCH_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)


// Register MISCREG_PROTO_PROT0_SCRATCH6_0
#define MISCREG_PROTO_PROT0_SCRATCH6_0                  _MK_ADDR_CONST(0x3140)
#define MISCREG_PROTO_PROT0_SCRATCH6_0_SECURE                   0x0
#define MISCREG_PROTO_PROT0_SCRATCH6_0_DUAL                     0x0
#define MISCREG_PROTO_PROT0_SCRATCH6_0_SCR                      0
#define MISCREG_PROTO_PROT0_SCRATCH6_0_WORD_COUNT                       0x1
#define MISCREG_PROTO_PROT0_SCRATCH6_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define MISCREG_PROTO_PROT0_SCRATCH6_0_RESET_MASK                       _MK_MASK_CONST(0xffffffff)
#define MISCREG_PROTO_PROT0_SCRATCH6_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define MISCREG_PROTO_PROT0_SCRATCH6_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define MISCREG_PROTO_PROT0_SCRATCH6_0_READ_MASK                        _MK_MASK_CONST(0xffffffff)
#define MISCREG_PROTO_PROT0_SCRATCH6_0_WRITE_MASK                       _MK_MASK_CONST(0xffffffff)
#define MISCREG_PROTO_PROT0_SCRATCH6_0_PROTO_SCRATCH_SHIFT                      _MK_SHIFT_CONST(0)
#define MISCREG_PROTO_PROT0_SCRATCH6_0_PROTO_SCRATCH_FIELD                      _MK_FIELD_CONST(0xffffffff, MISCREG_PROTO_PROT0_SCRATCH6_0_PROTO_SCRATCH_SHIFT)
#define MISCREG_PROTO_PROT0_SCRATCH6_0_PROTO_SCRATCH_RANGE                      31:0
#define MISCREG_PROTO_PROT0_SCRATCH6_0_PROTO_SCRATCH_WOFFSET                    0x0
#define MISCREG_PROTO_PROT0_SCRATCH6_0_PROTO_SCRATCH_DEFAULT                    _MK_MASK_CONST(0x0)
#define MISCREG_PROTO_PROT0_SCRATCH6_0_PROTO_SCRATCH_DEFAULT_MASK                       _MK_MASK_CONST(0xffffffff)
#define MISCREG_PROTO_PROT0_SCRATCH6_0_PROTO_SCRATCH_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define MISCREG_PROTO_PROT0_SCRATCH6_0_PROTO_SCRATCH_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define MISCREG_PROTO_PROT0_SCRATCH6_0_PROTO_SCRATCH_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define MISCREG_PROTO_PROT0_SCRATCH6_0_PROTO_SCRATCH_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)


// Register MISCREG_PROTO_PROT0_SCRATCH7_0
#define MISCREG_PROTO_PROT0_SCRATCH7_0                  _MK_ADDR_CONST(0x3144)
#define MISCREG_PROTO_PROT0_SCRATCH7_0_SECURE                   0x0
#define MISCREG_PROTO_PROT0_SCRATCH7_0_DUAL                     0x0
#define MISCREG_PROTO_PROT0_SCRATCH7_0_SCR                      0
#define MISCREG_PROTO_PROT0_SCRATCH7_0_WORD_COUNT                       0x1
#define MISCREG_PROTO_PROT0_SCRATCH7_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define MISCREG_PROTO_PROT0_SCRATCH7_0_RESET_MASK                       _MK_MASK_CONST(0xffffffff)
#define MISCREG_PROTO_PROT0_SCRATCH7_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define MISCREG_PROTO_PROT0_SCRATCH7_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define MISCREG_PROTO_PROT0_SCRATCH7_0_READ_MASK                        _MK_MASK_CONST(0xffffffff)
#define MISCREG_PROTO_PROT0_SCRATCH7_0_WRITE_MASK                       _MK_MASK_CONST(0xffffffff)
#define MISCREG_PROTO_PROT0_SCRATCH7_0_PROTO_SCRATCH_SHIFT                      _MK_SHIFT_CONST(0)
#define MISCREG_PROTO_PROT0_SCRATCH7_0_PROTO_SCRATCH_FIELD                      _MK_FIELD_CONST(0xffffffff, MISCREG_PROTO_PROT0_SCRATCH7_0_PROTO_SCRATCH_SHIFT)
#define MISCREG_PROTO_PROT0_SCRATCH7_0_PROTO_SCRATCH_RANGE                      31:0
#define MISCREG_PROTO_PROT0_SCRATCH7_0_PROTO_SCRATCH_WOFFSET                    0x0
#define MISCREG_PROTO_PROT0_SCRATCH7_0_PROTO_SCRATCH_DEFAULT                    _MK_MASK_CONST(0x0)
#define MISCREG_PROTO_PROT0_SCRATCH7_0_PROTO_SCRATCH_DEFAULT_MASK                       _MK_MASK_CONST(0xffffffff)
#define MISCREG_PROTO_PROT0_SCRATCH7_0_PROTO_SCRATCH_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define MISCREG_PROTO_PROT0_SCRATCH7_0_PROTO_SCRATCH_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define MISCREG_PROTO_PROT0_SCRATCH7_0_PROTO_SCRATCH_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define MISCREG_PROTO_PROT0_SCRATCH7_0_PROTO_SCRATCH_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)


// Reserved address 0x3148

// Reserved address 0x314c

// Reserved address 0x3150

// Register MISCREG_EMU_REVID_0
#define MISCREG_EMU_REVID_0                     _MK_ADDR_CONST(0x3160)
#define MISCREG_EMU_REVID_0_SECURE                      0x0
#define MISCREG_EMU_REVID_0_DUAL                        0x0
#define MISCREG_EMU_REVID_0_SCR                         0
#define MISCREG_EMU_REVID_0_WORD_COUNT                  0x1
#define MISCREG_EMU_REVID_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define MISCREG_EMU_REVID_0_RESET_MASK                  _MK_MASK_CONST(0x0)
#define MISCREG_EMU_REVID_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define MISCREG_EMU_REVID_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define MISCREG_EMU_REVID_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
#define MISCREG_EMU_REVID_0_WRITE_MASK                  _MK_MASK_CONST(0x0)
#define MISCREG_EMU_REVID_0_NETLIST_SHIFT                       _MK_SHIFT_CONST(0)
#define MISCREG_EMU_REVID_0_NETLIST_FIELD                       _MK_FIELD_CONST(0xff, MISCREG_EMU_REVID_0_NETLIST_SHIFT)
#define MISCREG_EMU_REVID_0_NETLIST_RANGE                       7:0
#define MISCREG_EMU_REVID_0_NETLIST_WOFFSET                     0x0
#define MISCREG_EMU_REVID_0_NETLIST_DEFAULT                     _MK_MASK_CONST(0x0)
#define MISCREG_EMU_REVID_0_NETLIST_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define MISCREG_EMU_REVID_0_NETLIST_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define MISCREG_EMU_REVID_0_NETLIST_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define MISCREG_EMU_REVID_0_NETLIST_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define MISCREG_EMU_REVID_0_NETLIST_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define MISCREG_EMU_REVID_0_PATCH_SHIFT                 _MK_SHIFT_CONST(8)
#define MISCREG_EMU_REVID_0_PATCH_FIELD                 _MK_FIELD_CONST(0xff, MISCREG_EMU_REVID_0_PATCH_SHIFT)
#define MISCREG_EMU_REVID_0_PATCH_RANGE                 15:8
#define MISCREG_EMU_REVID_0_PATCH_WOFFSET                       0x0
#define MISCREG_EMU_REVID_0_PATCH_DEFAULT                       _MK_MASK_CONST(0x0)
#define MISCREG_EMU_REVID_0_PATCH_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define MISCREG_EMU_REVID_0_PATCH_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define MISCREG_EMU_REVID_0_PATCH_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define MISCREG_EMU_REVID_0_PATCH_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define MISCREG_EMU_REVID_0_PATCH_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)

#define MISCREG_EMU_REVID_0_CORE_SHIFT                  _MK_SHIFT_CONST(16)
#define MISCREG_EMU_REVID_0_CORE_FIELD                  _MK_FIELD_CONST(0xff, MISCREG_EMU_REVID_0_CORE_SHIFT)
#define MISCREG_EMU_REVID_0_CORE_RANGE                  23:16
#define MISCREG_EMU_REVID_0_CORE_WOFFSET                        0x0
#define MISCREG_EMU_REVID_0_CORE_DEFAULT                        _MK_MASK_CONST(0x0)
#define MISCREG_EMU_REVID_0_CORE_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define MISCREG_EMU_REVID_0_CORE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define MISCREG_EMU_REVID_0_CORE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define MISCREG_EMU_REVID_0_CORE_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define MISCREG_EMU_REVID_0_CORE_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)

#define MISCREG_EMU_REVID_0_BOARD_SHIFT                 _MK_SHIFT_CONST(24)
#define MISCREG_EMU_REVID_0_BOARD_FIELD                 _MK_FIELD_CONST(0xff, MISCREG_EMU_REVID_0_BOARD_SHIFT)
#define MISCREG_EMU_REVID_0_BOARD_RANGE                 31:24
#define MISCREG_EMU_REVID_0_BOARD_WOFFSET                       0x0
#define MISCREG_EMU_REVID_0_BOARD_DEFAULT                       _MK_MASK_CONST(0x0)
#define MISCREG_EMU_REVID_0_BOARD_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define MISCREG_EMU_REVID_0_BOARD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define MISCREG_EMU_REVID_0_BOARD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define MISCREG_EMU_REVID_0_BOARD_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define MISCREG_EMU_REVID_0_BOARD_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)
#define MISCREG_EMU_REVID_0_BOARD_SYSTEM_FPGA_BASE                      _MK_ENUM_CONST(1)
#define MISCREG_EMU_REVID_0_BOARD_SYSTEM_FPGA_MAX                       _MK_ENUM_CONST(2)
#define MISCREG_EMU_REVID_0_BOARD_SYSTEM_FPGA_GPU                       _MK_ENUM_CONST(3)


// Register MISCREG_TRANSACTOR_SCRATCH_0
#define MISCREG_TRANSACTOR_SCRATCH_0                    _MK_ADDR_CONST(0x3164)
#define MISCREG_TRANSACTOR_SCRATCH_0_SECURE                     0x0
#define MISCREG_TRANSACTOR_SCRATCH_0_DUAL                       0x0
#define MISCREG_TRANSACTOR_SCRATCH_0_SCR                        0
#define MISCREG_TRANSACTOR_SCRATCH_0_WORD_COUNT                         0x1
#define MISCREG_TRANSACTOR_SCRATCH_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define MISCREG_TRANSACTOR_SCRATCH_0_RESET_MASK                         _MK_MASK_CONST(0xffffffff)
#define MISCREG_TRANSACTOR_SCRATCH_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define MISCREG_TRANSACTOR_SCRATCH_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define MISCREG_TRANSACTOR_SCRATCH_0_READ_MASK                  _MK_MASK_CONST(0xffffffff)
#define MISCREG_TRANSACTOR_SCRATCH_0_WRITE_MASK                         _MK_MASK_CONST(0xffffffff)
#define MISCREG_TRANSACTOR_SCRATCH_0_TRANSACTOR_SCRATCH_SHIFT                   _MK_SHIFT_CONST(0)
#define MISCREG_TRANSACTOR_SCRATCH_0_TRANSACTOR_SCRATCH_FIELD                   _MK_FIELD_CONST(0xffffffff, MISCREG_TRANSACTOR_SCRATCH_0_TRANSACTOR_SCRATCH_SHIFT)
#define MISCREG_TRANSACTOR_SCRATCH_0_TRANSACTOR_SCRATCH_RANGE                   31:0
#define MISCREG_TRANSACTOR_SCRATCH_0_TRANSACTOR_SCRATCH_WOFFSET                 0x0
#define MISCREG_TRANSACTOR_SCRATCH_0_TRANSACTOR_SCRATCH_DEFAULT                 _MK_MASK_CONST(0x0)
#define MISCREG_TRANSACTOR_SCRATCH_0_TRANSACTOR_SCRATCH_DEFAULT_MASK                    _MK_MASK_CONST(0xffffffff)
#define MISCREG_TRANSACTOR_SCRATCH_0_TRANSACTOR_SCRATCH_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define MISCREG_TRANSACTOR_SCRATCH_0_TRANSACTOR_SCRATCH_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define MISCREG_TRANSACTOR_SCRATCH_0_TRANSACTOR_SCRATCH_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define MISCREG_TRANSACTOR_SCRATCH_0_TRANSACTOR_SCRATCH_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)


// Register MISCREG_COP0_TRANSACTOR_SCRATCH_0
#define MISCREG_COP0_TRANSACTOR_SCRATCH_0                       _MK_ADDR_CONST(0x3180)
#define MISCREG_COP0_TRANSACTOR_SCRATCH_0_SECURE                        0x0
#define MISCREG_COP0_TRANSACTOR_SCRATCH_0_DUAL                  0x0
#define MISCREG_COP0_TRANSACTOR_SCRATCH_0_SCR                   0
#define MISCREG_COP0_TRANSACTOR_SCRATCH_0_WORD_COUNT                    0x1
#define MISCREG_COP0_TRANSACTOR_SCRATCH_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define MISCREG_COP0_TRANSACTOR_SCRATCH_0_RESET_MASK                    _MK_MASK_CONST(0xffffffff)
#define MISCREG_COP0_TRANSACTOR_SCRATCH_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define MISCREG_COP0_TRANSACTOR_SCRATCH_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define MISCREG_COP0_TRANSACTOR_SCRATCH_0_READ_MASK                     _MK_MASK_CONST(0xffffffff)
#define MISCREG_COP0_TRANSACTOR_SCRATCH_0_WRITE_MASK                    _MK_MASK_CONST(0xffffffff)
#define MISCREG_COP0_TRANSACTOR_SCRATCH_0_COP0_TRANSACTOR_SCRATCH_SHIFT                 _MK_SHIFT_CONST(0)
#define MISCREG_COP0_TRANSACTOR_SCRATCH_0_COP0_TRANSACTOR_SCRATCH_FIELD                 _MK_FIELD_CONST(0xffffffff, MISCREG_COP0_TRANSACTOR_SCRATCH_0_COP0_TRANSACTOR_SCRATCH_SHIFT)
#define MISCREG_COP0_TRANSACTOR_SCRATCH_0_COP0_TRANSACTOR_SCRATCH_RANGE                 31:0
#define MISCREG_COP0_TRANSACTOR_SCRATCH_0_COP0_TRANSACTOR_SCRATCH_WOFFSET                       0x0
#define MISCREG_COP0_TRANSACTOR_SCRATCH_0_COP0_TRANSACTOR_SCRATCH_DEFAULT                       _MK_MASK_CONST(0x0)
#define MISCREG_COP0_TRANSACTOR_SCRATCH_0_COP0_TRANSACTOR_SCRATCH_DEFAULT_MASK                  _MK_MASK_CONST(0xffffffff)
#define MISCREG_COP0_TRANSACTOR_SCRATCH_0_COP0_TRANSACTOR_SCRATCH_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define MISCREG_COP0_TRANSACTOR_SCRATCH_0_COP0_TRANSACTOR_SCRATCH_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define MISCREG_COP0_TRANSACTOR_SCRATCH_0_COP0_TRANSACTOR_SCRATCH_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define MISCREG_COP0_TRANSACTOR_SCRATCH_0_COP0_TRANSACTOR_SCRATCH_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)


// Register MISCREG_COP1_TRANSACTOR_SCRATCH_0
#define MISCREG_COP1_TRANSACTOR_SCRATCH_0                       _MK_ADDR_CONST(0x3184)
#define MISCREG_COP1_TRANSACTOR_SCRATCH_0_SECURE                        0x0
#define MISCREG_COP1_TRANSACTOR_SCRATCH_0_DUAL                  0x0
#define MISCREG_COP1_TRANSACTOR_SCRATCH_0_SCR                   0
#define MISCREG_COP1_TRANSACTOR_SCRATCH_0_WORD_COUNT                    0x1
#define MISCREG_COP1_TRANSACTOR_SCRATCH_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define MISCREG_COP1_TRANSACTOR_SCRATCH_0_RESET_MASK                    _MK_MASK_CONST(0xffffffff)
#define MISCREG_COP1_TRANSACTOR_SCRATCH_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define MISCREG_COP1_TRANSACTOR_SCRATCH_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define MISCREG_COP1_TRANSACTOR_SCRATCH_0_READ_MASK                     _MK_MASK_CONST(0xffffffff)
#define MISCREG_COP1_TRANSACTOR_SCRATCH_0_WRITE_MASK                    _MK_MASK_CONST(0xffffffff)
#define MISCREG_COP1_TRANSACTOR_SCRATCH_0_COP1_TRANSACTOR_SCRATCH_SHIFT                 _MK_SHIFT_CONST(0)
#define MISCREG_COP1_TRANSACTOR_SCRATCH_0_COP1_TRANSACTOR_SCRATCH_FIELD                 _MK_FIELD_CONST(0xffffffff, MISCREG_COP1_TRANSACTOR_SCRATCH_0_COP1_TRANSACTOR_SCRATCH_SHIFT)
#define MISCREG_COP1_TRANSACTOR_SCRATCH_0_COP1_TRANSACTOR_SCRATCH_RANGE                 31:0
#define MISCREG_COP1_TRANSACTOR_SCRATCH_0_COP1_TRANSACTOR_SCRATCH_WOFFSET                       0x0
#define MISCREG_COP1_TRANSACTOR_SCRATCH_0_COP1_TRANSACTOR_SCRATCH_DEFAULT                       _MK_MASK_CONST(0x0)
#define MISCREG_COP1_TRANSACTOR_SCRATCH_0_COP1_TRANSACTOR_SCRATCH_DEFAULT_MASK                  _MK_MASK_CONST(0xffffffff)
#define MISCREG_COP1_TRANSACTOR_SCRATCH_0_COP1_TRANSACTOR_SCRATCH_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define MISCREG_COP1_TRANSACTOR_SCRATCH_0_COP1_TRANSACTOR_SCRATCH_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define MISCREG_COP1_TRANSACTOR_SCRATCH_0_COP1_TRANSACTOR_SCRATCH_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define MISCREG_COP1_TRANSACTOR_SCRATCH_0_COP1_TRANSACTOR_SCRATCH_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)


// Register MISCREG_COP2_TRANSACTOR_SCRATCH_0
#define MISCREG_COP2_TRANSACTOR_SCRATCH_0                       _MK_ADDR_CONST(0x3188)
#define MISCREG_COP2_TRANSACTOR_SCRATCH_0_SECURE                        0x0
#define MISCREG_COP2_TRANSACTOR_SCRATCH_0_DUAL                  0x0
#define MISCREG_COP2_TRANSACTOR_SCRATCH_0_SCR                   0
#define MISCREG_COP2_TRANSACTOR_SCRATCH_0_WORD_COUNT                    0x1
#define MISCREG_COP2_TRANSACTOR_SCRATCH_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define MISCREG_COP2_TRANSACTOR_SCRATCH_0_RESET_MASK                    _MK_MASK_CONST(0xffffffff)
#define MISCREG_COP2_TRANSACTOR_SCRATCH_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define MISCREG_COP2_TRANSACTOR_SCRATCH_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define MISCREG_COP2_TRANSACTOR_SCRATCH_0_READ_MASK                     _MK_MASK_CONST(0xffffffff)
#define MISCREG_COP2_TRANSACTOR_SCRATCH_0_WRITE_MASK                    _MK_MASK_CONST(0xffffffff)
#define MISCREG_COP2_TRANSACTOR_SCRATCH_0_COP2_TRANSACTOR_SCRATCH_SHIFT                 _MK_SHIFT_CONST(0)
#define MISCREG_COP2_TRANSACTOR_SCRATCH_0_COP2_TRANSACTOR_SCRATCH_FIELD                 _MK_FIELD_CONST(0xffffffff, MISCREG_COP2_TRANSACTOR_SCRATCH_0_COP2_TRANSACTOR_SCRATCH_SHIFT)
#define MISCREG_COP2_TRANSACTOR_SCRATCH_0_COP2_TRANSACTOR_SCRATCH_RANGE                 31:0
#define MISCREG_COP2_TRANSACTOR_SCRATCH_0_COP2_TRANSACTOR_SCRATCH_WOFFSET                       0x0
#define MISCREG_COP2_TRANSACTOR_SCRATCH_0_COP2_TRANSACTOR_SCRATCH_DEFAULT                       _MK_MASK_CONST(0x0)
#define MISCREG_COP2_TRANSACTOR_SCRATCH_0_COP2_TRANSACTOR_SCRATCH_DEFAULT_MASK                  _MK_MASK_CONST(0xffffffff)
#define MISCREG_COP2_TRANSACTOR_SCRATCH_0_COP2_TRANSACTOR_SCRATCH_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define MISCREG_COP2_TRANSACTOR_SCRATCH_0_COP2_TRANSACTOR_SCRATCH_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define MISCREG_COP2_TRANSACTOR_SCRATCH_0_COP2_TRANSACTOR_SCRATCH_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define MISCREG_COP2_TRANSACTOR_SCRATCH_0_COP2_TRANSACTOR_SCRATCH_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)


// Register MISCREG_COP3_TRANSACTOR_SCRATCH_0
#define MISCREG_COP3_TRANSACTOR_SCRATCH_0                       _MK_ADDR_CONST(0x318c)
#define MISCREG_COP3_TRANSACTOR_SCRATCH_0_SECURE                        0x0
#define MISCREG_COP3_TRANSACTOR_SCRATCH_0_DUAL                  0x0
#define MISCREG_COP3_TRANSACTOR_SCRATCH_0_SCR                   0
#define MISCREG_COP3_TRANSACTOR_SCRATCH_0_WORD_COUNT                    0x1
#define MISCREG_COP3_TRANSACTOR_SCRATCH_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define MISCREG_COP3_TRANSACTOR_SCRATCH_0_RESET_MASK                    _MK_MASK_CONST(0xffffffff)
#define MISCREG_COP3_TRANSACTOR_SCRATCH_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define MISCREG_COP3_TRANSACTOR_SCRATCH_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define MISCREG_COP3_TRANSACTOR_SCRATCH_0_READ_MASK                     _MK_MASK_CONST(0xffffffff)
#define MISCREG_COP3_TRANSACTOR_SCRATCH_0_WRITE_MASK                    _MK_MASK_CONST(0xffffffff)
#define MISCREG_COP3_TRANSACTOR_SCRATCH_0_COP3_TRANSACTOR_SCRATCH_SHIFT                 _MK_SHIFT_CONST(0)
#define MISCREG_COP3_TRANSACTOR_SCRATCH_0_COP3_TRANSACTOR_SCRATCH_FIELD                 _MK_FIELD_CONST(0xffffffff, MISCREG_COP3_TRANSACTOR_SCRATCH_0_COP3_TRANSACTOR_SCRATCH_SHIFT)
#define MISCREG_COP3_TRANSACTOR_SCRATCH_0_COP3_TRANSACTOR_SCRATCH_RANGE                 31:0
#define MISCREG_COP3_TRANSACTOR_SCRATCH_0_COP3_TRANSACTOR_SCRATCH_WOFFSET                       0x0
#define MISCREG_COP3_TRANSACTOR_SCRATCH_0_COP3_TRANSACTOR_SCRATCH_DEFAULT                       _MK_MASK_CONST(0x0)
#define MISCREG_COP3_TRANSACTOR_SCRATCH_0_COP3_TRANSACTOR_SCRATCH_DEFAULT_MASK                  _MK_MASK_CONST(0xffffffff)
#define MISCREG_COP3_TRANSACTOR_SCRATCH_0_COP3_TRANSACTOR_SCRATCH_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define MISCREG_COP3_TRANSACTOR_SCRATCH_0_COP3_TRANSACTOR_SCRATCH_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define MISCREG_COP3_TRANSACTOR_SCRATCH_0_COP3_TRANSACTOR_SCRATCH_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define MISCREG_COP3_TRANSACTOR_SCRATCH_0_COP3_TRANSACTOR_SCRATCH_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)


// Register MISCREG_CPU0_TRANSACTOR_SCRATCH_0
#define MISCREG_CPU0_TRANSACTOR_SCRATCH_0                       _MK_ADDR_CONST(0x3190)
#define MISCREG_CPU0_TRANSACTOR_SCRATCH_0_SECURE                        0x0
#define MISCREG_CPU0_TRANSACTOR_SCRATCH_0_DUAL                  0x0
#define MISCREG_CPU0_TRANSACTOR_SCRATCH_0_SCR                   0
#define MISCREG_CPU0_TRANSACTOR_SCRATCH_0_WORD_COUNT                    0x1
#define MISCREG_CPU0_TRANSACTOR_SCRATCH_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define MISCREG_CPU0_TRANSACTOR_SCRATCH_0_RESET_MASK                    _MK_MASK_CONST(0xffffffff)
#define MISCREG_CPU0_TRANSACTOR_SCRATCH_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define MISCREG_CPU0_TRANSACTOR_SCRATCH_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define MISCREG_CPU0_TRANSACTOR_SCRATCH_0_READ_MASK                     _MK_MASK_CONST(0xffffffff)
#define MISCREG_CPU0_TRANSACTOR_SCRATCH_0_WRITE_MASK                    _MK_MASK_CONST(0xffffffff)
#define MISCREG_CPU0_TRANSACTOR_SCRATCH_0_CPU0_TRANSACTOR_SCRATCH_SHIFT                 _MK_SHIFT_CONST(0)
#define MISCREG_CPU0_TRANSACTOR_SCRATCH_0_CPU0_TRANSACTOR_SCRATCH_FIELD                 _MK_FIELD_CONST(0xffffffff, MISCREG_CPU0_TRANSACTOR_SCRATCH_0_CPU0_TRANSACTOR_SCRATCH_SHIFT)
#define MISCREG_CPU0_TRANSACTOR_SCRATCH_0_CPU0_TRANSACTOR_SCRATCH_RANGE                 31:0
#define MISCREG_CPU0_TRANSACTOR_SCRATCH_0_CPU0_TRANSACTOR_SCRATCH_WOFFSET                       0x0
#define MISCREG_CPU0_TRANSACTOR_SCRATCH_0_CPU0_TRANSACTOR_SCRATCH_DEFAULT                       _MK_MASK_CONST(0x0)
#define MISCREG_CPU0_TRANSACTOR_SCRATCH_0_CPU0_TRANSACTOR_SCRATCH_DEFAULT_MASK                  _MK_MASK_CONST(0xffffffff)
#define MISCREG_CPU0_TRANSACTOR_SCRATCH_0_CPU0_TRANSACTOR_SCRATCH_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define MISCREG_CPU0_TRANSACTOR_SCRATCH_0_CPU0_TRANSACTOR_SCRATCH_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define MISCREG_CPU0_TRANSACTOR_SCRATCH_0_CPU0_TRANSACTOR_SCRATCH_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define MISCREG_CPU0_TRANSACTOR_SCRATCH_0_CPU0_TRANSACTOR_SCRATCH_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)


// Register MISCREG_CPU1_TRANSACTOR_SCRATCH_0
#define MISCREG_CPU1_TRANSACTOR_SCRATCH_0                       _MK_ADDR_CONST(0x3194)
#define MISCREG_CPU1_TRANSACTOR_SCRATCH_0_SECURE                        0x0
#define MISCREG_CPU1_TRANSACTOR_SCRATCH_0_DUAL                  0x0
#define MISCREG_CPU1_TRANSACTOR_SCRATCH_0_SCR                   0
#define MISCREG_CPU1_TRANSACTOR_SCRATCH_0_WORD_COUNT                    0x1
#define MISCREG_CPU1_TRANSACTOR_SCRATCH_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define MISCREG_CPU1_TRANSACTOR_SCRATCH_0_RESET_MASK                    _MK_MASK_CONST(0xffffffff)
#define MISCREG_CPU1_TRANSACTOR_SCRATCH_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define MISCREG_CPU1_TRANSACTOR_SCRATCH_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define MISCREG_CPU1_TRANSACTOR_SCRATCH_0_READ_MASK                     _MK_MASK_CONST(0xffffffff)
#define MISCREG_CPU1_TRANSACTOR_SCRATCH_0_WRITE_MASK                    _MK_MASK_CONST(0xffffffff)
#define MISCREG_CPU1_TRANSACTOR_SCRATCH_0_CPU1_TRANSACTOR_SCRATCH_SHIFT                 _MK_SHIFT_CONST(0)
#define MISCREG_CPU1_TRANSACTOR_SCRATCH_0_CPU1_TRANSACTOR_SCRATCH_FIELD                 _MK_FIELD_CONST(0xffffffff, MISCREG_CPU1_TRANSACTOR_SCRATCH_0_CPU1_TRANSACTOR_SCRATCH_SHIFT)
#define MISCREG_CPU1_TRANSACTOR_SCRATCH_0_CPU1_TRANSACTOR_SCRATCH_RANGE                 31:0
#define MISCREG_CPU1_TRANSACTOR_SCRATCH_0_CPU1_TRANSACTOR_SCRATCH_WOFFSET                       0x0
#define MISCREG_CPU1_TRANSACTOR_SCRATCH_0_CPU1_TRANSACTOR_SCRATCH_DEFAULT                       _MK_MASK_CONST(0x0)
#define MISCREG_CPU1_TRANSACTOR_SCRATCH_0_CPU1_TRANSACTOR_SCRATCH_DEFAULT_MASK                  _MK_MASK_CONST(0xffffffff)
#define MISCREG_CPU1_TRANSACTOR_SCRATCH_0_CPU1_TRANSACTOR_SCRATCH_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define MISCREG_CPU1_TRANSACTOR_SCRATCH_0_CPU1_TRANSACTOR_SCRATCH_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define MISCREG_CPU1_TRANSACTOR_SCRATCH_0_CPU1_TRANSACTOR_SCRATCH_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define MISCREG_CPU1_TRANSACTOR_SCRATCH_0_CPU1_TRANSACTOR_SCRATCH_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)


// Register MISCREG_CPU2_TRANSACTOR_SCRATCH_0
#define MISCREG_CPU2_TRANSACTOR_SCRATCH_0                       _MK_ADDR_CONST(0x3198)
#define MISCREG_CPU2_TRANSACTOR_SCRATCH_0_SECURE                        0x0
#define MISCREG_CPU2_TRANSACTOR_SCRATCH_0_DUAL                  0x0
#define MISCREG_CPU2_TRANSACTOR_SCRATCH_0_SCR                   0
#define MISCREG_CPU2_TRANSACTOR_SCRATCH_0_WORD_COUNT                    0x1
#define MISCREG_CPU2_TRANSACTOR_SCRATCH_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define MISCREG_CPU2_TRANSACTOR_SCRATCH_0_RESET_MASK                    _MK_MASK_CONST(0xffffffff)
#define MISCREG_CPU2_TRANSACTOR_SCRATCH_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define MISCREG_CPU2_TRANSACTOR_SCRATCH_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define MISCREG_CPU2_TRANSACTOR_SCRATCH_0_READ_MASK                     _MK_MASK_CONST(0xffffffff)
#define MISCREG_CPU2_TRANSACTOR_SCRATCH_0_WRITE_MASK                    _MK_MASK_CONST(0xffffffff)
#define MISCREG_CPU2_TRANSACTOR_SCRATCH_0_CPU2_TRANSACTOR_SCRATCH_SHIFT                 _MK_SHIFT_CONST(0)
#define MISCREG_CPU2_TRANSACTOR_SCRATCH_0_CPU2_TRANSACTOR_SCRATCH_FIELD                 _MK_FIELD_CONST(0xffffffff, MISCREG_CPU2_TRANSACTOR_SCRATCH_0_CPU2_TRANSACTOR_SCRATCH_SHIFT)
#define MISCREG_CPU2_TRANSACTOR_SCRATCH_0_CPU2_TRANSACTOR_SCRATCH_RANGE                 31:0
#define MISCREG_CPU2_TRANSACTOR_SCRATCH_0_CPU2_TRANSACTOR_SCRATCH_WOFFSET                       0x0
#define MISCREG_CPU2_TRANSACTOR_SCRATCH_0_CPU2_TRANSACTOR_SCRATCH_DEFAULT                       _MK_MASK_CONST(0x0)
#define MISCREG_CPU2_TRANSACTOR_SCRATCH_0_CPU2_TRANSACTOR_SCRATCH_DEFAULT_MASK                  _MK_MASK_CONST(0xffffffff)
#define MISCREG_CPU2_TRANSACTOR_SCRATCH_0_CPU2_TRANSACTOR_SCRATCH_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define MISCREG_CPU2_TRANSACTOR_SCRATCH_0_CPU2_TRANSACTOR_SCRATCH_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define MISCREG_CPU2_TRANSACTOR_SCRATCH_0_CPU2_TRANSACTOR_SCRATCH_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define MISCREG_CPU2_TRANSACTOR_SCRATCH_0_CPU2_TRANSACTOR_SCRATCH_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)


// Register MISCREG_CPU3_TRANSACTOR_SCRATCH_0
#define MISCREG_CPU3_TRANSACTOR_SCRATCH_0                       _MK_ADDR_CONST(0x319c)
#define MISCREG_CPU3_TRANSACTOR_SCRATCH_0_SECURE                        0x0
#define MISCREG_CPU3_TRANSACTOR_SCRATCH_0_DUAL                  0x0
#define MISCREG_CPU3_TRANSACTOR_SCRATCH_0_SCR                   0
#define MISCREG_CPU3_TRANSACTOR_SCRATCH_0_WORD_COUNT                    0x1
#define MISCREG_CPU3_TRANSACTOR_SCRATCH_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define MISCREG_CPU3_TRANSACTOR_SCRATCH_0_RESET_MASK                    _MK_MASK_CONST(0xffffffff)
#define MISCREG_CPU3_TRANSACTOR_SCRATCH_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define MISCREG_CPU3_TRANSACTOR_SCRATCH_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define MISCREG_CPU3_TRANSACTOR_SCRATCH_0_READ_MASK                     _MK_MASK_CONST(0xffffffff)
#define MISCREG_CPU3_TRANSACTOR_SCRATCH_0_WRITE_MASK                    _MK_MASK_CONST(0xffffffff)
#define MISCREG_CPU3_TRANSACTOR_SCRATCH_0_CPU3_TRANSACTOR_SCRATCH_SHIFT                 _MK_SHIFT_CONST(0)
#define MISCREG_CPU3_TRANSACTOR_SCRATCH_0_CPU3_TRANSACTOR_SCRATCH_FIELD                 _MK_FIELD_CONST(0xffffffff, MISCREG_CPU3_TRANSACTOR_SCRATCH_0_CPU3_TRANSACTOR_SCRATCH_SHIFT)
#define MISCREG_CPU3_TRANSACTOR_SCRATCH_0_CPU3_TRANSACTOR_SCRATCH_RANGE                 31:0
#define MISCREG_CPU3_TRANSACTOR_SCRATCH_0_CPU3_TRANSACTOR_SCRATCH_WOFFSET                       0x0
#define MISCREG_CPU3_TRANSACTOR_SCRATCH_0_CPU3_TRANSACTOR_SCRATCH_DEFAULT                       _MK_MASK_CONST(0x0)
#define MISCREG_CPU3_TRANSACTOR_SCRATCH_0_CPU3_TRANSACTOR_SCRATCH_DEFAULT_MASK                  _MK_MASK_CONST(0xffffffff)
#define MISCREG_CPU3_TRANSACTOR_SCRATCH_0_CPU3_TRANSACTOR_SCRATCH_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define MISCREG_CPU3_TRANSACTOR_SCRATCH_0_CPU3_TRANSACTOR_SCRATCH_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define MISCREG_CPU3_TRANSACTOR_SCRATCH_0_CPU3_TRANSACTOR_SCRATCH_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define MISCREG_CPU3_TRANSACTOR_SCRATCH_0_CPU3_TRANSACTOR_SCRATCH_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)


// Register MISCREG_CPU4_TRANSACTOR_SCRATCH_0
#define MISCREG_CPU4_TRANSACTOR_SCRATCH_0                       _MK_ADDR_CONST(0x31a0)
#define MISCREG_CPU4_TRANSACTOR_SCRATCH_0_SECURE                        0x0
#define MISCREG_CPU4_TRANSACTOR_SCRATCH_0_DUAL                  0x0
#define MISCREG_CPU4_TRANSACTOR_SCRATCH_0_SCR                   0
#define MISCREG_CPU4_TRANSACTOR_SCRATCH_0_WORD_COUNT                    0x1
#define MISCREG_CPU4_TRANSACTOR_SCRATCH_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define MISCREG_CPU4_TRANSACTOR_SCRATCH_0_RESET_MASK                    _MK_MASK_CONST(0xffffffff)
#define MISCREG_CPU4_TRANSACTOR_SCRATCH_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define MISCREG_CPU4_TRANSACTOR_SCRATCH_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define MISCREG_CPU4_TRANSACTOR_SCRATCH_0_READ_MASK                     _MK_MASK_CONST(0xffffffff)
#define MISCREG_CPU4_TRANSACTOR_SCRATCH_0_WRITE_MASK                    _MK_MASK_CONST(0xffffffff)
#define MISCREG_CPU4_TRANSACTOR_SCRATCH_0_CPU4_TRANSACTOR_SCRATCH_SHIFT                 _MK_SHIFT_CONST(0)
#define MISCREG_CPU4_TRANSACTOR_SCRATCH_0_CPU4_TRANSACTOR_SCRATCH_FIELD                 _MK_FIELD_CONST(0xffffffff, MISCREG_CPU4_TRANSACTOR_SCRATCH_0_CPU4_TRANSACTOR_SCRATCH_SHIFT)
#define MISCREG_CPU4_TRANSACTOR_SCRATCH_0_CPU4_TRANSACTOR_SCRATCH_RANGE                 31:0
#define MISCREG_CPU4_TRANSACTOR_SCRATCH_0_CPU4_TRANSACTOR_SCRATCH_WOFFSET                       0x0
#define MISCREG_CPU4_TRANSACTOR_SCRATCH_0_CPU4_TRANSACTOR_SCRATCH_DEFAULT                       _MK_MASK_CONST(0x0)
#define MISCREG_CPU4_TRANSACTOR_SCRATCH_0_CPU4_TRANSACTOR_SCRATCH_DEFAULT_MASK                  _MK_MASK_CONST(0xffffffff)
#define MISCREG_CPU4_TRANSACTOR_SCRATCH_0_CPU4_TRANSACTOR_SCRATCH_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define MISCREG_CPU4_TRANSACTOR_SCRATCH_0_CPU4_TRANSACTOR_SCRATCH_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define MISCREG_CPU4_TRANSACTOR_SCRATCH_0_CPU4_TRANSACTOR_SCRATCH_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define MISCREG_CPU4_TRANSACTOR_SCRATCH_0_CPU4_TRANSACTOR_SCRATCH_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)


// Register MISCREG_CPU5_TRANSACTOR_SCRATCH_0
#define MISCREG_CPU5_TRANSACTOR_SCRATCH_0                       _MK_ADDR_CONST(0x31a4)
#define MISCREG_CPU5_TRANSACTOR_SCRATCH_0_SECURE                        0x0
#define MISCREG_CPU5_TRANSACTOR_SCRATCH_0_DUAL                  0x0
#define MISCREG_CPU5_TRANSACTOR_SCRATCH_0_SCR                   0
#define MISCREG_CPU5_TRANSACTOR_SCRATCH_0_WORD_COUNT                    0x1
#define MISCREG_CPU5_TRANSACTOR_SCRATCH_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define MISCREG_CPU5_TRANSACTOR_SCRATCH_0_RESET_MASK                    _MK_MASK_CONST(0xffffffff)
#define MISCREG_CPU5_TRANSACTOR_SCRATCH_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define MISCREG_CPU5_TRANSACTOR_SCRATCH_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define MISCREG_CPU5_TRANSACTOR_SCRATCH_0_READ_MASK                     _MK_MASK_CONST(0xffffffff)
#define MISCREG_CPU5_TRANSACTOR_SCRATCH_0_WRITE_MASK                    _MK_MASK_CONST(0xffffffff)
#define MISCREG_CPU5_TRANSACTOR_SCRATCH_0_CPU5_TRANSACTOR_SCRATCH_SHIFT                 _MK_SHIFT_CONST(0)
#define MISCREG_CPU5_TRANSACTOR_SCRATCH_0_CPU5_TRANSACTOR_SCRATCH_FIELD                 _MK_FIELD_CONST(0xffffffff, MISCREG_CPU5_TRANSACTOR_SCRATCH_0_CPU5_TRANSACTOR_SCRATCH_SHIFT)
#define MISCREG_CPU5_TRANSACTOR_SCRATCH_0_CPU5_TRANSACTOR_SCRATCH_RANGE                 31:0
#define MISCREG_CPU5_TRANSACTOR_SCRATCH_0_CPU5_TRANSACTOR_SCRATCH_WOFFSET                       0x0
#define MISCREG_CPU5_TRANSACTOR_SCRATCH_0_CPU5_TRANSACTOR_SCRATCH_DEFAULT                       _MK_MASK_CONST(0x0)
#define MISCREG_CPU5_TRANSACTOR_SCRATCH_0_CPU5_TRANSACTOR_SCRATCH_DEFAULT_MASK                  _MK_MASK_CONST(0xffffffff)
#define MISCREG_CPU5_TRANSACTOR_SCRATCH_0_CPU5_TRANSACTOR_SCRATCH_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define MISCREG_CPU5_TRANSACTOR_SCRATCH_0_CPU5_TRANSACTOR_SCRATCH_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define MISCREG_CPU5_TRANSACTOR_SCRATCH_0_CPU5_TRANSACTOR_SCRATCH_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define MISCREG_CPU5_TRANSACTOR_SCRATCH_0_CPU5_TRANSACTOR_SCRATCH_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)


// Reserved address 0x31a8

// Register MISCREG_MISC_SPARE_REG_0
#define MISCREG_MISC_SPARE_REG_0                        _MK_ADDR_CONST(0x31ac)
#define MISCREG_MISC_SPARE_REG_0_SECURE                         0x0
#define MISCREG_MISC_SPARE_REG_0_DUAL                   0x0
#define MISCREG_MISC_SPARE_REG_0_SCR                    0
#define MISCREG_MISC_SPARE_REG_0_WORD_COUNT                     0x1
#define MISCREG_MISC_SPARE_REG_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define MISCREG_MISC_SPARE_REG_0_RESET_MASK                     _MK_MASK_CONST(0xffffffff)
#define MISCREG_MISC_SPARE_REG_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define MISCREG_MISC_SPARE_REG_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define MISCREG_MISC_SPARE_REG_0_READ_MASK                      _MK_MASK_CONST(0xffffffff)
#define MISCREG_MISC_SPARE_REG_0_WRITE_MASK                     _MK_MASK_CONST(0xffffffff)
#define MISCREG_MISC_SPARE_REG_0_MISC_SPARE_REG_SHIFT                   _MK_SHIFT_CONST(0)
#define MISCREG_MISC_SPARE_REG_0_MISC_SPARE_REG_FIELD                   _MK_FIELD_CONST(0xffffffff, MISCREG_MISC_SPARE_REG_0_MISC_SPARE_REG_SHIFT)
#define MISCREG_MISC_SPARE_REG_0_MISC_SPARE_REG_RANGE                   31:0
#define MISCREG_MISC_SPARE_REG_0_MISC_SPARE_REG_WOFFSET                 0x0
#define MISCREG_MISC_SPARE_REG_0_MISC_SPARE_REG_DEFAULT                 _MK_MASK_CONST(0x0)
#define MISCREG_MISC_SPARE_REG_0_MISC_SPARE_REG_DEFAULT_MASK                    _MK_MASK_CONST(0xffffffff)
#define MISCREG_MISC_SPARE_REG_0_MISC_SPARE_REG_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define MISCREG_MISC_SPARE_REG_0_MISC_SPARE_REG_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define MISCREG_MISC_SPARE_REG_0_MISC_SPARE_REG_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define MISCREG_MISC_SPARE_REG_0_MISC_SPARE_REG_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)


// Register MISCREG_STRAP_STRAPPING_OPT_A_0
#define MISCREG_STRAP_STRAPPING_OPT_A_0                 _MK_ADDR_CONST(0xf000)
#define MISCREG_STRAP_STRAPPING_OPT_A_0_SECURE                  0x0
#define MISCREG_STRAP_STRAPPING_OPT_A_0_DUAL                    0x0
#define MISCREG_STRAP_STRAPPING_OPT_A_0_SCR                     0
#define MISCREG_STRAP_STRAPPING_OPT_A_0_WORD_COUNT                      0x1
#define MISCREG_STRAP_STRAPPING_OPT_A_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define MISCREG_STRAP_STRAPPING_OPT_A_0_RESET_MASK                      _MK_MASK_CONST(0x20000301)
#define MISCREG_STRAP_STRAPPING_OPT_A_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define MISCREG_STRAP_STRAPPING_OPT_A_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define MISCREG_STRAP_STRAPPING_OPT_A_0_READ_MASK                       _MK_MASK_CONST(0x3c003ff1)
#define MISCREG_STRAP_STRAPPING_OPT_A_0_WRITE_MASK                      _MK_MASK_CONST(0x3c003ff1)
#define MISCREG_STRAP_STRAPPING_OPT_A_0_UFS_SEL_SHIFT                   _MK_SHIFT_CONST(29)
#define MISCREG_STRAP_STRAPPING_OPT_A_0_UFS_SEL_FIELD                   _MK_FIELD_CONST(0x1, MISCREG_STRAP_STRAPPING_OPT_A_0_UFS_SEL_SHIFT)
#define MISCREG_STRAP_STRAPPING_OPT_A_0_UFS_SEL_RANGE                   29:29
#define MISCREG_STRAP_STRAPPING_OPT_A_0_UFS_SEL_WOFFSET                 0x0
#define MISCREG_STRAP_STRAPPING_OPT_A_0_UFS_SEL_DEFAULT                 _MK_MASK_CONST(0x0)
#define MISCREG_STRAP_STRAPPING_OPT_A_0_UFS_SEL_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define MISCREG_STRAP_STRAPPING_OPT_A_0_UFS_SEL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define MISCREG_STRAP_STRAPPING_OPT_A_0_UFS_SEL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define MISCREG_STRAP_STRAPPING_OPT_A_0_UFS_SEL_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define MISCREG_STRAP_STRAPPING_OPT_A_0_UFS_SEL_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define MISCREG_STRAP_STRAPPING_OPT_A_0_UFS_SEL_INIT_ENUM                       E12V
#define MISCREG_STRAP_STRAPPING_OPT_A_0_UFS_SEL_E12V                    _MK_ENUM_CONST(0)
#define MISCREG_STRAP_STRAPPING_OPT_A_0_UFS_SEL_E18V                    _MK_ENUM_CONST(1)

#define MISCREG_STRAP_STRAPPING_OPT_A_0_BOOT_SELECT_SHIFT                       _MK_SHIFT_CONST(26)
#define MISCREG_STRAP_STRAPPING_OPT_A_0_BOOT_SELECT_FIELD                       _MK_FIELD_CONST(0x7, MISCREG_STRAP_STRAPPING_OPT_A_0_BOOT_SELECT_SHIFT)
#define MISCREG_STRAP_STRAPPING_OPT_A_0_BOOT_SELECT_RANGE                       28:26
#define MISCREG_STRAP_STRAPPING_OPT_A_0_BOOT_SELECT_WOFFSET                     0x0
#define MISCREG_STRAP_STRAPPING_OPT_A_0_BOOT_SELECT_DEFAULT                     _MK_MASK_CONST(0x0)
#define MISCREG_STRAP_STRAPPING_OPT_A_0_BOOT_SELECT_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define MISCREG_STRAP_STRAPPING_OPT_A_0_BOOT_SELECT_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define MISCREG_STRAP_STRAPPING_OPT_A_0_BOOT_SELECT_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define MISCREG_STRAP_STRAPPING_OPT_A_0_BOOT_SELECT_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define MISCREG_STRAP_STRAPPING_OPT_A_0_BOOT_SELECT_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define MISCREG_STRAP_STRAPPING_OPT_A_0_NVPROD_UART_SHIFT                       _MK_SHIFT_CONST(13)
#define MISCREG_STRAP_STRAPPING_OPT_A_0_NVPROD_UART_FIELD                       _MK_FIELD_CONST(0x1, MISCREG_STRAP_STRAPPING_OPT_A_0_NVPROD_UART_SHIFT)
#define MISCREG_STRAP_STRAPPING_OPT_A_0_NVPROD_UART_RANGE                       13:13
#define MISCREG_STRAP_STRAPPING_OPT_A_0_NVPROD_UART_WOFFSET                     0x0
#define MISCREG_STRAP_STRAPPING_OPT_A_0_NVPROD_UART_DEFAULT                     _MK_MASK_CONST(0x0)
#define MISCREG_STRAP_STRAPPING_OPT_A_0_NVPROD_UART_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define MISCREG_STRAP_STRAPPING_OPT_A_0_NVPROD_UART_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define MISCREG_STRAP_STRAPPING_OPT_A_0_NVPROD_UART_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define MISCREG_STRAP_STRAPPING_OPT_A_0_NVPROD_UART_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define MISCREG_STRAP_STRAPPING_OPT_A_0_NVPROD_UART_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define MISCREG_STRAP_STRAPPING_OPT_A_0_RCM_STRAPS_SHIFT                        _MK_SHIFT_CONST(10)
#define MISCREG_STRAP_STRAPPING_OPT_A_0_RCM_STRAPS_FIELD                        _MK_FIELD_CONST(0x7, MISCREG_STRAP_STRAPPING_OPT_A_0_RCM_STRAPS_SHIFT)
#define MISCREG_STRAP_STRAPPING_OPT_A_0_RCM_STRAPS_RANGE                        12:10
#define MISCREG_STRAP_STRAPPING_OPT_A_0_RCM_STRAPS_WOFFSET                      0x0
#define MISCREG_STRAP_STRAPPING_OPT_A_0_RCM_STRAPS_DEFAULT                      _MK_MASK_CONST(0x0)
#define MISCREG_STRAP_STRAPPING_OPT_A_0_RCM_STRAPS_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define MISCREG_STRAP_STRAPPING_OPT_A_0_RCM_STRAPS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define MISCREG_STRAP_STRAPPING_OPT_A_0_RCM_STRAPS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define MISCREG_STRAP_STRAPPING_OPT_A_0_RCM_STRAPS_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define MISCREG_STRAP_STRAPPING_OPT_A_0_RCM_STRAPS_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define MISCREG_STRAP_STRAPPING_OPT_A_0_BOOT_FAST_UART_SHIFT                    _MK_SHIFT_CONST(9)
#define MISCREG_STRAP_STRAPPING_OPT_A_0_BOOT_FAST_UART_FIELD                    _MK_FIELD_CONST(0x1, MISCREG_STRAP_STRAPPING_OPT_A_0_BOOT_FAST_UART_SHIFT)
#define MISCREG_STRAP_STRAPPING_OPT_A_0_BOOT_FAST_UART_RANGE                    9:9
#define MISCREG_STRAP_STRAPPING_OPT_A_0_BOOT_FAST_UART_WOFFSET                  0x0
#define MISCREG_STRAP_STRAPPING_OPT_A_0_BOOT_FAST_UART_DEFAULT                  _MK_MASK_CONST(0x0)
#define MISCREG_STRAP_STRAPPING_OPT_A_0_BOOT_FAST_UART_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define MISCREG_STRAP_STRAPPING_OPT_A_0_BOOT_FAST_UART_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define MISCREG_STRAP_STRAPPING_OPT_A_0_BOOT_FAST_UART_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define MISCREG_STRAP_STRAPPING_OPT_A_0_BOOT_FAST_UART_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define MISCREG_STRAP_STRAPPING_OPT_A_0_BOOT_FAST_UART_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)
#define MISCREG_STRAP_STRAPPING_OPT_A_0_BOOT_FAST_UART_SLOW                     _MK_ENUM_CONST(0)
#define MISCREG_STRAP_STRAPPING_OPT_A_0_BOOT_FAST_UART_FAST                     _MK_ENUM_CONST(1)

#define MISCREG_STRAP_STRAPPING_OPT_A_0_MIO_WIDTH_SHIFT                 _MK_SHIFT_CONST(8)
#define MISCREG_STRAP_STRAPPING_OPT_A_0_MIO_WIDTH_FIELD                 _MK_FIELD_CONST(0x1, MISCREG_STRAP_STRAPPING_OPT_A_0_MIO_WIDTH_SHIFT)
#define MISCREG_STRAP_STRAPPING_OPT_A_0_MIO_WIDTH_RANGE                 8:8
#define MISCREG_STRAP_STRAPPING_OPT_A_0_MIO_WIDTH_WOFFSET                       0x0
#define MISCREG_STRAP_STRAPPING_OPT_A_0_MIO_WIDTH_DEFAULT                       _MK_MASK_CONST(0x0)
#define MISCREG_STRAP_STRAPPING_OPT_A_0_MIO_WIDTH_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define MISCREG_STRAP_STRAPPING_OPT_A_0_MIO_WIDTH_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define MISCREG_STRAP_STRAPPING_OPT_A_0_MIO_WIDTH_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define MISCREG_STRAP_STRAPPING_OPT_A_0_MIO_WIDTH_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define MISCREG_STRAP_STRAPPING_OPT_A_0_MIO_WIDTH_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)
#define MISCREG_STRAP_STRAPPING_OPT_A_0_MIO_WIDTH_INIT_ENUM                     RSVD1
#define MISCREG_STRAP_STRAPPING_OPT_A_0_MIO_WIDTH_RSVD1                 _MK_ENUM_CONST(0)
#define MISCREG_STRAP_STRAPPING_OPT_A_0_MIO_WIDTH_RSVD2                 _MK_ENUM_CONST(1)

#define MISCREG_STRAP_STRAPPING_OPT_A_0_RAM_CODE_SHIFT                  _MK_SHIFT_CONST(4)
#define MISCREG_STRAP_STRAPPING_OPT_A_0_RAM_CODE_FIELD                  _MK_FIELD_CONST(0xf, MISCREG_STRAP_STRAPPING_OPT_A_0_RAM_CODE_SHIFT)
#define MISCREG_STRAP_STRAPPING_OPT_A_0_RAM_CODE_RANGE                  7:4
#define MISCREG_STRAP_STRAPPING_OPT_A_0_RAM_CODE_WOFFSET                        0x0
#define MISCREG_STRAP_STRAPPING_OPT_A_0_RAM_CODE_DEFAULT                        _MK_MASK_CONST(0x0)
#define MISCREG_STRAP_STRAPPING_OPT_A_0_RAM_CODE_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define MISCREG_STRAP_STRAPPING_OPT_A_0_RAM_CODE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define MISCREG_STRAP_STRAPPING_OPT_A_0_RAM_CODE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define MISCREG_STRAP_STRAPPING_OPT_A_0_RAM_CODE_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define MISCREG_STRAP_STRAPPING_OPT_A_0_RAM_CODE_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)

#define MISCREG_STRAP_STRAPPING_OPT_A_0_NOR_WIDTH_SHIFT                 _MK_SHIFT_CONST(0)
#define MISCREG_STRAP_STRAPPING_OPT_A_0_NOR_WIDTH_FIELD                 _MK_FIELD_CONST(0x1, MISCREG_STRAP_STRAPPING_OPT_A_0_NOR_WIDTH_SHIFT)
#define MISCREG_STRAP_STRAPPING_OPT_A_0_NOR_WIDTH_RANGE                 0:0
#define MISCREG_STRAP_STRAPPING_OPT_A_0_NOR_WIDTH_WOFFSET                       0x0
#define MISCREG_STRAP_STRAPPING_OPT_A_0_NOR_WIDTH_DEFAULT                       _MK_MASK_CONST(0x0)
#define MISCREG_STRAP_STRAPPING_OPT_A_0_NOR_WIDTH_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define MISCREG_STRAP_STRAPPING_OPT_A_0_NOR_WIDTH_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define MISCREG_STRAP_STRAPPING_OPT_A_0_NOR_WIDTH_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define MISCREG_STRAP_STRAPPING_OPT_A_0_NOR_WIDTH_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define MISCREG_STRAP_STRAPPING_OPT_A_0_NOR_WIDTH_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)
#define MISCREG_STRAP_STRAPPING_OPT_A_0_NOR_WIDTH_INIT_ENUM                     RSVD1
#define MISCREG_STRAP_STRAPPING_OPT_A_0_NOR_WIDTH_RSVD1                 _MK_ENUM_CONST(0)
#define MISCREG_STRAP_STRAPPING_OPT_A_0_NOR_WIDTH_RSVD2                 _MK_ENUM_CONST(1)


//
// REGISTER LIST
//
#define LIST_ARMISCREG_REGS(_op_) \
_op_(MISCREG_MODS_REDIRCT_0) \
_op_(MISCREG_HIDREV_0) \
_op_(MISCREG_NVDEC1_HS_SECURITY_0) \
_op_(MISCREG_NVDEC1_LS_SECURITY_0) \
_op_(MISCREG_BPMP_SECURITY_0) \
_op_(MISCREG_CPU_SECURITY_0) \
_op_(MISCREG_APE_SECURITY_0) \
_op_(MISCREG_GPCDMA_SECURITY_0) \
_op_(MISCREG_SCE_SECURITY_0) \
_op_(MISCREG_SPE_SECURITY_0) \
_op_(MISCREG_TSECA_HS_SECURITY_0) \
_op_(MISCREG_TSECA_LS_SECURITY_0) \
_op_(MISCREG_TSECB_HS_SECURITY_0) \
_op_(MISCREG_TSECB_LS_SECURITY_0) \
_op_(MISCREG_JTAGM_SECURITY_0) \
_op_(MISCREG_CSITE_SECURITY_0) \
_op_(MISCREG_DPMU_SECURITY_0) \
_op_(MISCREG_NVDEC_HS_SECURITY_0) \
_op_(MISCREG_NVDEC_LS_SECURITY_0) \
_op_(MISCREG_RCE_SECURITY_0) \
_op_(MISCREG_LPI_CONFIG_0) \
_op_(MISCREG_LPI_STATUS_0) \
_op_(MISCREG_LPI_HYSTERESIS_0) \
_op_(MISCREG_GP0_GPU_SEC_0) \
_op_(MISCREG_FUSEROMENCRYPTIONTESTKEY0_0) \
_op_(MISCREG_FUSEROMENCRYPTIONTESTKEY1_0) \
_op_(MISCREG_FUSEROMENCRYPTIONTESTKEY2_0) \
_op_(MISCREG_FUSEROMENCRYPTIONTESTKEY3_0) \
_op_(MISCREG_FUSEROMENCRYPTIONNVKEY0_0) \
_op_(MISCREG_FUSEROMENCRYPTIONNVKEY1_0) \
_op_(MISCREG_FUSEROMENCRYPTIONNVKEY2_0) \
_op_(MISCREG_FUSEROMENCRYPTIONNVKEY3_0) \
_op_(MISCREG_FUSEROMENCRYPTIONOEM1KEY0_0) \
_op_(MISCREG_FUSEROMENCRYPTIONOEM1KEY1_0) \
_op_(MISCREG_FUSEROMENCRYPTIONOEM1KEY2_0) \
_op_(MISCREG_FUSEROMENCRYPTIONOEM1KEY3_0) \
_op_(MISCREG_FUSEROMENCRYPTIONOEM2KEY0_0) \
_op_(MISCREG_FUSEROMENCRYPTIONOEM2KEY1_0) \
_op_(MISCREG_FUSEROMENCRYPTIONOEM2KEY2_0) \
_op_(MISCREG_FUSEROMENCRYPTIONOEM2KEY3_0) \
_op_(MISCREG_FUSEROMENCRYPTIONOEM3KEY0_0) \
_op_(MISCREG_FUSEROMENCRYPTIONOEM3KEY1_0) \
_op_(MISCREG_FUSEROMENCRYPTIONOEM3KEY2_0) \
_op_(MISCREG_FUSEROMENCRYPTIONOEM3KEY3_0) \
_op_(MISCREG_FUSEROMENCRYPTIONOEM4KEY0_0) \
_op_(MISCREG_FUSEROMENCRYPTIONOEM4KEY1_0) \
_op_(MISCREG_FUSEROMENCRYPTIONOEM4KEY2_0) \
_op_(MISCREG_FUSEROMENCRYPTIONOEM4KEY3_0) \
_op_(MISCREG_FUSEROMENCRYPTIONOEM5KEY0_0) \
_op_(MISCREG_FUSEROMENCRYPTIONOEM5KEY1_0) \
_op_(MISCREG_FUSEROMENCRYPTIONOEM5KEY2_0) \
_op_(MISCREG_FUSEROMENCRYPTIONOEM5KEY3_0) \
_op_(MISCREG_FUSEROMENCRYPTIONOEM6KEY0_0) \
_op_(MISCREG_FUSEROMENCRYPTIONOEM6KEY1_0) \
_op_(MISCREG_FUSEROMENCRYPTIONOEM6KEY2_0) \
_op_(MISCREG_FUSEROMENCRYPTIONOEM6KEY3_0) \
_op_(MISCREG_AON_ERR_CONFIG_0) \
_op_(MISCREG_APE_ERR_CONFIG_0) \
_op_(MISCREG_BPMP_ERR_CONFIG_0) \
_op_(MISCREG_CCROC_ERR_CONFIG_0) \
_op_(MISCREG_CSITE_ERR_CONFIG_0) \
_op_(MISCREG_GPCDMA_MMIO_ERR_CONFIG_0) \
_op_(MISCREG_JTAG_ERR_CONFIG_0) \
_op_(MISCREG_NVDEC_ERR_CONFIG_0) \
_op_(MISCREG_NVDEC1_ERR_CONFIG_0) \
_op_(MISCREG_RCE_ERR_CONFIG_0) \
_op_(MISCREG_SCE_ERR_CONFIG_0) \
_op_(MISCREG_TSECA_ERR_CONFIG_0) \
_op_(MISCREG_TSECB_ERR_CONFIG_0) \
_op_(MISCREG_IORAIL_FENCE_CONFIG_0) \
_op_(MISCREG_CVRAIL_FENCE_CONFIG_0) \
_op_(MISCREG_GPURAIL_FENCE_CONFIG_0) \
_op_(MISCREG_AXIS_CENTRAL_CLK_OVR_ON_0) \
_op_(MISCREG_AXIS_SATELLITE_AON_CLK_OVR_ON_0) \
_op_(MISCREG_AXIS_SATELLITE_AXI2APB_CLK_OVR_ON_0) \
_op_(MISCREG_AXIS_SATELLITE_PCIE_CLK_OVR_ON_0) \
_op_(MISCREG_AXIS_SATELLITE_GROUT_CLK_OVR_ON_0) \
_op_(MISCREG_AON_P2PS_MST_TIMEOUT_PRESCALER_CFG_0) \
_op_(MISCREG_APE_P2PS_MST_TIMEOUT_PRESCALER_CFG_0) \
_op_(MISCREG_BPMP_P2PS_MST_TIMEOUT_PRESCALER_CFG_0) \
_op_(MISCREG_CCROC_P2PS_MST_TIMEOUT_PRESCALER_CFG_0) \
_op_(MISCREG_CSITE_P2PS_MST_TIMEOUT_PRESCALER_CFG_0) \
_op_(MISCREG_GPCDMA_MMIO_P2PS_MST_TIMEOUT_PRESCALER_CFG_0) \
_op_(MISCREG_JTAG_P2PS_MST_TIMEOUT_PRESCALER_CFG_0) \
_op_(MISCREG_NVDEC_P2PS_MST_TIMEOUT_PRESCALER_CFG_0) \
_op_(MISCREG_NVDEC1_P2PS_MST_TIMEOUT_PRESCALER_CFG_0) \
_op_(MISCREG_RCE_P2PS_MST_TIMEOUT_PRESCALER_CFG_0) \
_op_(MISCREG_SCE_P2PS_MST_TIMEOUT_PRESCALER_CFG_0) \
_op_(MISCREG_TSECA_P2PS_MST_TIMEOUT_PRESCALER_CFG_0) \
_op_(MISCREG_TSECB_P2PS_MST_TIMEOUT_PRESCALER_CFG_0) \
_op_(MISCREG_AXIS_SATELLITE_AXI2APB_P2PM_SLV_TIMEOUT_PRESCALER_CFG_0) \
_op_(MISCREG_AXIS_SATELLITE_GROUT_SLV_TIMEOUT_PRESCALER_CFG_0) \
_op_(MISCREG_GPU_P2PM_SLV_TIMEOUT_PRESCALER_CFG_0) \
_op_(MISCREG_HOST1X_P2PM_SLV_TIMEOUT_PRESCALER_CFG_0) \
_op_(MISCREG_SAPB_3_P2PM_SLV_TIMEOUT_PRESCALER_CFG_0) \
_op_(MISCREG_SMMU0_P2PM_SLV_TIMEOUT_PRESCALER_CFG_0) \
_op_(MISCREG_SMMU1_P2PM_SLV_TIMEOUT_PRESCALER_CFG_0) \
_op_(MISCREG_SMMU2_P2PM_SLV_TIMEOUT_PRESCALER_CFG_0) \
_op_(MISCREG_STM_P2PM_SLV_TIMEOUT_PRESCALER_CFG_0) \
_op_(MISCREG_SVC_SLV_TIMEOUT_PRESCALER_CFG_0) \
_op_(MISCREG_CBB_FIREWALL_SLV_TIMEOUT_PRESCALER_CFG_0) \
_op_(MISCREG_TOP_HSP_LOCKSTEP_CLK_ENABLE_0) \
_op_(MISCREG_AXIS_CENTRAL_PENDING_TRANS_0) \
_op_(MISCREG_CPU_RESET_VECTOR_0) \
_op_(MISCREG_AA64_RESET_LOW_0) \
_op_(MISCREG_AA64_RESET_HIGH_0) \
_op_(MISCREG_PFCFG_0) \
_op_(MISCREG_STICKY_REG0_0) \
_op_(MISCREG_STICKY_REG1_0) \
_op_(MISCREG_STICKY_REG2_0) \
_op_(MISCREG_STICKY_REG3_0) \
_op_(MISCREG_SPARE_REG0_0) \
_op_(MISCREG_SPARE_REG1_0) \
_op_(MISCREG_SPARE_REG2_0) \
_op_(MISCREG_SPARE_REG3_0) \
_op_(MISCREG_PROTO_CVRPTS_DATA0_0) \
_op_(MISCREG_PROTO_CVRPTS_DATA1_0) \
_op_(MISCREG_PROTO_CVRPTS_DATA2_0) \
_op_(MISCREG_PROTO_CVRPTS_DATA3_0) \
_op_(MISCREG_PROTO_CVRPTS_DATA4_0) \
_op_(MISCREG_PROTO_CVRPTS_DATA5_0) \
_op_(MISCREG_PROTO_CVRPTS_DATA6_0) \
_op_(MISCREG_PROTO_CVRPTS_DATA7_0) \
_op_(MISCREG_PROTO_CVRPTS_RESET_0) \
_op_(MISCREG_PROTO_CVRPTS_STATUS_0) \
_op_(MISCREG_PROTO_PROT0_SCRATCH0_0) \
_op_(MISCREG_PROTO_PROT0_SCRATCH1_0) \
_op_(MISCREG_PROTO_PROT0_SCRATCH2_0) \
_op_(MISCREG_PROTO_PROT0_SCRATCH3_0) \
_op_(MISCREG_PROTO_PROT0_SCRATCH4_0) \
_op_(MISCREG_PROTO_PROT0_SCRATCH5_0) \
_op_(MISCREG_PROTO_PROT0_SCRATCH6_0) \
_op_(MISCREG_PROTO_PROT0_SCRATCH7_0) \
_op_(MISCREG_EMU_REVID_0) \
_op_(MISCREG_TRANSACTOR_SCRATCH_0) \
_op_(MISCREG_COP0_TRANSACTOR_SCRATCH_0) \
_op_(MISCREG_COP1_TRANSACTOR_SCRATCH_0) \
_op_(MISCREG_COP2_TRANSACTOR_SCRATCH_0) \
_op_(MISCREG_COP3_TRANSACTOR_SCRATCH_0) \
_op_(MISCREG_CPU0_TRANSACTOR_SCRATCH_0) \
_op_(MISCREG_CPU1_TRANSACTOR_SCRATCH_0) \
_op_(MISCREG_CPU2_TRANSACTOR_SCRATCH_0) \
_op_(MISCREG_CPU3_TRANSACTOR_SCRATCH_0) \
_op_(MISCREG_CPU4_TRANSACTOR_SCRATCH_0) \
_op_(MISCREG_CPU5_TRANSACTOR_SCRATCH_0) \
_op_(MISCREG_MISC_SPARE_REG_0) \
_op_(MISCREG_STRAP_STRAPPING_OPT_A_0)


//
// ADDRESS SPACES
//

#define BASE_ADDRESS_MISCREG    0x00000000
#define BASE_ADDRESS_MISCREG_STRAP      0x0000f000

//
// ARMISCREG REGISTER BANKS
//

#define MISCREG0_FIRST_REG 0x0000 // MISCREG_MODS_REDIRCT_0
#define MISCREG0_LAST_REG 0x0004 // MISCREG_HIDREV_0
#define MISCREG1_FIRST_REG 0x0ffc // MISCREG_NVDEC1_HS_SECURITY_0
#define MISCREG1_LAST_REG 0x1040 // MISCREG_RCE_SECURITY_0
#define MISCREG2_FIRST_REG 0x1050 // MISCREG_LPI_CONFIG_0
#define MISCREG2_LAST_REG 0x105c // MISCREG_GP0_GPU_SEC_0
#define MISCREG3_FIRST_REG 0x1080 // MISCREG_FUSEROMENCRYPTIONTESTKEY0_0
#define MISCREG3_LAST_REG 0x10fc // MISCREG_FUSEROMENCRYPTIONOEM6KEY3_0
#define MISCREG4_FIRST_REG 0x1200 // MISCREG_AON_ERR_CONFIG_0
#define MISCREG4_LAST_REG 0x123c // MISCREG_GPURAIL_FENCE_CONFIG_0
#define MISCREG5_FIRST_REG 0x1244 // MISCREG_AXIS_CENTRAL_CLK_OVR_ON_0
#define MISCREG5_LAST_REG 0x1288 // MISCREG_TSECB_P2PS_MST_TIMEOUT_PRESCALER_CFG_0
#define MISCREG6_FIRST_REG 0x130c // MISCREG_AXIS_SATELLITE_AXI2APB_P2PM_SLV_TIMEOUT_PRESCALER_CFG_0
#define MISCREG6_LAST_REG 0x1334 // MISCREG_CBB_FIREWALL_SLV_TIMEOUT_PRESCALER_CFG_0
#define MISCREG7_FIRST_REG 0x13b8 // MISCREG_TOP_HSP_LOCKSTEP_CLK_ENABLE_0
#define MISCREG7_LAST_REG 0x13bc // MISCREG_AXIS_CENTRAL_PENDING_TRANS_0
#define MISCREG8_FIRST_REG 0x2000 // MISCREG_CPU_RESET_VECTOR_0
#define MISCREG8_LAST_REG 0x200c // MISCREG_PFCFG_0
#define MISCREG9_FIRST_REG 0x3000 // MISCREG_STICKY_REG0_0
#define MISCREG9_LAST_REG 0x301c // MISCREG_SPARE_REG3_0
#define MISCREG10_FIRST_REG 0x3100 // MISCREG_PROTO_CVRPTS_DATA0_0
#define MISCREG10_LAST_REG 0x3144 // MISCREG_PROTO_PROT0_SCRATCH7_0
#define MISCREG11_FIRST_REG 0x3160 // MISCREG_EMU_REVID_0
#define MISCREG11_LAST_REG 0x3164 // MISCREG_TRANSACTOR_SCRATCH_0
#define MISCREG12_FIRST_REG 0x3180 // MISCREG_COP0_TRANSACTOR_SCRATCH_0
#define MISCREG12_LAST_REG 0x31a4 // MISCREG_CPU5_TRANSACTOR_SCRATCH_0
#define MISCREG13_FIRST_REG 0x31ac // MISCREG_MISC_SPARE_REG_0
#define MISCREG13_LAST_REG 0x31ac // MISCREG_MISC_SPARE_REG_0
#define MISCREG_STRAP0_FIRST_REG 0xf000 // MISCREG_STRAP_STRAPPING_OPT_A_0
#define MISCREG_STRAP0_LAST_REG 0xf000 // MISCREG_STRAP_STRAPPING_OPT_A_0

// To satisfy various compilers and platforms,
// we let users control the types and syntax of certain constants, using macros.
#ifndef _MK_SHIFT_CONST
  #define _MK_SHIFT_CONST(_constant_) _constant_
#endif
#ifndef _MK_MASK_CONST
  #define _MK_MASK_CONST(_constant_) _constant_
#endif
#ifndef _MK_ENUM_CONST
  #define _MK_ENUM_CONST(_constant_) (_constant_ ## UL)
#endif
#ifndef _MK_ADDR_CONST
  #define _MK_ADDR_CONST(_constant_) _constant_
#endif
#ifndef _MK_FIELD_CONST
  #define _MK_FIELD_CONST(_mask_, _shift_) (_MK_MASK_CONST(_mask_) << _MK_SHIFT_CONST(_shift_))
#endif

#endif // ifndef ___ARMISCREG_H_INC_
