//
// Copyright (c) 2018 NVIDIA Corporation.
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are met:
//
// Redistributions of source code must retain the above copyright notice,
// this list of conditions and the following disclaimer.
//
// Redistributions in binary form must reproduce the above copyright notice,
// this list of conditions and the following disclaimer in the documentation
// and/or other materials provided with the distribution.
//
// Neither the name of the NVIDIA Corporation nor the names of its contributors
// may be used to endorse or promote products derived from this software
// without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
// POSSIBILITY OF SUCH DAMAGE.
//

//
// DO NOT EDIT - generated by simspec!
//

#ifndef ___ARHSP_DBELL_H_INC_
#define ___ARHSP_DBELL_H_INC_
#define NV_MOBILE_ARHSP_DBELL_H_UNIT_OF_OFFSET 1B


// Register HSP_DBELL_0_TRIGGER_0
#define HSP_DBELL_0_TRIGGER_0                   _MK_ADDR_CONST(0x0)
#define HSP_DBELL_0_TRIGGER_0_SECURE                    0x0
#define HSP_DBELL_0_TRIGGER_0_DUAL                      0x0
#define HSP_DBELL_0_TRIGGER_0_SCR                       0
#define HSP_DBELL_0_TRIGGER_0_WORD_COUNT                        0x1
#define HSP_DBELL_0_TRIGGER_0_RESET_VAL                         _MK_MASK_CONST(0x0)
#define HSP_DBELL_0_TRIGGER_0_RESET_MASK                        _MK_MASK_CONST(0xffffffff)
#define HSP_DBELL_0_TRIGGER_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define HSP_DBELL_0_TRIGGER_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define HSP_DBELL_0_TRIGGER_0_READ_MASK                         _MK_MASK_CONST(0xffffffff)
#define HSP_DBELL_0_TRIGGER_0_WRITE_MASK                        _MK_MASK_CONST(0xffffffff)
#define HSP_DBELL_0_TRIGGER_0_DUMMY_SHIFT                       _MK_SHIFT_CONST(0)
#define HSP_DBELL_0_TRIGGER_0_DUMMY_FIELD                       _MK_FIELD_CONST(0xffffffff, HSP_DBELL_0_TRIGGER_0_DUMMY_SHIFT)
#define HSP_DBELL_0_TRIGGER_0_DUMMY_RANGE                       31:0
#define HSP_DBELL_0_TRIGGER_0_DUMMY_WOFFSET                     0x0
#define HSP_DBELL_0_TRIGGER_0_DUMMY_DEFAULT                     _MK_MASK_CONST(0x0)
#define HSP_DBELL_0_TRIGGER_0_DUMMY_DEFAULT_MASK                        _MK_MASK_CONST(0xffffffff)
#define HSP_DBELL_0_TRIGGER_0_DUMMY_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define HSP_DBELL_0_TRIGGER_0_DUMMY_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define HSP_DBELL_0_TRIGGER_0_DUMMY_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define HSP_DBELL_0_TRIGGER_0_DUMMY_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)


// Register HSP_DBELL_0_ENABLE_0
#define HSP_DBELL_0_ENABLE_0                    _MK_ADDR_CONST(0x4)
#define HSP_DBELL_0_ENABLE_0_SECURE                     0x0
#define HSP_DBELL_0_ENABLE_0_DUAL                       0x0
#define HSP_DBELL_0_ENABLE_0_SCR                        DB_0_REG_0
#define HSP_DBELL_0_ENABLE_0_WORD_COUNT                         0x1
#define HSP_DBELL_0_ENABLE_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define HSP_DBELL_0_ENABLE_0_RESET_MASK                         _MK_MASK_CONST(0xffffffff)
#define HSP_DBELL_0_ENABLE_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define HSP_DBELL_0_ENABLE_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define HSP_DBELL_0_ENABLE_0_READ_MASK                  _MK_MASK_CONST(0xffffffff)
#define HSP_DBELL_0_ENABLE_0_WRITE_MASK                         _MK_MASK_CONST(0xffffffff)
#define HSP_DBELL_0_ENABLE_0_MAP1_SHIFT                 _MK_SHIFT_CONST(16)
#define HSP_DBELL_0_ENABLE_0_MAP1_FIELD                 _MK_FIELD_CONST(0xffff, HSP_DBELL_0_ENABLE_0_MAP1_SHIFT)
#define HSP_DBELL_0_ENABLE_0_MAP1_RANGE                 31:16
#define HSP_DBELL_0_ENABLE_0_MAP1_WOFFSET                       0x0
#define HSP_DBELL_0_ENABLE_0_MAP1_DEFAULT                       _MK_MASK_CONST(0x0)
#define HSP_DBELL_0_ENABLE_0_MAP1_DEFAULT_MASK                  _MK_MASK_CONST(0xffff)
#define HSP_DBELL_0_ENABLE_0_MAP1_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define HSP_DBELL_0_ENABLE_0_MAP1_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define HSP_DBELL_0_ENABLE_0_MAP1_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define HSP_DBELL_0_ENABLE_0_MAP1_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)

#define HSP_DBELL_0_ENABLE_0_MAP0_SHIFT                 _MK_SHIFT_CONST(0)
#define HSP_DBELL_0_ENABLE_0_MAP0_FIELD                 _MK_FIELD_CONST(0xffff, HSP_DBELL_0_ENABLE_0_MAP0_SHIFT)
#define HSP_DBELL_0_ENABLE_0_MAP0_RANGE                 15:0
#define HSP_DBELL_0_ENABLE_0_MAP0_WOFFSET                       0x0
#define HSP_DBELL_0_ENABLE_0_MAP0_DEFAULT                       _MK_MASK_CONST(0x0)
#define HSP_DBELL_0_ENABLE_0_MAP0_DEFAULT_MASK                  _MK_MASK_CONST(0xffff)
#define HSP_DBELL_0_ENABLE_0_MAP0_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define HSP_DBELL_0_ENABLE_0_MAP0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define HSP_DBELL_0_ENABLE_0_MAP0_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define HSP_DBELL_0_ENABLE_0_MAP0_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)


// Register HSP_DBELL_0_RAW_0
#define HSP_DBELL_0_RAW_0                       _MK_ADDR_CONST(0x8)
#define HSP_DBELL_0_RAW_0_SECURE                        0x0
#define HSP_DBELL_0_RAW_0_DUAL                  0x0
#define HSP_DBELL_0_RAW_0_SCR                   DB_0_REG_0
#define HSP_DBELL_0_RAW_0_WORD_COUNT                    0x1
#define HSP_DBELL_0_RAW_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define HSP_DBELL_0_RAW_0_RESET_MASK                    _MK_MASK_CONST(0xffffffff)
#define HSP_DBELL_0_RAW_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define HSP_DBELL_0_RAW_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define HSP_DBELL_0_RAW_0_READ_MASK                     _MK_MASK_CONST(0xffffffff)
#define HSP_DBELL_0_RAW_0_WRITE_MASK                    _MK_MASK_CONST(0xffffffff)
#define HSP_DBELL_0_RAW_0_MAP1_SHIFT                    _MK_SHIFT_CONST(16)
#define HSP_DBELL_0_RAW_0_MAP1_FIELD                    _MK_FIELD_CONST(0xffff, HSP_DBELL_0_RAW_0_MAP1_SHIFT)
#define HSP_DBELL_0_RAW_0_MAP1_RANGE                    31:16
#define HSP_DBELL_0_RAW_0_MAP1_WOFFSET                  0x0
#define HSP_DBELL_0_RAW_0_MAP1_DEFAULT                  _MK_MASK_CONST(0x0)
#define HSP_DBELL_0_RAW_0_MAP1_DEFAULT_MASK                     _MK_MASK_CONST(0xffff)
#define HSP_DBELL_0_RAW_0_MAP1_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define HSP_DBELL_0_RAW_0_MAP1_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define HSP_DBELL_0_RAW_0_MAP1_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define HSP_DBELL_0_RAW_0_MAP1_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)

#define HSP_DBELL_0_RAW_0_MAP0_SHIFT                    _MK_SHIFT_CONST(0)
#define HSP_DBELL_0_RAW_0_MAP0_FIELD                    _MK_FIELD_CONST(0xffff, HSP_DBELL_0_RAW_0_MAP0_SHIFT)
#define HSP_DBELL_0_RAW_0_MAP0_RANGE                    15:0
#define HSP_DBELL_0_RAW_0_MAP0_WOFFSET                  0x0
#define HSP_DBELL_0_RAW_0_MAP0_DEFAULT                  _MK_MASK_CONST(0x0)
#define HSP_DBELL_0_RAW_0_MAP0_DEFAULT_MASK                     _MK_MASK_CONST(0xffff)
#define HSP_DBELL_0_RAW_0_MAP0_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define HSP_DBELL_0_RAW_0_MAP0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define HSP_DBELL_0_RAW_0_MAP0_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define HSP_DBELL_0_RAW_0_MAP0_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)


// Register HSP_DBELL_0_PENDING_0
#define HSP_DBELL_0_PENDING_0                   _MK_ADDR_CONST(0xc)
#define HSP_DBELL_0_PENDING_0_SECURE                    0x0
#define HSP_DBELL_0_PENDING_0_DUAL                      0x0
#define HSP_DBELL_0_PENDING_0_SCR                       DB_0_REG_0
#define HSP_DBELL_0_PENDING_0_WORD_COUNT                        0x1
#define HSP_DBELL_0_PENDING_0_RESET_VAL                         _MK_MASK_CONST(0x0)
#define HSP_DBELL_0_PENDING_0_RESET_MASK                        _MK_MASK_CONST(0xffffffff)
#define HSP_DBELL_0_PENDING_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define HSP_DBELL_0_PENDING_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define HSP_DBELL_0_PENDING_0_READ_MASK                         _MK_MASK_CONST(0xffffffff)
#define HSP_DBELL_0_PENDING_0_WRITE_MASK                        _MK_MASK_CONST(0xffffffff)
#define HSP_DBELL_0_PENDING_0_MAP1_SHIFT                        _MK_SHIFT_CONST(16)
#define HSP_DBELL_0_PENDING_0_MAP1_FIELD                        _MK_FIELD_CONST(0xffff, HSP_DBELL_0_PENDING_0_MAP1_SHIFT)
#define HSP_DBELL_0_PENDING_0_MAP1_RANGE                        31:16
#define HSP_DBELL_0_PENDING_0_MAP1_WOFFSET                      0x0
#define HSP_DBELL_0_PENDING_0_MAP1_DEFAULT                      _MK_MASK_CONST(0x0)
#define HSP_DBELL_0_PENDING_0_MAP1_DEFAULT_MASK                 _MK_MASK_CONST(0xffff)
#define HSP_DBELL_0_PENDING_0_MAP1_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define HSP_DBELL_0_PENDING_0_MAP1_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define HSP_DBELL_0_PENDING_0_MAP1_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define HSP_DBELL_0_PENDING_0_MAP1_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define HSP_DBELL_0_PENDING_0_MAP0_SHIFT                        _MK_SHIFT_CONST(0)
#define HSP_DBELL_0_PENDING_0_MAP0_FIELD                        _MK_FIELD_CONST(0xffff, HSP_DBELL_0_PENDING_0_MAP0_SHIFT)
#define HSP_DBELL_0_PENDING_0_MAP0_RANGE                        15:0
#define HSP_DBELL_0_PENDING_0_MAP0_WOFFSET                      0x0
#define HSP_DBELL_0_PENDING_0_MAP0_DEFAULT                      _MK_MASK_CONST(0x0)
#define HSP_DBELL_0_PENDING_0_MAP0_DEFAULT_MASK                 _MK_MASK_CONST(0xffff)
#define HSP_DBELL_0_PENDING_0_MAP0_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define HSP_DBELL_0_PENDING_0_MAP0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define HSP_DBELL_0_PENDING_0_MAP0_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define HSP_DBELL_0_PENDING_0_MAP0_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)


// Register HSP_DBELL_1_TRIGGER_0
#define HSP_DBELL_1_TRIGGER_0                   _MK_ADDR_CONST(0x100)
#define HSP_DBELL_1_TRIGGER_0_SECURE                    0x0
#define HSP_DBELL_1_TRIGGER_0_DUAL                      0x0
#define HSP_DBELL_1_TRIGGER_0_SCR                       0
#define HSP_DBELL_1_TRIGGER_0_WORD_COUNT                        0x1
#define HSP_DBELL_1_TRIGGER_0_RESET_VAL                         _MK_MASK_CONST(0x0)
#define HSP_DBELL_1_TRIGGER_0_RESET_MASK                        _MK_MASK_CONST(0xffffffff)
#define HSP_DBELL_1_TRIGGER_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define HSP_DBELL_1_TRIGGER_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define HSP_DBELL_1_TRIGGER_0_READ_MASK                         _MK_MASK_CONST(0xffffffff)
#define HSP_DBELL_1_TRIGGER_0_WRITE_MASK                        _MK_MASK_CONST(0xffffffff)
#define HSP_DBELL_1_TRIGGER_0_DUMMY_SHIFT                       _MK_SHIFT_CONST(0)
#define HSP_DBELL_1_TRIGGER_0_DUMMY_FIELD                       _MK_FIELD_CONST(0xffffffff, HSP_DBELL_1_TRIGGER_0_DUMMY_SHIFT)
#define HSP_DBELL_1_TRIGGER_0_DUMMY_RANGE                       31:0
#define HSP_DBELL_1_TRIGGER_0_DUMMY_WOFFSET                     0x0
#define HSP_DBELL_1_TRIGGER_0_DUMMY_DEFAULT                     _MK_MASK_CONST(0x0)
#define HSP_DBELL_1_TRIGGER_0_DUMMY_DEFAULT_MASK                        _MK_MASK_CONST(0xffffffff)
#define HSP_DBELL_1_TRIGGER_0_DUMMY_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define HSP_DBELL_1_TRIGGER_0_DUMMY_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define HSP_DBELL_1_TRIGGER_0_DUMMY_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define HSP_DBELL_1_TRIGGER_0_DUMMY_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)


// Register HSP_DBELL_1_ENABLE_0
#define HSP_DBELL_1_ENABLE_0                    _MK_ADDR_CONST(0x104)
#define HSP_DBELL_1_ENABLE_0_SECURE                     0x0
#define HSP_DBELL_1_ENABLE_0_DUAL                       0x0
#define HSP_DBELL_1_ENABLE_0_SCR                        DB_1_REG_0
#define HSP_DBELL_1_ENABLE_0_WORD_COUNT                         0x1
#define HSP_DBELL_1_ENABLE_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define HSP_DBELL_1_ENABLE_0_RESET_MASK                         _MK_MASK_CONST(0xffffffff)
#define HSP_DBELL_1_ENABLE_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define HSP_DBELL_1_ENABLE_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define HSP_DBELL_1_ENABLE_0_READ_MASK                  _MK_MASK_CONST(0xffffffff)
#define HSP_DBELL_1_ENABLE_0_WRITE_MASK                         _MK_MASK_CONST(0xffffffff)
#define HSP_DBELL_1_ENABLE_0_MAP1_SHIFT                 _MK_SHIFT_CONST(16)
#define HSP_DBELL_1_ENABLE_0_MAP1_FIELD                 _MK_FIELD_CONST(0xffff, HSP_DBELL_1_ENABLE_0_MAP1_SHIFT)
#define HSP_DBELL_1_ENABLE_0_MAP1_RANGE                 31:16
#define HSP_DBELL_1_ENABLE_0_MAP1_WOFFSET                       0x0
#define HSP_DBELL_1_ENABLE_0_MAP1_DEFAULT                       _MK_MASK_CONST(0x0)
#define HSP_DBELL_1_ENABLE_0_MAP1_DEFAULT_MASK                  _MK_MASK_CONST(0xffff)
#define HSP_DBELL_1_ENABLE_0_MAP1_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define HSP_DBELL_1_ENABLE_0_MAP1_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define HSP_DBELL_1_ENABLE_0_MAP1_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define HSP_DBELL_1_ENABLE_0_MAP1_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)

#define HSP_DBELL_1_ENABLE_0_MAP0_SHIFT                 _MK_SHIFT_CONST(0)
#define HSP_DBELL_1_ENABLE_0_MAP0_FIELD                 _MK_FIELD_CONST(0xffff, HSP_DBELL_1_ENABLE_0_MAP0_SHIFT)
#define HSP_DBELL_1_ENABLE_0_MAP0_RANGE                 15:0
#define HSP_DBELL_1_ENABLE_0_MAP0_WOFFSET                       0x0
#define HSP_DBELL_1_ENABLE_0_MAP0_DEFAULT                       _MK_MASK_CONST(0x0)
#define HSP_DBELL_1_ENABLE_0_MAP0_DEFAULT_MASK                  _MK_MASK_CONST(0xffff)
#define HSP_DBELL_1_ENABLE_0_MAP0_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define HSP_DBELL_1_ENABLE_0_MAP0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define HSP_DBELL_1_ENABLE_0_MAP0_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define HSP_DBELL_1_ENABLE_0_MAP0_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)


// Register HSP_DBELL_1_RAW_0
#define HSP_DBELL_1_RAW_0                       _MK_ADDR_CONST(0x108)
#define HSP_DBELL_1_RAW_0_SECURE                        0x0
#define HSP_DBELL_1_RAW_0_DUAL                  0x0
#define HSP_DBELL_1_RAW_0_SCR                   DB_1_REG_0
#define HSP_DBELL_1_RAW_0_WORD_COUNT                    0x1
#define HSP_DBELL_1_RAW_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define HSP_DBELL_1_RAW_0_RESET_MASK                    _MK_MASK_CONST(0xffffffff)
#define HSP_DBELL_1_RAW_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define HSP_DBELL_1_RAW_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define HSP_DBELL_1_RAW_0_READ_MASK                     _MK_MASK_CONST(0xffffffff)
#define HSP_DBELL_1_RAW_0_WRITE_MASK                    _MK_MASK_CONST(0xffffffff)
#define HSP_DBELL_1_RAW_0_MAP1_SHIFT                    _MK_SHIFT_CONST(16)
#define HSP_DBELL_1_RAW_0_MAP1_FIELD                    _MK_FIELD_CONST(0xffff, HSP_DBELL_1_RAW_0_MAP1_SHIFT)
#define HSP_DBELL_1_RAW_0_MAP1_RANGE                    31:16
#define HSP_DBELL_1_RAW_0_MAP1_WOFFSET                  0x0
#define HSP_DBELL_1_RAW_0_MAP1_DEFAULT                  _MK_MASK_CONST(0x0)
#define HSP_DBELL_1_RAW_0_MAP1_DEFAULT_MASK                     _MK_MASK_CONST(0xffff)
#define HSP_DBELL_1_RAW_0_MAP1_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define HSP_DBELL_1_RAW_0_MAP1_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define HSP_DBELL_1_RAW_0_MAP1_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define HSP_DBELL_1_RAW_0_MAP1_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)

#define HSP_DBELL_1_RAW_0_MAP0_SHIFT                    _MK_SHIFT_CONST(0)
#define HSP_DBELL_1_RAW_0_MAP0_FIELD                    _MK_FIELD_CONST(0xffff, HSP_DBELL_1_RAW_0_MAP0_SHIFT)
#define HSP_DBELL_1_RAW_0_MAP0_RANGE                    15:0
#define HSP_DBELL_1_RAW_0_MAP0_WOFFSET                  0x0
#define HSP_DBELL_1_RAW_0_MAP0_DEFAULT                  _MK_MASK_CONST(0x0)
#define HSP_DBELL_1_RAW_0_MAP0_DEFAULT_MASK                     _MK_MASK_CONST(0xffff)
#define HSP_DBELL_1_RAW_0_MAP0_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define HSP_DBELL_1_RAW_0_MAP0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define HSP_DBELL_1_RAW_0_MAP0_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define HSP_DBELL_1_RAW_0_MAP0_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)


// Register HSP_DBELL_1_PENDING_0
#define HSP_DBELL_1_PENDING_0                   _MK_ADDR_CONST(0x10c)
#define HSP_DBELL_1_PENDING_0_SECURE                    0x0
#define HSP_DBELL_1_PENDING_0_DUAL                      0x0
#define HSP_DBELL_1_PENDING_0_SCR                       DB_1_REG_0
#define HSP_DBELL_1_PENDING_0_WORD_COUNT                        0x1
#define HSP_DBELL_1_PENDING_0_RESET_VAL                         _MK_MASK_CONST(0x0)
#define HSP_DBELL_1_PENDING_0_RESET_MASK                        _MK_MASK_CONST(0xffffffff)
#define HSP_DBELL_1_PENDING_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define HSP_DBELL_1_PENDING_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define HSP_DBELL_1_PENDING_0_READ_MASK                         _MK_MASK_CONST(0xffffffff)
#define HSP_DBELL_1_PENDING_0_WRITE_MASK                        _MK_MASK_CONST(0xffffffff)
#define HSP_DBELL_1_PENDING_0_MAP1_SHIFT                        _MK_SHIFT_CONST(16)
#define HSP_DBELL_1_PENDING_0_MAP1_FIELD                        _MK_FIELD_CONST(0xffff, HSP_DBELL_1_PENDING_0_MAP1_SHIFT)
#define HSP_DBELL_1_PENDING_0_MAP1_RANGE                        31:16
#define HSP_DBELL_1_PENDING_0_MAP1_WOFFSET                      0x0
#define HSP_DBELL_1_PENDING_0_MAP1_DEFAULT                      _MK_MASK_CONST(0x0)
#define HSP_DBELL_1_PENDING_0_MAP1_DEFAULT_MASK                 _MK_MASK_CONST(0xffff)
#define HSP_DBELL_1_PENDING_0_MAP1_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define HSP_DBELL_1_PENDING_0_MAP1_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define HSP_DBELL_1_PENDING_0_MAP1_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define HSP_DBELL_1_PENDING_0_MAP1_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define HSP_DBELL_1_PENDING_0_MAP0_SHIFT                        _MK_SHIFT_CONST(0)
#define HSP_DBELL_1_PENDING_0_MAP0_FIELD                        _MK_FIELD_CONST(0xffff, HSP_DBELL_1_PENDING_0_MAP0_SHIFT)
#define HSP_DBELL_1_PENDING_0_MAP0_RANGE                        15:0
#define HSP_DBELL_1_PENDING_0_MAP0_WOFFSET                      0x0
#define HSP_DBELL_1_PENDING_0_MAP0_DEFAULT                      _MK_MASK_CONST(0x0)
#define HSP_DBELL_1_PENDING_0_MAP0_DEFAULT_MASK                 _MK_MASK_CONST(0xffff)
#define HSP_DBELL_1_PENDING_0_MAP0_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define HSP_DBELL_1_PENDING_0_MAP0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define HSP_DBELL_1_PENDING_0_MAP0_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define HSP_DBELL_1_PENDING_0_MAP0_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)


// Register HSP_DBELL_2_TRIGGER_0
#define HSP_DBELL_2_TRIGGER_0                   _MK_ADDR_CONST(0x200)
#define HSP_DBELL_2_TRIGGER_0_SECURE                    0x0
#define HSP_DBELL_2_TRIGGER_0_DUAL                      0x0
#define HSP_DBELL_2_TRIGGER_0_SCR                       0
#define HSP_DBELL_2_TRIGGER_0_WORD_COUNT                        0x1
#define HSP_DBELL_2_TRIGGER_0_RESET_VAL                         _MK_MASK_CONST(0x0)
#define HSP_DBELL_2_TRIGGER_0_RESET_MASK                        _MK_MASK_CONST(0xffffffff)
#define HSP_DBELL_2_TRIGGER_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define HSP_DBELL_2_TRIGGER_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define HSP_DBELL_2_TRIGGER_0_READ_MASK                         _MK_MASK_CONST(0xffffffff)
#define HSP_DBELL_2_TRIGGER_0_WRITE_MASK                        _MK_MASK_CONST(0xffffffff)
#define HSP_DBELL_2_TRIGGER_0_DUMMY_SHIFT                       _MK_SHIFT_CONST(0)
#define HSP_DBELL_2_TRIGGER_0_DUMMY_FIELD                       _MK_FIELD_CONST(0xffffffff, HSP_DBELL_2_TRIGGER_0_DUMMY_SHIFT)
#define HSP_DBELL_2_TRIGGER_0_DUMMY_RANGE                       31:0
#define HSP_DBELL_2_TRIGGER_0_DUMMY_WOFFSET                     0x0
#define HSP_DBELL_2_TRIGGER_0_DUMMY_DEFAULT                     _MK_MASK_CONST(0x0)
#define HSP_DBELL_2_TRIGGER_0_DUMMY_DEFAULT_MASK                        _MK_MASK_CONST(0xffffffff)
#define HSP_DBELL_2_TRIGGER_0_DUMMY_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define HSP_DBELL_2_TRIGGER_0_DUMMY_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define HSP_DBELL_2_TRIGGER_0_DUMMY_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define HSP_DBELL_2_TRIGGER_0_DUMMY_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)


// Register HSP_DBELL_2_ENABLE_0
#define HSP_DBELL_2_ENABLE_0                    _MK_ADDR_CONST(0x204)
#define HSP_DBELL_2_ENABLE_0_SECURE                     0x0
#define HSP_DBELL_2_ENABLE_0_DUAL                       0x0
#define HSP_DBELL_2_ENABLE_0_SCR                        DB_2_REG_0
#define HSP_DBELL_2_ENABLE_0_WORD_COUNT                         0x1
#define HSP_DBELL_2_ENABLE_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define HSP_DBELL_2_ENABLE_0_RESET_MASK                         _MK_MASK_CONST(0xffffffff)
#define HSP_DBELL_2_ENABLE_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define HSP_DBELL_2_ENABLE_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define HSP_DBELL_2_ENABLE_0_READ_MASK                  _MK_MASK_CONST(0xffffffff)
#define HSP_DBELL_2_ENABLE_0_WRITE_MASK                         _MK_MASK_CONST(0xffffffff)
#define HSP_DBELL_2_ENABLE_0_MAP1_SHIFT                 _MK_SHIFT_CONST(16)
#define HSP_DBELL_2_ENABLE_0_MAP1_FIELD                 _MK_FIELD_CONST(0xffff, HSP_DBELL_2_ENABLE_0_MAP1_SHIFT)
#define HSP_DBELL_2_ENABLE_0_MAP1_RANGE                 31:16
#define HSP_DBELL_2_ENABLE_0_MAP1_WOFFSET                       0x0
#define HSP_DBELL_2_ENABLE_0_MAP1_DEFAULT                       _MK_MASK_CONST(0x0)
#define HSP_DBELL_2_ENABLE_0_MAP1_DEFAULT_MASK                  _MK_MASK_CONST(0xffff)
#define HSP_DBELL_2_ENABLE_0_MAP1_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define HSP_DBELL_2_ENABLE_0_MAP1_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define HSP_DBELL_2_ENABLE_0_MAP1_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define HSP_DBELL_2_ENABLE_0_MAP1_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)

#define HSP_DBELL_2_ENABLE_0_MAP0_SHIFT                 _MK_SHIFT_CONST(0)
#define HSP_DBELL_2_ENABLE_0_MAP0_FIELD                 _MK_FIELD_CONST(0xffff, HSP_DBELL_2_ENABLE_0_MAP0_SHIFT)
#define HSP_DBELL_2_ENABLE_0_MAP0_RANGE                 15:0
#define HSP_DBELL_2_ENABLE_0_MAP0_WOFFSET                       0x0
#define HSP_DBELL_2_ENABLE_0_MAP0_DEFAULT                       _MK_MASK_CONST(0x0)
#define HSP_DBELL_2_ENABLE_0_MAP0_DEFAULT_MASK                  _MK_MASK_CONST(0xffff)
#define HSP_DBELL_2_ENABLE_0_MAP0_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define HSP_DBELL_2_ENABLE_0_MAP0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define HSP_DBELL_2_ENABLE_0_MAP0_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define HSP_DBELL_2_ENABLE_0_MAP0_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)


// Register HSP_DBELL_2_RAW_0
#define HSP_DBELL_2_RAW_0                       _MK_ADDR_CONST(0x208)
#define HSP_DBELL_2_RAW_0_SECURE                        0x0
#define HSP_DBELL_2_RAW_0_DUAL                  0x0
#define HSP_DBELL_2_RAW_0_SCR                   DB_2_REG_0
#define HSP_DBELL_2_RAW_0_WORD_COUNT                    0x1
#define HSP_DBELL_2_RAW_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define HSP_DBELL_2_RAW_0_RESET_MASK                    _MK_MASK_CONST(0xffffffff)
#define HSP_DBELL_2_RAW_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define HSP_DBELL_2_RAW_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define HSP_DBELL_2_RAW_0_READ_MASK                     _MK_MASK_CONST(0xffffffff)
#define HSP_DBELL_2_RAW_0_WRITE_MASK                    _MK_MASK_CONST(0xffffffff)
#define HSP_DBELL_2_RAW_0_MAP1_SHIFT                    _MK_SHIFT_CONST(16)
#define HSP_DBELL_2_RAW_0_MAP1_FIELD                    _MK_FIELD_CONST(0xffff, HSP_DBELL_2_RAW_0_MAP1_SHIFT)
#define HSP_DBELL_2_RAW_0_MAP1_RANGE                    31:16
#define HSP_DBELL_2_RAW_0_MAP1_WOFFSET                  0x0
#define HSP_DBELL_2_RAW_0_MAP1_DEFAULT                  _MK_MASK_CONST(0x0)
#define HSP_DBELL_2_RAW_0_MAP1_DEFAULT_MASK                     _MK_MASK_CONST(0xffff)
#define HSP_DBELL_2_RAW_0_MAP1_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define HSP_DBELL_2_RAW_0_MAP1_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define HSP_DBELL_2_RAW_0_MAP1_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define HSP_DBELL_2_RAW_0_MAP1_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)

#define HSP_DBELL_2_RAW_0_MAP0_SHIFT                    _MK_SHIFT_CONST(0)
#define HSP_DBELL_2_RAW_0_MAP0_FIELD                    _MK_FIELD_CONST(0xffff, HSP_DBELL_2_RAW_0_MAP0_SHIFT)
#define HSP_DBELL_2_RAW_0_MAP0_RANGE                    15:0
#define HSP_DBELL_2_RAW_0_MAP0_WOFFSET                  0x0
#define HSP_DBELL_2_RAW_0_MAP0_DEFAULT                  _MK_MASK_CONST(0x0)
#define HSP_DBELL_2_RAW_0_MAP0_DEFAULT_MASK                     _MK_MASK_CONST(0xffff)
#define HSP_DBELL_2_RAW_0_MAP0_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define HSP_DBELL_2_RAW_0_MAP0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define HSP_DBELL_2_RAW_0_MAP0_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define HSP_DBELL_2_RAW_0_MAP0_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)


// Register HSP_DBELL_2_PENDING_0
#define HSP_DBELL_2_PENDING_0                   _MK_ADDR_CONST(0x20c)
#define HSP_DBELL_2_PENDING_0_SECURE                    0x0
#define HSP_DBELL_2_PENDING_0_DUAL                      0x0
#define HSP_DBELL_2_PENDING_0_SCR                       DB_2_REG_0
#define HSP_DBELL_2_PENDING_0_WORD_COUNT                        0x1
#define HSP_DBELL_2_PENDING_0_RESET_VAL                         _MK_MASK_CONST(0x0)
#define HSP_DBELL_2_PENDING_0_RESET_MASK                        _MK_MASK_CONST(0xffffffff)
#define HSP_DBELL_2_PENDING_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define HSP_DBELL_2_PENDING_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define HSP_DBELL_2_PENDING_0_READ_MASK                         _MK_MASK_CONST(0xffffffff)
#define HSP_DBELL_2_PENDING_0_WRITE_MASK                        _MK_MASK_CONST(0xffffffff)
#define HSP_DBELL_2_PENDING_0_MAP1_SHIFT                        _MK_SHIFT_CONST(16)
#define HSP_DBELL_2_PENDING_0_MAP1_FIELD                        _MK_FIELD_CONST(0xffff, HSP_DBELL_2_PENDING_0_MAP1_SHIFT)
#define HSP_DBELL_2_PENDING_0_MAP1_RANGE                        31:16
#define HSP_DBELL_2_PENDING_0_MAP1_WOFFSET                      0x0
#define HSP_DBELL_2_PENDING_0_MAP1_DEFAULT                      _MK_MASK_CONST(0x0)
#define HSP_DBELL_2_PENDING_0_MAP1_DEFAULT_MASK                 _MK_MASK_CONST(0xffff)
#define HSP_DBELL_2_PENDING_0_MAP1_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define HSP_DBELL_2_PENDING_0_MAP1_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define HSP_DBELL_2_PENDING_0_MAP1_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define HSP_DBELL_2_PENDING_0_MAP1_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define HSP_DBELL_2_PENDING_0_MAP0_SHIFT                        _MK_SHIFT_CONST(0)
#define HSP_DBELL_2_PENDING_0_MAP0_FIELD                        _MK_FIELD_CONST(0xffff, HSP_DBELL_2_PENDING_0_MAP0_SHIFT)
#define HSP_DBELL_2_PENDING_0_MAP0_RANGE                        15:0
#define HSP_DBELL_2_PENDING_0_MAP0_WOFFSET                      0x0
#define HSP_DBELL_2_PENDING_0_MAP0_DEFAULT                      _MK_MASK_CONST(0x0)
#define HSP_DBELL_2_PENDING_0_MAP0_DEFAULT_MASK                 _MK_MASK_CONST(0xffff)
#define HSP_DBELL_2_PENDING_0_MAP0_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define HSP_DBELL_2_PENDING_0_MAP0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define HSP_DBELL_2_PENDING_0_MAP0_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define HSP_DBELL_2_PENDING_0_MAP0_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)


// Register HSP_DBELL_3_TRIGGER_0
#define HSP_DBELL_3_TRIGGER_0                   _MK_ADDR_CONST(0x300)
#define HSP_DBELL_3_TRIGGER_0_SECURE                    0x0
#define HSP_DBELL_3_TRIGGER_0_DUAL                      0x0
#define HSP_DBELL_3_TRIGGER_0_SCR                       0
#define HSP_DBELL_3_TRIGGER_0_WORD_COUNT                        0x1
#define HSP_DBELL_3_TRIGGER_0_RESET_VAL                         _MK_MASK_CONST(0x0)
#define HSP_DBELL_3_TRIGGER_0_RESET_MASK                        _MK_MASK_CONST(0xffffffff)
#define HSP_DBELL_3_TRIGGER_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define HSP_DBELL_3_TRIGGER_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define HSP_DBELL_3_TRIGGER_0_READ_MASK                         _MK_MASK_CONST(0xffffffff)
#define HSP_DBELL_3_TRIGGER_0_WRITE_MASK                        _MK_MASK_CONST(0xffffffff)
#define HSP_DBELL_3_TRIGGER_0_DUMMY_SHIFT                       _MK_SHIFT_CONST(0)
#define HSP_DBELL_3_TRIGGER_0_DUMMY_FIELD                       _MK_FIELD_CONST(0xffffffff, HSP_DBELL_3_TRIGGER_0_DUMMY_SHIFT)
#define HSP_DBELL_3_TRIGGER_0_DUMMY_RANGE                       31:0
#define HSP_DBELL_3_TRIGGER_0_DUMMY_WOFFSET                     0x0
#define HSP_DBELL_3_TRIGGER_0_DUMMY_DEFAULT                     _MK_MASK_CONST(0x0)
#define HSP_DBELL_3_TRIGGER_0_DUMMY_DEFAULT_MASK                        _MK_MASK_CONST(0xffffffff)
#define HSP_DBELL_3_TRIGGER_0_DUMMY_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define HSP_DBELL_3_TRIGGER_0_DUMMY_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define HSP_DBELL_3_TRIGGER_0_DUMMY_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define HSP_DBELL_3_TRIGGER_0_DUMMY_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)


// Register HSP_DBELL_3_ENABLE_0
#define HSP_DBELL_3_ENABLE_0                    _MK_ADDR_CONST(0x304)
#define HSP_DBELL_3_ENABLE_0_SECURE                     0x0
#define HSP_DBELL_3_ENABLE_0_DUAL                       0x0
#define HSP_DBELL_3_ENABLE_0_SCR                        DB_3_REG_0
#define HSP_DBELL_3_ENABLE_0_WORD_COUNT                         0x1
#define HSP_DBELL_3_ENABLE_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define HSP_DBELL_3_ENABLE_0_RESET_MASK                         _MK_MASK_CONST(0xffffffff)
#define HSP_DBELL_3_ENABLE_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define HSP_DBELL_3_ENABLE_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define HSP_DBELL_3_ENABLE_0_READ_MASK                  _MK_MASK_CONST(0xffffffff)
#define HSP_DBELL_3_ENABLE_0_WRITE_MASK                         _MK_MASK_CONST(0xffffffff)
#define HSP_DBELL_3_ENABLE_0_MAP1_SHIFT                 _MK_SHIFT_CONST(16)
#define HSP_DBELL_3_ENABLE_0_MAP1_FIELD                 _MK_FIELD_CONST(0xffff, HSP_DBELL_3_ENABLE_0_MAP1_SHIFT)
#define HSP_DBELL_3_ENABLE_0_MAP1_RANGE                 31:16
#define HSP_DBELL_3_ENABLE_0_MAP1_WOFFSET                       0x0
#define HSP_DBELL_3_ENABLE_0_MAP1_DEFAULT                       _MK_MASK_CONST(0x0)
#define HSP_DBELL_3_ENABLE_0_MAP1_DEFAULT_MASK                  _MK_MASK_CONST(0xffff)
#define HSP_DBELL_3_ENABLE_0_MAP1_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define HSP_DBELL_3_ENABLE_0_MAP1_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define HSP_DBELL_3_ENABLE_0_MAP1_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define HSP_DBELL_3_ENABLE_0_MAP1_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)

#define HSP_DBELL_3_ENABLE_0_MAP0_SHIFT                 _MK_SHIFT_CONST(0)
#define HSP_DBELL_3_ENABLE_0_MAP0_FIELD                 _MK_FIELD_CONST(0xffff, HSP_DBELL_3_ENABLE_0_MAP0_SHIFT)
#define HSP_DBELL_3_ENABLE_0_MAP0_RANGE                 15:0
#define HSP_DBELL_3_ENABLE_0_MAP0_WOFFSET                       0x0
#define HSP_DBELL_3_ENABLE_0_MAP0_DEFAULT                       _MK_MASK_CONST(0x0)
#define HSP_DBELL_3_ENABLE_0_MAP0_DEFAULT_MASK                  _MK_MASK_CONST(0xffff)
#define HSP_DBELL_3_ENABLE_0_MAP0_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define HSP_DBELL_3_ENABLE_0_MAP0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define HSP_DBELL_3_ENABLE_0_MAP0_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define HSP_DBELL_3_ENABLE_0_MAP0_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)


// Register HSP_DBELL_3_RAW_0
#define HSP_DBELL_3_RAW_0                       _MK_ADDR_CONST(0x308)
#define HSP_DBELL_3_RAW_0_SECURE                        0x0
#define HSP_DBELL_3_RAW_0_DUAL                  0x0
#define HSP_DBELL_3_RAW_0_SCR                   DB_3_REG_0
#define HSP_DBELL_3_RAW_0_WORD_COUNT                    0x1
#define HSP_DBELL_3_RAW_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define HSP_DBELL_3_RAW_0_RESET_MASK                    _MK_MASK_CONST(0xffffffff)
#define HSP_DBELL_3_RAW_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define HSP_DBELL_3_RAW_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define HSP_DBELL_3_RAW_0_READ_MASK                     _MK_MASK_CONST(0xffffffff)
#define HSP_DBELL_3_RAW_0_WRITE_MASK                    _MK_MASK_CONST(0xffffffff)
#define HSP_DBELL_3_RAW_0_MAP1_SHIFT                    _MK_SHIFT_CONST(16)
#define HSP_DBELL_3_RAW_0_MAP1_FIELD                    _MK_FIELD_CONST(0xffff, HSP_DBELL_3_RAW_0_MAP1_SHIFT)
#define HSP_DBELL_3_RAW_0_MAP1_RANGE                    31:16
#define HSP_DBELL_3_RAW_0_MAP1_WOFFSET                  0x0
#define HSP_DBELL_3_RAW_0_MAP1_DEFAULT                  _MK_MASK_CONST(0x0)
#define HSP_DBELL_3_RAW_0_MAP1_DEFAULT_MASK                     _MK_MASK_CONST(0xffff)
#define HSP_DBELL_3_RAW_0_MAP1_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define HSP_DBELL_3_RAW_0_MAP1_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define HSP_DBELL_3_RAW_0_MAP1_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define HSP_DBELL_3_RAW_0_MAP1_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)

#define HSP_DBELL_3_RAW_0_MAP0_SHIFT                    _MK_SHIFT_CONST(0)
#define HSP_DBELL_3_RAW_0_MAP0_FIELD                    _MK_FIELD_CONST(0xffff, HSP_DBELL_3_RAW_0_MAP0_SHIFT)
#define HSP_DBELL_3_RAW_0_MAP0_RANGE                    15:0
#define HSP_DBELL_3_RAW_0_MAP0_WOFFSET                  0x0
#define HSP_DBELL_3_RAW_0_MAP0_DEFAULT                  _MK_MASK_CONST(0x0)
#define HSP_DBELL_3_RAW_0_MAP0_DEFAULT_MASK                     _MK_MASK_CONST(0xffff)
#define HSP_DBELL_3_RAW_0_MAP0_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define HSP_DBELL_3_RAW_0_MAP0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define HSP_DBELL_3_RAW_0_MAP0_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define HSP_DBELL_3_RAW_0_MAP0_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)


// Register HSP_DBELL_3_PENDING_0
#define HSP_DBELL_3_PENDING_0                   _MK_ADDR_CONST(0x30c)
#define HSP_DBELL_3_PENDING_0_SECURE                    0x0
#define HSP_DBELL_3_PENDING_0_DUAL                      0x0
#define HSP_DBELL_3_PENDING_0_SCR                       DB_3_REG_0
#define HSP_DBELL_3_PENDING_0_WORD_COUNT                        0x1
#define HSP_DBELL_3_PENDING_0_RESET_VAL                         _MK_MASK_CONST(0x0)
#define HSP_DBELL_3_PENDING_0_RESET_MASK                        _MK_MASK_CONST(0xffffffff)
#define HSP_DBELL_3_PENDING_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define HSP_DBELL_3_PENDING_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define HSP_DBELL_3_PENDING_0_READ_MASK                         _MK_MASK_CONST(0xffffffff)
#define HSP_DBELL_3_PENDING_0_WRITE_MASK                        _MK_MASK_CONST(0xffffffff)
#define HSP_DBELL_3_PENDING_0_MAP1_SHIFT                        _MK_SHIFT_CONST(16)
#define HSP_DBELL_3_PENDING_0_MAP1_FIELD                        _MK_FIELD_CONST(0xffff, HSP_DBELL_3_PENDING_0_MAP1_SHIFT)
#define HSP_DBELL_3_PENDING_0_MAP1_RANGE                        31:16
#define HSP_DBELL_3_PENDING_0_MAP1_WOFFSET                      0x0
#define HSP_DBELL_3_PENDING_0_MAP1_DEFAULT                      _MK_MASK_CONST(0x0)
#define HSP_DBELL_3_PENDING_0_MAP1_DEFAULT_MASK                 _MK_MASK_CONST(0xffff)
#define HSP_DBELL_3_PENDING_0_MAP1_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define HSP_DBELL_3_PENDING_0_MAP1_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define HSP_DBELL_3_PENDING_0_MAP1_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define HSP_DBELL_3_PENDING_0_MAP1_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define HSP_DBELL_3_PENDING_0_MAP0_SHIFT                        _MK_SHIFT_CONST(0)
#define HSP_DBELL_3_PENDING_0_MAP0_FIELD                        _MK_FIELD_CONST(0xffff, HSP_DBELL_3_PENDING_0_MAP0_SHIFT)
#define HSP_DBELL_3_PENDING_0_MAP0_RANGE                        15:0
#define HSP_DBELL_3_PENDING_0_MAP0_WOFFSET                      0x0
#define HSP_DBELL_3_PENDING_0_MAP0_DEFAULT                      _MK_MASK_CONST(0x0)
#define HSP_DBELL_3_PENDING_0_MAP0_DEFAULT_MASK                 _MK_MASK_CONST(0xffff)
#define HSP_DBELL_3_PENDING_0_MAP0_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define HSP_DBELL_3_PENDING_0_MAP0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define HSP_DBELL_3_PENDING_0_MAP0_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define HSP_DBELL_3_PENDING_0_MAP0_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)


// Register HSP_DBELL_4_TRIGGER_0
#define HSP_DBELL_4_TRIGGER_0                   _MK_ADDR_CONST(0x400)
#define HSP_DBELL_4_TRIGGER_0_SECURE                    0x0
#define HSP_DBELL_4_TRIGGER_0_DUAL                      0x0
#define HSP_DBELL_4_TRIGGER_0_SCR                       0
#define HSP_DBELL_4_TRIGGER_0_WORD_COUNT                        0x1
#define HSP_DBELL_4_TRIGGER_0_RESET_VAL                         _MK_MASK_CONST(0x0)
#define HSP_DBELL_4_TRIGGER_0_RESET_MASK                        _MK_MASK_CONST(0xffffffff)
#define HSP_DBELL_4_TRIGGER_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define HSP_DBELL_4_TRIGGER_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define HSP_DBELL_4_TRIGGER_0_READ_MASK                         _MK_MASK_CONST(0xffffffff)
#define HSP_DBELL_4_TRIGGER_0_WRITE_MASK                        _MK_MASK_CONST(0xffffffff)
#define HSP_DBELL_4_TRIGGER_0_DUMMY_SHIFT                       _MK_SHIFT_CONST(0)
#define HSP_DBELL_4_TRIGGER_0_DUMMY_FIELD                       _MK_FIELD_CONST(0xffffffff, HSP_DBELL_4_TRIGGER_0_DUMMY_SHIFT)
#define HSP_DBELL_4_TRIGGER_0_DUMMY_RANGE                       31:0
#define HSP_DBELL_4_TRIGGER_0_DUMMY_WOFFSET                     0x0
#define HSP_DBELL_4_TRIGGER_0_DUMMY_DEFAULT                     _MK_MASK_CONST(0x0)
#define HSP_DBELL_4_TRIGGER_0_DUMMY_DEFAULT_MASK                        _MK_MASK_CONST(0xffffffff)
#define HSP_DBELL_4_TRIGGER_0_DUMMY_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define HSP_DBELL_4_TRIGGER_0_DUMMY_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define HSP_DBELL_4_TRIGGER_0_DUMMY_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define HSP_DBELL_4_TRIGGER_0_DUMMY_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)


// Register HSP_DBELL_4_ENABLE_0
#define HSP_DBELL_4_ENABLE_0                    _MK_ADDR_CONST(0x404)
#define HSP_DBELL_4_ENABLE_0_SECURE                     0x0
#define HSP_DBELL_4_ENABLE_0_DUAL                       0x0
#define HSP_DBELL_4_ENABLE_0_SCR                        DB_4_REG_0
#define HSP_DBELL_4_ENABLE_0_WORD_COUNT                         0x1
#define HSP_DBELL_4_ENABLE_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define HSP_DBELL_4_ENABLE_0_RESET_MASK                         _MK_MASK_CONST(0xffffffff)
#define HSP_DBELL_4_ENABLE_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define HSP_DBELL_4_ENABLE_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define HSP_DBELL_4_ENABLE_0_READ_MASK                  _MK_MASK_CONST(0xffffffff)
#define HSP_DBELL_4_ENABLE_0_WRITE_MASK                         _MK_MASK_CONST(0xffffffff)
#define HSP_DBELL_4_ENABLE_0_MAP1_SHIFT                 _MK_SHIFT_CONST(16)
#define HSP_DBELL_4_ENABLE_0_MAP1_FIELD                 _MK_FIELD_CONST(0xffff, HSP_DBELL_4_ENABLE_0_MAP1_SHIFT)
#define HSP_DBELL_4_ENABLE_0_MAP1_RANGE                 31:16
#define HSP_DBELL_4_ENABLE_0_MAP1_WOFFSET                       0x0
#define HSP_DBELL_4_ENABLE_0_MAP1_DEFAULT                       _MK_MASK_CONST(0x0)
#define HSP_DBELL_4_ENABLE_0_MAP1_DEFAULT_MASK                  _MK_MASK_CONST(0xffff)
#define HSP_DBELL_4_ENABLE_0_MAP1_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define HSP_DBELL_4_ENABLE_0_MAP1_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define HSP_DBELL_4_ENABLE_0_MAP1_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define HSP_DBELL_4_ENABLE_0_MAP1_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)

#define HSP_DBELL_4_ENABLE_0_MAP0_SHIFT                 _MK_SHIFT_CONST(0)
#define HSP_DBELL_4_ENABLE_0_MAP0_FIELD                 _MK_FIELD_CONST(0xffff, HSP_DBELL_4_ENABLE_0_MAP0_SHIFT)
#define HSP_DBELL_4_ENABLE_0_MAP0_RANGE                 15:0
#define HSP_DBELL_4_ENABLE_0_MAP0_WOFFSET                       0x0
#define HSP_DBELL_4_ENABLE_0_MAP0_DEFAULT                       _MK_MASK_CONST(0x0)
#define HSP_DBELL_4_ENABLE_0_MAP0_DEFAULT_MASK                  _MK_MASK_CONST(0xffff)
#define HSP_DBELL_4_ENABLE_0_MAP0_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define HSP_DBELL_4_ENABLE_0_MAP0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define HSP_DBELL_4_ENABLE_0_MAP0_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define HSP_DBELL_4_ENABLE_0_MAP0_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)


// Register HSP_DBELL_4_RAW_0
#define HSP_DBELL_4_RAW_0                       _MK_ADDR_CONST(0x408)
#define HSP_DBELL_4_RAW_0_SECURE                        0x0
#define HSP_DBELL_4_RAW_0_DUAL                  0x0
#define HSP_DBELL_4_RAW_0_SCR                   DB_4_REG_0
#define HSP_DBELL_4_RAW_0_WORD_COUNT                    0x1
#define HSP_DBELL_4_RAW_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define HSP_DBELL_4_RAW_0_RESET_MASK                    _MK_MASK_CONST(0xffffffff)
#define HSP_DBELL_4_RAW_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define HSP_DBELL_4_RAW_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define HSP_DBELL_4_RAW_0_READ_MASK                     _MK_MASK_CONST(0xffffffff)
#define HSP_DBELL_4_RAW_0_WRITE_MASK                    _MK_MASK_CONST(0xffffffff)
#define HSP_DBELL_4_RAW_0_MAP1_SHIFT                    _MK_SHIFT_CONST(16)
#define HSP_DBELL_4_RAW_0_MAP1_FIELD                    _MK_FIELD_CONST(0xffff, HSP_DBELL_4_RAW_0_MAP1_SHIFT)
#define HSP_DBELL_4_RAW_0_MAP1_RANGE                    31:16
#define HSP_DBELL_4_RAW_0_MAP1_WOFFSET                  0x0
#define HSP_DBELL_4_RAW_0_MAP1_DEFAULT                  _MK_MASK_CONST(0x0)
#define HSP_DBELL_4_RAW_0_MAP1_DEFAULT_MASK                     _MK_MASK_CONST(0xffff)
#define HSP_DBELL_4_RAW_0_MAP1_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define HSP_DBELL_4_RAW_0_MAP1_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define HSP_DBELL_4_RAW_0_MAP1_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define HSP_DBELL_4_RAW_0_MAP1_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)

#define HSP_DBELL_4_RAW_0_MAP0_SHIFT                    _MK_SHIFT_CONST(0)
#define HSP_DBELL_4_RAW_0_MAP0_FIELD                    _MK_FIELD_CONST(0xffff, HSP_DBELL_4_RAW_0_MAP0_SHIFT)
#define HSP_DBELL_4_RAW_0_MAP0_RANGE                    15:0
#define HSP_DBELL_4_RAW_0_MAP0_WOFFSET                  0x0
#define HSP_DBELL_4_RAW_0_MAP0_DEFAULT                  _MK_MASK_CONST(0x0)
#define HSP_DBELL_4_RAW_0_MAP0_DEFAULT_MASK                     _MK_MASK_CONST(0xffff)
#define HSP_DBELL_4_RAW_0_MAP0_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define HSP_DBELL_4_RAW_0_MAP0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define HSP_DBELL_4_RAW_0_MAP0_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define HSP_DBELL_4_RAW_0_MAP0_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)


// Register HSP_DBELL_4_PENDING_0
#define HSP_DBELL_4_PENDING_0                   _MK_ADDR_CONST(0x40c)
#define HSP_DBELL_4_PENDING_0_SECURE                    0x0
#define HSP_DBELL_4_PENDING_0_DUAL                      0x0
#define HSP_DBELL_4_PENDING_0_SCR                       DB_4_REG_0
#define HSP_DBELL_4_PENDING_0_WORD_COUNT                        0x1
#define HSP_DBELL_4_PENDING_0_RESET_VAL                         _MK_MASK_CONST(0x0)
#define HSP_DBELL_4_PENDING_0_RESET_MASK                        _MK_MASK_CONST(0xffffffff)
#define HSP_DBELL_4_PENDING_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define HSP_DBELL_4_PENDING_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define HSP_DBELL_4_PENDING_0_READ_MASK                         _MK_MASK_CONST(0xffffffff)
#define HSP_DBELL_4_PENDING_0_WRITE_MASK                        _MK_MASK_CONST(0xffffffff)
#define HSP_DBELL_4_PENDING_0_MAP1_SHIFT                        _MK_SHIFT_CONST(16)
#define HSP_DBELL_4_PENDING_0_MAP1_FIELD                        _MK_FIELD_CONST(0xffff, HSP_DBELL_4_PENDING_0_MAP1_SHIFT)
#define HSP_DBELL_4_PENDING_0_MAP1_RANGE                        31:16
#define HSP_DBELL_4_PENDING_0_MAP1_WOFFSET                      0x0
#define HSP_DBELL_4_PENDING_0_MAP1_DEFAULT                      _MK_MASK_CONST(0x0)
#define HSP_DBELL_4_PENDING_0_MAP1_DEFAULT_MASK                 _MK_MASK_CONST(0xffff)
#define HSP_DBELL_4_PENDING_0_MAP1_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define HSP_DBELL_4_PENDING_0_MAP1_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define HSP_DBELL_4_PENDING_0_MAP1_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define HSP_DBELL_4_PENDING_0_MAP1_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define HSP_DBELL_4_PENDING_0_MAP0_SHIFT                        _MK_SHIFT_CONST(0)
#define HSP_DBELL_4_PENDING_0_MAP0_FIELD                        _MK_FIELD_CONST(0xffff, HSP_DBELL_4_PENDING_0_MAP0_SHIFT)
#define HSP_DBELL_4_PENDING_0_MAP0_RANGE                        15:0
#define HSP_DBELL_4_PENDING_0_MAP0_WOFFSET                      0x0
#define HSP_DBELL_4_PENDING_0_MAP0_DEFAULT                      _MK_MASK_CONST(0x0)
#define HSP_DBELL_4_PENDING_0_MAP0_DEFAULT_MASK                 _MK_MASK_CONST(0xffff)
#define HSP_DBELL_4_PENDING_0_MAP0_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define HSP_DBELL_4_PENDING_0_MAP0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define HSP_DBELL_4_PENDING_0_MAP0_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define HSP_DBELL_4_PENDING_0_MAP0_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)


// Register HSP_DBELL_5_TRIGGER_0
#define HSP_DBELL_5_TRIGGER_0                   _MK_ADDR_CONST(0x500)
#define HSP_DBELL_5_TRIGGER_0_SECURE                    0x0
#define HSP_DBELL_5_TRIGGER_0_DUAL                      0x0
#define HSP_DBELL_5_TRIGGER_0_SCR                       0
#define HSP_DBELL_5_TRIGGER_0_WORD_COUNT                        0x1
#define HSP_DBELL_5_TRIGGER_0_RESET_VAL                         _MK_MASK_CONST(0x0)
#define HSP_DBELL_5_TRIGGER_0_RESET_MASK                        _MK_MASK_CONST(0xffffffff)
#define HSP_DBELL_5_TRIGGER_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define HSP_DBELL_5_TRIGGER_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define HSP_DBELL_5_TRIGGER_0_READ_MASK                         _MK_MASK_CONST(0xffffffff)
#define HSP_DBELL_5_TRIGGER_0_WRITE_MASK                        _MK_MASK_CONST(0xffffffff)
#define HSP_DBELL_5_TRIGGER_0_DUMMY_SHIFT                       _MK_SHIFT_CONST(0)
#define HSP_DBELL_5_TRIGGER_0_DUMMY_FIELD                       _MK_FIELD_CONST(0xffffffff, HSP_DBELL_5_TRIGGER_0_DUMMY_SHIFT)
#define HSP_DBELL_5_TRIGGER_0_DUMMY_RANGE                       31:0
#define HSP_DBELL_5_TRIGGER_0_DUMMY_WOFFSET                     0x0
#define HSP_DBELL_5_TRIGGER_0_DUMMY_DEFAULT                     _MK_MASK_CONST(0x0)
#define HSP_DBELL_5_TRIGGER_0_DUMMY_DEFAULT_MASK                        _MK_MASK_CONST(0xffffffff)
#define HSP_DBELL_5_TRIGGER_0_DUMMY_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define HSP_DBELL_5_TRIGGER_0_DUMMY_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define HSP_DBELL_5_TRIGGER_0_DUMMY_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define HSP_DBELL_5_TRIGGER_0_DUMMY_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)


// Register HSP_DBELL_5_ENABLE_0
#define HSP_DBELL_5_ENABLE_0                    _MK_ADDR_CONST(0x504)
#define HSP_DBELL_5_ENABLE_0_SECURE                     0x0
#define HSP_DBELL_5_ENABLE_0_DUAL                       0x0
#define HSP_DBELL_5_ENABLE_0_SCR                        DB_5_REG_0
#define HSP_DBELL_5_ENABLE_0_WORD_COUNT                         0x1
#define HSP_DBELL_5_ENABLE_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define HSP_DBELL_5_ENABLE_0_RESET_MASK                         _MK_MASK_CONST(0xffffffff)
#define HSP_DBELL_5_ENABLE_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define HSP_DBELL_5_ENABLE_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define HSP_DBELL_5_ENABLE_0_READ_MASK                  _MK_MASK_CONST(0xffffffff)
#define HSP_DBELL_5_ENABLE_0_WRITE_MASK                         _MK_MASK_CONST(0xffffffff)
#define HSP_DBELL_5_ENABLE_0_MAP1_SHIFT                 _MK_SHIFT_CONST(16)
#define HSP_DBELL_5_ENABLE_0_MAP1_FIELD                 _MK_FIELD_CONST(0xffff, HSP_DBELL_5_ENABLE_0_MAP1_SHIFT)
#define HSP_DBELL_5_ENABLE_0_MAP1_RANGE                 31:16
#define HSP_DBELL_5_ENABLE_0_MAP1_WOFFSET                       0x0
#define HSP_DBELL_5_ENABLE_0_MAP1_DEFAULT                       _MK_MASK_CONST(0x0)
#define HSP_DBELL_5_ENABLE_0_MAP1_DEFAULT_MASK                  _MK_MASK_CONST(0xffff)
#define HSP_DBELL_5_ENABLE_0_MAP1_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define HSP_DBELL_5_ENABLE_0_MAP1_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define HSP_DBELL_5_ENABLE_0_MAP1_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define HSP_DBELL_5_ENABLE_0_MAP1_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)

#define HSP_DBELL_5_ENABLE_0_MAP0_SHIFT                 _MK_SHIFT_CONST(0)
#define HSP_DBELL_5_ENABLE_0_MAP0_FIELD                 _MK_FIELD_CONST(0xffff, HSP_DBELL_5_ENABLE_0_MAP0_SHIFT)
#define HSP_DBELL_5_ENABLE_0_MAP0_RANGE                 15:0
#define HSP_DBELL_5_ENABLE_0_MAP0_WOFFSET                       0x0
#define HSP_DBELL_5_ENABLE_0_MAP0_DEFAULT                       _MK_MASK_CONST(0x0)
#define HSP_DBELL_5_ENABLE_0_MAP0_DEFAULT_MASK                  _MK_MASK_CONST(0xffff)
#define HSP_DBELL_5_ENABLE_0_MAP0_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define HSP_DBELL_5_ENABLE_0_MAP0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define HSP_DBELL_5_ENABLE_0_MAP0_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define HSP_DBELL_5_ENABLE_0_MAP0_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)


// Register HSP_DBELL_5_RAW_0
#define HSP_DBELL_5_RAW_0                       _MK_ADDR_CONST(0x508)
#define HSP_DBELL_5_RAW_0_SECURE                        0x0
#define HSP_DBELL_5_RAW_0_DUAL                  0x0
#define HSP_DBELL_5_RAW_0_SCR                   DB_5_REG_0
#define HSP_DBELL_5_RAW_0_WORD_COUNT                    0x1
#define HSP_DBELL_5_RAW_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define HSP_DBELL_5_RAW_0_RESET_MASK                    _MK_MASK_CONST(0xffffffff)
#define HSP_DBELL_5_RAW_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define HSP_DBELL_5_RAW_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define HSP_DBELL_5_RAW_0_READ_MASK                     _MK_MASK_CONST(0xffffffff)
#define HSP_DBELL_5_RAW_0_WRITE_MASK                    _MK_MASK_CONST(0xffffffff)
#define HSP_DBELL_5_RAW_0_MAP1_SHIFT                    _MK_SHIFT_CONST(16)
#define HSP_DBELL_5_RAW_0_MAP1_FIELD                    _MK_FIELD_CONST(0xffff, HSP_DBELL_5_RAW_0_MAP1_SHIFT)
#define HSP_DBELL_5_RAW_0_MAP1_RANGE                    31:16
#define HSP_DBELL_5_RAW_0_MAP1_WOFFSET                  0x0
#define HSP_DBELL_5_RAW_0_MAP1_DEFAULT                  _MK_MASK_CONST(0x0)
#define HSP_DBELL_5_RAW_0_MAP1_DEFAULT_MASK                     _MK_MASK_CONST(0xffff)
#define HSP_DBELL_5_RAW_0_MAP1_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define HSP_DBELL_5_RAW_0_MAP1_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define HSP_DBELL_5_RAW_0_MAP1_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define HSP_DBELL_5_RAW_0_MAP1_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)

#define HSP_DBELL_5_RAW_0_MAP0_SHIFT                    _MK_SHIFT_CONST(0)
#define HSP_DBELL_5_RAW_0_MAP0_FIELD                    _MK_FIELD_CONST(0xffff, HSP_DBELL_5_RAW_0_MAP0_SHIFT)
#define HSP_DBELL_5_RAW_0_MAP0_RANGE                    15:0
#define HSP_DBELL_5_RAW_0_MAP0_WOFFSET                  0x0
#define HSP_DBELL_5_RAW_0_MAP0_DEFAULT                  _MK_MASK_CONST(0x0)
#define HSP_DBELL_5_RAW_0_MAP0_DEFAULT_MASK                     _MK_MASK_CONST(0xffff)
#define HSP_DBELL_5_RAW_0_MAP0_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define HSP_DBELL_5_RAW_0_MAP0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define HSP_DBELL_5_RAW_0_MAP0_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define HSP_DBELL_5_RAW_0_MAP0_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)


// Register HSP_DBELL_5_PENDING_0
#define HSP_DBELL_5_PENDING_0                   _MK_ADDR_CONST(0x50c)
#define HSP_DBELL_5_PENDING_0_SECURE                    0x0
#define HSP_DBELL_5_PENDING_0_DUAL                      0x0
#define HSP_DBELL_5_PENDING_0_SCR                       DB_5_REG_0
#define HSP_DBELL_5_PENDING_0_WORD_COUNT                        0x1
#define HSP_DBELL_5_PENDING_0_RESET_VAL                         _MK_MASK_CONST(0x0)
#define HSP_DBELL_5_PENDING_0_RESET_MASK                        _MK_MASK_CONST(0xffffffff)
#define HSP_DBELL_5_PENDING_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define HSP_DBELL_5_PENDING_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define HSP_DBELL_5_PENDING_0_READ_MASK                         _MK_MASK_CONST(0xffffffff)
#define HSP_DBELL_5_PENDING_0_WRITE_MASK                        _MK_MASK_CONST(0xffffffff)
#define HSP_DBELL_5_PENDING_0_MAP1_SHIFT                        _MK_SHIFT_CONST(16)
#define HSP_DBELL_5_PENDING_0_MAP1_FIELD                        _MK_FIELD_CONST(0xffff, HSP_DBELL_5_PENDING_0_MAP1_SHIFT)
#define HSP_DBELL_5_PENDING_0_MAP1_RANGE                        31:16
#define HSP_DBELL_5_PENDING_0_MAP1_WOFFSET                      0x0
#define HSP_DBELL_5_PENDING_0_MAP1_DEFAULT                      _MK_MASK_CONST(0x0)
#define HSP_DBELL_5_PENDING_0_MAP1_DEFAULT_MASK                 _MK_MASK_CONST(0xffff)
#define HSP_DBELL_5_PENDING_0_MAP1_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define HSP_DBELL_5_PENDING_0_MAP1_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define HSP_DBELL_5_PENDING_0_MAP1_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define HSP_DBELL_5_PENDING_0_MAP1_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define HSP_DBELL_5_PENDING_0_MAP0_SHIFT                        _MK_SHIFT_CONST(0)
#define HSP_DBELL_5_PENDING_0_MAP0_FIELD                        _MK_FIELD_CONST(0xffff, HSP_DBELL_5_PENDING_0_MAP0_SHIFT)
#define HSP_DBELL_5_PENDING_0_MAP0_RANGE                        15:0
#define HSP_DBELL_5_PENDING_0_MAP0_WOFFSET                      0x0
#define HSP_DBELL_5_PENDING_0_MAP0_DEFAULT                      _MK_MASK_CONST(0x0)
#define HSP_DBELL_5_PENDING_0_MAP0_DEFAULT_MASK                 _MK_MASK_CONST(0xffff)
#define HSP_DBELL_5_PENDING_0_MAP0_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define HSP_DBELL_5_PENDING_0_MAP0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define HSP_DBELL_5_PENDING_0_MAP0_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define HSP_DBELL_5_PENDING_0_MAP0_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)


// Register HSP_DBELL_6_TRIGGER_0
#define HSP_DBELL_6_TRIGGER_0                   _MK_ADDR_CONST(0x600)
#define HSP_DBELL_6_TRIGGER_0_SECURE                    0x0
#define HSP_DBELL_6_TRIGGER_0_DUAL                      0x0
#define HSP_DBELL_6_TRIGGER_0_SCR                       0
#define HSP_DBELL_6_TRIGGER_0_WORD_COUNT                        0x1
#define HSP_DBELL_6_TRIGGER_0_RESET_VAL                         _MK_MASK_CONST(0x0)
#define HSP_DBELL_6_TRIGGER_0_RESET_MASK                        _MK_MASK_CONST(0xffffffff)
#define HSP_DBELL_6_TRIGGER_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define HSP_DBELL_6_TRIGGER_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define HSP_DBELL_6_TRIGGER_0_READ_MASK                         _MK_MASK_CONST(0xffffffff)
#define HSP_DBELL_6_TRIGGER_0_WRITE_MASK                        _MK_MASK_CONST(0xffffffff)
#define HSP_DBELL_6_TRIGGER_0_DUMMY_SHIFT                       _MK_SHIFT_CONST(0)
#define HSP_DBELL_6_TRIGGER_0_DUMMY_FIELD                       _MK_FIELD_CONST(0xffffffff, HSP_DBELL_6_TRIGGER_0_DUMMY_SHIFT)
#define HSP_DBELL_6_TRIGGER_0_DUMMY_RANGE                       31:0
#define HSP_DBELL_6_TRIGGER_0_DUMMY_WOFFSET                     0x0
#define HSP_DBELL_6_TRIGGER_0_DUMMY_DEFAULT                     _MK_MASK_CONST(0x0)
#define HSP_DBELL_6_TRIGGER_0_DUMMY_DEFAULT_MASK                        _MK_MASK_CONST(0xffffffff)
#define HSP_DBELL_6_TRIGGER_0_DUMMY_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define HSP_DBELL_6_TRIGGER_0_DUMMY_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define HSP_DBELL_6_TRIGGER_0_DUMMY_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define HSP_DBELL_6_TRIGGER_0_DUMMY_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)


// Register HSP_DBELL_6_ENABLE_0
#define HSP_DBELL_6_ENABLE_0                    _MK_ADDR_CONST(0x604)
#define HSP_DBELL_6_ENABLE_0_SECURE                     0x0
#define HSP_DBELL_6_ENABLE_0_DUAL                       0x0
#define HSP_DBELL_6_ENABLE_0_SCR                        DB_6_REG_0
#define HSP_DBELL_6_ENABLE_0_WORD_COUNT                         0x1
#define HSP_DBELL_6_ENABLE_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define HSP_DBELL_6_ENABLE_0_RESET_MASK                         _MK_MASK_CONST(0xffffffff)
#define HSP_DBELL_6_ENABLE_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define HSP_DBELL_6_ENABLE_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define HSP_DBELL_6_ENABLE_0_READ_MASK                  _MK_MASK_CONST(0xffffffff)
#define HSP_DBELL_6_ENABLE_0_WRITE_MASK                         _MK_MASK_CONST(0xffffffff)
#define HSP_DBELL_6_ENABLE_0_MAP1_SHIFT                 _MK_SHIFT_CONST(16)
#define HSP_DBELL_6_ENABLE_0_MAP1_FIELD                 _MK_FIELD_CONST(0xffff, HSP_DBELL_6_ENABLE_0_MAP1_SHIFT)
#define HSP_DBELL_6_ENABLE_0_MAP1_RANGE                 31:16
#define HSP_DBELL_6_ENABLE_0_MAP1_WOFFSET                       0x0
#define HSP_DBELL_6_ENABLE_0_MAP1_DEFAULT                       _MK_MASK_CONST(0x0)
#define HSP_DBELL_6_ENABLE_0_MAP1_DEFAULT_MASK                  _MK_MASK_CONST(0xffff)
#define HSP_DBELL_6_ENABLE_0_MAP1_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define HSP_DBELL_6_ENABLE_0_MAP1_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define HSP_DBELL_6_ENABLE_0_MAP1_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define HSP_DBELL_6_ENABLE_0_MAP1_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)

#define HSP_DBELL_6_ENABLE_0_MAP0_SHIFT                 _MK_SHIFT_CONST(0)
#define HSP_DBELL_6_ENABLE_0_MAP0_FIELD                 _MK_FIELD_CONST(0xffff, HSP_DBELL_6_ENABLE_0_MAP0_SHIFT)
#define HSP_DBELL_6_ENABLE_0_MAP0_RANGE                 15:0
#define HSP_DBELL_6_ENABLE_0_MAP0_WOFFSET                       0x0
#define HSP_DBELL_6_ENABLE_0_MAP0_DEFAULT                       _MK_MASK_CONST(0x0)
#define HSP_DBELL_6_ENABLE_0_MAP0_DEFAULT_MASK                  _MK_MASK_CONST(0xffff)
#define HSP_DBELL_6_ENABLE_0_MAP0_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define HSP_DBELL_6_ENABLE_0_MAP0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define HSP_DBELL_6_ENABLE_0_MAP0_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define HSP_DBELL_6_ENABLE_0_MAP0_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)


// Register HSP_DBELL_6_RAW_0
#define HSP_DBELL_6_RAW_0                       _MK_ADDR_CONST(0x608)
#define HSP_DBELL_6_RAW_0_SECURE                        0x0
#define HSP_DBELL_6_RAW_0_DUAL                  0x0
#define HSP_DBELL_6_RAW_0_SCR                   DB_6_REG_0
#define HSP_DBELL_6_RAW_0_WORD_COUNT                    0x1
#define HSP_DBELL_6_RAW_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define HSP_DBELL_6_RAW_0_RESET_MASK                    _MK_MASK_CONST(0xffffffff)
#define HSP_DBELL_6_RAW_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define HSP_DBELL_6_RAW_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define HSP_DBELL_6_RAW_0_READ_MASK                     _MK_MASK_CONST(0xffffffff)
#define HSP_DBELL_6_RAW_0_WRITE_MASK                    _MK_MASK_CONST(0xffffffff)
#define HSP_DBELL_6_RAW_0_MAP1_SHIFT                    _MK_SHIFT_CONST(16)
#define HSP_DBELL_6_RAW_0_MAP1_FIELD                    _MK_FIELD_CONST(0xffff, HSP_DBELL_6_RAW_0_MAP1_SHIFT)
#define HSP_DBELL_6_RAW_0_MAP1_RANGE                    31:16
#define HSP_DBELL_6_RAW_0_MAP1_WOFFSET                  0x0
#define HSP_DBELL_6_RAW_0_MAP1_DEFAULT                  _MK_MASK_CONST(0x0)
#define HSP_DBELL_6_RAW_0_MAP1_DEFAULT_MASK                     _MK_MASK_CONST(0xffff)
#define HSP_DBELL_6_RAW_0_MAP1_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define HSP_DBELL_6_RAW_0_MAP1_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define HSP_DBELL_6_RAW_0_MAP1_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define HSP_DBELL_6_RAW_0_MAP1_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)

#define HSP_DBELL_6_RAW_0_MAP0_SHIFT                    _MK_SHIFT_CONST(0)
#define HSP_DBELL_6_RAW_0_MAP0_FIELD                    _MK_FIELD_CONST(0xffff, HSP_DBELL_6_RAW_0_MAP0_SHIFT)
#define HSP_DBELL_6_RAW_0_MAP0_RANGE                    15:0
#define HSP_DBELL_6_RAW_0_MAP0_WOFFSET                  0x0
#define HSP_DBELL_6_RAW_0_MAP0_DEFAULT                  _MK_MASK_CONST(0x0)
#define HSP_DBELL_6_RAW_0_MAP0_DEFAULT_MASK                     _MK_MASK_CONST(0xffff)
#define HSP_DBELL_6_RAW_0_MAP0_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define HSP_DBELL_6_RAW_0_MAP0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define HSP_DBELL_6_RAW_0_MAP0_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define HSP_DBELL_6_RAW_0_MAP0_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)


// Register HSP_DBELL_6_PENDING_0
#define HSP_DBELL_6_PENDING_0                   _MK_ADDR_CONST(0x60c)
#define HSP_DBELL_6_PENDING_0_SECURE                    0x0
#define HSP_DBELL_6_PENDING_0_DUAL                      0x0
#define HSP_DBELL_6_PENDING_0_SCR                       DB_6_REG_0
#define HSP_DBELL_6_PENDING_0_WORD_COUNT                        0x1
#define HSP_DBELL_6_PENDING_0_RESET_VAL                         _MK_MASK_CONST(0x0)
#define HSP_DBELL_6_PENDING_0_RESET_MASK                        _MK_MASK_CONST(0xffffffff)
#define HSP_DBELL_6_PENDING_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define HSP_DBELL_6_PENDING_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define HSP_DBELL_6_PENDING_0_READ_MASK                         _MK_MASK_CONST(0xffffffff)
#define HSP_DBELL_6_PENDING_0_WRITE_MASK                        _MK_MASK_CONST(0xffffffff)
#define HSP_DBELL_6_PENDING_0_MAP1_SHIFT                        _MK_SHIFT_CONST(16)
#define HSP_DBELL_6_PENDING_0_MAP1_FIELD                        _MK_FIELD_CONST(0xffff, HSP_DBELL_6_PENDING_0_MAP1_SHIFT)
#define HSP_DBELL_6_PENDING_0_MAP1_RANGE                        31:16
#define HSP_DBELL_6_PENDING_0_MAP1_WOFFSET                      0x0
#define HSP_DBELL_6_PENDING_0_MAP1_DEFAULT                      _MK_MASK_CONST(0x0)
#define HSP_DBELL_6_PENDING_0_MAP1_DEFAULT_MASK                 _MK_MASK_CONST(0xffff)
#define HSP_DBELL_6_PENDING_0_MAP1_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define HSP_DBELL_6_PENDING_0_MAP1_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define HSP_DBELL_6_PENDING_0_MAP1_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define HSP_DBELL_6_PENDING_0_MAP1_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define HSP_DBELL_6_PENDING_0_MAP0_SHIFT                        _MK_SHIFT_CONST(0)
#define HSP_DBELL_6_PENDING_0_MAP0_FIELD                        _MK_FIELD_CONST(0xffff, HSP_DBELL_6_PENDING_0_MAP0_SHIFT)
#define HSP_DBELL_6_PENDING_0_MAP0_RANGE                        15:0
#define HSP_DBELL_6_PENDING_0_MAP0_WOFFSET                      0x0
#define HSP_DBELL_6_PENDING_0_MAP0_DEFAULT                      _MK_MASK_CONST(0x0)
#define HSP_DBELL_6_PENDING_0_MAP0_DEFAULT_MASK                 _MK_MASK_CONST(0xffff)
#define HSP_DBELL_6_PENDING_0_MAP0_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define HSP_DBELL_6_PENDING_0_MAP0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define HSP_DBELL_6_PENDING_0_MAP0_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define HSP_DBELL_6_PENDING_0_MAP0_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)


// Register HSP_DBELL_7_TRIGGER_0
#define HSP_DBELL_7_TRIGGER_0                   _MK_ADDR_CONST(0x700)
#define HSP_DBELL_7_TRIGGER_0_SECURE                    0x0
#define HSP_DBELL_7_TRIGGER_0_DUAL                      0x0
#define HSP_DBELL_7_TRIGGER_0_SCR                       0
#define HSP_DBELL_7_TRIGGER_0_WORD_COUNT                        0x1
#define HSP_DBELL_7_TRIGGER_0_RESET_VAL                         _MK_MASK_CONST(0x0)
#define HSP_DBELL_7_TRIGGER_0_RESET_MASK                        _MK_MASK_CONST(0xffffffff)
#define HSP_DBELL_7_TRIGGER_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define HSP_DBELL_7_TRIGGER_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define HSP_DBELL_7_TRIGGER_0_READ_MASK                         _MK_MASK_CONST(0xffffffff)
#define HSP_DBELL_7_TRIGGER_0_WRITE_MASK                        _MK_MASK_CONST(0xffffffff)
#define HSP_DBELL_7_TRIGGER_0_DUMMY_SHIFT                       _MK_SHIFT_CONST(0)
#define HSP_DBELL_7_TRIGGER_0_DUMMY_FIELD                       _MK_FIELD_CONST(0xffffffff, HSP_DBELL_7_TRIGGER_0_DUMMY_SHIFT)
#define HSP_DBELL_7_TRIGGER_0_DUMMY_RANGE                       31:0
#define HSP_DBELL_7_TRIGGER_0_DUMMY_WOFFSET                     0x0
#define HSP_DBELL_7_TRIGGER_0_DUMMY_DEFAULT                     _MK_MASK_CONST(0x0)
#define HSP_DBELL_7_TRIGGER_0_DUMMY_DEFAULT_MASK                        _MK_MASK_CONST(0xffffffff)
#define HSP_DBELL_7_TRIGGER_0_DUMMY_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define HSP_DBELL_7_TRIGGER_0_DUMMY_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define HSP_DBELL_7_TRIGGER_0_DUMMY_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define HSP_DBELL_7_TRIGGER_0_DUMMY_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)


// Register HSP_DBELL_7_ENABLE_0
#define HSP_DBELL_7_ENABLE_0                    _MK_ADDR_CONST(0x704)
#define HSP_DBELL_7_ENABLE_0_SECURE                     0x0
#define HSP_DBELL_7_ENABLE_0_DUAL                       0x0
#define HSP_DBELL_7_ENABLE_0_SCR                        DB_7_REG_0
#define HSP_DBELL_7_ENABLE_0_WORD_COUNT                         0x1
#define HSP_DBELL_7_ENABLE_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define HSP_DBELL_7_ENABLE_0_RESET_MASK                         _MK_MASK_CONST(0xffffffff)
#define HSP_DBELL_7_ENABLE_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define HSP_DBELL_7_ENABLE_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define HSP_DBELL_7_ENABLE_0_READ_MASK                  _MK_MASK_CONST(0xffffffff)
#define HSP_DBELL_7_ENABLE_0_WRITE_MASK                         _MK_MASK_CONST(0xffffffff)
#define HSP_DBELL_7_ENABLE_0_MAP1_SHIFT                 _MK_SHIFT_CONST(16)
#define HSP_DBELL_7_ENABLE_0_MAP1_FIELD                 _MK_FIELD_CONST(0xffff, HSP_DBELL_7_ENABLE_0_MAP1_SHIFT)
#define HSP_DBELL_7_ENABLE_0_MAP1_RANGE                 31:16
#define HSP_DBELL_7_ENABLE_0_MAP1_WOFFSET                       0x0
#define HSP_DBELL_7_ENABLE_0_MAP1_DEFAULT                       _MK_MASK_CONST(0x0)
#define HSP_DBELL_7_ENABLE_0_MAP1_DEFAULT_MASK                  _MK_MASK_CONST(0xffff)
#define HSP_DBELL_7_ENABLE_0_MAP1_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define HSP_DBELL_7_ENABLE_0_MAP1_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define HSP_DBELL_7_ENABLE_0_MAP1_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define HSP_DBELL_7_ENABLE_0_MAP1_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)

#define HSP_DBELL_7_ENABLE_0_MAP0_SHIFT                 _MK_SHIFT_CONST(0)
#define HSP_DBELL_7_ENABLE_0_MAP0_FIELD                 _MK_FIELD_CONST(0xffff, HSP_DBELL_7_ENABLE_0_MAP0_SHIFT)
#define HSP_DBELL_7_ENABLE_0_MAP0_RANGE                 15:0
#define HSP_DBELL_7_ENABLE_0_MAP0_WOFFSET                       0x0
#define HSP_DBELL_7_ENABLE_0_MAP0_DEFAULT                       _MK_MASK_CONST(0x0)
#define HSP_DBELL_7_ENABLE_0_MAP0_DEFAULT_MASK                  _MK_MASK_CONST(0xffff)
#define HSP_DBELL_7_ENABLE_0_MAP0_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define HSP_DBELL_7_ENABLE_0_MAP0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define HSP_DBELL_7_ENABLE_0_MAP0_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define HSP_DBELL_7_ENABLE_0_MAP0_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)


// Register HSP_DBELL_7_RAW_0
#define HSP_DBELL_7_RAW_0                       _MK_ADDR_CONST(0x708)
#define HSP_DBELL_7_RAW_0_SECURE                        0x0
#define HSP_DBELL_7_RAW_0_DUAL                  0x0
#define HSP_DBELL_7_RAW_0_SCR                   DB_7_REG_0
#define HSP_DBELL_7_RAW_0_WORD_COUNT                    0x1
#define HSP_DBELL_7_RAW_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define HSP_DBELL_7_RAW_0_RESET_MASK                    _MK_MASK_CONST(0xffffffff)
#define HSP_DBELL_7_RAW_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define HSP_DBELL_7_RAW_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define HSP_DBELL_7_RAW_0_READ_MASK                     _MK_MASK_CONST(0xffffffff)
#define HSP_DBELL_7_RAW_0_WRITE_MASK                    _MK_MASK_CONST(0xffffffff)
#define HSP_DBELL_7_RAW_0_MAP1_SHIFT                    _MK_SHIFT_CONST(16)
#define HSP_DBELL_7_RAW_0_MAP1_FIELD                    _MK_FIELD_CONST(0xffff, HSP_DBELL_7_RAW_0_MAP1_SHIFT)
#define HSP_DBELL_7_RAW_0_MAP1_RANGE                    31:16
#define HSP_DBELL_7_RAW_0_MAP1_WOFFSET                  0x0
#define HSP_DBELL_7_RAW_0_MAP1_DEFAULT                  _MK_MASK_CONST(0x0)
#define HSP_DBELL_7_RAW_0_MAP1_DEFAULT_MASK                     _MK_MASK_CONST(0xffff)
#define HSP_DBELL_7_RAW_0_MAP1_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define HSP_DBELL_7_RAW_0_MAP1_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define HSP_DBELL_7_RAW_0_MAP1_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define HSP_DBELL_7_RAW_0_MAP1_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)

#define HSP_DBELL_7_RAW_0_MAP0_SHIFT                    _MK_SHIFT_CONST(0)
#define HSP_DBELL_7_RAW_0_MAP0_FIELD                    _MK_FIELD_CONST(0xffff, HSP_DBELL_7_RAW_0_MAP0_SHIFT)
#define HSP_DBELL_7_RAW_0_MAP0_RANGE                    15:0
#define HSP_DBELL_7_RAW_0_MAP0_WOFFSET                  0x0
#define HSP_DBELL_7_RAW_0_MAP0_DEFAULT                  _MK_MASK_CONST(0x0)
#define HSP_DBELL_7_RAW_0_MAP0_DEFAULT_MASK                     _MK_MASK_CONST(0xffff)
#define HSP_DBELL_7_RAW_0_MAP0_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define HSP_DBELL_7_RAW_0_MAP0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define HSP_DBELL_7_RAW_0_MAP0_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define HSP_DBELL_7_RAW_0_MAP0_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)


// Register HSP_DBELL_7_PENDING_0
#define HSP_DBELL_7_PENDING_0                   _MK_ADDR_CONST(0x70c)
#define HSP_DBELL_7_PENDING_0_SECURE                    0x0
#define HSP_DBELL_7_PENDING_0_DUAL                      0x0
#define HSP_DBELL_7_PENDING_0_SCR                       DB_7_REG_0
#define HSP_DBELL_7_PENDING_0_WORD_COUNT                        0x1
#define HSP_DBELL_7_PENDING_0_RESET_VAL                         _MK_MASK_CONST(0x0)
#define HSP_DBELL_7_PENDING_0_RESET_MASK                        _MK_MASK_CONST(0xffffffff)
#define HSP_DBELL_7_PENDING_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define HSP_DBELL_7_PENDING_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define HSP_DBELL_7_PENDING_0_READ_MASK                         _MK_MASK_CONST(0xffffffff)
#define HSP_DBELL_7_PENDING_0_WRITE_MASK                        _MK_MASK_CONST(0xffffffff)
#define HSP_DBELL_7_PENDING_0_MAP1_SHIFT                        _MK_SHIFT_CONST(16)
#define HSP_DBELL_7_PENDING_0_MAP1_FIELD                        _MK_FIELD_CONST(0xffff, HSP_DBELL_7_PENDING_0_MAP1_SHIFT)
#define HSP_DBELL_7_PENDING_0_MAP1_RANGE                        31:16
#define HSP_DBELL_7_PENDING_0_MAP1_WOFFSET                      0x0
#define HSP_DBELL_7_PENDING_0_MAP1_DEFAULT                      _MK_MASK_CONST(0x0)
#define HSP_DBELL_7_PENDING_0_MAP1_DEFAULT_MASK                 _MK_MASK_CONST(0xffff)
#define HSP_DBELL_7_PENDING_0_MAP1_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define HSP_DBELL_7_PENDING_0_MAP1_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define HSP_DBELL_7_PENDING_0_MAP1_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define HSP_DBELL_7_PENDING_0_MAP1_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define HSP_DBELL_7_PENDING_0_MAP0_SHIFT                        _MK_SHIFT_CONST(0)
#define HSP_DBELL_7_PENDING_0_MAP0_FIELD                        _MK_FIELD_CONST(0xffff, HSP_DBELL_7_PENDING_0_MAP0_SHIFT)
#define HSP_DBELL_7_PENDING_0_MAP0_RANGE                        15:0
#define HSP_DBELL_7_PENDING_0_MAP0_WOFFSET                      0x0
#define HSP_DBELL_7_PENDING_0_MAP0_DEFAULT                      _MK_MASK_CONST(0x0)
#define HSP_DBELL_7_PENDING_0_MAP0_DEFAULT_MASK                 _MK_MASK_CONST(0xffff)
#define HSP_DBELL_7_PENDING_0_MAP0_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define HSP_DBELL_7_PENDING_0_MAP0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define HSP_DBELL_7_PENDING_0_MAP0_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define HSP_DBELL_7_PENDING_0_MAP0_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)


//
// REGISTER LIST
//
#define LIST_ARHSP_DBELL_REGS(_op_) \
_op_(HSP_DBELL_0_TRIGGER_0) \
_op_(HSP_DBELL_0_ENABLE_0) \
_op_(HSP_DBELL_0_RAW_0) \
_op_(HSP_DBELL_0_PENDING_0) \
_op_(HSP_DBELL_1_TRIGGER_0) \
_op_(HSP_DBELL_1_ENABLE_0) \
_op_(HSP_DBELL_1_RAW_0) \
_op_(HSP_DBELL_1_PENDING_0) \
_op_(HSP_DBELL_2_TRIGGER_0) \
_op_(HSP_DBELL_2_ENABLE_0) \
_op_(HSP_DBELL_2_RAW_0) \
_op_(HSP_DBELL_2_PENDING_0) \
_op_(HSP_DBELL_3_TRIGGER_0) \
_op_(HSP_DBELL_3_ENABLE_0) \
_op_(HSP_DBELL_3_RAW_0) \
_op_(HSP_DBELL_3_PENDING_0) \
_op_(HSP_DBELL_4_TRIGGER_0) \
_op_(HSP_DBELL_4_ENABLE_0) \
_op_(HSP_DBELL_4_RAW_0) \
_op_(HSP_DBELL_4_PENDING_0) \
_op_(HSP_DBELL_5_TRIGGER_0) \
_op_(HSP_DBELL_5_ENABLE_0) \
_op_(HSP_DBELL_5_RAW_0) \
_op_(HSP_DBELL_5_PENDING_0) \
_op_(HSP_DBELL_6_TRIGGER_0) \
_op_(HSP_DBELL_6_ENABLE_0) \
_op_(HSP_DBELL_6_RAW_0) \
_op_(HSP_DBELL_6_PENDING_0) \
_op_(HSP_DBELL_7_TRIGGER_0) \
_op_(HSP_DBELL_7_ENABLE_0) \
_op_(HSP_DBELL_7_RAW_0) \
_op_(HSP_DBELL_7_PENDING_0)


//
// ADDRESS SPACES
//

#define BASE_ADDRESS_HSP        0x00000000

//
// ARHSP_DBELL REGISTER BANKS
//

#define HSP0_FIRST_REG 0x0000 // HSP_DBELL_0_TRIGGER_0
#define HSP0_LAST_REG 0x000c // HSP_DBELL_0_PENDING_0
#define HSP1_FIRST_REG 0x0100 // HSP_DBELL_1_TRIGGER_0
#define HSP1_LAST_REG 0x010c // HSP_DBELL_1_PENDING_0
#define HSP2_FIRST_REG 0x0200 // HSP_DBELL_2_TRIGGER_0
#define HSP2_LAST_REG 0x020c // HSP_DBELL_2_PENDING_0
#define HSP3_FIRST_REG 0x0300 // HSP_DBELL_3_TRIGGER_0
#define HSP3_LAST_REG 0x030c // HSP_DBELL_3_PENDING_0
#define HSP4_FIRST_REG 0x0400 // HSP_DBELL_4_TRIGGER_0
#define HSP4_LAST_REG 0x040c // HSP_DBELL_4_PENDING_0
#define HSP5_FIRST_REG 0x0500 // HSP_DBELL_5_TRIGGER_0
#define HSP5_LAST_REG 0x050c // HSP_DBELL_5_PENDING_0
#define HSP6_FIRST_REG 0x0600 // HSP_DBELL_6_TRIGGER_0
#define HSP6_LAST_REG 0x060c // HSP_DBELL_6_PENDING_0
#define HSP7_FIRST_REG 0x0700 // HSP_DBELL_7_TRIGGER_0
#define HSP7_LAST_REG 0x070c // HSP_DBELL_7_PENDING_0

// To satisfy various compilers and platforms,
// we let users control the types and syntax of certain constants, using macros.
#ifndef _MK_SHIFT_CONST
  #define _MK_SHIFT_CONST(_constant_) _constant_
#endif
#ifndef _MK_MASK_CONST
  #define _MK_MASK_CONST(_constant_) _constant_
#endif
#ifndef _MK_ENUM_CONST
  #define _MK_ENUM_CONST(_constant_) (_constant_ ## UL)
#endif
#ifndef _MK_ADDR_CONST
  #define _MK_ADDR_CONST(_constant_) _constant_
#endif
#ifndef _MK_FIELD_CONST
  #define _MK_FIELD_CONST(_mask_, _shift_) (_MK_MASK_CONST(_mask_) << _MK_SHIFT_CONST(_shift_))
#endif

#endif // ifndef ___ARHSP_DBELL_H_INC_
